mirror of
https://github.com/ikawrakow/ik_llama.cpp.git
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6a56d5075d
* cuda: faster MMQ for iq2_ks, iq2_k, iq2_k_r4 * Lookup is still beter for MMQ if we get 4 values at once * Minor --------- Co-authored-by: Iwan Kawrakow <iwan.kawrakow@gmail.com>
245 lines
7.8 KiB
Plaintext
245 lines
7.8 KiB
Plaintext
//
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// Copyright (C) 2023-2024 The ggml authors
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// Copyright (C) 2024 Iwan Kawrakow
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// MIT license
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// SPDX-License-Identifier: MIT
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//
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#include "mmq.cuh"
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void ggml_cuda_op_mul_mat_q(
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ggml_backend_cuda_context & ctx,
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const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, const char * src0_dd_i, const float * src1_ddf_i,
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const char * src1_ddq_i, float * dst_dd_i, const int64_t row_low, const int64_t row_high, const int64_t src1_ncols,
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const int64_t src1_padded_row_size, cudaStream_t stream) {
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const int64_t ne00 = src0->ne[0];
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const int64_t nb01 = src0->nb[1];
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const int64_t ne10 = src1->ne[0];
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const int64_t ne11 = src1->ne[1];
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GGML_ASSERT(ne10 % QK8_1 == 0);
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const int64_t ne0 = dst->ne[0];
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const int64_t row_diff = row_high - row_low;
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int id = ggml_cuda_get_device();
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const int compute_capability = ggml_cuda_info().devices[id].cc;
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// the main device has a larger memory buffer to hold the results from all GPUs
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// nrows_dst == nrows of the matrix that the kernel writes into
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const int64_t nrows_dst = id == ctx.device ? ne0 : row_diff;
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const mmq_args args = {src0_dd_i, src1_ddq_i, dst_dd_i, ne00, row_diff, nb01, src1_padded_row_size, src1_ncols, ne11, nrows_dst};
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switch (src0->type) {
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case GGML_TYPE_Q4_0:
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mul_mat_q_case<GGML_TYPE_Q4_0>(ctx, args, stream);
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break;
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case GGML_TYPE_Q4_1:
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mul_mat_q_case<GGML_TYPE_Q4_1>(ctx, args, stream);
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break;
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case GGML_TYPE_Q5_0:
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mul_mat_q_case<GGML_TYPE_Q5_0>(ctx, args, stream);
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break;
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case GGML_TYPE_Q5_1:
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mul_mat_q_case<GGML_TYPE_Q5_1>(ctx, args, stream);
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break;
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case GGML_TYPE_Q6_0:
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mul_mat_q_case<GGML_TYPE_Q6_0>(ctx, args, stream);
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break;
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case GGML_TYPE_Q8_0:
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mul_mat_q_case<GGML_TYPE_Q8_0>(ctx, args, stream);
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break;
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case GGML_TYPE_Q2_K:
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mul_mat_q_case<GGML_TYPE_Q2_K>(ctx, args, stream);
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break;
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case GGML_TYPE_Q3_K:
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mul_mat_q_case<GGML_TYPE_Q3_K>(ctx, args, stream);
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break;
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case GGML_TYPE_Q4_K:
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mul_mat_q_case<GGML_TYPE_Q4_K>(ctx, args, stream);
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break;
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case GGML_TYPE_Q5_K:
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mul_mat_q_case<GGML_TYPE_Q5_K>(ctx, args, stream);
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break;
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case GGML_TYPE_Q6_K:
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mul_mat_q_case<GGML_TYPE_Q6_K>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_XXS:
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mul_mat_q_case<GGML_TYPE_IQ2_XXS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_XS:
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mul_mat_q_case<GGML_TYPE_IQ2_XS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_S:
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mul_mat_q_case<GGML_TYPE_IQ2_S>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ3_XXS:
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mul_mat_q_case<GGML_TYPE_IQ3_XXS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ3_S:
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mul_mat_q_case<GGML_TYPE_IQ3_S>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ1_S:
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mul_mat_q_case<GGML_TYPE_IQ1_S>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ1_S_R4:
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mul_mat_q_case<GGML_TYPE_IQ1_S_R4>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ4_XS:
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mul_mat_q_case<GGML_TYPE_IQ4_XS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ4_NL:
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mul_mat_q_case<GGML_TYPE_IQ4_NL>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ3_KS:
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mul_mat_q_case<GGML_TYPE_IQ3_KS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ4_KS:
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mul_mat_q_case<GGML_TYPE_IQ4_KS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ4_KS_R4:
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mul_mat_q_case<GGML_TYPE_IQ4_KS_R4>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ4_KT:
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mul_mat_q_case<GGML_TYPE_IQ4_KT>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_KT:
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mul_mat_q_case<GGML_TYPE_IQ2_KT>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ3_KT:
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mul_mat_q_case<GGML_TYPE_IQ3_KT>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ5_KS:
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mul_mat_q_case<GGML_TYPE_IQ5_KS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ5_KS_R4:
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mul_mat_q_case<GGML_TYPE_IQ5_KS_R4>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_KS:
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mul_mat_q_case<GGML_TYPE_IQ2_KS>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_K:
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mul_mat_q_case<GGML_TYPE_IQ2_K>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ3_K:
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mul_mat_q_case<GGML_TYPE_IQ3_K>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ4_K:
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mul_mat_q_case<GGML_TYPE_IQ4_K>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ5_K:
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mul_mat_q_case<GGML_TYPE_IQ5_K>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ6_K:
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mul_mat_q_case<GGML_TYPE_IQ6_K>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ2_K_R4:
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mul_mat_q_case<GGML_TYPE_IQ2_K_R4>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ3_K_R4:
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mul_mat_q_case<GGML_TYPE_IQ3_K_R4>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ4_K_R4:
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mul_mat_q_case<GGML_TYPE_IQ4_K_R4>(ctx, args, stream);
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break;
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case GGML_TYPE_IQ5_K_R4:
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mul_mat_q_case<GGML_TYPE_IQ5_K_R4>(ctx, args, stream);
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break;
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default:
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GGML_ABORT("fatal error");
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break;
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}
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GGML_UNUSED(src1);
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GGML_UNUSED(dst);
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GGML_UNUSED(src1_ddf_i);
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}
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bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11) {
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#ifdef GGML_CUDA_FORCE_CUBLAS
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return false;
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#endif // GGML_CUDA_FORCE_CUBLAS
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bool mmq_supported;
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switch (type) {
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case GGML_TYPE_Q2_K: mmq_supported = ne11 < 384; break;
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case GGML_TYPE_Q3_K:
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case GGML_TYPE_Q6_K:
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case GGML_TYPE_IQ2_XS:
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case GGML_TYPE_IQ2_S:
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mmq_supported = ne11 < 1536;
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break;
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case GGML_TYPE_IQ2_K:
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case GGML_TYPE_IQ2_K_R4:
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mmq_supported = ne11 < 2048;
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break;
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case GGML_TYPE_IQ3_K:
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case GGML_TYPE_IQ4_K:
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case GGML_TYPE_IQ5_K:
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case GGML_TYPE_IQ6_K:
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case GGML_TYPE_IQ3_K_R4:
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case GGML_TYPE_IQ4_K_R4:
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case GGML_TYPE_IQ5_K_R4:
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mmq_supported = ne11 < 1024;
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break;
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case GGML_TYPE_Q4_0:
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case GGML_TYPE_Q4_1:
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case GGML_TYPE_Q5_0:
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case GGML_TYPE_Q5_1:
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case GGML_TYPE_Q6_0:
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case GGML_TYPE_Q8_0:
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case GGML_TYPE_Q4_K:
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case GGML_TYPE_Q5_K:
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case GGML_TYPE_IQ2_XXS:
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case GGML_TYPE_IQ3_XXS:
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case GGML_TYPE_IQ3_S:
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case GGML_TYPE_IQ1_S:
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case GGML_TYPE_IQ1_S_R4:
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case GGML_TYPE_IQ4_XS:
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case GGML_TYPE_IQ4_NL:
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case GGML_TYPE_IQ3_KS:
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case GGML_TYPE_IQ4_KS:
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case GGML_TYPE_IQ4_KS_R4:
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case GGML_TYPE_IQ5_KS:
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case GGML_TYPE_IQ5_KS_R4:
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case GGML_TYPE_IQ2_KS:
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case GGML_TYPE_IQ2_KT:
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case GGML_TYPE_IQ3_KT:
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case GGML_TYPE_IQ4_KT:
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mmq_supported = true;
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break;
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default:
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mmq_supported = false;
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break;
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}
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if (!mmq_supported) {
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return false;
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}
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if (int8_mma_available(cc)) {
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return true;
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}
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if (type == GGML_TYPE_IQ1_S_R4) {
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return false;
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}
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if (cc < MIN_CC_DP4A) {
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return false;
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}
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#ifdef GGML_CUDA_FORCE_MMQ
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return true;
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#endif //GGML_CUDA_FORCE_MMQ
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if (cc < CC_OFFSET_AMD) {
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return cc < CC_VOLTA || ne11 < MMQ_DP4A_MAX_BATCH_SIZE;
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}
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return cc < CC_RDNA3 || ne11 < MMQ_DP4A_MAX_BATCH_SIZE;
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}
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