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[PR #102] [Fix] Fence all TP readers before FP8 staging-slot reuse #103
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📋 Pull Request Information
Original PR: https://github.com/kvcache-ai/sglang/pull/102
Author: @f-wunderlich
Created: 10/10/2026
Status: 🔄 Open
Base:
main← Head:fix-fp8-staging-reader-fence📝 Commits (1)
db97622Fence all TP readers before reusing FP8 staging slots📊 Changes
2 files changed (+251 additions, -3 deletions)
View changed files
📝
python/sglang/srt/layers/moe/kt_ep_wrapper.py(+14 -3)➕
test/unit/test_fp8_staging_readers.py(+237 -0)📄 Description
Motivation
Fixes https://github.com/kvcache-ai/ktransformers/issues/2226.
SharedFullContext._prepare_weight_fp8double-buffers host expert weights,but rank zero waits only for its own GPU reader before the native writer
overwrites every TP rank's slot. A slower peer can still be copying expert E
when the writer replaces that slot with E+2. The existing publication barrier
after the write cannot protect those earlier reads.
The same issue remains on this fork's current main
18c0de72e59359baba793f7a5675f983aa656fc9. The fix is submitted here becausethis code belongs to KTransformers' SGLang fork, not the parent SGLang main.
Modifications
the first write of a new layer load.
collectively fence before rank zero submits the next native write.
quantization and kernel arithmetic. Skip the reader wait when no subsequent
write will reuse the slot.
with simulated asynchronous CUDA/native boundaries. Queued copies retain
references to the host slots; the writer rejects overwriting a slot while
any rank still has a pending read. This checks a state invariant, not merely
the presence of synchronization calls in the source.
This intentionally changes only the reproduced generic FP8 method. Formats
delegating to it inherit the fences; separate FP8-channel/BF16 transports and
the specialized GLM-5-Next path are not modified or qualified here.
Accuracy Tests
New CPU fixture:
two successive loads with 1/2/5 experts, and TP1 without collectives.
TP2 schedules with premature slot reuse; TP1 passes.
checks pass for the new test and changed code as applicable.
The production diff is the same fence ordering already deployed and GPU-validated
in our pinned Qwen integration; only upstream line offsets differ. Historical
runtime evidence from #2226, not a new full GPU run of this PR branch:
before expert arithmetic. One unfenced load had 253/256 down-projection
scale tensors matching expert E+2 rather than the intended expert.
their checkpoint TP shards across three requests, both ranks and five chunks.
two tool-evidence extensions and a structured tool-call/result round trip.
The simulated test does not replace real GPU validation. These results prove
the reproduced transport race, not bit-equivalence of CPU/GPU arithmetic or
universal prefix-cache/agent correctness.
Benchmarking and Profiling
The fences have a real prefill cost; the faster unfenced timings are not a
correct-execution baseline. Historical deployed 2K-chunk measurements:
Each request generated 16 tokens. Decode remained about 14.5 tok/s in that
configuration. These are pinned-integration observations, not benchmarks of
the entire latest fork or a full-window qualification.
Checklist
🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.