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eda74a7f29
Introduce handle cache for AMD platform. Avoid reaching handle limitation if we open too much IPC handles For nvidia, we don't need this feature since nvidia will count the handle reference internally and reuse the same handle if already be opened --------- Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> Co-authored-by: Binyang2014 <9415966+Binyang2014@users.noreply.github.com> Co-authored-by: Changho Hwang <changhohwang@microsoft.com>
28 lines
752 B
Python
28 lines
752 B
Python
# Copyright (c) Microsoft Corporation.
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# Licensed under the MIT License.
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import mpi4py
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import os
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import sys
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mpi4py.rc.initialize = False
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mpi4py.rc.finalize = True
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import cupy as cp
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from mpi4py import MPI
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def pytest_configure(config):
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"""Initialize MPI before test collection."""
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if not MPI.Is_initialized():
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MPI.Init()
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shm_comm = MPI.COMM_WORLD.Split_type(MPI.COMM_TYPE_SHARED, 0, MPI.INFO_NULL)
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N_GPUS_PER_NODE = shm_comm.size
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shm_comm.Free()
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cp.cuda.Device(MPI.COMM_WORLD.rank % N_GPUS_PER_NODE).use()
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# only print process with rank 0 to avoid bad fd issue
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if MPI.COMM_WORLD.rank != 0:
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sys.stdout = open(os.devnull, "w")
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sys.stderr = open(os.devnull, "w")
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