Binyang Li 865c2bc795 Optimize MNNVL allreduce without symmetric memory ...

Run the tuning example with symmetric memory disabled, make allreduce tuning use the same symmetric-memory mode as execution, and narrow the MNNVL small-message candidate set to avoid slower packet/NVLS choices. Increase packet and RSAG channel parallelism so non-symmetric CUDA-IPC paths can use 112-block packet and 128-block RSAG configs.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

2026-04-28 07:55:52 +00:00

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customized-collective-algorithm

Support E4M3B15 datatype (#765)

2026-04-07 13:37:02 -07:00

torch-integration

Optimize MNNVL allreduce without symmetric memory

2026-04-28 07:55:52 +00:00

tutorials

Mahdieh/switchchannel test clean (#751)

2026-02-20 22:46:32 -05:00