Binyang Li 893a08e69c Enable MNNVL allreduce tuning ...

Add an MNNVL rank-domain override so MSCCL++ collectives can treat multi-host NVLink fabrics as a single CUDA IPC/NVLS peer group. Update packet, RSAG, and NVLS allreduce paths to use the collective domain size and teach the torch integration tuning example to select MNNVL-capable allreduce algorithms.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

2026-04-28 05:38:59 +00:00

..

ext

Refactor algo selection logic and introduce symmetric_memory env (#741)

2026-02-12 19:06:18 -08:00

npkit

Supporting New Packet Kernel Operation at Executor (#677)

2025-11-13 14:08:44 -08:00

algorithm.hpp

Support E4M3B15 datatype (#765)

2026-04-07 13:37:02 -07:00

assert_device.hpp

Fix cpplint error in main branch (#740)

2026-02-05 09:25:12 -08:00

atomic_device.hpp

IB host-no-atomic: GDRCopy + mlx5dv Data Direct for memory-consistent low-latency signaling (#753)

2026-04-09 09:24:30 +00:00

concurrency_device.hpp

all2all implementation (#609)

2025-08-14 11:30:40 -07:00

copy_device.hpp

New DSL implementation (#579)

2025-08-09 00:36:20 -07:00

core.hpp

Add MSCCLPP_IB_GID_INDEX env (#780)

2026-04-13 09:59:42 -07:00

device.hpp

Multi-stream CUDA IPC (#326)

2025-06-04 10:31:04 -07:00

env.hpp

Enable MNNVL allreduce tuning

2026-04-28 05:38:59 +00:00

errors.hpp

Improved documentation & minor interface revision (#541)

2025-06-03 14:26:27 -07:00

executor.hpp

Torch integration (#692)

2026-01-21 20:32:24 -08:00

fifo_device.hpp

Add FifoDeviceHandle::poll() (#630)

2025-09-09 23:32:35 +00:00

fifo.hpp

Fix a FIFO correctness bug (#549)

2025-07-11 23:53:59 +00:00

gpu_data_types.hpp

Add ROCm FP8 E4M3B15 support (#774)

2026-04-08 09:53:45 -07:00

gpu_utils.hpp

Add CudaDeviceGuard (#691)

2025-11-24 13:38:44 -08:00

gpu.hpp

Refactor algo selection logic and introduce symmetric_memory env (#741)

2026-02-12 19:06:18 -08:00

memory_channel_device.hpp

Revise NVLS interface (#458)

2025-07-12 00:33:03 +00:00

memory_channel.hpp

Use smart pointer for IB structure (#585)

2025-08-06 10:01:58 -07:00

numa.hpp

Improved documentation & minor interface revision (#541)

2025-06-03 14:26:27 -07:00

packet_device.hpp

Multi-stream CUDA IPC (#326)

2025-06-04 10:31:04 -07:00

poll_device.hpp

Rename ChannelTrigger fields and check field values in debug builds (#529)

2025-05-27 14:36:22 -07:00

port_channel_device.hpp

Merge ChannelTrigger with ProxyTrigger (#601)

2025-08-08 19:07:50 +00:00

port_channel.hpp

connect() APIs changed to return an instance instead of a shared_ptr (#680)

2025-11-15 11:40:40 -08:00

proxy.hpp

Do threadInit/cudaSetDevice before other cuda calls (#757)

2026-03-02 15:53:59 -08:00

semaphore_device.hpp

Use PTX red for D2D semaphore signal (#768)

2026-03-31 15:34:43 -07:00

semaphore.hpp

IB host-no-atomic: GDRCopy + mlx5dv Data Direct for memory-consistent low-latency signaling (#753)

2026-04-09 09:24:30 +00:00

switch_channel_device.hpp

Refactor reduce kernel (#738)

2026-02-05 09:23:43 -08:00

switch_channel.hpp

Use GpuIpcMem for NVLS connections (#719)

2026-01-15 13:16:04 +08:00

utils.hpp

Remove UB std:: declarations (#709)

2026-01-05 11:11:46 +08:00

version.hpp.in

Add MSCCLPP_GIT_COMMIT micro (#640)

2025-10-06 15:57:28 -07:00