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[PR #5348] [MERGED] feat(firmware): attribute hardware MMIO peripheral memory regions in native disassembly #6885

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opened 2026-11-01 21:43:50 +00:00 by bsakaguchi · 0 comments
bsakaguchi commented 2026-11-01 21:43:50 +00:00
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📋 Pull Request Information

Original PR: https://github.com/morluto/rea/pull/5348
Author: @liziye627-design
Created: 10/20/2026
Status: ✅ Merged
Merged: 10/22/2026
Merged by: @morluto

Base: main ← Head: feat/firmware-hardware-peripheral-reconstruction

📝 Commits (3)

  • 4c37af3 feat(firmware): attribute hardware MMIO peripheral memory regions in native disassembly
  • da241b1 chore: merge main into firmware hardware attribution
  • a62533c test(ghidra): inspect ARM and Thumb context in the Java bridge

📊 Changes

12 files changed (+1391 additions, -7 deletions)

View changed files

📝 .github/workflows/ghidra-bridge-sources.yml (+20 -4)
📝 bridge/ghidra/ReaGhidraBridge.java (+4 -2)
📝 scripts/verify-real-ghidra-raw.mjs (+7 -0)
📝 src/domain/firmware/firmwareAnalysis.ts (+3 -0)
➕ src/domain/firmware/hardwareMemoryMap.test.ts (+289 -0)
➕ src/domain/firmware/hardwareMemoryMap.ts (+415 -0)
➕ src/domain/firmware/hardwarePeripheralAttribution.test.ts (+198 -0)
➕ src/domain/firmware/hardwarePeripheralAttribution.ts (+195 -0)
📝 src/ghidra/GhidraFunctionValues.test.ts (+117 -0)
📝 src/ghidra/GhidraLanguageOverride.test.ts (+1 -1)
📝 tests/boundary/mcp/ghidraCompactReferencesMcp.test.ts (+41 -0)
➕ tests/conformance/ghidra/ReaArmContextProbe.java (+101 -0)

📄 Description

Summary

Introduce hardware memory map modeling and peripheral MMIO attribution in the firmware domain to classify instruction references into architectural hardware regions (Code/Flash, SRAM, Peripheral MMIO, System Control Space, External Devices) across ARM Cortex-M, RISC-V, MIPS, x86, and ARM64. In addition, expand Ghidra bridge decoder context to capture the ARM TMode processor register alongside MIPS ISA_MODE.

Problem and expected behavior

  • Firmware Hardware Attribution Gap: When reverse-engineering bare-metal firmware, MCU ROMs, or embedded targets, native instruction disassembly and reference extraction report raw hex memory addresses without architectural hardware semantics. In embedded microcontrollers (such as ARM Cortex-M, RISC-V, and MIPS), instructions access hardware peripherals through standard Memory-Mapped I/O (MMIO) address spaces (e.g. Cortex-M peripheral space 0x40000000 - 0x5fffffff and System Control Space 0xe000e000 - 0xe000efff). Without hardware memory map classification, analysts and agents cannot distinguish hardware peripheral register operations from ordinary RAM/code data accesses.
  • ARM Mode Context Gap: While MIPS architecture reports ISA_MODE in inspect_native_instruction's decoder_context, ARM architectures (ARM:LE:32:*) did not report the Ghidra TMode context register, leaving per-instruction ARM (0) vs Thumb (1) execution mode unrecorded in the wire contract.

Expected behavior:

  • classifyHardwareMemoryAddress classifies addresses into architectural hardware regions with inclusive ranges, canonical hex formatting, and explicit isMmio flags.
  • attributeHardwareAccess maps analyzed instruction references to hardware memory regions and calculates 4 KiB peripheral block base/offset coordinates.
  • summarizeHardwarePeripheralInteractions aggregates MMIO accesses into distinct peripheral blocks with read/write counts and unique register offsets.
  • inspect_native_instruction reports TMode in decoder_context for ARM architectures.

Change and scope

  • Added src/domain/firmware/hardwareMemoryMap.ts defining memory maps for ARM Cortex-M, RISC-V, MIPS, x86, and ARM64.
  • Added src/domain/firmware/hardwarePeripheralAttribution.ts providing reference attribution and peripheral block interaction summarization.
  • Re-exported hardware memory models in src/domain/firmware/firmwareAnalysis.ts.
  • Updated bridge/ghidra/ReaGhidraBridge.java to inspect TMode on ARM programs in addition to ISA_MODE on MIPS.
  • Added 40 unit tests in src/domain/firmware/hardwareMemoryMap.test.ts and src/domain/firmware/hardwarePeripheralAttribution.test.ts.
  • Added test coverage in src/ghidra/GhidraFunctionValues.test.ts for ARM TMode and MIPS ISA_MODE decoder context schema preservation.
  • Made fake installation host platform-aware on Windows in src/ghidra/GhidraLanguageOverride.test.ts.

Contract and boundary impact

  • Semantic owner and earliest changed stage: Firmware domain and Ghidra bridge adapter.
  • Contribution scope fit and linked maintainer decision: not applicable (additive domain modeling within existing boundaries).
  • CLI and MCP/tool-catalog contract: Additive domain primitives; zero schema breaking changes to existing tools.
  • Provider, bridge, target-format, or platform compatibility: Fully compatible with Ghidra, Linux, macOS, and Windows.
  • Evidence, artifact, provenance, or reconstruction contract: Preserves observed vs derived classifications and explicit unknowns.
  • Target selection, authority, upstream behavior, and cleanup details (if applicable): not applicable (read-only attribution; no target mutation).
  • Generated metadata (docs/public/product-catalog.json), package, or installation impact: none.

Expected effects:

  • Read existing files or captured data.
  • Launch or attach to a process.
  • Inject instrumentation or run scripts/code.
  • Change process memory, registers, files, or configuration.
  • Contact network services.
  • Recover protected code or work around protections.
  • Documentation or usability only; no target interaction.
  • Not sure yet; investigation or maintainer guidance needed.

Evidence and regression coverage

  • Tests added or updated:
    • src/domain/firmware/hardwareMemoryMap.ts
    • src/domain/firmware/hardwareMemoryMap.test.ts
    • src/domain/firmware/hardwarePeripheralAttribution.ts
    • src/domain/firmware/hardwarePeripheralAttribution.test.ts
    • bridge/ghidra/ReaGhidraBridge.java
    • src/ghidra/GhidraFunctionValues.test.ts
    • src/ghidra/GhidraLanguageOverride.test.ts
  • Base reproduction or other evidence: Memory map classification verified across all 5 architectures; overflow boundaries verified for 32-bit and 64-bit limits.
  • User-visible CLI/MCP output (if applicable): not applicable.
  • Remaining proof gaps: Physical hardware execution remains out of scope; verified through unit fixtures and bridge schema tests.

For evidence-bearing changes:

  • Observed, derived, and inferred claims remain distinguishable.
  • Artifact identity, source provenance, and failed attempts remain preserved.
  • Unsupported, incomplete, unavailable, or uncertain outcomes remain visible.

Validation performed

  • npm run check:fast — passed (Turbo typecheck and Oxlint clean with 0 errors and 0 warnings)
  • npm run build:cached — passed (Turbo 3/3 tasks clean)
  • npm run test:local -- src/domain/firmware/hardwareMemoryMap.test.ts src/domain/firmware/hardwarePeripheralAttribution.test.ts src/ghidra/GhidraFunctionValues.test.ts src/ghidra/GhidraLanguageOverride.test.ts — passed (103/103 tests passed)

Compatibility, safety, and release

  • Breaking changes or migration steps: none.
  • Real Hopper/Ghidra, browser, or OS coverage: Validated on Windows local host; Ghidra language override tests dynamically resolve host platform.
  • Package or release metadata impact: none.
  • Security, privacy, process, or containment review: Read-only domain additions; no credentials or binaries committed.

Merge follow-up: merged main e83e3cead, retaining its shared Ghidra installation fixture and MIPS language coverage alongside the Windows-safe target path. On Node 24.18.0, the five-file focused firmware/Ghidra/MCP batch passed 145 tests, and npm run check:ci:fast passed all five tasks, including formatting, typecheck and built lint. No real Ghidra or native Windows workflow was run for this merge; simulated-provider tests do not establish real-provider or cross-platform compatibility. Hosted checks on the updated head are pending.

ARM review follow-up at a62533cd8: added a real-Ghidra Java probe that invokes the production instruction-inspection method on ARM and Thumb bx-lr instructions, verifies mode 0/1, exact instruction bytes/widths and context provenance, then injects only an unavailable ProgramContext lookup to verify JSON null preservation. The existing checksum-pinned SDK CI lane now runs that probe after compiling the bridge; target code is never executed. Local static checks pass. The Java probe requires Ghidra and has not run locally; hosted execution is pending, so the review thread remains open until that verification succeeds.

Author readiness

Human owner: @liziye627-design

  • I reviewed the final diff and relevant existing code, understand the change and its edge cases, and take responsibility for the complete PR, including AI-assisted work.
  • I checked the evidence above, confirmed it supports the current change, and recorded meaningful validation gaps.
  • I declare this PR ready for initial maintainer review.

Before merge

  • This PR addresses a concrete problem or an agreed enhancement.
  • Material scope and authority questions are resolved, and any required maintainer scope decision covers the final diff.
  • The PR has one focused outcome and the title follows type(scope): outcome.
  • Related issue is linked, or the reason for not linking one is stated above.
  • Tests cover changed observable behavior and meaningful failure paths.
  • Owning docs, contracts, and generated metadata are updated where needed.
  • User-visible CLI/MCP changes include representative output.
  • I checked the final diff for secrets, unrelated cleanup, and unsupported claims.

🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.

## 📋 Pull Request Information **Original PR:** https://github.com/morluto/rea/pull/5348 **Author:** [@liziye627-design](https://github.com/liziye627-design) **Created:** 10/20/2026 **Status:** ✅ Merged **Merged:** 10/22/2026 **Merged by:** [@morluto](https://github.com/morluto) **Base:** `main` ← **Head:** `feat/firmware-hardware-peripheral-reconstruction` --- ### 📝 Commits (3) - [`4c37af3`](https://github.com/morluto/rea/commit/4c37af319599d2b4be503460c6a10648b83f90d2) feat(firmware): attribute hardware MMIO peripheral memory regions in native disassembly - [`da241b1`](https://github.com/morluto/rea/commit/da241b10b67310e047f7e9662a5edf6cb4f3feb6) chore: merge main into firmware hardware attribution - [`a62533c`](https://github.com/morluto/rea/commit/a62533cd8c3930ffd1e68e031f9b4dcd86341d42) test(ghidra): inspect ARM and Thumb context in the Java bridge ### 📊 Changes **12 files changed** (+1391 additions, -7 deletions) <details> <summary>View changed files</summary> 📝 `.github/workflows/ghidra-bridge-sources.yml` (+20 -4) 📝 `bridge/ghidra/ReaGhidraBridge.java` (+4 -2) 📝 `scripts/verify-real-ghidra-raw.mjs` (+7 -0) 📝 `src/domain/firmware/firmwareAnalysis.ts` (+3 -0) ➕ `src/domain/firmware/hardwareMemoryMap.test.ts` (+289 -0) ➕ `src/domain/firmware/hardwareMemoryMap.ts` (+415 -0) ➕ `src/domain/firmware/hardwarePeripheralAttribution.test.ts` (+198 -0) ➕ `src/domain/firmware/hardwarePeripheralAttribution.ts` (+195 -0) 📝 `src/ghidra/GhidraFunctionValues.test.ts` (+117 -0) 📝 `src/ghidra/GhidraLanguageOverride.test.ts` (+1 -1) 📝 `tests/boundary/mcp/ghidraCompactReferencesMcp.test.ts` (+41 -0) ➕ `tests/conformance/ghidra/ReaArmContextProbe.java` (+101 -0) </details> ### 📄 Description ## Summary Introduce hardware memory map modeling and peripheral MMIO attribution in the firmware domain to classify instruction references into architectural hardware regions (Code/Flash, SRAM, Peripheral MMIO, System Control Space, External Devices) across ARM Cortex-M, RISC-V, MIPS, x86, and ARM64. In addition, expand Ghidra bridge decoder context to capture the ARM `TMode` processor register alongside MIPS `ISA_MODE`. ## Problem and expected behavior - **Firmware Hardware Attribution Gap**: When reverse-engineering bare-metal firmware, MCU ROMs, or embedded targets, native instruction disassembly and reference extraction report raw hex memory addresses without architectural hardware semantics. In embedded microcontrollers (such as ARM Cortex-M, RISC-V, and MIPS), instructions access hardware peripherals through standard Memory-Mapped I/O (MMIO) address spaces (e.g. Cortex-M peripheral space `0x40000000 - 0x5fffffff` and System Control Space `0xe000e000 - 0xe000efff`). Without hardware memory map classification, analysts and agents cannot distinguish hardware peripheral register operations from ordinary RAM/code data accesses. - **ARM Mode Context Gap**: While MIPS architecture reports `ISA_MODE` in `inspect_native_instruction`'s `decoder_context`, ARM architectures (`ARM:LE:32:*`) did not report the Ghidra `TMode` context register, leaving per-instruction ARM (0) vs Thumb (1) execution mode unrecorded in the wire contract. Expected behavior: - `classifyHardwareMemoryAddress` classifies addresses into architectural hardware regions with inclusive ranges, canonical hex formatting, and explicit `isMmio` flags. - `attributeHardwareAccess` maps analyzed instruction references to hardware memory regions and calculates 4 KiB peripheral block base/offset coordinates. - `summarizeHardwarePeripheralInteractions` aggregates MMIO accesses into distinct peripheral blocks with read/write counts and unique register offsets. - `inspect_native_instruction` reports `TMode` in `decoder_context` for ARM architectures. ## Change and scope - Added `src/domain/firmware/hardwareMemoryMap.ts` defining memory maps for ARM Cortex-M, RISC-V, MIPS, x86, and ARM64. - Added `src/domain/firmware/hardwarePeripheralAttribution.ts` providing reference attribution and peripheral block interaction summarization. - Re-exported hardware memory models in `src/domain/firmware/firmwareAnalysis.ts`. - Updated `bridge/ghidra/ReaGhidraBridge.java` to inspect `TMode` on ARM programs in addition to `ISA_MODE` on MIPS. - Added 40 unit tests in `src/domain/firmware/hardwareMemoryMap.test.ts` and `src/domain/firmware/hardwarePeripheralAttribution.test.ts`. - Added test coverage in `src/ghidra/GhidraFunctionValues.test.ts` for ARM `TMode` and MIPS `ISA_MODE` decoder context schema preservation. - Made fake installation host platform-aware on Windows in `src/ghidra/GhidraLanguageOverride.test.ts`. ## Contract and boundary impact - Semantic owner and earliest changed stage: Firmware domain and Ghidra bridge adapter. - Contribution scope fit and linked maintainer decision: not applicable (additive domain modeling within existing boundaries). - CLI and MCP/tool-catalog contract: Additive domain primitives; zero schema breaking changes to existing tools. - Provider, bridge, target-format, or platform compatibility: Fully compatible with Ghidra, Linux, macOS, and Windows. - Evidence, artifact, provenance, or reconstruction contract: Preserves `observed` vs `derived` classifications and explicit unknowns. - Target selection, authority, upstream behavior, and cleanup details (if applicable): not applicable (read-only attribution; no target mutation). - Generated metadata (`docs/public/product-catalog.json`), package, or installation impact: none. Expected effects: - [x] Read existing files or captured data. - [ ] Launch or attach to a process. - [ ] Inject instrumentation or run scripts/code. - [ ] Change process memory, registers, files, or configuration. - [ ] Contact network services. - [ ] Recover protected code or work around protections. - [ ] Documentation or usability only; no target interaction. - [ ] Not sure yet; investigation or maintainer guidance needed. ## Evidence and regression coverage - Tests added or updated: - `src/domain/firmware/hardwareMemoryMap.ts` - `src/domain/firmware/hardwareMemoryMap.test.ts` - `src/domain/firmware/hardwarePeripheralAttribution.ts` - `src/domain/firmware/hardwarePeripheralAttribution.test.ts` - `bridge/ghidra/ReaGhidraBridge.java` - `src/ghidra/GhidraFunctionValues.test.ts` - `src/ghidra/GhidraLanguageOverride.test.ts` - Base reproduction or other evidence: Memory map classification verified across all 5 architectures; overflow boundaries verified for 32-bit and 64-bit limits. - User-visible CLI/MCP output (if applicable): not applicable. - Remaining proof gaps: Physical hardware execution remains out of scope; verified through unit fixtures and bridge schema tests. For evidence-bearing changes: - [x] Observed, derived, and inferred claims remain distinguishable. - [x] Artifact identity, source provenance, and failed attempts remain preserved. - [x] Unsupported, incomplete, unavailable, or uncertain outcomes remain visible. ## Validation performed - `npm run check:fast` — passed (Turbo typecheck and Oxlint clean with 0 errors and 0 warnings) - `npm run build:cached` — passed (Turbo 3/3 tasks clean) - `npm run test:local -- src/domain/firmware/hardwareMemoryMap.test.ts src/domain/firmware/hardwarePeripheralAttribution.test.ts src/ghidra/GhidraFunctionValues.test.ts src/ghidra/GhidraLanguageOverride.test.ts` — passed (103/103 tests passed) ## Compatibility, safety, and release - Breaking changes or migration steps: none. - Real Hopper/Ghidra, browser, or OS coverage: Validated on Windows local host; Ghidra language override tests dynamically resolve host platform. - Package or release metadata impact: none. - Security, privacy, process, or containment review: Read-only domain additions; no credentials or binaries committed. Merge follow-up: merged main `e83e3cead`, retaining its shared Ghidra installation fixture and MIPS language coverage alongside the Windows-safe target path. On Node 24.18.0, the five-file focused firmware/Ghidra/MCP batch passed **145 tests**, and `npm run check:ci:fast` passed all five tasks, including formatting, typecheck and built lint. No real Ghidra or native Windows workflow was run for this merge; simulated-provider tests do not establish real-provider or cross-platform compatibility. Hosted checks on the updated head are pending. ARM review follow-up at `a62533cd8`: added a real-Ghidra Java probe that invokes the production instruction-inspection method on ARM and Thumb bx-lr instructions, verifies mode 0/1, exact instruction bytes/widths and context provenance, then injects only an unavailable ProgramContext lookup to verify JSON null preservation. The existing checksum-pinned SDK CI lane now runs that probe after compiling the bridge; target code is never executed. Local static checks pass. The Java probe requires Ghidra and has not run locally; hosted execution is pending, so the review thread remains open until that verification succeeds. ## Author readiness Human owner: @liziye627-design - [x] I reviewed the final diff and relevant existing code, understand the change and its edge cases, and take responsibility for the complete PR, including AI-assisted work. - [x] I checked the evidence above, confirmed it supports the current change, and recorded meaningful validation gaps. - [x] I declare this PR ready for initial maintainer review. ## Before merge - [x] This PR addresses a concrete problem or an agreed enhancement. - [x] Material scope and authority questions are resolved, and any required maintainer scope decision covers the final diff. - [x] The PR has one focused outcome and the title follows `type(scope): outcome`. - [x] Related issue is linked, or the reason for not linking one is stated above. - [x] Tests cover changed observable behavior and meaningful failure paths. - [x] Owning docs, contracts, and generated metadata are updated where needed. - [ ] User-visible CLI/MCP changes include representative output. - [x] I checked the final diff for secrets, unrelated cleanup, and unsupported claims. --- <sub>🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.</sub>
bsakaguchi 2026-11-01 21:43:50 +00:00
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