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[PR #89] [MERGED] Improve alignment between the ROCm and CUDA backends #111
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Comfy-Org/comfy-aimdo#111
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📋 Pull Request Information
Original PR: https://github.com/Comfy-Org/comfy-aimdo/pull/89
Author: @0xDELUXA
Created: 8/15/2026
Status: ✅ Merged
Merged: 9/7/2026
Merged by: @rattus128
Base:
master← Head:amd/rocm-parity📝 Commits (5)
9a5da80hip: prefer the ROCm 7 runtime and correct dispatch symbol resolution6bef92bshmem-detect: drop vendor specific sysmem fallback wording2614512control: prefer torch.version.hip over the local version segment8d50ceavrambuf: lock and tear down the rocm windows VA reservation pool21e94b6control: budget integrated rocm GPUs against system RAM on linux📊 Changes
8 files changed (+88 additions, -7 deletions)
View changed files
📝
comfy_aimdo/control.py(+11 -0)📝
src-hip/dispatch.c(+14 -3)📝
src-win/shmem-detect.c(+1 -1)📝
src/control.c(+5 -3)📝
src/control.h(+2 -0)📝
src/gpu_abi.h(+8 -0)📝
src/plat.h(+9 -0)📝
src/vrambuf.c(+38 -0)📄 Description
Five places where the HIP backend has drifted from the CUDA one, found by diffing the two side by side. Some are plainly bugs, some are divergences, marked below.
github.com/Comfy-Org/comfy-aimdo@159abbelanded behind a!defined(__HIP_PLATFORM_AMD__)guard, so APUs on ROCm get budgeted againsthipMemGetInforather than/proc/meminfoMemAvailable. Enabling it needs a per-backend attribute value:hipDeviceAttributeIntegratedis 16, so reusing the CUDA 18 would have queriedhipDeviceAttributeKernelExecTimeout. Whether theMemAvailableheuristic suits an AMD APU needs testing.hipGetDevicePropertiesfallback returns the wrong struct layout.shmem-detect.creadsuuidandluid, which the R0000 layout does not have, so the fallback can only ever produce a bogus LUID and a failed adapter match. Removed rather than fixed. Latent; the R0600 lookup succeeds on current runtimes.github.com/Comfy-Org/comfy-aimdo@2362071added a mutex,github.com/Comfy-Org/comfy-aimdo@c760f6amoved the pool intoAimdoContextand dropped it, but that struct is shared across threads andvrambuf_destroyruns on whichever thread drops the last Python reference. Nothing drained the pool either, so parked reservations leaked acrossinit/cleanupcycles. Leak is a straightforward bug; race is real by inspection, not reproduced.torch.version.hipis authoritative and is checked before the+rocmstring match. Defensive; current wheels do carry+rocm.amdhip64_7.dllis now searched before the unsuffixed ROCm 5 eraamdhip64.dll. Cosmetic ordering change.Testing
Linux and APUs are the gap: Windows on a discrete RDNA4 card (gfx1200) is already covered, see below.
Nothing needs building. CI builds wheels for every push to this PR. On the Checks tab open the latest Build Wheels run, download the artifact for your platform (
wheels-windows-amd64,wheels-linux-x86_64, and so on), and unzip it to get a.whl. Then, with ComfyUI closed, install it into ComfyUI's venv:The version in the file name moves with each push, so use whatever the artifact you downloaded actually contains. Downloading run artifacts requires being signed in to GitHub. To go back afterwards:
pip install --force-reinstall --no-deps comfy-aimdo==<the version you had>.If you would rather build it yourself,
.github/workflows/build-wheels.ymlcarries the exact commands for both platforms.Verification
CI is green on all four wheel targets, linux x86_64 and aarch64 and windows amd64 and arm64, which builds both backends on both platforms.
hipDeviceAttributeIntegrated == 16was confirmed against the ROCm headers and by querying a live gfx1200 GPU.Run in ComfyUI on Windows on a discrete gfx1200 (RDNA4) card with a current ROCm PyTorch wheel, on workloads that offload: behaves the same as upstream. That exercises runtime and symbol resolution, the WDDM adapter match through the R0600 lookup, and the hook dedup.
It does not exercise the integrated path, which is compiled out on Windows. No Linux ROCm install or APU was available here, so that one is compiled but never run and is where testing would help most.
🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.