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Andy Ritger
2022-05-09 13:18:59 -07:00
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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _DISPLAYPORT_H_
#define _DISPLAYPORT_H_
#include "nvmisc.h"
#include "dpcd.h"
#include "dpcd14.h"
#include "dpcd20.h"
/**************** Resource Manager Defines and Structures ******************\
* *
* Module: DISPLAYPORT.H *
* Defines DISPLAYPORT V1.2 *
* *
\***************************************************************************/
// Displayport interoperability with HDMI dongle i2c addr
#define DP2HDMI_DONGLE_I2C_ADDR 0x80
#define DP2HDMI_DONGLE_DDC_BUFFER_ID_LEN 16
#define DP2HDMI_DONGLE_CAP_BUFFER_LEN 32
// Offset to read the dongle identifier
#define NV_DP2HDMI_DONGLE_IDENTIFIER (0x00000010)
#define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_REV 2:0
#define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_REV_TYPE2 (0x00000000)
#define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_ID 7:4
#define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_ID_TYPE2 (0x0000000A)
// Offset to read the dongle TMDS clock rate
#define NV_DP2HDMI_DONGLE_TMDS_CLOCK_RATE (0x0000001D)
// HDMI dongle types
#define DP2HDMI_DONGLE_TYPE_1 0x1
#define DP2HDMI_DONGLE_TYPE_2 0x2
// HDMI dongle frequency limits
#define DP2HDMI_DONGLE_TYPE_1_PCLK_LIMIT 165*1000*1000
#define DP2HDMI_DONGLE_TYPE_2_PCLK_LIMIT 300*1000*1000
#define DPCD_VERSION_12 0x12
#define DPCD_VERSION_13 0x13
#define DPCD_VERSION_14 0x14
#define DP_LINKINDEX_0 0x0
#define DP_LINKINDEX_1 0x1
// Two Head One OR
#define NV_PRIMARY_HEAD_INDEX_0 0
#define NV_SECONDARY_HEAD_INDEX_1 1
#define NV_PRIMARY_HEAD_INDEX_2 2
#define NV_SECONDARY_HEAD_INDEX_3 3
typedef enum
{
displayPort_Lane0 = 0,
displayPort_Lane1 = 1,
displayPort_Lane2 = 2,
displayPort_Lane3 = 3,
displayPort_Lane4 = 4,
displayPort_Lane5 = 5,
displayPort_Lane6 = 6,
displayPort_Lane7 = 7,
displayPort_LaneSupported
} DP_LANE;
typedef enum
{
laneCount_0 = 0x0,
laneCount_1 = 0x1,
laneCount_2 = 0x2,
laneCount_4 = 0x4,
laneCount_8 = 0x8,
laneCount_Supported
} DP_LANE_COUNT;
typedef enum
{
linkBW_1_62Gbps = 0x06,
linkBW_2_16Gbps = 0x08,
linkBW_2_43Gbps = 0x09,
linkBW_2_70Gbps = 0x0A,
linkBW_3_24Gbps = 0x0C,
linkBW_4_32Gbps = 0x10,
linkBW_5_40Gbps = 0x14,
linkBW_8_10Gbps = 0x1E,
linkBW_Supported
} DP_LINK_BANDWIDTH;
typedef enum
{
linkSpeedId_1_62Gbps = 0x00,
linkSpeedId_2_70Gbps = 0x01,
linkSpeedId_5_40Gbps = 0x02,
linkSpeedId_8_10Gbps = 0x03,
linkSpeedId_2_16Gbps = 0x04,
linkSpeedId_2_43Gbps = 0x05,
linkSpeedId_3_24Gbps = 0x06,
linkSpeedId_4_32Gbps = 0x07,
linkSpeedId_Supported
} DP_LINK_SPEED_INDEX;
typedef enum
{
postCursor2_Level0 = 0,
postCursor2_Level1 = 1,
postCursor2_Level2 = 2,
postCursor2_Level3 = 3,
postCursor2_Supported
} DP_POSTCURSOR2;
typedef enum
{
preEmphasis_Disabled = 0,
preEmphasis_Level1 = 1,
preEmphasis_Level2 = 2,
preEmphasis_Level3 = 3,
preEmphasis_Supported
} DP_PREEMPHASIS;
typedef enum
{
driveCurrent_Level0 = 0,
driveCurrent_Level1 = 1,
driveCurrent_Level2 = 2,
driveCurrent_Level3 = 3,
driveCurrent_Supported
} DP_DRIVECURRENT;
typedef enum
{
trainingPattern_Disabled = 0x0,
trainingPattern_1 = 0x1,
trainingPattern_2 = 0x2,
trainingPattern_3 = 0x3,
trainingPattern_4 = 0xB
} DP_TRAININGPATTERN;
typedef enum
{
dpOverclock_Percentage_0 = 0,
dpOverclock_Percentage_10 = 10,
dpOverclock_Percentage_20 = 20
}DP_OVERCLOCKPERCENTAGE;
typedef enum
{
dpColorFormat_RGB = 0,
dpColorFormat_YCbCr444 = 0x1,
dpColorFormat_YCbCr422 = 0x2,
dpColorFormat_YCbCr420 = 0x3,
dpColorFormat_Unknown = 0xF
} DP_COLORFORMAT;
typedef enum
{
dp_pktType_VideoStreamconfig = 0x7,
dp_pktType_CeaHdrMetaData = 0x21,
dp_pktType_SRInfoFrame = 0x7f, // Self refresh infoframe for eDP enter/exit self refresh, SRS 1698
dp_pktType_Cea861BInfoFrame = 0x80,
dp_pktType_VendorSpecInfoFrame = 0x81,
dp_pktType_AviInfoFrame = 0x82,
dp_pktType_AudioInfoFrame = 0x84,
dp_pktType_SrcProdDescInfoFrame = 0x83,
dp_pktType_MpegSrcInfoFrame = 0x85,
dp_pktType_DynamicRangeMasteringInfoFrame = 0x87
} DP_PACKET_TYPE;
typedef enum
{
DSC_SLICES_PER_SINK_1 = 1,
DSC_SLICES_PER_SINK_2 = 2,
DSC_SLICES_PER_SINK_4 = 4,
DSC_SLICES_PER_SINK_6 = 6,
DSC_SLICES_PER_SINK_8 = 8,
DSC_SLICES_PER_SINK_10 = 10,
DSC_SLICES_PER_SINK_12 = 12,
DSC_SLICES_PER_SINK_16 = 16,
DSC_SLICES_PER_SINK_20 = 20,
DSC_SLICES_PER_SINK_24 = 24
} DscSliceCount;
typedef enum
{
DSC_BITS_PER_COLOR_MASK_8 = 1,
DSC_BITS_PER_COLOR_MASK_10 = 2,
DSC_BITS_PER_COLOR_MASK_12 = 4
}DscBitsPerColorMask;
enum DSC_MODE
{
DSC_SINGLE,
DSC_DUAL,
DSC_DROP,
DSC_MODE_NONE
};
typedef enum
{
BITS_PER_PIXEL_PRECISION_1_16 = 0,
BITS_PER_PIXEL_PRECISION_1_8 = 1,
BITS_PER_PIXEL_PRECISION_1_4 = 2,
BITS_PER_PIXEL_PRECISION_1_2 = 3,
BITS_PER_PIXEL_PRECISION_1 = 4
}BITS_PER_PIXEL_INCREMENT;
typedef enum
{
NV_DP_FEC_UNCORRECTED = 0,
NV_DP_FEC_CORRECTED = 1,
NV_DP_FEC_BIT = 2,
NV_DP_FEC_PARITY_BLOCK = 3,
NV_DP_FEC_PARITY_BIT = 4
}FEC_ERROR_COUNTER;
typedef struct DscCaps
{
NvBool bDSCSupported;
NvBool bDSCPassThroughSupported;
unsigned versionMajor, versionMinor;
unsigned rcBufferBlockSize;
unsigned rcBuffersize;
unsigned maxSlicesPerSink;
unsigned lineBufferBitDepth;
NvBool bDscBlockPredictionSupport;
unsigned maxBitsPerPixelX16;
unsigned sliceCountSupportedMask;
struct
{
NvBool bRgb;
NvBool bYCbCr444;
NvBool bYCbCrSimple422;
NvBool bYCbCrNative422;
NvBool bYCbCrNative420;
}dscDecoderColorFormatCaps;
unsigned dscDecoderColorDepthMask;
unsigned dscPeakThroughputMode0;
unsigned dscPeakThroughputMode1;
unsigned dscMaxSliceWidth;
BITS_PER_PIXEL_INCREMENT dscBitsPerPixelIncrement;
} DscCaps;
typedef struct GpuDscCrc
{
NvU16 gpuCrc0;
NvU16 gpuCrc1;
NvU16 gpuCrc2;
} gpuDscCrc;
typedef struct SinkDscCrc
{
NvU16 sinkCrc0;
NvU16 sinkCrc1;
NvU16 sinkCrc2;
} sinkDscCrc;
typedef struct
{
NvBool bSourceControlModeSupported;
NvBool bConcurrentLTSupported;
NvU8 maxTmdsClkRate;
NvU8 maxBpc;
NvU8 maxHdmiLinkBandwidthGbps;
} PCONCaps;
typedef enum
{
PCON_HDMI_LINK_BW_FRL_9GBPS = 0,
PCON_HDMI_LINK_BW_FRL_18GBPS,
PCON_HDMI_LINK_BW_FRL_24GBPS,
PCON_HDMI_LINK_BW_FRL_32GBPS,
PCON_HDMI_LINK_BW_FRL_40GBPS,
PCON_HDMI_LINK_BW_FRL_48GBPS,
PCON_HDMI_LINK_BW_FRL_INVALID
} PCONHdmiLinkBw;
typedef enum
{
NV_DP_PCON_CONTROL_STATUS_SUCCESS = 0,
NV_DP_PCON_CONTROL_STATUS_ERROR_TIMEOUT = 0x80000001,
NV_DP_PCON_CONTROL_STATUS_ERROR_FRL_LT_FAILURE = 0x80000002,
NV_DP_PCON_CONTROL_STATUS_ERROR_FRL_NOT_SUPPORTED = 0x80000003,
NV_DP_PCON_CONTROL_STATUS_ERROR_GENERIC = 0x8000000F
} NV_DP_PCON_CONTROL_STATUS;
//
// Poll HDMI-Link Status change and FRL Ready.
// Spec says it should be done in 500ms, we give it 20% extra time:
// 60 times with interval 10ms.
//
#define NV_PCON_SOURCE_CONTROL_MODE_TIMEOUT_THRESHOLD (60)
#define NV_PCON_SOURCE_CONTROL_MODE_TIMEOUT_INTERVAL_MS (10)
//
// Poll HDMI-Link Status change IRQ and Link Status.
// Spec says it should be done in 250ms, we give it 20% extra time:
// 30 times with interval 10ms.
//
#define NV_PCON_FRL_LT_TIMEOUT_THRESHOLD (30)
#define NV_PCON_FRL_LT_TIMEOUT_INTERVAL_MS (10)
typedef struct _PCONLinkControl
{
struct
{
// This struct is being passed in for assessPCONLink I/F
NvU32 bAssessLink : 1;
// Specify if client wants to use src control - set it false DPLib can just do DP LT alone.
// By default it should be true.
NvU32 bSourceControlMode : 1;
// Default is sequential mode, set this to choose concurrent mode
NvU32 bConcurrentMode : 1;
// Default is normal link training mode (stop once FRL-LT succeed).
// Set this to link train all requested FRL Bw in allowedFrlBwMask.
NvU32 bExtendedLTMode : 1;
// Keep PCON links (DP and FRL link) alive
NvU32 bKeepPCONLinkAlive : 1;
// Default DPLib will fallback to autonomous mode and perform DP assessLink.
NvU32 bSkipFallback : 1;
} flags;
// Input: Clients use this to specify the FRL BW PCON should try.
NvU32 frlHdmiBwMask;
struct
{
NV_DP_PCON_CONTROL_STATUS status;
PCONHdmiLinkBw maxFrlBwTrained;
NvU32 trainedFrlBwMask;
} result;
} PCONLinkControl;
static NV_INLINE PCONHdmiLinkBw getMaxFrlBwFromMask(NvU32 frlRateMask)
{
if (frlRateMask == 0)
{
// Nothing is set. Assume TMDS
return PCON_HDMI_LINK_BW_FRL_INVALID;
}
// find highest set bit (destructive operation)
HIGHESTBITIDX_32(frlRateMask);
return (PCONHdmiLinkBw)frlRateMask;
}
/*
EDP VESA PSR defines
*/
// PSR state transitions
typedef enum
{
vesaPsrStatus_Inactive = 0,
vesaPsrStatus_Transition2Active = 1,
vesaPsrStatus_DisplayFromRfb = 2,
vesaPsrStatus_CaptureAndDisplay = 3,
vesaPsrStatus_Transition2Inactive = 4,
vesaPsrStatus_Undefined5 = 5,
vesaPsrStatus_Undefined6 = 6,
vesaPsrStatus_SinkError = 7
} vesaPsrState;
typedef struct VesaPsrConfig
{
NvU8 psrCfgEnable : 1;
NvU8 srcTxEnabledInPsrActive : 1;
NvU8 crcVerifEnabledInPsrActive : 1;
NvU8 frameCaptureSecondActiveFrame : 1;
NvU8 selectiveUpdateOnSecondActiveline : 1;
NvU8 enableHpdIrqOnCrcMismatch : 1;
NvU8 enablePsr2 : 1;
NvU8 reserved : 1;
} vesaPsrConfig;
typedef struct VesaPsrDebugStatus
{
NvBool lastSdpPsrState;
NvBool lastSdpUpdateRfb;
NvBool lastSdpCrcValid;
NvBool lastSdpSuValid;
NvBool lastSdpFirstSURcvd;
NvBool lastSdpLastSURcvd;
NvBool lastSdpYCoordValid;
NvU8 maxResyncFrames;
NvU8 actualResyncFrames;
} vesaPsrDebugStatus;
typedef struct VesaPsrErrorStatus
{
NvU8 linkCrcError : 1;
NvU8 rfbStoreError : 1;
NvU8 vscSdpError : 1;
NvU8 rsvd : 5;
} vesaPsrErrorStatus;
typedef struct VesaPsrEventIndicator
{
NvU8 sinkCapChange : 1;
NvU8 rsvd : 7;
} vesaPsrEventIndicator;
#pragma pack(1)
typedef struct VesaPsrSinkCaps
{
NvU8 psrVersion;
NvU8 linkTrainingRequired : 1;
NvU8 psrSetupTime : 3;
NvU8 yCoordinateRequired : 1;
NvU8 psr2UpdateGranularityRequired : 1;
NvU8 reserved : 2;
NvU16 suXGranularity;
NvU8 suYGranularity;
} vesaPsrSinkCaps;
#pragma pack()
typedef struct PanelReplayCaps
{
NvBool panelReplaySupported;
} panelReplayCaps;
typedef struct PanelReplayConfig
{
NvBool enablePanelReplay;
} panelReplayConfig;
// Multiplier constant to get link frequency in KHZ
// Maximum link rate of Main Link lanes = Value x 270M.
// To get it to KHz unit, we need to multiply 270K.
#define DP_LINK_BW_FREQUENCY_MULTIPLIER_KHZ (270*1000)
// Multiplier constant to get link rate table's in KHZ
#define DP_LINK_RATE_TABLE_MULTIPLIER_KHZ 200
//
// Multiplier constant to get link frequency (multiplier of 270MHz) in MBps
// a * 270 * 1000 * 1000(270Mhz) * (8 / 10)(8b/10b) / 8(Byte)
// = a * 27000000
//
#define DP_LINK_BW_FREQ_MULTI_MBPS 27000000
//
// Get link rate in multiplier of 270MHz from KHz:
// a * 1000(KHz) / 270 * 1000 * 1000(270Mhz)
//
#define LINK_RATE_KHZ_TO_MULTP(a) ((a) / 270000)
//
// Get link rate in MBps from KHz:
// a * 1000 * (8 / 10)(8b/10b) / 8(Byte)
// = a * 100
//
#define LINK_RATE_KHZ_TO_MBPS(a) ((a) * 100)
#define DP_MAX_LANES 8 // This defines the maximum number of lanes supported on a chip.
#define DP_MAX_LANES_PER_LINK 4 // This defines the maximum number of lanes per link in a chip.
#define DP_AUX_CHANNEL_MAX_BYTES 16
#define DP_CLOCK_RECOVERY_TOT_TRIES 10
#define DP_CLOCK_RECOVERY_MAX_TRIES 5
#define DP_CH_EQ_MAX_RETRIES 5
#define DP_LT_MAX_FOR_MST_MAX_RETRIES 3
#define DP_READ_EDID_MAX_RETRIES 7
#define DP_AUX_CHANNEL_DEFAULT_DEFER_MAX_TRIES 7
#define DP_AUX_CHANNEL_TIMEOUT_MAX_TRIES 2
#define DP_SET_POWER_D0_NORMAL_MAX_TRIES 3
#define DP_SW_AUTO_READ_REQ_SIZE 6
#define NV_DP_RBR_FALLBACK_MAX_TRIES 3
#define DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_DEFAULT_MS 1
#define DP_AUX_CHANNEL_TIMEOUT_WAITIDLE 400 // source is required to wait at least 400us before it considers the AUX transaction to have timed out.
#define DP_AUX_CHANNEL_TIMEOUT_VALUE_DEFAULT 400
#define DP_AUX_CHANNEL_TIMEOUT_VALUE_MAX 3200
#define DP_PHY_REPEATER_INDEX_FOR_SINK 0xFFFFFFFF
#define DP_MESSAGEBOX_SIZE 48
#define DP_POST_LT_ADJ_REQ_LIMIT 6
#define DP_POST_LT_ADJ_REQ_TIMER 200000
#define DP_AUX_HYBRID_TIMEOUT 600
#define DP_AUX_SEMA_ACQUIRE_TIMEOUT 20000
#define DP_CONFIG_WATERMARK_ADJUST 2
#define DP_CONFIG_WATERMARK_LIMIT 20
#define DP_CONFIG_INCREASED_WATERMARK_ADJUST 8
#define DP_CONFIG_INCREASED_WATERMARK_LIMIT 22
#define NV_DP_MSA_PROPERTIES_MISC1_STEREO 2:1
#define DP_LANE_STATUS_ARRAY_SIZE ((displayPort_LaneSupported + 1) / 2)
#define DP_LANE_STATUS_ARRAY_INDEX(lane) ((lane) < displayPort_LaneSupported ? ((lane) / 2) : 0)
#define IS_VALID_LANECOUNT(val) (((NvU32)(val)==0) || ((NvU32)(val)==1) || \
((NvU32)(val)==2) || ((NvU32)(val)==4) || \
((NvU32)(val)==8))
#define IS_STANDARD_LINKBW(val) (((NvU32)(val)==linkBW_1_62Gbps) || \
((NvU32)(val)==linkBW_2_70Gbps) || \
((NvU32)(val)==linkBW_5_40Gbps) || \
((NvU32)(val)==linkBW_8_10Gbps))
#define IS_INTERMEDIATE_LINKBW(val) (((NvU32)(val)==linkBW_2_16Gbps) || \
((NvU32)(val)==linkBW_2_43Gbps) || \
((NvU32)(val)==linkBW_3_24Gbps) || \
((NvU32)(val)==linkBW_4_32Gbps))
#define IS_VALID_LINKBW(val) (IS_STANDARD_LINKBW(val) || \
IS_INTERMEDIATE_LINKBW(val))
//
// Phy Repeater count read from DPCD offset F0002h is an
// 8 bit value where each bit represents the total count
// 80h = 1 repeater, 40h = 2 , 20h = 3 ... 01h = 8
// This function maps it to decimal system
//
static NV_INLINE NvU32 mapPhyRepeaterVal(NvU32 value)
{
switch (value)
{
case NV_DPCD14_PHY_REPEATER_CNT_VAL_0:
return 0;
case NV_DPCD14_PHY_REPEATER_CNT_VAL_1:
return 1;
case NV_DPCD14_PHY_REPEATER_CNT_VAL_2:
return 2;
case NV_DPCD14_PHY_REPEATER_CNT_VAL_3:
return 3;
case NV_DPCD14_PHY_REPEATER_CNT_VAL_4:
return 4;
case NV_DPCD14_PHY_REPEATER_CNT_VAL_5:
return 5;
case NV_DPCD14_PHY_REPEATER_CNT_VAL_6:
return 6;
case NV_DPCD14_PHY_REPEATER_CNT_VAL_7:
return 7;
case NV_DPCD14_PHY_REPEATER_CNT_VAL_8:
return 8;
default:
return 0;
}
}
// HDCP specific definitions
#define HDCP22_RTX_SIMPLE_PATTERN 0x12345678
#define HDCP22_TX_CAPS_PATTERN_BIG_ENDIAN {0x02, 0x00, 0x00}
#define DP_MST_HEAD_TO_STREAMID(head, pipeId, numHeads) ((head) + 1 + (pipeId) * (numHeads))
#define DP_MST_STREAMID_TO_HEAD(streamid, pipeId, numHeads) ((streamid) - 1 - ((pipeId) * (numHeads)))
#define DP_MST_STREAMID_TO_PIPE(streamid, head, numHeads) (((streamid) - (head) - 1) / (numHeads))
typedef enum
{
NV_DP_SBMSG_REQUEST_ID_GET_MESSAGE_TRANSACTION_VERSION = 0x00,
NV_DP_SBMSG_REQUEST_ID_LINK_ADDRESS = 0x01,
NV_DP_SBMSG_REQUEST_ID_CONNECTION_STATUS_NOTIFY = 0x02,
NV_DP_SBMSG_REQUEST_ID_ENUM_PATH_RESOURCES = 0x10,
NV_DP_SBMSG_REQUEST_ID_ALLOCATE_PAYLOAD = 0x11,
NV_DP_SBMSG_REQUEST_ID_QUERY_PAYLOAD = 0x12,
NV_DP_SBMSG_REQUEST_ID_RESOURCE_STATUS_NOTIFY = 0x13,
NV_DP_SBMSG_REQUEST_ID_CLEAR_PAYLOAD_ID_TABLE = 0x14,
NV_DP_SBMSG_REQUEST_ID_REMOTE_DPCD_READ = 0x20,
NV_DP_SBMSG_REQUEST_ID_REMOTE_DPCD_WRITE = 0x21,
NV_DP_SBMSG_REQUEST_ID_REMOTE_I2C_READ = 0x22,
NV_DP_SBMSG_REQUEST_ID_REMOTE_I2C_WRITE = 0x23,
NV_DP_SBMSG_REQUEST_ID_POWER_UP_PHY = 0x24,
NV_DP_SBMSG_REQUEST_ID_POWER_DOWN_PHY = 0x25,
NV_DP_SBMSG_REQUEST_ID_SINK_EVENT_NOTIFY = 0x30,
NV_DP_SBMSG_REQUEST_ID_QUERY_STREAM_ENCRYPTION_STATUS = 0x38,
NV_DP_SBMSG_REQUEST_ID_UNDEFINED = 0xFF,
} NV_DP_SBMSG_REQUEST_ID;
// FEC
#define NV_DP_FEC_FLAGS_SELECT_ALL 0x7
#define NV_DP_ERROR_COUNTERS_PER_LANE 5
#define NV_DP_MAX_NUM_OF_LANES 4
#define NV_DP_FEC_ERROR_COUNT_INVALID 0xbadf
#define NV_DP_UNCORRECTED_ERROR NV_DP_FEC_UNCORRECTED : NV_DP_FEC_UNCORRECTED
#define NV_DP_CORRECTED_ERROR NV_DP_FEC_CORRECTED : NV_DP_FEC_CORRECTED
#define NV_DP_BIT_ERROR NV_DP_FEC_BIT : NV_DP_FEC_BIT
#define NV_DP_PARITY_BLOCK_ERROR NV_DP_FEC_PARITY_BLOCK : NV_DP_FEC_PARITY_BLOCK
#define NV_DP_PARITY_BIT_ERROR NV_DP_FEC_PARITY_BIT : NV_DP_FEC_PARITY_BIT
#define NV_DP_UNCORRECTED_ERROR_NO 0
#define NV_DP_UNCORRECTED_ERROR_YES 1
#define NV_DP_CORRECTED_ERROR_NO 0
#define NV_DP_CORRECTED_ERROR_YES 1
#define NV_DP_BIT_ERROR_NO 0
#define NV_DP_BIT_ERROR_YES 1
#define NV_DP_PARITY_BLOCK_ERROR_NO 0
#define NV_DP_PARITY_BLOCK_ERROR_YES 1
#define NV_DP_PARITY_BIT_ERROR_NO 0
#define NV_DP_PARITY_BIT_ERROR_YES 1
#endif // #ifndef _DISPLAYPORT_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _DISPLAYPORT14_H_
#define _DISPLAYPORT14_H_
#define NV_DPCD14_EXTEND_CAP_BASE (0x00002200)
#define NV_DPCD14_MAX_LINK_BANDWIDTH (0x00000001) /* R-XUR */
#define NV_DPCD14_MAX_LINK_BANDWIDTH_VAL 7:0 /* R-XUF */
#define NV_DPCD14_MAX_LINK_BANDWIDTH_VAL_8_10_GBPS (0x0000001E) /* R-XUV */
#define NV_DPCD14_MAX_DOWNSPREAD (0x00000003) /* R-XUR */
#define NV_DPCD14_MAX_DOWNSPREAD_TPS4_SUPPORTED 7:7 /* R-XUF */
#define NV_DPCD14_MAX_DOWNSPREAD_TPS4_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_MAX_DOWNSPREAD_TPS4_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_TRAINING_AUX_RD_INTERVAL (0x0000000E) /* R-XUR */
#define NV_DPCD14_TRAINING_AUX_RD_INTERVAL_EXTENDED_RX_CAP 7:7 /* R-XUF */
#define NV_DPCD14_TRAINING_AUX_RD_INTERVAL_EXTENDED_RX_CAP_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_TRAINING_AUX_RD_INTERVAL_EXTENDED_RX_CAP_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SUPPORT (0x00000060) /* R-XUR */
#define NV_DPCD14_DSC_SUPPORT_DSC_SUPPORT 0:0 /* R-XUF */
#define NV_DPCD14_DSC_SUPPORT_DSC_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SUPPORT_DSC_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_ALGORITHM_REVISION (0x00000061) /* R-XUR */
#define NV_DPCD14_DSC_ALGORITHM_REVISION_MAJOR 3:0 /* R-XUF */
#define NV_DPCD14_DSC_ALGORITHM_REVISION_MINOR 7:4 /* R-XUF */
#define NV_DPCD14_DSC_RC_BUFFER_BLOCK (0x00000062) /* R-XUR */
#define NV_DPCD14_DSC_RC_BUFFER_BLOCK_SIZE 1:0 /* R-XUF */
#define NV_DPCD14_DSC_RC_BUFFER_BLOCK_SIZE_1KB (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_RC_BUFFER_BLOCK_SIZE_4KB (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_RC_BUFFER_BLOCK_SIZE_16KB (0x00000002) /* R-XUV */
#define NV_DPCD14_DSC_RC_BUFFER_BLOCK_SIZE_64KB (0x00000003) /* R-XUV */
#define NV_DPCD14_DSC_RC_BUFFER (0x00000063) /* R-XUR */
#define NV_DPCD14_DSC_RC_BUFFER_SIZE 7:0 /* R-XUF */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1 (0x00000064) /* R-XUR */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_1 0:0 /* R-XUF */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_1_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_1_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_2 1:1 /* R-XUF */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_2_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_2_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_4 3:3 /* R-XUF */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_4_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_4_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_6 4:4 /* R-XUF */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_6_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_6_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_8 5:5 /* R-XUF */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_8_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_8_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_10 6:6 /* R-XUF */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_10_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_10_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_12 7:7 /* R-XUF */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_12_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_1_SLICES_PER_SINK_12_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_LINE_BUFFER (0x00000065) /* R-XUR */
#define NV_DPCD14_DSC_LINE_BUFFER_BIT_DEPTH 3:0 /* R-XUF */
#define NV_DPCD14_DSC_LINE_BUFFER_BIT_DEPTH_9 (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_LINE_BUFFER_BIT_DEPTH_10 (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_LINE_BUFFER_BIT_DEPTH_11 (0x00000002) /* R-XUV */
#define NV_DPCD14_DSC_LINE_BUFFER_BIT_DEPTH_12 (0x00000003) /* R-XUV */
#define NV_DPCD14_DSC_LINE_BUFFER_BIT_DEPTH_13 (0x00000004) /* R-XUV */
#define NV_DPCD14_DSC_LINE_BUFFER_BIT_DEPTH_14 (0x00000005) /* R-XUV */
#define NV_DPCD14_DSC_LINE_BUFFER_BIT_DEPTH_15 (0x00000006) /* R-XUV */
#define NV_DPCD14_DSC_LINE_BUFFER_BIT_DEPTH_16 (0x00000007) /* R-XUV */
#define NV_DPCD14_DSC_LINE_BUFFER_BIT_DEPTH_8 (0x00000008) /* R-XUV */
#define NV_DPCD14_DSC_BLOCK_PREDICTION (0x00000066) /* R-XUR */
#define NV_DPCD14_DSC_BLOCK_PREDICTION_SUPPORT 0:0 /* R-XUF */
#define NV_DPCD14_DSC_BLOCK_PREDICTION_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_BLOCK_PREDICTION_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_MAXIMUM_BITS_PER_PIXEL_1 (0x00000067) /* R-XUR */
#define NV_DPCD14_DSC_MAXIMUM_BITS_PER_PIXEL_1_LSB 7:0 /* R-XUF */
#define NV_DPCD14_DSC_MAXIMUM_BITS_PER_PIXEL_2 (0x00000068) /* R-XUR */
#define NV_DPCD14_DSC_MAXIMUM_BITS_PER_PIXEL_2_MSB 1:0 /* R-XUF */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES (0x00000069) /* R-XUR */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_RGB 0:0 /* R-XUF */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_RGB_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_RGB_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_YCbCr_444 1:1 /* R-XUF */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_YCbCr_444_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_YCbCr_444_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_YCbCr_SIMPLE_422 2:2 /* R-XUF */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_YCbCr_SIMPLE_422_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_YCbCr_SIMPLE_422_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_YCbCr_NATIVE_422 3:3 /* R-XUF */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_YCbCr_NATIVE_422_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_YCbCr_NATIVE_422_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_YCbCr_NATIVE_420 4:4 /* R-XUF */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_YCbCr_NATIVE_420_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_FORMAT_CAPABILITIES_YCbCr_NATIVE_420_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_DEPTH_CAPABILITIES (0x0000006A) /* R-XUR */
#define NV_DPCD14_DSC_DECODER_COLOR_DEPTH_CAPABILITIES_8_BITS_PER_COLOR 1:1 /* R-XUF */
#define NV_DPCD14_DSC_DECODER_COLOR_DEPTH_CAPABILITIES_8_BITS_PER_COLOR_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_DEPTH_CAPABILITIES_8_BITS_PER_COLOR_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_DEPTH_CAPABILITIES_10_BITS_PER_COLOR 2:2 /* R-XUF */
#define NV_DPCD14_DSC_DECODER_COLOR_DEPTH_CAPABILITIES_10_BITS_PER_COLOR_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_DEPTH_CAPABILITIES_10_BITS_PER_COLOR_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_DEPTH_CAPABILITIES_12_BITS_PER_COLOR 3:3 /* R-XUF */
#define NV_DPCD14_DSC_DECODER_COLOR_DEPTH_CAPABILITIES_12_BITS_PER_COLOR_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_DECODER_COLOR_DEPTH_CAPABILITIES_12_BITS_PER_COLOR_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT (0x0000006B) /* R-XUR */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0 3:0 /* R-XUF */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_340 (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_400 (0x00000002) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_450 (0x00000003) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_500 (0x00000004) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_550 (0x00000005) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_600 (0x00000006) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_650 (0x00000007) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_700 (0x00000008) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_750 (0x00000009) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_800 (0x0000000A) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_850 (0x0000000B) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_900 (0x0000000C) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_950 (0x0000000D) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE0_1000 (0x0000000E) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1 7:4 /* R-XUF */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_340 (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_400 (0x00000002) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_450 (0x00000003) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_500 (0x00000004) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_550 (0x00000005) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_600 (0x00000006) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_650 (0x00000007) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_700 (0x00000008) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_750 (0x00000009) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_800 (0x0000000A) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_850 (0x0000000B) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_900 (0x0000000C) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_950 (0x0000000D) /* R-XUV */
#define NV_DPCD14_DSC_PEAK_THROUGHPUT_MODE1_1000 (0x0000000E) /* R-XUV */
#define NV_DPCD14_DSC_MAXIMUM_SLICE_WIDTH (0x0000006C) /* R-XUR */
#define NV_DPCD14_DSC_MAXIMUM_SLICE_WIDTH_MAX 7:0 /* R-XUF */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_2 (0x0000006D) /* R-XUR */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_2_SLICES_PER_SINK_16 0:0 /* R-XUF */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_2_SLICES_PER_SINK_16_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_2_SLICES_PER_SINK_16_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_2_SLICES_PER_SINK_20 1:1 /* R-XUF */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_2_SLICES_PER_SINK_20_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_2_SLICES_PER_SINK_20_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_2_SLICES_PER_SINK_24 2:2 /* R-XUF */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_2_SLICES_PER_SINK_24_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_SLICE_CAPABILITIES_2_SLICES_PER_SINK_24_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT (0x0000006F) /* R-XUR */
#define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED 2:0 /* R-XUF */
#define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED_1_16 (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED_1_8 (0x00000001) /* R-XUV */
#define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED_1_4 (0x00000002) /* R-XUV */
#define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED_1_2 (0x00000003) /* R-XUV */
#define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED_1 (0x00000004) /* R-XUV */
// Field definition only used only with 128b/132b for DP2.0+
#define NV_DPCD20_TRAINING_LANE_SET(i) (0x00000103+(i)) /* RW-1A */
#define NV_DPCD20_TRAINING_LANE_SET__SIZE 4 /* RW--S */
#define NV_DPCD20_TRAINING_LANE_SET_TX_FFE_PRESET_VALUE 3:0 /* RWXUF */
#define NV_DPCD14_DSC_ENABLE (0x00000160) /* R-XUR */
#define NV_DPCD14_DSC_ENABLE_SINK 0:0 /* R-XUF */
#define NV_DPCD14_DSC_ENABLE_SINK_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DSC_ENABLE_SINK_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY (0x00000090) /* R-XUR */
#define NV_DPCD14_FEC_CAPABILITY_FEC_CAPABLE 0:0 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_FEC_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_FEC_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE 1:1 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_CORRECTED_BLOCK_ERROR_COUNT_CAPABLE 2:2 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_CORRECTED_BLOCK_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_CORRECTED_BLOCK_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_BIT_ERROR_COUNT_CAPABLE 3:3 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_BIT_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_BIT_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_PARITY_BLOCK_ERROR_COUNT_CAPABLE 4:4 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_PARITY_BLOCK_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_PARITY_BLOCK_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_PARITY_ERROR_COUNT_CAPABLE 5:5 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_PARITY_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_PARITY_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */
// Bit 6 : RESERVED. Read 0
#define NV_DPCD14_FEC_CAPABILITY_FEC_ERROR_REPORTING_POLICY_SUPPORTED 7:7 /* R-XUF */
#define NV_DPCD14_FEC_CAPABILITY_FEC_ERROR_REPORTING_POLICY_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_CAPABILITY_FEC_ERROR_REPORTING_POLICY_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_TRAINING_PATTERN_SET (0x00000102) /* RWXUR */
#define NV_DPCD14_TRAINING_PATTERN_SET_TPS 3:0 /* RWXUF */
#define NV_DPCD14_TRAINING_PATTERN_SET_TPS_NONE (0x00000000) /* RWXUV */
#define NV_DPCD14_TRAINING_PATTERN_SET_TPS_TP1 (0x00000001) /* RWXUV */
#define NV_DPCD14_TRAINING_PATTERN_SET_TPS_TP2 (0x00000002) /* RWXUV */
#define NV_DPCD14_TRAINING_PATTERN_SET_TPS_TP3 (0x00000003) /* RWXUV */
#define NV_DPCD14_TRAINING_PATTERN_SET_TPS_TP4 (0x00000007) /* RWXUV */
#define NV_DPCD14_TRAINING_PATTERN_SET_RECOVERED_CLOCK_OUT_EN 4:4 /* RWXUF */
#define NV_DPCD14_TRAINING_PATTERN_SET_RECOVERED_CLOCK_OUT_EN_NO (0x00000000) /* RWXUV */
#define NV_DPCD14_TRAINING_PATTERN_SET_RECOVERED_CLOCK_OUT_EN_YES (0x00000001) /* RWXUV */
#define NV_DPCD14_TRAINING_PATTERN_SET_SCRAMBLING_DISABLED 5:5 /* RWXUF */
#define NV_DPCD14_TRAINING_PATTERN_SET_SCRAMBLING_DISABLED_FALSE (0x00000000) /* RWXUV */
#define NV_DPCD14_TRAINING_PATTERN_SET_SCRAMBLING_DISABLED_TRUE (0x00000001) /* RWXUV */
#define NV_DPCD14_TRAINING_PATTERN_SET_SYM_ERR_SEL 7:6 /* RWXUF */
#define NV_DPCD14_TRAINING_PATTERN_SET_SYM_ERR_SEL_DISPARITY_ILLEGAL_SYMBOL_ERROR (0x00000000) /* RWXUV */
#define NV_DPCD14_TRAINING_PATTERN_SET_SYM_ERR_SEL_DISPARITY_ERROR (0x00000001) /* RWXUV */
#define NV_DPCD14_TRAINING_PATTERN_SET_SYM_ERR_SEL_ILLEGAL_SYMBOL_ERROR (0x00000002) /* RWXUV */
// Field definition only used only with 128b/132b for DP2.0+
#define NV_DPCD20_128B_132B_TRAINING_PATTERN (0x00000102) /* RWXUR */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT 3:0 /* RWXUF */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_NONE (0x00000000) /* RWXUV */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS1 (0x00000001) /* RWXUV */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS2 (0x00000002) /* RWXUV */
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS2_CDS (0x00000003) /* RWXUV */
// Note: Bit 7:4 are reserved for 128b/132b. Driver should keep them 0
#define NV_DPCD14_LINK_QUAL_LANE_SET(i) (0x0000010B+(i)) /* RW-1A */
#define NV_DPCD14_LINK_QUAL_LANE_SET__SIZE 4 /* R---S */
#define NV_DPCD14_LINK_QUAL_LANE_SET_LQS 2:0 /* RWXUF */
#define NV_DPCD14_LINK_QUAL_LANE_SET_LQS_CP2520PAT3 (0x00000007) /* RWXUV */
#define NV_DPCD14_FEC_CONFIGURATION (0x00000120) /* RWXUR */
#define NV_DPCD14_FEC_CONFIGURATION_FEC_READY 0:0 /* RWXUF */
#define NV_DPCD14_FEC_CONFIGURATION_FEC_READY_NO (0x00000000) /* RWXUV */
#define NV_DPCD14_FEC_CONFIGURATION_FEC_READY_YES (0x00000001) /* RWXUV */
#define NV_DPCD14_FEC_CONFIGURATION_FEC_ERROR_COUNT_SEL 3:1 /* RWXUF */
#define NV_DPCD14_FEC_CONFIGURATION_FEC_ERROR_COUNT_SEL_FEC_ERROR_COUNT_DIS (0x00000000) /* RWXUV */
#define NV_DPCD14_FEC_CONFIGURATION_FEC_ERROR_COUNT_SEL_UNCORRECTED_BLOCK_ERROR_COUNT (0x00000001) /* RWXUV */
#define NV_DPCD14_FEC_CONFIGURATION_FEC_ERROR_COUNT_SEL_CORRECTED_BLOCK_ERROR_COUNT (0x00000002) /* RWXUV */
#define NV_DPCD14_FEC_CONFIGURATION_FEC_ERROR_COUNT_SEL_BIT_ERROR_COUNT (0x00000003) /* RWXUV */
#define NV_DPCD14_FEC_CONFIGURATION_FEC_ERROR_COUNT_SEL_PARITY_BLOCK_ERROR_COUNT (0x00000004) /* RWXUV */
#define NV_DPCD14_FEC_CONFIGURATION_FEC_ERROR_COUNT_SEL_PARITY_BIT_ERROR_COUNT (0x00000005) /* RWXUV */
#define NV_DPCD14_FEC_CONFIGURATION_LANE_SELECT 5:4 /* RWXUF */
#define NV_DPCD14_FEC_CONFIGURATION_LANE_SELECT_LANE_0 (0x00000000) /* RWXUV */
#define NV_DPCD14_FEC_CONFIGURATION_LANE_SELECT_LANE_1 (0x00000001) /* RWXUV */
#define NV_DPCD14_FEC_CONFIGURATION_LANE_SELECT_LANE_2 (0x00000002) /* RWXUV */
#define NV_DPCD14_FEC_CONFIGURATION_LANE_SELECT_LANE_3 (0x00000003) /* RWXUV */
// Field definition only used only with 128b/132b for DP2.0+
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED (0x00000204) /* R-XUR */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE 3:3 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED 4:4 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */
// Field definition for 0x0206/0x0207h (ADJUST_REQUEST_LANEX), only used only with 128b/132b for DP2.0+
#define NV_DPCD20_LANEX_XPLUS1_ADJUST_REQ_LANEX_TX_FFE_PRESET_VALUE 3:0 /* R-XUF */
#define NV_DPCD20_LANEX_XPLUS1_ADJUST_REQ_LANEXPLUS1_TX_FFE_PRESET_VALUE 7:4 /* R-XUF */
// PANEL REPLAY RELATED DPCD
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY (0x000000B0)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED 0:0
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE 1:1
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION (0x000001B0)
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE 0:0
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001)
#define NV_DPCD14_PHY_TEST_PATTERN (0x00000248) /* R-XUR */
#define NV_DPCD14_PHY_TEST_PATTERN_SEL_CP2520PAT3 (0x00000007) /* R-XUV */
#define NV_DPCD14_DSC_CRC_0 (0x00000262) /* R-XUR */
#define NV_DPCD14_DSC_CRC_0_LOW_BYTE NV_DPCD14_DSC_CRC_0
#define NV_DPCD14_DSC_CRC_0_HIGH_BYTE (0x00000263) /* R-XUR */
#define NV_DPCD14_DSC_CRC_1 (0x00000264) /* R-XUR */
#define NV_DPCD14_DSC_CRC_1_LOW_BYTE NV_DPCD14_DSC_CRC_1
#define NV_DPCD14_DSC_CRC_1_HIGH_BYTE (0x00000265) /* R-XUR */
#define NV_DPCD14_DSC_CRC_2 (0x00000266) /* R-XUR */
#define NV_DPCD14_DSC_CRC_2_LOW_BYTE NV_DPCD14_DSC_CRC_2
#define NV_DPCD14_DSC_CRC_2_HIGH_BYTE (0x00000267) /* R-XUR */
#define NV_DPCD14_FEC_STATUS (0x00000280) /* R-XUR */
#define NV_DPCD14_FEC_STATUS_FEC_DECODE_EN_DETECTED 0:0 /* R-XUF */
#define NV_DPCD14_FEC_STATUS_FEC_DECODE_EN_DETECTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_STATUS_FEC_DECODE_EN_DETECTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_FEC_STATUS_FEC_DECODE_DIS_DETECTED 1:1 /* R-XUF */
#define NV_DPCD14_FEC_STATUS_FEC_DECODE_DIS_DETECTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_STATUS_FEC_DECODE_DIS_DETECTED_YES (0x00000001) /* R-XUV */
// Bits 7-2: RESERVED.
#define NV_DPCD14_FEC_STATUS_CLEAR (0x00000001)
#define NV_DPCD14_FEC_ERROR_COUNT (0x00000281) /* R-XUR */
#define NV_DPCD14_FEC_ERROR_COUNT_FEC_ERROR_COUNT_LOW_BYTE NV_DPCD14_FEC_ERROR_COUNT
#define NV_DPCD14_FEC_ERROR_COUNT_FEC_ERROR_COUNT_HIGH_BYTE (0x00000282) /* R-XUR */
#define NV_DPCD14_FEC_ERROR_COUNT_FEC_ERROR_COUNT_VALID 7:7 /* R-XUF */
#define NV_DPCD14_FEC_ERROR_COUNT_FEC_ERROR_COUNT_VALID_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_ERROR_COUNT_FEC_ERROR_COUNT_VALID_YES (0x00000001) /* R-XUV */
// Field definition for 0x0200E (LANE_ALIGN_STATUS_UPDATED_ESI), used only when DP2.0+ 128b/132b is enabled.
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI (0x0000200E) /* R-XUR */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE 3:3 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED 4:4 /* R-XUF */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */
// Field definition for 0x0200F (SINK_STATUS_ESI), used only when DP2.0+ 128b/132b is enabled.
#define NV_DPCD20_SINK_STATUS_ESI (0x0000200F) /* R-XUR */
#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY 3:3 /* R-XUF */
#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY_DPRX (0x00000000) /* R-XUV */
#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY_LTTPR (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_REV (0x00002200) /* R-XUR */
#define NV_DPCD14_EXTENDED_REV_MAJOR 7:4 /* R-XUF */
#define NV_DPCD14_EXTENDED_REV_MAJOR_1 (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_REV_MINOR 3:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_REV_MINOR_4 (0x00000004) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_LINK_BANDWIDTH (0x00002201) /* R-XUR */
#define NV_DPCD14_EXTENDED_MAX_LINK_BANDWIDTH_VAL 7:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_MAX_LINK_BANDWIDTH_VAL_8_10_GBPS (0x0000001E) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT (0x00002202) /* R-XUR */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_LANE 4:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_LANE_1 (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_LANE_2 (0x00000002) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_LANE_4 (0x00000004) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_POST_LT_ADJ_REQ_SUPPORT 5:5 /* R-XUF */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_POST_LT_ADJ_REQ_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_POST_LT_ADJ_REQ_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_TPS3_SUPPORTED 6:6 /* R-XUF */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_TPS3_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_TPS3_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_ENHANCED_FRAMING 7:7 /* R-XUF */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_ENHANCED_FRAMING_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_DOWNSPREAD (0x00002203) /* R-XUR */
#define NV_DPCD14_EXTENDED_MAX_DOWNSPREAD_VAL 0:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_MAX_DOWNSPREAD_VAL_NONE (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_DOWNSPREAD_VAL_0_5_PCT (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT 6:6 /* R-XUF */
#define NV_DPCD14_EXTENDED_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_FALSE (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_TRUE (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_DOWNSPREAD_TPS4_SUPPORTED 7:7 /* R-XUF */
#define NV_DPCD14_EXTENDED_MAX_DOWNSPREAD_TPS4_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAX_DOWNSPREAD_TPS4_SUPPORTED_YES (0x00000001) /* R-XUV */
// NORP = Number of Receiver Ports = Value + 1
#define NV_DPCD14_EXTENDED_NORP (0x00002204) /* R-XUR */
#define NV_DPCD14_EXTENDED_NORP_VAL 0:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_NORP_VAL_ONE (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_NORP_VAL_TWO (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_NORP_VAL_SST_MAX (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_NORP_DP_PWR_CAP_5V 5:5 /* R-XUF */
#define NV_DPCD14_EXTENDED_NORP_DP_PWR_CAP_12V 6:6 /* R-XUF */
#define NV_DPCD14_EXTENDED_NORP_DP_PWR_CAP_18V 7:7 /* R-XUF */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT (0x00002205) /* R-XUR */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_PRESENT 0:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_PRESENT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_PRESENT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_TYPE 2:1 /* R-XUF */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_TYPE_DISPLAYPORT (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_TYPE_ANALOG (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_TYPE_HDMI_DVI (0x00000002) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_TYPE_OTHERS (0x00000003) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_FORMAT_CONVERSION 3:3 /* R-XUF */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_FORMAT_CONVERSION_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_FORMAT_CONVERSION_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_DETAILED_CAP_INFO_AVAILABLE 4:4 /* R-XUF */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_DETAILED_CAP_INFO_AVAILABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWNSTREAMPORT_DETAILED_CAP_INFO_AVAILABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING (0x00002206) /* R-XUR */
#define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B 0:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B 1:1 /* R-XUF */
#define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWN_STREAM_PORT (0x00002207) /* R-XUR */
#define NV_DPCD14_EXTENDED_DOWN_STREAM_PORT_COUNT 3:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_DOWN_STREAM_PORT_MSA_TIMING_PAR_IGNORED 6:6 /* R-XUF */
#define NV_DPCD14_EXTENDED_DOWN_STREAM_PORT_MSA_TIMING_PAR_IGNORED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWN_STREAM_PORT_MSA_TIMING_PAR_IGNORED_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWN_STREAM_PORT_OUI_SUPPORT 7:7 /* R-XUF */
#define NV_DPCD14_EXTENDED_DOWN_STREAM_PORT_OUI_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DOWN_STREAM_PORT_OUI_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_RECEIVE_PORT0_CAP_0 (0x00002208) /* R-XUR */
#define NV_DPCD14_EXTENDED_RECEIVE_PORT1_CAP_0 (0x0000220A) /* R-XUR */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_LOCAL_EDID 1:1 /* R-XUF */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_LOCAL_EDID_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_LOCAL_EDID_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_ASSO_TO_PRECEDING_PORT 2:2 /* R-XUF */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_ASSO_TO_PRECEDING_PORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_ASSO_TO_PRECEDING_PORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_HBLANK_EXPANSION_CAPABLE 3:3 /* R-XUF */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_HBLANK_EXPANSION_CAPABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_HBLANK_EXPANSION_CAPABLE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_BUFFER_SIZE_UNIT 4:4 /* R-XUF */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_BUFFER_SIZE_UNIT_PIXEL (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_BUFFER_SIZE_UNIT_BYTE (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_BUFFER_SIZE_PER_PORT 5:5 /* R-XUF */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_BUFFER_SIZE_PER_PORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_0_BUFFER_SIZE_PER_PORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_RECEIVE_PORT0_CAP_1 (0x00002209) /* R-XUR */
#define NV_DPCD14_EXTENDED_RECEIVE_PORT1_CAP_1 (0x0000220B) /* R-XUR */
#define NV_DPCD14_EXTENDED_RECEIVE_PORTX_CAP_1_BUFFER_SIZE 7:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_I2C_CTRL_CAP (0x0000220C) /* R-XUR */
#define NV_DPCD14_EXTENDED_I2C_CTRL_CAP_SPEED 7:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_I2C_CTRL_CAP_SPEED_1K (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_I2C_CTRL_CAP_SPEED_5K (0x00000002) /* R-XUV */
#define NV_DPCD14_EXTENDED_I2C_CTRL_CAP_SPEED_10K (0x00000004) /* R-XUV */
#define NV_DPCD14_EXTENDED_I2C_CTRL_CAP_SPEED_100K (0x00000008) /* R-XUV */
#define NV_DPCD14_EXTENDED_I2C_CTRL_CAP_SPEED_400K (0x00000010) /* R-XUV */
#define NV_DPCD14_EXTENDED_I2C_CTRL_CAP_SPEED_1M (0x00000020) /* R-XUV */
#define NV_DPCD14_EXTENDED_EDP_CONFIG_CAP (0x0000220D) /* R-XUR */
#define NV_DPCD14_EXTENDED_EDP_CONFIG_CAP_ALTERNATE_SCRAMBLER_RESET 0:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_EDP_CONFIG_CAP_ALTERNATE_SCRAMBLER_RESET_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_EDP_CONFIG_CAP_ALTERNATE_SCRAMBLER_RESET_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_TRAINING_AUX_RD_INTERVAL (0x0000220E) /* R-XUR */
#define NV_DPCD14_EXTENDED_TRAINING_AUX_RD_INTERVAL_VAL 6:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_TRAINING_AUX_RD_INTERVAL_VAL_DEFAULT (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_TRAINING_AUX_RD_INTERVAL_VAL_4MS (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_TRAINING_AUX_RD_INTERVAL_VAL_8MS (0x00000002) /* R-XUV */
#define NV_DPCD14_EXTENDED_TRAINING_AUX_RD_INTERVAL_VAL_12MS (0x00000003) /* R-XUV */
#define NV_DPCD14_EXTENDED_TRAINING_AUX_RD_INTERVAL_VAL_16MS (0x00000004) /* R-XUV */
#define NV_DPCD14_EXTENDED_TRAINING_AUX_RD_INTERVAL_EXTENDED_RECEIVER_CAP 7:7 /* R-XUF */
#define NV_DPCD14_EXTENDED_TRAINING_AUX_RD_INTERVAL_EXTENDED_RECEIVER_CAP_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_TRAINING_AUX_RD_INTERVAL_EXTENDED_RECEIVER_CAP_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_ADAPTER_CAP (0x0000220F) /* R-XUR */
#define NV_DPCD14_EXTENDED_ADAPTER_CAP_FORCE_LOAD_SENSE 0:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_ADAPTER_CAP_FORCE_LOAD_SENSE_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_ADAPTER_CAP_FORCE_LOAD_SENSE_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_ADAPTER_CAP_ALT_I2C_PATTERN 1:1 /* R-XUF */
#define NV_DPCD14_EXTENDED_ADAPTER_CAP_ALT_I2C_PATTERN_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_ADAPTER_CAP_ALT_I2C_PATTERN_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST (0x00002210) /* R-XUR */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_GTC_CAP 0:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_GTC_CAP_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_GTC_CAP_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_AV_SYNC_CAP 2:2 /* R-XUF */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_AV_SYNC_CAP_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_AV_SYNC_CAP_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_SDP_EXT_FOR_COLORIMETRY 3:3 /* R-XUF */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_SDP_EXT_FOR_COLORIMETRY_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_SDP_EXT_FOR_COLORIMETRY_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_EXT_VESA_SDP 4:4 /* R-XUF */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_EXT_VESA_SDP_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_EXT_VESA_SDP_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_EXT_VESA_SDP_CHAINING 5:5 /* R-XUF */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_EXT_VESA_SDP_CHAINING_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_EXT_VESA_SDP_CHAINING_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_EXT_CTA_SDP 6:6 /* R-XUF */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_EXT_CTA_SDP_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_EXT_CTA_SDP_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_EXT_CTA_SDP_CHAINING 7:7 /* R-XUF */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_EXT_CTA_SDP_CHAINING_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_FEATURE_ENUM_LIST_VSC_EXT_CTA_SDP_CHAINING_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST (0x00002211) /* R-XUR */
#define NV_DPCD14_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST_PERIOD 7:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST_PERIOD_1MS (0x00000000) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST_PERIOD_20MS (0x00000001) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST_PERIOD_40MS (0x00000002) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST_PERIOD_60MS (0x00000003) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST_PERIOD_80MS (0x00000004) /* R-XUV */
#define NV_DPCD14_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST_PERIOD_100MS (0x00000005) /* R-XUV */
#define NV_DPCD14_EXTENDED_VSC_EXT_VESA_SDP_MAX_CHAINING (0x00002212) /* R-XUR */
#define NV_DPCD14_EXTENDED_VSC_EXT_VESA_SDP_MAX_CHAINING_VAL 7:0 /* R-XUF */
#define NV_DPCD14_EXTENDED_VSC_EXT_CTA_SDP_MAX_CHAINING (0x00002213) /* R-XUR */
#define NV_DPCD14_EXTENDED_VSC_EXT_CTA_SDP_MAX_CHAINING_VAL 7:0 /* R-XUF */
#define NV_DPCD14_DPRX_FEATURE_ENUM_LIST (0x00002214) /* R-XUR */
#define NV_DPCD14_DPRX_FEATURE_ENUM_LIST_ADAPTIVE_SYNC_SDP_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD14_DPRX_FEATURE_ENUM_LIST_ADAPTIVE_SYNC_SDP_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DPRX_FEATURE_ENUM_LIST_ADAPTIVE_SYNC_SDP_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_DPRX_FEATURE_ENUM_LIST_VSC_EXT_FRAMEWORK_V1_SUPPORTED 4:4 /* R-XUF */
#define NV_DPCD14_DPRX_FEATURE_ENUM_LIST_VSC_EXT_FRAMEWORK_V1_SUPPORTED_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_DPRX_FEATURE_ENUM_LIST_VSC_EXT_FRAMEWORK_V1_SUPPORTED_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES (0x00002215) /* R-XUR */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10 0:0 /* R-XUF */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20 1:1 /* R-XUF */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5 2:2 /* R-XUF */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5_YES (0x00000001) /* R-XUV */
//
// The interval is (128b/132b_TRAINING_AUX_RD_INTERVAL value + 1) * INTERVAL_UNIT.
// The maximum is 256 ms.
//
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL (0x00002216) /* R-XUR */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_VAL 6:0 /* R-XUF */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT 7:7 /* R-XUF */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT_2MS (0x00000000) /* R-XUV */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT_1MS (0x00000001) /* R-XUV */
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_MAX_MS 256
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS (0x00003036) /* R-XUR */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_MODE 0:0 /* R-XUF */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_MODE_TMDS (0x00000000) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_MODE_FRL (0x00000001) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RESULT 6:1 /* R-XUF */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G 1:1 /* R-XUF */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_9G_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G 2:2 /* R-XUF */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_18G_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G 3:3 /* R-XUF */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_24G_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G 4:4 /* R-XUF */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_32G_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G 5:5 /* R-XUF */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_40G_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G 6:6 /* R-XUF */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_LINK_CONFIG_STATUS_LT_RES_48G_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE(i) (0x00003037+(i)) /* RW-1A */
#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE__SIZE 4 /* R---S */
#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT 3:0 /* R-XUF */
#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_ZERO (0x00000000) /* R-XUV */
#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_THREE (0x00000001) /* R-XUV */
#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_TEN (0x00000002) /* R-XUV */
#define NV_DPCD20_PCON_DOWNSTREAM_LINK_ERROR_LANE_COUNT_HUNDRED (0x00000004) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS (0x0000303B) /* R-XUR */
#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE 0:0 /* R-XUF */
#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_ACTIVE_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_READY 1:1 /* R-XUF */
#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_READY_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_PCON_HDMI_TX_LINK_STATUS_LINK_READY_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_PCON_CONTROL_0 (0x00003050) /* RWXUR */
#define NV_DPCD20_PCON_CONTROL_0_OUTPUT_CONFIG 0:0 /* RWXUF */
#define NV_DPCD20_PCON_CONTROL_0_OUTPUT_CONFIG_DVI (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_0_OUTPUT_CONFIG_HDMI (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_1 (0x00003051) /* RWXUR */
#define NV_DPCD20_PCON_CONTROL_1_CONVERT_YCBCR420 0:0 /* RWXUF */
#define NV_DPCD20_PCON_CONTROL_1_CONVERT_YCBCR420_DISABLE (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_1_CONVERT_YCBCR420_ENABLE (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS 1:1 /* RWXUF */
#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS_NO (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_EDID_PROCESS_YES (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING 2:2 /* RWXUF */
#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING_NO (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_AUTO_SCRAMBLING_YES (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING 3:3 /* RWXUF */
#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING_NO (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_1_DISABLE_HDMI_FORCE_SCRAMBLING_YES (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_2 (0x00003052) /* RWXUR */
#define NV_DPCD20_PCON_CONTROL_2_CONVERT_YCBCR422 0:0 /* RWXUF */
#define NV_DPCD20_PCON_CONTROL_2_CONVERT_YCBCR422_DISABLE (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_2_CONVERT_YCBCR422_ENABLE (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_3 (0x00003053) /* RWXUR */
#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH 1:0 /* RWXUF */
#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_SAME_AS_INC (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_8BPC (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_10BPC (0x00000002) /* RWXUV */
#define NV_DPCD20_PCON_CONTROL_3_COMPONENT_BIT_DEPTH_12BPC (0x00000003) /* RWXUV */
#define NV_DPCD14_OUTPUT_HTOTAL_LOW (0x00003054) /* RWXUR */
#define NV_DPCD14_OUTPUT_HTOTAL_HIGH (0x00003055) /* RWXUR */
#define NV_DPCD14_OUTPUT_HSTART_LOW (0x00003056) /* RWXUR */
#define NV_DPCD14_OUTPUT_HSTART_HIGH (0x00003057) /* RWXUR */
#define NV_DPCD14_OUTPUT_HSP_HSW_LOW (0x00003056) /* RWXUR */
#define NV_DPCD14_OUTPUT_HSP_HSW_HIGH (0x00003057) /* RWXUR */
#define NV_DPCD14_OUTPUT_HSP_HSW_HIGH_VAL 6:0 /* RWXUF */
#define NV_DPCD14_OUTPUT_HSP_HSW_HIGH_OUTPUT_HSP 7:7 /* RWXUF */
#define NV_DPCD14_OUTPUT_HSP_HSW_HIGH_OUTPUT_HSP_POSITIVE (0x00000000) /* RWXUV */
#define NV_DPCD14_OUTPUT_HSP_HSW_HIGH_OUTPUT_HSP_NEGATIVE (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1 (0x0000305A) /* RWXUR */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW 2:0 /* RWXUF */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_ZERO (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_9G (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_18G (0x00000002) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_24G (0x00000003) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_32G (0x00000004) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_40G (0x00000005) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_MAX_LINK_BW_48G (0x00000006) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE 3:3 /* RWXUF */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE_DISABLE (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_SRC_CONTROL_MODE_ENABLE (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE 4:4 /* RWXUF */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE_DISABLE (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_CONCURRENT_LT_MODE_ENABLE (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE 5:5 /* RWXUF */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE_DISABLE (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_LINK_FRL_MODE_ENABLE (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE 6:6 /* RWXUF */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE_DISABLE (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_IRQ_LINK_FRL_MODE_ENABLE (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_HDMI_LINK 7:7 /* RWXUF */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_HDMI_LINK_DISABLE (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_1_HDMI_LINK_ENABLE (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2 (0x0000305B) /* RWXUR */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK 5:0 /* RWXUF */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_9G (0x00000001) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_18G (0x00000002) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_24G (0x00000004) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_32G (0x00000008) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_40G (0x00000010) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_LINK_BW_MASK_48G (0x00000020) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL 6:6 /* RWXUF */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL_NORMAL (0x00000000) /* RWXUV */
#define NV_DPCD20_PCON_FRL_LINK_CONFIG_2_FRL_LT_CONTROL_EXTENDED (0x00000001) /* RWXUV */
// LT Tunable Repeater Related offsets
#define NV_DPCD14_LT_TUNABLE_PHY_REPEATER_REV (0x000F0000) /* R-XUR */
#define NV_DPCD14_LT_TUNABLE_PHY_REPEATER_REV_MINOR 3:0 /* R-XUF */
#define NV_DPCD14_LT_TUNABLE_PHY_REPEATER_REV_MINOR_0 (0x00000000) /* R-XUV */
#define NV_DPCD14_LT_TUNABLE_PHY_REPEATER_REV_MAJOR 7:4 /* R-XUF */
#define NV_DPCD14_LT_TUNABLE_PHY_REPEATER_REV_MAJOR_1 (0x00000001) /* R-XUV */
#define NV_DPCD14_MAX_LINK_RATE_PHY_REPEATER (0x000F0001) /* R-XUR */
#define NV_DPCD14_MAX_LINK_RATE_PHY_REPEATER_VAL 7:0 /* R-XUF */
#define NV_DPCD14_MAX_LINK_RATE_PHY_REPEATER_VAL_1_62_GBPS (0x00000006) /* R-XUV */
#define NV_DPCD14_MAX_LINK_RATE_PHY_REPEATER_VAL_2_70_GBPS (0x0000000A) /* R-XUV */
#define NV_DPCD14_MAX_LINK_RATE_PHY_REPEATER_VAL_5_40_GBPS (0x00000014) /* R-XUV */
#define NV_DPCD14_MAX_LINK_RATE_PHY_REPEATER_VAL_8_10_GBPS (0x0000001E) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_CNT (0x000F0002) /* R-XUR */
#define NV_DPCD14_PHY_REPEATER_CNT_VAL 7:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_CNT_VAL_0 (0x00000000) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_CNT_VAL_1 (0x00000080) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_CNT_VAL_2 (0x00000040) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_CNT_VAL_3 (0x00000020) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_CNT_VAL_4 (0x00000010) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_CNT_VAL_5 (0x00000008) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_CNT_VAL_6 (0x00000004) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_CNT_VAL_7 (0x00000002) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_CNT_VAL_8 (0x00000001) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_CNT_MAX 8
#define NV_DPCD14_PHY_REPEATER_MODE (0x000F0003) /* R-XUR */
#define NV_DPCD14_PHY_REPEATER_MODE_VAL_TRANSPARENT (0x00000055) /* R-XUV */
#define NV_DPCD14_PHY_REPEATER_MODE_VAL_NON_TRANSPARENT (0x000000AA) /* R-XUV */
#define NV_DPCD14_MAX_LANE_COUNT_PHY_REPEATER (0x000F0004) /* R-XUR */
#define NV_DPCD14_MAX_LANE_COUNT_PHY_REPEATER_VAL 4:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EXTENDED_WAKE_TIMEOUT (0x000F0005) /* RWXUR */
#define NV_DPCD14_PHY_REPEATER_EXTENDED_WAKE_TIMEOUT_REQ 6:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EXTENDED_WAKE_TIMEOUT_GRANT 7:7 /* RWXUF */
#define NV_DPCD14_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING (0x000F0006) /* RWXUR */
#define NV_DPCD14_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED_NO (0x00000000) /* RWXUF */
#define NV_DPCD14_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED_YES (0x00000001) /* RWXUF */
#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES (0x000F0007) /* R-XUR */
#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED 0:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED 1:1 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED 2:2 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE (0x000F0008) /* R-XUR */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR(i) (i):(i) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_0 0:0 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_0_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_0_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_1 1:1 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_1_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_1_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_2 2:2 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_2_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_2_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_3 3:3 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_3_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_3_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_4 4:4 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_4_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_4_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_5 5:5 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_5_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_5_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_6 6:6 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_6_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_6_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_7 7:7 /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_7_NO (0x00000000) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_7_YES (0x00000001) /* R-XUF */
#define NV_DPCD14_PHY_REPEATER_START(i) (0x000F0010+(i)*0x50) /* RW-1A */
#define NV_DPCD14_PHY_REPEATER_START__SIZE 8 /* R---S */
// Following defines are offsets
#define NV_DPCD14_TRAINING_PATTERN_SET_PHY_REPEATER (0x00000000) /* RWXUV */
#define NV_DPCD14_TRAINING_LANE0_SET_PHY_REPEATER (0x00000001) /* RWXUV */
#define NV_DPCD14_TRAINING_LANE1_SET_PHY_REPEATER (0x00000002) /* RWXUV */
#define NV_DPCD14_TRAINING_LANE2_SET_PHY_REPEATER (0x00000003) /* RWXUV */
#define NV_DPCD14_TRAINING_LANE3_SET_PHY_REPEATER (0x00000004) /* RWXUV */
#define NV_DPCD14_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER (0x00000010) /* R-XUR */
#define NV_DPCD14_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER_VAL 6:0 /* R-XUF */
#define NV_DPCD14_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER_VAL_4MS (0x00000001) /* R-XUV */
#define NV_DPCD14_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER_VAL_8MS (0x00000002) /* R-XUV */
#define NV_DPCD14_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER_VAL_12MS (0x00000003) /* R-XUV */
#define NV_DPCD14_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER_VAL_16MS (0x00000004) /* R-XUV */
#define NV_DPCD14_TRANSMITTER_CAP_PHY_REPEATER (0x00000011) /* R-XUR */
#define NV_DPCD14_TRANSMITTER_CAP_PHY_REPEATER_VOLTAGE_SWING_3 0:0 /* R-XUF */
#define NV_DPCD14_TRANSMITTER_CAP_PHY_REPEATER_VOLTAGE_SWING_3_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_TRANSMITTER_CAP_PHY_REPEATER_VOLTAGE_SWING_3_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_TRANSMITTER_CAP_PHY_REPEATER_PRE_EMPHASIS_3 1:1 /* R-XUF */
#define NV_DPCD14_TRANSMITTER_CAP_PHY_REPEATER_PRE_EMPHASIS_3_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_TRANSMITTER_CAP_PHY_REPEATER_PRE_EMPHASIS_3_YES (0x00000001) /* R-XUV */
#define NV_DPCD14_LANE0_1_STATUS_PHY_REPEATER (0x00000020) /* R-XUR */
#define NV_DPCD14_LANE2_3_STATUS_PHY_REPEATER (0x00000021) /* R-XUR */
#define NV_DPCD14_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER (0x00000022) /* R-XUR */
#define NV_DPCD14_ADJUST_REQUEST_LANE0_1_PHY_REPEATER (0x00000023) /* R-XUR */
#define NV_DPCD14_ADJUST_REQUEST_LANE2_3_PHY_REPEATER (0x00000024) /* R-XUR */
#endif // #ifndef _DISPLAYPORT14_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#define NV_DPCD20_DSC_SUPPORT (0x00000060) /* R-XUR */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT 1:1 /* R-XUF */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT_YES (0x00000001) /* R-XUV */
#define NV_DPCD20_DSC_PASS_THROUGH (0x00000160) /* R-XUR */
#define NV_DPCD20_DSC_PASS_THROUGH_ENABLE 1:1 /* R-XUF */
#define NV_DPCD20_DSC_PASS_THROUGH_ENABLE_NO (0x00000000) /* R-XUV */
#define NV_DPCD20_DSC_PASS_THROUGH_ENABLE_YES (0x00000001) /* R-XUV */
// PANEL REPLAY RELATED DPCD
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY (0x000000B0)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED 0:0
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE 1:1
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_YES (0x00000001)
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION (0x000001B0)
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE 0:0
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000)
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001)

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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _HDMI_SPEC_H_
#define _HDMI_SPEC_H_
/**************** Resource Manager Defines and Structures ******************\
* *
* Module: HDMI_SPEC.H *
* Defines Common HDMI flags *
* *
\***************************************************************************/
/*
* RM will be moving to separate packet types for DP and HDMI
* since the SDP packet type differ between HDMI and DP. Going forward
* clients are expected to use the respective packet type. Once all the
* clients move to the new data types, we can remove the redundant
* PACKET_TYPE definition.
*/
typedef enum
{
pktType_AudioClkRegeneration = 0x01,
pktType_GeneralControl = 0x03,
pktType_GamutMetadata = 0x0a,
pktType_SRInfoFrame = 0x7f, // Self refresh infoframe for eDP enter/exit self refresh, SRS 1698
pktType_Cea861BInfoFrame = 0x80,
pktType_VendorSpecInfoFrame = 0x81,
pktType_AviInfoFrame = 0x82,
pktType_AudioInfoFrame = 0x84,
pktType_SrcProdDescInfoFrame = 0x83,
pktType_MpegSrcInfoFrame = 0x85,
pktType_DynamicRangeMasteringInfoFrame = 0x87
} PACKET_TYPE;
typedef enum
{
hdmi_pktType_AudioClkRegeneration = 0x01,
hdmi_pktType_GeneralControl = 0x03,
hdmi_pktType_GamutMetadata = 0x0a,
hdmi_pktType_ExtendedMetadata = 0x7f,
hdmi_pktType_Cea861BInfoFrame = 0x80,
hdmi_pktType_VendorSpecInfoFrame = 0x81,
hdmi_pktType_AviInfoFrame = 0x82,
hdmi_pktType_AudioInfoFrame = 0x84,
hdmi_pktType_SrcProdDescInfoFrame = 0x83,
hdmi_pktType_MpegSrcInfoFrame = 0x85,
hdmi_pktType_DynamicRangeMasteringInfoFrame = 0x87
} HDMI_PACKET_TYPE;
#define HDMI_PKT_HDR_SIZE 3
#define HDMI_PKT_AVI_NUM_DBYTES 14
#define HDMI_PKT_AUDIO_NUM_DBYTES 11
#define HDMI_PKT_GENCTRL_NUM_DBYTES 7
#define HDMI_PKT_ACR_NUM_DBYTES 7
#define HDMI_PKT_GAMUT_METADATA_NUM_DBYTES 28
#define HDMI_PKT_VS_MAX_NUM_DBYTES 28
#define HDMI_GENCTRL_PACKET_MUTE_ENABLE 0x01
#define HDMI_GENCTRL_PACKET_MUTE_DISABLE 0x10
#endif // #ifndef _HDMI_SPEC_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVBINSEGMENT_H
#define NVBINSEGMENT_H
#define PUSH_SEGMENTS
#define POP_SEGMENTS
#define CODE_SEGMENT(__seg)
#define DATA_SEGMENT(__seg)
#define BSS_SEGMENT(__seg)
#define CONS_SEGMENT(__seg)
#define PAGE_SEGMENT
#define NONPAGE_SEGMENT
#endif // NVBINSEGMENT_H

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#ifndef _NVBLDVER_H_
#define _NVBLDVER_H_
#ifndef NVBLDVER_STRINGIZE
#define NVBLDVER_STRINGIZE(t) #t
#endif
#ifndef STRINGIZE
#define STRINGIZE(t) NVBLDVER_STRINGIZE(t)
#endif
// These variables can be overridden using ENV vars, see nvCommon.nvmk.
// If no env vars are set, then the defaults seen here will be used.
// In DVS builds, the ENV vars are used to control these values.
// Note- the value of NV_BUILD_CL and NV_BUILD_TYPE_NON_BM is only used in
// non-buildmeister builds, see override section below.
// DVS_SW_CHANGELIST has been added to ENV vars in bug 1486673
#ifndef DVS_SW_CHANGELIST
#define DVS_SW_CHANGELIST 0
#endif
#ifndef NV_BUILD_CL
#define NV_BUILD_CL (DVS_SW_CHANGELIST)
#endif
#if NV_BUILD_CL == 0
#define NV_BUILD_CL (DVS_SW_CHANGELIST)
#endif
#ifndef NV_BUILD_TYPE_NON_BM
#define NV_BUILD_TYPE_NON_BM Private
#endif
#ifndef NV_BUILD_AUTHOR
#define NV_BUILD_AUTHOR unknown
#endif
// End ENV var section
// The values of the following strings are set via a buildmeister python script,
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r515_95
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r515_95
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r515/r515_95-155"
#define NV_BUILD_CHANGELIST_NUM (31261195)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r515/r515_95-155"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31261195)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r515_95-3"
#define NV_BUILD_CHANGELIST_NUM (31249857)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "516.01"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31249857)
#endif
// End buildmeister python edited section
// A few of the values are defined differently for non-buildmeister builds,
// this section redefines those defines
#ifndef NV_BUILDMEISTER_BLD
#undef NV_BUILD_TYPE
#define NV_BUILD_TYPE STRINGIZE(NV_BUILD_TYPE_NON_BM)
#undef NV_BUILD_CHANGELIST_NUM
#define NV_BUILD_CHANGELIST_NUM NV_BUILD_CL
#endif
#define NV_DISPLAY_DRIVER_TITLE NV_BUILD_TYPE " " STRINGIZE(NV_BUILD_BRANCH) " " NV_BUILD_NAME " " STRINGIZE(NV_BUILD_AUTHOR)
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _NV_CPU_UUID_H_
#define _NV_CPU_UUID_H_
#define NV_UUID_LEN 16
typedef struct nv_uuid
{
NvU8 uuid[NV_UUID_LEN];
} NvUuid;
#define NV_UUID_HI(pUuid) (*((NvU64*)((pUuid)->uuid + (NV_UUID_LEN >> 1))))
#define NV_UUID_LO(pUuid) (*((NvU64*)((pUuid)->uuid + 0)))
typedef NvUuid NvSystemUuid;
typedef NvUuid NvProcessorUuid;
extern const NvProcessorUuid NV_PROCESSOR_UUID_CPU_DEFAULT;
#endif // _NV_CPU_UUID_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/** @file nvHdmiFrlCommon.h
* @brief This file defines data needed for and returned by HDMI 2.1 spec FRL calculations
* It meant to be a spec layer within HDMI lib, without carrying any
* driver/hw related information
*/
#ifndef _NVHDMIFRLCOMMON_H_
#define _NVHDMIFRLCOMMON_H_
#include "nvmisc.h"
//******************************************************************************
// Constants/Structures
//******************************************************************************
#define MAX_RECONSTRUCTED_HACTIVE_PIXELS 2720
// HDMI_BPC: Bits per component enums.
typedef enum tagHDMI_BPC
{
HDMI_BPC8 = 8,
HDMI_BPC10 = 10,
HDMI_BPC12 = 12,
HDMI_BPC16 = 16
} HDMI_BPC;
// HDMI_PIXEL_PACKING: Pixel packing type enums
typedef enum tagHDMI_PIXEL_PACKING
{
HDMI_PIXEL_PACKING_RGB = 0,
HDMI_PIXEL_PACKING_YCbCr444,
HDMI_PIXEL_PACKING_YCbCr422,
HDMI_PIXEL_PACKING_YCbCr420
} HDMI_PIXEL_PACKING;
// HDMI_FRL_DATA_RATE: FRL mode enums
typedef enum tagHDMI_FRL_DATA_RATE
{
HDMI_FRL_DATA_RATE_NONE,
HDMI_FRL_DATA_RATE_3LANES_3GBPS,
HDMI_FRL_DATA_RATE_3LANES_6GBPS,
HDMI_FRL_DATA_RATE_4LANES_6GBPS,
HDMI_FRL_DATA_RATE_4LANES_8GBPS,
HDMI_FRL_DATA_RATE_4LANES_10GBPS,
HDMI_FRL_DATA_RATE_4LANES_12GBPS,
HDMI_FRL_DATA_RATE_UNSPECIFIED
} HDMI_FRL_DATA_RATE;
typedef enum tagAUDIO_PKTTYPE
{
AUDIO_PKTTYPE_LPCM_SAMPLE = 0,
AUDIO_PKTTYPE_ONE_BIT_LPCM_SAMPLE,
AUDIO_PKTTYPE_DST_AUDIO,
AUDIO_PKTTYPE_HBR_AUDIO,
AUDIO_PKTTYPE_MULTI_STREAM_AUDIO,
AUDIO_PKTTYPE_ONE_BIT_MULTI_STREAM_AUDIO,
AUDIO_PKTTYPE_3D_AUDIO,
AUDIO_PKTTYPE_ONE_BIT_3D_AUDIO,
NO_AUDIO
} AUDIO_PKTTYPE;
typedef struct tagFRL_CAPACITY_COMPUTATION_PARAMS
{
NvU32 numLanes;
NvU32 frlBitRateGbps;
NvU32 pclk10KHz;
NvU32 hTotal;
NvU32 hActive;
NvU32 bpc;
HDMI_PIXEL_PACKING pixelPacking;
AUDIO_PKTTYPE audioType;
NvU32 numAudioChannels;
NvU32 audioFreqKHz;
struct
{
NvU32 bppTargetx16;
NvU32 hSlices;
NvU32 sliceWidth;
NvU32 dscTotalChunkKBytes;
} compressionInfo;
} FRL_CAPACITY_COMPUTATION_PARAMS;
typedef struct tagFRL_COMPUTATION_RESULT
{
HDMI_FRL_DATA_RATE frlRate;
NvU32 bppTargetx16;
NvBool engageCompression;
NvBool isAudioSupported;
NvBool dataFlowDisparityReqMet;
NvBool dataFlowMeteringReqMet;
NvBool isVideoTransportSupported;
NvU32 triBytesBorrowed; // uncompressed mode: num of active Tri-bytes to be transmitted at HBlank
NvU32 hcActiveBytes; // compressed mode: num of FRL character bytes in active region
NvU32 hcActiveTriBytes; // compressed mode: num of FRL tri-bytes in active region
NvU32 hcBlankTriBytes; // compressed mode: num of FRL tri-bytes in blanking region
NvU32 tBlankToTTotalX1k; // compressed mode: ratio of time spent on blanking to the total line time
} FRL_COMPUTATION_RESULT;
typedef struct tagFRL_PRE_CALC_CONFIG
{
NvU32 vic;
HDMI_PIXEL_PACKING packing;
HDMI_BPC bpc;
HDMI_FRL_DATA_RATE frlRate;
NvU32 bppX16;
NvBool bCompressedMode;
} FRL_PRE_CALC_CONFIG;
#endif // _NVHDMIFRLCOMMON_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2009 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* This header file contains the 3-character Plug and Play Vendor IDs and
* their translation into Vendor names.
*
* If the includer defines NV_PNP_VENDOR_IDS_USE_TCHAR, then
* PNPVendorID::vendorName will have type const TCHAR*; otherwise, it will have
* type const char*.
*
* References:
* http://www.uefi.org/pnp_id_list
*
*/
#ifndef __NV_PNP_VENDOR_IDS_H__
#define __NV_PNP_VENDOR_IDS_H__
#if defined(NV_PNP_VENDOR_IDS_USE_TCHAR)
#define _VENDOR_NAME_TYPE const TCHAR
#define _VENDOR_NAME_ENTRY(x) _T(x)
#else
#define _VENDOR_NAME_TYPE const char
#define _VENDOR_NAME_ENTRY(x) (x)
#endif
typedef struct tagPNPVendorID
{
char vendorId[4]; // PNP Vendor ID (example: "SNY")
_VENDOR_NAME_TYPE* vendorName; // Vendor name for display (example: "Sony")
} PNPVendorId;
/*
* The PNPVendorIds[] table maps between the 3-character Plug and
* Play Vendor Identifiers and user-friendly vendor names
*/
static const PNPVendorId PNPVendorIds[] =
{
{ "___", _VENDOR_NAME_ENTRY("Targa") },
{ "@@@", _VENDOR_NAME_ENTRY("Sangyo") },
{ "AAC", _VENDOR_NAME_ENTRY("Acer") },
{ "ABC", _VENDOR_NAME_ENTRY("AboCom System Inc") },
{ "ABP", _VENDOR_NAME_ENTRY("Advanced System Products") },
{ "ACE", _VENDOR_NAME_ENTRY("ACME") },
{ "ACC", _VENDOR_NAME_ENTRY("ACCTON") },
{ "ACI", _VENDOR_NAME_ENTRY("Ancor Communications Inc") },
{ "ACK", _VENDOR_NAME_ENTRY("ACKSYS") },
{ "ACN", _VENDOR_NAME_ENTRY("ACON") },
{ "ACR", _VENDOR_NAME_ENTRY("Acer") },
{ "ACS", _VENDOR_NAME_ENTRY("Altos/ACS") },
{ "ACT", _VENDOR_NAME_ENTRY("Actebis/Targa") },
{ "ADI", _VENDOR_NAME_ENTRY("ADI") },
{ "ADP", _VENDOR_NAME_ENTRY("Adaptec") },
{ "ADT", _VENDOR_NAME_ENTRY("ADTEK") },
{ "ADV", _VENDOR_NAME_ENTRY("AMD") },
{ "ADX", _VENDOR_NAME_ENTRY("ADAX") },
{ "AEI", _VENDOR_NAME_ENTRY("AIR") },
{ "AEM", _VENDOR_NAME_ENTRY("AEM") },
{ "AEO", _VENDOR_NAME_ENTRY("UHC") },
{ "AGI", _VENDOR_NAME_ENTRY("Artish Graphics") },
{ "AKB", _VENDOR_NAME_ENTRY("Akebia") },
{ "AIC", _VENDOR_NAME_ENTRY("Arnos Instruments") },
{ "AIR", _VENDOR_NAME_ENTRY("Advanced Integrated Research") },
{ "AKB", _VENDOR_NAME_ENTRY("Akebia") },
{ "ALA", _VENDOR_NAME_ENTRY("Alacron") },
{ "ALR", _VENDOR_NAME_ENTRY("Advanced Logic Research") },
{ "AMC", _VENDOR_NAME_ENTRY("Attachmate") },
{ "AMD", _VENDOR_NAME_ENTRY("Amdek") },
{ "AMI", _VENDOR_NAME_ENTRY("American Megatrends") },
{ "AMP", _VENDOR_NAME_ENTRY("Amptron") },
{ "AMT", _VENDOR_NAME_ENTRY("Amtrans") },
{ "ANC", _VENDOR_NAME_ENTRY("Ancot") },
{ "ANI", _VENDOR_NAME_ENTRY("Anigma") },
{ "AOC", _VENDOR_NAME_ENTRY("AOC") },
{ "APD", _VENDOR_NAME_ENTRY("Applidata") },
{ "API", _VENDOR_NAME_ENTRY("AcerView") },
{ "APP", _VENDOR_NAME_ENTRY("Apple") },
{ "APS", _VENDOR_NAME_ENTRY("Autologic") },
{ "ARC", _VENDOR_NAME_ENTRY("Alta Research") },
{ "ART", _VENDOR_NAME_ENTRY("ArtMedia") },
{ "ASE", _VENDOR_NAME_ENTRY("ASEM") },
{ "ASI", _VENDOR_NAME_ENTRY("Ahead Systems") },
{ "AST", _VENDOR_NAME_ENTRY("AST Research") },
{ "ASU", _VENDOR_NAME_ENTRY("ASUS") },
{ "ATI", _VENDOR_NAME_ENTRY("Allied Telesis") },
{ "ATO", _VENDOR_NAME_ENTRY("ASTRO DESIGN, INC.") },
{ "ATT", _VENDOR_NAME_ENTRY("AT&T") },
{ "ATX", _VENDOR_NAME_ENTRY("Athenix") },
{ "AUO", _VENDOR_NAME_ENTRY("AU Optronics Corporation") },
{ "AVI", _VENDOR_NAME_ENTRY("AIR") },
{ "AVO", _VENDOR_NAME_ENTRY("Avocent Corporation") },
{ "AZU", _VENDOR_NAME_ENTRY("Azura") },
{ "BAN", _VENDOR_NAME_ENTRY("Banyan") },
{ "BCC", _VENDOR_NAME_ENTRY("Beaver Computer Corporation") },
{ "BCD", _VENDOR_NAME_ENTRY("Dr. Seufert GmbH") },
{ "BEO", _VENDOR_NAME_ENTRY("Bang & Olufsen") },
{ "BGT", _VENDOR_NAME_ENTRY("Budzetron") },
{ "BMM", _VENDOR_NAME_ENTRY("MAG Technology") },
{ "BNQ", _VENDOR_NAME_ENTRY("BenQ") },
{ "BOE", _VENDOR_NAME_ENTRY("BOE Technology Group Co., Ltd") },
{ "BRG", _VENDOR_NAME_ENTRY("Bridge") },
{ "BTC", _VENDOR_NAME_ENTRY("Bit 3") },
{ "BTE", _VENDOR_NAME_ENTRY("Brilliant Technology") },
{ "BUS", _VENDOR_NAME_ENTRY("BusTek") },
{ "CAL", _VENDOR_NAME_ENTRY("Acon") },
{ "CCI", _VENDOR_NAME_ENTRY("Cache") },
{ "CCP", _VENDOR_NAME_ENTRY("Epson") },
{ "CDP", _VENDOR_NAME_ENTRY("CalComp") },
{ "CFG", _VENDOR_NAME_ENTRY("Atlantis") },
{ "CHA", _VENDOR_NAME_ENTRY("Chase Research") },
{ "CIP", _VENDOR_NAME_ENTRY("Ciprico") },
{ "CLO", _VENDOR_NAME_ENTRY("Clone Computers/Analogy") },
{ "CLT", _VENDOR_NAME_ENTRY("automated computer control systems")},
{ "CMD", _VENDOR_NAME_ENTRY("CMD Technology") },
{ "CMO", _VENDOR_NAME_ENTRY("Chi Mei Optoelectronics corp.") },
{ "CNI", _VENDOR_NAME_ENTRY("Connect International") },
{ "CNT", _VENDOR_NAME_ENTRY("CNet Technology") },
{ "COM", _VENDOR_NAME_ENTRY("Comtrol") },
{ "CPC", _VENDOR_NAME_ENTRY("Ciprico") },
{ "CPD", _VENDOR_NAME_ENTRY("CompuAdd") },
{ "CPG", _VENDOR_NAME_ENTRY("DFI") },
{ "CPI", _VENDOR_NAME_ENTRY("Computer Peripherals") },
{ "CPL", _VENDOR_NAME_ENTRY("Compal") },
{ "CPQ", _VENDOR_NAME_ENTRY("Compaq") },
{ "CPT", _VENDOR_NAME_ENTRY("cPATH") },
{ "CPX", _VENDOR_NAME_ENTRY("Powermatic Data Systems") },
{ "CRD", _VENDOR_NAME_ENTRY("Cardinal Technologies") },
{ "CRN", _VENDOR_NAME_ENTRY("Cornerstone") },
{ "CRS", _VENDOR_NAME_ENTRY("Cisco") },
{ "CSE", _VENDOR_NAME_ENTRY("Compu Shack") },
{ "CSI", _VENDOR_NAME_ENTRY("Cabletron") },
{ "CSS", _VENDOR_NAME_ENTRY("CSS Laboratories") },
{ "CTN", _VENDOR_NAME_ENTRY("Computone") },
{ "CTX", _VENDOR_NAME_ENTRY("Chuntex/CTX") },
{ "CUB", _VENDOR_NAME_ENTRY("Cubix") },
{ "CUI", _VENDOR_NAME_ENTRY("CUI") },
{ "CYB", _VENDOR_NAME_ENTRY("CyberVision") },
{ "DBI", _VENDOR_NAME_ENTRY("DigiBoard") },
{ "DBL", _VENDOR_NAME_ENTRY("Doble Engineering") },
{ "DCC", _VENDOR_NAME_ENTRY("Dale Computer") },
{ "DCE", _VENDOR_NAME_ENTRY("Mylex") },
{ "DCM", _VENDOR_NAME_ENTRY("DCM Data Products") },
{ "DEC", _VENDOR_NAME_ENTRY("DEC") },
{ "DEI", _VENDOR_NAME_ENTRY("Deico Electronics") },
{ "DEL", _VENDOR_NAME_ENTRY("Dell") },
{ "DFI", _VENDOR_NAME_ENTRY("DFI") },
{ "DGC", _VENDOR_NAME_ENTRY("Data General") },
{ "DGS", _VENDOR_NAME_ENTRY("Diagsoft") },
{ "DIA", _VENDOR_NAME_ENTRY("Diadem") },
{ "DIO", _VENDOR_NAME_ENTRY("DIO") },
{ "DIS", _VENDOR_NAME_ENTRY("Diseda") },
{ "DIT", _VENDOR_NAME_ENTRY("Dragon Information Technology") },
{ "DLK", _VENDOR_NAME_ENTRY("D-Link") },
{ "DLO", _VENDOR_NAME_ENTRY("Dlodlo Technologies Co., Ltd") },
{ "DMB", _VENDOR_NAME_ENTRY("Digicom Systems") },
{ "DMS", _VENDOR_NAME_ENTRY("DOME imaging systems") },
{ "DNV", _VENDOR_NAME_ENTRY("NexView") },
{ "DOM", _VENDOR_NAME_ENTRY("Dome Imaging Systems") },
{ "DON", _VENDOR_NAME_ENTRY("DENON, Ltd.") },
{ "DPC", _VENDOR_NAME_ENTRY("Delta") },
{ "DPI", _VENDOR_NAME_ENTRY("DocuPoint") },
{ "DPL", _VENDOR_NAME_ENTRY("Digital Projection Limited") },
{ "DPN", _VENDOR_NAME_ENTRY("Shanghai Lexiang Technology Limited") },
{ "DPT", _VENDOR_NAME_ENTRY("DPT") },
{ "DRT", _VENDOR_NAME_ENTRY("Digital Research") },
{ "DSJ", _VENDOR_NAME_ENTRY("VR Technology Holdings Limited") },
{ "DSM", _VENDOR_NAME_ENTRY("DSM Digial Services") },
{ "DTC", _VENDOR_NAME_ENTRY("Data Technology") },
{ "DTI", _VENDOR_NAME_ENTRY("Diversified Technology") },
{ "DTK", _VENDOR_NAME_ENTRY("DTK Computer") },
{ "DTX", _VENDOR_NAME_ENTRY("Data Translation") },
{ "DVC", _VENDOR_NAME_ENTRY("DecaView") },
{ "DWE", _VENDOR_NAME_ENTRY("Daewoo") },
{ "ECS", _VENDOR_NAME_ENTRY("EliteGroup/ECS") },
{ "ENC", _VENDOR_NAME_ENTRY("Eizo") },
{ "EGO", _VENDOR_NAME_ENTRY("Ergo Electronics") },
{ "EKC", _VENDOR_NAME_ENTRY("Kodak") },
{ "EHJ", _VENDOR_NAME_ENTRY("Epson") },
{ "EIZ", _VENDOR_NAME_ENTRY("Eizo") },
{ "ELI", _VENDOR_NAME_ENTRY("Edsun") },
{ "ELS", _VENDOR_NAME_ENTRY("ELSA") },
{ "ELX", _VENDOR_NAME_ENTRY("Elonex") },
{ "EMC", _VENDOR_NAME_ENTRY("ProView/EMC") },
{ "ENC", _VENDOR_NAME_ENTRY("Eizo") },
{ "EPI", _VENDOR_NAME_ENTRY("Envision") },
{ "EQX", _VENDOR_NAME_ENTRY("Equinox") },
{ "ERG", _VENDOR_NAME_ENTRY("Ergo") },
{ "ERP", _VENDOR_NAME_ENTRY("EURAPLAN") },
{ "ESI", _VENDOR_NAME_ENTRY("Extended Systems") },
{ "ETT", _VENDOR_NAME_ENTRY("E-Tech Research") },
{ "EVX", _VENDOR_NAME_ENTRY("Everex") },
{ "EXP", _VENDOR_NAME_ENTRY("Data Export") },
{ "FCB", _VENDOR_NAME_ENTRY("Furukawa Electric") },
{ "FCM", _VENDOR_NAME_ENTRY("Funai") },
{ "FCT", _VENDOR_NAME_ENTRY("Free Computer Technology") },
{ "FDC", _VENDOR_NAME_ENTRY("Future Domain") },
{ "FDX", _VENDOR_NAME_ENTRY("Findex, Inc. ") },
{ "FGL", _VENDOR_NAME_ENTRY("Fujitsu") },
{ "FIC", _VENDOR_NAME_ENTRY("First International") },
{ "FOR", _VENDOR_NAME_ENTRY("Formac") },
{ "FOV", _VENDOR_NAME_ENTRY("FOVE INC") },
{ "FRC", _VENDOR_NAME_ENTRY("FORCE Computers") },
{ "FRI", _VENDOR_NAME_ENTRY("Fibernet Research") },
{ "FTN", _VENDOR_NAME_ENTRY("Fountain Technologies") },
{ "FUJ", _VENDOR_NAME_ENTRY("Fujitsu") },
{ "GAG", _VENDOR_NAME_ENTRY("Gage Applied Sciences") },
{ "GCI", _VENDOR_NAME_ENTRY("Gateway Communications") },
{ "GEN", _VENDOR_NAME_ENTRY("Genesys") },
{ "GMX", _VENDOR_NAME_ENTRY("GMX") },
{ "GRA", _VENDOR_NAME_ENTRY("Graphica") },
{ "GSM", _VENDOR_NAME_ENTRY("LG Electronics") },
{ "GVC", _VENDOR_NAME_ENTRY("GVC") },
{ "GWY", _VENDOR_NAME_ENTRY("Gateway") },
{ "HCL", _VENDOR_NAME_ENTRY("HCL") },
{ "HCP", _VENDOR_NAME_ENTRY("Hitachi") },
{ "HCW", _VENDOR_NAME_ENTRY("Hauppauge") },
{ "HDL", _VENDOR_NAME_ENTRY("Headland") },
{ "HEC", _VENDOR_NAME_ENTRY("Hisense") },
{ "HEI", _VENDOR_NAME_ENTRY("Hyundai") },
{ "HIT", _VENDOR_NAME_ENTRY("Hitachi/HINT") },
{ "HMX", _VENDOR_NAME_ENTRY("HUMAX Co., Ltd.") },
{ "HSD", _VENDOR_NAME_ENTRY("HannStar Display Corp") },
{ "HSL", _VENDOR_NAME_ENTRY("Hansol") },
{ "HTC", _VENDOR_NAME_ENTRY("Hitachi") },
{ "HVR", _VENDOR_NAME_ENTRY("HTC Corporation") },
{ "HWD", _VENDOR_NAME_ENTRY("HighWater Designs") },
{ "HWP", _VENDOR_NAME_ENTRY("HP") },
{ "HYL", _VENDOR_NAME_ENTRY("Hypereal") },
{ "HYP", _VENDOR_NAME_ENTRY("Hyphen Limited") },
{ "HWV", _VENDOR_NAME_ENTRY("Huawei Technologies Co., Ltd") },
{ "IBC", _VENDOR_NAME_ENTRY("IBS") },
{ "IBM", _VENDOR_NAME_ENTRY("IBM") },
{ "ICC", _VENDOR_NAME_ENTRY("BICC Data Networks") },
{ "ICL", _VENDOR_NAME_ENTRY("Fujitsu/ICL") },
{ "ICN", _VENDOR_NAME_ENTRY("Sanyo/Icon") },
{ "ICU", _VENDOR_NAME_ENTRY("Intel") },
{ "IDS", _VENDOR_NAME_ENTRY("Intellistor") },
{ "IFT", _VENDOR_NAME_ENTRY("Informtech") },
{ "IGM", _VENDOR_NAME_ENTRY("IGM Communications") },
{ "III", _VENDOR_NAME_ENTRY("Intelligent Instrumentation") },
{ "IIN", _VENDOR_NAME_ENTRY("Intel") },
{ "IMA", _VENDOR_NAME_ENTRY("Imagraph") },
{ "IMC", _VENDOR_NAME_ENTRY("IMC Networks") },
{ "IMP", _VENDOR_NAME_ENTRY("Impression") },
{ "INF", _VENDOR_NAME_ENTRY("Inframetrics") },
{ "INL", _VENDOR_NAME_ENTRY("InnoLux Display Corporation") },
{ "INP", _VENDOR_NAME_ENTRY("Interphase") },
{ "INS", _VENDOR_NAME_ENTRY("Ines") },
{ "INT", _VENDOR_NAME_ENTRY("Intel") },
{ "IOD", _VENDOR_NAME_ENTRY("IODATA") },
{ "ISA", _VENDOR_NAME_ENTRY("ISA") },
{ "ISI", _VENDOR_NAME_ENTRY("Interface Solutions") },
{ "ISL", _VENDOR_NAME_ENTRY("Isolation Systems") },
{ "ITA", _VENDOR_NAME_ENTRY("Itausa") },
{ "ITC", _VENDOR_NAME_ENTRY("ITK") },
{ "ITN", _VENDOR_NAME_ENTRY("NTI Group/ASUS") },
{ "ITK", _VENDOR_NAME_ENTRY("NTI Group") },
{ "IVK", _VENDOR_NAME_ENTRY("Iiyama") },
{ "IVM", _VENDOR_NAME_ENTRY("Idek Iiyama") },
{ "IVR", _VENDOR_NAME_ENTRY("Inlife-Handnet Co., Ltd.") },
{ "IWR", _VENDOR_NAME_ENTRY("Icuiti Corporation") },
{ "JDI", _VENDOR_NAME_ENTRY("Japan Display Inc") },
{ "JEN", _VENDOR_NAME_ENTRY("Jean") },
{ "JKC", _VENDOR_NAME_ENTRY("JVC Kenwood Corporation") },
{ "JVC", _VENDOR_NAME_ENTRY("JVC") },
{ "KDS", _VENDOR_NAME_ENTRY("Korea Data Systems") },
{ "KDK", _VENDOR_NAME_ENTRY("Kodiak") },
{ "KES", _VENDOR_NAME_ENTRY("Kesa Crop") },
{ "KFC", _VENDOR_NAME_ENTRY("KFC Computek") },
{ "KPC", _VENDOR_NAME_ENTRY("King Phoenix") },
{ "KSC", _VENDOR_NAME_ENTRY("Kinetic Systems") },
{ "KTC", _VENDOR_NAME_ENTRY("Kingston Technology") },
{ "KTG", _VENDOR_NAME_ENTRY("KayserThrede") },
{ "KTR", _VENDOR_NAME_ENTRY("IMRI") },
{ "KYC", _VENDOR_NAME_ENTRY("Kyocera") },
{ "LAG", _VENDOR_NAME_ENTRY("Laguna Systems") },
{ "LCD", _VENDOR_NAME_ENTRY("Toshiba Matsushita Display Technology Co., Ltd")},
{ "LCS", _VENDOR_NAME_ENTRY("Longshine Electronics") },
{ "LEF", _VENDOR_NAME_ENTRY("Leaf Systems") },
{ "LEN", _VENDOR_NAME_ENTRY("Lenovo Group Limited") },
{ "LGE", _VENDOR_NAME_ENTRY("LG Electronics") },
{ "LKM", _VENDOR_NAME_ENTRY("Likom/LKM") },
{ "LNK", _VENDOR_NAME_ENTRY("Link Technologies") },
{ "LTI", _VENDOR_NAME_ENTRY("Longshine") },
{ "LTN", _VENDOR_NAME_ENTRY("Lite-On") },
{ "MAG", _VENDOR_NAME_ENTRY("MAG Technology") },
{ "MAX", _VENDOR_NAME_ENTRY("Maxdata/Belinea") },
{ "MAY", _VENDOR_NAME_ENTRY("Maynard Electronics") },
{ "MBC", _VENDOR_NAME_ENTRY("MBC") },
{ "MCC", _VENDOR_NAME_ENTRY("MCCI") },
{ "MCD", _VENDOR_NAME_ENTRY("McDATA") },
{ "MCI", _VENDOR_NAME_ENTRY("Micronics") },
{ "MCR", _VENDOR_NAME_ENTRY("Marina Communications") },
{ "MCS", _VENDOR_NAME_ENTRY("Micro Computer Systems") },
{ "MCT", _VENDOR_NAME_ENTRY("Microtec") },
{ "MDD", _VENDOR_NAME_ENTRY("Modis") },
{ "MDG", _VENDOR_NAME_ENTRY("Madge Networks") },
{ "MDS", _VENDOR_NAME_ENTRY("Micro Display Systems") },
{ "MDT", _VENDOR_NAME_ENTRY("Magus Data") },
{ "MED", _VENDOR_NAME_ENTRY("Medion") },
{ "MEI", _VENDOR_NAME_ENTRY("Panasonic") },
{ "MEL", _VENDOR_NAME_ENTRY("Mitsubishi") },
{ "MET", _VENDOR_NAME_ENTRY("Metheus") },
{ "MFG", _VENDOR_NAME_ENTRY("Microfield Graphics") },
{ "MGC", _VENDOR_NAME_ENTRY("CompuAdd") },
{ "MGT", _VENDOR_NAME_ENTRY("Megatech") },
{ "MIC", _VENDOR_NAME_ENTRY("Micronics") },
{ "MIR", _VENDOR_NAME_ENTRY("Miro") },
{ "MJI", _VENDOR_NAME_ENTRY("MARANTZ JAPAN, INC.") },
{ "MLX", _VENDOR_NAME_ENTRY("Mylex") },
{ "MMX", _VENDOR_NAME_ENTRY("MAG Technology") },
{ "MOR", _VENDOR_NAME_ENTRY("Morse Technology") },
{ "MSI", _VENDOR_NAME_ENTRY("Microstep") },
{ "MSV", _VENDOR_NAME_ENTRY("Mosgi") },
{ "MTC", _VENDOR_NAME_ENTRY("Mitac") },
{ "MTI", _VENDOR_NAME_ENTRY("Morse Technology") },
{ "MTQ", _VENDOR_NAME_ENTRY("Mountain Computer") },
{ "MTS", _VENDOR_NAME_ENTRY("Multi-Tech Systems") },
{ "MTX", _VENDOR_NAME_ENTRY("Matrox") },
{ "MVD", _VENDOR_NAME_ENTRY("Microvitec PLC") },
{ "MVN", _VENDOR_NAME_ENTRY("META COMPANY") },
{ "MWY", _VENDOR_NAME_ENTRY("Microway") },
{ "MYA", _VENDOR_NAME_ENTRY("Monydata") },
{ "MYL", _VENDOR_NAME_ENTRY("Mylex") },
{ "MYX", _VENDOR_NAME_ENTRY("Micronyx") },
{ "MZI", _VENDOR_NAME_ENTRY("Mozo") },
{ "NAN", _VENDOR_NAME_ENTRY("Nanao") },
{ "NCA", _VENDOR_NAME_ENTRY("Siemens Nixdorf") },
{ "NCD", _VENDOR_NAME_ENTRY("NCD") },
{ "NCS", _VENDOR_NAME_ENTRY("Northgate") },
{ "NDC", _VENDOR_NAME_ENTRY("National DataComm") },
{ "NDS", _VENDOR_NAME_ENTRY("Nokia") },
{ "NEC", _VENDOR_NAME_ENTRY("NEC") },
{ "NIC", _VENDOR_NAME_ENTRY("National Instruments") },
{ "NIT", _VENDOR_NAME_ENTRY("Network Info Technology") },
{ "NOK", _VENDOR_NAME_ENTRY("Nokia") },
{ "NPI", _VENDOR_NAME_ENTRY("Network Peripherals") },
{ "NSC", _VENDOR_NAME_ENTRY("National Semiconductor") },
{ "NSS", _VENDOR_NAME_ENTRY("Newport Systems") },
{ "NTI", _VENDOR_NAME_ENTRY("New Tech") },
{ "NVD", _VENDOR_NAME_ENTRY("NVIDIA") },
{ "NVL", _VENDOR_NAME_ENTRY("Novell") },
{ "NXG", _VENDOR_NAME_ENTRY("Nexgen") },
{ "OAS", _VENDOR_NAME_ENTRY("OAsys") },
{ "OCN", _VENDOR_NAME_ENTRY("Olfan") },
{ "OEC", _VENDOR_NAME_ENTRY("Daytek") },
{ "OLC", _VENDOR_NAME_ENTRY("Olicom") },
{ "OLI", _VENDOR_NAME_ENTRY("Olivetti") },
{ "OKI", _VENDOR_NAME_ENTRY("OKI Electric Industrial Company Ltd") },
{ "ONK", _VENDOR_NAME_ENTRY("ONKYO Corporation") },
{ "OPT", _VENDOR_NAME_ENTRY("OPTi") },
{ "OQI", _VENDOR_NAME_ENTRY("Optiquest") },
{ "OTI", _VENDOR_NAME_ENTRY("Orchid Technology") },
{ "OVR", _VENDOR_NAME_ENTRY("Oculus VR Inc.") },
{ "OZO", _VENDOR_NAME_ENTRY("Zoom Telephonics") },
{ "PAR", _VENDOR_NAME_ENTRY("Parallan Comp Inc") },
{ "PBE", _VENDOR_NAME_ENTRY("Packard Bell") },
{ "PBI", _VENDOR_NAME_ENTRY("Pitney Bowes") },
{ "PBN", _VENDOR_NAME_ENTRY("Packard Bell") },
{ "PCI", _VENDOR_NAME_ENTRY("Pioneer Computer") },
{ "PCP", _VENDOR_NAME_ENTRY("Procomp") },
{ "PDR", _VENDOR_NAME_ENTRY("Pure Data") },
{ "PEA", _VENDOR_NAME_ENTRY("Peacock") },
{ "PGS", _VENDOR_NAME_ENTRY("Princeton Graphics") },
{ "PHI", _VENDOR_NAME_ENTRY("Phillips") },
{ "PHL", _VENDOR_NAME_ENTRY("Philips") },
{ "PIO", _VENDOR_NAME_ENTRY("Pioneer Electronic Corporation") },
{ "PI0", _VENDOR_NAME_ENTRY("Pioneer") },
{ "PIR", _VENDOR_NAME_ENTRY("Pico Technology Inc") },
{ "PJD", _VENDOR_NAME_ENTRY("Projectiondesign AS") },
{ "PLB", _VENDOR_NAME_ENTRY("PLB") },
{ "PLX", _VENDOR_NAME_ENTRY("Ocean Office Automation") },
{ "PMC", _VENDOR_NAME_ENTRY("PMC Consumer Electronics") },
{ "PMV", _VENDOR_NAME_ENTRY("MAG Technology") },
{ "PNR", _VENDOR_NAME_ENTRY("Planar Systems, Inc.") },
{ "PRO", _VENDOR_NAME_ENTRY("Proteon") },
{ "PSI", _VENDOR_NAME_ENTRY("PSI Perceptive Solutions") },
{ "PTS", _VENDOR_NAME_ENTRY("ProView/EMC/PTS") },
{ "PVR", _VENDOR_NAME_ENTRY("Pimax Tech Co., Ltd") },
{ "QDI", _VENDOR_NAME_ENTRY("Quantum Data Incorporated") },
{ "QDM", _VENDOR_NAME_ENTRY("Quadram") },
{ "QTD", _VENDOR_NAME_ENTRY("Quantum 3D Inc") },
{ "QTM", _VENDOR_NAME_ENTRY("Quantum") },
{ "RAC", _VENDOR_NAME_ENTRY("Racore Computer Products") },
{ "RCE", _VENDOR_NAME_ENTRY("RCE") },
{ "RCI", _VENDOR_NAME_ENTRY("RC International") },
{ "REL", _VENDOR_NAME_ENTRY("Relisys") },
{ "REM", _VENDOR_NAME_ENTRY("REM") },
{ "RII", _VENDOR_NAME_ENTRY("Racal Interlan") },
{ "RMP", _VENDOR_NAME_ENTRY("Research Machines") },
{ "ROK", _VENDOR_NAME_ENTRY("Rockwell") },
{ "RTI", _VENDOR_NAME_ENTRY("Rancho Technology") },
{ "RUN", _VENDOR_NAME_ENTRY("RUNCO International") },
{ "SAM", _VENDOR_NAME_ENTRY("Samsung") },
{ "SAN", _VENDOR_NAME_ENTRY("Sanyo Electric Co.,Ltd.") },
{ "SCC", _VENDOR_NAME_ENTRY("SORD") },
{ "SCD", _VENDOR_NAME_ENTRY("Sanyo") },
{ "SDI", _VENDOR_NAME_ENTRY("Samtron/Sigma Designs") },
{ "SDT", _VENDOR_NAME_ENTRY("Siemens AG") },
{ "SEA", _VENDOR_NAME_ENTRY("Segate") },
{ "SEC", _VENDOR_NAME_ENTRY("Seiko/Epson") },
{ "SEN", _VENDOR_NAME_ENTRY("Sencore") },
{ "SGT", _VENDOR_NAME_ENTRY("Stargate Technology/AT&T") },
{ "SGX", _VENDOR_NAME_ENTRY("SGI") },
{ "SHP", _VENDOR_NAME_ENTRY("Sharp") },
{ "SIB", _VENDOR_NAME_ENTRY("Sanyo") },
{ "SIE", _VENDOR_NAME_ENTRY("Siemens Nixdorf") },
{ "SII", _VENDOR_NAME_ENTRY("Silicon Image, Inc.") },
{ "SIS", _VENDOR_NAME_ENTRY("SiS/Modula Tech") },
{ "SIT", _VENDOR_NAME_ENTRY("Sitintel") },
{ "SIX", _VENDOR_NAME_ENTRY("Zuniq Data") },
{ "SKD", _VENDOR_NAME_ENTRY("Schneider & Koch") },
{ "SKW", _VENDOR_NAME_ENTRY("Skyworth") },
{ "SKY", _VENDOR_NAME_ENTRY("SKYDATA S.P.A.") },
{ "SLB", _VENDOR_NAME_ENTRY("Shlumberger Ltd") },
{ "SLT", _VENDOR_NAME_ENTRY("Salt Internatioinal Corp.") },
{ "SLX", _VENDOR_NAME_ENTRY("Specialix") },
{ "SMC", _VENDOR_NAME_ENTRY("Standard Microsystems") },
{ "SMI", _VENDOR_NAME_ENTRY("Smile") },
{ "SML", _VENDOR_NAME_ENTRY("Smile") },
{ "SMS", _VENDOR_NAME_ENTRY("Silicon Multimedia Systems") },
{ "SNI", _VENDOR_NAME_ENTRY("Siemens Nixdorf") },
{ "SNY", _VENDOR_NAME_ENTRY("Sony") },
{ "SOB", _VENDOR_NAME_ENTRY("Sanyo") },
{ "SPE", _VENDOR_NAME_ENTRY("SPEA") },
{ "SPT", _VENDOR_NAME_ENTRY("Sceptre") },
{ "SRC", _VENDOR_NAME_ENTRY("Shamrock/SunRiver") },
{ "SSS", _VENDOR_NAME_ENTRY("S3") },
{ "STA", _VENDOR_NAME_ENTRY("Stesa") },
{ "STB", _VENDOR_NAME_ENTRY("STB Systems") },
{ "STC", _VENDOR_NAME_ENTRY("Sampo/STAC") },
{ "STP", _VENDOR_NAME_ENTRY("Sceptre") },
{ "STR", _VENDOR_NAME_ENTRY("Starlight Networks") },
{ "SUK", _VENDOR_NAME_ENTRY("Schneider & Koch") },
{ "SUP", _VENDOR_NAME_ENTRY("Supra/Diamond Media") },
{ "SUR", _VENDOR_NAME_ENTRY("Surenam") },
{ "SVR", _VENDOR_NAME_ENTRY("Sensics Inc.") },
{ "SYL", _VENDOR_NAME_ENTRY("Sylvania") },
{ "SYN", _VENDOR_NAME_ENTRY("Synaptics Inc") },
{ "TAI", _VENDOR_NAME_ENTRY("Toshiba") },
{ "TAT", _VENDOR_NAME_ENTRY("Tatung") },
{ "TAX", _VENDOR_NAME_ENTRY("Taxan") },
{ "TCC", _VENDOR_NAME_ENTRY("Tandon") },
{ "TCI", _VENDOR_NAME_ENTRY("Tulip") },
{ "TCL", _VENDOR_NAME_ENTRY("Tech Concepts") },
{ "TCM", _VENDOR_NAME_ENTRY("Techmedia/3Com") },
{ "TCO", _VENDOR_NAME_ENTRY("Thomas Conrad") },
{ "TCR", _VENDOR_NAME_ENTRY("Thomson Consumer Electronics") },
{ "TCS", _VENDOR_NAME_ENTRY("Tatung") },
{ "TDS", _VENDOR_NAME_ENTRY("Tri Data Systems") },
{ "TDT", _VENDOR_NAME_ENTRY("TDT") },
{ "TDY", _VENDOR_NAME_ENTRY("Tandy") },
{ "TEA", _VENDOR_NAME_ENTRY("Teac") },
{ "TEC", _VENDOR_NAME_ENTRY("Tecmar") },
{ "TEI", _VENDOR_NAME_ENTRY("TECO") },
{ "TGI", _VENDOR_NAME_ENTRY("TriGem") },
{ "TGS", _VENDOR_NAME_ENTRY("Torus") },
{ "TOS", _VENDOR_NAME_ENTRY("Toshiba") },
{ "TRI", _VENDOR_NAME_ENTRY("Tricord") },
{ "TRM", _VENDOR_NAME_ENTRY("Tekram") },
{ "TRL", _VENDOR_NAME_ENTRY("Royal") },
{ "TRS", _VENDOR_NAME_ENTRY("Torus") },
{ "TRU", _VENDOR_NAME_ENTRY("Aashima/Truevision") },
{ "TSB", _VENDOR_NAME_ENTRY("Toshiba") },
{ "TSC", _VENDOR_NAME_ENTRY("Sanyo") },
{ "TSI", _VENDOR_NAME_ENTRY("TeleVideo") },
{ "TST", _VENDOR_NAME_ENTRY("Transtream Inc") },
{ "TTC", _VENDOR_NAME_ENTRY("Telecommunications Techniques") },
{ "TTK", _VENDOR_NAME_ENTRY("Totoku") },
{ "TTX", _VENDOR_NAME_ENTRY("TTX") },
{ "TVI", _VENDOR_NAME_ENTRY("TeleVideo/Truevision") },
{ "TVM", _VENDOR_NAME_ENTRY("TVM") },
{ "TWA", _VENDOR_NAME_ENTRY("Tidewater") },
{ "TWE", _VENDOR_NAME_ENTRY("Kontron") },
{ "TXN", _VENDOR_NAME_ENTRY("Texas Instruments") },
{ "TYN", _VENDOR_NAME_ENTRY("Tyan Computer") },
{ "UBI", _VENDOR_NAME_ENTRY("Ungermann Bass") },
{ "UFO", _VENDOR_NAME_ENTRY("UFO Systems") },
{ "UNA", _VENDOR_NAME_ENTRY("Unisys") },
{ "UNI", _VENDOR_NAME_ENTRY("Unisys") },
{ "UNM", _VENDOR_NAME_ENTRY("Unisys") },
{ "UNO", _VENDOR_NAME_ENTRY("Unisys") },
{ "UNS", _VENDOR_NAME_ENTRY("Unisys") },
{ "UNT", _VENDOR_NAME_ENTRY("Unisys") },
{ "USC", _VENDOR_NAME_ENTRY("UltraStor") },
{ "USR", _VENDOR_NAME_ENTRY("US Robotics") },
{ "UTB", _VENDOR_NAME_ENTRY("Utobia") },
{ "VES", _VENDOR_NAME_ENTRY("Vestel") },
{ "VIK", _VENDOR_NAME_ENTRY("Viking") },
{ "VLV", _VENDOR_NAME_ENTRY("Valve Corporation") },
{ "VMI", _VENDOR_NAME_ENTRY("Vermont MicroSystems") },
{ "VOB", _VENDOR_NAME_ENTRY("Vobis") },
{ "VRG", _VENDOR_NAME_ENTRY("VRgineers, Inc. ") },
{ "VRT", _VENDOR_NAME_ENTRY("Varjo Technologies") },
{ "VSC", _VENDOR_NAME_ENTRY("ViewSonic") },
{ "WAC", _VENDOR_NAME_ENTRY("Wacom Tech") },
{ "WDC", _VENDOR_NAME_ENTRY("Western Digital") },
{ "WDE", _VENDOR_NAME_ENTRY("Westinghouse Digital Electronics") },
{ "WIL", _VENDOR_NAME_ENTRY("WIPRO") },
{ "WTC", _VENDOR_NAME_ENTRY("Wen Technology") },
{ "WYS", _VENDOR_NAME_ENTRY("Wyse Technology") },
{ "YMH", _VENDOR_NAME_ENTRY("Yamaha Corporation") },
{ "YHQ", _VENDOR_NAME_ENTRY("Yokogawa") },
{ "ZCM", _VENDOR_NAME_ENTRY("Zenith") },
{ "ZDS", _VENDOR_NAME_ENTRY("Zenith") },
{ "ZYT", _VENDOR_NAME_ENTRY("Zytex") },
};
#endif /* __NV_PNP_VENDOR_IDS_H__ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2012 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* Utility header file to generate a one-way hash from an arbitrary
* byte array, using the Secure Hashing Algorithm 1 (SHA-1) as defined
* in FIPS PUB 180-1 published April 17, 1995:
*
* http://www.itl.nist.gov/fipspubs/fip180-1.htm
*
* Some common test cases (see Appendices A and B of the above document):
*
* SHA1("abc") =
* A9993E36 4706816A BA3E2571 7850C26C 9CD0D89D
*
* SHA1("abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq") =
* 84983E44 1C3BD26E BAAE4AA1 F95129E5 E54670F1
*/
#ifndef __NV_SHA1_H__
#define __NV_SHA1_H__
#include "nvtypes.h"
/*!
* @brief Structure used by the SHA-1 functions to maintain the state of the
* calculations.
*/
typedef struct
{
NvU32 state[5];
NvU32 count;
NvU8 buffer[128];
} Sha1Context;
/*!
* @brief Pointer to a memory accessor function for use by the SHA-1 hash
* function.
*
* Due to memory constraints in some environments where this code is executed
* (e.g., the PMU/DPU), the data that needs to be processed by the SHA-1 hash
* function may not be readily available. This function is responsible for
* copying the data into a buffer to be used by the SHA-1 function.
*
* Besides, SHA1 library can be used by many different clients, so we need to
* provide the memory accessor functions which can work in client's environment.
*
* @param[out] pBuff The buffer to copy the new data to.
* @param[in] index The desired offset to begin copying from.
* @param[in] size The requested number of bytes to be copied.
* @param[in] info Pointer to the data passed into GenerateSha1 as pData.
*
* @return The actual number of bytes copied into the buffer.
*/
typedef NvU32 Sha1CopyFunc(NvU8 *pBuff, NvU32 index, NvU32 size, void *pInfo);
/*
* The following values are defined by the SHA-1 algorithm for initial values.
*/
#define SHA1_INIT_H0 0x67452301 //!< Initial H0 value
#define SHA1_INIT_H1 0xEFCDAB89 //!< Initial H1 value
#define SHA1_INIT_H2 0x98BADCFE //!< Initial H2 value
#define SHA1_INIT_H3 0x10325476 //!< Initial H3 value
#define SHA1_INIT_H4 0xC3D2E1F0 //!< Initial H4 value
/*!
* @brief Reverses the byte order of a word; that is, switching the endianness
* of the word.
*
* @param[in] a A 32-bit word
*
* @returns The 32-bit word with its byte order reversed.
*/
#define REVERSE_BYTE_ORDER(a) \
(((a) >> 24) | ((a) << 24) | (((a) >> 8) & 0xFF00) | (((a) << 8) & 0xFF0000))
/*!
* @brief Computation step as defined by SHA-1.
*
* Unlike the 64 byte buffer version outlined in the SHA-1 algorithm, this
* function uses a 128 byte buffer to minimize the calculation needed to
* index the data.
*
* @param[in,out] pState
* Pointer to State word array.
*
* @param[in] pBuffer
* Data to operate on. 128 bytes in length. No length checking is done,
* and is assumed to have been done by the calling function.
*/
static void
_sha1Transform
(
NvU32 *pState,
NvU8 *pBuffer
)
{
NvU32 a = pState[0];
NvU32 b = pState[1];
NvU32 c = pState[2];
NvU32 d = pState[3];
NvU32 e = pState[4];
NvU32 *pBuf = (NvU32 *)pBuffer;
NvU32 *p;
NvU32 i;
NvU32 j;
NvU32 k;
for (i = 0; i < 80; i++)
{
p = &pBuf[i & 0xf];
j = p[0];
if (i < 16)
{
j = REVERSE_BYTE_ORDER(j);
}
else
{
j ^= p[2] ^ p[8] ^ p[13];
j = (j << 1) + (j >> 31);
}
p[0] = p[16] = j;
if (i < 40)
{
if (i < 20)
{
k = 0x5a827999 + ((b & (c ^ d)) ^ d);
}
else
{
k = 0x6ed9eba1 + (b ^ c ^ d);
}
}
else
{
if (i < 60)
{
k = 0x8f1bbcdc + (((b | c) & d) | (b & c));
}
else
{
k = 0xca62c1d6 + (b ^ c ^ d);
}
}
j += (a << 5) + (a >> 27) + e + k;
e = d;
d = c;
c = (b << 30) + (b >> 2);
b = a;
a = j;
}
pState[0] += a;
pState[1] += b;
pState[2] += c;
pState[3] += d;
pState[4] += e;
}
/*!
* Initializes the SHA-1 context.
*
* @param[out] pContext
* Pointer to the context to initialize.
*/
static void
_sha1Initialize
(
Sha1Context *pContext
)
{
pContext->count = 0;
pContext->state[0] = SHA1_INIT_H0;
pContext->state[1] = SHA1_INIT_H1;
pContext->state[2] = SHA1_INIT_H2;
pContext->state[3] = SHA1_INIT_H3;
pContext->state[4] = SHA1_INIT_H4;
}
/*!
* @brief Divides the input buffer into multiple 64-byte buffers and computes
* the message digest for each.
*
* @param[in] pContext
* Pointer to a Sha1Context.
*
* @param[in] pData
* Pointer to the data array to compute the message digest.
*
* @param[in] len
* Size of the data.
*
* @param[in] copyFunc
* Copy routine to use.
*/
static void
_sha1Update
(
Sha1Context *pContext,
void *pData,
NvU32 len,
Sha1CopyFunc copyFunc
)
{
NvU32 buffer_offset = (pContext->count & 63);
NvU32 copy_size;
NvU32 idx = 0;
pContext->count += len;
while ((buffer_offset + len) > 63)
{
copy_size = 64 - buffer_offset;
copyFunc(&pContext->buffer[buffer_offset], idx, copy_size, pData);
_sha1Transform(pContext->state, pContext->buffer);
buffer_offset = 0;
idx += copy_size;
len -= copy_size;
}
if (len > 0)
{
copyFunc(&pContext->buffer[buffer_offset], idx, len, pData);
}
}
/*!
* @brief fill memory with zero; not all environments in which this
* code runs have memset(3).
*
* @param[out] pData
* The memory to be filled with zero
*
* @param[in] nBytes
* The number of bytes of memory to fill with zero
*/
static NV_INLINE void
_sha1MemZero
(
NvU8 *pData,
NvU32 nBytes
)
{
NvU32 i;
for (i = 0; i < nBytes; i++) {
pData[i] = 0;
}
}
/*!
* @brief Pads the message as specified by the SHA-1 algorithm and computes
* the message digest on the final message chunk(s).
*
* @param[out] pDigest
* The SHA-1 hash values.
*
* @param[in] pContext
* Pointer to a Sha1Context.
*/
static void
_sha1Final
(
NvU8 *pDigest,
Sha1Context *pContext
)
{
NvU32 i;
NvU32 bufferOffset = (pContext->count & 63);
NvU8 *pBuffer = (NvU8*)&pContext->buffer[bufferOffset];
NvU32 *pCount;
NvU32 *pDig32;
// append padding pattern to the end of input
*pBuffer++ = 0x80;
if (bufferOffset < 56)
{
_sha1MemZero(pBuffer, 59 - bufferOffset);
}
else
{
// need an extra sha1_transform
if (bufferOffset < 63)
{
_sha1MemZero(pBuffer, 63 - bufferOffset);
}
_sha1Transform(pContext->state, pContext->buffer);
_sha1MemZero(pContext->buffer, 60);
}
// set final count (this is the number of *bits* not *bytes*)
pCount = (NvU32*)&pContext->buffer[15 << 2];
*pCount = REVERSE_BYTE_ORDER(pContext->count << 3);
_sha1Transform(pContext->state, pContext->buffer);
// output hash with each dword in big endian
if (pDigest)
{
pDig32 = (NvU32*) pDigest;
for (i = 0; i < 5; i++)
{
pDig32[i] = REVERSE_BYTE_ORDER(pContext->state[i]);
}
}
}
/*!
* @brief Generates the SHA-1 hash value on the data provided.
*
* The function does not manipulate the source data directly, as it may not
* have direct access to it. Therefore, it relies upon the copy function to
* copy segments of the data into a local buffer before any manipulation takes
* place.
*
* @param[out] pHash
* Pointer to store the hash array. The buffer must be 20 bytes in
* length, and the result is stored in big endian format.
*
* @param[in] pData
* The source data array to transform. The actual values and make-up
* of this parameter are dependent on the copy function.
*
* @param[in] nBytes
* The size, in bytes, of the source data.
*
* @param[in] copyFunc
* The function responsible for copying data from the source
* for use by the sha1 function. It is possible for the data
* to exist outside the current execution environment (e.g.,
* the PMU, and the data to hash are in system memory), so
* the function will never directly manipulate the source
* data.
*/
#define NV_SHA1_BLOCK_LENGTH 64
#define NV_SHA1_DIGEST_LENGTH 20
static void
sha1Generate
(
NvU8 pHash[NV_SHA1_DIGEST_LENGTH],
void *pData,
NvU32 nBytes,
Sha1CopyFunc copyFunc
)
{
Sha1Context context;
_sha1Initialize(&context);
_sha1Update(&context, pData, nBytes, copyFunc);
_sha1Final(pHash, &context);
}
#endif /* __NV_SHA1_H__ */

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/*
* FIPS 180-2 SHA-224/256/384/512 implementation
* Last update: 02/02/2007
* Issue date: 04/30/2005
*
* Copyright (C) 2005, 2007 Olivier Gay <olivier.gay@a3.epfl.ch>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the project nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/** \file SHA256.h
* \brief SHA256 definitions.
* \author Steven A. Fontana Sr.
* \date September 4 2009
*/
#ifndef NV_SHA2_H
#define NV_SHA2_H
#include <nvtypes.h>
#define NV_SHA256_DIGEST_SIZE ( 256 / 8)
#define NV_SHA256_BLOCK_SIZE ( 512 / 8)
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
NvU32 tot_len;
NvU32 len;
NvU8 block[2 * NV_SHA256_BLOCK_SIZE];
NvU32 h[8];
} nv_sha256_ctx;
void nv_sha256_init(nv_sha256_ctx * ctx);
void nv_sha256_update(nv_sha256_ctx *ctx, const NvU8 *message, NvU32 len);
void nv_sha256_final(nv_sha256_ctx *ctx, NvU8 *digest);
void nv_sha256_noPad(nv_sha256_ctx *ctx, NvU8 *digest);
void nv_sha256(const NvU8 *message, NvU32 len, NvU8 *digest);
#ifdef __cplusplus
}
#endif
#endif /* !NV_SHA2_H */

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#ifndef __NV_UNIX_VERSION_H__
#define __NV_UNIX_VERSION_H__
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "515.43.04"
#else
#error "nvUnixVersion.h should only be included in UNIX builds"
#endif
#endif /* __NV_UNIX_VERSION_H__ */

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// nvVer.h - Versions of NV drivers
#define NV_COMPANY_NAME_STRING_SHORT "NVIDIA"
#define NV_COMPANY_NAME_STRING_FULL "NVIDIA Corporation"
#define NV_COMPANY_NAME_STRING NV_COMPANY_NAME_STRING_FULL
#define NV_COPYRIGHT_YEAR "2022"
#define NV_COPYRIGHT "(C) " NV_COPYRIGHT_YEAR " NVIDIA Corporation. All rights reserved." // Please do not use the non-ascii copyright symbol for (C).
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
// All Version numbering for Unix builds has moved. (Source should be re-directed to directly include that header.)
#include "nvUnixVersion.h"
#else
#endif

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/*
* Copyright © 2010 Intel Corporation
* Copyright © 2010 Francisco Jerez <currojerez@riseup.net>
* Copyright © 2012 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
*/
/*
* This file was copied from the X.Org X server source at commit
* 5884e7dedecdd82ddbb037360cf9c85143e094b5 and modified to match NVIDIA's X
* driver code style.
*/
#ifndef _NV_LIST_H_
#define _NV_LIST_H_
#ifdef __cplusplus
extern "C" {
#endif //__cplusplus
#include "nvmisc.h"
#define HAVE_TYPEOF 1
/**
* @file Classic doubly-link circular list implementation.
* For real usage examples of the linked list, see the file test/list.c
*
* Example:
* We need to keep a list of struct foo in the parent struct bar, i.e. what
* we want is something like this.
*
* struct bar {
* ...
* struct foo *list_of_foos; -----> struct foo {}, struct foo {}, struct foo{}
* ...
* }
*
* We need one list head in bar and a list element in all list_of_foos (both are of
* data type 'NVListRec').
*
* struct bar {
* ...
* NVListRec list_of_foos;
* ...
* }
*
* struct foo {
* ...
* NVListRec entry;
* ...
* }
*
* Now we initialize the list head:
*
* struct bar bar;
* ...
* nvListInit(&bar.list_of_foos);
*
* Then we create the first element and add it to this list:
*
* struct foo *foo = malloc(...);
* ....
* nvListAdd(&foo->entry, &bar.list_of_foos);
*
* Repeat the above for each element you want to add to the list. Deleting
* works with the element itself.
* nvListDel(&foo->entry);
* free(foo);
*
* Note: calling nvListDel(&bar.list_of_foos) will set bar.list_of_foos to an empty
* list again.
*
* Looping through the list requires a 'struct foo' as iterator and the
* name of the field the subnodes use.
*
* struct foo *iterator;
* nvListForEachEntry(iterator, &bar.list_of_foos, entry) {
* if (iterator->something == ...)
* ...
* }
*
* Note: You must not call nvListDel() on the iterator if you continue the
* loop. You need to run the safe for-each loop instead:
*
* struct foo *iterator, *next;
* nvListForEachEntry_safe(iterator, next, &bar.list_of_foos, entry) {
* if (...)
* nvListDel(&iterator->entry);
* }
*
*/
/**
* The linkage struct for list nodes. This struct must be part of your
* to-be-linked struct. NVListRec is required for both the head of the
* list and for each list node.
*
* Position and name of the NVListRec field is irrelevant.
* There are no requirements that elements of a list are of the same type.
* There are no requirements for a list head, any NVListRec can be a list
* head.
*/
typedef struct NVList {
struct NVList *next, *prev;
} NVListRec, *NVListPtr;
/**
* Initialize the list as an empty list.
*
* Example:
* nvListInit(&bar->list_of_foos);
*
* @param The list to initialized.
*/
static NV_INLINE void
nvListInit(NVListPtr list)
{
list->next = list->prev = list;
}
/**
* Initialize the list as an empty list.
*
* This is functionally the same as nvListInit, but can be used for
* initialization of global variables.
*
* Example:
* static NVListRec list_of_foos = NV_LIST_INIT(&list_of_foos);
*
* @param The list to initialized.
*/
#define NV_LIST_INIT(head) { .prev = (head), .next = (head) }
static NV_INLINE void
__nvListAdd(NVListPtr entry, NVListPtr prev, NVListPtr next)
{
next->prev = entry;
entry->next = next;
entry->prev = prev;
prev->next = entry;
}
/**
* Insert a new element after the given list head. The new element does not
* need to be initialised as empty list.
* The list changes from:
* head -> some element -> ...
* to
* head -> new element -> older element -> ...
*
* Example:
* struct foo *newfoo = malloc(...);
* nvListAdd(&newfoo->entry, &bar->list_of_foos);
*
* @param entry The new element to prepend to the list.
* @param head The existing list.
*/
static NV_INLINE void
nvListAdd(NVListPtr entry, NVListPtr head)
{
__nvListAdd(entry, head, head->next);
}
/**
* Append a new element to the end of the list given with this list head.
*
* The list changes from:
* head -> some element -> ... -> lastelement
* to
* head -> some element -> ... -> lastelement -> new element
*
* Example:
* struct foo *newfoo = malloc(...);
* nvListAppend(&newfoo->entry, &bar->list_of_foos);
*
* @param entry The new element to prepend to the list.
* @param head The existing list.
*/
static NV_INLINE void
nvListAppend(NVListPtr entry, NVListPtr head)
{
__nvListAdd(entry, head->prev, head);
}
static NV_INLINE void
__nvListDel(NVListPtr prev, NVListPtr next)
{
next->prev = prev;
prev->next = next;
}
/**
* Remove the element from the list it is in. Using this function will reset
* the pointers to/from this element so it is removed from the list. It does
* NOT free the element itself or manipulate it otherwise.
*
* Using nvListDel on a pure list head (like in the example at the top of
* this file) will NOT remove the first element from
* the list but rather reset the list as empty list.
*
* Example:
* nvListDel(&foo->entry);
*
* @param entry The element to remove.
*/
static NV_INLINE void
nvListDel(NVListPtr entry)
{
__nvListDel(entry->prev, entry->next);
nvListInit(entry);
}
/**
* Check if the list is empty.
*
* Example:
* nvListIsEmpty(&bar->list_of_foos);
*
* @return True if the list contains one or more elements or False otherwise.
*/
static NV_INLINE NvBool
nvListIsEmpty(const NVListRec *head)
{
return head->next == head;
}
static NV_INLINE int
nvListCount(const NVListRec *head)
{
NVListPtr next;
int count = 0;
for (next = head->next; next != head; next = next->next) {
count++;
}
return count;
}
/**
* Check if entry is present in the list.
*
* Example:
* nvListPresent(&foo->entry, &bar->list_of_foos);
*
* @return 1 if the list contains the specified entry; otherwise, return 0.
*/
static NV_INLINE NvBool
nvListPresent(const NVListRec *entry, const NVListRec *head)
{
const NVListRec *next;
for (next = head->next; next != head; next = next->next) {
if (next == entry) {
return NV_TRUE;
}
}
return NV_FALSE;
}
/**
* Returns a pointer to the container of this list element.
*
* Example:
* struct foo* f;
* f = nv_container_of(&foo->entry, struct foo, entry);
* assert(f == foo);
*
* @param ptr Pointer to the NVListRec.
* @param type Data type of the list element.
* @param member Member name of the NVListRec field in the list element.
* @return A pointer to the data struct containing the list head.
*/
#ifndef nv_container_of
#define nv_container_of(ptr, type, member) \
(type *)((char *)(ptr) - NV_OFFSETOF(type, member))
#endif
/**
* Alias of nv_container_of
*/
#define nvListEntry(ptr, type, member) \
nv_container_of(ptr, type, member)
/**
* Retrieve the first list entry for the given list pointer.
*
* Example:
* struct foo *first;
* first = nvListFirstEntry(&bar->list_of_foos, struct foo, list_of_foos);
*
* @param ptr The list head
* @param type Data type of the list element to retrieve
* @param member Member name of the NVListRec field in the list element.
* @return A pointer to the first list element.
*/
#define nvListFirstEntry(ptr, type, member) \
nvListEntry((ptr)->next, type, member)
/**
* Retrieve the last list entry for the given listpointer.
*
* Example:
* struct foo *first;
* first = nvListLastEntry(&bar->list_of_foos, struct foo, list_of_foos);
*
* @param ptr The list head
* @param type Data type of the list element to retrieve
* @param member Member name of the NVListRec field in the list element.
* @return A pointer to the last list element.
*/
#define nvListLastEntry(ptr, type, member) \
nvListEntry((ptr)->prev, type, member)
#ifdef HAVE_TYPEOF
#define __nv_container_of(ptr, sample, member) \
nv_container_of(ptr, __typeof__(*sample), member)
#else
/* This implementation of __nv_container_of has undefined behavior according
* to the C standard, but it works in many cases. If your compiler doesn't
* support __typeof__() and fails with this implementation, please try a newer
* compiler.
*/
#define __nv_container_of(ptr, sample, member) \
(void *)((char *)(ptr) \
- ((char *)&(sample)->member - (char *)(sample)))
#endif
/**
* Loop through the list given by head and set pos to struct in the list.
*
* Example:
* struct foo *iterator;
* nvListForEachEntry(iterator, &bar->list_of_foos, entry) {
* [modify iterator]
* }
*
* This macro is not safe for node deletion. Use nvListForEachEntry_safe
* instead.
*
* @param pos Iterator variable of the type of the list elements.
* @param head List head
* @param member Member name of the NVListRec in the list elements.
*
*/
#ifdef HAVE_TYPEOF
#define __NV_LIST_SET(x, y) x = y
#else
static NV_INLINE void __nvListSet(void **x, void *y)
{
*x = y;
}
#define __NV_LIST_SET(x, y) __nvListSet((void **) &x, (void *) (y))
#endif
#define nvListForEachEntry(pos, head, member) \
for (__NV_LIST_SET(pos, __nv_container_of((head)->next, pos, member)); \
&pos->member != (head); \
__NV_LIST_SET(pos, __nv_container_of(pos->member.next, pos, member)))
/**
* Loop through the list, keeping a backup pointer to the element. This
* macro allows for the deletion of a list element while looping through the
* list.
*
* See nvListForEachEntry for more details.
*/
#define nvListForEachEntry_safe(pos, tmp, head, member) \
for (__NV_LIST_SET(pos, __nv_container_of((head)->next, pos, member)), \
__NV_LIST_SET(tmp, __nv_container_of(pos->member.next, pos, member)); \
&pos->member != (head); \
__NV_LIST_SET(pos, tmp), \
__NV_LIST_SET(tmp, __nv_container_of(pos->member.next, tmp, member)))
/* NULL-Terminated List Interface
*
* The interface below does _not_ use the NVListRec as described above.
* It is mainly for legacy structures that cannot easily be switched to
* NVListRec.
*
* This interface is for structs like
* struct foo {
* [...]
* struct foo *next;
* [...]
* };
*
* The position and field name of "next" are arbitrary.
*/
/**
* Init the element as null-terminated list.
*
* Example:
* struct foo *list = malloc();
* nvNTListInit(list, next);
*
* @param list The list element that will be the start of the list
* @param member Member name of the field pointing to next struct
*/
#define nvNTListInit(_list, _member) \
(_list)->_member = NULL
/**
* Returns the next element in the list or NULL on termination.
*
* Example:
* struct foo *element = list;
* while ((element = nvNTListNext(element, next)) { }
*
* This macro is not safe for node deletion. Use nvListForEachEntry_safe
* instead.
*
* @param list The list or current element.
* @param member Member name of the field pointing to next struct.
*/
#define nvNTListNext(_list, _member) \
(_list)->_member
/**
* Iterate through each element in the list.
*
* Example:
* struct foo *iterator;
* nvNTListForEachEntry(iterator, list, next) {
* [modify iterator]
* }
*
* @param entry Assigned to the current list element
* @param list The list to iterate through.
* @param member Member name of the field pointing to next struct.
*/
#define nvNTListForEachEntry(_entry, _list, _member) \
for (_entry = _list; _entry; _entry = (_entry)->_member)
/**
* Iterate through each element in the list, keeping a backup pointer to the
* element. This macro allows for the deletion of a list element while
* looping through the list.
*
* See nvNTListForEachEntry for more details.
*
* @param entry Assigned to the current list element
* @param tmp The pointer to the next element
* @param list The list to iterate through.
* @param member Member name of the field pointing to next struct.
*/
#define nvNTListForEachEntrySafe(_entry, _tmp, _list, _member) \
for (_entry = _list, _tmp = (_entry) ? (_entry)->_member : NULL;\
_entry; \
_entry = _tmp, _tmp = (_tmp) ? (_tmp)->_member: NULL)
/**
* Append the element to the end of the list. This macro may be used to
* merge two lists.
*
* Example:
* struct foo *elem = malloc(...);
* nvNTListInit(elem, next)
* nvNTListAppend(elem, list, struct foo, next);
*
* Resulting list order:
* list_item_0 -> list_item_1 -> ... -> elem_item_0 -> elem_item_1 ...
*
* @param entry An entry (or list) to append to the list
* @param list The list to append to. This list must be a valid list, not
* NULL.
* @param type The list type
* @param member Member name of the field pointing to next struct
*/
#define nvNTListAppend(_entry, _list, _type, _member) \
do { \
_type *__iterator = _list; \
while (__iterator->_member) { __iterator = __iterator->_member;}\
__iterator->_member = _entry; \
} while (0)
/**
* Insert the element at the next position in the list. This macro may be
* used to insert a list into a list.
*
* struct foo *elem = malloc(...);
* nvNTListInit(elem, next)
* nvNTListInsert(elem, list, struct foo, next);
*
* Resulting list order:
* list_item_0 -> elem_item_0 -> elem_item_1 ... -> list_item_1 -> ...
*
* @param entry An entry (or list) to append to the list
* @param list The list to insert to. This list must be a valid list, not
* NULL.
* @param type The list type
* @param member Member name of the field pointing to next struct
*/
#define nvNTListInsert(_entry, _list, _type, _member) \
do { \
nvNTListAppend((_list)->_member, _entry, _type, _member); \
(_list)->_member = _entry; \
} while (0)
/**
* Delete the entry from the list by iterating through the list and
* removing any reference from the list to the entry.
*
* Example:
* struct foo *elem = <assign to right element>
* nvNTListDel(elem, list, struct foo, next);
*
* @param entry The entry to delete from the list. entry is always
* re-initialized as a null-terminated list.
* @param list The list containing the entry, set to the new list without
* the removed entry.
* @param type The list type
* @param member Member name of the field pointing to the next entry
*/
#define nvNTListDel(_entry, _list, _type, _member) \
do { \
_type *__e = _entry; \
if (__e == NULL || _list == NULL) break; \
if ((_list) == __e) { \
_list = __e->_member; \
} else { \
_type *__prev = _list; \
while (__prev->_member && __prev->_member != __e) \
__prev = nvNTListNext(__prev, _member); \
if (__prev->_member) \
__prev->_member = __e->_member; \
} \
nvNTListInit(__e, _member); \
} while(0)
#ifdef __cplusplus
}
#endif //__cplusplus
#endif /* _NV_LIST_H_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* NVIDIA GPZ vulnerability mitigation definitions.
*/
/*
* There are two copies of this file for legacy reasons:
*
* P4: <$NV_SOURCE/>drivers/common/inc/nv_speculation_barrier.h
* Git: <tegra/core/>include/nv_speculation_barrier.h
*
* Both files need to be kept in sync if any changes are required.
*/
#ifndef _NV_SPECULATION_BARRIER_H_
#define _NV_SPECULATION_BARRIER_H_
#define NV_SPECULATION_BARRIER_VERSION 2
/*
* GNU-C/MSC/clang - x86/x86_64 : x86_64, __i386, __i386__
* GNU-C - THUMB mode : __GNUC__, __thumb__
* GNU-C - ARM modes : __GNUC__, __arm__, __aarch64__
* armclang - THUMB mode : __ARMCC_VERSION, __thumb__
* armclang - ARM modes : __ARMCC_VERSION, __arm__, __aarch64__
* GHS - THUMB mode : __ghs__, __THUMB__
* GHS - ARM modes : __ghs__, __ARM__, __ARM64__
*/
#if defined(_M_IX86) || defined(__i386__) || defined(__i386) \
|| defined(__x86_64) || defined(AMD64) || defined(_M_AMD64)
/* All x86 */
#define NV_SPECULATION_BARRIER_x86
#elif defined(macintosh) || defined(__APPLE__) \
|| defined(__powerpc) || defined(__powerpc__) || defined(__powerpc64__) \
|| defined(__POWERPC__) || defined(__ppc) || defined(__ppc__) \
|| defined(__ppc64__) || defined(__PPC__) \
|| defined(__PPC64__) || defined(_ARCH_PPC) || defined(_ARCH_PPC64)
/* All PowerPC */
#define NV_SPECULATION_BARRIER_PPC
#elif (defined(__GNUC__) && defined(__thumb__)) \
|| (defined(__ARMCC_VERSION) && defined(__thumb__)) \
|| (defined(__ghs__) && defined(__THUMB__))
/* ARM-thumb mode(<=ARMv7)/T32 (ARMv8) */
#define NV_SPECULATION_BARRIER_ARM_COMMON
#define NV_SPEC_BARRIER_CSDB ".inst.w 0xf3af8014\n"
#elif (defined(__GNUC__) && defined(__arm__)) \
|| (defined(__ARMCC_VERSION) && defined(__arm__)) \
|| (defined(__ghs__) && defined(__ARM__))
/* aarch32(ARMv8) / arm(<=ARMv7) mode */
#define NV_SPECULATION_BARRIER_ARM_COMMON
#define NV_SPEC_BARRIER_CSDB ".inst 0xe320f014\n"
#elif (defined(__GNUC__) && defined(__aarch64__)) \
|| (defined(__ARMCC_VERSION) && defined(__aarch64__)) \
|| (defined(__ghs__) && defined(__ARM64__))
/* aarch64(ARMv8) mode */
#define NV_SPECULATION_BARRIER_ARM_COMMON
#define NV_SPEC_BARRIER_CSDB "HINT #20\n"
#elif defined(NVCPU_NVRISCV64) && NVOS_IS_LIBOS
# define nv_speculation_barrier()
#else
#error "Unknown compiler/chip family"
#endif
/*
* nv_speculation_barrier -- General-purpose speculation barrier
*
* This approach provides full protection against variant-1 vulnerability.
* However, the recommended approach is detailed below (See:
* nv_array_index_no_speculate)
*
* Semantics:
* Any memory read that is sequenced after a nv_speculation_barrier(),
* and contained directly within the scope of nv_speculation_barrier() or
* directly within a nested scope, will not speculatively execute until all
* conditions for entering that scope have been architecturally resolved.
*
* Example:
* if (untrusted_index_from_user < bound) {
* ...
* nv_speculation_barrier();
* ...
* x = array1[untrusted_index_from_user];
* bit = x & 1;
* y = array2[0x100 * bit];
* }
*/
#if defined(NV_SPECULATION_BARRIER_x86)
// Delete after all references are changed to nv_speculation_barrier
#define speculation_barrier() nv_speculation_barrier()
static inline void nv_speculation_barrier(void)
{
#if defined(__GNUC__) || defined(__clang__)
__asm__ __volatile__ ("lfence" : : : "memory");
#endif
}
#elif defined(NV_SPECULATION_BARRIER_PPC)
static inline void nv_speculation_barrier(void)
{
asm volatile("ori 31,31,0");
}
#elif defined(NV_SPECULATION_BARRIER_ARM_COMMON)
/* Note: Cortex-A9 GNU-assembler seems to complain about DSB SY */
#define nv_speculation_barrier() \
asm volatile \
( \
"DSB sy\n" \
"ISB\n" \
: : : "memory" \
)
#endif
/*
* nv_array_index_no_speculate -- Recommended variant-1 mitigation approach
*
* The array-index-no-speculate approach "de-speculates" an array index that
* has already been bounds-checked.
*
* This approach is preferred over nv_speculation_barrier due to the following
* reasons:
* - It is just as effective as the general-purpose speculation barrier.
* - It clearly identifies what array index is being de-speculated and is thus
* self-commenting, whereas the general-purpose speculation barrier requires
* an explanation of what array index is being de-speculated.
* - It performs substantially better than the general-purpose speculation
* barrier on ARM Cortex-A cores (the difference is expected to be tens of
* cycles per invocation). Within tight loops, this difference may become
* noticeable.
*
* Semantics:
* Provided count is non-zero and the caller has already validated or otherwise
* established that index < count, any speculative use of the return value will
* use a speculative value that is less than count.
*
* Example:
* if (untrusted_index_from_user < bound) {
* untrusted_index_from_user = nv_array_index_no_speculate(
* untrusted_index_from_user, bound);
* ...
* x = array1[untrusted_index_from_user];
* ...
* }
*
* The use of nv_array_index_no_speculate() in the above example ensures that
* subsequent uses of untrusted_index_from_user will not execute speculatively
* (they will wait for the bounds check to complete).
*/
static inline unsigned long nv_array_index_no_speculate(unsigned long index,
unsigned long count)
{
#if defined(NV_SPECULATION_BARRIER_x86) && (defined(__GNUC__) || defined(__clang__))
unsigned long mask;
__asm__ __volatile__
(
"CMP %2, %1 \n"
"SBB %0, %0 \n"
: "=r"(mask) : "r"(index), "r"(count) : "cc"
);
return (index & mask);
#elif defined(NV_SPECULATION_BARRIER_ARM_COMMON)
unsigned long mask;
asm volatile
(
"CMP %[ind], %[cnt] \n"
"SBC %[res], %[cnt], %[cnt] \n"
NV_SPEC_BARRIER_CSDB
: [res] "=r" (mask) : [ind] "r" (index), [cnt] "r" (count): "cc"
);
return (index & mask);
/* Fallback to generic speculation barrier for unsupported platforms */
#else
nv_speculation_barrier();
return index;
#endif
}
#endif //_NV_SPECULATION_BARRIER_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 1997-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NV_CTASSERT_H
#define __NV_CTASSERT_H
/*****************************************************************************/
/* Compile Time assert
* -------------------
* Use ct_assert(b) instead of assert(b) whenever the condition 'b' is constant,
* i.e. when 'b' can be determined at compile time.
*
* e.g.: check array size:
* ct_assert(__GL_ARRAYSIZE(arrayName) == constArraySize);
* e.g.: check struct size alignment:
* ct_assert(sizeof(struct xy) % 64 == 0);
*
* When available, standard C or C++ language constructs are used:
* - ISO C++11 defines the static_assert keyword
* - ISO C11 defines the _Static_assert keyword
*
* Note that recent versions of Clang support _Static_assert in all compiler modes
* - not just C11 mode - so we test for that in addition to checking explicitly for
* C11 and C++11 support.
*
* Those new language standards aren't available on all supported platforms; an
* alternate method which involves array declarations is employed in that case,
* described below.
*
* In C, there is a restriction where ct_assert() can be placed:
* It can be placed wherever a variable declaration can be placed, i.e.:
* - either anywhere at file scope
* - or inside a function at the beginning of any {} block; it may be mixed
* with variable declarations.
* e.g.:
* void function()
* {
* ct_assert(...); <-- ok \
* int a; |
* ct_assert(...); <-- ok | declaration section
* int b; |
* ct_assert(...); <-- ok /
*
* a = 0; -- first statement
*
* int c; <-- error
* ct_assert(...); <-- error
*
* {ct_assert(...);} <-- ok (uses its own block for ct_assert())
* }
*
* In CPP, there is no such restriction, i.e. it can be placed at file scope
* or anywhere inside a function or namespace or class (i.e., wherever
* a variable declaration may be placed).
*
* For C code, the mechanism of this ct_assert() is to declare a prototype
* of a function (e.g. compile_time_assertion_failed_in_line_555, if current
* line number is 555), which gets an array as argument:
* (1) the size of this array is +1, if b != 0 (ok)
* (2) the size of this array is -1, if b == 0 (error)
*
* In case (2) the compiler throws an error.
* e.g. msvc compiler:
* error C2118: negative subscript or subscript is too large
* e.g. gcc 2.95.3:
* size of array `_compile_time_assertion_failed_in_line_555' is negative
*
* In case the condition 'b' is not constant, the msvc compiler throws
* an error:
* error C2057: expected constant expression
* In this case the run time assert() must be used.
*
* For C++ code, we use a different technique because the function prototype
* declaration can have function linkage conflicts. If a single compilation
* unit has ct_assert() statements on the same line number in two different
* files, we would have:
*
* compile_time_assertion_failed_in_line_777(...); from xxx.cpp
* compile_time_assertion_failed_in_line_777(...); from xxx.h
*
* That is valid C++. But if either declaration were in an extern "C" block,
* the same function would be declared with two different linkage types and an
* error would ensue.
*
* Instead, ct_assert() for C++ simply declares an array typedef. As in the C
* version, we will get a compilation error if a typedef with a negative size
* is specified. Line numbers are not needed because C++ allows redundant
* typedefs as long as they are all defined the same way. But we tack them on
* anyway in case the typedef name is reported in compiler errors. C does not
* permit redundant typedefs, so this version should not be used in true C
* code. It can be used in extern "C" blocks of C++ code, however. As with
* the C version, MSVC will throw a "negative subscript" or "expected constant
* expression" error if the expression asserted is false or non-constant.
*
* Notes:
* - This ct_assert() does *not* generate any code or variable.
* Therefore there is no need to define it away for RELEASE builds.
* - The integration of the current source file number (__LINE__) ...
* ... would be required in C++ to allow multiple use inside the same
* class/namespace (if we used the C-style expansion), because the id
* must be unique.
* ... is nice to have in C or C++ if the compiler's error message contains
* the id (this is not the case for msvc)
* - Using three nested macros instead of only one is necessary to get the id
* compile_time_assertion_failed_in_line_555
* instead of
* compile_time_assertion_failed_in_line___LINE__
*/
#if defined(__clang__)
# ifndef __has_extension
# define __has_extension __has_feature // Compatibility with Clang pre-3.0 compilers.
# endif
# define CLANG_C_STATIC_ASSERT __has_extension(c_static_assert)
#else
# define CLANG_C_STATIC_ASSERT 0
#endif
// Adding this macro to fix MISRA 2012 rule 20.12
#define NV_CTASSERT_STRINGIFY_MACRO(b) #b
#if !defined(NVOC) && ((defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) || CLANG_C_STATIC_ASSERT)
// ISO C11 defines the _Static_assert keyword
# define ct_assert(b) _Static_assert((b), "Compile time assertion failed: " NV_CTASSERT_STRINGIFY_MACRO(b))
# define ct_assert_i(b,line) _Static_assert((b), "Compile time assertion failed: " NV_CTASSERT_STRINGIFY_MACRO(b)NV_CTASSERT_STRINGIFY_MACRO(line))
#elif (defined(__cplusplus) && __cplusplus >= 201103L) || (defined(_MSVC_LANG) && _MSVC_LANG >= 201103L)
// ISO C++11 defines the static_assert keyword
# define ct_assert(b) static_assert((b), "Compile time assertion failed: " NV_CTASSERT_STRINGIFY_MACRO(b))
# define ct_assert_i(b,line) static_assert((b), "Compile time assertion failed: " NV_CTASSERT_STRINGIFY_MACRO(b)NV_CTASSERT_STRINGIFY_MACRO(line))
#else
// For compilers which don't support ISO C11 or C++11, we fall back to an
// array (type) declaration
# define ct_assert(b) ct_assert_i(b,__LINE__)
# define ct_assert_i(b,line) ct_assert_ii(b,line)
# ifdef __cplusplus
# define ct_assert_ii(b,line) typedef char compile_time_assertion_failed_in_line_##line[(b)?1:-1]
# else
/*
* The use of a function prototype "void compile_time_assertion_failed_in_line_##line(..)
* above violates MISRA-C 2012 Rule 8.6 since the rule disallows a function
* declaration without a definition. To fix the MISRA rule, the cplusplus style
* 'typdef char compile_time_assertion_failed_in_line_##line'
* is acceptable, but doesn't work for typical C code since there can be duplicate
* line numbers leading to duplicate typedefs which C doesn't allow.
*
* The following macro uses the predefined macro __COUNTER__ to create unique
* typedefs that fixes the MISRA violations. However, not all C compilers support
* that macro and even for compilers that support it, the underlying code makes
* use of variably modified identifiers in ct_assert that makes the use of this
* unviable.
*
* For now restrict the use of MACRO only on
* i) GCC 4.3.0 and above that supports __COUNTER__ macro
* ii) Specifically the Falcon port of the compiler since the use of variably
* modified identifiers have been removed on those projects
*
* TBD: Enable the macro on MSVC and CLANG pending
*/
# if defined(__GNUC__) && ((__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) >= 40300) && defined(GCC_FALCON)
# define ct_assert_ii(b,line) ct_assert_iii(b,line,__COUNTER__)
# define ct_assert_iii(b,line,cntr) ct_assert_cntr(b,line,cntr)
# define ct_assert_cntr(b,line,cntr) typedef char cnt##cntr##_compile_time_assertion_failed_in_line_##line[(b)?1:-1] __attribute__((unused))
# else
# define ct_assert_ii(b,line) void compile_time_assertion_failed_in_line_##line(int _compile_time_assertion_failed_in_line_##line[(b) ? 1 : -1])
# endif
# endif
#endif
#endif // __NV_CTASSERT_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _NVEGPUCONFIG_H_
#define _NVEGPUCONFIG_H_
#include <nvtypes.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
#define EGPU_INLINE NV_FORCEINLINE
#else //!__cplusplus
#if defined(NV_UNIX) || defined(NVCPU_RISCV64) || defined(NV_MODS)
#define EGPU_INLINE static NV_INLINE
#else //NV_UNIX
#define EGPU_INLINE NV_INLINE
#endif //NV_UNIX
#endif //!__cplusplus
// Surprise removal capable TB3 and TB2 BUS Device ID
#define BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01 0x1578
#define BUS_DEVICE_ID_TB3_02 0x1576
#define BUS_DEVICE_ID_TB3_03 0x15C0
#define BUS_DEVICE_ID_TB3_04 0x15D3
#define BUS_DEVICE_ID_TB3_05 0x15DA
#define BUS_DEVICE_ID_TB3_06 0x15EA
#define BUS_DEVICE_ID_TB3_07 0x15E7
#define BUS_DEVICE_ID_TB3_08 0x15EF
#define BUS_DEVICE_ID_TB3_09 0x1133
#define BUS_DEVICE_ID_TB3_10 0x1136
// IceLake-U TB3 device ids. Below TB3 would be integrated to CPU.
#define BUS_DEVICE_ID_ICELAKE_TB3_01 0x8A1D
#define BUS_DEVICE_ID_ICELAKE_TB3_02 0x8A1F
#define BUS_DEVICE_ID_ICELAKE_TB3_03 0x8A21
#define BUS_DEVICE_ID_ICELAKE_TB3_04 0x8A23
#define BUS_DEVICE_ID_ICELAKE_TB3_05 0x8A0D
#define BUS_DEVICE_ID_ICELAKE_TB3_06 0x8A17
// TigerLake Thunderbolt device ids.
#define BUS_DEVICE_ID_TIGERLAKE_TB3_01 0x9A1B
#define BUS_DEVICE_ID_TIGERLAKE_TB3_02 0x9A1D
#define BUS_DEVICE_ID_TIGERLAKE_TB3_03 0x9A1F
#define BUS_DEVICE_ID_TIGERLAKE_TB3_04 0x9A21
#define BUS_DEVICE_ID_TIGERLAKE_TB3_05 0x9A23
#define BUS_DEVICE_ID_TIGERLAKE_TB3_06 0x9A25
#define BUS_DEVICE_ID_TIGERLAKE_TB3_07 0x9A27
#define BUS_DEVICE_ID_TIGERLAKE_TB3_08 0x9A29
#define BUS_DEVICE_ID_TIGERLAKE_TB3_09 0x9A2B
#define BUS_DEVICE_ID_TIGERLAKE_TB3_10 0x9A2D
//#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_01 0X156C // obsolete
#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02 0X156D
#define BUS_DEVICE_ID_TB2_03 0x157E
#define BUS_DEVICE_ID_TB2_04 0x156B
#define BUS_DEVICE_ID_TB2_05 0x1567
#define BUS_DEVICE_ID_TB2_06 0x1569
//#define BUS_DEVICE_ID_TB2_07 0x1548 // obsolete
#define BUS_DEVICE_ID_TB2_08 0x151B
#define BUS_DEVICE_ID_TB2_09 0x1549
#define BUS_DEVICE_ID_TB2_10 0x1513
//*****************************************************************************
// Function: isTB3DeviceID
//
// Routine Description:
//
// Function to match the specified Device ID with the known TB3 BUS's
// device IDs.
//
// Arguments:
//
// deviceID[IN]: Device ID to match with the TB3 Bus
//
// Return Value:
//
// true: When the passed Dev ID match with TB3's BUS Device ID
// false: When the passed Dev ID is not matching with known TB3's
// BUS Device ID
//*****************************************************************************
EGPU_INLINE NvBool isTB3DeviceID(NvU16 deviceID)
{
NvU32 index;
NvU16 tb3DeviceIDList[]={ BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01,
BUS_DEVICE_ID_TB3_02,
BUS_DEVICE_ID_TB3_03,
BUS_DEVICE_ID_TB3_04,
BUS_DEVICE_ID_TB3_05,
BUS_DEVICE_ID_TB3_06,
BUS_DEVICE_ID_TB3_07,
BUS_DEVICE_ID_TB3_08,
BUS_DEVICE_ID_TB3_09,
BUS_DEVICE_ID_TB3_10,
BUS_DEVICE_ID_ICELAKE_TB3_01,
BUS_DEVICE_ID_ICELAKE_TB3_02,
BUS_DEVICE_ID_ICELAKE_TB3_03,
BUS_DEVICE_ID_ICELAKE_TB3_04,
BUS_DEVICE_ID_ICELAKE_TB3_05,
BUS_DEVICE_ID_ICELAKE_TB3_06,
BUS_DEVICE_ID_TIGERLAKE_TB3_01,
BUS_DEVICE_ID_TIGERLAKE_TB3_02,
BUS_DEVICE_ID_TIGERLAKE_TB3_03,
BUS_DEVICE_ID_TIGERLAKE_TB3_04,
BUS_DEVICE_ID_TIGERLAKE_TB3_05,
BUS_DEVICE_ID_TIGERLAKE_TB3_06,
BUS_DEVICE_ID_TIGERLAKE_TB3_07,
BUS_DEVICE_ID_TIGERLAKE_TB3_08,
BUS_DEVICE_ID_TIGERLAKE_TB3_09,
BUS_DEVICE_ID_TIGERLAKE_TB3_10
};
for (index = 0; index < (sizeof(tb3DeviceIDList)/sizeof(NvU16)); index++)
{
if (deviceID == tb3DeviceIDList[index])
{
return NV_TRUE;
}
}
return NV_FALSE;
} // isTB3DeviceID
//*****************************************************************************
// Function: isTB2DeviceID
//
// Routine Description:
//
// Function to match the specified Device ID with the known TB2 BUS's
// device IDs.
//
// Arguments:
//
// deviceID[IN]: Device ID to match with the TB2 Bus
//
// Return Value:
//
// true: When the passed Dev ID match with TB2's BUS Device ID
// false: When the passed Dev ID is not matching with known TB2's
// BUS Device ID
//*****************************************************************************
EGPU_INLINE NvBool isTB2DeviceID(NvU16 deviceID)
{
NvU32 index;
NvU16 tb2DeviceIDList[]={ BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02,
BUS_DEVICE_ID_TB2_03, BUS_DEVICE_ID_TB2_04,
BUS_DEVICE_ID_TB2_05, BUS_DEVICE_ID_TB2_06,
BUS_DEVICE_ID_TB2_08, BUS_DEVICE_ID_TB2_09,
BUS_DEVICE_ID_TB2_10
};
for (index = 0; index < (sizeof(tb2DeviceIDList)/sizeof(NvU16)); index++)
{
if (deviceID == tb2DeviceIDList[index])
{
return NV_TRUE;
}
}
return NV_FALSE;
} // isTB2DeviceID
#ifdef __cplusplus
}
#endif
#endif //_NVEGPUCONFIG_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _NVLOG_DEFS_H_
#define _NVLOG_DEFS_H_
#include "nvtypes.h"
/******************* Common Debug & Trace Defines ***************************\
* *
* Module: NVLOG_DEFS.H *
* *
\****************************************************************************/
#define NVLOG_MAX_DBG_MODULES 256
/********************************/
/********* Structures *********/
/********************************/
// Forward declaration, so it can be used in the function type definition.
/**
* @brief Struct representing a buffer in NvLog
*
* All logging (Print, Regtrace, etc) use these buffers.
*/
typedef struct _NVLOG_BUFFER NVLOG_BUFFER;
/**
* @brief Type of the 'push' function for NvLog buffers
*
* Function called whenever pushing something to an NvLog buffer
*/
typedef NvBool (*NVLOG_BUFFER_PUSHFUNC) (NVLOG_BUFFER *, NvU8 *, NvU32);
/**
* @brief Fields specific to ring buffers
*/
typedef struct _NVLOG_RING_BUFFER_EXTRA_FIELDS
{
/** How many times the ring buffer has overflown */
NvU32 overflow;
} NVLOG_RING_BUFFER_EXTRA_FIELDS;
/**
* @brief Struct representing a buffer in NvLog
*
* All logging (Print, Regtrace, etc) use these buffers.
*/
struct _NVLOG_BUFFER
{
/** Function to call when writing to this buffer */
union
{
NVLOG_BUFFER_PUSHFUNC fn;
// Pad this union to prevent struct size from varying between 32/64 bit platforms
NvP64 padding;
} push;
/** Size of the buffer data section */
NvU32 size;
/** Buffer tag, for easier identification in a dump */
NvU32 tag;
/** Flags of the buffer, following NVLOG_BUFFER_FLAGS_* DRF's */
NvU32 flags;
/** Position of the next available byte in the buffer */
NvU32 pos;
/** Number of threads currently writing to this buffer */
volatile NvS32 threadCount;
/** Specific buffer types will define their fields here */
union
{
NVLOG_RING_BUFFER_EXTRA_FIELDS ring;
} extra;
/** Buffer data. */
NvU8 data[1];
};
#define NVLOG_MAX_BUFFERS_v11 16
#define NVLOG_MAX_BUFFERS_v12 256
#if NVOS_IS_UNIX
#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v12
#define NVLOG_LOGGER_VERSION 12 // v1.2
#else
#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v11
#define NVLOG_LOGGER_VERSION 11 // v1.1
#endif // NVOS_IS_UNIX
//
// Due to this file's peculiar location, NvPort may or may not be includable
// This hack will go away when NvLog is moved into common/shared
//
#if NVOS_IS_MACINTOSH
#if !PORT_IS_KERNEL_BUILD
typedef struct PORT_SPINLOCK PORT_SPINLOCK;
#else
#include "nvport/nvport.h"
#endif
#elif !defined(PORT_IS_KERNEL_BUILD)
typedef struct PORT_SPINLOCK PORT_SPINLOCK;
#else
#include "nvport/nvport.h"
#endif
/**
* @brief Information about the entire NvLog system
*/
typedef struct _NVLOG_LOGGER
{
/** NvLog logger version */
NvU32 version;
/** Logging buffers */
NVLOG_BUFFER * pBuffers[NVLOG_MAX_BUFFERS];
/** Index of the first unallocated buffer */
NvU32 nextFree;
/** Total number of free buffer slots */
NvU32 totalFree;
/** Lock for all buffer oprations */
PORT_SPINLOCK* mainLock;
} NVLOG_LOGGER;
extern NVLOG_LOGGER NvLogLogger;
//
// Buffer flags
//
// Logging to this buffer is disabled
#define NVLOG_BUFFER_FLAGS_DISABLED 0:0
#define NVLOG_BUFFER_FLAGS_DISABLED_NO 0
#define NVLOG_BUFFER_FLAGS_DISABLED_YES 1
#define NVLOG_BUFFER_FLAGS_TYPE 2:1
#define NVLOG_BUFFER_FLAGS_TYPE_RING 0
#define NVLOG_BUFFER_FLAGS_TYPE_NOWRAP 1
#define NVLOG_BUFFER_FLAGS_TYPE_SYSTEMLOG 2
// Expand buffer when full
#define NVLOG_BUFFER_FLAGS_EXPANDABLE 3:3
#define NVLOG_BUFFER_FLAGS_EXPANDABLE_NO 0
#define NVLOG_BUFFER_FLAGS_EXPANDABLE_YES 1
// Allocate buffer in non paged memory
#define NVLOG_BUFFER_FLAGS_NONPAGED 4:4
#define NVLOG_BUFFER_FLAGS_NONPAGED_NO 0
#define NVLOG_BUFFER_FLAGS_NONPAGED_YES 1
//
// Type of buffer locking to use
// NONE - No locking performed, for buffers that are inherently single threaded
// STATE - Lock only during state change, do memory copying unlocked
// Don't use with tiny buffers that overflow every write or two.
// FULL - Keep everything locked for the full duration of the write
//
#define NVLOG_BUFFER_FLAGS_LOCKING 6:5
#define NVLOG_BUFFER_FLAGS_LOCKING_NONE 0
#define NVLOG_BUFFER_FLAGS_LOCKING_STATE 1
#define NVLOG_BUFFER_FLAGS_LOCKING_FULL 2
// Store this buffer in OCA minidumps
#define NVLOG_BUFFER_FLAGS_OCA 7:7
#define NVLOG_BUFFER_FLAGS_OCA_NO 0
#define NVLOG_BUFFER_FLAGS_OCA_YES 1
// Buffer format (not included in registry key)
#define NVLOG_BUFFER_FLAGS_FORMAT 10:8
#define NVLOG_BUFFER_FLAGS_FORMAT_PRINTF 0
#define NVLOG_BUFFER_FLAGS_FORMAT_LIBOS_LOG 1
#define NVLOG_BUFFER_FLAGS_FORMAT_MEMTRACK 2
// Buffer GPU index
#define NVLOG_BUFFER_FLAGS_GPU_INSTANCE 31:24
typedef NvU32 NVLOG_BUFFER_HANDLE;
//
// Utility macros
//
#define NVLOG_IS_RING_BUFFER(pBuffer) \
FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _TYPE, _RING, pBuffer->flags)
#define NVLOG_IS_NOWRAP_BUFFER(pBuffer) \
FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _TYPE, _NOWRAP, pBuffer->flags)
#define NVLOG_PRINT_BUFFER_SIZE(pBuffer) ((pBuffer)->size)
#define NVLOG_BUFFER_SIZE(pBuffer) \
(NV_OFFSETOF(NVLOG_BUFFER, data) + NVLOG_PRINT_BUFFER_SIZE(pBuffer))
/********************************/
/********* Filtering **********/
/********************************/
// TODO - Remove all this once tools are updated
#define NVLOG_FILTER_INVALID (~0)
#define NVLOG_FILTER_VALUE_SIMPLE_NO 0x0
#define NVLOG_FILTER_VALUE_SIMPLE_YES 0x1
#define NVLOG_FILTER_VALUE_EXPLICIT_NO 0x2
#define NVLOG_FILTER_VALUE_EXPLICIT_YES 0x3
#define NVLOG_FILTER_PRINT_LEVEL_REGTRACE 1:0
#define NVLOG_FILTER_PRINT_LEVEL_INFO 3:2
#define NVLOG_FILTER_PRINT_LEVEL_NOTICE 5:4
#define NVLOG_FILTER_PRINT_LEVEL_WARNINGS 7:6
#define NVLOG_FILTER_PRINT_LEVEL_ERRORS 9:8
#define NVLOG_FILTER_PRINT_LEVEL_HW_ERROR 11:10
#define NVLOG_FILTER_PRINT_LEVEL_FATAL 13:12
#define NVLOG_FILTER_PRINT_BUFFER 18:14
#define NVLOG_FILTER_REGTRACE_BUFFER 22:19
#define NVLOG_FILTER_REGTRACE_LOG_READ 25:23
#define NVLOG_FILTER_REGTRACE_LOG_WRITE 27:26
#define NVLOG_FILTER_REGTRACE_BREAK_READ 29:28
#define NVLOG_FILTER_REGTRACE_BREAK_WRITE 31:30
#define NVLOG_FILTER_VALUE_IS_NO(val) ((val & 0x1) == 0)
#define NVLOG_FILTER_VALUE_IS_YES(val) (val & 0x1)
#define NVLOG_FILTER_PRINT_GET_VALUE(level, num) ((num >> (level*2)) & 0x3)
/**
* @brief Type representing a value of a given 16bit range.
*/
typedef struct _NVLOG_RANGE_16
{
NvU16 low;
NvU16 high;
NvU32 value;
} NVLOG_RANGE_16;
/**
* @brief Type representing a value of a given 32bit range.
*/
typedef struct _NVLOG_RANGE_32
{
NvU32 low;
NvU32 high;
NvU32 value;
} NVLOG_RANGE_32;
//
// Maximum number of files that have a filter assigned to them.
//
#define NVLOG_MAX_FILES 1
//
// Maximum number of line rules (both single line and range) allowed per file
//
#define NVLOG_FILELINE_FILTER_MAX_RANGES 1
/**
* @brief Internal type for NVLOG_FILELINE_FILTER.
*
* Contains filtering info for a single file.
*/
typedef struct _NVLOG_FILELINE_FILTER_FILEHASH
{
/** ID of the file (24bit MD5) */
NvU32 fileId;
/** Number of elements in the array 'ranges' */
NvU32 numElems;
/** Value to use if the given value isn't found in the range array */
NvU32 defaultValue;
/** Array of ranges representing lines in the file */
NVLOG_RANGE_16 ranges[NVLOG_FILELINE_FILTER_MAX_RANGES];
} NVLOG_FILELINE_FILTER_FILEHASH;
/**
* @brief Filter that contains rules that depend on the file and line number.
*/
typedef struct _NVLOG_FILELINE_FILTER
{
/** Number of elements in the fileHash array */
NvU32 numFiles;
/** Value to use if a given file isn't found */
NvU32 defaultValue;
/** Array of file entries, ordered as a hash table */
NVLOG_FILELINE_FILTER_FILEHASH fileHash[NVLOG_MAX_FILES];
} NVLOG_FILELINE_FILTER;
/********************************/
/********* Print Logger *********/
/********************************/
#define NVLOG_PRINT_LOGGER_VERSION 11 // v1.1
// Max buffers cannot be over 32.
#define NVLOG_PRINT_MAX_BUFFERS 8
#define NVLOG_PRINT_BUFFER_PRIMARY 1
#define NVLOG_PRINT_BUFFER_SECONDARY 2
#define NVLOG_PRINT_BUFFER_SYSTEMLOG 3
#define NVLOG_PRINT_DESC1_FILEID 23:0
#define NVLOG_PRINT_DESC1_GPUID 28:24 // 2^5 = 32 possible
#define NVLOG_PRINT_DESC1_MAGIC 31:29
#define NVLOG_PRINT_DESC1_MAGIC_VALUE 5
#define NVLOG_PRINT_DESC2_LINEID 15:0
#define NVLOG_PRINT_DESC2_GROUPID 17:16
#define NVLOG_PRINT_DESC2_GROUPID_RM 0
#define NVLOG_PRINT_DESC2_GROUPID_PMU 1
#define NVLOG_PRINT_DESC2_OPT_DATA_COUNT 24:18 // number of dwords
#define NVLOG_PRINT_DESC2_OPT_DATA_COUNT_MAX 0x7F
#define NVLOG_PRINT_DESC2_RESERVED 28:25
#define NVLOG_PRINT_DESC2_MAGIC 31:29
#define NVLOG_PRINT_DESC2_MAGIC_VALUE 6
#define NVLOG_UNKNOWN_GPU_INSTANCE 0x1f
#define NVLOG_PRINT_MODULE_FILTER_VALUE 1:0
#define NVLOG_PRINT_MODULE_FILTER_BUFFER 6:2
#define NVLOG_PRINT_MODULE_FILTER_ENABLED 7:7
//
// Regkey fields - These are copied directly from nvRmReg.h
// A copy is necessary as these might be needed on systems that don't
// have nvRmReg.h, such as DVS builds for NvWatch
//
#ifndef NV_REG_STR_RM_NVLOG
#define NV_REG_STR_RM_NVLOG "RMNvLog"
#define NV_REG_STR_RM_NVLOG_BUFFER_FLAGS 7:0
#define NV_REG_STR_RM_NVLOG_BUFFER_SIZE 23:8
#define NV_REG_STR_RM_NVLOG_BUFFER_SIZE_DEFAULT ((NVOS_IS_WINDOWS||NVOS_IS_MACINTOSH)?8:250)
#define NV_REG_STR_RM_NVLOG_BUFFER_SIZE_DISABLE 0
#define NV_REG_STR_RM_NVLOG_RUNTIME_LEVEL 28:25
#define NV_REG_STR_RM_NVLOG_TIMESTAMP 30:29
#define NV_REG_STR_RM_NVLOG_TIMESTAMP_NONE 0
#define NV_REG_STR_RM_NVLOG_TIMESTAMP_32 1
#define NV_REG_STR_RM_NVLOG_TIMESTAMP_64 2
#define NV_REG_STR_RM_NVLOG_TIMESTAMP_32_DIFF 3
#define NV_REG_STR_RM_NVLOG_INITED 31:31
#define NV_REG_STR_RM_NVLOG_INITED_NO 0
#define NV_REG_STR_RM_NVLOG_INITED_YES 1
#endif // NV_REG_STR_RM_NVLOG
//
// Arg types:
// 0: Special meaning. End of argument list.
// 1: d, u, x, X, i, o - Integer type
// 2: lld, llu, llx, llX, lli, llo - Long long integer type
// 3: s - string type (size is 0)
// 4: p - pointer type
// 5: c - char type
// 6: f, g, e, F, G, E - floating point type
// 7-14: Unused at the moment, default value is 0
// 15: Special meaning. Error value - unsupported type.
//
#define NVLOG_PRINT_MAX_ARG_TYPES 0x10
#define NVLOG_PRINT_ARG_TYPE_ARGLIST_END 0x0
#define NVLOG_PRINT_ARG_TYPE_INT 0x1
#define NVLOG_PRINT_ARG_TYPE_LONGLONG 0x2
#define NVLOG_PRINT_ARG_TYPE_STRING 0x3
#define NVLOG_PRINT_ARG_TYPE_POINTER 0x4
#define NVLOG_PRINT_ARG_TYPE_CHAR 0x5
#define NVLOG_PRINT_ARG_TYPE_FLOAT 0x6
#define NVLOG_PRINT_ARG_TYPE_ERROR 0xf
/**
* @brief Signature of the database required to decode the print logs
*
* The sig1-sig3 values are generated randomly at compile time.
*/
typedef struct _NVLOG_DB_SIGNATURE
{
NvU32 timestamp;
NvU32 sig1;
NvU32 sig2;
NvU32 sig3;
} NVLOG_DB_SIGNATURE;
/**
* @brief Filter that contains all rules used to filter DBG_PRINTF calls
*/
typedef struct _NVLOG_PRINT_FILTER
{
/** Same file:line filter is shared with the Regtrace system */
NVLOG_FILELINE_FILTER *pFileLineFilter;
/** Filter based on debug levels. Uses NVLOG_FILTER_PRINT_LEVEL_* DRF's */
NvU32 runtimePrintLevelFilter;
/** Filter based on debug modules. Uses NVLOG_PRINT_MODULE_FILTER_* DRF's */
NvU8 runtimePrintModuleFilter[NVLOG_MAX_DBG_MODULES];
} NVLOG_PRINT_FILTER;
/**
* @brief Enum representing all possible argument types to DBG_PRINTF
*/
typedef enum _NVLOG_ARGTYPE
{
NVLOG_ARGTYPE_NONE,
NVLOG_ARGTYPE_INT,
NVLOG_ARGTYPE_LONG_LONG_INT,
NVLOG_ARGTYPE_STRING,
NVLOG_ARGTYPE_POINTER,
NVLOG_ARGTYPE_FLOAT,
NVLOG_ARGTYPE__COUNT
} NVLOG_ARGTYPE;
/**
* @brief General info about the NvLog Print system
*/
typedef struct _NVLOG_PRINT_LOGGER
{
/** NvLog print logger version */
NvU32 version;
/** Runtime argument sizes (16 different arglist values) */
NvU8 runtimeSizes[NVLOG_PRINT_MAX_ARG_TYPES];
/** Database signature for decoding */
NVLOG_DB_SIGNATURE signature;
/** Filter buffer for print statements */
NVLOG_PRINT_FILTER filter;
/** Flags for all NvLog print buffers */
NvU32 flags;
/** Buffer indices for all nvlog buffers. buffers[1] is default. */
NvU32 buffers[NVLOG_PRINT_MAX_BUFFERS];
/** Initialized flag, set to true after nvlogPrintInit has executed */
NvBool initialized;
/** Paused flag, set to true after nvlogPrintInit has executed */
NvBool paused;
} NVLOG_PRINT_LOGGER;
extern NVLOG_PRINT_LOGGER NvLogPrintLogger;
#define NVLOG_PRINT_BUFFER_TAG(_i) NvU32_BUILD('t','r','p','0' + (_i))
/********************************/
/********** Regtrace **********/
/********************************/
#define NVLOG_REGTRACE_LOGGER_VERSION 10 // v1.0
#define NVLOG_REGTRACE_MAX_BUFFERS 4
#define NVLOG_REGTRACE_READ 0
#define NVLOG_REGTRACE_WRITE 1
#define NVLOG_REGTRACE_DESC1_FILEID NVLOG_PRINT_DESC1_FILEID
#define NVLOG_REGTRACE_DESC1_GPUID NVLOG_PRINT_DESC1_GPUID
#define NVLOG_REGTRACE_DESC1_MAGIC NVLOG_PRINT_DESC1_MAGIC
#define NVLOG_REGTRACE_DESC1_MAGIC_VALUE (NVLOG_PRINT_DESC1_MAGIC_VALUE-1)
#define NVLOG_REGTRACE_DESC2_LINEID 15:0
#define NVLOG_REGTRACE_DESC2_READWRITE 16:16
#define NVLOG_REGTRACE_DESC2_READWRITE_READ NVLOG_REGTRACE_READ
#define NVLOG_REGTRACE_DESC2_READWRITE_WRITE NVLOG_REGTRACE_WRITE
#define NVLOG_REGTRACE_DESC2_REGSIZE 18:17
#define NVLOG_REGTRACE_DESC2_REGSIZE_8 0
#define NVLOG_REGTRACE_DESC2_REGSIZE_16 1
#define NVLOG_REGTRACE_DESC2_REGSIZE_32 2
#define NVLOG_REGTRACE_DESC2_REGSIZE_64 3
#define NVLOG_REGTRACE_DESC2_THREADID 28:19
#define NVLOG_REGTRACE_DESC2_MAGIC 31:29
#define NVLOG_REGTRACE_DESC2_MAGIC_VALUE 3
/**
* @brief Single entry in an NvLog Regtrace buffer.
*/
typedef struct _NVLOG_REGTRACE_RECORD
{
/** Uses NVLOG_REGTRACE_DESC1_* DRF's */
NvU32 desc1;
/** Uses NVLOG_REGTRACE_DESC1_* DRF's */
NvU32 desc2;
/** Address of the register being accessed */
NvU32 address;
/** Value that was read/written */
NvU32 value;
} NVLOG_REGTRACE_RECORD;
#define NVLOG_REGTRACE_FILTER_MAX_RANGES 256
// Regtrace shares the file:line filter with print
/**
* @brief Filter that contains all rules used to filter register access logging
*/
typedef struct _NVLOG_REGTRACE_FILTER
{
/** Number of elements in the 'ranges' array */
NvU32 numRanges;
/** File:line based filter. Shared with NvLog print system */
NVLOG_FILELINE_FILTER *pFileLineFilter;
/** Range array for filtering based on register addresses */
NVLOG_RANGE_32 ranges[NVLOG_REGTRACE_FILTER_MAX_RANGES];
} NVLOG_REGTRACE_FILTER;
/**
* @brief General info about the NvLog Regtrace system
*/
typedef struct _NVLOG_REGTRACE_LOGGER
{
/** NvLog regtrace logger version */
NvU32 version;
/** Filter buffer for regtrace statements */
NVLOG_REGTRACE_FILTER filter;
/** Buffer indices for all NvLog buffers. First element is default buffer */
NvU32 buffers[NVLOG_REGTRACE_MAX_BUFFERS];
} NVLOG_REGTRACE_LOGGER;
#endif // _NVLOG_DEFS_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2016 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
//
// This file must not have include guards, it is supposed to be included
// multiple times - Once in a precompiled header, once through noprecomp.h
//
// WAR for a GCC precompiled headers problem
#if !defined(NV_RM_PRECOMPILED_HEADER)
#include "nvlog_inc2.h"
//
// If noprecomp is not included, this will not expand and will result in an
// undefined identifier. Hopefully, the meaningful name will hint at the
// underlying problem.
//
#define ___please_include_noprecomp_h___
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 2013,2016-2017,2020-2020 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _NVLOG_INC2_H_
#define _NVLOG_INC2_H_
//
// Include the auto-generated g_$(filename)-nvlog.h header. The file contains
// information about the trace statements that was pulled out by the NvLog preprocessor.
// NVLOG_INCLUDE is defined by make at compile time, for every source file.
//
// The four lines of macros is some trickiness needed to make it work.
//
#if (defined(NVLOG_ENABLED) || defined(NV_MODS)) && defined(NVLOG_INCLUDE) && !defined(NVLOG_PARSING)
#if NVLOG_ENABLED || defined(NV_MODS)
#ifndef NVLOG_FILEID // Acts as an include guard
#define NVLOG_INCLUDE3(a) #a
#define NVLOG_INCLUDE2(a) NVLOG_INCLUDE3 a
#define NVLOG_INCLUDE1 NVLOG_INCLUDE2((NVLOG_INCLUDE))
#include NVLOG_INCLUDE1
#endif // NVLOG_FILEID
#endif // NVLOG_ENABLED
#endif // defined(NVLOG_ENABLED) && defined(NVLOG_INCLUDE)
#endif // _NVLOG_INC2_H_

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/*
* Lightweight protocol buffers.
*
* Based on code taken from
* https://code.google.com/archive/p/lwpb/source/default/source
*
* The code there is licensed as Apache 2.0. However, NVIDIA has received the
* code from the original author under MIT license terms.
*
*
* Copyright 2009 Simon Kallweit
* Copyright 2010-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* This file contains the definitions used by the code generated
* by the protobuf compiler.
*/
#ifndef __PRBRT_H__
#define __PRBRT_H__
// Maximum depth of message embedding
#ifndef PRB_MAX_DEPTH
#define PRB_MAX_DEPTH 8
#endif
// Maximum number of required fields in a message
#ifndef PRB_MAX_REQUIRED_FIELDS
#define PRB_MAX_REQUIRED_FIELDS 16
#endif
// Provide enum names as strings
#ifndef PRB_ENUM_NAMES
#define PRB_ENUM_NAMES 0
#endif
#if PRB_ENUM_NAMES
#define PRB_MAYBE_ENUM_NAME(n) n,
#else
#define PRB_MAYBE_ENUM_NAME(n)
#endif
// Provide field names as strings
#ifndef PRB_FIELD_NAMES
#define PRB_FIELD_NAMES 0
#endif
#if PRB_FIELD_NAMES
#define PRB_MAYBE_FIELD_NAME(n) n,
#else
#define PRB_MAYBE_FIELD_NAME(n)
#endif
// Provide field default values
#ifndef PRB_FIELD_DEFAULTS
#define PRB_FIELD_DEFAULTS 0
#endif
#if PRB_FIELD_DEFAULTS
#define PRB_MAYBE_FIELD_DEFAULT_DEF(n) n
#define PRB_MAYBE_FIELD_DEFAULT(n) n,
#else
#define PRB_MAYBE_FIELD_DEFAULT_DEF(n)
#define PRB_MAYBE_FIELD_DEFAULT(n)
#endif
// Provide message names as strings
#ifndef PRB_MESSAGE_NAMES
#define PRB_MESSAGE_NAMES 0
#endif
#if PRB_MESSAGE_NAMES
#define PRB_MAYBE_MESSAGE_NAME(n) n,
#else
#define PRB_MAYBE_MESSAGE_NAME(n)
#endif
// Provide method names as strings
#ifndef PRB_METHOD_NAMES
#define PRB_METHOD_NAMES 0
#endif
#if PRB_METHOD_NAMES
#define PRB_MAYBE_METHOD_NAME(n) n,
#else
#define PRB_MAYBE_METHOD_NAME(n)
#endif
// Provide service names as strings
#ifndef PRB_SERVICE_NAMES
#define PRB_SERVICE_NAMES 0
#endif
#if PRB_SERVICE_NAMES
#define PRB_MAYBE_SERVICE_NAME(n) n,
#else
#define PRB_MAYBE_SERVICE_NAME(n)
#endif
// Field labels
#define PRB_REQUIRED 0
#define PRB_OPTIONAL 1
#define PRB_REPEATED 2
// Field value types
#define PRB_DOUBLE 0
#define PRB_FLOAT 1
#define PRB_INT32 2
#define PRB_INT64 3
#define PRB_UINT32 4
#define PRB_UINT64 5
#define PRB_SINT32 6
#define PRB_SINT64 7
#define PRB_FIXED32 8
#define PRB_FIXED64 9
#define PRB_SFIXED32 10
#define PRB_SFIXED64 11
#define PRB_BOOL 12
#define PRB_ENUM 13
#define PRB_STRING 14
#define PRB_BYTES 15
#define PRB_MESSAGE 16
// Field flags
#define PRB_HAS_DEFAULT (1 << 0)
#define PRB_IS_PACKED (1 << 1)
#define PRB_IS_DEPRECATED (1 << 2)
typedef struct
{
unsigned int label : 2;
unsigned int typ : 6;
unsigned int flags : 8;
} PRB_FIELD_OPTS;
// Protocol buffer wire types
typedef enum
{
WT_VARINT = 0,
WT_64BIT = 1,
WT_STRING = 2,
WT_32BIT = 5
} WIRE_TYPE;
// Protocol buffer wire values
typedef union
{
NvU64 varint;
NvU64 int64;
struct {
NvU64 len;
const void *data;
} string;
NvU32 int32;
} WIRE_VALUE;
typedef struct
{
char *str;
NvU32 len;
} PRB_VALUE_STRING;
typedef struct
{
NvU8 *data;
NvU32 len;
} PRB_VALUE_BYTES;
typedef struct
{
void *data;
NvU32 len;
} PRB_VALUE_MESSAGE;
typedef union
{
NvF64 double_;
NvF32 float_;
NvS32 int32;
NvS64 int64;
NvU32 uint32;
NvU64 uint64;
NvBool bool_;
PRB_VALUE_STRING string;
PRB_VALUE_BYTES bytes;
PRB_VALUE_MESSAGE message;
int enum_;
int null;
} PRB_VALUE;
typedef struct
{
int value;
#if PRB_ENUM_NAMES
const char *name;
#endif
} PRB_ENUM_MAPPING;
typedef struct
{
const PRB_ENUM_MAPPING *mappings;
NvU32 count;
#if PRB_ENUM_NAMES
const char *name;
#endif
} PRB_ENUM_DESC;
struct PRB_MSG_DESC;
//* Protocol buffer field descriptor
typedef struct PRB_FIELD_DESC
{
NvU32 number;
PRB_FIELD_OPTS opts;
const struct PRB_MSG_DESC *msg_desc;
const PRB_ENUM_DESC *enum_desc;
#if PRB_FIELD_NAMES
const char *name;
#endif
#if PRB_FIELD_DEFAULTS
const PRB_VALUE *def;
#endif
} PRB_FIELD_DESC;
//* Protocol buffer message descriptor
typedef struct PRB_MSG_DESC
{
NvU32 num_fields;
const PRB_FIELD_DESC *fields;
#if PRB_MESSAGE_NAMES
const char *name;
#endif
} PRB_MSG_DESC;
// Forward declaration
struct PRB_SERVICE_DESC;
// Protocol buffer method descriptor
struct PRB_METHOD_DESC
{
const struct PRB_SERVICE_DESC *service;
const PRB_MSG_DESC *req_desc;
const PRB_MSG_DESC *res_desc;
#if PRB_METHOD_NAMES
const char *name;
#endif
};
// Protocol buffer service descriptor
typedef struct PRB_SERVICE_DESC
{
NvU32 num_methods;
const struct PRB_METHOD_DESC *methods;
#if PRB_SERVICE_NAMES
const char *name;
#endif
} PRB_SERVICE_DESC;
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2003 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _RMOSXFAC_H_
#define _RMOSXFAC_H_
/**************** Resource Manager Defines and Structures ******************\
* *
* Module: RMOSXFAC.H *
* Declarations for common OS interface functions. *
* *
\***************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
extern NvS32 RmInitRm(void);
extern NvS32 RmDestroyRm(void);
#ifdef __cplusplus
}
#endif
#endif // _RMOSXFAC_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_boot_h__
#define __ga100_dev_boot_h__
#define NV_PMC 0x00000fff:0x00000000 /* RW--D */
#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_DEVICE(i) (i):(i) /* */
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_DEVICE_ENABLE(i) (0x000000600+(i)*4) /* RW-4A */
#define NV_PMC_DEVICE_ENABLE__SIZE_1 1 /* */
#define NV_PMC_DEVICE_ENABLE__PRIV_LEVEL_MASK 0x00000084 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS 31:0 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_STATUS_DISABLE_ALL 0x00000000 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT(i) (i):(i) /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT__SIZE_1 32 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_ENABLE 0x00000001 /* */
#endif // __ga100_dev_boot_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef ga100_dev_nv_bus_h
#define ga100_dev_nv_bus_h
#define NV_PBUS_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */
#endif // ga100_dev_nv_bus_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef ga100_dev_nv_bus_addendum_h
#define ga100_dev_nv_bus_addendum_h
#define NV_PBUS_SW_SCRATCH1_SMC_MODE 15:15
#define NV_PBUS_SW_SCRATCH1_SMC_MODE_OFF 0x00000000
#define NV_PBUS_SW_SCRATCH1_SMC_MODE_ON 0x00000001
#endif // ga100_dev_nv_bus_addendum_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_ce_h__
#define __ga100_dev_ce_h__
#define NV_CE_PCE_MAP 0x00104028 /* R--4R */
#define NV_CE_PCE2LCE_CONFIG__SIZE_1 18 /* */
#define NV_CE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE 0x0000000f /* RW--V */
#define NV_CE_GRCE_CONFIG__SIZE_1 2 /* */
#define NV_CE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#define NV_CE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_ctrl_h__
#define __ga100_dev_ctrl_h__
#define NV_CTRL_VF_DOORBELL_VECTOR 11:0 /* -WXUF */
#define NV_CTRL_VF_DOORBELL_RUNLIST_ID 22:16 /* -WXUF */
#endif // __ga100_dev_ctrl_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_falcon_v4_h__
#define __ga100_dev_falcon_v4_h__
#define NV_PFALCON_FALCON_IRQSCLR 0x00000004 /* -W-4R */
#define NV_PFALCON_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSTAT 0x00000008 /* R--4R */
#define NV_PFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMSET 0x00000010 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMCLR 0x00000014 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */
#define NV_PFALCON_FALCON_IRQDEST 0x0000001c /* RW-4R */
#define NV_PFALCON_FALCON_INTR_RETRIGGER(i) (0x000003e8+(i)*4) /* -W-4A */
#define NV_PFALCON_FALCON_INTR_RETRIGGER__SIZE_1 2 /* */
#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */
#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */
#define NV_PFALCON_FALCON_OS 0x00000080 /* RW-4R */
#define NV_PFALCON_FALCON_RM 0x00000084 /* RW-4R */
#define NV_PFALCON_FALCON_DEBUGINFO 0x00000094 /* RW-4R */
#define NV_PFALCON_FALCON_CPUCTL 0x00000100 /* RW-4R */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
#define NV_PFALCON_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS 0x00000130 /* -W-4R */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_BOOTVEC 0x00000104 /* RW-4R */
#define NV_PFALCON_FALCON_HWCFG 0x00000108 /* R--4R */
#define NV_PFALCON_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */
#define NV_PFALCON_FALCON_HWCFG2 0x000000f4 /* R--4R */
#define NV_PFALCON_FALCON_HWCFG2_RISCV 10:10 /* R--VF */
#define NV_PFALCON_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMACTL 0x0000010c /* RW-4R */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMATRFBASE 0x00000110 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFMOFFS 0x00000114 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFCMD 0x00000118 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */
#define NV_PFALCON_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMATRFCMD_SEC 3:2 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFFBOFFS 0x0000011c /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFBASE1 0x00000128 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFBASE1_BASE 8:0 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC(i) (0x00000180+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_BLK 23:8 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMD(i) (0x00000184+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMD_DATA 31:0 /* RW-VF */
#define NV_PFALCON_FALCON_IMEMT(i) (0x00000188+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMT_TAG 15:0 /* RW-VF */
#define NV_PFALCON_FALCON_DMEMC(i) (0x000001c0+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMC_OFFS 7:2 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_BLK 23:8 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMD_DATA 31:0 /* RW-VF */
#endif // __ga100_dev_falcon_v4_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_fb_h__
#define __ga100_dev_fb_h__
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR 0x00100C10 /* RW-4R */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_ADR_39_08 31:0 /* RWIVF */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_ADR_39_08_INIT 0x00000000 /* RWI-V */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI 0x00100C40 /* RW-4R */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI_MASK 0x7F /* */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI_ADR_63_40 23:0 /* RWIVF */
#define NV_PFB_FBHUB_POISON_INTR_VECTOR 0x00100A24 /* R--4R */
#define NV_PFB_FBHUB_POISON_INTR_VECTOR_HW 7:0 /* R-IVF */
#define NV_PFB_FBHUB_POISON_INTR_VECTOR_HW_INIT 135 /* R-I-V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK 0x001FA7C8 /* RW-4R */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO 0x001FA82C /* RW-4R */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7C8 /* */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_LOCK_ADDR_HI 0x001FA830 /* RW-4R */
#define NV_PFB_PRI_MMU_LOCK_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_ADDR_HI_ALIGNMENT 0x0000000c /* */
#endif // __ga100_dev_fb_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_fbif_v4_h__
#define __ga100_dev_fbif_v4_h__
#define NV_PFALCON_FBIF_TRANSCFG(i) (0x00000000+(i)*4) /* RW-4A */
#define NV_PFALCON_FBIF_TRANSCFG__SIZE_1 8 /* */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_CTL 0x00000024 /* RW-4R */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */
#endif // __ga100_dev_fbif_v4_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_fuse_h__
#define __ga100_dev_fuse_h__
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS 0x0082074C /* RW-4R */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA 0:0 /* RWIVF */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */
#define NV_FUSE_OPT_NVDEC_DISABLE 0x00820378 /* RW-4R */
#define NV_FUSE_OPT_NVDEC_DISABLE_DATA 4:0 /* RWIVF */
#define NV_FUSE_OPT_NVDEC_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION 0x00824100 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION 0x00824104 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION 0x00824108 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION 0x0082410C /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION 0x00824110 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION 0x00824114 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION 0x00824118 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION 0x0082411C /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION 0x00824120 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION 0x00824124 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION 0x00824128 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION 0x0082412C /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION 0x00824130 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION 0x00824134 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION 0x00824138 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION 0x0082413C /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION 0x00824140 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION 0x00824144 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION 0x00824148 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION 0x0082414C /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION 0x00824150 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION 0x00824154 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION 0x00824158 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION 0x0082415C /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION 0x00824160 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION 0x00824164 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION 0x00824168 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION 0x0082416C /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION 0x00824170 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION 0x00824174 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION 0x00824178 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION 0x0082417C /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION 0x008241C0 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION 0x008241C4 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION 0x008241C8 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION 0x008241CC /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION 0x008241D0 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION 0x008241D4 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION 0x008241D8 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION 0x008241DC /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION 0x008241E0 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION 0x008241E4 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION 0x008241E8 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION 0x008241EC /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION 0x008241F0 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION 0x008241F4 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION 0x008241F8 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION 0x008241FC /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION_DATA 15:0 /* RWIVF */
#endif // __ga100_dev_fuse_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_mmu_h__
#define __ga100_dev_mmu_h__
#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */
#define NV_MMU_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */
#define NV_MMU_PDE_SIZE_FULL 0x00000000 /* RW--V */
#define NV_MMU_PDE_SIZE_HALF 0x00000001 /* RW--V */
#define NV_MMU_PDE_SIZE_QUARTER 0x00000002 /* RW--V */
#define NV_MMU_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */
#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */
#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */
#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */
#define NV_MMU_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_PDE__SIZE 8
#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */
#define NV_MMU_PTE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */
#define NV_MMU_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */
#define NV_MMU_PTE_READ_ONLY_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_READ_ONLY_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */
#define NV_MMU_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */
#define NV_MMU_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */
#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */
#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */
#define NV_MMU_PTE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PTE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */
#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PTE_LOCK (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_PTE_LOCK_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_LOCK_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_COMPTAGLINE (1*32+20+11):(1*32+12) /* RWXVF */
#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) /* RWXVF */
#define NV_MMU_PTE_READ_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_READ_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) /* RWXVF */
#define NV_MMU_PTE_WRITE_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_WRITE_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_PTE__SIZE 8
#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x09 /* R---V */
#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0x0F /* R---V */
#endif // __ga100_dev_mmu_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_nv_xve_h__
#define __ga100_dev_nv_xve_h__
#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */
#define NV_XVE_LINK_CONTROL_STATUS 0x00000088 /* RW-4R */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED 19:16 /* R--VF */
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_nv_xve_addendum_h__
#define __ga100_dev_nv_xve_addendum_h__
//
// Extra config bits that can be emulated by the hypervisor for passthrough.
// This offset is unused in HW and HW returns 0x0 on read.
//
#define NV_XVE_PASSTHROUGH_EMULATED_CONFIG 0xE8
//
// On GA100, we need to be able to detect the case where the GPU is running at
// gen4, but the root port is at gen3. On baremetal, we just check the root
// port directly, but for passthrough root port is commonly completely hidden
// or fake. To handle this case we support the hypervisor explicitly
// communicating the speed to us through emulated config space. The
// ROOT_PORT_SPEED field follows the usual link speed encoding with the
// numerical value matching the gen speed, i.e. gen3 is 0x3.
// See bug 2927491 for more details.
//
#define NV_XVE_PASSTHROUGH_EMULATED_CONFIG_ROOT_PORT_SPEED 3:0
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_nvdec_addendum_h__
#define __ga100_dev_nvdec_addendum_h__
#define NV_PNVDEC_FBIF_BASE(dev) (0x00848600+(dev)*16384)
#endif // __ga100_dev_nvdec_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_nvdec_pri_h__
#define __ga100_dev_nvdec_pri_h__
#define NV_PNVDEC(dev) 0x0084bfff+(dev)*16384:0x00848000+(dev)*16384 /* RW--D */
#endif // __ga100_dev_nvdec_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_ram_h__
#define __ga100_dev_ram_h__
#define NV_RAMIN_ALLOC_SIZE 4096 /* */
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_LO (31+0*32):(8+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI_HW (7+1*32):(0+1*32) /* RWXUF */
#define NV_RAMRL_ENTRY_BASE_SHIFT 12 /* */
#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) /* RW-UF */
#define NV_RAMUSERD_GET (17*32+31):(17*32+0) /* RW-UF */
#define NV_RAMUSERD_REF (18*32+31):(18*32+0) /* RW-UF */
#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) /* RW-UF */
#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) /* RW-UF */
#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) /* RW-UF */
#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) /* RW-UF */
#define NV_RAMUSERD_GP_GET (34*32+31):(34*32+0) /* RW-UF */
#define NV_RAMUSERD_GP_PUT (35*32+31):(35*32+0) /* RW-UF */
#endif // __ga100_dev_ram_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_riscv_pri_h__
#define __ga100_dev_riscv_pri_h__
#define NV_FALCON2_GSP_BASE 0x00111000
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS 0x00000240 /* R-I4R */
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS_ACTIVE_STAT 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_IRQMASK 0x000002b4 /* R-I4R */
#define NV_PRISCV_RISCV_IRQDEST 0x000002b8 /* RW-4R */
#endif // __ga100_dev_riscv_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_runlist_h__
#define __ga100_dev_runlist_h__
#define NV_CHRAM_CHANNEL(i) (0x000+(i)*4) /* RW-4A */
#endif // __ga100_dev_runlist_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_sec_addendum_h__
#define __ga100_dev_sec_addendum_h__
#define NV_PSEC_FBIF_BASE 0x00840600
#endif // __ga100_dev_sec_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_sec_pri_h__
#define __ga100_dev_sec_pri_h__
#define NV_PSEC 0x843fff:0x840000 /* RW--D */
#define NV_PSEC_FALCON_ENGINE 0x008403c0 /* RW-4R */
#define NV_PSEC_FALCON_ENGINE_RESET 0:0 /* RWIVF */
#define NV_PSEC_FALCON_ENGINE_RESET_TRUE 0x00000001 /* RW--V */
#define NV_PSEC_FALCON_ENGINE_RESET_FALSE 0x00000000 /* RWI-V */
#define NV_PSEC_MAILBOX(i) (0x00840804+(i)*4) /* RW-4A */
#define NV_PSEC_MAILBOX__SIZE_1 4 /* */
#define NV_PSEC_MAILBOX_DATA 31:0 /* RWIVF */
#define NV_PSEC_MAILBOX_DATA_INIT 0x00000000 /* RWI-V */
#endif // __ga100_dev_sec_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_timer_h__
#define __ga100_dev_timer_h__
#define NV_PTIMER_ALARM_INTR 0x00009140 /* RW-4R */
#define NV_PTIMER_ALARM_INTR_MASK 0:0 /* RWIVF */
#define NV_PTIMER_ALARM_INTR_MASK_DISABLED 0x00000000 /* RWI-V */
#define NV_PTIMER_ALARM_INTR_MASK_ENABLED 0x00000001 /* RW--V */
#endif // __ga100_dev_timer_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_vm_h__
#define __ga100_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP(i) (0x1600+(i)*4) /* R--4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_VALUE 31:0 /* R--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_PENDING 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_NOT_PENDING 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(i) (0x1608+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLE 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLED 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_DISABLED 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(i) (0x1610+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLE 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_ENABLED 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLED 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(i) (0x1000+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 8 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(i) (0x1200+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1 8 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(i) (0x1400+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 8 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER 0x00001640 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -W-VF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE 0x000030B0 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA 0:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_PDB 1:1 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_PDB_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_PDB_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_HUBTLB_ONLY 2:2 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_HUBTLB_ONLY_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_HUBTLB_ONLY_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY 5:3 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_NONE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_START 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SYS_MEMBAR 6:6 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SYS_MEMBAR_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SYS_MEMBAR_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK 8:7 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK_NONE_REQUIRED 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK_INTRANODE 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK_GLOBALLY 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_ID 14:9 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_GPC_ID 19:15 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_INVAL_SCOPE 16:15 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_INVAL_SCOPE_LINK_TLBS 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE 20:20 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_PASID 21:21 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_PASID_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_PASID_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_SIZE 22:22 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_SIZE_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_SIZE_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PROP_FLUSH 23:23 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PROP_FLUSH_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PROP_FLUSH_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL 26:24 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_ALL 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2 0x00000004 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3 0x00000005 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4 0x00000006 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5 0x00000007 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_READ 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_STRONG 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_RSVRVD 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_WEAK 0x00000004 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_ALL 0x00000005 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE_AND_ATOMIC 0x00000006 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ALL 0x00000007 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER 31:31 /* -WEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER_FALSE 0x00000000 /* -WE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER_TRUE 0x00000001 /* -W--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_MAX_CACHELINE_SIZE 0x00000010 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_TIME_0 0x30080 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_0_NSEC 31:5 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_TIME_1 0x30084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_1_NSEC 28:0 /* R-XUF */
#endif // __ga100_dev_vm_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef ga100_dev_vm_addendum_h
#define ga100_dev_vm_addendum_h
//
// Compile time asserts in the source code files will ensure that
// these don't end up exceeding the range of the top level registers.
//
// Subtrees at CPU_INTR top level for UVM owned interrupts
#define NV_CPU_INTR_UVM_SUBTREE_START NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(1)
#define NV_CPU_INTR_UVM_SUBTREE_LAST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(1)
#define NV_CPU_INTR_UVM_SHARED_SUBTREE_START NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(2)
#define NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(2)
//
// Subtrees at CPU_INTR top level for all stall interrupts from host-driven
// engines
//
#define NV_CPU_INTR_STALL_SUBTREE_START NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(3)
#define NV_CPU_INTR_STALL_SUBTREE_LAST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(3)
#endif // ga100_dev_vm_addendum_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_boot_h__
#define __ga102_dev_boot_h__
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_DEVICE(i) (i):(i) /* */
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_DEVICE_ENABLE(i) (0x000000600+(i)*4) /* RW-4A */
#define NV_PMC_DEVICE_ENABLE__SIZE_1 1 /* */
#define NV_PMC_DEVICE_ENABLE__PRIV_LEVEL_MASK 0x00000084 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS 31:0 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_STATUS_DISABLE_ALL 0x00000000 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT(i) (i):(i) /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT__SIZE_1 26 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_ENABLE 0x00000001 /* */
#endif // __ga102_dev_boot_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_ce_h__
#define __ga102_dev_ce_h__
#define NV_CE_PCE_MAP 0x00104028 /* R--4R */
#define NV_CE_PCE_MAP_VALUE 23:0 /* R-XVF */
#define NV_CE_HSH_PCE_MASK 0x0010404c /* C--4R */
#define NV_CE_HSH_PCE_MASK_VALUE 23:0 /* C--VF */
#define NV_CE_PCE2LCE_CONFIG__SIZE_1 6 /* */
#define NV_CE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE 0x0000000f /* RW--V */
#define NV_CE_GRCE_CONFIG__SIZE_1 2 /* */
#define NV_CE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#define NV_CE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_falcon_second_pri_h__
#define __ga102_dev_falcon_second_pri_h__
#define NV_FALCON2_GSP_BASE 0x00111000
#define NV_FALCON2_NVDEC0_BASE 0x00849c00
#define NV_FALCON2_SEC_BASE 0x00841000
#define NV_PFALCON2_FALCON_MOD_SEL 0x00000180 /* RWI4R */
#define NV_PFALCON2_FALCON_MOD_SEL_ALGO 7:0 /* RWIVF */
#define NV_PFALCON2_FALCON_MOD_SEL_ALGO_RSA3K 0x00000001 /* RW--V */
#define NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID 0x00000198 /* RWI4R */
#define NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID_VAL 7:0 /* RWIVF */
#define NV_PFALCON2_FALCON_BROM_ENGIDMASK 0x0000019c /* RWI4R */
#define NV_PFALCON2_FALCON_BROM_PARAADDR(i) (0x00000210+(i)*4) /* RWI4A */
#endif // __ga102_dev_falcon_second_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_falcon_v4_h__
#define __ga102_dev_falcon_v4_h__
#define NV_PFALCON_FALCON_IRQSCLR 0x00000004 /* -W-4R */
#define NV_PFALCON_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSTAT 0x00000008 /* R--4R */
#define NV_PFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_INTR_RETRIGGER(i) (0x000003e8+(i)*4) /* -W-4A */
#define NV_PFALCON_FALCON_INTR_RETRIGGER__SIZE_1 2 /* */
#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */
#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQMSET 0x00000010 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMCLR 0x00000014 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */
#define NV_PFALCON_FALCON_IRQDEST 0x0000001c /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */
#define NV_PFALCON_FALCON_DMACTL 0x0000010c /* RW-4R */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMATRFBASE 0x00000110 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFMOFFS 0x00000114 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFCMD 0x00000118 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */
#define NV_PFALCON_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMATRFCMD_SEC 3:2 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFFBOFFS 0x0000011c /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFBASE1 0x00000128 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFBASE1_BASE 8:0 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC(i) (0x00000180+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_BLK 23:8 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMD(i) (0x00000184+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMD_DATA 31:0 /* RWXVF */
#define NV_PFALCON_FALCON_IMEMT(i) (0x00000188+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMT_TAG 15:0 /* RWXVF */
#define NV_PFALCON_FALCON_DMEMC(i) (0x000001c0+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMC_OFFS 7:2 /* */
#define NV_PFALCON_FALCON_DMEMC_BLK 23:8 /* */
#define NV_PFALCON_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMD_DATA 31:0 /* RWXVF */
#define NV_PFALCON_FALCON_HWCFG 0x00000108 /* R--4R */
#define NV_PFALCON_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */
#define NV_PFALCON_FALCON_HWCFG2 0x000000f4 /* R--4R */
#define NV_PFALCON_FALCON_HWCFG2_RISCV 10:10 /* R--VF */
#define NV_PFALCON_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */
#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_OS 0x00000080 /* RW-4R */
#define NV_PFALCON_FALCON_RM 0x00000084 /* RW-4R */
#define NV_PFALCON_FALCON_DEBUGINFO 0x00000094 /* RW-4R */
#define NV_PFALCON_FALCON_CPUCTL 0x00000100 /* RW-4R */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
#define NV_PFALCON_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS 0x00000130 /* -W-4R */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_BOOTVEC 0x00000104 /* RW-4R */
#endif // __ga102_dev_falcon_v4_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_falcon_v4_addendum_h__
#define __ga102_dev_falcon_v4_addendum_h__
#define NV_PFALCON_FALCON_HWCFG2_RESET_READY 31:31
#define NV_PFALCON_FALCON_HWCFG2_RESET_READY_TRUE 0x00000001
#define NV_PFALCON_FALCON_HWCFG2_RESET_READY_FALSE 0x00000000
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_fbif_v4_h__
#define __ga102_dev_fbif_v4_h__
#define NV_PFALCON_FBIF_TRANSCFG(i) (0x00000000+(i)*4) /* RW-4A */
#define NV_PFALCON_FBIF_TRANSCFG__SIZE_1 8 /* */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_CTL 0x00000024 /* RW-4R */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */
#endif // __ga102_dev_fbif_v4_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_gc6_island_h__
#define __ga102_dev_gc6_island_h__
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK 0x00118128 /* RW-4R */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 0x001183a4 /* RW-4R */
#endif // __ga102_dev_gc6_island_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_gc6_island_addendum_h__
#define __ga102_dev_gc6_island_addendum_h__
#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0 NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(0)
#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE 15:0
#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K 0x100
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(0)
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS 7:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED 0x000000FF
#define NV_USABLE_FB_SIZE_IN_MB NV_PGC6_AON_SECURE_SCRATCH_GROUP_42
#define NV_USABLE_FB_SIZE_IN_MB_VALUE 31:0
#define NV_USABLE_FB_SIZE_IN_MB_VALUE_INIT 0
#endif // __ga102_dev_gc6_island_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_gsp_h__
#define __ga102_dev_gsp_h__
#define NV_PGSP 0x113fff:0x110000 /* RW--D */
#define NV_PGSP_FALCON_MAILBOX0 0x110040 /* RW-4R */
#define NV_PGSP_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
#define NV_PGSP_FALCON_MAILBOX1 0x110044 /* RW-4R */
#define NV_PGSP_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
#define NV_PGSP_FALCON_ENGINE 0x1103c0 /* RW-4R */
#define NV_PGSP_FALCON_ENGINE_RESET 0:0 /* RWIVF */
#define NV_PGSP_FALCON_ENGINE_RESET_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_FALCON_ENGINE_RESET_FALSE 0x00000000 /* RWI-V */
#define NV_PGSP_MAILBOX(i) (0x110804+(i)*4) /* RW-4A */
#define NV_PGSP_MAILBOX__SIZE_1 4 /* */
#define NV_PGSP_MAILBOX_DATA 31:0 /* RWIVF */
#define NV_PGSP_QUEUE_HEAD(i) (0x110c00+(i)*8) /* RW-4A */
#define NV_PGSP_QUEUE_HEAD__SIZE_1 8 /* */
#define NV_PGSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
#endif // __ga102_dev_gsp_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_gsp_addendum_h__
#define __ga102_dev_gsp_addendum_h__
#define NV_PGSP_FBIF_BASE 0x110600
#endif // __ga102_dev_gsp_addendum_h__

29
src/common/inc/swref/published/ampere/ga102/dev_nvdec_addendum.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_nvdec_addendum_h__
#define __ga102_dev_nvdec_addendum_h__
#define NV_PNVDEC_FBIF_BASE(dev) (0x00848600+(dev)*16384)
#endif // __ga102_dev_nvdec_addendum_h__

29
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_nvdec_pri_h__
#define __ga102_dev_nvdec_pri_h__
#define NV_PNVDEC(dev) 0x0084bfff+(dev)*16384:0x00848000+(dev)*16384 /* RW--D */
#endif // __ga102_dev_nvdec_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_ram_h__
#define __ga102_dev_ram_h__
#define NV_RAMRL_ENTRY_BASE_SHIFT 10 /* */
#endif // __ga102_dev_ram_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_riscv_pri_h__
#define __ga102_dev_riscv_pri_h__
#define NV_FALCON2_GSP_BASE 0x00111000
#define NV_PRISCV_RISCV_IRQMASK 0x00000528 /* R-I4R */
#define NV_PRISCV_RISCV_IRQDEST 0x0000052c /* RW-4R */
#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RWI4R */
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_BCR_CTRL 0x00000668 /* RWI4R */
#define NV_PRISCV_RISCV_BCR_CTRL_VALID 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_BCR_CTRL_VALID_TRUE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_BCR_CTRL_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_BCR_CTRL_CORE_SELECT 4:4 /* RWIVF */
#define NV_PRISCV_RISCV_BCR_CTRL_CORE_SELECT_FALCON 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_BCR_CTRL_CORE_SELECT_RISCV 0x00000001 /* RW--V */
#define NV_PRISCV_RISCV_BCR_CTRL_BRFETCH 8:8 /* RWIVF */
#define NV_PRISCV_RISCV_BCR_CTRL_BRFETCH_TRUE 0x00000001 /* RWI-V */
#define NV_PRISCV_RISCV_BCR_CTRL_BRFETCH_FALSE 0x00000000 /* RW--V */
#endif // __ga102_dev_riscv_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_sec_addendum_h__
#define __ga102_dev_sec_addendum_h__
#define NV_PSEC_FBIF_BASE 0x00840600
#endif // __ga102_dev_sec_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_sec_pri_h__
#define __ga102_dev_sec_pri_h__
#define NV_PSEC 0x843fff:0x840000 /* RW--D */
#define NV_PSEC_FALCON_ENGINE 0x008403c0 /* RW-4R */
#define NV_PSEC_FALCON_ENGINE_RESET 0:0 /* RWIVF */
#define NV_PSEC_FALCON_ENGINE_RESET_TRUE 0x00000001 /* RW--V */
#define NV_PSEC_FALCON_ENGINE_RESET_FALSE 0x00000000 /* RWI-V */
#define NV_PSEC_MAILBOX(i) (0x00840804+(i)*4) /* RW-4A */
#define NV_PSEC_MAILBOX__SIZE_1 4 /* */
#define NV_PSEC_MAILBOX_DATA 31:0 /* RWIVF */
#define NV_PSEC_MAILBOX_DATA_INIT 0x00000000 /* RWI-V */
#endif // __ga102_dev_sec_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_vm_h__
#define __ga102_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP(i) (0x1600+(i)*4) /* R--4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_VALUE 31:0 /* R--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_PENDING 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_NOT_PENDING 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(i) (0x1608+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLE 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLED 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_DISABLED 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(i) (0x1610+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLE 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_ENABLED 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLED 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(i) (0x1000+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 8 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(i) (0x1200+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1 8 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(i) (0x1400+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 8 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER 0x00001640 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -WXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#endif // __ga102_dev_vm_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DEV_BR03_XVD_H
#define DEV_BR03_XVD_H
#define NV_BR03_XVD_LINK_CTRLSTAT 0x00000070 /* RWI4R */
#define NV_BR03_XVD_XP_0 0x00000B00 /* RW-4R */
#define NV_BR03_XVD_XP_0_UPDATE_FC_THRESHOLD 9:1 /* RWIVF */
#define NV_BR03_XVD_XP_0_UPDATE_FC_THRESHOLD_INIT 0x00000000 /* RWI-V */
#define NV_BR03_XVD_XP_0_OPPORTUNISTIC_ACK 29:29 /* RWIVF */
#define NV_BR03_XVD_XP_0_OPPORTUNISTIC_ACK_INIT 0x00000000 /* RWI-V */
#define NV_BR03_XVD_XP_0_OPPORTUNISTIC_UPDATE_FC 30:30 /* RWIVF */
#define NV_BR03_XVD_XP_0_OPPORTUNISTIC_UPDATE_FC_INIT 0x00000000 /* RWI-V */
#endif /* DEV_BR03_XVD_H */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DEV_BR03_XVU_H
#define DEV_BR03_XVU_H
#define NV_BR03_XVU 0x00000FFF:0x00000000 /* RW--D */
#define NV_BR03_XVU_DEV_ID 0x00000000 /* R--4R */
#define NV_BR03_XVU_DEV_ID_DEVICE_ID 31:16 /* C--VF */
#define NV_BR03_XVU_DEV_ID_DEVICE_ID_BR03 0x000001B3 /* C---V */
#define NV_BR03_XVU_REV_CC 0x00000008 /* R--4R */
#define NV_BR03_XVU_MCC_REG_ALIAS 0x00000600 /* RW-4R */
#define NV_BR03_XVU_MCC_REG_ALIAS_ACCESS 0:0 /* RWIVF */
#define NV_BR03_XVU_MCC_REG_ALIAS_ACCESS_INIT 0x00000000 /* RWI-V */
#define NV_BR03_XVU_MCC_REG_ALIAS_ACCESS_DISABLED 0x00000000 /* RW--V */
#define NV_BR03_XVU_MCC_REG_ALIAS_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_BR03_XVU_MCC_REG_ALIAS_BASE_ADDRESS 31:14 /* RWIUF */
#define NV_BR03_XVU_MCC_REG_ALIAS_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_BR03_XVU_UP0_INT_BUFSIZE_CPL 0x00000300 /* R--4R */
#define NV_BR03_XVU_UP0_INT_BUFSIZE_CPL_H 7:0 /* R--UF */
#define NV_BR03_XVU_UP0_INT_BUFSIZE_CPL_D 27:16 /* R--UF */
#define NV_BR03_XVU_INT_FLOW_CTL 0x00000340 /* RW-4R */
#define NV_BR03_XVU_INT_FLOW_CTL_DP0_TO_UP0_CPL 0x00000350 /* RW-4R */
#define NV_BR03_XVU_INT_FLOW_CTL_UP0_TO_MH0_PW 0x00000408 /* RW-4R */
#define NV_BR03_XVU_ITX_ALLOCATION 0x00000500 /* RW-4R */
#define NV_BR03_XVU_ITX_ALLOCATION_UP0 3:0 /* RWIUF */
#define NV_BR03_XVU_ITX_ALLOCATION_UP0_INIT 0x00000001 /* RWI-V */
#define NV_BR03_XVU_ITX_ALLOCATION_DP0 11:8 /* RWIUF */
#define NV_BR03_XVU_ITX_ALLOCATION_DP0_INIT 0x00000001 /* RWI-V */
#define NV_BR03_XVU_ITX_ALLOCATION_DP1 19:16 /* RWIUF */
#define NV_BR03_XVU_ITX_ALLOCATION_DP1_INIT 0x00000001 /* RWI-V */
#define NV_BR03_XVU_ITX_ALLOCATION_MH0 27:24 /* RWIUF */
#define NV_BR03_XVU_ITX_ALLOCATION_MH0_INIT 0x00000001 /* RWI-V */
#define NV_BR03_XVU_XP_0 0x00000B00 /* RW-4R */
#define NV_BR03_XVU_XP_0_OPPORTUNISTIC_ACK 29:29 /* RWIVF */
#define NV_BR03_XVU_XP_0_OPPORTUNISTIC_ACK_INIT 0x00000000 /* RWI-V */
#define NV_BR03_XVU_XP_0_OPPORTUNISTIC_UPDATE_FC 30:30 /* RWIVF */
#define NV_BR03_XVU_XP_0_OPPORTUNISTIC_UPDATE_FC_INIT 0x00000000 /* RWI-V */
#endif /* DEV_BR03_XVU_H */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef BR04_REF_H
#define BR04_REF_H
#include "published/br04/dev_br04_xvd.h"
#include "published/br04/dev_br04_xvu.h"
// BR04 can be accessed through a window in GPU register space
#define NV_BR04(i) (0x00018000 + (i * 0x00004000))
// Config space access for downstream ports begins at 8Ki, a port every 2Ki
#define NV_BR04_XVD_OFFSET(i) ((1<<13) + (1<<11)*i)
// Size of total config space and for upstream, downstream ports.
#define NV_BR04_CONFIG_SIZE (1 << 14)
#define NV_BR04_XVU_CONFIG_SIZE (1 << 12)
#define NV_BR04_XVD_CONFIG_SIZE (1 << 11)
// This enumeration is in the order of the _BUFSIZE_ registers; the FLOW_CTL
// registers are in a different order.
typedef enum {
BR04_PORT_UP0 = 0,
BR04_PORT_DP0,
BR04_PORT_DP1,
BR04_PORT_DP2,
BR04_PORT_DP3,
BR04_PORT_MH0,
NUM_BR04_PORTS
} BR04_PORT;
// Is this a BR04 devid or not
// Based on assumption that XVD and XVU has same deviceID
#define IS_DEVID_BR04(i) ((i >> 4) == (NV_BR04_XVU_DEV_ID_DEVICE_ID_BR04_0 >> 4))
// Phantom address to use for HGPU P2P transfers
#define HGPU_P2P_PHANTOM_BASE 0xf0f0f0f000000000LL
#endif // BR04_REF_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DEV_BR04_XVD_H
#define DEV_BR04_XVD_H
#define NV_BR04_XVD_LINK_CTRLSTAT 0x00000070 /* RW-4R */
#define NV_BR04_XVD_LINK_CTRLSTAT_ASPM_CTRL 1:0 /* RWIVF */
#define NV_BR04_XVD_LINK_CTRLSTAT_ASPM_CTRL_DISABLED 0x00000000 /* RWI-V */
#define NV_BR04_XVD_LINK_CTRLSTAT_ASPM_CTRL_L0S 0x00000001 /* RW--V */
#define NV_BR04_XVD_LINK_CTRLSTAT_ASPM_CTRL_L1 0x00000002 /* RW--V */
#define NV_BR04_XVD_LINK_CTRLSTAT_ASPM_CTRL_L0S_L1 0x00000003 /* RW--V */
#define NV_BR04_XVD_LINK_CTRLSTAT2 0x00000090 /* RW-4R */
#define NV_BR04_XVD_LINK_CTRLSTAT2_TARGET_LINK_SPEED 3:0 /* RWIVF */
#define NV_BR04_XVD_LINK_CTRLSTAT2_TARGET_LINK_SPEED_2P5G 0x00000001 /* RW--V */
#define NV_BR04_XVD_LINK_CTRLSTAT2_TARGET_LINK_SPEED_5P0G 0x00000002 /* RWI-V */
#define NV_BR04_XVD_G2_PRIV_XP_LCTRL_2 0x0000046C /* RW-4R */
#define NV_BR04_XVD_G2_PRIV_XP_LCTRL_2_ADVERTISED_RATE_CHANGE 1:1 /* CWIVF */
#define NV_BR04_XVD_G2_PRIV_XP_LCTRL_2_ADVERTISED_RATE_CHANGE_ZERO 0x00000000 /* CWI-V */
#define NV_BR04_XVD_BUS 0x00000018 /* RW-4R */
#define NV_BR04_XVD_BUS_SEC_NUMBER 15:8 /* RWIUF */
#define NV_BR04_XVD_BUS_SEC_NUMBER_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVD_BUS_SUB_NUMBER 23:16 /* RWIUF */
#define NV_BR04_XVD_BUS_SUB_NUMBER_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVD_G2_PRIV_XP_CONFIG 0x00000494 /* RW-4R */
#define NV_BR04_XVD_G2_PRIV_XP_CONFIG_GEN2_REPLAY_TIMER_LIMIT 11:2 /* RWIVF */
#define NV_BR04_XVD_G2_PRIV_XP_CONFIG_GEN2_REPLAY_TIMER_LIMIT_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVD_LINK_CTRLSTAT_DLL_LINK_SM 29:29 /* R--VF */
#define NV_BR04_XVD_LINK_CTRLSTAT_DLL_LINK_SM_NOT_ACTIVE 0x00000000 /* R---V */
#define NV_BR04_XVD_LINK_CTRLSTAT_DLL_LINK_SM_ACTIVE 0x00000001 /* R---V */
#define NV_BR04_XVD_G2_VEND_XP 0x00000400 /* RW-4R */
#define NV_BR04_XVD_G2_VEND_XP_OPPORTUNISTIC_ACK 28:28 /* RWIVF */
#define NV_BR04_XVD_G2_VEND_XP_OPPORTUNISTIC_ACK_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVD_G2_VEND_XP_OPPORTUNISTIC_UPDATEFC 29:29 /* RWIVF */
#define NV_BR04_XVD_G2_VEND_XP_OPPORTUNISTIC_UPDATEFC_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVD_G2_VEND_XP1 0x00000404 /* RW-4R */
#define NV_BR04_XVD_G2_VEND_XP1_REPLAY_TIMER_LIMIT 9:0 /* RWIVF */
#define NV_BR04_XVD_G2_VEND_XP1_REPLAY_TIMER_LIMIT_INIT 0x00000000 /* RWI-V */
#endif // DEV_BR04_XVD_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DEV_BR04_XVU_H
#define DEV_BR04_XVU_H
#define NV_BR04_XVU 0x00000DFF:0x00000000 /* RW--D */
#define NV_BR04_XVU_DEV_ID 0x00000000 /* R--4R */
#define NV_BR04_XVU_DEV_ID_VENDOR_ID 15:0 /* C--VF */
#define NV_BR04_XVU_DEV_ID_VENDOR_ID_NVIDIA 0x000010DE /* C---V */
#define NV_BR04_XVU_DEV_ID_DEVICE_ID 31:16 /* R-IVF */
#define NV_BR04_XVU_DEV_ID_DEVICE_ID_BR04_0 0x000005B0 /* R---V */
#define NV_BR04_XVU_DEV_ID_DEVICE_ID_BR04_15 0x000005BF /* R---V */
#define NV_BR04_XVU_DEV_ID_DEVICE_ID_DEFAULT 0x000005BF /* R-I-V */
#define NV_BR04_XVU_BUS 0x00000018 /* RW-4R */
#define NV_BR04_XVU_BUS_PRI_NUMBER 7:0 /* RWIUF */
#define NV_BR04_XVU_BUS_PRI_NUMBER_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_BUS_SEC_NUMBER 15:8 /* RWIUF */
#define NV_BR04_XVU_BUS_SEC_NUMBER_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_BUS_SUB_NUMBER 23:16 /* RWIUF */
#define NV_BR04_XVU_BUS_SUB_NUMBER_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_REV_CC 0x00000008 /* R--4R */
#define NV_BR04_XVU_REV_CC_MINOR_REVISION_ID 3:0 /* R--VF */
#define NV_BR04_XVU_REV_CC_MAJOR_REVISION_ID 7:4 /* R--VF */
#define NV_BR04_XVU_INT_FLOW_CTL 0x00000360 /* RW-4R */
#define NV_BR04_XVU_INT_FLOW_CTL_UP0_TOO_CPL(i) (0x000004F0+(i)*16) /* RW-4A */
#define NV_BR04_XVU_INT_FLOW_CTL_DP0_TOO_CPL(i) (0x00000370+(i)*16) /* RW-4A */
#define NV_BR04_XVU_INT_FLOW_CTL_DP0_TOO_CPL__SIZE_1 6 /* */
#define NV_BR04_XVU_INT_FLOW_CTL_DP0_TOO_CPL_H 6:0 /* RWIUF */
#define NV_BR04_XVU_INT_FLOW_CTL_DP0_TOO_CPL_H_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_INT_FLOW_CTL_DP0_TOO_CPL_D 15:7 /* RWIUF */
#define NV_BR04_XVU_INT_FLOW_CTL_DP0_TOO_CPL_D_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_INT_FLOW_CTL_UP0_TOO_NP(i) (0x000004F4+(i)*16) /* RW-4A */
#define NV_BR04_XVU_INT_FLOW_CTL_UP0_TOO_PW(i) (0x000004F8+(i)*16) /* RW-4A */
#define NV_BR04_XVU_HGPU_CTRL 0x00000980 /* RW-4R */
#define NV_BR04_XVU_HGPU_CTRL_EN 0:0 /* RWIVF */
#define NV_BR04_XVU_HGPU_CTRL_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_BR04_XVU_HGPU_CTRL_EN_ENABLED 0x00000001 /* RW--V */
#define NV_BR04_XVU_HGPU_PEER_FB_LOWER_BASE 0x00000990 /* RW-4R */
#define NV_BR04_XVU_HGPU_PEER_FB_UPPER_BASE 0x00000994 /* RW-4R */
#define NV_BR04_XVU_ITX_ALLOCATION 0x000005B0 /* RW-4R */
#define NV_BR04_XVU_ITX_ALLOCATION_DP0 3:0 /* RWIUF */
#define NV_BR04_XVU_ITX_ALLOCATION_DP0_INIT 0x00000001 /* RWI-V */
#define NV_BR04_XVU_ITX_ALLOCATION_DP1 7:4 /* RWIUF */
#define NV_BR04_XVU_ITX_ALLOCATION_DP1_INIT 0x00000001 /* RWI-V */
#define NV_BR04_XVU_ITX_ALLOCATION_DP2 11:8 /* RWIUF */
#define NV_BR04_XVU_ITX_ALLOCATION_DP2_INIT 0x00000001 /* RWI-V */
#define NV_BR04_XVU_ITX_ALLOCATION_DP3 15:12 /* RWIUF */
#define NV_BR04_XVU_ITX_ALLOCATION_DP3_INIT 0x00000001 /* RWI-V */
#define NV_BR04_XVU_ITX_ALLOCATION_UP0 19:16 /* RWIUF */
#define NV_BR04_XVU_ITX_ALLOCATION_UP0_INIT 0x00000001 /* RWI-V */
#define NV_BR04_XVU_ITX_ALLOCATION_MH0 23:20 /* RWIUF */
#define NV_BR04_XVU_ITX_ALLOCATION_MH0_INIT 0x00000001 /* RWI-V */
#define NV_BR04_XVU_MCC_REG_ALIAS 0x00000600 /* RW-4R */
#define NV_BR04_XVU_MCC_REG_ALIAS_DONOR_BUS 7:0 /* RWIUF */
#define NV_BR04_XVU_MCC_REG_ALIAS_DONOR_BUS_INIT 0x00000000 /* R-I-V */
#define NV_BR04_XVU_MCC_REG_ALIAS_ACCESS 8:8 /* RWIVF */
#define NV_BR04_XVU_MCC_REG_ALIAS_ACCESS_DISABLED 0x00000000 /* RW--V */
#define NV_BR04_XVU_MCC_REG_ALIAS_ACCESS_ENABLED 0x00000001 /* RWI-V */
#define NV_BR04_XVU_MCC_REG_ALIAS_ADDR_SELECT 9:9 /* RWIVF */
#define NV_BR04_XVU_MCC_REG_ALIAS_ADDR_SELECT_AUTO 0x00000000 /* RWI-V */
#define NV_BR04_XVU_MCC_REG_ALIAS_ADDR_SELECT_MANUAL 0x00000001 /* RW--V */
#define NV_BR04_XVU_MCC_REG_OFFSET 0x00000604 /* RW-4R */
#define NV_BR04_XVU_BAR_0 0x00000010 /* RW-4R */
#define NV_BR04_XVU_DEV_CTRLSTAT 0x00000068 /* RW-4R */
#define NV_BR04_XVU_DEV_CTRLSTAT_CORR_ERR_RPT_EN 0:0 /* RWIVF */
#define NV_BR04_XVU_DEV_CTRLSTAT_CORR_ERR_RPT_EN_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_LINK_CTRLSTAT 0x00000070 /* RW-4R */
#define NV_BR04_XVU_LINK_CTRLSTAT_ASPM_CTRL 1:0 /* RWIVF */
#define NV_BR04_XVU_LINK_CTRLSTAT_ASPM_CTRL_DISABLED 0x00000000 /* RWI-V */
#define NV_BR04_XVU_LINK_CTRLSTAT_ASPM_CTRL_L0S 0x00000001 /* RW--V */
#define NV_BR04_XVU_LINK_CTRLSTAT_ASPM_CTRL_L1 0x00000002 /* RW--V */
#define NV_BR04_XVU_LINK_CTRLSTAT_ASPM_CTRL_L0S_L1 0x00000003 /* RW--V */
#define NV_BR04_XVU_LINK_CTRLSTAT_LINK_SPEED 19:16 /* R--VF */
#define NV_BR04_XVU_LINK_CTRLSTAT_LINK_SPEED_2P5G 0x00000001 /* R---V */
#define NV_BR04_XVU_LINK_CTRLSTAT_LINK_SPEED_5P0G 0x00000002 /* R---V */
#define NV_BR04_XVU_LINK_CTRLSTAT2 0x00000090 /* RW-4R */
#define NV_BR04_XVU_LINK_CTRLSTAT2_TARGET_LINK_SPEED 3:0 /* RWIVF */
#define NV_BR04_XVU_LINK_CTRLSTAT2_TARGET_LINK_SPEED_2P5G 0x00000001 /* RW--V */
#define NV_BR04_XVU_LINK_CTRLSTAT2_TARGET_LINK_SPEED_5P0G 0x00000002 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_0 0x00000C00 /* RW-4R */
#define NV_BR04_XVU_G2_PRIV_XP_0_REPLAY_TIMER_LIMIT 28:19 /* RWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_0_REPLAY_TIMER_LIMIT_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_0_OPPORTUNISTIC_ACK 29:29 /* RWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_0_OPPORTUNISTIC_ACK_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_0_OPPORTUNISTIC_UPDATE_FC 30:30 /* RWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_0_OPPORTUNISTIC_UPDATE_FC_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2 0x00000C44 /* RW-4R */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_SPEED_CHANGE 0:0 /* CWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_SPEED_CHANGE_ZERO 0x00000000 /* CWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_CYA_DEEMPHASIS_OVERRIDE 2:2 /* RWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_CYA_DEEMPHASIS_OVERRIDE_DISABLED 0x00000000 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_CYA_DEEMPHASIS_OVERRIDE_ENABLED 0x00000001 /* RW--V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_TARGET_LINK_SPEED 7:4 /* RWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_TARGET_LINK_SPEED_2P5 0x00000001 /* RW--V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_TARGET_LINK_SPEED_5P0 0x00000002 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED 11:8 /* RWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_2P5 0x00000001 /* RW--V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_5P0_2P5 0x00000002 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE 15:12 /* R-IVF */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE_2P5 0x00000001 /* R-I-V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE_5P0_2P5 0x00000002 /* R---V */
#define NV_BR04_XVU_BOOT_1 0x00000204 /* R--4R */
#define NV_BR04_XVU_BOOT_1_LINK_SPEED 1:1 /* RWIVF */
#define NV_BR04_XVU_BOOT_1_LINK_SPEED_2500 0x00000000 /* RWI-V */
#define NV_BR04_XVU_BOOT_1_LINK_SPEED_5000 0x00000001 /* RW--V */
#define NV_BR04_XVU_CYA_BIT0 0x00000AB0 /* RW-4R */
#define NV_BR04_XVU_CYA_BIT0_RSVD_28 28:28 /* RWIVF */
#define NV_BR04_XVU_CYA_BIT0_RSVD_28_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_CYA_BIT0_RSVD_29 29:29 /* RWIVF */
#define NV_BR04_XVU_CYA_BIT0_RSVD_29_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_CYA_BIT0_RSVD_30 30:30 /* RWIVF */
#define NV_BR04_XVU_CYA_BIT0_RSVD_30_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_CYA_BIT0_RSVD_31 31:31 /* RWIVF */
#define NV_BR04_XVU_CYA_BIT0_RSVD_31_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_CYA_NIBBLE0 0x00000AB4 /* RW-4R */
#define NV_BR04_XVU_CYA_NIBBLE0_RSVD_0 3:0 /* RWIVF */
#define NV_BR04_XVU_CYA_NIBBLE0_RSVD_0_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_CYA_NIBBLE0_RSVD_4 19:16 /* RWIVF */
#define NV_BR04_XVU_CYA_NIBBLE0_RSVD_4_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_ROM_REVISION 0x00000B08 /* RW-4R */
#endif // DEV_BR04_XVU_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __v03_00_dev_disp_h__
#define __v03_00_dev_disp_h__
#define NV_PDISP_CHN_NUM_CORE 0 /* */
#define NV_PDISP_CHN_NUM_WIN(i) (1+(i)) /* */
#define NV_PDISP_CHN_NUM_WIN__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_WINIM(i) (33+(i)) /* */
#define NV_PDISP_CHN_NUM_WINIM__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_CURS(i) (73+(i)) /* */
#define NV_PDISP_CHN_NUM_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* R---V */
#define NV_PDISP_FE_SW 0x00640FFF:0x00640000 /* RW--D */
#define NV_PDISP_SF_USER_0 0x006F03FF:0x006F0000 /* RW--D */
#define NV_UDISP_HASH_BASE 0x00000000 /* */
#define NV_UDISP_HASH_LIMIT 0x00001FFF /* */
#define NV_UDISP_OBJ_MEM_BASE 0x00002000 /* */
#define NV_UDISP_OBJ_MEM_LIMIT 0x0000FFFF /* */
#define NV_UDISP_HASH_TBL_CLIENT_ID (1*32+13):(1*32+0) /* RWXVF */
#define NV_UDISP_HASH_TBL_INSTANCE (1*32+24):(1*32+14) /* RWXUF */
#define NV_UDISP_HASH_TBL_CHN (1*32+31):(1*32+25) /* RWXUF */
#define NV_DMA_TARGET_NODE (0*32+1):(0*32+0) /* RWXVF */
#define NV_DMA_TARGET_NODE_PHYSICAL_NVM 0x00000001 /* RW--V */
#define NV_DMA_TARGET_NODE_PHYSICAL_PCI 0x00000002 /* RW--V */
#define NV_DMA_TARGET_NODE_PHYSICAL_PCI_COHERENT 0x00000003 /* RW--V */
#define NV_DMA_ACCESS (0*32+2):(0*32+2) /* RWXVF */
#define NV_DMA_ACCESS_READ_ONLY 0x00000000 /* RW--V */
#define NV_DMA_ACCESS_READ_AND_WRITE 0x00000001 /* RW--V */
#define NV_DMA_KIND (0*32+20):(0*32+20) /* RWXVF */
#define NV_DMA_KIND_PITCH 0x00000000 /* RW--V */
#define NV_DMA_KIND_BLOCKLINEAR 0x00000001 /* RW--V */
#define NV_DMA_ADDRESS_BASE_LO (1*32+31):(1*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_BASE_HI (2*32+6):(2*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_LIMIT_LO (3*32+31):(3*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_LIMIT_HI (4*32+6):(4*32+0) /* RWXUF */
#define NV_DMA_SIZE 20 /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_CORE 0x00680000 /* */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_CORE (0x00680000+32768) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN(i) ((0x00690000+(i)*4096)) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM(i) ((0x00690000+((i+32)*4096))) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_CURS(i) (0x006D8000+(i)*4096) /* RW-4A */
#define NV_UDISP_FE_CHN_ASSY_BASEADR(i) ((i)>0?(((0x00690000+(i-1)*4096))):0x00680000) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR__SIZE_1 81 /* */
#endif // __v03_00_dev_disp_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __v04_00_dev_disp_h__
#define __v04_00_dev_disp_h__
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING(i) (0x00611800+(i)*4) /* RW-4A */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_NOT_PENDING 0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_RESET 0x00000001 /* -W--V */
#define NV_PDISP_FE_RM_INTR_DISPATCH 0x00611EC0 /* R--4R */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_NOT_PENDING 0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_PENDING 0x00000001 /* R---V */
#define NV_PDISP_VGA_WORKSPACE_BASE 0x00625F04 /* RW-4R */
#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS 3:3 /* RWIVF */
#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_VALID 0x00000001 /* RW--V */
#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR 31:8 /* RWIVF */
#endif // __v04_00_dev_disp_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gk104_dev_timer_h__
#define __gk104_dev_timer_h__
#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */
#define NV_PTIMER_INTR_0_ALARM 0:0 /* RWXVF */
#define NV_PTIMER_INTR_0_ALARM_NOT_PENDING 0x00000000 /* R---V */
#define NV_PTIMER_INTR_0_ALARM_PENDING 0x00000001 /* R---V */
#define NV_PTIMER_INTR_0_ALARM_RESET 0x00000001 /* -W--V */
#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */
#define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* RWIVF */
#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* RWI-V */
#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* RW--V */
#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */
#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */
#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */
#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */
#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */
#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWXUF */
#endif // __gk104_dev_timer_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_boot_h__
#define __gm107_dev_boot_h__
#define NV_PMC 0x00000FFF:0x00000000 /* RW--D */
#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
#define NV_PMC_INTR(i) (0x00000100+(i)*4) /* RW-4A */
#define NV_PMC_INTR__SIZE_1 3 /* */
#define NV_PMC_INTR_DEVICE(i) (i):(i) /* */
#define NV_PMC_INTR_DEVICE__SIZE_1 31 /* */
#define NV_PMC_INTR_DEVICE_NOT_PENDING 0x00000000 /* */
#define NV_PMC_INTR_DEVICE_PENDING 0x00000001 /* */
#define NV_PMC_INTR_EN(i) (0x00000140+(i)*4) /* RW-4A */
#define NV_PMC_INTR_EN__SIZE_1 3 /* */
#define NV_PMC_INTR_0 0x00000100 /* */
#define NV_PMC_INTR_1 0x00000104 /* */
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_DEVICE(i) (i):(i) /* */
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#endif // __gm107_dev_boot_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_bus_h__
#define __gm107_dev_bus_h__
#define NV_PBUS_INTR_0 0x00001100 /* RW-4R */
#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 /* RWIVF */
#define NV_PBUS_INTR_0_PRI_SQUASH_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_PRI_SQUASH_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_PRI_SQUASH_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 /* RWIVF */
#define NV_PBUS_INTR_0_PRI_FECSERR_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_PRI_FECSERR_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_PRI_FECSERR_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 /* RWIVF */
#define NV_PBUS_INTR_0_PRI_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_PRI_TIMEOUT_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_PRI_TIMEOUT_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT 5:5 /* RWIVF */
#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_RESET 0x00000001 /* -W--C */
#define NV_PBUS_BAR0_WINDOW 0x00001700 /* RW-4R */
#define NV_PBUS_BAR0_WINDOW_BASE 23:0 /* RWIUF */
#define NV_PBUS_BAR0_WINDOW_BASE_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR0_WINDOW_TARGET 25:24 /* RWIUF */
#define NV_PBUS_BAR0_WINDOW_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR0_WINDOW_BASE_SHIFT 16 /* */
#define NV_PBUS_BAR2_BLOCK 0x00001714 /* RW-4R */
#define NV_PBUS_BAR2_BLOCK_MAP 29:0 /* RWXUF */
#define NV_PBUS_BAR2_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA 30:30 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_OFF 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_ON 0x00000000 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_INIT 0x00000001 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 /* */
#endif // __gm107_dev_bus_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_fb_h__
#define __gm107_dev_fb_h__
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR 0x00100C10 /* RW-4R */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_ADR_39_08 31:0 /* RWIVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x00100CB8 /* RW-4R */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_SYS_MEM 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_INVALIDATE 0x00100CBC /* RW-4R */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY 2:2 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 /* -WEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_FALSE 0x00000000 /* -WE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_TRUE 0x00000001 /* -W--T */
#endif // __gm107_dev_fb_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_flush_h__
#define __gm107_dev_flush_h__
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x00070004 /* RW-4R */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE 0x00070008 /* RW-4R */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS 0x0007000c /* RW-4R */
#define NV_UFLUSH_L2_FLUSH_DIRTY 0x00070010 /* RW-4R */
#define NV_UFLUSH_FB_FLUSH 0x00070000 /* RW-4R */
#endif // __gm107_dev_flush_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_mmu_h__
#define __gm107_dev_mmu_h__
#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */
#define NV_MMU_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */
#define NV_MMU_PDE_SIZE_FULL 0x00000000 /* RW--V */
#define NV_MMU_PDE_SIZE_HALF 0x00000001 /* RW--V */
#define NV_MMU_PDE_SIZE_QUARTER 0x00000002 /* RW--V */
#define NV_MMU_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */
#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */
#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */
#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */
#define NV_MMU_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_PDE__SIZE 8
#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */
#define NV_MMU_PTE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */
#define NV_MMU_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */
#define NV_MMU_PTE_READ_ONLY_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_READ_ONLY_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */
#define NV_MMU_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */
#define NV_MMU_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */
#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */
#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */
#define NV_MMU_PTE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PTE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */
#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PTE_LOCK (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_PTE_LOCK_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_LOCK_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) /* RWXVF */
#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) /* RWXVF */
#define NV_MMU_PTE_READ_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_READ_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) /* RWXVF */
#define NV_MMU_PTE_WRITE_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_WRITE_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_PTE__SIZE 8
#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */
#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe /* R---V */
#define NV_MMU_PTE_KIND_C32_2CRA 0xdb /* R---V */
#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 /* R---V */
#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 /* R---V */
#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 /* R---V */
#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 /* R---V */
#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 /* R---V */
#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee /* R---V */
#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef /* R---V */
#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 /* R---V */
#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 /* R---V */
#define NV_MMU_PTE_KIND_C128_2CR 0xf5 /* R---V */
#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 /* R---V */
#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 /* R---V */
#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb /* R---V */
#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb /* R---V */
#endif // __gm107_dev_mmu_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_nv_xve_h__
#define __gm107_dev_nv_xve_h__
#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */
#define NV_XVE_ID 0x00000000 /* R--4R */
#define NV_XVE_ID_VENDOR 15:0 /* C--VF */
#define NV_XVE_ID_VENDOR_NVIDIA 0x000010DE /* C---V */
#define NV_XVE_DEV_CTRL 0x00000004 /* RW-4R */
#define NV_XVE_DEV_CTRL_CMD_IO_SPACE 0:0 /* RWIVF */
#define NV_XVE_DEV_CTRL_CMD_IO_SPACE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_DEV_CTRL_CMD_IO_SPACE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_REV_ID 0x00000008 /* R--4R */
#define NV_XVE_REV_ID_CLASS_CODE 31:8 /* R-CVF */
#define NV_XVE_REV_ID_CLASS_CODE_3D 0x00030200 /* ----V */
#define NV_XVE_SUBSYSTEM 0x0000002C /* R--4R */
#define NV_XVE_MSI_CTRL 0x00000068 /* RW-4R */
#define NV_XVE_MSI_CTRL_MSI 16:16 /* RWIVF */
#define NV_XVE_MSI_CTRL_MSI_DISABLE 0x00000000 /* RWI-V */
#define NV_XVE_MSI_CTRL_MSI_ENABLE 0x00000001 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS 0x00000080 /* RWI4R */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE 0:0 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE 1:1 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE 2:2 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE 3:3 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING 4:4 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT 0x00000001 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE 7:5 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_128B 0x00000000 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_256B 0x00000001 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_512B 0x00000002 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_1024B 0x00000003 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_2048B 0x00000004 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_4096B 0x00000005 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:8 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT 0x00000001 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE 9:9 /* R-IVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE 10:10 /* R-IVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP 11:11 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP_INIT 0x00000001 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE 14:12 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE_INIT 0x00000002 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_RSVD 15:15 /* C--VF */
#define NV_XVE_DEVICE_CONTROL_STATUS_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED 16:16 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED 17:17 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED 18:18 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED 19:19 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED 20:20 /* R-IVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING 21:21 /* R-IVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING_INIT 0x00000000 /* R-I-V */
#define NV_XVE_LINK_CAPABILITIES 0x00000084 /* R--4R */
#define NV_XVE_LINK_CONTROL_STATUS 0x00000088 /* RWI4R */
#define NV_XVE_VCCAP_HDR 0x00000100 /* R--4R */
#define NV_XVE_VCCAP_HDR_ID 15:0 /* C--VF */
#define NV_XVE_VCCAP_HDR_ID_VC 0x00000002 /* C---V */
#define NV_XVE_VCCAP_HDR_VER 19:16 /* C--VF */
#define NV_XVE_VCCAP_HDR_VER_1 0x00000001 /* C---V */
#define NV_XVE_VCCAP_CTRL0 0x00000114 /* RW-4R */
#define NV_XVE_VCCAP_CTRL0_MAP 7:1 /* RWIVF */
#define NV_XVE_AER_UNCORR_ERR 0x00000424 /* RWC4R */
#define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR 4:4 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_POISONED_TLP 12:12 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT 14:14 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL 16:16 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP 18:18 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ 20:20 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR 0x00000430 /* RW-4R */
#define NV_XVE_AER_CORR_ERR_RCV_ERR 0:0 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_RCV_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_RCV_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_RCV_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_BAD_TLP 6:6 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_BAD_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_BAD_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_BAD_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_BAD_DLLP 7:7 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_BAD_DLLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_BAD_DLLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_BAD_DLLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER 8:8 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT 12:12 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL 13:13 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_CYA_2 0x00000704 /* RW-4R */
#endif // __gm107_dev_nv_xve_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_nv_xve1_h__
#define __gm107_dev_nv_xve1_h__
#define NV_PCFG1 0x0008AFFF:0x0008A000 /* RW--D */
#endif // __gm107_dev_nv_xve1_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_ram_h__
#define __gm107_dev_ram_h__
#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */
#define NV_PRAMIN_DATA032(i) (0x00700000+(i)*4) /* RW-4A */
#define NV_PRAMIN_DATA032__SIZE_1 524288 /* */
#define NV_PRAMIN_DATA032_VALUE 31:0 /* RWXUF */
#define NV_PRAMIN_DATA016(i) (0x00700000+((i)/3)*4+((i)%3)) /* RW-2A */
#define NV_PRAMIN_DATA016__SIZE_1 1572864 /* */
#define NV_PRAMIN_DATA016_VALUE 15:0 /* RWXUF */
#define NV_PRAMIN_DATA008(i) (0x00700000+(i)) /* RW-1A */
#define NV_PRAMIN_DATA008__SIZE_1 2097152 /* */
#define NV_PRAMIN_DATA008_VALUE 7:0 /* RWXUF */
#define NV_RAMIN_BASE_SHIFT 12 /* */
#define NV_RAMIN_ALLOC_SIZE 4096 /* */
#define NV_RAMIN_RAMFC (127*32+31):(0*32+0) /* RWXUF */
#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) /* RWXUF */
#define NV_RAMUSERD_GET (17*32+31):(17*32+0) /* RWXUF */
#define NV_RAMUSERD_REF (18*32+31):(18*32+0) /* RWXUF */
#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) /* RWXUF */
#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) /* */
#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) /* RWXUF */
#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) /* RWXUF */
#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) /* RWXUF */
#define NV_RAMUSERD_GP_GET (34*32+31):(34*32+0) /* RWXUF */
#define NV_RAMUSERD_GP_PUT (35*32+31):(35*32+0) /* RWXUF */
#define NV_RAMUSERD_BASE_SHIFT 9 /* */
#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) /* RWXUF */
#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) /* RWXUF */
#define NV_RAMRL_BASE_SHIFT 12 /* */
#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 0x00000003 /* RWI-V */
#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x00000080 /* RWI-V */
#define NV_RAMRL_ENTRY_SIZE 8 /* */
#define NV_RAMRL_ENTRY_TSG_LENGTH_MAX 0x00000020 /* RW--V */
#endif // __gm107_dev_ram_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_timer_h__
#define __gm107_dev_timer_h__
#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */
#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */
#define NV_PTIMER_TIMER_CFG0 0x00009300 /* RW-4R */
#define NV_PTIMER_TIMER_CFG0_DEN 4:0 /* RWIUF */
#define NV_PTIMER_TIMER_CFG0_DEN_108MHZ_REF 0x1b /* RWI-V */
#define NV_PTIMER_TIMER_CFG0_NUM 18:16 /* RWIUF */
#define NV_PTIMER_TIMER_CFG0_NUM_108MHZ_REF 0x7 /* RWI-V */
#define NV_PTIMER_TIMER_CFG1 0x00009304 /* RW-4R */
#define NV_PTIMER_TIMER_CFG1_INTEGER 5:0 /* RWIUF */
#define NV_PTIMER_TIMER_CFG1_INTEGER_108MHZ_REF 0x000009 /* RWI-V */
#define NV_PTIMER_GR_TICK_FREQ 0x00009480 /* RW-4R */
#define NV_PTIMER_GR_TICK_FREQ_SELECT 2:0 /* RWIUF */
#define NV_PTIMER_GR_TICK_FREQ_SELECT_MAX 0x00000000 /* RW--V */
#define NV_PTIMER_GR_TICK_FREQ_SELECT_DEFAULT 0x00000005 /* RWI-V */
#define NV_PTIMER_GR_TICK_FREQ_SELECT_MIN 0x00000007 /* RW--V */
#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */
#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */
#endif // __gm107_dev_timer_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_flush_h__
#define __gm200_dev_flush_h__
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x00070004 /* RW-4R */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE 0x00070008 /* RW-4R */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS 0x0007000c /* RW-4R */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_UFLUSH_L2_FLUSH_DIRTY 0x00070010 /* RW-4R */
#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING_TRUE 0x00000001 /* R---V */
#endif // __gm200_dev_flush_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_nv_p2p_h__
#define __gm200_dev_nv_p2p_h__
#define NV_P2P 0x0013AFFF:0x00139000 /* RW--D */
#define NV_P2P_WMBOX_ADDR_ADDR 18:1 /* RWIUF */
#define NV_P2P_WREQMB_L(i) (0x00139068+(i)*64) /* R--4A */
#define NV_P2P_WREQMB_L__SIZE_1 8 /* */
#define NV_P2P_WREQMB_L_PAGE_ADDR 20:0 /* R-IUF */
#define NV_P2P_WREQMB_L_PAGE_ADDR_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WREQMB_H(i) (0x0013906c+(i)*64) /* R--4A */
#define NV_P2P_WREQMB_H__SIZE_1 8 /* */
#define NV_P2P_WREQMB_H_KIND 7:0 /* R-IUF */
#define NV_P2P_WREQMB_H_KIND_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WREQMB_H_COMPTAGLINE 24:8 /* R-IUF */
#define NV_P2P_WREQMB_H_COMPTAGLINE_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WREQMB_H_PAGE_SIZE 25:25 /* R-IUF */
#define NV_P2P_WREQMB_H_PAGE_SIZE_INIT 0x00000000 /* R-I-V */
#endif // __gm200_dev_nv_p2p_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_timer_h__
#define __gm200_dev_timer_h__
#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */
#define NV_PTIMER_INTR_0_TIMER 1:1 /* RWXVF */
#define NV_PTIMER_INTR_0_TIMER_NOT_PENDING 0x00000000 /* R---V */
#define NV_PTIMER_INTR_0_TIMER_PENDING 0x00000001 /* R---V */
#define NV_PTIMER_INTR_0_TIMER_RESET 0x00000001 /* -W--C */
#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */
#define NV_PTIMER_INTR_EN_0_TIMER 1:1 /* RWIVF */
#define NV_PTIMER_INTR_EN_0_TIMER_DISABLED 0x00000000 /* RWI-V */
#define NV_PTIMER_INTR_EN_0_TIMER_ENABLED 0x00000001 /* RW--V */
#define NV_PTIMER_TIMER_0 0x00009428 /* RW-4R */
#endif // __gm200_dev_timer_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NV_ARCH_PUBLISHED_H
#define NV_ARCH_PUBLISHED_H
// high byte indicates GPU-SERIES, as defined in Gpus.pm.
#define NVGPU_ARCHITECTURE_SERIES 31:24
#define NVGPU_ARCHITECTURE_SERIES_CLASSIC 0x00
#define NVGPU_ARCHITECTURE_SERIES_SIMULATION 0x00 // XXX - really should be distinct from CLASSIC_GPUS
#define NVGPU_ARCHITECTURE_SERIES_TEGRA 0xE0
#define NVGPU_ARCHITECTURE_ARCH 23:0
#define GPU_ARCHITECTURE(series, arch) (DRF_DEF(GPU, _ARCHITECTURE, _SERIES, series) | \
DRF_NUM(GPU, _ARCHITECTURE, _ARCH, arch))
//
// Architecture constants.
//
#define GPU_ARCHITECTURE_MAXWELL GPU_ARCHITECTURE(_CLASSIC, 0x0110)
#define GPU_ARCHITECTURE_MAXWELL2 GPU_ARCHITECTURE(_CLASSIC, 0x0120)
#define GPU_ARCHITECTURE_PASCAL GPU_ARCHITECTURE(_CLASSIC, 0x0130)
#define GPU_ARCHITECTURE_VOLTA GPU_ARCHITECTURE(_CLASSIC, 0x0140)
#define GPU_ARCHITECTURE_VOLTA2 GPU_ARCHITECTURE(_CLASSIC, 0x0150)
#define GPU_ARCHITECTURE_TURING GPU_ARCHITECTURE(_CLASSIC, 0x0160)
#define GPU_ARCHITECTURE_AMPERE GPU_ARCHITECTURE(_CLASSIC, 0x0170)
#define GPU_ARCHITECTURE_T12X GPU_ARCHITECTURE(_TEGRA, 0x0040)
#define GPU_ARCHITECTURE_T13X GPU_ARCHITECTURE(_TEGRA, 0x0013)
#define GPU_ARCHITECTURE_T21X GPU_ARCHITECTURE(_TEGRA, 0x0021)
#define GPU_ARCHITECTURE_T18X GPU_ARCHITECTURE(_TEGRA, 0x0018)
#define GPU_ARCHITECTURE_T19X GPU_ARCHITECTURE(_TEGRA, 0x0019)
#define GPU_ARCHITECTURE_T23X GPU_ARCHITECTURE(_TEGRA, 0x0023)
#define GPU_ARCHITECTURE_SIMS GPU_ARCHITECTURE(_SIMULATION, 0x01f0) // eg: AMODEL
//
// Implementation constants.
// These must be unique within a single architecture.
//
#define GPU_IMPLEMENTATION_GM108 0x08
#define GPU_IMPLEMENTATION_GM107 0x07
#define GPU_IMPLEMENTATION_GM200 0x00
#define GPU_IMPLEMENTATION_GM204 0x04
#define GPU_IMPLEMENTATION_GM206 0x06
#define GPU_IMPLEMENTATION_GP100 0x00
#define GPU_IMPLEMENTATION_GP102 0x02
#define GPU_IMPLEMENTATION_GP104 0x04
#define GPU_IMPLEMENTATION_GP106 0x06
#define GPU_IMPLEMENTATION_GP107 0x07
#define GPU_IMPLEMENTATION_GP108 0x08
#define GPU_IMPLEMENTATION_GV100 0x00
#define GPU_IMPLEMENTATION_GV11B 0x0B
#define GPU_IMPLEMENTATION_TU102 0x02
#define GPU_IMPLEMENTATION_TU104 0x04
#define GPU_IMPLEMENTATION_TU106 0x06
#define GPU_IMPLEMENTATION_TU116 0x08 // TU116 has implementation ID 8 in HW
#define GPU_IMPLEMENTATION_TU117 0x07
#define GPU_IMPLEMENTATION_GA100 0x00
#define GPU_IMPLEMENTATION_GA102 0x02
#define GPU_IMPLEMENTATION_GA103 0x03
#define GPU_IMPLEMENTATION_GA104 0x04
#define GPU_IMPLEMENTATION_GA106 0x06
#define GPU_IMPLEMENTATION_GA107 0x07
#define GPU_IMPLEMENTATION_GA102F 0x0F
#define GPU_IMPLEMENTATION_T124 0x00
#define GPU_IMPLEMENTATION_T132 0x00
#define GPU_IMPLEMENTATION_T210 0x00
#define GPU_IMPLEMENTATION_T186 0x00
#define GPU_IMPLEMENTATION_T194 0x00
#define GPU_IMPLEMENTATION_T234 0x04
#define GPU_IMPLEMENTATION_T234D 0x05
/* SIMS gpus */
#define GPU_IMPLEMENTATION_AMODEL 0x00
#endif // NV_ARCH_PUBLISHED_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
//
/***************************************************************************\
* *
* Hardware Reference Manual extracted defines. *
* - Defines in this file are approved by the HW team for publishing. *
* *
\***************************************************************************/
#ifndef NV_REF_PUBLISHED_H
#define NV_REF_PUBLISHED_H
//
// These registers can be accessed by chip-independent code as
// well as chip-dependent code.
//
// NOTE: DO NOT ADD TO THIS FILE. CREATE CHIP SPECIFIC HAL ROUTINES INSTEAD.
//
/*
* Standard PCI config space header defines.
* The defines here cannot change across generations.
*/
/* dev_nv_xve.ref */
/* PBUS field defines converted to NV_CONFIG field defines */
#define NV_CONFIG_PCI_NV_0 0x00000000 /* R--4R */
#define NV_CONFIG_PCI_NV_0_VENDOR_ID 15:0 /* C--UF */
#define NV_CONFIG_PCI_NV_0_VENDOR_ID_NVIDIA 0x000010DE /* C---V */
#define NV_CONFIG_PCI_NV_0_DEVICE_ID 31:16 /* R--UF */
#define NV_CONFIG_PCI_NV_1 0x00000004 /* RW-4R */
#define NV_CONFIG_PCI_NV_1_IO_SPACE 0:0 /* RWIVF */
#define NV_CONFIG_PCI_NV_1_IO_SPACE_DISABLED 0x00000000 /* RWI-V */
#define NV_CONFIG_PCI_NV_1_IO_SPACE_ENABLED 0x00000001 /* RW--V */
#define NV_CONFIG_PCI_NV_1_MEMORY_SPACE 1:1 /* RWIVF */
#define NV_CONFIG_PCI_NV_1_MEMORY_SPACE_DISABLED 0x00000000 /* RWI-V */
#define NV_CONFIG_PCI_NV_1_MEMORY_SPACE_ENABLED 0x00000001 /* RW--V */
#define NV_CONFIG_PCI_NV_1_BUS_MASTER 2:2 /* RWIVF */
#define NV_CONFIG_PCI_NV_1_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */
#define NV_CONFIG_PCI_NV_1_BUS_MASTER_ENABLED 0x00000001 /* RW--V */
#define NV_CONFIG_PCI_NV_2 0x00000008 /* R--4R */
#define NV_CONFIG_PCI_NV_2_REVISION_ID 7:0 /* C--UF */
#define NV_CONFIG_PCI_NV_2_CLASS_CODE 31:8 /* C--VF */
#define NV_CONFIG_PCI_NV_3 0x0000000C /* RW-4R */
#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER 15:11 /* RWIUF */
#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER_0_CLOCKS 0x00000000 /* RWI-V */
#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER_8_CLOCKS 0x00000001 /* RW--V */
#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER_240_CLOCKS 0x0000001E /* RW--V */
#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER_248_CLOCKS 0x0000001F /* RW--V */
#define NV_CONFIG_PCI_NV_4 0x00000010 /* RW-4R */
#define NV_CONFIG_PCI_NV_5 0x00000014 /* RW-4R */
#define NV_CONFIG_PCI_NV_5_ADDRESS_TYPE 2:1 /* C--VF */
#define NV_CONFIG_PCI_NV_5_ADDRESS_TYPE_64_BIT 0x00000002 /* ----V */
#define NV_CONFIG_PCI_NV_6 0x00000018 /* RW-4R */
#define NV_CONFIG_PCI_NV_7(i) (0x0000001C+(i)*4) /* R--4A */
#define NV_CONFIG_PCI_NV_11 0x0000002C /* R--4R */
#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_VENDOR_ID 15:0 /* R--UF */
#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_VENDOR_ID_NONE 0x00000000 /* R---V */
#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_ID 31:16 /* R--UF */
#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_ID_NONE 0x00000000 /* R---V */
#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_ID_TNT2PRO 0x0000001f
#define NV_CONFIG_PCI_NV_12 0x00000030 /* RW-4R */
#define NV_CONFIG_PCI_NV_13 0x00000034 /* RW-4R */
#define NV_CONFIG_PCI_NV_13_CAP_PTR 7:0 /* C--VF */
#define NV_CONFIG_PCI_NV_14 0x00000038 /* R--4R */
#define NV_CONFIG_PCI_NV_15 0x0000003C /* RW-4R */
#define NV_CONFIG_PCI_NV_15_INTR_LINE 7:0 /* RWIVF */
/*
* These defines are the correct fields to be used to extract the
* NEXT_PTR and CAP_ID from any PCI capability structure,
* but they still have NV_24 in the name because they were from the
* first PCI capability structure in the capability list in older GPUs.
*/
#define NV_CONFIG_PCI_NV_24_NEXT_PTR 15:8 /* R--VF */
#define NV_CONFIG_PCI_NV_24_CAP_ID 7:0 /* C--VF */
/*
* Standard registers present on NVIDIA chips used to ID the chip.
* Very stable across generations.
*/
/* dev_master.ref */
#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* R--VF */
#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* R--VF */
#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 /* R--VF */
#define NV_PMC_BOOT_0_IMPLEMENTATION_0 0x00000000 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_4 0x00000004 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_5 0x00000005 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_6 0x00000006 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_7 0x00000007 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_8 0x00000008 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_9 0x00000009 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_A 0x0000000A /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0x0000000B /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_C 0x0000000C /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_D 0x0000000D /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_E 0x0000000E /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_F 0x0000000F /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 /* R--VF */
#define NV_PMC_BOOT_0_ARCHITECTURE_TU100 0x00000016 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_TU110 0x00000016 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 0x00000017 /* R---V */
#define NV_PMC_BOOT_1 0x00000004 /* R--4R */
#define NV_PMC_BOOT_1_VGPU8 8:8 /* R--VF */
#define NV_PMC_BOOT_1_VGPU8_REAL 0x00000000 /* R-I-V */
#define NV_PMC_BOOT_1_VGPU8_VIRTUAL 0x00000001 /* R---V */
#define NV_PMC_BOOT_1_VGPU16 16:16 /* R--VF */
#define NV_PMC_BOOT_1_VGPU16_REAL 0x00000000 /* R-I-V */
#define NV_PMC_BOOT_1_VGPU16_VIRTUAL 0x00000001 /* R---V */
#define NV_PMC_BOOT_1_VGPU 17:16 /* C--VF */
#define NV_PMC_BOOT_1_VGPU_REAL 0x00000000 /* C---V */
#define NV_PMC_BOOT_1_VGPU_PV 0x00000001 /* ----V */
#define NV_PMC_BOOT_1_VGPU_VF 0x00000002 /* ----V */
#define NV_PMC_BOOT_42 0x00000A00 /* R--4R */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION 11:8 /* R-XVF */
#define NV_PMC_BOOT_42_MINOR_REVISION 15:12 /* R-XVF */
#define NV_PMC_BOOT_42_MAJOR_REVISION 19:16 /* R-XVF */
#define NV_PMC_BOOT_42_IMPLEMENTATION 23:20 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE 28:24 /* */
#define NV_PMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */
/* dev_arapb_misc.h */
#define NV_PAPB_MISC_GP_HIDREV_CHIPID 15:8 /* ----F */
#define NV_PAPB_MISC_GP_HIDREV_MAJORREV 7:4 /* ----F */
#endif // NV_REF_PUBLISHED_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_egress_ip_h__
#define __lr10_dev_egress_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_EGRESS_ERR_LOG_EN_0 0x00004404 /* RW-4R */
#define NV_EGRESS_ERR_LOG_EN_0_EGRESSBUFERR 0:0 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_EGRESSBUFERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_PKTROUTEERR 1:1 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_PKTROUTEERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_SEQIDERR 2:2 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_SEQIDERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOCCREDITOVFL__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR 10:10 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR 11:11 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR 12:12 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0 0x00004410 /* RW-4R */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_EGRESSBUFERR 0:0 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_EGRESSBUFERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PKTROUTEERR 1:1 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PKTROUTEERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_SEQIDERR 2:2 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_SEQIDERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOCCREDITOVFL__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_URRSPERR 10:10 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_URRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PRIVRSPERR 11:11 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PRIVRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_HWRSPERR 12:12 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_HWRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_TIMESTAMP_LOG 0x00004450 /* R--4R */
#define NV_EGRESS_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-IVF */
#define NV_EGRESS_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_ERR_HEADER_LOG_VALID 0x0000444c /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0 0:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0_INVALID 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0_VALID 0x00000001 /* R---V */
#define NV_EGRESS_ERR_MISC_LOG_0 0x00004454 /* R--4R */
#define NV_EGRESS_ERR_MISC_LOG_0_SPORT 5:0 /* R-IVF */
#define NV_EGRESS_ERR_MISC_LOG_0_SPORT_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_ERR_MISC_LOG_0_ENCODEDVC 10:8 /* R-IVF */
#define NV_EGRESS_ERR_MISC_LOG_0_ENCODEDVC_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_ERR_HEADER_LOG_0 0x00004420 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_0_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_0_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_1 0x00004424 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_1_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_1_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_2 0x00004428 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_2_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_2_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_3 0x0000442c /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_3_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_3_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_4 0x00004430 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_4_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_4_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_5 0x00004434 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_5_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_5_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_6 0x00004438 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_6_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_6_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_7 0x0000443c /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_7_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_7_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_8 0x00004440 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_8_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_8_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_9 0x00004444 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_9_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_9_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_10 0x00004448 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_10_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_10_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS 0x00004494 /* R--4R */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_FIRST_0 0x0000441c /* RW-4R */
#define NV_EGRESS_ERR_FIRST_0_EGRESSBUFERR 0:0 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_EGRESSBUFERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_EGRESSBUFERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_PKTROUTEERR 1:1 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_PKTROUTEERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_PKTROUTEERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_SEQIDERR 2:2 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_SEQIDERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_SEQIDERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_NCISOCCREDITOVFL 7:7 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_NCISOCCREDITOVFL_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_NCISOCCREDITOVFL_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_REQTGTIDMISMATCHERR 8:8 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_REQTGTIDMISMATCHERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_REQTGTIDMISMATCHERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_RSPREQIDMISMATCHERR 9:9 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_RSPREQIDMISMATCHERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_RSPREQIDMISMATCHERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_URRSPERR 10:10 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_URRSPERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_URRSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_PRIVRSPERR 11:11 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_PRIVRSPERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_PRIVRSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_HWRSPERR 12:12 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_HWRSPERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_HWRSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_NCISOC_CREDIT_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_NCISOC_CREDIT_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_FLITTYPE_MISMATCH_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_FLITTYPE_MISMATCH_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_CREDIT_TIME_OUT_ERR 16:16 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_CREDIT_TIME_OUT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_CREDIT_TIME_OUT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0 0x00004414 /* RW-4R */
#define NV_EGRESS_ERR_CONTAIN_EN_0_EGRESSBUFERR 0:0 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_EGRESSBUFERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PKTROUTEERR 1:1 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PKTROUTEERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_SEQIDERR 2:2 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_SEQIDERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOCCREDITOVFL__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR 10:10 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PRIVRSPERR 11:11 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PRIVRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR 12:12 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_BUFFER_POINTERS0 0x00004310 /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS0_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS0_WRITE_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS0_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS0_READ_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS1 0x00004314 /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS1_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS1_WRITE_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS1_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS1_READ_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS2 0x00004318 /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS2_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS2_WRITE_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS2_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS2_READ_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS3 0x0000431c /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS3_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS3_WRITE_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS3_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS3_READ_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS4 0x00004320 /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS4_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS4_WRITE_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS4_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS4_READ_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS5 0x00004324 /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS5_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS5_WRITE_INIT 0x00000040 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS5_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS5_READ_INIT 0x00000040 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS6 0x00004328 /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS6_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS6_WRITE_INIT 0x00000080 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS6_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS6_READ_INIT 0x00000080 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS7 0x0000432c /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS7_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS7_WRITE_INIT 0x000000c0 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS7_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS7_READ_INIT 0x000000c0 /* R-E-V */
#define NV_EGRESS_ERR_STATUS_0 0x00004400 /* RW-4R */
#define NV_EGRESS_ERR_STATUS_0_EGRESSBUFERR 0:0 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_EGRESSBUFERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_EGRESSBUFERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_PKTROUTEERR 1:1 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_PKTROUTEERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_PKTROUTEERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_SEQIDERR 2:2 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_SEQIDERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_SEQIDERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_NCISOCCREDITOVFL 7:7 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_NCISOCCREDITOVFL_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_NCISOCCREDITOVFL_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_REQTGTIDMISMATCHERR 8:8 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_REQTGTIDMISMATCHERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_REQTGTIDMISMATCHERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_RSPREQIDMISMATCHERR 9:9 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_RSPREQIDMISMATCHERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_RSPREQIDMISMATCHERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_URRSPERR 10:10 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_URRSPERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_URRSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_PRIVRSPERR 11:11 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_PRIVRSPERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_PRIVRSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_HWRSPERR 12:12 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_HWRSPERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_HWRSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_NCISOC_CREDIT_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_NCISOC_CREDIT_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_FLITTYPE_MISMATCH_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_FLITTYPE_MISMATCH_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_CREDIT_TIME_OUT_ERR 16:16 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_CREDIT_TIME_OUT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_CREDIT_TIME_OUT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_NCISOC_CREDIT0 0x00004370 /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT0_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT0_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT1 0x00004374 /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT1_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT1_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT2 0x00004378 /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT2_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT2_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT3 0x0000437c /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT3_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT3_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT4 0x00004380 /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT4_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT4_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT5 0x00004384 /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT5_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT5_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT6 0x00004388 /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT6_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT6_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT7 0x0000438c /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT7_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT7_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER 0x00004480 /* RW-4R */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_LIMIT 0x00004484 /* RW-4R */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER 0x0000448c /* RW-4R */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_LIMIT 0x00004490 /* RW-4R */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_EGRESS_CTRL 0x00004040 /* RW-4R */
#define NV_EGRESS_CTRL_DESTINATIONIDCHECKENB 0:0 /* RWEVF */
#define NV_EGRESS_CTRL_DESTINATIONIDCHECKENB_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_CTRL_DESTINATIONIDCHECKENB_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_CTRL_DESTINATIONIDCHECKENB__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_CTRL_ZERO_OUT_SWXATTR_DISABLE 1:1 /* RWEVF */
#define NV_EGRESS_CTRL_ZERO_OUT_SWXATTR_DISABLE_OFF 0x00000000 /* RWE-V */
#define NV_EGRESS_CTRL_ZERO_OUT_SWXATTR_DISABLE_SET 0x00000001 /* RW--V */
#define NV_EGRESS_CTRL_CTO_ENB 9:9 /* RWEVF */
#define NV_EGRESS_CTRL_CTO_ENB_ON 0x00000001 /* RW--V */
#define NV_EGRESS_CTRL_CTO_ENB_OFF 0x00000000 /* RWE-V */
#define NV_EGRESS_CTRL_CTO_ENB__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_CTO_TIMER_LIMIT 0x00004048 /* RW-4R */
#define NV_EGRESS_CTO_TIMER_LIMIT_LIMIT 19:0 /* RWEVF */
#define NV_EGRESS_CTO_TIMER_LIMIT_LIMIT_INIT 0x000fffff /* RWE-V */
#define NV_EGRESS_CTO_TIMER_LIMIT_LIMIT__PROD 0x00004000 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0 0x00004408 /* RW-4R */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_EGRESSBUFERR 0:0 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_EGRESSBUFERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PKTROUTEERR 1:1 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PKTROUTEERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_SEQIDERR 2:2 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_SEQIDERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOCCREDITOVFL__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR 10:10 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PRIVRSPERR 11:11 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PRIVRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR 12:12 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0 0x0000440c /* RW-4R */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_EGRESSBUFERR 0:0 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_EGRESSBUFERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PKTROUTEERR 1:1 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PKTROUTEERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_SEQIDERR 2:2 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_SEQIDERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOCCREDITOVFL__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_URRSPERR 10:10 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_URRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR 11:11 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_HWRSPERR 12:12 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_HWRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL 0x00004470 /* RW-4R */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_ECC_ENABLE 0:0 /* RWEVF */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_PARITY_ENABLE 1:1 /* RWEVF */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_PARITY_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_RAM_OUT_ECC_ENABLE 8:8 /* RWEVF */
#define NV_EGRESS_ERR_ECC_CTRL_RAM_OUT_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_RAM_OUT_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_ECC_CTRL_RAM_OUT_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE 9:9 /* RWEVF */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE 10:10 /* RWEVF */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID 0x00004498 /* R--4R */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#endif // __lr10_dev_egress_ip_h__

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src/common/inc/swref/published/nvswitch/lr10/dev_ext_devices.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_ext_devices_h__
#define __lr10_dev_ext_devices_h__
/* This file is autogenerated. Do not edit */
#define NV_PROM_DATA(i) (0x00300000+(i)) /* RW-1A */
#define NV_PROM_DATA__SIZE_1 1048576 /* */
#define NV_PROM_DATA_VALUE 7:0 /* RW-VF */
#endif // __lr10_dev_ext_devices_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_falcon_v4_h__
#define __lr10_dev_falcon_v4_h__
/* This file is autogenerated. Do not edit */
#define NV_PFALCON_FALCON_INTR_RETRIGGER(i) (0x000003e8+(i)*4) /* -W-4A */
#define NV_PFALCON_FALCON_INTR_RETRIGGER__SIZE_1 2 /* */
#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */
#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_HWCFG1 0x0000012c /* R--4R */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_INIT 0x00000006 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_1_0 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_2_0 0x00000002 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_3_0 0x00000003 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_4_0 0x00000004 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_5_0 0x00000005 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_6_0 0x00000006 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_7_0 0x00000007 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x00000003 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x00000002 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x00000003 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x00000002 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x00000003 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_IMEM_PORTS_INIT 0x00000001 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_PORTS_INIT 0x00000001 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_TAG_WIDTH_INIT 0x00000010 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00000010 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x00000001 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x00000001 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x00000001 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_IRQSSET 0x00000000 /* -W-4R */
#define NV_PFALCON_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_HALT 4:4 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_EXT 15:8 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_DMA 16:16 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_SHA 17:17 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_SHA_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_MEMERR 18:18 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_MEMERR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_FALCON 19:19 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_FALCON_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_RISCV 20:20 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_RISCV_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_TRACE 21:21 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_TRACE_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_TRACEPC 0x0000014c /* R--4R */
#define NV_PFALCON_FALCON_TRACEPC_PC 23:0 /* R--VF */
#define NV_PFALCON_FALCON_TRACEIDX 0x00000148 /* RW-4R */
#define NV_PFALCON_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */
#define NV_PFALCON_FALCON_TRACEIDX_CNT_INIT 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */
#define NV_PFALCON_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */
#define NV_PFALCON_FALCON_TRACEIDX_IDX_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQSCLR 0x00000004 /* -W-4R */
#define NV_PFALCON_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_EXT 15:8 /* */
#define NV_PFALCON_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SHA 17:17 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SHA_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_MEMERR 18:18 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_MEMERR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_FALCON 19:19 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_FALCON_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_RISCV 20:20 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_RISCV_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_TRACE 21:21 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_TRACE_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IMEMT(i) (0x00000188+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMT__SIZE_1 4 /* */
#define NV_PFALCON_FALCON_IMEMT_TAG 15:0 /* RW-VF */
#define NV_PFALCON_FALCON_IMEMD(i) (0x00000184+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMD__SIZE_1 4 /* */
#define NV_PFALCON_FALCON_IMEMD_DATA 31:0 /* RW-VF */
#define NV_PFALCON_FALCON_IMEMC(i) (0x00000180+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMC__SIZE_1 4 /* */
#define NV_PFALCON_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IMEMC_BLK 23:8 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_AINCR 25:25 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */
#define NV_PFALCON_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */
#define NV_PFALCON_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */
#define NV_PFALCON_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_DMEMC(i) (0x000001c0+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMC__SIZE_1 8 /* */
#define NV_PFALCON_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_OFFS 7:2 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_BLK 23:8 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCR 25:25 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_VA 28:28 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_MISS 29:29 /* R-IVF */
#define NV_PFALCON_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */
#define NV_PFALCON_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */
#define NV_PFALCON_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMD__SIZE_1 8 /* */
#define NV_PFALCON_FALCON_DMEMD_DATA 31:0 /* RW-VF */
#define NV_PFALCON_FALCON_DMACTL 0x0000010c /* RW-4R */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMACTL_DMAQ_NUM 6:3 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_SECURE_STAT 7:7 /* R--VF */
#define NV_PFALCON_FALCON_BOOTVEC 0x00000104 /* RW-4R */
#define NV_PFALCON_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_CPUCTL 0x00000100 /* RW-4R */
#define NV_PFALCON_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
#define NV_PFALCON_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */
#define NV_PFALCON_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS 0x00000130 /* -W-4R */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQSTAT 0x00000008 /* R--4R */
#define NV_PFALCON_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_EXT 15:8 /* */
#define NV_PFALCON_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_MEMERR 18:18 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_MEMERR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_MEMERR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_FALCON 19:19 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_FALCON_TURE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_FALCON_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_RISCV 20:20 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_RISCV_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_RISCV_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_TRACE 21:21 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_TRACE_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_TRACE_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */
#define NV_PFALCON_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_HALT 4:4 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_EXT 15:8 /* */
#define NV_PFALCON_FALCON_IRQMASK_DMA 16:16 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_SHA 17:17 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_SHA_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_SHA_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_MEMERR 18:18 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_MEMERR_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_MEMERR_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_FALCON 19:19 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_FALCON_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_FALCON_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_RISCV 20:20 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_RISCV_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_RISCV_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_TRACE 21:21 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_TRACE_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_TRACE_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQDEST 0x0000001c /* RW-4R */
#define NV_PFALCON_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_EXT 15:8 /* */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXT 31:24 /* */
#define NV_PFALCON_FALCON_OS 0x00000080 /* RW-4R */
#define NV_PFALCON_FALCON_OS_VERSION 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */
#endif // __lr10_dev_falcon_v4_h__

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@@ -0,0 +1,928 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_ingress_ip_h__
#define __lr10_dev_ingress_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_INGRESS_ERR_LOG_EN_0 0x00001404 /* RW-4R */
#define NV_INGRESS_ERR_LOG_EN_0_CMDDECODEERR 0:0 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_CMDDECODEERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL 3:3 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET 6:6 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTABCFGERR 8:8 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTABCFGERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTABCFGERR 9:9 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTABCFGERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR 17:17 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0 0x00001410 /* RW-4R */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_CMDDECODEERR 0:0 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_CMDDECODEERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQCONTEXTMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ACLFAIL 3:3 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ACLFAIL__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_INVALIDVCSET 6:6 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_INVALIDVCSET__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRBOUNDSERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTABCFGERR 8:8 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTABCFGERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTABCFGERR 9:9 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTABCFGERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRTYPEERR 17:17 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRTYPEERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_TIMESTAMP_LOG 0x00001450 /* R--4R */
#define NV_INGRESS_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-IVF */
#define NV_INGRESS_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-I-V */
#define NV_INGRESS_ERR_HEADER_LOG_VALID 0x0000144c /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0 0:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0_INVALID 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0_VALID 0x00000001 /* R---V */
#define NV_INGRESS_ERR_MISC_LOG_0 0x00001454 /* R--4R */
#define NV_INGRESS_ERR_MISC_LOG_0_SPORT 5:0 /* R-IVF */
#define NV_INGRESS_ERR_MISC_LOG_0_SPORT_INIT 0x00000000 /* R-I-V */
#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC 10:8 /* R-IVF */
#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC_CREQ0 0x00000000 /* R-I-V */
#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC_RSP0 0x00000005 /* R---V */
#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC_CREQ1 0x00000006 /* R---V */
#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC_RSP1 0x00000007 /* R---V */
#define NV_INGRESS_ERR_HEADER_LOG_0 0x00001420 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_0_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_0_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_1 0x00001424 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_1_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_1_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_2 0x00001428 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_2_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_2_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_3 0x0000142c /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_3_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_3_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_4 0x00001430 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_4_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_4_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_5 0x00001434 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_5_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_5_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_6 0x00001438 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_6_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_6_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_7 0x0000143c /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_7_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_7_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_8 0x00001440 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_8_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_8_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_9 0x00001444 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_9_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_9_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_10 0x00001448 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_10_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_10_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0 0x00001414 /* RW-4R */
#define NV_INGRESS_ERR_CONTAIN_EN_0_CMDDECODEERR 0:0 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_CMDDECODEERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REQCONTEXTMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ACLFAIL 3:3 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ACLFAIL__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET 6:6 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRBOUNDSERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTABCFGERR 8:8 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTABCFGERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTABCFGERR 9:9 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTABCFGERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRTYPEERR 17:17 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRTYPEERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER 0x00001480 /* RW-4R */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS 0x00001488 /* R--4R */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID 0x0000148c /* R--4R */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER 0x00001490 /* RW-4R */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS 0x00001498 /* R--4R */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID 0x0000149c /* R--4R */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER 0x000014a0 /* RW-4R */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS 0x000014a8 /* R--4R */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID 0x000014ac /* R--4R */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_INGRESS_ERR_FIRST_0 0x0000141c /* RW-4R */
#define NV_INGRESS_ERR_FIRST_0_CMDDECODEERR 0:0 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_CMDDECODEERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_CMDDECODEERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_REQCONTEXTMISMATCHERR 2:2 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_REQCONTEXTMISMATCHERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_REQCONTEXTMISMATCHERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_ACLFAIL 3:3 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_ACLFAIL_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_ACLFAIL_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_INVALIDVCSET 6:6 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_INVALIDVCSET_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_INVALIDVCSET_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_ADDRBOUNDSERR 7:7 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_ADDRBOUNDSERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_ADDRBOUNDSERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_RIDTABCFGERR 8:8 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_RIDTABCFGERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_RIDTABCFGERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_RLANTABCFGERR 9:9 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_RLANTABCFGERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_RLANTABCFGERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_PARITY_ERR 13:13 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_ADDRTYPEERR 17:17 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_ADDRTYPEERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_ADDRTYPEERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0 0x00001400 /* RW-4R */
#define NV_INGRESS_ERR_STATUS_0_CMDDECODEERR 0:0 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_CMDDECODEERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_CMDDECODEERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_REQCONTEXTMISMATCHERR 2:2 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_REQCONTEXTMISMATCHERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_REQCONTEXTMISMATCHERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_ACLFAIL 3:3 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_ACLFAIL_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_ACLFAIL_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_INVALIDVCSET 6:6 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_INVALIDVCSET_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_INVALIDVCSET_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_ADDRBOUNDSERR 7:7 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_ADDRBOUNDSERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_ADDRBOUNDSERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_RIDTABCFGERR 8:8 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_RIDTABCFGERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_RIDTABCFGERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_RLANTABCFGERR 9:9 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_RLANTABCFGERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_RLANTABCFGERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_PARITY_ERR 13:13 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_ADDRTYPEERR 17:17 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_ADDRTYPEERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_ADDRTYPEERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_REMAPTABDATA0 0x00001090 /* RW-4R */
#define NV_INGRESS_REMAPTABDATA0_RMAP_ADDR 10:0 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA0_RMAP_ADDR_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA0_IRL_SEL 16:15 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA0_IRL_SEL_SELECTNONE 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA0_IRL_SEL_SELECTIRL0 0x00000001 /* RW--V */
#define NV_INGRESS_REMAPTABDATA0_IRL_SEL_SELECTIRL1 0x00000002 /* RW--V */
#define NV_INGRESS_REMAPTABDATA0_IRL_SEL_ENABLEERRRSP 0x00000003 /* RW--V */
#define NV_INGRESS_REMAPTABDATA0_ECC 30:22 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA0_ECC_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA0_ACLVALID 31:31 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA0_ACLVALID_INVALID 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA0_ACLVALID_VALID 0x00000001 /* RW--V */
#define NV_INGRESS_REMAPTABDATA1 0x00001094 /* RW-4R */
#define NV_INGRESS_REMAPTABDATA1_REQCTXT_MSK 15:0 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA1_REQCTXT_MSK_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA1_REQCTXT_CHK 31:16 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA1_REQCTXT_CHK_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA2 0x00001098 /* RW-4R */
#define NV_INGRESS_REMAPTABDATA2_REQCTXT_REP 15:0 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA2_REQCTXT_REP_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA2_ADR_OFFSET 31:16 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA2_ADR_OFFSET_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA3 0x0000109c /* RW-4R */
#define NV_INGRESS_REMAPTABDATA3_ADR_BASE 15:0 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA3_ADR_BASE_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA3_ADR_LIMIT 31:16 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA3_ADR_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4 0x000010a0 /* RW-4R */
#define NV_INGRESS_REMAPTABDATA4_TGTID 10:0 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_TGTID_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4_P2R_SWIZ 12:12 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_P2R_SWIZ_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4_PLANE_SELECT 13:13 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_PLANE_SELECT_EVEN 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4_PLANE_SELECT_ODD 0x00000001 /* RW--V */
#define NV_INGRESS_REMAPTABDATA4_MULT2 14:14 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_MULT2_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4_RFUNC 21:15 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_RFUNC_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4_GPU_DIV 26:24 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_GPU_DIV_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4_RSVD 31:27 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_RSVD_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0 0x000010b0 /* RW-4R */
#define NV_INGRESS_RIDTABDATA0_GSIZE 3:0 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_GSIZE_16X 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_1X 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_2X 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_3X 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_4X 0x00000004 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_5X 0x00000005 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_6X 0x00000006 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_7X 0x00000007 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_8X 0x00000008 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_9X 0x00000009 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_10X 0x0000000a /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_11X 0x0000000b /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_12X 0x0000000c /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_13X 0x0000000d /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_14X 0x0000000e /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_15X 0x0000000f /* RW--V */
#define NV_INGRESS_RIDTABDATA0_PORT0 10:5 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_PORT0_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE0 13:12 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_VC_MODE0_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE0_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE0_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE0_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_PORT1 19:14 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_PORT1_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE1 22:21 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_VC_MODE1_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE1_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE1_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE1_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_PORT2 28:23 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_PORT2_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE2 31:30 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_VC_MODE2_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE2_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE2_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE2_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA1 0x000010b4 /* RW-4R */
#define NV_INGRESS_RIDTABDATA1_PORT3 5:0 /* RWEVF */
#define NV_INGRESS_RIDTABDATA1_PORT3_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE3 8:7 /* RWEVF */
#define NV_INGRESS_RIDTABDATA1_VC_MODE3_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE3_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE3_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE3_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_PORT4 14:9 /* RWEVF */
#define NV_INGRESS_RIDTABDATA1_PORT4_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE4 17:16 /* RWEVF */
#define NV_INGRESS_RIDTABDATA1_VC_MODE4_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE4_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE4_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE4_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_PORT5 23:18 /* RWEVF */
#define NV_INGRESS_RIDTABDATA1_PORT5_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE5 26:25 /* RWEVF */
#define NV_INGRESS_RIDTABDATA1_VC_MODE5_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE5_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE5_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE5_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA2 0x000010b8 /* RW-4R */
#define NV_INGRESS_RIDTABDATA2_PORT6 5:0 /* RWEVF */
#define NV_INGRESS_RIDTABDATA2_PORT6_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE6 8:7 /* RWEVF */
#define NV_INGRESS_RIDTABDATA2_VC_MODE6_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE6_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE6_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE6_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_PORT7 14:9 /* RWEVF */
#define NV_INGRESS_RIDTABDATA2_PORT7_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE7 17:16 /* RWEVF */
#define NV_INGRESS_RIDTABDATA2_VC_MODE7_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE7_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE7_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE7_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_PORT8 23:18 /* RWEVF */
#define NV_INGRESS_RIDTABDATA2_PORT8_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE8 26:25 /* RWEVF */
#define NV_INGRESS_RIDTABDATA2_VC_MODE8_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE8_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE8_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE8_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA3 0x000010bc /* RW-4R */
#define NV_INGRESS_RIDTABDATA3_PORT9 5:0 /* RWEVF */
#define NV_INGRESS_RIDTABDATA3_PORT9_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE9 8:7 /* RWEVF */
#define NV_INGRESS_RIDTABDATA3_VC_MODE9_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE9_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE9_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE9_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_PORT10 14:9 /* RWEVF */
#define NV_INGRESS_RIDTABDATA3_PORT10_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE10 17:16 /* RWEVF */
#define NV_INGRESS_RIDTABDATA3_VC_MODE10_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE10_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE10_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE10_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_PORT11 23:18 /* RWEVF */
#define NV_INGRESS_RIDTABDATA3_PORT11_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE11 26:25 /* RWEVF */
#define NV_INGRESS_RIDTABDATA3_VC_MODE11_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE11_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE11_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE11_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA4 0x000010c0 /* RW-4R */
#define NV_INGRESS_RIDTABDATA4_PORT12 5:0 /* RWEVF */
#define NV_INGRESS_RIDTABDATA4_PORT12_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE12 8:7 /* RWEVF */
#define NV_INGRESS_RIDTABDATA4_VC_MODE12_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE12_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE12_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE12_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_PORT13 14:9 /* RWEVF */
#define NV_INGRESS_RIDTABDATA4_PORT13_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE13 17:16 /* RWEVF */
#define NV_INGRESS_RIDTABDATA4_VC_MODE13_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE13_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE13_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE13_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_PORT14 23:18 /* RWEVF */
#define NV_INGRESS_RIDTABDATA4_PORT14_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE14 26:25 /* RWEVF */
#define NV_INGRESS_RIDTABDATA4_VC_MODE14_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE14_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE14_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE14_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA5 0x000010c4 /* RW-4R */
#define NV_INGRESS_RIDTABDATA5_PORT15 5:0 /* RWEVF */
#define NV_INGRESS_RIDTABDATA5_PORT15_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA5_VC_MODE15 8:7 /* RWEVF */
#define NV_INGRESS_RIDTABDATA5_VC_MODE15_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA5_VC_MODE15_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA5_VC_MODE15_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA5_VC_MODE15_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA5_RMOD 18:9 /* RWEVF */
#define NV_INGRESS_RIDTABDATA5_RMOD_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA5_ECC 30:22 /* RWEVF */
#define NV_INGRESS_RIDTABDATA5_ECC_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA5_ACLVALID 31:31 /* RWEVF */
#define NV_INGRESS_RIDTABDATA5_ACLVALID_INVALID 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA5_ACLVALID_VALID 0x00000001 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR 0x00001080 /* RW-4R */
#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS 13:0 /* RWEVF */
#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_REMAPTAB_DEPTH 0x000007ff /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_RID_TAB_DEPTH 0x000001ff /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_RLAN_TAB_DEPTH 0x000001ff /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL 18:16 /* RWEVF */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSREMAPPOLICYRAM 0x00000000 /* RWE-V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSRIDROUTERAM 0x00000001 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSRLANROUTERAM 0x00000002 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_RSVD3 0x00000003 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_RSVD4 0x00000004 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_RSVD5 0x00000005 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_RSVD6 0x00000006 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_RSVD7 0x00000007 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_AUTO_INCR 31:31 /* RWEVF */
#define NV_INGRESS_REQRSPMAPADDR_AUTO_INCR_ENABLE 0x00000001 /* RWE-V */
#define NV_INGRESS_REQRSPMAPADDR_AUTO_INCR_DISABLE 0x00000000 /* RW--V */
#define NV_INGRESS_RLANTABDATA0 0x000010d0 /* RW-4R */
#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_0 3:0 /* RWEVF */
#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_0_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA0_GRP_SEL_0 8:5 /* RWEVF */
#define NV_INGRESS_RLANTABDATA0_GRP_SEL_0_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_1 13:10 /* RWEVF */
#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_1_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA0_GRP_SEL_1 18:15 /* RWEVF */
#define NV_INGRESS_RLANTABDATA0_GRP_SEL_1_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_2 23:20 /* RWEVF */
#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_2_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA0_GRP_SEL_2 28:25 /* RWEVF */
#define NV_INGRESS_RLANTABDATA0_GRP_SEL_2_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA1 0x000010d4 /* RW-4R */
#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_3 3:0 /* RWEVF */
#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_3_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA1_GRP_SEL_3 8:5 /* RWEVF */
#define NV_INGRESS_RLANTABDATA1_GRP_SEL_3_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_4 13:10 /* RWEVF */
#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_4_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA1_GRP_SEL_4 18:15 /* RWEVF */
#define NV_INGRESS_RLANTABDATA1_GRP_SEL_4_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_5 23:20 /* RWEVF */
#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_5_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA1_GRP_SEL_5 28:25 /* RWEVF */
#define NV_INGRESS_RLANTABDATA1_GRP_SEL_5_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA2 0x000010d8 /* RW-4R */
#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_6 3:0 /* RWEVF */
#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_6_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA2_GRP_SEL_6 8:5 /* RWEVF */
#define NV_INGRESS_RLANTABDATA2_GRP_SEL_6_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_7 13:10 /* RWEVF */
#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_7_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA2_GRP_SEL_7 18:15 /* RWEVF */
#define NV_INGRESS_RLANTABDATA2_GRP_SEL_7_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_8 23:20 /* RWEVF */
#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_8_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA2_GRP_SEL_8 28:25 /* RWEVF */
#define NV_INGRESS_RLANTABDATA2_GRP_SEL_8_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA3 0x000010dc /* RW-4R */
#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_9 3:0 /* RWEVF */
#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_9_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA3_GRP_SEL_9 8:5 /* RWEVF */
#define NV_INGRESS_RLANTABDATA3_GRP_SEL_9_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_10 13:10 /* RWEVF */
#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_10_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA3_GRP_SEL_10 18:15 /* RWEVF */
#define NV_INGRESS_RLANTABDATA3_GRP_SEL_10_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_11 23:20 /* RWEVF */
#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_11_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA3_GRP_SEL_11 28:25 /* RWEVF */
#define NV_INGRESS_RLANTABDATA3_GRP_SEL_11_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA4 0x000010e0 /* RW-4R */
#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_12 3:0 /* RWEVF */
#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_12_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA4_GRP_SEL_12 8:5 /* RWEVF */
#define NV_INGRESS_RLANTABDATA4_GRP_SEL_12_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_13 13:10 /* RWEVF */
#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_13_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA4_GRP_SEL_13 18:15 /* RWEVF */
#define NV_INGRESS_RLANTABDATA4_GRP_SEL_13_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_14 23:20 /* RWEVF */
#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_14_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA4_GRP_SEL_14 28:25 /* RWEVF */
#define NV_INGRESS_RLANTABDATA4_GRP_SEL_14_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA5 0x000010e4 /* RW-4R */
#define NV_INGRESS_RLANTABDATA5_GRP_SIZE_15 3:0 /* RWEVF */
#define NV_INGRESS_RLANTABDATA5_GRP_SIZE_15_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA5_GRP_SEL_15 8:5 /* RWEVF */
#define NV_INGRESS_RLANTABDATA5_GRP_SEL_15_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA5_RSVD 21:20 /* RWEVF */
#define NV_INGRESS_RLANTABDATA5_RSVD_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA5_ECC 30:22 /* RWEVF */
#define NV_INGRESS_RLANTABDATA5_ECC_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA5_ACLVALID 31:31 /* RWEVF */
#define NV_INGRESS_RLANTABDATA5_ACLVALID_INVALID 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA5_ACLVALID_VALID 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER 0x000014b0 /* RW-4R */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_LIMIT 0x000014b4 /* RW-4R */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0 0x00001408 /* RW-4R */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_CMDDECODEERR 0:0 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_CMDDECODEERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ACLFAIL 3:3 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ACLFAIL__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET 6:6 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRBOUNDSERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTABCFGERR 8:8 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTABCFGERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTABCFGERR 9:9 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTABCFGERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRTYPEERR 17:17 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRTYPEERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0 0x0000140c /* RW-4R */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_CMDDECODEERR 0:0 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_CMDDECODEERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL 3:3 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET 6:6 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTABCFGERR 8:8 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTABCFGERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTABCFGERR 9:9 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTABCFGERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR 17:17 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL 0x00001470 /* RW-4R */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_HDR_ECC_ENABLE 0:0 /* RWEVF */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_HDR_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_HDR_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_HDR_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE 1:1 /* RWEVF */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_REMAPTAB_ECC_ENABLE 8:8 /* RWEVF */
#define NV_INGRESS_ERR_ECC_CTRL_REMAPTAB_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_REMAPTAB_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_ECC_CTRL_REMAPTAB_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_RIDTAB_ECC_ENABLE 9:9 /* RWEVF */
#define NV_INGRESS_ERR_ECC_CTRL_RIDTAB_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_RIDTAB_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_ECC_CTRL_RIDTAB_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_RLANTAB_ECC_ENABLE 10:10 /* RWEVF */
#define NV_INGRESS_ERR_ECC_CTRL_RLANTAB_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_RLANTAB_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_ECC_CTRL_RLANTAB_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_LIMIT 0x00001484 /* RW-4R */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_LIMIT 0x00001494 /* RW-4R */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_LIMIT 0x000014a4 /* RW-4R */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#endif // __lr10_dev_ingress_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_minion_ip_h__
#define __lr10_dev_minion_ip_h__
/* This file is autogenerated. Do not edit */
// did not include the regs that weren't approved for Tegra
#define NV_CMINION_FALCON_CG2 0x00000134 /* RWI4R */
#define NV_CMINION_FALCON_CG2_SLCG 17:1 /* */
#define NV_CMINION_FALCON_CG2_SLCG_ENABLED 0 /* */
#define NV_CMINION_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */
#define NV_CMINION_FALCON_CG2_SLCG__PROD 0x10004 /* */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_IRQMASK 0x00000018 /* R--4R */
#define NV_CMINION_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_HALT 4:4 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_DMA 16:16 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSCLR 0x00000004 /* -W-4R */
#define NV_CMINION_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSTAT 0x00000008 /* R--4R */
#define NV_CMINION_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMSET 0x00000010 /* -W-4R */
#define NV_CMINION_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_MTHD_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_HALT 4:4 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_HALT_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_DMA 16:16 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_DMA_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQDEST 0x0000001c /* RW-4R */
#define NV_CMINION_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT 31:24 /* */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMACTL 0x0000010c /* RW-4R */
#define NV_CMINION_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
#define NV_CMINION_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
#define NV_CMINION_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
#define NV_CMINION_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
#define NV_CMINION_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
#define NV_CMINION_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_DMACTL_DMAQ_NUM 6:3 /* R--VF */
#define NV_CMINION_FALCON_DMACTL_SECURE_STAT 7:7 /* R--VF */
#define NV_CMINION_FALCON_IMEMC(i) (0x00000180+(i)*16) /* RW-4A */
#define NV_CMINION_FALCON_IMEMC__SIZE_1 4 /* */
#define NV_CMINION_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
#define NV_CMINION_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IMEMC_BLK 23:8 /* RWIVF */
#define NV_CMINION_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
#define NV_CMINION_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IMEMC_AINCR 25:25 /* RWIVF */
#define NV_CMINION_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
#define NV_CMINION_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */
#define NV_CMINION_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */
#define NV_CMINION_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */
#define NV_CMINION_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IMEMT(i) (0x00000188+(i)*16) /* RW-4A */
#define NV_CMINION_FALCON_IMEMT__SIZE_1 4 /* */
#define NV_CMINION_FALCON_IMEMT_TAG 15:0 /* RW-VF */
#define NV_CMINION_FALCON_IMEMD(i) (0x00000184+(i)*16) /* RW-4A */
#define NV_CMINION_FALCON_IMEMD__SIZE_1 4 /* */
#define NV_CMINION_FALCON_IMEMD_DATA 31:0 /* RW-VF */
#define NV_CMINION_FALCON_DMEMC(i) (0x000001c0+(i)*8) /* RW-4A */
#define NV_CMINION_FALCON_DMEMC__SIZE_1 8 /* */
#define NV_CMINION_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_OFFS 7:2 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_BLK 23:8 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_AINCR 25:25 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_VA 28:28 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_MISS 29:29 /* R-IVF */
#define NV_CMINION_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */
#define NV_CMINION_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */
#define NV_CMINION_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */
#define NV_CMINION_FALCON_DMEMD__SIZE_1 8 /* */
#define NV_CMINION_FALCON_DMEMD_DATA 31:0 /* RW-VF */
#define NV_CMINION_FALCON_OS 0x00000080 /* RW-4R */
#define NV_CMINION_FALCON_OS_VERSION 31:0 /* RWIVF */
#define NV_CMINION_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_MAILBOX1 0x00000044 /* RW-4R */
#define NV_CMINION_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
#define NV_CMINION_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_SCTL 0x00000240 /* RW-4R */
#define NV_CMINION_FALCON_SCTL_LSMODE 0:0 /* RWIVF */
#define NV_CMINION_FALCON_SCTL_LSMODE_FALSE 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_SCTL_LSMODE_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_SCTL_HSMODE 1:1 /* R--VF */
#define NV_CMINION_FALCON_SCTL_HSMODE_FALSE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_SCTL_HSMODE_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */
#define NV_CMINION_FALCON_SCTL_LSMODE_LEVEL_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_SCTL_UCODE_LEVEL 5:4 /* */
#define NV_CMINION_FALCON_SCTL_UCODE_LEVEL_INIT 0 /* */
#define NV_CMINION_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */
#define NV_CMINION_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */
#define NV_CMINION_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */
#define NV_CMINION_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */
#define NV_CMINION_FALCON_SCTL_AUTH_EN_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_SCTL_AUTH_EN_FALSE 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_SCTL1 0x00000250 /* RW-4R */
#define NV_CMINION_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */
#define NV_CMINION_FALCON_SCTL1_CSBLVL_MASK_INIT 0x00000003 /* RWI-V */
#define NV_CMINION_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */
#define NV_CMINION_FALCON_SCTL1_EXTLVL_MASK_INIT 0x00000003 /* RWI-V */
#define NV_CMINION_FALCON_BOOTVEC 0x00000104 /* RW-4R */
#define NV_CMINION_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */
#define NV_CMINION_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_CPUCTL 0x00000100 /* RW-4R */
#define NV_CMINION_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */
#define NV_CMINION_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
#define NV_CMINION_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */
#define NV_CMINION_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */
#define NV_CMINION_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
#define NV_CMINION_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */
#define NV_CMINION_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
#define NV_CMINION_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_SCP_CTL_STAT 0x00000608 /* R--4R */
#define NV_CMINION_SCP_CTL_STAT_DEBUG_MODE 20:20 /* R--VF */
#define NV_CMINION_SCP_CTL_STAT_DEBUG_MODE_DISABLED 0x00000000 /* R---V */
#define NV_CMINION_SCP_CTL_STAT_AES_SCC_DIS 2:2 /* R--VF */
#define NV_CMINION_SCP_CTL_STAT_AES_SCC_DIS_TRUE 0x00000001 /* R---V */
#define NV_CMINION_SCP_CTL_STAT_AES_SCC_DIS_FALSE 0x00000000 /* R---V */
#define NV_CMINION_SCP_CTL_STAT_HSMODE 1:1 /* R--VF */
#define NV_CMINION_SCP_CTL_STAT_HSMODE_TRUE 0x00000001 /* R---V */
#define NV_CMINION_SCP_CTL_STAT_HSMODE_FALSE 0x00000000 /* R---V */
#define NV_CMINION_SCP_CTL_STAT_SBOOT 0:0 /* R--VF */
#define NV_CMINION_SCP_CTL_STAT_SBOOT_TRUE 0x00000001 /* R---V */
#define NV_CMINION_SCP_CTL_STAT_SBOOT_FALSE 0x00000000 /* R---V */
#define NV_MINION_NVLINK_DL_STAT(i) (0x00000980+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_DL_STAT__SIZE_1 4 /* */
#define NV_MINION_NVLINK_DL_STAT_ARGS 15:0 /* RWEVF */
#define NV_MINION_NVLINK_DL_STAT_ARGS_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_STAT_STATUSIDX 23:16 /* RWEVF */
#define NV_MINION_NVLINK_DL_STAT_STATUSIDX_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_STAT_READY 31:31 /* RWEVF */
#define NV_MINION_NVLINK_DL_STAT_READY_TRUE 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_STAT_READY_FALSE 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_STATDATA(i) (0x000009c0+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_DL_STATDATA__SIZE_1 4 /* */
#define NV_MINION_NVLINK_DL_STATDATA_DATA 31:0 /* RWEVF */
#define NV_MINION_NVLINK_DL_STATDATA_DATA_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_LINK_INTR(i) (0x00000a00+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_LINK_INTR__SIZE_1 4 /* */
#define NV_MINION_NVLINK_LINK_INTR_CODE 7:0 /* RWEVF */
#define NV_MINION_NVLINK_LINK_INTR_CODE_NA 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_SWREQ 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_DLREQ 0x00000002 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_PMDISABLED 0x00000003 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_DLCMDFAULT 0x00000004 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_TLREQ 0x00000005 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_NOINIT 0x00000010 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_NOTIFY 0x00000017 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_LOCAL_CONFIG_ERR 0x00000018 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_NEGOTIATION_CONFIG_ERR 0x00000019 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_BADINIT 0x00000020 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_PMFAIL 0x00000021 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_SUBCODE 15:8 /* RWEVF */
#define NV_MINION_NVLINK_LINK_INTR_SUBCODE_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_LINK_INTR_STATE 31:31 /* RWEVF */
#define NV_MINION_NVLINK_LINK_INTR_STATE_INIT 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR 0x00000810 /* RW-4R */
#define NV_MINION_MINION_INTR_FATAL 0:0 /* RWEVF */
#define NV_MINION_MINION_INTR_FATAL_INIT 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONFATAL 1:1 /* RWEVF */
#define NV_MINION_MINION_INTR_NONFATAL_INIT 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_FALCON_STALL 2:2 /* R-EVF */
#define NV_MINION_MINION_INTR_FALCON_STALL_INIT 0x00000000 /* R-E-V */
#define NV_MINION_MINION_INTR_FALCON_NOSTALL 3:3 /* R-EVF */
#define NV_MINION_MINION_INTR_FALCON_NOSTALL_INIT 0x00000000 /* R-E-V */
#define NV_MINION_MINION_INTR_LINK 31:16 /* R-EVF */
#define NV_MINION_MINION_INTR_LINK_INIT 0x00000000 /* R-E-V */
#define NV_MINION_MINION_INTR_STALL_EN 0x00000818 /* RW-4R */
#define NV_MINION_MINION_INTR_STALL_EN_FATAL 0:0 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_FATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_FATAL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_STALL_EN_NONFATAL 1:1 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_NONFATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_NONFATAL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_STALL 2:2 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_STALL_DISABLE 0x00000000 /* RW--V */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_STALL_ENABLE 0x00000001 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_NOSTALL 3:3 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_NOSTALL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_NOSTALL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_STALL_EN_LINK 31:16 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_LINK_DISABLE_ALL 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_LINK_ENABLE_ALL 0x0000ffff /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN 0x0000081c /* RW-4R */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FATAL 0:0 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FATAL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_NONFATAL 1:1 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_NONFATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_NONFATAL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_STALL 2:2 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_STALL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_STALL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_NOSTALL 3:3 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_NOSTALL_DISABLE 0x00000000 /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_NOSTALL_ENABLE 0x00000001 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_LINK 31:16 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_LINK_DISABLE_ALL 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_LINK_ENABLE_ALL 0x0000ffff /* RW--V */
#define NV_MINION_MINION_STATUS 0x00000830 /* RW-4R */
#define NV_MINION_MINION_STATUS_STATUS 7:0 /* RWEVF */
#define NV_MINION_MINION_STATUS_STATUS_INIT 0x00000000 /* RWE-V */
#define NV_MINION_MINION_STATUS_STATUS_BOOT 0x00000001 /* RW--V */
#define NV_MINION_MINION_STATUS_INTR_CODE 31:8 /* RWEVF */
#define NV_MINION_MINION_STATUS_INTR_CODE_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD(i) (0x00000900+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_DL_CMD__SIZE_1 4 /* */
#define NV_MINION_NVLINK_DL_CMD_COMMAND 7:0 /* RWEVF */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_NOP 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHY 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SWINTR 0x00000002 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITLANEENABLE 0x00000003 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITDLPL 0x00000004 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITRXTERM 0x00000005 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITTL 0x00000006 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPLL 0x00000007 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_LANEDISABLE 0x00000008 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_LANESHUTDOWN 0x0000000c /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE1 0x0000000d /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITNEGOTIATE 0x0000000e /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITOPTIMIZE 0x0000000f /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_ENABLEPM 0x00000010 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DISABLEPM 0x00000011 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_TXCLKSWITCH_PLL 0x00000014 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_TXCLKSWITCH_ALT 0x00000015 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_CLEARRESTORESTATE 0x00000017 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SAVESTATE 0x00000018 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_READ_PHY_TRAINING_PARAMS 0x00000020 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_PHY_TRAINING_PARAMS 0x00000021 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_CONFIGEOM 0x00000040 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEA 0x00000041 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEDR 0x00000042 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEDW 0x00000043 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_XAVIER_PLLOVERRIDE_ON 0x00000050 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_XAVIER_PLLOVERRIDE_OFF 0x00000051 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_XAVIER_CALIBRATEPLL 0x00000052 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_TURING_RXDET 0x00000058 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLERRCNT 0x00000070 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLLPCNT 0x00000071 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLTHROUGHPUTCNT 0x00000072 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_PROTECTIONS_OFF 0x000000f0 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_ALWAYSFAULT 0x000000ff /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_FAULT 30:30 /* RWEVF */
#define NV_MINION_NVLINK_DL_CMD_FAULT_FAULT_CLEAR 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_FAULT_NOFAULT_NOCLEAR 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD_READY 31:31 /* RWEVF */
#define NV_MINION_NVLINK_DL_CMD_READY_TRUE 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_READY_FALSE 0x00000000 /* RWE-V */
#define NV_MINION_MISC_0 0x000008b0 /* RW-4R */
#define NV_MINION_MISC_0_SCRATCH_SWRW_0 31:0 /* RWEVF */
#define NV_MINION_MISC_0_SCRATCH_SWRW_0_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD_DATA(i) (0x00000920+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_DL_CMD_DATA__SIZE_1 4 /* */
#define NV_MINION_NVLINK_DL_CMD_DATA_DATA 31:0 /* RWEVF */
#define NV_MINION_NVLINK_DL_CMD_DATA_DATA_INIT 0x00000000 /* RWE-V */
#endif // __lr10_dev_minion_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_minion_ip_addendum_h__
#define __lr10_dev_minion_ip_addendum_h__
#define NV_NVLSTAT 0x00000103:0x00000000 /* RW--D */
#define NV_NVLSTAT_UC01 0x00000001 /* R--4R */
#define NV_NVLSTAT_UC01_PM_STATE 31:31 /* R---F */
#define NV_NVLSTAT_UC01_ACMODE_STATE 30:30 /* R---F */
#define NV_NVLSTAT_UC01_LANES_ENABLED 29:29 /* R---F */
#define NV_NVLSTAT_UC01_LANES_ENABLED_TRUE 0x1 /* R---V */
#define NV_NVLSTAT_UC01_LANES_ENABLED_FALSE 0x0 /* R---V */
#define NV_NVLSTAT_UC01_TRAINING_BUFFER_STATUS 23:20 /* R---F */
#define NV_NVLSTAT_UC01_SEARCH_ERROR 19:19 /* R---F */
#define NV_NVLSTAT_UC01_TRAINING_GOOD 18:18 /* R---F */
#define NV_NVLSTAT_UC01_TRAINING_GOOD_SUCCESS 0x1 /* R---V */
#define NV_NVLSTAT_UC01_TRAINING_GOOD_UNKNOWN 0x0 /* R---V */
#define NV_NVLSTAT_UC01_CONFIG_GOOD 16:16 /* R---F */
#define NV_NVLSTAT_UC01_CONFIG_GOOD_SUCCESS 0x1 /* R---V */
#define NV_NVLSTAT_UC01_CONFIG_GOOD_UNKNOWN 0x0 /* R---V */
#define NV_NVLSTAT_UC01_LINK_STATE 15:0 /* R---F */
#define NV_NVLSTAT_LNK0 0x00000010 /* R--4R */
#define NV_NVLSTAT_LNK0_INTR_TX_FAULT_RAM 4:4 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_TX_FAULT_INTERFACE 5:5 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_TX_FAULT_SUBLINK_CHANGE 8:8 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_SUBLINK_CHANGE 16:16 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_DL_PROTOCOL 20:20 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_SHORT_ERROR_RATE 21:21 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_LONG_ERROR_RATE 22:22 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_LTSSM_PROTOCOL 29:29 /* R---F */
#define NV_NVLSTAT_LNK1 0x00000011 /* R--4R */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_VALUE_SRCOVF 0x000003ff /* R---V */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_LNK2 0x00000012 /* R--4R */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS 9:8 /* R---F */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_UNINITIALIZED 0x0 /* R---V */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_SEARCH 0x1 /* R---V */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_FOUND 0x2 /* R---V */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_TIMEOUT 0x3 /* R---V */
#define NV_NVLSTAT_LNK2_RXDET_LANE_STATUS 7:0 /* R---F */
#define NV_NVLSTAT_LNK2_RXDET_LANE_STATUS_FOUND 0x0f /* R---V */
#define NV_NVLSTAT_LNK3 0x00000013 /* R--4R */
#define NV_NVLSTAT_LNK3_LINERATE 23:0 /* R---F */
#define NV_NVLSTAT_LNK4 0x00000014 /* R--4R */
#define NV_NVLSTAT_LNK4_LINKCLOCK 15:0 /* R---F */
#define NV_NVLSTAT_LNK5 0x00000015 /* R--4R */
#define NV_NVLSTAT_LNK5_DATARATE 31:0 /* R---F */
#define NV_NVLSTAT_TX00 0x00000020 /* R--4R */
#define NV_NVLSTAT_TX00_COUNT_TX_STATE_EIGHTH_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX00_COUNT_TX_STATE_EIGHTH_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX00_COUNT_TX_STATE_EIGHTH_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX00_COUNT_TX_STATE_EIGHTH_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX00_COUNT_TX_STATE_EIGHTH_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX01 0x00000021 /* R--4R */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX02 0x00000022 /* R--4R */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX03 0x00000023 /* R--4R */
#define NV_NVLSTAT_TX03_DELAY_TX_STATE_LP_ENTER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX03_DELAY_TX_STATE_LP_ENTER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX03_DELAY_TX_STATE_LP_ENTER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX03_DELAY_TX_STATE_LP_ENTER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX03_DELAY_TX_STATE_LP_ENTER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX04 0x00000024 /* R--4R */
#define NV_NVLSTAT_TX04_DELAY_TX_STATE_LP_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX04_DELAY_TX_STATE_LP_EXIT_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX04_DELAY_TX_STATE_LP_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX04_DELAY_TX_STATE_LP_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX04_DELAY_TX_STATE_LP_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX05 0x00000025 /* R--4R */
#define NV_NVLSTAT_TX05_NUM_TX_STATE_LP_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX05_NUM_TX_STATE_LP_EXIT_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX05_NUM_TX_STATE_LP_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX05_NUM_TX_STATE_LP_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX05_NUM_TX_STATE_LP_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX06 0x00000026 /* R--4R */
#define NV_NVLSTAT_TX06_NUM_TX_STATE_LP_ENTER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX06_NUM_TX_STATE_LP_ENTER_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX06_NUM_TX_STATE_LP_ENTER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX06_NUM_TX_STATE_LP_ENTER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX06_NUM_TX_STATE_LP_ENTER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX07 0x00000027 /* R--4R */
#define NV_NVLSTAT_TX07_DELAY_TX_FB_EXIT_OTHER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX07_DELAY_TX_FB_EXIT_OTHER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX07_DELAY_TX_FB_EXIT_OTHER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX07_DELAY_TX_FB_EXIT_OTHER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX07_DELAY_TX_FB_EXIT_OTHER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX08 0x00000028 /* R--4R */
#define NV_NVLSTAT_TX08_DELAY_TX_FB_ENTER_OTHER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX08_DELAY_TX_FB_ENTER_OTHER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX08_DELAY_TX_FB_ENTER_OTHER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX08_DELAY_TX_FB_ENTER_OTHER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX08_DELAY_TX_FB_ENTER_OTHER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX09 0x00000029 /* R--4R */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX12 0x0000002c /* R--4R */
#define NV_NVLSTAT_TX12_TX_LPOCC_HIST 31:0 /* R---F */
#define NV_NVLSTAT_TX13 0x0000002d /* R--4R */
#define NV_NVLSTAT_TX13_TX_LPOCC_HIST 31:0 /* R---F */
#define NV_NVLSTAT_TX14 0x0000002e /* R--4R */
#define NV_NVLSTAT_TX14_TX_LPEXIT_HIST 31:0 /* R---F */
#define NV_NVLSTAT_TX15 0x0000002f /* R--4R */
#define NV_NVLSTAT_TX15_TX_LPEXIT_HIST 31:0 /* R---F */
#define NV_NVLSTAT_RX00 0x00000040 /* R--4R */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX01 0x00000041 /* R--4R */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX03 0x00000043 /* R--4R */
#define NV_NVLSTAT_RX03_DELAY_RX_LP_ENTER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX03_DELAY_RX_LP_ENTER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_RX03_DELAY_RX_LP_ENTER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX03_DELAY_RX_LP_ENTER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX03_DELAY_RX_LP_ENTER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX04 0x00000044 /* R--4R */
#define NV_NVLSTAT_RX04_DELAY_RX_LP_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX04_DELAY_RX_LP_EXIT_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_RX04_DELAY_RX_LP_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX04_DELAY_RX_LP_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX04_DELAY_RX_LP_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX05 0x00000045 /* R--4R */
#define NV_NVLSTAT_RX05_DELAY_RX_FB_ENTER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX05_DELAY_RX_FB_ENTER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_RX05_DELAY_RX_FB_ENTER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX05_DELAY_RX_FB_ENTER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX05_DELAY_RX_FB_ENTER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX06 0x00000046 /* R--4R */
#define NV_NVLSTAT_RX06_DELAY_RX_FB_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX06_DELAY_RX_FB_EXIT_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_RX06_DELAY_RX_FB_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX06_DELAY_RX_FB_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX06_DELAY_RX_FB_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX08 0x00000048 /* R--4R */
#define NV_NVLSTAT_RX08_ERRORLOG_ERR_CNT_MULTI 7:0 /* R---F */
#define NV_NVLSTAT_RX09 0x00000049 /* R--4R */
#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_7 31:24 /* R---F */
#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_6 23:16 /* R---F */
#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_5 15:8 /* R---F */
#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_4 7:0 /* R---F */
#define NV_NVLSTAT_RX10 0x0000004a /* R--4R */
#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_3 31:24 /* R---F */
#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_2 23:16 /* R---F */
#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_1 15:8 /* R---F */
#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_0 7:0 /* R---F */
#define NV_NVLSTAT_RX12 0x0000004c /* R--4R */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX13 0x0000004d /* R--4R */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX14 0x0000004e /* R--4R */
#define NV_NVLSTAT_RX14_ECC_CORRECTED_ERR_L2_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX14_ECC_CORRECTED_ERR_L2_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX14_ECC_CORRECTED_ERR_L2_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX14_ECC_CORRECTED_ERR_L2_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX14_ECC_CORRECTED_ERR_L2_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX15 0x0000004f /* R--4R */
#define NV_NVLSTAT_RX15_ECC_CORRECTED_ERR_L3_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX15_ECC_CORRECTED_ERR_L3_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX15_ECC_CORRECTED_ERR_L3_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX15_ECC_CORRECTED_ERR_L3_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX15_ECC_CORRECTED_ERR_L3_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TR00 0x00000090 /* R--4R */
#define NV_NVLSTAT_TR00_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR01 0x00000091 /* R--4R */
#define NV_NVLSTAT_TR01_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR02 0x00000092 /* R--4R */
#define NV_NVLSTAT_TR02_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR03 0x00000093 /* R--4R */
#define NV_NVLSTAT_TR03_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR04 0x00000094 /* R--4R */
#define NV_NVLSTAT_TR04_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR05 0x00000095 /* R--4R */
#define NV_NVLSTAT_TR05_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR06 0x00000096 /* R--4R */
#define NV_NVLSTAT_TR06_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR07 0x00000097 /* R--4R */
#define NV_NVLSTAT_TR07_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR08 0x00000098 /* R--4R */
#define NV_NVLSTAT_TR08_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR09 0x00000099 /* R--4R */
#define NV_NVLSTAT_TR09_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR10 0x0000009a /* R--4R */
#define NV_NVLSTAT_TR10_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR11 0x0000009b /* R--4R */
#define NV_NVLSTAT_TR11_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR12 0x0000009c /* R--4R */
#define NV_NVLSTAT_TR12_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR13 0x0000009d /* R--4R */
#define NV_NVLSTAT_TR13_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR14 0x0000009e /* R--4R */
#define NV_NVLSTAT_TR14_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR15 0x0000009f /* R--4R */
#define NV_NVLSTAT_TR15_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR16 0x000000a0 /* R--4R */
#define NV_NVLSTAT_TR16_L0FOM 15:0 /* R---F */
#define NV_NVLSTAT_TR16_L1FOM 31:16 /* R---F */
#define NV_NVLSTAT_TR17 0x000000a1 /* R--4R */
#define NV_NVLSTAT_TR17_L2FOM 15:0 /* R---F */
#define NV_NVLSTAT_TR17_L3FOM 31:16 /* R---F */
#define NV_NVLSTAT_DB00 0x00000080 /* R--4R */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_VALUE_SRCOVF 0x7fffffff /* R---V */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_OVER 31:31 /* R---F */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_DB01 0x00000081 /* R--4R */
#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L3 31:24 /* R---F */
#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L2 23:16 /* R---F */
#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L1 15:8 /* R---F */
#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L0 7:0 /* R---F */
#define NV_NVLSTAT_DB02 0x00000082 /* R--4R */
#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L7 31:24 /* R---F */
#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L6 23:16 /* R---F */
#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L5 15:8 /* R---F */
#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L4 7:0 /* R---F */
#define NV_NVLSTAT_DB03 0x00000083 /* R--4R */
#define NV_NVLSTAT_DB03_RXSLSM_ERR_CNTL_CLK_SWITCH_ERR 31:31 /* R---F */
#define NV_NVLSTAT_DB03_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR 2:2 /* R---F */
#define NV_NVLSTAT_DB03_RXSLSM_ERR_CNTL_CONST_DET_ERR 1:1 /* R---F */
#define NV_NVLSTAT_DB04 0x00000084 /* R--4R */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_E2S_STROBE_NO_LD_ERR 23:23 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_H2S_STROBE_NO_LD_ERR 22:22 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_02S_STROBE_NO_LD_ERR 21:21 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_E2S_SD_NO_LD_ERR 20:20 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR 19:19 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR 18:18 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR 15:15 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_RC_TXPWR_ERR 14:14 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_RC_RXPWR_ERR 13:13 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_E2SAFE_LD_ERR 12:12 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SAFE_NO_LD_ERR 11:11 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_FENCE_ERR 10:10 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR 9:9 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR 8:8 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR 7:7 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR 6:6 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SYM_LOCK_ERR 5:5 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR 4:4 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SAFE2NO_LINK_DET_ERR 3:3 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR 2:2 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_CONST_DET_ERR 1:1 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_FIFO_DRAIN_ERR 0:0 /* R---F */
#define NV_NVLSTAT_DB05 0x00000085 /* R--4R */
#define NV_NVLSTAT_DB05_TIMEOUT_LOG_SYM_LOCK_LANE 31:24 /* R---F */
#define NV_NVLSTAT_DB05_TIMEOUT_LOG_SCRAM_LOCK_LANE 23:16 /* R---F */
#define NV_NVLSTAT_DB05_TIMEOUT_LOG_CONST_DET_LANE 15:8 /* R---F */
#define NV_NVLSTAT_DB05_TIMEOUT_LOG_FIFO_DRAIN_LANE 7:0 /* R---F */
#define NV_NVLSTAT_DB06 0x00000086 /* R--4R */
#define NV_NVLSTAT_DB06_TIMEOUT_LOG_SYM_ALIGN_END_LANE 31:24 /* R---F */
#define NV_NVLSTAT_DB06_TIMEOUT_LOG_FIFO_SKEW_LANE 23:16 /* R---F */
#define NV_NVLSTAT_DB07 0x00000087 /* R--4R */
#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_3 29:24 /* R---F */
#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_2 21:16 /* R---F */
#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_1 13:8 /* R---F */
#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_0 5:0 /* R---F */
#define NV_NVLSTAT_DB08 0x00000088 /* R--4R */
#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_7 29:24 /* R---F */
#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_6 21:16 /* R---F */
#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_5 13:8 /* R---F */
#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_4 5:0 /* R---F */
#define NV_NVLSTAT_DB09 0x00000089 /* R--4R */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_DB10 0x0000008a /* R--4R */
#define NV_NVLSTAT_DB10_DATA 31:0 /* R---F */
#define NV_NVLSTAT_MN00 0x000000ff /* R--4R */
#define NV_NVLSTAT_MN00_LINK_INTR_SUBCODE 15:8 /* R---F */
#define NV_NVLSTAT_MN00_LINK_INTR_CODE 7:0 /* R---F */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_FORCE_EQ_OVERRIDE_1 0x00000060 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_RELEASE_EQ_OVERRIDE_1 0x00000061 /* RWE-V */
#endif // __lr10_dev_minion_ip_addendum_h__

99
src/common/inc/swref/published/nvswitch/lr10/dev_npg_ip.h Normal file
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@@ -0,0 +1,99 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_npg_ip_h__
#define __lr10_dev_npg_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NPG_NPG_INTERRUPT_STATUS 0x00000400 /* R--4R */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_FNC_OR 0:0 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_FNC_OR_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS 3:1 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_FATAL 0x00000001 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_NONFATAL 0x00000002 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_FNC_OR 4:4 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_FNC_OR_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS 7:5 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_FATAL 0x00000001 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_NONFATAL 0x00000002 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_FNC_OR 8:8 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_FNC_OR_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS 11:9 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_FATAL 0x00000001 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_NONFATAL 0x00000002 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_FNC_OR 12:12 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_FNC_OR_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS 15:13 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_FATAL 0x00000001 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_NONFATAL 0x00000002 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_WARMRESET 0x00000140 /* RW-4R */
#define NV_NPG_WARMRESET_NPORTWARMRESET 11:8 /* RWEVF */
#define NV_NPG_WARMRESET_NPORTWARMRESET_INIT 0x0000000f /* RWE-V */
#define NV_NPG_WARMRESET_NPORTWARMRESET_ASSERT 0x00000000 /* RW--V */
#define NV_NPG_WARMRESET_NPORTWARMRESET_DEASSERT 0x00000001 /* RW--V */
#define NV_NPG_DEBUG_CLEAR 0x00000144 /* RW-4R */
#define NV_NPG_DEBUG_CLEAR_CLEAR 3:0 /* RWIVF */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_NPORT_0 0x00000001 /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_NPORT_1 0x00000002 /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_NPORT_2 0x00000004 /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_NPORT_3 0x00000008 /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_ALL 0x0000000f /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_DEASSERT 0x00000000 /* RWI-V */
#define NV_NPG_DEBUG_CLEAR_CMN_CLEAR 31:31 /* RWIVF */
#define NV_NPG_DEBUG_CLEAR_CMN_CLEAR_ASSERT 0x00000001 /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CMN_CLEAR_DEASSERT 0x00000000 /* RWI-V */
#define NV_NPG_CTRL_PRI_MULTICAST 0x000000c0 /* RW-4R */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE 5:0 /* RWEVF */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_NO_NPORT_ENABLED 0x00000000 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT0_NPORT_ENABLED 0x00000001 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT1_NPORT_ENABLED 0x00000002 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT01_NPORT_ENABLED 0x00000003 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT2_NPORT_ENABLED 0x00000004 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT02_NPORT_ENABLED 0x00000005 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT3_NPORT_ENABLED 0x00000008 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_ALL_NPORT_ENABLED 0x0000000f /* RWE-V */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE 7:6 /* RWEVF */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE_LOW_SELECTED_BUS 0x00000000 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE_OR_ALL_BUSSES 0x00000001 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE_AND_ALL_BUSSES 0x00000002 /* RWE-V */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE_ZEROS 0x00000003 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED 13:8 /* R-EVF */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_NO_MCAST_ENABLED 0x00000000 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT0_MCAST_ENABLED 0x00000001 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT1_MCAST_ENABLED 0x00000002 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT01_MCAST_ENABLED 0x00000003 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT2_MCAST_ENABLED 0x00000004 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT02_MCAST_ENABLED 0x00000005 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT3_MCAST_ENABLED 0x00000008 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_ALL_MCAST_ENABLED 0x0000000f /* R-E-V */
#endif // __lr10_dev_npg_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_npgperf_ip_h__
#define __lr10_dev_npgperf_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NPGPERF_CTRL_CLOCK_GATING 0x000000c8 /* RW-4R */
#define NV_NPGPERF_CTRL_CLOCK_GATING_CG1_SLCG 3:0 /* RWEVF */
#define NV_NPGPERF_CTRL_CLOCK_GATING_CG1_SLCG_INIT 0x0000000f /* RWE-V */
#define NV_NPGPERF_CTRL_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING 0x000000cc /* RW-4R */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG 3:0 /* RWEVF */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG_INIT 0x0000000f /* RWE-V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE 7:4 /* RWEVF */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE_DISABLED 0x00000000 /* RWE-V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE_ENABLED 0x00000001 /* RW--V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE__PROD 0x00000000 /* RW--V */
#define NV_NPGPERF_CTRL_PRI_MULTICAST 0x000000c0 /* RW-4R */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_NPORT_ENABLE 5:0 /* RWEVF */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_NPORT_ENABLE_INIT 0x0000000f /* RWE-V */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_READ_MODE 7:6 /* RWEVF */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_READ_MODE_LOW_SELECTED_BUS 0x00000000 /* RW--V */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_READ_MODE_OR_ALL_BUSSES 0x00000001 /* RW--V */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_READ_MODE_AND_ALL_BUSSES 0x00000002 /* RWE-V */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_READ_MODE_ZEROS 0x00000003 /* RW--V */
#endif // __lr10_dev_npgperf_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nport_ip_h__
#define __lr10_dev_nport_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_0 0x0000010c /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_0_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_0_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_0_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0 0x00000110 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0 0x00000114 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_CTRL_SLCG 0x00000050 /* RW-4R */
#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS 0:0 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS__PROD 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE 1:1 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS 2:2 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK 3:3 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE 4:4 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX 5:5 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX__PROD 0x00000000 /* RW--V */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_0 0x00000120 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_1 0x00000124 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_1_PACKETCOUNT 15:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_1_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_0 0x00000128 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_1 0x0000012c /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_1_PACKETCOUNT 15:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_1_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_0 0x00000130 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_1 0x00000134 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_1_PACKETCOUNT 15:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_1_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_0 0x00000138 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_1 0x0000013c /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_1_PACKETCOUNT 15:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_1_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_0 0x00000118 /* R--4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_1 0x0000011c /* R--4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_1_PACKETCOUNT 15:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_1_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_CONTROL 0x00000100 /* RW-4R */
#define NV_NPORT_PORTSTAT_CONTROL_SWEEPMODE 1:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_CONTROL_SWEEPMODE_SINGLE 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_CONTROL_SWEEPMODE_CONTINUOUS 0x00000001 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_SWEEPMODE_SWONDEMAND 0x00000002 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT 7:4 /* RWEVF */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS13TO0 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS15TO2 0x00000001 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS17TO4 0x00000002 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS19TO6 0x00000003 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS21TO8 0x00000004 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS23TO10 0x00000005 /* RW--V */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_0 0x000002ac /* RW-4R */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_0_SRCFILTERBIT 31:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_0_SRCFILTERBIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_1 0x000002b0 /* RW-4R */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_1_SRCFILTERBIT 3:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_1_SRCFILTERBIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_WINDOW_LIMIT 0x00000108 /* RW-4R */
#define NV_NPORT_PORTSTAT_WINDOW_LIMIT_WINDOWLIMIT 31:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_WINDOW_LIMIT_WINDOWLIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL 0x00000104 /* RW-4R */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_STARTCOUNTER 0:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_STARTCOUNTER_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_STARTCOUNTER_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_SNAPONDEMAND 4:4 /* RWEVF */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_SNAPONDEMAND_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_SNAPONDEMAND_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_BUFFER_READY 0x00000044 /* RW-4R */
#define NV_NPORT_CTRL_BUFFER_READY_BUFFERRDY 0:0 /* RWEVF */
#define NV_NPORT_CTRL_BUFFER_READY_BUFFERRDY_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_BUFFER_READY_BUFFERRDY_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_REQLINKID 0x00000054 /* RW-4R */
#define NV_NPORT_REQLINKID_REQROUTINGID 8:0 /* RWEVF */
#define NV_NPORT_REQLINKID_REQROUTINGID_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_REQLINKID_REQROUTINGLAN 18:15 /* RWEVF */
#define NV_NPORT_REQLINKID_REQROUTINGLAN_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_REQLINKID_REQROUTINGIDREMAP 21:21 /* RWEVF */
#define NV_NPORT_REQLINKID_REQROUTINGIDREMAP_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_REQLINKID_REQROUTINGIDREMAP_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_REQLINKID_REQROUTINGLANREMAP 22:22 /* RWEVF */
#define NV_NPORT_REQLINKID_REQROUTINGLANREMAP_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_REQLINKID_REQROUTINGLANREMAP_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_REQLINKID_MASKS 0x00000058 /* RW-4R */
#define NV_NPORT_REQLINKID_MASKS_REQROUTINGID_MASK 8:0 /* RWEVF */
#define NV_NPORT_REQLINKID_MASKS_REQROUTINGID_MASK_INIT 0x000001ff /* RWE-V */
#define NV_NPORT_REQLINKID_MASKS_REQROUTINGLAN_MASK 18:15 /* RWEVF */
#define NV_NPORT_REQLINKID_MASKS_REQROUTINGLAN_MASK_INIT 0x0000000f /* RWE-V */
#define NV_NPORT_CTRL 0x00000040 /* RW-4R */
#define NV_NPORT_CTRL_TRUNKLINKENB 0:0 /* RWEVF */
#define NV_NPORT_CTRL_TRUNKLINKENB_TRUNKLINK 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_TRUNKLINKENB_ACCESSLINK 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_EGDRAINENB 1:1 /* RWEVF */
#define NV_NPORT_CTRL_EGDRAINENB_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_EGDRAINENB_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_RTDRAINENB 2:2 /* RWEVF */
#define NV_NPORT_CTRL_RTDRAINENB_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_RTDRAINENB_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_ENDPOINT_COUNT 5:4 /* RWEVF */
#define NV_NPORT_CTRL_ENDPOINT_COUNT_512 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_ENDPOINT_COUNT_1024 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_ENDPOINT_COUNT_2048 0x00000003 /* RW--V */
#define NV_NPORT_CTRL_INHIBITRAMLOAD 8:8 /* RWEVF */
#define NV_NPORT_CTRL_INHIBITRAMLOAD_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_SPARE 13:9 /* RWEVF */
#define NV_NPORT_CTRL_SPARE_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_ENROUTEDBI 16:16 /* RWEVF */
#define NV_NPORT_CTRL_ENROUTEDBI_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_ENROUTEDBI_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_ENEGRESSDBI 17:17 /* RWEVF */
#define NV_NPORT_CTRL_ENEGRESSDBI_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_ENEGRESSDBI_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT 0x00000470 /* RW-4R */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_CORRECTABLEENABLE 0:0 /* RWEVF */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_CORRECTABLEENABLE_INIT 0x00000001 /* RWE-V */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_FATALENABLE 1:1 /* RWEVF */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_FATALENABLE_INIT 0x00000001 /* RWE-V */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_NONFATALENABLE 2:2 /* RWEVF */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_NONFATALENABLE_INIT 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_STOP 0x00000048 /* RW-4R */
#define NV_NPORT_CTRL_STOP_INGRESS_STOP 0:0 /* RWEVF */
#define NV_NPORT_CTRL_STOP_INGRESS_STOP_STOP 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_STOP_INGRESS_STOP_ALLOWTRAFFIC 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_STOP_EGRESS_STOP 8:8 /* RWEVF */
#define NV_NPORT_CTRL_STOP_EGRESS_STOP_STOP 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_STOP_EGRESS_STOP_ALLOWTRAFFIC 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC 23:16 /* RWEVF */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_ALLOWTRAFFIC 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC0 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC1 0x00000002 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC2 0x00000004 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC3 0x00000008 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC4 0x00000010 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC5 0x00000020 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC6 0x00000040 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC7 0x00000080 /* RW--V */
#define NV_NPORT_CONTAIN_AND_DRAIN 0x0000005c /* RW-4R */
#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR 18:18 /* RWIVF */
#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR_DISABLE 0x00000000 /* RWI-V */
#define NV_NPORT_INITIALIZATION 0x0000004c /* RW-4R */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0 0:0 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1 1:1 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2 2:2 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3 3:3 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4 4:4 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5 5:5 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6 6:6 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_LINKTABLEINIT 8:8 /* RWEVF */
#define NV_NPORT_INITIALIZATION_LINKTABLEINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_LINKTABLEINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_REMAPTABINIT 9:9 /* RWEVF */
#define NV_NPORT_INITIALIZATION_REMAPTABINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_REMAPTABINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_RIDTABINIT 10:10 /* RWEVF */
#define NV_NPORT_INITIALIZATION_RIDTABINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_RIDTABINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_RLANTABINIT 11:11 /* RWEVF */
#define NV_NPORT_INITIALIZATION_RLANTABINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_RLANTABINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_SCRATCH_WARM 0x00000fc0 /* RW-4R */
#define NV_NPORT_SCRATCH_WARM_DATA 31:0 /* RWEVF */
#define NV_NPORT_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
#define NV_NPORT_PORTSTAT_COUNT_LOW_1_0 0x00000154 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_1_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_1_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_0 0x0000015c /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_0 0x00000164 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_0 0x0000016c /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_0 0x0000014c /* R--4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1 0x00000140 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1 0x00000144 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1 0x00000148 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1 0x00000140 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1 0x00000144 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1 0x00000148 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_2 0x00000174 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_2_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_2_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_2_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2 0x00000178 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2 0x0000017c /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_3 0x000001a8 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_3_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_3_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_3_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3 0x000001ac /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3 0x000001b0 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_4 0x000001dc /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_4_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_4_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_4_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4 0x000001e0 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4 0x000001e4 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_5 0x00000210 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_5_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_5_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_5_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5 0x00000214 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5 0x00000218 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_6 0x00000244 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_6_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_6_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_6_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6 0x00000248 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6 0x0000024c /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_7 0x00000278 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_7_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_7_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_7_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7 0x0000027c /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7 0x00000280 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7_LIMIT__PROD 0x00000680 /* RW--V */
#endif // __lr10_dev_nport_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nport_ip_addendum_h__
#define __lr10_dev_nport_ip_addendum_h__
// VC mapping
// IAS section 8.2.4.5 Table 40. LimeRock VC Error Encoding
#define NV_NPORT_VC_MAPPING_CREQ0 0x0
#define NV_NPORT_VC_MAPPING_RSP0 0x5
#define NV_NPORT_VC_MAPPING_CREQ1 0x6
#define NV_NPORT_VC_MAPPING_RSP1 0x7
#define NV_NPORT_SCRATCH_WARM_PORT_RESET_REQUIRED 0:0
#endif // __lr10_dev_nport_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nv_xp_h__
#define __lr10_dev_nv_xp_h__
/* This file is autogenerated. Do not edit */
#define NV_XP_LANE_ERROR_STATUS 0x0008D400 /* RW-4R */
#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_CODING_ERR 0:0 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_CODING_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_CODING_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_ORDER_ERR 1:1 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_ORDER_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_ORDER_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_OS_DATA_SEQ_ERR 2:2 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_OS_DATA_SEQ_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_OS_DATA_SEQ_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_TSX_DATA_SEQ_ERR 3:3 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_TSX_DATA_SEQ_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_TSX_DATA_SEQ_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_SKPOS_LFSR_ERR 4:4 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_SKPOS_LFSR_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_SKPOS_LFSR_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_RX_CLK_FIFO_OVERFLOW 5:5 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_RX_CLK_FIFO_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_RX_CLK_FIFO_OVERFLOW_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_ELASTIC_FIFO_OVERFLOW 6:6 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_ELASTIC_FIFO_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_ELASTIC_FIFO_OVERFLOW_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_RCVD_LINK_NUM_ERR 7:7 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_RCVD_LINK_NUM_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_RCVD_LINK_NUM_ERR_ACTIVE 0x00000000 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_RCVD_LANE_NUM_ERR 8:8 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_RCVD_LANE_NUM_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_RCVD_LANE_NUM_ERR_ACTIVE 0x00000000 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_SKP_RCV_SYM_ERR 9:9 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_SKP_RCV_SYM_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_SKP_RCV_SYM_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_SKPOS_PARITY_ERR 10:10 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_SKPOS_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_SKPOS_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_LOCAL_DATA_PARITY_ERR 11:11 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_LOCAL_DATA_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_LOCAL_DATA_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_FIRST_RETIMER_DATA_PARITY_ERR 12:12 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_FIRST_RETIMER_DATA_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_FIRST_RETIMER_DATA_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_SECOND_RETIMER_DATA_PARITY_ERR 13:13 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_SECOND_RETIMER_DATA_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_SECOND_RETIMER_DATA_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_CRC_ERR 14:14 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_CRC_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_CRC_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_PARITY_ERR 15:15 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERRORS_COUNT_0 0x0008D40C /* R--4R */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_0_VALUE 7:0 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_0_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_1_VALUE 15:8 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_1_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_2_VALUE 23:16 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_2_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_3_VALUE 31:24 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_3_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_1 0x0008D410 /* R--4R */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_4_VALUE 7:0 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_4_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_5_VALUE 15:8 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_5_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_6_VALUE 23:16 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_6_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_7_VALUE 31:24 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_7_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_2 0x0008D414 /* R--4R */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_8_VALUE 7:0 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_8_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_9_VALUE 15:8 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_9_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_10_VALUE 23:16 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_10_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_11_VALUE 31:24 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_11_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_3 0x0008D418 /* R--4R */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_12_VALUE 7:0 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_12_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_13_VALUE 15:8 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_13_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_14_VALUE 23:16 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_14_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_15_VALUE 31:24 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_15_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_1_ENTRY_COUNT(i) (0x0008D910+(i)*4) /* R--4A */
#define NV_XP_L1_1_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_1_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_1_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_2_ENTRY_COUNT(i) (0x0008D950+(i)*4) /* R--4A */
#define NV_XP_L1_2_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_2_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_2_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_2_ABORT_COUNT(i) (0x0008D990+(i)*4) /* R--4A */
#define NV_XP_L1_2_ABORT_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_2_ABORT_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_2_ABORT_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT(i) (0x0008D9D0+(i)*4) /* R--4A */
#define NV_XP_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_SHORT_DURATION_COUNT(i) (0x0008E0C4+(i)*4) /* R--4A */
#define NV_XP_L1_SHORT_DURATION_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_SHORT_DURATION_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_SHORT_DURATION_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_RECEIVER_ERRORS_COUNT(i) (0x0008D440+(i)*4) /* R--4A */
#define NV_XP_RECEIVER_ERRORS_COUNT__SIZE_1 1 /* */
#define NV_XP_RECEIVER_ERRORS_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_RECEIVER_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_REPLAY_ROLLOVER_COUNT(i) (0x0008D5C0+(i)*4) /* R--4A */
#define NV_XP_REPLAY_ROLLOVER_COUNT__SIZE_1 1 /* */
#define NV_XP_REPLAY_ROLLOVER_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_REPLAY_ROLLOVER_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_BAD_DLLP_COUNT(i) (0x0008D6C0+(i)*4) /* R--4A */
#define NV_XP_BAD_DLLP_COUNT__SIZE_1 1 /* */
#define NV_XP_BAD_DLLP_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_BAD_DLLP_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_BAD_TLP_COUNT(i) (0x0008D700+(i)*4) /* R--4A */
#define NV_XP_BAD_TLP_COUNT__SIZE_1 1 /* */
#define NV_XP_BAD_TLP_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_BAD_TLP_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP__8B10B_ERRORS_COUNT 0x0008D404 /* R--4R */
#define NV_XP__8B10B_ERRORS_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP__8B10B_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_SYNC_HEADER_ERRORS_COUNT 0x0008D408 /* R--4R */
#define NV_XP_SYNC_HEADER_ERRORS_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_SYNC_HEADER_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LCRC_ERRORS_COUNT(i) (0x0008D480+(i)*4) /* R--4A */
#define NV_XP_LCRC_ERRORS_COUNT__SIZE_1 1 /* */
#define NV_XP_LCRC_ERRORS_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_LCRC_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_FAILED_L0S_EXITS_COUNT(i) (0x0008D4C0+(i)*4) /* R--4A */
#define NV_XP_FAILED_L0S_EXITS_COUNT__SIZE_1 1 /* */
#define NV_XP_FAILED_L0S_EXITS_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_FAILED_L0S_EXITS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_NAKS_SENT_COUNT(i) (0x0008D500+(i)*4) /* R--4A */
#define NV_XP_NAKS_SENT_COUNT__SIZE_1 1 /* */
#define NV_XP_NAKS_SENT_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_NAKS_SENT_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_NAKS_RCVD_COUNT(i) (0x0008D540+(i)*4) /* R--4A */
#define NV_XP_NAKS_RCVD_COUNT__SIZE_1 1 /* */
#define NV_XP_NAKS_RCVD_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_NAKS_RCVD_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_NAKS_RCVD_COUNT_ILLOGICAL_VALUE 23:16 /* R-IVF */
#define NV_XP_NAKS_RCVD_COUNT_ILLOGICAL_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_TO_RECOVERY_COUNT(i) (0x0008D600+(i)*4) /* R--4A */
#define NV_XP_L1_TO_RECOVERY_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_TO_RECOVERY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_TO_RECOVERY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L0_TO_RECOVERY_COUNT(i) (0x0008D640+(i)*4) /* R--4A */
#define NV_XP_L0_TO_RECOVERY_COUNT__SIZE_1 1 /* */
#define NV_XP_L0_TO_RECOVERY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L0_TO_RECOVERY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_RECOVERY_COUNT(i) (0x0008D680+(i)*4) /* R--4A */
#define NV_XP_RECOVERY_COUNT__SIZE_1 1 /* */
#define NV_XP_RECOVERY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_RECOVERY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_CHIPSET_XMIT_L0S_ENTRY_COUNT(i) (0x0008D740+(i)*4) /* R--4A */
#define NV_XP_CHIPSET_XMIT_L0S_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_CHIPSET_XMIT_L0S_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_CHIPSET_XMIT_L0S_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_GPU_XMIT_L0S_ENTRY_COUNT(i) (0x0008D780+(i)*4) /* R--4A */
#define NV_XP_GPU_XMIT_L0S_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_GPU_XMIT_L0S_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_GPU_XMIT_L0S_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_ENTRY_COUNT(i) (0x0008D7C0+(i)*4) /* R--4A */
#define NV_XP_L1_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1P_ENTRY_COUNT(i) (0x0008D800+(i)*4) /* R--4A */
#define NV_XP_L1P_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_L1P_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1P_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_DEEP_L1_ENTRY_COUNT(i) (0x0008D840+(i)*4) /* R--4A */
#define NV_XP_DEEP_L1_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_DEEP_L1_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_DEEP_L1_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_ASLM_COUNT(i) (0x0008D880+(i)*4) /* R--4A */
#define NV_XP_ASLM_COUNT__SIZE_1 1 /* */
#define NV_XP_ASLM_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_ASLM_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_ERROR_COUNTER_RESET 0x0008D900 /* RWI4R */
#define NV_XP_ERROR_COUNTER_RESET_8B10B_ERRORS_COUNT 0:0 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_8B10B_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_8B10B_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_SYNC_HEADER_ERRORS_COUNT 1:1 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_SYNC_HEADER_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_SYNC_HEADER_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_LANE_ERRORS_COUNT 2:2 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_LANE_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_LANE_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_RECEIVER_ERRORS_COUNT 3:3 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_RECEIVER_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_RECEIVER_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_LCRC_ERRORS_COUNT 4:4 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_LCRC_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_LCRC_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_FAILED_L0S_EXITS_COUNT 5:5 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_FAILED_L0S_EXITS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_FAILED_L0S_EXITS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_NAKS_SENT_COUNT 6:6 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_NAKS_SENT_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_NAKS_SENT_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_NAKS_RCVD_COUNT 7:7 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_NAKS_RCVD_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_NAKS_RCVD_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_REPLAY_COUNT 8:8 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_REPLAY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_REPLAY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_REPLAY_ROLLOVER_COUNT 9:9 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_REPLAY_ROLLOVER_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_REPLAY_ROLLOVER_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_TO_RECOVERY_COUNT 10:10 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_TO_RECOVERY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_TO_RECOVERY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L0_TO_RECOVERY_COUNT 11:11 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L0_TO_RECOVERY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L0_TO_RECOVERY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_RECOVERY_COUNT 12:12 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_RECOVERY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_RECOVERY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_BAD_DLLP_COUNT 13:13 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_BAD_DLLP_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_BAD_DLLP_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_BAD_TLP_COUNT 14:14 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_BAD_TLP_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_BAD_TLP_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_CHIPSET_XMIT_L0S_ENTRY_COUNT 15:15 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_CHIPSET_XMIT_L0S_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_CHIPSET_XMIT_L0S_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_GPU_XMIT_L0S_ENTRY_COUNT 16:16 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_GPU_XMIT_L0S_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_GPU_XMIT_L0S_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_ENTRY_COUNT 17:17 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1P_ENTRY_COUNT 18:18 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1P_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1P_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_DEEP_L1_ENTRY_COUNT 19:19 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_DEEP_L1_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_DEEP_L1_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_ASLM_COUNT 20:20 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_ASLM_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_ASLM_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_SKPOS_ERRORS_COUNT 21:21 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_SKPOS_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_SKPOS_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_1_ENTRY_COUNT 22:22 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_1_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_1_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_2_ENTRY_COUNT 23:23 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_2_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_2_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_2_ABORT_COUNT 24:24 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_2_ABORT_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_2_ABORT_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT 25:25 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_SHORT_DURATION_COUNT 26:26 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_SHORT_DURATION_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_SHORT_DURATION_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_PRI_XP3G_CG 0x0008E000 /* RWI4R */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_DLY_CNT__PROD 0x0000000B /* RW--V */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_EN 6:6 /* RWIVF */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_XP_PRI_XP3G_CG_STATE_CG_EN 7:7 /* */
#define NV_XP_PRI_XP3G_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_XP_PRI_XP3G_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_XP_PRI_XP3G_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_STALL_CG_EN 14:14 /* RWIVF */
#define NV_XP_PRI_XP3G_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XP_PRI_XP3G_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XP_PRI_XP3G_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XP_PRI_XP3G_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_XP_PRI_XP3G_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_XP_PRI_XP3G_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
#define NV_XP_PRI_XP3G_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
#define NV_XP_PRI_XP3G_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_CNT 23:20 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_XP_PRI_XP3G_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_EN 28:28 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_PAUSE_CG_EN 30:30 /* */
#define NV_XP_PRI_XP3G_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_XP_PRI_XP3G_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_HALT_CG_EN 31:31 /* */
#define NV_XP_PRI_XP3G_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_XP_PRI_XP3G_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG1 0x0008E004 /* RWI4R */
#define NV_XP_PRI_XP3G_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_XP_PRI_XP3G_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XP_PRI_XP3G_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XP_PRI_XP3G_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XP_REPLAY_COUNT(i) (0x0008D580+(i)*4) /* R--4A */
#define NV_XP_REPLAY_COUNT__SIZE_1 1 /* */
#define NV_XP_REPLAY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_REPLAY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#endif // __lr10_dev_nv_xp_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nv_xve_h__
#define __lr10_dev_nv_xve_h__
/* This file is autogenerated. Do not edit */
#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */
#define NV_XVE_ERROR_COUNTER1 0x00000854 /* R--4R */
#define NV_XVE_ERROR_COUNTER1_CORR_ERROR_COUNT_VALUE 15:0 /* R-XVF */
#define NV_XVE_ERROR_COUNTER 0x000004AC /* R--4R */
#define NV_XVE_ERROR_COUNTER_RSVD_CORR_ERROR_COUNT_VALUE 7:0 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RSVD_CORR_ERROR_COUNT_VALUE_INIT 0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_NON_FATAL_ERROR_COUNT_VALUE 15:8 /* R-XVF */
#define NV_XVE_ERROR_COUNTER_FATAL_ERROR_COUNT_VALUE 23:16 /* R-XVF */
#define NV_XVE_ERROR_COUNTER_UNSUPP_REQ_COUNT_VALUE 31:24 /* R-XVF */
#define NV_XVE_PRI_XVE_CG 0x000004E8 /* RWI4R */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_EN 6:6 /* RWIVF */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG_STATE_CG_EN 7:7 /* */
#define NV_XVE_PRI_XVE_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_XVE_PRI_XVE_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_XVE_PRI_XVE_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_STALL_CG_EN 14:14 /* RWIVF */
#define NV_XVE_PRI_XVE_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PRI_XVE_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
#define NV_XVE_PRI_XVE_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_CNT 23:20 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_XVE_PRI_XVE_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_EN 28:28 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN 30:30 /* */
#define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_HALT_CG_EN 31:31 /* */
#define NV_XVE_PRI_XVE_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_XVE_PRI_XVE_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG1 0x000004EC /* RWI4R */
#define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG1_SLCG 17:1 /* RWIVF */
#define NV_XVE_PRI_XVE_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG1_SLCG_DISABLED 0x0001FFFF /* RWI-V */
#define NV_XVE_PRI_XVE_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_XVE_CYA_2 0x00000704 /* RW-4R */
#define NV_XVE_CYA_2_RSVD 31:0 /* RWCVF */
#define NV_XVE_CYA_2_RSVD_INIT 0x00000000 /* RWC-V */
#endif // __lr10_dev_nv_xve_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvlctrl_ip_h__
#define __lr10_dev_nvlctrl_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLCTRL_LINK_INTR_0_STATUS(i) (0x00000304+(i)*0x40) /* R--4A */
#define NV_NVLCTRL_LINK_INTR_0_STATUS__SIZE_1 4 /* */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_FATAL 0:0 /* R-EVF */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_FATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_NONFATAL 1:1 /* R-EVF */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_CORRECTABLE 2:2 /* R-EVF */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_INTR0 3:3 /* R-EVF */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_INTR1 4:4 /* R-EVF */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
#define NV_NVLCTRL_PLL_PRI_CLOCK_GATING 0x00000604 /* RW-4R */
#define NV_NVLCTRL_PLL_PRI_CLOCK_GATING_CG1_SLCG 0:0 /* RWEVF */
#define NV_NVLCTRL_PLL_PRI_CLOCK_GATING_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_NVLCTRL_PLL_PRI_CLOCK_GATING_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */
#define NV_NVLCTRL_PLL_PRI_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_NVLCTRL_COMMON_INTR_0_MASK 0x00000220 /* RW-4R */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_FATAL 0:0 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_FATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_NONFATAL 1:1 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_CORRECTABLE 2:2 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_INTR0 3:3 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_INTR0_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_INTR1 4:4 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_INTR1_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_1_MASK 0x00000228 /* RW-4R */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_FATAL 0:0 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_FATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_NONFATAL 1:1 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_CORRECTABLE 2:2 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_INTR0 3:3 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_INTR0_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_INTR1 4:4 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_INTR1_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_2_MASK 0x00000230 /* RW-4R */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_FATAL 0:0 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_FATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_NONFATAL 1:1 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_CORRECTABLE 2:2 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_INTR0 3:3 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_INTR0_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_INTR1 4:4 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_INTR1_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_0_MASK(i) (0x00000300+(i)*0x40) /* RW-4A */
#define NV_NVLCTRL_LINK_INTR_0_MASK__SIZE_1 4 /* */
#define NV_NVLCTRL_LINK_INTR_0_MASK_FATAL 0:0 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_0_MASK_FATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_0_MASK_NONFATAL 1:1 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_0_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_0_MASK_CORRECTABLE 2:2 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_0_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_0_MASK_INTR0 3:3 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_0_MASK_INTR0_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_0_MASK_INTR1 4:4 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_0_MASK_INTR1_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_1_MASK(i) (0x00000308+(i)*0x40) /* RW-4A */
#define NV_NVLCTRL_LINK_INTR_1_MASK__SIZE_1 4 /* */
#define NV_NVLCTRL_LINK_INTR_1_MASK_FATAL 0:0 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_1_MASK_FATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_1_MASK_NONFATAL 1:1 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_1_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_1_MASK_CORRECTABLE 2:2 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_1_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_1_MASK_INTR0 3:3 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_1_MASK_INTR0_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_1_MASK_INTR1 4:4 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_1_MASK_INTR1_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_2_MASK(i) (0x00000310+(i)*0x40) /* RW-4A */
#define NV_NVLCTRL_LINK_INTR_2_MASK__SIZE_1 4 /* */
#define NV_NVLCTRL_LINK_INTR_2_MASK_FATAL 0:0 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_2_MASK_FATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_2_MASK_NONFATAL 1:1 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_2_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_2_MASK_CORRECTABLE 2:2 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_2_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_2_MASK_INTR0 3:3 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_2_MASK_INTR0_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_2_MASK_INTR1 4:4 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_2_MASK_INTR1_INIT 0x00000000 /* RWI-V */
#endif // __lr10_dev_nvlctrl_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvldl_ip_h__
#define __lr10_dev_nvldl_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLDL_TOP_LINK_STATE 0x00000000 /* R--4R */
#define NV_NVLDL_TOP_LINK_STATE_STATE 7:0 /* R-XVF */
#define NV_NVLDL_TOP_LINK_STATE_STATE_INIT 0x00000000 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_HWCFG 0x00000001 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_SWCFG 0x00000002 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_ACTIVE 0x00000003 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_FAULT 0x00000004 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_SLEEP 0x00000005 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_RCVY_AC 0x00000008 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_RCVY_RX 0x0000000a /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_TRAIN 0x0000000b /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_AN0_BUSY 12:12 /* R-XVF */
#define NV_NVLDL_TOP_LINK_STATE_TL_BUSY 13:13 /* R-XVF */
#define NV_NVLDL_TOP_LINK_STATE_DBG_SUBSTATE 31:16 /* R-XVF */
#define NV_NVLDL_TOP_LINK_CHANGE 0x00000040 /* RW-4R */
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS 1:0 /* R-XVF */
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS_DONE 0x00000000 /* R---V */
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS_BUSY 0x00000001 /* R---V */
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS_FAULT 0x00000002 /* R---V */
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS_ABORT 0x00000003 /* R---V */
#define NV_NVLDL_TOP_LINK_CHANGE_ACTION 3:2 /* -WXVF */
#define NV_NVLDL_TOP_LINK_CHANGE_ACTION_LTSSM_CHANGE 0x00000001 /* -W--V */
#define NV_NVLDL_TOP_LINK_CHANGE_ACTION_LTSSM_FORCE 0x00000003 /* -W--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE 7:4 /* RWEVF */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_HWCFG 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_SWCFG 0x00000002 /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_ACTIVE 0x00000003 /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_RCVY_AC 0x00000008 /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_FAULT 0x00000004 /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_RCVY_RX 0x0000000a /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_SLEEP 0x00000005 /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_TRAIN 0x0000000b /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_OLDSTATE_MASK 19:16 /* RWEVF */
#define NV_NVLDL_TOP_LINK_CHANGE_OLDSTATE_MASK_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_LINK_CHANGE_OLDSTATE_MASK_DONTCARE 0x0000000f /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE 0x00000044 /* RW-4R */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS 1:0 /* R-EVF */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS_DONE 0x00000000 /* R-E-V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS_BUSY 0x00000001 /* R---V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS_FAULT 0x00000002 /* R---V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS_ABORT 0x00000003 /* R---V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_ACTION 3:2 /* -WEVF */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_ACTION_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_ACTION_SLSM_CHANGE 0x00000001 /* -W--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_ACTION_SLSM_FORCE 0x00000003 /* -W--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE 7:4 /* RWEUF */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_HS 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_EIGHTH 0x00000004 /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_TRAIN 0x00000005 /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_SAFE 0x00000006 /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_OFF 0x00000007 /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_SUBLINK 15:12 /* RWEUF */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_SUBLINK_TX 0x00000000 /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_SUBLINK_RX 0x00000001 /* RWE-V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_OLDSTATE_MASK 19:16 /* RWEUF */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_OLDSTATE_MASK_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_OLDSTATE_MASK_DONTCARE 0x0000000f /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_COUNTDOWN 31:20 /* RWEUF */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_COUNTDOWN_MAXIMUM 0x0000007f /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_COUNTDOWN_MINIMUM 0x00000008 /* RWE-V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_COUNTDOWN_IMMEDIATE 0x00000000 /* RW--V */
#define NV_NVLDL_TOP_LINK_TEST 0x00000048 /* RW-4R */
#define NV_NVLDL_TOP_LINK_TEST_MODE 0:0 /* RWEVF */
#define NV_NVLDL_TOP_LINK_TEST_MODE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_LINK_TEST_MODE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_LINK_TEST_AUTO_HWCFG 30:30 /* RWEVF */
#define NV_NVLDL_TOP_LINK_TEST_AUTO_HWCFG_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_LINK_TEST_AUTO_HWCFG_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_LINK_TEST_AUTO_NVHS 31:31 /* RWEVF */
#define NV_NVLDL_TOP_LINK_TEST_AUTO_NVHS_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_LINK_TEST_AUTO_NVHS_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR 0x00000050 /* RW-4R */
#define NV_NVLDL_TOP_INTR_TX_REPLAY 0:0 /* RWXVF */
#define NV_NVLDL_TOP_INTR_TX_RECOVERY_SHORT 1:1 /* RWXVF */
#define NV_NVLDL_TOP_INTR_TX_FAULT_RAM 4:4 /* RWXVF */
#define NV_NVLDL_TOP_INTR_TX_FAULT_INTERFACE 5:5 /* RWXVF */
#define NV_NVLDL_TOP_INTR_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWXVF */
#define NV_NVLDL_TOP_INTR_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWXVF */
#define NV_NVLDL_TOP_INTR_RX_FAULT_DL_PROTOCOL 20:20 /* RWXVF */
#define NV_NVLDL_TOP_INTR_RX_SHORT_ERROR_RATE 21:21 /* RWXVF */
#define NV_NVLDL_TOP_INTR_RX_LONG_ERROR_RATE 22:22 /* RWXVF */
#define NV_NVLDL_TOP_INTR_RX_ILA_TRIGGER 23:23 /* RWXVF */
#define NV_NVLDL_TOP_INTR_RX_CRC_COUNTER 24:24 /* RWXVF */
#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_DOWN 27:27 /* RWXVF */
#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_UP 28:28 /* RWXVF */
#define NV_NVLDL_TOP_INTR_LTSSM_PROTOCOL 29:29 /* RWXVF */
#define NV_NVLDL_TOP_INTR_MINION_REQUEST 30:30 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2 0x00000054 /* RW-4R */
#define NV_NVLDL_TOP_INTR_SW2_TX_REPLAY 0:0 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_RECOVERY_SHORT 1:1 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_RAM 4:4 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_INTERFACE 5:5 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_DL_PROTOCOL 20:20 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_SHORT_ERROR_RATE 21:21 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_LONG_ERROR_RATE 22:22 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_ILA_TRIGGER 23:23 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_CRC_COUNTER 24:24 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_DOWN 27:27 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_UP 28:28 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_PROTOCOL 29:29 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_MINION_REQUEST 30:30 /* RWXVF */
#define NV_NVLDL_TOP_INTR_STALL_EN 0x00000058 /* RW-4R */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_REPLAY 0:0 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_REPLAY_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT 1:1 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM 4:4 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE 5:5 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE 22:22 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER 23:23 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER 24:24 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN 27:27 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP 28:28 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL 29:29 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST 30:30 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN 0x0000005c /* RW-4R */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_REPLAY 0:0 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_REPLAY_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT 1:1 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM 4:4 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE 5:5 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE 22:22 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER 23:23 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER 24:24 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN 27:27 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP 28:28 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL 29:29 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST 30:30 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL 0x00000080 /* -W-4R */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_CLEAR_RECOVERY 2:2 /* -WXVF */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_CLEAR_RECOVERY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_TX_TRAIN0_TX 0x00002018 /* RW-4R */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0 10:0 /* RWEVF */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_INIT 0x00000260 /* RWE-V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_MINIMUM 0x00000001 /* RW--V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0__PROD_ISSC 0x00000648 /* RW--V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_SCL 15:11 /* RWEVF */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_SCL_INIT 0x00000004 /* RWE-V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_SCL_MINIMUM 0x00000000 /* RW--V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_SCL__PROD_ISSC 0x00000005 /* RW--V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_INFINITE 31:31 /* RWEVF */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_INFINITE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_INFINITE_ON 0x00000001 /* RW--V */
#define NV_NVLDL_TX_SLSM_STATUS_TX 0x00002024 /* R--4R */
#define NV_NVLDL_TX_SLSM_STATUS_TX_SUBSTATE 3:0 /* R-XVF */
#define NV_NVLDL_TX_SLSM_STATUS_TX_SUBSTATE_STABLE 0x00000000 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE 7:4 /* R-XVF */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_HS 0x00000000 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_EIGHTH 0x00000004 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN 0x00000005 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_SAFE 0x00000006 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_OFF 0x00000007 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_UNKNOWN 0x0000000d /* R---V */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL 0x00002280 /* -W-4R */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY 8:8 /* -WXVF */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_CONFIG_RX 0x00003000 /* RW-4R */
#define NV_NVLDL_RX_CONFIG_RX_HW_POLARITY_INVERT 3:0 /* R-EVF */
#define NV_NVLDL_RX_CONFIG_RX_HW_POLARITY_INVERT_NONE 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_CONFIG_RX_HW_POLARITY_INVERT_ALL 0x0000000f /* R---V */
#define NV_NVLDL_RX_CONFIG_RX_FIFO_WR_REQ_DELAY 7:4 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_FIFO_WR_REQ_DELAY_INIT 0x0000000a /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_HW_LANE_REVERSE 8:8 /* R-EVF */
#define NV_NVLDL_RX_CONFIG_RX_HW_LANE_REVERSE_OFF 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_CONFIG_RX_HW_LANE_REVERSE_ON 0x00000001 /* R---V */
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_INVERT 19:16 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_INVERT_NONE 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_INVERT_ALL 0x0000000f /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_ECC_MODE 23:22 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_ECC_MODE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_ECC_MODE_ECC96 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_ECC_MODE_ECC88 0x00000002 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_LANE_REVERSE 24:24 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_LANE_REVERSE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_LANE_REVERSE_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_IOBIST_EN 25:25 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_IOBIST_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_IOBIST_EN_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_PHY_NO_ADJUST 26:26 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_PHY_NO_ADJUST_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_PHY_NO_ADJUST_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_PHY_ADJUST_OVERRIDE 27:27 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_PHY_ADJUST_OVERRIDE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_PHY_ADJUST_OVERRIDE_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_OVERRIDE 28:28 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_OVERRIDE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_OVERRIDE_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_REVERSAL_OVERRIDE 29:29 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_REVERSAL_OVERRIDE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_REVERSAL_OVERRIDE_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_SKIP_TOGGLE_CONST 30:30 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_SKIP_TOGGLE_CONST_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_SKIP_TOGGLE_CONST_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_DEBUG_ENABLE 31:31 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_DEBUG_ENABLE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_DEBUG_ENABLE_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_SLSM_STATUS_RX 0x00003014 /* R--4R */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE 3:0 /* R-EVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE_STABLE 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE 7:4 /* R-XVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_HS 0x00000000 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_EIGHTH 0x00000004 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN 0x00000005 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_SAFE 0x00000006 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_OFF 0x00000007 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_UNKNOWN 0x0000000d /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SURPRISE_LD_CNT 15:8 /* R-EVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SURPRISE_LD_CNT_INIT 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS 31:31 /* R-EVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS_OFF 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS_ON 0x00000001 /* R---V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL 0x00003280 /* RW-4R */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC 0:0 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC 1:1 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES 2:2 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY 3:3 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS 4:4 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE 8:8 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE 9:9 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE 10:10 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE_FLIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE_SEQUENCE 0x00000001 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE 11:11 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE_FLIT 0x00000000 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE_SEQUENCE 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL 0x00003284 /* RW-4R */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN 2:0 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_EXP 3:3 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_EXP_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_MAN 6:4 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_MAN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP 11:8 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP_INIT 0x00000006 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_MAN 18:16 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_MAN_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_EXP 19:19 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_EXP_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_MAN 22:20 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_MAN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_EXP 28:24 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_EXP_INIT 0x00000006 /* RWE-V */
#endif // __lr10_dev_nvldl_ip_h__

30
src/common/inc/swref/published/nvswitch/lr10/dev_nvldl_ip_addendum.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvldl_ip_addendum_h__
#define __lr10_dev_nvldl_ip_addendum_h__
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK1_INITPLL_LINK_STATE 0:0
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK1_INITPLL_LINK_STATE_DONE 0x1
#endif // __lr10_dev_nvldl_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvlipt_ip_h__
#define __lr10_dev_nvlipt_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLIPT_COMMON_ERR_STATUS_0 0x00000280 /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_RSTSEQ_PLL_TIMEOUT 1:1 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_RSTSEQ_PLL_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_RSTSEQ_PLL_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_RSTSEQ_PHYARB_TIMEOUT 2:2 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_RSTSEQ_PHYARB_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_RSTSEQ_PHYARB_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0 0x00000288 /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PLL_TIMEOUT 1:1 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PLL_TIMEOUT__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PLL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PLL_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYARB_TIMEOUT 2:2 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYARB_TIMEOUT__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYARB_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYARB_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0 0x00000294 /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PLL_TIMEOUT 1:1 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PLL_TIMEOUT__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PLL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PLL_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PHYARB_TIMEOUT 2:2 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PHYARB_TIMEOUT__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PHYARB_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PHYARB_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0 0x00000298 /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_CLKCTL_ILLEGAL_REQUEST_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_CLKCTL_ILLEGAL_REQUEST_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_RSTSEQ_PLL_TIMEOUT 1:1 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_RSTSEQ_PLL_TIMEOUT_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_RSTSEQ_PLL_TIMEOUT_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_RSTSEQ_PHYARB_TIMEOUT 2:2 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_RSTSEQ_PHYARB_TIMEOUT_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_RSTSEQ_PHYARB_TIMEOUT_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0 0x0000029c /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_RSTSEQ_PLL_TIMEOUT 1:1 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_RSTSEQ_PLL_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_RSTSEQ_PLL_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_RSTSEQ_PHYARB_TIMEOUT 2:2 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_RSTSEQ_PHYARB_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_RSTSEQ_PHYARB_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON 0x00000300 /* RW-4R */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT0_EN 0:0 /* RWEVF */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT0_EN_INIT 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT1_EN 1:1 /* RWEVF */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT1_EN_INIT 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_LO 0x00000108 /* R--4R */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_LO_SID_31_0 31:0 /* R-IVF */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_LO_SID_31_0_INIT 0x00000000 /* R-I-V */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_HI 0x0000010c /* R--4R */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_HI_SID_63_32 31:0 /* R-IVF */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_HI_SID_63_32_INIT 0x00000000 /* R-I-V */
#endif // __lr10_dev_nvlipt_ip_h__

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