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Andy Ritger
2022-05-09 13:18:59 -07:00
commit 1739a20efc
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45
src/common/inc/swref/published/ampere/ga100/dev_boot.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_boot_h__
#define __ga100_dev_boot_h__
#define NV_PMC 0x00000fff:0x00000000 /* RW--D */
#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_DEVICE(i) (i):(i) /* */
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_DEVICE_ENABLE(i) (0x000000600+(i)*4) /* RW-4A */
#define NV_PMC_DEVICE_ENABLE__SIZE_1 1 /* */
#define NV_PMC_DEVICE_ENABLE__PRIV_LEVEL_MASK 0x00000084 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS 31:0 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_STATUS_DISABLE_ALL 0x00000000 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT(i) (i):(i) /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT__SIZE_1 32 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_ENABLE 0x00000001 /* */
#endif // __ga100_dev_boot_h__

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src/common/inc/swref/published/ampere/ga100/dev_bus.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef ga100_dev_nv_bus_h
#define ga100_dev_nv_bus_h
#define NV_PBUS_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */
#endif // ga100_dev_nv_bus_h

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src/common/inc/swref/published/ampere/ga100/dev_bus_addendum.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef ga100_dev_nv_bus_addendum_h
#define ga100_dev_nv_bus_addendum_h
#define NV_PBUS_SW_SCRATCH1_SMC_MODE 15:15
#define NV_PBUS_SW_SCRATCH1_SMC_MODE_OFF 0x00000000
#define NV_PBUS_SW_SCRATCH1_SMC_MODE_ON 0x00000001
#endif // ga100_dev_nv_bus_addendum_h

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src/common/inc/swref/published/ampere/ga100/dev_ce.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_ce_h__
#define __ga100_dev_ce_h__
#define NV_CE_PCE_MAP 0x00104028 /* R--4R */
#define NV_CE_PCE2LCE_CONFIG__SIZE_1 18 /* */
#define NV_CE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE 0x0000000f /* RW--V */
#define NV_CE_GRCE_CONFIG__SIZE_1 2 /* */
#define NV_CE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#define NV_CE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#endif

28
src/common/inc/swref/published/ampere/ga100/dev_ctrl.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_ctrl_h__
#define __ga100_dev_ctrl_h__
#define NV_CTRL_VF_DOORBELL_VECTOR 11:0 /* -WXUF */
#define NV_CTRL_VF_DOORBELL_RUNLIST_ID 22:16 /* -WXUF */
#endif // __ga100_dev_ctrl_h__

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src/common/inc/swref/published/ampere/ga100/dev_falcon_v4.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_falcon_v4_h__
#define __ga100_dev_falcon_v4_h__
#define NV_PFALCON_FALCON_IRQSCLR 0x00000004 /* -W-4R */
#define NV_PFALCON_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSTAT 0x00000008 /* R--4R */
#define NV_PFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMSET 0x00000010 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMCLR 0x00000014 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */
#define NV_PFALCON_FALCON_IRQDEST 0x0000001c /* RW-4R */
#define NV_PFALCON_FALCON_INTR_RETRIGGER(i) (0x000003e8+(i)*4) /* -W-4A */
#define NV_PFALCON_FALCON_INTR_RETRIGGER__SIZE_1 2 /* */
#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */
#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */
#define NV_PFALCON_FALCON_OS 0x00000080 /* RW-4R */
#define NV_PFALCON_FALCON_RM 0x00000084 /* RW-4R */
#define NV_PFALCON_FALCON_DEBUGINFO 0x00000094 /* RW-4R */
#define NV_PFALCON_FALCON_CPUCTL 0x00000100 /* RW-4R */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
#define NV_PFALCON_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS 0x00000130 /* -W-4R */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_BOOTVEC 0x00000104 /* RW-4R */
#define NV_PFALCON_FALCON_HWCFG 0x00000108 /* R--4R */
#define NV_PFALCON_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */
#define NV_PFALCON_FALCON_HWCFG2 0x000000f4 /* R--4R */
#define NV_PFALCON_FALCON_HWCFG2_RISCV 10:10 /* R--VF */
#define NV_PFALCON_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMACTL 0x0000010c /* RW-4R */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMATRFBASE 0x00000110 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFMOFFS 0x00000114 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFCMD 0x00000118 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */
#define NV_PFALCON_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMATRFCMD_SEC 3:2 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFFBOFFS 0x0000011c /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFBASE1 0x00000128 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFBASE1_BASE 8:0 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC(i) (0x00000180+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_BLK 23:8 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMD(i) (0x00000184+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMD_DATA 31:0 /* RW-VF */
#define NV_PFALCON_FALCON_IMEMT(i) (0x00000188+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMT_TAG 15:0 /* RW-VF */
#define NV_PFALCON_FALCON_DMEMC(i) (0x000001c0+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMC_OFFS 7:2 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_BLK 23:8 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMD_DATA 31:0 /* RW-VF */
#endif // __ga100_dev_falcon_v4_h__

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src/common/inc/swref/published/ampere/ga100/dev_fb.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_fb_h__
#define __ga100_dev_fb_h__
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR 0x00100C10 /* RW-4R */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_ADR_39_08 31:0 /* RWIVF */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_ADR_39_08_INIT 0x00000000 /* RWI-V */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI 0x00100C40 /* RW-4R */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI_MASK 0x7F /* */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI_ADR_63_40 23:0 /* RWIVF */
#define NV_PFB_FBHUB_POISON_INTR_VECTOR 0x00100A24 /* R--4R */
#define NV_PFB_FBHUB_POISON_INTR_VECTOR_HW 7:0 /* R-IVF */
#define NV_PFB_FBHUB_POISON_INTR_VECTOR_HW_INIT 135 /* R-I-V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK 0x001FA7C8 /* RW-4R */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO 0x001FA82C /* RW-4R */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7C8 /* */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_LOCK_ADDR_HI 0x001FA830 /* RW-4R */
#define NV_PFB_PRI_MMU_LOCK_ADDR_HI_VAL 31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_ADDR_HI_ALIGNMENT 0x0000000c /* */
#endif // __ga100_dev_fb_h__

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src/common/inc/swref/published/ampere/ga100/dev_fbif_v4.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_fbif_v4_h__
#define __ga100_dev_fbif_v4_h__
#define NV_PFALCON_FBIF_TRANSCFG(i) (0x00000000+(i)*4) /* RW-4A */
#define NV_PFALCON_FBIF_TRANSCFG__SIZE_1 8 /* */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_CTL 0x00000024 /* RW-4R */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */
#endif // __ga100_dev_fbif_v4_h__

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src/common/inc/swref/published/ampere/ga100/dev_fuse.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_fuse_h__
#define __ga100_dev_fuse_h__
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS 0x0082074C /* RW-4R */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA 0:0 /* RWIVF */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */
#define NV_FUSE_OPT_NVDEC_DISABLE 0x00820378 /* RW-4R */
#define NV_FUSE_OPT_NVDEC_DISABLE_DATA 4:0 /* RWIVF */
#define NV_FUSE_OPT_NVDEC_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION 0x00824100 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION 0x00824104 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION 0x00824108 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION 0x0082410C /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION 0x00824110 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION 0x00824114 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION 0x00824118 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION 0x0082411C /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION 0x00824120 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION 0x00824124 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION 0x00824128 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION 0x0082412C /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION 0x00824130 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION 0x00824134 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION 0x00824138 /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION 0x0082413C /* RW-4R */
#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION 0x00824140 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION 0x00824144 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION 0x00824148 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION 0x0082414C /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION 0x00824150 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION 0x00824154 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION 0x00824158 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION 0x0082415C /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION 0x00824160 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION 0x00824164 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION 0x00824168 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION 0x0082416C /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION 0x00824170 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION 0x00824174 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION 0x00824178 /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION 0x0082417C /* RW-4R */
#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION 0x008241C0 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION 0x008241C4 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION 0x008241C8 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION 0x008241CC /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION 0x008241D0 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION 0x008241D4 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION 0x008241D8 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION 0x008241DC /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION 0x008241E0 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION 0x008241E4 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION 0x008241E8 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION 0x008241EC /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION 0x008241F0 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION 0x008241F4 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION 0x008241F8 /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION_DATA 15:0 /* RWIVF */
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION 0x008241FC /* RW-4R */
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION_DATA 15:0 /* RWIVF */
#endif // __ga100_dev_fuse_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_mmu_h__
#define __ga100_dev_mmu_h__
#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */
#define NV_MMU_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */
#define NV_MMU_PDE_SIZE_FULL 0x00000000 /* RW--V */
#define NV_MMU_PDE_SIZE_HALF 0x00000001 /* RW--V */
#define NV_MMU_PDE_SIZE_QUARTER 0x00000002 /* RW--V */
#define NV_MMU_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */
#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */
#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */
#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */
#define NV_MMU_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_PDE__SIZE 8
#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */
#define NV_MMU_PTE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */
#define NV_MMU_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */
#define NV_MMU_PTE_READ_ONLY_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_READ_ONLY_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */
#define NV_MMU_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */
#define NV_MMU_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */
#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */
#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */
#define NV_MMU_PTE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PTE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */
#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PTE_LOCK (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_PTE_LOCK_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_LOCK_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_COMPTAGLINE (1*32+20+11):(1*32+12) /* RWXVF */
#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) /* RWXVF */
#define NV_MMU_PTE_READ_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_READ_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) /* RWXVF */
#define NV_MMU_PTE_WRITE_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_WRITE_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_PTE__SIZE 8
#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x09 /* R---V */
#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0x0F /* R---V */
#endif // __ga100_dev_mmu_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_nv_xve_h__
#define __ga100_dev_nv_xve_h__
#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */
#define NV_XVE_LINK_CONTROL_STATUS 0x00000088 /* RW-4R */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED 19:16 /* R--VF */
#endif

45
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_nv_xve_addendum_h__
#define __ga100_dev_nv_xve_addendum_h__
//
// Extra config bits that can be emulated by the hypervisor for passthrough.
// This offset is unused in HW and HW returns 0x0 on read.
//
#define NV_XVE_PASSTHROUGH_EMULATED_CONFIG 0xE8
//
// On GA100, we need to be able to detect the case where the GPU is running at
// gen4, but the root port is at gen3. On baremetal, we just check the root
// port directly, but for passthrough root port is commonly completely hidden
// or fake. To handle this case we support the hypervisor explicitly
// communicating the speed to us through emulated config space. The
// ROOT_PORT_SPEED field follows the usual link speed encoding with the
// numerical value matching the gen speed, i.e. gen3 is 0x3.
// See bug 2927491 for more details.
//
#define NV_XVE_PASSTHROUGH_EMULATED_CONFIG_ROOT_PORT_SPEED 3:0
#endif

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src/common/inc/swref/published/ampere/ga100/dev_nvdec_addendum.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_nvdec_addendum_h__
#define __ga100_dev_nvdec_addendum_h__
#define NV_PNVDEC_FBIF_BASE(dev) (0x00848600+(dev)*16384)
#endif // __ga100_dev_nvdec_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_nvdec_pri_h__
#define __ga100_dev_nvdec_pri_h__
#define NV_PNVDEC(dev) 0x0084bfff+(dev)*16384:0x00848000+(dev)*16384 /* RW--D */
#endif // __ga100_dev_nvdec_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_ram_h__
#define __ga100_dev_ram_h__
#define NV_RAMIN_ALLOC_SIZE 4096 /* */
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_LO (31+0*32):(8+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI_HW (7+1*32):(0+1*32) /* RWXUF */
#define NV_RAMRL_ENTRY_BASE_SHIFT 12 /* */
#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) /* RW-UF */
#define NV_RAMUSERD_GET (17*32+31):(17*32+0) /* RW-UF */
#define NV_RAMUSERD_REF (18*32+31):(18*32+0) /* RW-UF */
#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) /* RW-UF */
#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) /* RW-UF */
#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) /* RW-UF */
#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) /* RW-UF */
#define NV_RAMUSERD_GP_GET (34*32+31):(34*32+0) /* RW-UF */
#define NV_RAMUSERD_GP_PUT (35*32+31):(35*32+0) /* RW-UF */
#endif // __ga100_dev_ram_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_riscv_pri_h__
#define __ga100_dev_riscv_pri_h__
#define NV_FALCON2_GSP_BASE 0x00111000
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS 0x00000240 /* R-I4R */
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS_ACTIVE_STAT 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_IRQMASK 0x000002b4 /* R-I4R */
#define NV_PRISCV_RISCV_IRQDEST 0x000002b8 /* RW-4R */
#endif // __ga100_dev_riscv_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_runlist_h__
#define __ga100_dev_runlist_h__
#define NV_CHRAM_CHANNEL(i) (0x000+(i)*4) /* RW-4A */
#endif // __ga100_dev_runlist_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_sec_addendum_h__
#define __ga100_dev_sec_addendum_h__
#define NV_PSEC_FBIF_BASE 0x00840600
#endif // __ga100_dev_sec_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_sec_pri_h__
#define __ga100_dev_sec_pri_h__
#define NV_PSEC 0x843fff:0x840000 /* RW--D */
#define NV_PSEC_FALCON_ENGINE 0x008403c0 /* RW-4R */
#define NV_PSEC_FALCON_ENGINE_RESET 0:0 /* RWIVF */
#define NV_PSEC_FALCON_ENGINE_RESET_TRUE 0x00000001 /* RW--V */
#define NV_PSEC_FALCON_ENGINE_RESET_FALSE 0x00000000 /* RWI-V */
#define NV_PSEC_MAILBOX(i) (0x00840804+(i)*4) /* RW-4A */
#define NV_PSEC_MAILBOX__SIZE_1 4 /* */
#define NV_PSEC_MAILBOX_DATA 31:0 /* RWIVF */
#define NV_PSEC_MAILBOX_DATA_INIT 0x00000000 /* RWI-V */
#endif // __ga100_dev_sec_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_timer_h__
#define __ga100_dev_timer_h__
#define NV_PTIMER_ALARM_INTR 0x00009140 /* RW-4R */
#define NV_PTIMER_ALARM_INTR_MASK 0:0 /* RWIVF */
#define NV_PTIMER_ALARM_INTR_MASK_DISABLED 0x00000000 /* RWI-V */
#define NV_PTIMER_ALARM_INTR_MASK_ENABLED 0x00000001 /* RW--V */
#endif // __ga100_dev_timer_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga100_dev_vm_h__
#define __ga100_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP(i) (0x1600+(i)*4) /* R--4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_VALUE 31:0 /* R--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_PENDING 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_NOT_PENDING 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(i) (0x1608+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLE 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLED 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_DISABLED 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(i) (0x1610+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLE 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_ENABLED 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLED 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(i) (0x1000+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 8 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(i) (0x1200+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1 8 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(i) (0x1400+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 8 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER 0x00001640 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -W-VF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE 0x000030B0 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA 0:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_PDB 1:1 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_PDB_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_PDB_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_HUBTLB_ONLY 2:2 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_HUBTLB_ONLY_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_HUBTLB_ONLY_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY 5:3 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_NONE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_START 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SYS_MEMBAR 6:6 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SYS_MEMBAR_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SYS_MEMBAR_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK 8:7 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK_NONE_REQUIRED 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK_INTRANODE 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK_GLOBALLY 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_ID 14:9 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_GPC_ID 19:15 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_INVAL_SCOPE 16:15 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_INVAL_SCOPE_LINK_TLBS 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE 20:20 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_PASID 21:21 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_PASID_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_PASID_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_SIZE 22:22 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_SIZE_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_SIZE_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PROP_FLUSH 23:23 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PROP_FLUSH_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PROP_FLUSH_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL 26:24 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_ALL 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2 0x00000004 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3 0x00000005 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4 0x00000006 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5 0x00000007 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_READ 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_STRONG 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_RSVRVD 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_WEAK 0x00000004 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_ALL 0x00000005 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE_AND_ATOMIC 0x00000006 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ALL 0x00000007 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER 31:31 /* -WEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER_FALSE 0x00000000 /* -WE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER_TRUE 0x00000001 /* -W--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_MAX_CACHELINE_SIZE 0x00000010 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_TIME_0 0x30080 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_0_NSEC 31:5 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_TIME_1 0x30084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_1_NSEC 28:0 /* R-XUF */
#endif // __ga100_dev_vm_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef ga100_dev_vm_addendum_h
#define ga100_dev_vm_addendum_h
//
// Compile time asserts in the source code files will ensure that
// these don't end up exceeding the range of the top level registers.
//
// Subtrees at CPU_INTR top level for UVM owned interrupts
#define NV_CPU_INTR_UVM_SUBTREE_START NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(1)
#define NV_CPU_INTR_UVM_SUBTREE_LAST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(1)
#define NV_CPU_INTR_UVM_SHARED_SUBTREE_START NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(2)
#define NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(2)
//
// Subtrees at CPU_INTR top level for all stall interrupts from host-driven
// engines
//
#define NV_CPU_INTR_STALL_SUBTREE_START NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(3)
#define NV_CPU_INTR_STALL_SUBTREE_LAST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(3)
#endif // ga100_dev_vm_addendum_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_boot_h__
#define __ga102_dev_boot_h__
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_DEVICE(i) (i):(i) /* */
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_DEVICE_ENABLE(i) (0x000000600+(i)*4) /* RW-4A */
#define NV_PMC_DEVICE_ENABLE__SIZE_1 1 /* */
#define NV_PMC_DEVICE_ENABLE__PRIV_LEVEL_MASK 0x00000084 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS 31:0 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_STATUS_DISABLE_ALL 0x00000000 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT(i) (i):(i) /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT__SIZE_1 26 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_ENABLE 0x00000001 /* */
#endif // __ga102_dev_boot_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_ce_h__
#define __ga102_dev_ce_h__
#define NV_CE_PCE_MAP 0x00104028 /* R--4R */
#define NV_CE_PCE_MAP_VALUE 23:0 /* R-XVF */
#define NV_CE_HSH_PCE_MASK 0x0010404c /* C--4R */
#define NV_CE_HSH_PCE_MASK_VALUE 23:0 /* C--VF */
#define NV_CE_PCE2LCE_CONFIG__SIZE_1 6 /* */
#define NV_CE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE 0x0000000f /* RW--V */
#define NV_CE_GRCE_CONFIG__SIZE_1 2 /* */
#define NV_CE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#define NV_CE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_falcon_second_pri_h__
#define __ga102_dev_falcon_second_pri_h__
#define NV_FALCON2_GSP_BASE 0x00111000
#define NV_FALCON2_NVDEC0_BASE 0x00849c00
#define NV_FALCON2_SEC_BASE 0x00841000
#define NV_PFALCON2_FALCON_MOD_SEL 0x00000180 /* RWI4R */
#define NV_PFALCON2_FALCON_MOD_SEL_ALGO 7:0 /* RWIVF */
#define NV_PFALCON2_FALCON_MOD_SEL_ALGO_RSA3K 0x00000001 /* RW--V */
#define NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID 0x00000198 /* RWI4R */
#define NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID_VAL 7:0 /* RWIVF */
#define NV_PFALCON2_FALCON_BROM_ENGIDMASK 0x0000019c /* RWI4R */
#define NV_PFALCON2_FALCON_BROM_PARAADDR(i) (0x00000210+(i)*4) /* RWI4A */
#endif // __ga102_dev_falcon_second_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_falcon_v4_h__
#define __ga102_dev_falcon_v4_h__
#define NV_PFALCON_FALCON_IRQSCLR 0x00000004 /* -W-4R */
#define NV_PFALCON_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSTAT 0x00000008 /* R--4R */
#define NV_PFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_INTR_RETRIGGER(i) (0x000003e8+(i)*4) /* -W-4A */
#define NV_PFALCON_FALCON_INTR_RETRIGGER__SIZE_1 2 /* */
#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */
#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQMSET 0x00000010 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMCLR 0x00000014 /* -W-4R */
#define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */
#define NV_PFALCON_FALCON_IRQDEST 0x0000001c /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */
#define NV_PFALCON_FALCON_DMACTL 0x0000010c /* RW-4R */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMATRFBASE 0x00000110 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFMOFFS 0x00000114 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFCMD 0x00000118 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */
#define NV_PFALCON_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMATRFCMD_SEC 3:2 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */
#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMATRFFBOFFS 0x0000011c /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMATRFBASE1 0x00000128 /* RW-4R */
#define NV_PFALCON_FALCON_DMATRFBASE1_BASE 8:0 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC(i) (0x00000180+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_BLK 23:8 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMD(i) (0x00000184+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMD_DATA 31:0 /* RWXVF */
#define NV_PFALCON_FALCON_IMEMT(i) (0x00000188+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMT_TAG 15:0 /* RWXVF */
#define NV_PFALCON_FALCON_DMEMC(i) (0x000001c0+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMC_OFFS 7:2 /* */
#define NV_PFALCON_FALCON_DMEMC_BLK 23:8 /* */
#define NV_PFALCON_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMD_DATA 31:0 /* RWXVF */
#define NV_PFALCON_FALCON_HWCFG 0x00000108 /* R--4R */
#define NV_PFALCON_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */
#define NV_PFALCON_FALCON_HWCFG2 0x000000f4 /* R--4R */
#define NV_PFALCON_FALCON_HWCFG2_RISCV 10:10 /* R--VF */
#define NV_PFALCON_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */
#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_OS 0x00000080 /* RW-4R */
#define NV_PFALCON_FALCON_RM 0x00000084 /* RW-4R */
#define NV_PFALCON_FALCON_DEBUGINFO 0x00000094 /* RW-4R */
#define NV_PFALCON_FALCON_CPUCTL 0x00000100 /* RW-4R */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
#define NV_PFALCON_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS 0x00000130 /* -W-4R */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_BOOTVEC 0x00000104 /* RW-4R */
#endif // __ga102_dev_falcon_v4_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_falcon_v4_addendum_h__
#define __ga102_dev_falcon_v4_addendum_h__
#define NV_PFALCON_FALCON_HWCFG2_RESET_READY 31:31
#define NV_PFALCON_FALCON_HWCFG2_RESET_READY_TRUE 0x00000001
#define NV_PFALCON_FALCON_HWCFG2_RESET_READY_FALSE 0x00000000
#endif

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_fbif_v4_h__
#define __ga102_dev_fbif_v4_h__
#define NV_PFALCON_FBIF_TRANSCFG(i) (0x00000000+(i)*4) /* RW-4A */
#define NV_PFALCON_FBIF_TRANSCFG__SIZE_1 8 /* */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_CTL 0x00000024 /* RW-4R */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */
#endif // __ga102_dev_fbif_v4_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_gc6_island_h__
#define __ga102_dev_gc6_island_h__
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK 0x00118128 /* RW-4R */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 0x001183a4 /* RW-4R */
#endif // __ga102_dev_gc6_island_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_gc6_island_addendum_h__
#define __ga102_dev_gc6_island_addendum_h__
#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0 NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(0)
#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE 15:0
#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K 0x100
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(0)
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS 7:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED 0x000000FF
#define NV_USABLE_FB_SIZE_IN_MB NV_PGC6_AON_SECURE_SCRATCH_GROUP_42
#define NV_USABLE_FB_SIZE_IN_MB_VALUE 31:0
#define NV_USABLE_FB_SIZE_IN_MB_VALUE_INIT 0
#endif // __ga102_dev_gc6_island_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_gsp_h__
#define __ga102_dev_gsp_h__
#define NV_PGSP 0x113fff:0x110000 /* RW--D */
#define NV_PGSP_FALCON_MAILBOX0 0x110040 /* RW-4R */
#define NV_PGSP_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
#define NV_PGSP_FALCON_MAILBOX1 0x110044 /* RW-4R */
#define NV_PGSP_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
#define NV_PGSP_FALCON_ENGINE 0x1103c0 /* RW-4R */
#define NV_PGSP_FALCON_ENGINE_RESET 0:0 /* RWIVF */
#define NV_PGSP_FALCON_ENGINE_RESET_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_FALCON_ENGINE_RESET_FALSE 0x00000000 /* RWI-V */
#define NV_PGSP_MAILBOX(i) (0x110804+(i)*4) /* RW-4A */
#define NV_PGSP_MAILBOX__SIZE_1 4 /* */
#define NV_PGSP_MAILBOX_DATA 31:0 /* RWIVF */
#define NV_PGSP_QUEUE_HEAD(i) (0x110c00+(i)*8) /* RW-4A */
#define NV_PGSP_QUEUE_HEAD__SIZE_1 8 /* */
#define NV_PGSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
#endif // __ga102_dev_gsp_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_gsp_addendum_h__
#define __ga102_dev_gsp_addendum_h__
#define NV_PGSP_FBIF_BASE 0x110600
#endif // __ga102_dev_gsp_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_nvdec_addendum_h__
#define __ga102_dev_nvdec_addendum_h__
#define NV_PNVDEC_FBIF_BASE(dev) (0x00848600+(dev)*16384)
#endif // __ga102_dev_nvdec_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_nvdec_pri_h__
#define __ga102_dev_nvdec_pri_h__
#define NV_PNVDEC(dev) 0x0084bfff+(dev)*16384:0x00848000+(dev)*16384 /* RW--D */
#endif // __ga102_dev_nvdec_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_ram_h__
#define __ga102_dev_ram_h__
#define NV_RAMRL_ENTRY_BASE_SHIFT 10 /* */
#endif // __ga102_dev_ram_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_riscv_pri_h__
#define __ga102_dev_riscv_pri_h__
#define NV_FALCON2_GSP_BASE 0x00111000
#define NV_PRISCV_RISCV_IRQMASK 0x00000528 /* R-I4R */
#define NV_PRISCV_RISCV_IRQDEST 0x0000052c /* RW-4R */
#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RWI4R */
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_BCR_CTRL 0x00000668 /* RWI4R */
#define NV_PRISCV_RISCV_BCR_CTRL_VALID 0:0 /* R-IVF */
#define NV_PRISCV_RISCV_BCR_CTRL_VALID_TRUE 0x00000001 /* R---V */
#define NV_PRISCV_RISCV_BCR_CTRL_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_PRISCV_RISCV_BCR_CTRL_CORE_SELECT 4:4 /* RWIVF */
#define NV_PRISCV_RISCV_BCR_CTRL_CORE_SELECT_FALCON 0x00000000 /* RWI-V */
#define NV_PRISCV_RISCV_BCR_CTRL_CORE_SELECT_RISCV 0x00000001 /* RW--V */
#define NV_PRISCV_RISCV_BCR_CTRL_BRFETCH 8:8 /* RWIVF */
#define NV_PRISCV_RISCV_BCR_CTRL_BRFETCH_TRUE 0x00000001 /* RWI-V */
#define NV_PRISCV_RISCV_BCR_CTRL_BRFETCH_FALSE 0x00000000 /* RW--V */
#endif // __ga102_dev_riscv_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_sec_addendum_h__
#define __ga102_dev_sec_addendum_h__
#define NV_PSEC_FBIF_BASE 0x00840600
#endif // __ga102_dev_sec_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_sec_pri_h__
#define __ga102_dev_sec_pri_h__
#define NV_PSEC 0x843fff:0x840000 /* RW--D */
#define NV_PSEC_FALCON_ENGINE 0x008403c0 /* RW-4R */
#define NV_PSEC_FALCON_ENGINE_RESET 0:0 /* RWIVF */
#define NV_PSEC_FALCON_ENGINE_RESET_TRUE 0x00000001 /* RW--V */
#define NV_PSEC_FALCON_ENGINE_RESET_FALSE 0x00000000 /* RWI-V */
#define NV_PSEC_MAILBOX(i) (0x00840804+(i)*4) /* RW-4A */
#define NV_PSEC_MAILBOX__SIZE_1 4 /* */
#define NV_PSEC_MAILBOX_DATA 31:0 /* RWIVF */
#define NV_PSEC_MAILBOX_DATA_INIT 0x00000000 /* RWI-V */
#endif // __ga102_dev_sec_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ga102_dev_vm_h__
#define __ga102_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP(i) (0x1600+(i)*4) /* R--4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_VALUE 31:0 /* R--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_PENDING 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_NOT_PENDING 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(i) (0x1608+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLE 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLED 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_DISABLED 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(i) (0x1610+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLE 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_ENABLED 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLED 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(i) (0x1000+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 8 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(i) (0x1200+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1 8 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(i) (0x1400+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 8 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER 0x00001640 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -WXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#endif // __ga102_dev_vm_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DEV_BR03_XVD_H
#define DEV_BR03_XVD_H
#define NV_BR03_XVD_LINK_CTRLSTAT 0x00000070 /* RWI4R */
#define NV_BR03_XVD_XP_0 0x00000B00 /* RW-4R */
#define NV_BR03_XVD_XP_0_UPDATE_FC_THRESHOLD 9:1 /* RWIVF */
#define NV_BR03_XVD_XP_0_UPDATE_FC_THRESHOLD_INIT 0x00000000 /* RWI-V */
#define NV_BR03_XVD_XP_0_OPPORTUNISTIC_ACK 29:29 /* RWIVF */
#define NV_BR03_XVD_XP_0_OPPORTUNISTIC_ACK_INIT 0x00000000 /* RWI-V */
#define NV_BR03_XVD_XP_0_OPPORTUNISTIC_UPDATE_FC 30:30 /* RWIVF */
#define NV_BR03_XVD_XP_0_OPPORTUNISTIC_UPDATE_FC_INIT 0x00000000 /* RWI-V */
#endif /* DEV_BR03_XVD_H */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DEV_BR03_XVU_H
#define DEV_BR03_XVU_H
#define NV_BR03_XVU 0x00000FFF:0x00000000 /* RW--D */
#define NV_BR03_XVU_DEV_ID 0x00000000 /* R--4R */
#define NV_BR03_XVU_DEV_ID_DEVICE_ID 31:16 /* C--VF */
#define NV_BR03_XVU_DEV_ID_DEVICE_ID_BR03 0x000001B3 /* C---V */
#define NV_BR03_XVU_REV_CC 0x00000008 /* R--4R */
#define NV_BR03_XVU_MCC_REG_ALIAS 0x00000600 /* RW-4R */
#define NV_BR03_XVU_MCC_REG_ALIAS_ACCESS 0:0 /* RWIVF */
#define NV_BR03_XVU_MCC_REG_ALIAS_ACCESS_INIT 0x00000000 /* RWI-V */
#define NV_BR03_XVU_MCC_REG_ALIAS_ACCESS_DISABLED 0x00000000 /* RW--V */
#define NV_BR03_XVU_MCC_REG_ALIAS_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_BR03_XVU_MCC_REG_ALIAS_BASE_ADDRESS 31:14 /* RWIUF */
#define NV_BR03_XVU_MCC_REG_ALIAS_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_BR03_XVU_UP0_INT_BUFSIZE_CPL 0x00000300 /* R--4R */
#define NV_BR03_XVU_UP0_INT_BUFSIZE_CPL_H 7:0 /* R--UF */
#define NV_BR03_XVU_UP0_INT_BUFSIZE_CPL_D 27:16 /* R--UF */
#define NV_BR03_XVU_INT_FLOW_CTL 0x00000340 /* RW-4R */
#define NV_BR03_XVU_INT_FLOW_CTL_DP0_TO_UP0_CPL 0x00000350 /* RW-4R */
#define NV_BR03_XVU_INT_FLOW_CTL_UP0_TO_MH0_PW 0x00000408 /* RW-4R */
#define NV_BR03_XVU_ITX_ALLOCATION 0x00000500 /* RW-4R */
#define NV_BR03_XVU_ITX_ALLOCATION_UP0 3:0 /* RWIUF */
#define NV_BR03_XVU_ITX_ALLOCATION_UP0_INIT 0x00000001 /* RWI-V */
#define NV_BR03_XVU_ITX_ALLOCATION_DP0 11:8 /* RWIUF */
#define NV_BR03_XVU_ITX_ALLOCATION_DP0_INIT 0x00000001 /* RWI-V */
#define NV_BR03_XVU_ITX_ALLOCATION_DP1 19:16 /* RWIUF */
#define NV_BR03_XVU_ITX_ALLOCATION_DP1_INIT 0x00000001 /* RWI-V */
#define NV_BR03_XVU_ITX_ALLOCATION_MH0 27:24 /* RWIUF */
#define NV_BR03_XVU_ITX_ALLOCATION_MH0_INIT 0x00000001 /* RWI-V */
#define NV_BR03_XVU_XP_0 0x00000B00 /* RW-4R */
#define NV_BR03_XVU_XP_0_OPPORTUNISTIC_ACK 29:29 /* RWIVF */
#define NV_BR03_XVU_XP_0_OPPORTUNISTIC_ACK_INIT 0x00000000 /* RWI-V */
#define NV_BR03_XVU_XP_0_OPPORTUNISTIC_UPDATE_FC 30:30 /* RWIVF */
#define NV_BR03_XVU_XP_0_OPPORTUNISTIC_UPDATE_FC_INIT 0x00000000 /* RWI-V */
#endif /* DEV_BR03_XVU_H */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef BR04_REF_H
#define BR04_REF_H
#include "published/br04/dev_br04_xvd.h"
#include "published/br04/dev_br04_xvu.h"
// BR04 can be accessed through a window in GPU register space
#define NV_BR04(i) (0x00018000 + (i * 0x00004000))
// Config space access for downstream ports begins at 8Ki, a port every 2Ki
#define NV_BR04_XVD_OFFSET(i) ((1<<13) + (1<<11)*i)
// Size of total config space and for upstream, downstream ports.
#define NV_BR04_CONFIG_SIZE (1 << 14)
#define NV_BR04_XVU_CONFIG_SIZE (1 << 12)
#define NV_BR04_XVD_CONFIG_SIZE (1 << 11)
// This enumeration is in the order of the _BUFSIZE_ registers; the FLOW_CTL
// registers are in a different order.
typedef enum {
BR04_PORT_UP0 = 0,
BR04_PORT_DP0,
BR04_PORT_DP1,
BR04_PORT_DP2,
BR04_PORT_DP3,
BR04_PORT_MH0,
NUM_BR04_PORTS
} BR04_PORT;
// Is this a BR04 devid or not
// Based on assumption that XVD and XVU has same deviceID
#define IS_DEVID_BR04(i) ((i >> 4) == (NV_BR04_XVU_DEV_ID_DEVICE_ID_BR04_0 >> 4))
// Phantom address to use for HGPU P2P transfers
#define HGPU_P2P_PHANTOM_BASE 0xf0f0f0f000000000LL
#endif // BR04_REF_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DEV_BR04_XVD_H
#define DEV_BR04_XVD_H
#define NV_BR04_XVD_LINK_CTRLSTAT 0x00000070 /* RW-4R */
#define NV_BR04_XVD_LINK_CTRLSTAT_ASPM_CTRL 1:0 /* RWIVF */
#define NV_BR04_XVD_LINK_CTRLSTAT_ASPM_CTRL_DISABLED 0x00000000 /* RWI-V */
#define NV_BR04_XVD_LINK_CTRLSTAT_ASPM_CTRL_L0S 0x00000001 /* RW--V */
#define NV_BR04_XVD_LINK_CTRLSTAT_ASPM_CTRL_L1 0x00000002 /* RW--V */
#define NV_BR04_XVD_LINK_CTRLSTAT_ASPM_CTRL_L0S_L1 0x00000003 /* RW--V */
#define NV_BR04_XVD_LINK_CTRLSTAT2 0x00000090 /* RW-4R */
#define NV_BR04_XVD_LINK_CTRLSTAT2_TARGET_LINK_SPEED 3:0 /* RWIVF */
#define NV_BR04_XVD_LINK_CTRLSTAT2_TARGET_LINK_SPEED_2P5G 0x00000001 /* RW--V */
#define NV_BR04_XVD_LINK_CTRLSTAT2_TARGET_LINK_SPEED_5P0G 0x00000002 /* RWI-V */
#define NV_BR04_XVD_G2_PRIV_XP_LCTRL_2 0x0000046C /* RW-4R */
#define NV_BR04_XVD_G2_PRIV_XP_LCTRL_2_ADVERTISED_RATE_CHANGE 1:1 /* CWIVF */
#define NV_BR04_XVD_G2_PRIV_XP_LCTRL_2_ADVERTISED_RATE_CHANGE_ZERO 0x00000000 /* CWI-V */
#define NV_BR04_XVD_BUS 0x00000018 /* RW-4R */
#define NV_BR04_XVD_BUS_SEC_NUMBER 15:8 /* RWIUF */
#define NV_BR04_XVD_BUS_SEC_NUMBER_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVD_BUS_SUB_NUMBER 23:16 /* RWIUF */
#define NV_BR04_XVD_BUS_SUB_NUMBER_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVD_G2_PRIV_XP_CONFIG 0x00000494 /* RW-4R */
#define NV_BR04_XVD_G2_PRIV_XP_CONFIG_GEN2_REPLAY_TIMER_LIMIT 11:2 /* RWIVF */
#define NV_BR04_XVD_G2_PRIV_XP_CONFIG_GEN2_REPLAY_TIMER_LIMIT_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVD_LINK_CTRLSTAT_DLL_LINK_SM 29:29 /* R--VF */
#define NV_BR04_XVD_LINK_CTRLSTAT_DLL_LINK_SM_NOT_ACTIVE 0x00000000 /* R---V */
#define NV_BR04_XVD_LINK_CTRLSTAT_DLL_LINK_SM_ACTIVE 0x00000001 /* R---V */
#define NV_BR04_XVD_G2_VEND_XP 0x00000400 /* RW-4R */
#define NV_BR04_XVD_G2_VEND_XP_OPPORTUNISTIC_ACK 28:28 /* RWIVF */
#define NV_BR04_XVD_G2_VEND_XP_OPPORTUNISTIC_ACK_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVD_G2_VEND_XP_OPPORTUNISTIC_UPDATEFC 29:29 /* RWIVF */
#define NV_BR04_XVD_G2_VEND_XP_OPPORTUNISTIC_UPDATEFC_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVD_G2_VEND_XP1 0x00000404 /* RW-4R */
#define NV_BR04_XVD_G2_VEND_XP1_REPLAY_TIMER_LIMIT 9:0 /* RWIVF */
#define NV_BR04_XVD_G2_VEND_XP1_REPLAY_TIMER_LIMIT_INIT 0x00000000 /* RWI-V */
#endif // DEV_BR04_XVD_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DEV_BR04_XVU_H
#define DEV_BR04_XVU_H
#define NV_BR04_XVU 0x00000DFF:0x00000000 /* RW--D */
#define NV_BR04_XVU_DEV_ID 0x00000000 /* R--4R */
#define NV_BR04_XVU_DEV_ID_VENDOR_ID 15:0 /* C--VF */
#define NV_BR04_XVU_DEV_ID_VENDOR_ID_NVIDIA 0x000010DE /* C---V */
#define NV_BR04_XVU_DEV_ID_DEVICE_ID 31:16 /* R-IVF */
#define NV_BR04_XVU_DEV_ID_DEVICE_ID_BR04_0 0x000005B0 /* R---V */
#define NV_BR04_XVU_DEV_ID_DEVICE_ID_BR04_15 0x000005BF /* R---V */
#define NV_BR04_XVU_DEV_ID_DEVICE_ID_DEFAULT 0x000005BF /* R-I-V */
#define NV_BR04_XVU_BUS 0x00000018 /* RW-4R */
#define NV_BR04_XVU_BUS_PRI_NUMBER 7:0 /* RWIUF */
#define NV_BR04_XVU_BUS_PRI_NUMBER_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_BUS_SEC_NUMBER 15:8 /* RWIUF */
#define NV_BR04_XVU_BUS_SEC_NUMBER_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_BUS_SUB_NUMBER 23:16 /* RWIUF */
#define NV_BR04_XVU_BUS_SUB_NUMBER_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_REV_CC 0x00000008 /* R--4R */
#define NV_BR04_XVU_REV_CC_MINOR_REVISION_ID 3:0 /* R--VF */
#define NV_BR04_XVU_REV_CC_MAJOR_REVISION_ID 7:4 /* R--VF */
#define NV_BR04_XVU_INT_FLOW_CTL 0x00000360 /* RW-4R */
#define NV_BR04_XVU_INT_FLOW_CTL_UP0_TOO_CPL(i) (0x000004F0+(i)*16) /* RW-4A */
#define NV_BR04_XVU_INT_FLOW_CTL_DP0_TOO_CPL(i) (0x00000370+(i)*16) /* RW-4A */
#define NV_BR04_XVU_INT_FLOW_CTL_DP0_TOO_CPL__SIZE_1 6 /* */
#define NV_BR04_XVU_INT_FLOW_CTL_DP0_TOO_CPL_H 6:0 /* RWIUF */
#define NV_BR04_XVU_INT_FLOW_CTL_DP0_TOO_CPL_H_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_INT_FLOW_CTL_DP0_TOO_CPL_D 15:7 /* RWIUF */
#define NV_BR04_XVU_INT_FLOW_CTL_DP0_TOO_CPL_D_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_INT_FLOW_CTL_UP0_TOO_NP(i) (0x000004F4+(i)*16) /* RW-4A */
#define NV_BR04_XVU_INT_FLOW_CTL_UP0_TOO_PW(i) (0x000004F8+(i)*16) /* RW-4A */
#define NV_BR04_XVU_HGPU_CTRL 0x00000980 /* RW-4R */
#define NV_BR04_XVU_HGPU_CTRL_EN 0:0 /* RWIVF */
#define NV_BR04_XVU_HGPU_CTRL_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_BR04_XVU_HGPU_CTRL_EN_ENABLED 0x00000001 /* RW--V */
#define NV_BR04_XVU_HGPU_PEER_FB_LOWER_BASE 0x00000990 /* RW-4R */
#define NV_BR04_XVU_HGPU_PEER_FB_UPPER_BASE 0x00000994 /* RW-4R */
#define NV_BR04_XVU_ITX_ALLOCATION 0x000005B0 /* RW-4R */
#define NV_BR04_XVU_ITX_ALLOCATION_DP0 3:0 /* RWIUF */
#define NV_BR04_XVU_ITX_ALLOCATION_DP0_INIT 0x00000001 /* RWI-V */
#define NV_BR04_XVU_ITX_ALLOCATION_DP1 7:4 /* RWIUF */
#define NV_BR04_XVU_ITX_ALLOCATION_DP1_INIT 0x00000001 /* RWI-V */
#define NV_BR04_XVU_ITX_ALLOCATION_DP2 11:8 /* RWIUF */
#define NV_BR04_XVU_ITX_ALLOCATION_DP2_INIT 0x00000001 /* RWI-V */
#define NV_BR04_XVU_ITX_ALLOCATION_DP3 15:12 /* RWIUF */
#define NV_BR04_XVU_ITX_ALLOCATION_DP3_INIT 0x00000001 /* RWI-V */
#define NV_BR04_XVU_ITX_ALLOCATION_UP0 19:16 /* RWIUF */
#define NV_BR04_XVU_ITX_ALLOCATION_UP0_INIT 0x00000001 /* RWI-V */
#define NV_BR04_XVU_ITX_ALLOCATION_MH0 23:20 /* RWIUF */
#define NV_BR04_XVU_ITX_ALLOCATION_MH0_INIT 0x00000001 /* RWI-V */
#define NV_BR04_XVU_MCC_REG_ALIAS 0x00000600 /* RW-4R */
#define NV_BR04_XVU_MCC_REG_ALIAS_DONOR_BUS 7:0 /* RWIUF */
#define NV_BR04_XVU_MCC_REG_ALIAS_DONOR_BUS_INIT 0x00000000 /* R-I-V */
#define NV_BR04_XVU_MCC_REG_ALIAS_ACCESS 8:8 /* RWIVF */
#define NV_BR04_XVU_MCC_REG_ALIAS_ACCESS_DISABLED 0x00000000 /* RW--V */
#define NV_BR04_XVU_MCC_REG_ALIAS_ACCESS_ENABLED 0x00000001 /* RWI-V */
#define NV_BR04_XVU_MCC_REG_ALIAS_ADDR_SELECT 9:9 /* RWIVF */
#define NV_BR04_XVU_MCC_REG_ALIAS_ADDR_SELECT_AUTO 0x00000000 /* RWI-V */
#define NV_BR04_XVU_MCC_REG_ALIAS_ADDR_SELECT_MANUAL 0x00000001 /* RW--V */
#define NV_BR04_XVU_MCC_REG_OFFSET 0x00000604 /* RW-4R */
#define NV_BR04_XVU_BAR_0 0x00000010 /* RW-4R */
#define NV_BR04_XVU_DEV_CTRLSTAT 0x00000068 /* RW-4R */
#define NV_BR04_XVU_DEV_CTRLSTAT_CORR_ERR_RPT_EN 0:0 /* RWIVF */
#define NV_BR04_XVU_DEV_CTRLSTAT_CORR_ERR_RPT_EN_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_LINK_CTRLSTAT 0x00000070 /* RW-4R */
#define NV_BR04_XVU_LINK_CTRLSTAT_ASPM_CTRL 1:0 /* RWIVF */
#define NV_BR04_XVU_LINK_CTRLSTAT_ASPM_CTRL_DISABLED 0x00000000 /* RWI-V */
#define NV_BR04_XVU_LINK_CTRLSTAT_ASPM_CTRL_L0S 0x00000001 /* RW--V */
#define NV_BR04_XVU_LINK_CTRLSTAT_ASPM_CTRL_L1 0x00000002 /* RW--V */
#define NV_BR04_XVU_LINK_CTRLSTAT_ASPM_CTRL_L0S_L1 0x00000003 /* RW--V */
#define NV_BR04_XVU_LINK_CTRLSTAT_LINK_SPEED 19:16 /* R--VF */
#define NV_BR04_XVU_LINK_CTRLSTAT_LINK_SPEED_2P5G 0x00000001 /* R---V */
#define NV_BR04_XVU_LINK_CTRLSTAT_LINK_SPEED_5P0G 0x00000002 /* R---V */
#define NV_BR04_XVU_LINK_CTRLSTAT2 0x00000090 /* RW-4R */
#define NV_BR04_XVU_LINK_CTRLSTAT2_TARGET_LINK_SPEED 3:0 /* RWIVF */
#define NV_BR04_XVU_LINK_CTRLSTAT2_TARGET_LINK_SPEED_2P5G 0x00000001 /* RW--V */
#define NV_BR04_XVU_LINK_CTRLSTAT2_TARGET_LINK_SPEED_5P0G 0x00000002 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_0 0x00000C00 /* RW-4R */
#define NV_BR04_XVU_G2_PRIV_XP_0_REPLAY_TIMER_LIMIT 28:19 /* RWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_0_REPLAY_TIMER_LIMIT_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_0_OPPORTUNISTIC_ACK 29:29 /* RWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_0_OPPORTUNISTIC_ACK_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_0_OPPORTUNISTIC_UPDATE_FC 30:30 /* RWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_0_OPPORTUNISTIC_UPDATE_FC_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2 0x00000C44 /* RW-4R */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_SPEED_CHANGE 0:0 /* CWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_SPEED_CHANGE_ZERO 0x00000000 /* CWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_CYA_DEEMPHASIS_OVERRIDE 2:2 /* RWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_CYA_DEEMPHASIS_OVERRIDE_DISABLED 0x00000000 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_CYA_DEEMPHASIS_OVERRIDE_ENABLED 0x00000001 /* RW--V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_TARGET_LINK_SPEED 7:4 /* RWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_TARGET_LINK_SPEED_2P5 0x00000001 /* RW--V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_TARGET_LINK_SPEED_5P0 0x00000002 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED 11:8 /* RWIVF */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_2P5 0x00000001 /* RW--V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_5P0_2P5 0x00000002 /* RWI-V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE 15:12 /* R-IVF */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE_2P5 0x00000001 /* R-I-V */
#define NV_BR04_XVU_G2_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE_5P0_2P5 0x00000002 /* R---V */
#define NV_BR04_XVU_BOOT_1 0x00000204 /* R--4R */
#define NV_BR04_XVU_BOOT_1_LINK_SPEED 1:1 /* RWIVF */
#define NV_BR04_XVU_BOOT_1_LINK_SPEED_2500 0x00000000 /* RWI-V */
#define NV_BR04_XVU_BOOT_1_LINK_SPEED_5000 0x00000001 /* RW--V */
#define NV_BR04_XVU_CYA_BIT0 0x00000AB0 /* RW-4R */
#define NV_BR04_XVU_CYA_BIT0_RSVD_28 28:28 /* RWIVF */
#define NV_BR04_XVU_CYA_BIT0_RSVD_28_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_CYA_BIT0_RSVD_29 29:29 /* RWIVF */
#define NV_BR04_XVU_CYA_BIT0_RSVD_29_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_CYA_BIT0_RSVD_30 30:30 /* RWIVF */
#define NV_BR04_XVU_CYA_BIT0_RSVD_30_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_CYA_BIT0_RSVD_31 31:31 /* RWIVF */
#define NV_BR04_XVU_CYA_BIT0_RSVD_31_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_CYA_NIBBLE0 0x00000AB4 /* RW-4R */
#define NV_BR04_XVU_CYA_NIBBLE0_RSVD_0 3:0 /* RWIVF */
#define NV_BR04_XVU_CYA_NIBBLE0_RSVD_0_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_CYA_NIBBLE0_RSVD_4 19:16 /* RWIVF */
#define NV_BR04_XVU_CYA_NIBBLE0_RSVD_4_INIT 0x00000000 /* RWI-V */
#define NV_BR04_XVU_ROM_REVISION 0x00000B08 /* RW-4R */
#endif // DEV_BR04_XVU_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __v03_00_dev_disp_h__
#define __v03_00_dev_disp_h__
#define NV_PDISP_CHN_NUM_CORE 0 /* */
#define NV_PDISP_CHN_NUM_WIN(i) (1+(i)) /* */
#define NV_PDISP_CHN_NUM_WIN__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_WINIM(i) (33+(i)) /* */
#define NV_PDISP_CHN_NUM_WINIM__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_CURS(i) (73+(i)) /* */
#define NV_PDISP_CHN_NUM_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* R---V */
#define NV_PDISP_FE_SW 0x00640FFF:0x00640000 /* RW--D */
#define NV_PDISP_SF_USER_0 0x006F03FF:0x006F0000 /* RW--D */
#define NV_UDISP_HASH_BASE 0x00000000 /* */
#define NV_UDISP_HASH_LIMIT 0x00001FFF /* */
#define NV_UDISP_OBJ_MEM_BASE 0x00002000 /* */
#define NV_UDISP_OBJ_MEM_LIMIT 0x0000FFFF /* */
#define NV_UDISP_HASH_TBL_CLIENT_ID (1*32+13):(1*32+0) /* RWXVF */
#define NV_UDISP_HASH_TBL_INSTANCE (1*32+24):(1*32+14) /* RWXUF */
#define NV_UDISP_HASH_TBL_CHN (1*32+31):(1*32+25) /* RWXUF */
#define NV_DMA_TARGET_NODE (0*32+1):(0*32+0) /* RWXVF */
#define NV_DMA_TARGET_NODE_PHYSICAL_NVM 0x00000001 /* RW--V */
#define NV_DMA_TARGET_NODE_PHYSICAL_PCI 0x00000002 /* RW--V */
#define NV_DMA_TARGET_NODE_PHYSICAL_PCI_COHERENT 0x00000003 /* RW--V */
#define NV_DMA_ACCESS (0*32+2):(0*32+2) /* RWXVF */
#define NV_DMA_ACCESS_READ_ONLY 0x00000000 /* RW--V */
#define NV_DMA_ACCESS_READ_AND_WRITE 0x00000001 /* RW--V */
#define NV_DMA_KIND (0*32+20):(0*32+20) /* RWXVF */
#define NV_DMA_KIND_PITCH 0x00000000 /* RW--V */
#define NV_DMA_KIND_BLOCKLINEAR 0x00000001 /* RW--V */
#define NV_DMA_ADDRESS_BASE_LO (1*32+31):(1*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_BASE_HI (2*32+6):(2*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_LIMIT_LO (3*32+31):(3*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_LIMIT_HI (4*32+6):(4*32+0) /* RWXUF */
#define NV_DMA_SIZE 20 /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_CORE 0x00680000 /* */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_CORE (0x00680000+32768) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN(i) ((0x00690000+(i)*4096)) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM(i) ((0x00690000+((i+32)*4096))) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_CURS(i) (0x006D8000+(i)*4096) /* RW-4A */
#define NV_UDISP_FE_CHN_ASSY_BASEADR(i) ((i)>0?(((0x00690000+(i-1)*4096))):0x00680000) /* */
#define NV_UDISP_FE_CHN_ASSY_BASEADR__SIZE_1 81 /* */
#endif // __v03_00_dev_disp_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __v04_00_dev_disp_h__
#define __v04_00_dev_disp_h__
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING(i) (0x00611800+(i)*4) /* RW-4A */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_NOT_PENDING 0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_RESET 0x00000001 /* -W--V */
#define NV_PDISP_FE_RM_INTR_DISPATCH 0x00611EC0 /* R--4R */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_NOT_PENDING 0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_PENDING 0x00000001 /* R---V */
#define NV_PDISP_VGA_WORKSPACE_BASE 0x00625F04 /* RW-4R */
#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS 3:3 /* RWIVF */
#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_VALID 0x00000001 /* RW--V */
#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR 31:8 /* RWIVF */
#endif // __v04_00_dev_disp_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gk104_dev_timer_h__
#define __gk104_dev_timer_h__
#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */
#define NV_PTIMER_INTR_0_ALARM 0:0 /* RWXVF */
#define NV_PTIMER_INTR_0_ALARM_NOT_PENDING 0x00000000 /* R---V */
#define NV_PTIMER_INTR_0_ALARM_PENDING 0x00000001 /* R---V */
#define NV_PTIMER_INTR_0_ALARM_RESET 0x00000001 /* -W--V */
#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */
#define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* RWIVF */
#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* RWI-V */
#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* RW--V */
#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */
#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */
#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */
#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */
#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */
#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWXUF */
#endif // __gk104_dev_timer_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_boot_h__
#define __gm107_dev_boot_h__
#define NV_PMC 0x00000FFF:0x00000000 /* RW--D */
#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
#define NV_PMC_INTR(i) (0x00000100+(i)*4) /* RW-4A */
#define NV_PMC_INTR__SIZE_1 3 /* */
#define NV_PMC_INTR_DEVICE(i) (i):(i) /* */
#define NV_PMC_INTR_DEVICE__SIZE_1 31 /* */
#define NV_PMC_INTR_DEVICE_NOT_PENDING 0x00000000 /* */
#define NV_PMC_INTR_DEVICE_PENDING 0x00000001 /* */
#define NV_PMC_INTR_EN(i) (0x00000140+(i)*4) /* RW-4A */
#define NV_PMC_INTR_EN__SIZE_1 3 /* */
#define NV_PMC_INTR_0 0x00000100 /* */
#define NV_PMC_INTR_1 0x00000104 /* */
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_DEVICE(i) (i):(i) /* */
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#endif // __gm107_dev_boot_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_bus_h__
#define __gm107_dev_bus_h__
#define NV_PBUS_INTR_0 0x00001100 /* RW-4R */
#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 /* RWIVF */
#define NV_PBUS_INTR_0_PRI_SQUASH_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_PRI_SQUASH_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_PRI_SQUASH_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 /* RWIVF */
#define NV_PBUS_INTR_0_PRI_FECSERR_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_PRI_FECSERR_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_PRI_FECSERR_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 /* RWIVF */
#define NV_PBUS_INTR_0_PRI_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_PRI_TIMEOUT_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_PRI_TIMEOUT_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT 5:5 /* RWIVF */
#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_RESET 0x00000001 /* -W--C */
#define NV_PBUS_BAR0_WINDOW 0x00001700 /* RW-4R */
#define NV_PBUS_BAR0_WINDOW_BASE 23:0 /* RWIUF */
#define NV_PBUS_BAR0_WINDOW_BASE_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR0_WINDOW_TARGET 25:24 /* RWIUF */
#define NV_PBUS_BAR0_WINDOW_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR0_WINDOW_BASE_SHIFT 16 /* */
#define NV_PBUS_BAR2_BLOCK 0x00001714 /* RW-4R */
#define NV_PBUS_BAR2_BLOCK_MAP 29:0 /* RWXUF */
#define NV_PBUS_BAR2_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA 30:30 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_OFF 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_ON 0x00000000 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_INIT 0x00000001 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 /* */
#endif // __gm107_dev_bus_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_fb_h__
#define __gm107_dev_fb_h__
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR 0x00100C10 /* RW-4R */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_ADR_39_08 31:0 /* RWIVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x00100CB8 /* RW-4R */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_SYS_MEM 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR_ALIGNMENT 0x0000000c /* */
#define NV_PFB_PRI_MMU_INVALIDATE 0x00100CBC /* RW-4R */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY 2:2 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_TRUE 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 /* -WEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_FALSE 0x00000000 /* -WE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_TRUE 0x00000001 /* -W--T */
#endif // __gm107_dev_fb_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_flush_h__
#define __gm107_dev_flush_h__
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x00070004 /* RW-4R */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE 0x00070008 /* RW-4R */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS 0x0007000c /* RW-4R */
#define NV_UFLUSH_L2_FLUSH_DIRTY 0x00070010 /* RW-4R */
#define NV_UFLUSH_FB_FLUSH 0x00070000 /* RW-4R */
#endif // __gm107_dev_flush_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_mmu_h__
#define __gm107_dev_mmu_h__
#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */
#define NV_MMU_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */
#define NV_MMU_PDE_SIZE_FULL 0x00000000 /* RW--V */
#define NV_MMU_PDE_SIZE_HALF 0x00000001 /* RW--V */
#define NV_MMU_PDE_SIZE_QUARTER 0x00000002 /* RW--V */
#define NV_MMU_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */
#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */
#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */
#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */
#define NV_MMU_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_PDE__SIZE 8
#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */
#define NV_MMU_PTE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */
#define NV_MMU_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */
#define NV_MMU_PTE_READ_ONLY_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_READ_ONLY_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */
#define NV_MMU_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */
#define NV_MMU_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */
#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */
#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */
#define NV_MMU_PTE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PTE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */
#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PTE_LOCK (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_PTE_LOCK_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_LOCK_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) /* RWXVF */
#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) /* RWXVF */
#define NV_MMU_PTE_READ_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_READ_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) /* RWXVF */
#define NV_MMU_PTE_WRITE_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_WRITE_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_PTE__SIZE 8
#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */
#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe /* R---V */
#define NV_MMU_PTE_KIND_C32_2CRA 0xdb /* R---V */
#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 /* R---V */
#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 /* R---V */
#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 /* R---V */
#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 /* R---V */
#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 /* R---V */
#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee /* R---V */
#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef /* R---V */
#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 /* R---V */
#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 /* R---V */
#define NV_MMU_PTE_KIND_C128_2CR 0xf5 /* R---V */
#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 /* R---V */
#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 /* R---V */
#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb /* R---V */
#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb /* R---V */
#endif // __gm107_dev_mmu_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_nv_xve_h__
#define __gm107_dev_nv_xve_h__
#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */
#define NV_XVE_ID 0x00000000 /* R--4R */
#define NV_XVE_ID_VENDOR 15:0 /* C--VF */
#define NV_XVE_ID_VENDOR_NVIDIA 0x000010DE /* C---V */
#define NV_XVE_DEV_CTRL 0x00000004 /* RW-4R */
#define NV_XVE_DEV_CTRL_CMD_IO_SPACE 0:0 /* RWIVF */
#define NV_XVE_DEV_CTRL_CMD_IO_SPACE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_DEV_CTRL_CMD_IO_SPACE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_REV_ID 0x00000008 /* R--4R */
#define NV_XVE_REV_ID_CLASS_CODE 31:8 /* R-CVF */
#define NV_XVE_REV_ID_CLASS_CODE_3D 0x00030200 /* ----V */
#define NV_XVE_SUBSYSTEM 0x0000002C /* R--4R */
#define NV_XVE_MSI_CTRL 0x00000068 /* RW-4R */
#define NV_XVE_MSI_CTRL_MSI 16:16 /* RWIVF */
#define NV_XVE_MSI_CTRL_MSI_DISABLE 0x00000000 /* RWI-V */
#define NV_XVE_MSI_CTRL_MSI_ENABLE 0x00000001 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS 0x00000080 /* RWI4R */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE 0:0 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE 1:1 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE 2:2 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE 3:3 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING 4:4 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT 0x00000001 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE 7:5 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_128B 0x00000000 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_256B 0x00000001 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_512B 0x00000002 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_1024B 0x00000003 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_2048B 0x00000004 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_4096B 0x00000005 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:8 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT 0x00000001 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE 9:9 /* R-IVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE 10:10 /* R-IVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP 11:11 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP_INIT 0x00000001 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE 14:12 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE_INIT 0x00000002 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_RSVD 15:15 /* C--VF */
#define NV_XVE_DEVICE_CONTROL_STATUS_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED 16:16 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED 17:17 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED 18:18 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED 19:19 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED 20:20 /* R-IVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING 21:21 /* R-IVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING_INIT 0x00000000 /* R-I-V */
#define NV_XVE_LINK_CAPABILITIES 0x00000084 /* R--4R */
#define NV_XVE_LINK_CONTROL_STATUS 0x00000088 /* RWI4R */
#define NV_XVE_VCCAP_HDR 0x00000100 /* R--4R */
#define NV_XVE_VCCAP_HDR_ID 15:0 /* C--VF */
#define NV_XVE_VCCAP_HDR_ID_VC 0x00000002 /* C---V */
#define NV_XVE_VCCAP_HDR_VER 19:16 /* C--VF */
#define NV_XVE_VCCAP_HDR_VER_1 0x00000001 /* C---V */
#define NV_XVE_VCCAP_CTRL0 0x00000114 /* RW-4R */
#define NV_XVE_VCCAP_CTRL0_MAP 7:1 /* RWIVF */
#define NV_XVE_AER_UNCORR_ERR 0x00000424 /* RWC4R */
#define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR 4:4 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_POISONED_TLP 12:12 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT 14:14 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL 16:16 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP 18:18 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ 20:20 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR 0x00000430 /* RW-4R */
#define NV_XVE_AER_CORR_ERR_RCV_ERR 0:0 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_RCV_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_RCV_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_RCV_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_BAD_TLP 6:6 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_BAD_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_BAD_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_BAD_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_BAD_DLLP 7:7 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_BAD_DLLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_BAD_DLLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_BAD_DLLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER 8:8 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT 12:12 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL 13:13 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_CYA_2 0x00000704 /* RW-4R */
#endif // __gm107_dev_nv_xve_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_nv_xve1_h__
#define __gm107_dev_nv_xve1_h__
#define NV_PCFG1 0x0008AFFF:0x0008A000 /* RW--D */
#endif // __gm107_dev_nv_xve1_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_ram_h__
#define __gm107_dev_ram_h__
#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */
#define NV_PRAMIN_DATA032(i) (0x00700000+(i)*4) /* RW-4A */
#define NV_PRAMIN_DATA032__SIZE_1 524288 /* */
#define NV_PRAMIN_DATA032_VALUE 31:0 /* RWXUF */
#define NV_PRAMIN_DATA016(i) (0x00700000+((i)/3)*4+((i)%3)) /* RW-2A */
#define NV_PRAMIN_DATA016__SIZE_1 1572864 /* */
#define NV_PRAMIN_DATA016_VALUE 15:0 /* RWXUF */
#define NV_PRAMIN_DATA008(i) (0x00700000+(i)) /* RW-1A */
#define NV_PRAMIN_DATA008__SIZE_1 2097152 /* */
#define NV_PRAMIN_DATA008_VALUE 7:0 /* RWXUF */
#define NV_RAMIN_BASE_SHIFT 12 /* */
#define NV_RAMIN_ALLOC_SIZE 4096 /* */
#define NV_RAMIN_RAMFC (127*32+31):(0*32+0) /* RWXUF */
#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) /* RWXUF */
#define NV_RAMUSERD_GET (17*32+31):(17*32+0) /* RWXUF */
#define NV_RAMUSERD_REF (18*32+31):(18*32+0) /* RWXUF */
#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) /* RWXUF */
#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) /* */
#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) /* RWXUF */
#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) /* RWXUF */
#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) /* RWXUF */
#define NV_RAMUSERD_GP_GET (34*32+31):(34*32+0) /* RWXUF */
#define NV_RAMUSERD_GP_PUT (35*32+31):(35*32+0) /* RWXUF */
#define NV_RAMUSERD_BASE_SHIFT 9 /* */
#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) /* RWXUF */
#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) /* RWXUF */
#define NV_RAMRL_BASE_SHIFT 12 /* */
#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 0x00000003 /* RWI-V */
#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x00000080 /* RWI-V */
#define NV_RAMRL_ENTRY_SIZE 8 /* */
#define NV_RAMRL_ENTRY_TSG_LENGTH_MAX 0x00000020 /* RW--V */
#endif // __gm107_dev_ram_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm107_dev_timer_h__
#define __gm107_dev_timer_h__
#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */
#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */
#define NV_PTIMER_TIMER_CFG0 0x00009300 /* RW-4R */
#define NV_PTIMER_TIMER_CFG0_DEN 4:0 /* RWIUF */
#define NV_PTIMER_TIMER_CFG0_DEN_108MHZ_REF 0x1b /* RWI-V */
#define NV_PTIMER_TIMER_CFG0_NUM 18:16 /* RWIUF */
#define NV_PTIMER_TIMER_CFG0_NUM_108MHZ_REF 0x7 /* RWI-V */
#define NV_PTIMER_TIMER_CFG1 0x00009304 /* RW-4R */
#define NV_PTIMER_TIMER_CFG1_INTEGER 5:0 /* RWIUF */
#define NV_PTIMER_TIMER_CFG1_INTEGER_108MHZ_REF 0x000009 /* RWI-V */
#define NV_PTIMER_GR_TICK_FREQ 0x00009480 /* RW-4R */
#define NV_PTIMER_GR_TICK_FREQ_SELECT 2:0 /* RWIUF */
#define NV_PTIMER_GR_TICK_FREQ_SELECT_MAX 0x00000000 /* RW--V */
#define NV_PTIMER_GR_TICK_FREQ_SELECT_DEFAULT 0x00000005 /* RWI-V */
#define NV_PTIMER_GR_TICK_FREQ_SELECT_MIN 0x00000007 /* RW--V */
#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */
#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */
#endif // __gm107_dev_timer_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_flush_h__
#define __gm200_dev_flush_h__
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x00070004 /* RW-4R */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE 0x00070008 /* RW-4R */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS 0x0007000c /* RW-4R */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_UFLUSH_L2_FLUSH_DIRTY 0x00070010 /* RW-4R */
#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING_TRUE 0x00000001 /* R---V */
#endif // __gm200_dev_flush_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_nv_p2p_h__
#define __gm200_dev_nv_p2p_h__
#define NV_P2P 0x0013AFFF:0x00139000 /* RW--D */
#define NV_P2P_WMBOX_ADDR_ADDR 18:1 /* RWIUF */
#define NV_P2P_WREQMB_L(i) (0x00139068+(i)*64) /* R--4A */
#define NV_P2P_WREQMB_L__SIZE_1 8 /* */
#define NV_P2P_WREQMB_L_PAGE_ADDR 20:0 /* R-IUF */
#define NV_P2P_WREQMB_L_PAGE_ADDR_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WREQMB_H(i) (0x0013906c+(i)*64) /* R--4A */
#define NV_P2P_WREQMB_H__SIZE_1 8 /* */
#define NV_P2P_WREQMB_H_KIND 7:0 /* R-IUF */
#define NV_P2P_WREQMB_H_KIND_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WREQMB_H_COMPTAGLINE 24:8 /* R-IUF */
#define NV_P2P_WREQMB_H_COMPTAGLINE_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WREQMB_H_PAGE_SIZE 25:25 /* R-IUF */
#define NV_P2P_WREQMB_H_PAGE_SIZE_INIT 0x00000000 /* R-I-V */
#endif // __gm200_dev_nv_p2p_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gm200_dev_timer_h__
#define __gm200_dev_timer_h__
#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */
#define NV_PTIMER_INTR_0_TIMER 1:1 /* RWXVF */
#define NV_PTIMER_INTR_0_TIMER_NOT_PENDING 0x00000000 /* R---V */
#define NV_PTIMER_INTR_0_TIMER_PENDING 0x00000001 /* R---V */
#define NV_PTIMER_INTR_0_TIMER_RESET 0x00000001 /* -W--C */
#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */
#define NV_PTIMER_INTR_EN_0_TIMER 1:1 /* RWIVF */
#define NV_PTIMER_INTR_EN_0_TIMER_DISABLED 0x00000000 /* RWI-V */
#define NV_PTIMER_INTR_EN_0_TIMER_ENABLED 0x00000001 /* RW--V */
#define NV_PTIMER_TIMER_0 0x00009428 /* RW-4R */
#endif // __gm200_dev_timer_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NV_ARCH_PUBLISHED_H
#define NV_ARCH_PUBLISHED_H
// high byte indicates GPU-SERIES, as defined in Gpus.pm.
#define NVGPU_ARCHITECTURE_SERIES 31:24
#define NVGPU_ARCHITECTURE_SERIES_CLASSIC 0x00
#define NVGPU_ARCHITECTURE_SERIES_SIMULATION 0x00 // XXX - really should be distinct from CLASSIC_GPUS
#define NVGPU_ARCHITECTURE_SERIES_TEGRA 0xE0
#define NVGPU_ARCHITECTURE_ARCH 23:0
#define GPU_ARCHITECTURE(series, arch) (DRF_DEF(GPU, _ARCHITECTURE, _SERIES, series) | \
DRF_NUM(GPU, _ARCHITECTURE, _ARCH, arch))
//
// Architecture constants.
//
#define GPU_ARCHITECTURE_MAXWELL GPU_ARCHITECTURE(_CLASSIC, 0x0110)
#define GPU_ARCHITECTURE_MAXWELL2 GPU_ARCHITECTURE(_CLASSIC, 0x0120)
#define GPU_ARCHITECTURE_PASCAL GPU_ARCHITECTURE(_CLASSIC, 0x0130)
#define GPU_ARCHITECTURE_VOLTA GPU_ARCHITECTURE(_CLASSIC, 0x0140)
#define GPU_ARCHITECTURE_VOLTA2 GPU_ARCHITECTURE(_CLASSIC, 0x0150)
#define GPU_ARCHITECTURE_TURING GPU_ARCHITECTURE(_CLASSIC, 0x0160)
#define GPU_ARCHITECTURE_AMPERE GPU_ARCHITECTURE(_CLASSIC, 0x0170)
#define GPU_ARCHITECTURE_T12X GPU_ARCHITECTURE(_TEGRA, 0x0040)
#define GPU_ARCHITECTURE_T13X GPU_ARCHITECTURE(_TEGRA, 0x0013)
#define GPU_ARCHITECTURE_T21X GPU_ARCHITECTURE(_TEGRA, 0x0021)
#define GPU_ARCHITECTURE_T18X GPU_ARCHITECTURE(_TEGRA, 0x0018)
#define GPU_ARCHITECTURE_T19X GPU_ARCHITECTURE(_TEGRA, 0x0019)
#define GPU_ARCHITECTURE_T23X GPU_ARCHITECTURE(_TEGRA, 0x0023)
#define GPU_ARCHITECTURE_SIMS GPU_ARCHITECTURE(_SIMULATION, 0x01f0) // eg: AMODEL
//
// Implementation constants.
// These must be unique within a single architecture.
//
#define GPU_IMPLEMENTATION_GM108 0x08
#define GPU_IMPLEMENTATION_GM107 0x07
#define GPU_IMPLEMENTATION_GM200 0x00
#define GPU_IMPLEMENTATION_GM204 0x04
#define GPU_IMPLEMENTATION_GM206 0x06
#define GPU_IMPLEMENTATION_GP100 0x00
#define GPU_IMPLEMENTATION_GP102 0x02
#define GPU_IMPLEMENTATION_GP104 0x04
#define GPU_IMPLEMENTATION_GP106 0x06
#define GPU_IMPLEMENTATION_GP107 0x07
#define GPU_IMPLEMENTATION_GP108 0x08
#define GPU_IMPLEMENTATION_GV100 0x00
#define GPU_IMPLEMENTATION_GV11B 0x0B
#define GPU_IMPLEMENTATION_TU102 0x02
#define GPU_IMPLEMENTATION_TU104 0x04
#define GPU_IMPLEMENTATION_TU106 0x06
#define GPU_IMPLEMENTATION_TU116 0x08 // TU116 has implementation ID 8 in HW
#define GPU_IMPLEMENTATION_TU117 0x07
#define GPU_IMPLEMENTATION_GA100 0x00
#define GPU_IMPLEMENTATION_GA102 0x02
#define GPU_IMPLEMENTATION_GA103 0x03
#define GPU_IMPLEMENTATION_GA104 0x04
#define GPU_IMPLEMENTATION_GA106 0x06
#define GPU_IMPLEMENTATION_GA107 0x07
#define GPU_IMPLEMENTATION_GA102F 0x0F
#define GPU_IMPLEMENTATION_T124 0x00
#define GPU_IMPLEMENTATION_T132 0x00
#define GPU_IMPLEMENTATION_T210 0x00
#define GPU_IMPLEMENTATION_T186 0x00
#define GPU_IMPLEMENTATION_T194 0x00
#define GPU_IMPLEMENTATION_T234 0x04
#define GPU_IMPLEMENTATION_T234D 0x05
/* SIMS gpus */
#define GPU_IMPLEMENTATION_AMODEL 0x00
#endif // NV_ARCH_PUBLISHED_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
//
/***************************************************************************\
* *
* Hardware Reference Manual extracted defines. *
* - Defines in this file are approved by the HW team for publishing. *
* *
\***************************************************************************/
#ifndef NV_REF_PUBLISHED_H
#define NV_REF_PUBLISHED_H
//
// These registers can be accessed by chip-independent code as
// well as chip-dependent code.
//
// NOTE: DO NOT ADD TO THIS FILE. CREATE CHIP SPECIFIC HAL ROUTINES INSTEAD.
//
/*
* Standard PCI config space header defines.
* The defines here cannot change across generations.
*/
/* dev_nv_xve.ref */
/* PBUS field defines converted to NV_CONFIG field defines */
#define NV_CONFIG_PCI_NV_0 0x00000000 /* R--4R */
#define NV_CONFIG_PCI_NV_0_VENDOR_ID 15:0 /* C--UF */
#define NV_CONFIG_PCI_NV_0_VENDOR_ID_NVIDIA 0x000010DE /* C---V */
#define NV_CONFIG_PCI_NV_0_DEVICE_ID 31:16 /* R--UF */
#define NV_CONFIG_PCI_NV_1 0x00000004 /* RW-4R */
#define NV_CONFIG_PCI_NV_1_IO_SPACE 0:0 /* RWIVF */
#define NV_CONFIG_PCI_NV_1_IO_SPACE_DISABLED 0x00000000 /* RWI-V */
#define NV_CONFIG_PCI_NV_1_IO_SPACE_ENABLED 0x00000001 /* RW--V */
#define NV_CONFIG_PCI_NV_1_MEMORY_SPACE 1:1 /* RWIVF */
#define NV_CONFIG_PCI_NV_1_MEMORY_SPACE_DISABLED 0x00000000 /* RWI-V */
#define NV_CONFIG_PCI_NV_1_MEMORY_SPACE_ENABLED 0x00000001 /* RW--V */
#define NV_CONFIG_PCI_NV_1_BUS_MASTER 2:2 /* RWIVF */
#define NV_CONFIG_PCI_NV_1_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */
#define NV_CONFIG_PCI_NV_1_BUS_MASTER_ENABLED 0x00000001 /* RW--V */
#define NV_CONFIG_PCI_NV_2 0x00000008 /* R--4R */
#define NV_CONFIG_PCI_NV_2_REVISION_ID 7:0 /* C--UF */
#define NV_CONFIG_PCI_NV_2_CLASS_CODE 31:8 /* C--VF */
#define NV_CONFIG_PCI_NV_3 0x0000000C /* RW-4R */
#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER 15:11 /* RWIUF */
#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER_0_CLOCKS 0x00000000 /* RWI-V */
#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER_8_CLOCKS 0x00000001 /* RW--V */
#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER_240_CLOCKS 0x0000001E /* RW--V */
#define NV_CONFIG_PCI_NV_3_LATENCY_TIMER_248_CLOCKS 0x0000001F /* RW--V */
#define NV_CONFIG_PCI_NV_4 0x00000010 /* RW-4R */
#define NV_CONFIG_PCI_NV_5 0x00000014 /* RW-4R */
#define NV_CONFIG_PCI_NV_5_ADDRESS_TYPE 2:1 /* C--VF */
#define NV_CONFIG_PCI_NV_5_ADDRESS_TYPE_64_BIT 0x00000002 /* ----V */
#define NV_CONFIG_PCI_NV_6 0x00000018 /* RW-4R */
#define NV_CONFIG_PCI_NV_7(i) (0x0000001C+(i)*4) /* R--4A */
#define NV_CONFIG_PCI_NV_11 0x0000002C /* R--4R */
#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_VENDOR_ID 15:0 /* R--UF */
#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_VENDOR_ID_NONE 0x00000000 /* R---V */
#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_ID 31:16 /* R--UF */
#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_ID_NONE 0x00000000 /* R---V */
#define NV_CONFIG_PCI_NV_11_SUBSYSTEM_ID_TNT2PRO 0x0000001f
#define NV_CONFIG_PCI_NV_12 0x00000030 /* RW-4R */
#define NV_CONFIG_PCI_NV_13 0x00000034 /* RW-4R */
#define NV_CONFIG_PCI_NV_13_CAP_PTR 7:0 /* C--VF */
#define NV_CONFIG_PCI_NV_14 0x00000038 /* R--4R */
#define NV_CONFIG_PCI_NV_15 0x0000003C /* RW-4R */
#define NV_CONFIG_PCI_NV_15_INTR_LINE 7:0 /* RWIVF */
/*
* These defines are the correct fields to be used to extract the
* NEXT_PTR and CAP_ID from any PCI capability structure,
* but they still have NV_24 in the name because they were from the
* first PCI capability structure in the capability list in older GPUs.
*/
#define NV_CONFIG_PCI_NV_24_NEXT_PTR 15:8 /* R--VF */
#define NV_CONFIG_PCI_NV_24_CAP_ID 7:0 /* C--VF */
/*
* Standard registers present on NVIDIA chips used to ID the chip.
* Very stable across generations.
*/
/* dev_master.ref */
#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* R--VF */
#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* R--VF */
#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 /* R--VF */
#define NV_PMC_BOOT_0_IMPLEMENTATION_0 0x00000000 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_4 0x00000004 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_5 0x00000005 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_6 0x00000006 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_7 0x00000007 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_8 0x00000008 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_9 0x00000009 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_A 0x0000000A /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0x0000000B /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_C 0x0000000C /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_D 0x0000000D /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_E 0x0000000E /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_F 0x0000000F /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 /* R--VF */
#define NV_PMC_BOOT_0_ARCHITECTURE_TU100 0x00000016 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_TU110 0x00000016 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 0x00000017 /* R---V */
#define NV_PMC_BOOT_1 0x00000004 /* R--4R */
#define NV_PMC_BOOT_1_VGPU8 8:8 /* R--VF */
#define NV_PMC_BOOT_1_VGPU8_REAL 0x00000000 /* R-I-V */
#define NV_PMC_BOOT_1_VGPU8_VIRTUAL 0x00000001 /* R---V */
#define NV_PMC_BOOT_1_VGPU16 16:16 /* R--VF */
#define NV_PMC_BOOT_1_VGPU16_REAL 0x00000000 /* R-I-V */
#define NV_PMC_BOOT_1_VGPU16_VIRTUAL 0x00000001 /* R---V */
#define NV_PMC_BOOT_1_VGPU 17:16 /* C--VF */
#define NV_PMC_BOOT_1_VGPU_REAL 0x00000000 /* C---V */
#define NV_PMC_BOOT_1_VGPU_PV 0x00000001 /* ----V */
#define NV_PMC_BOOT_1_VGPU_VF 0x00000002 /* ----V */
#define NV_PMC_BOOT_42 0x00000A00 /* R--4R */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION 11:8 /* R-XVF */
#define NV_PMC_BOOT_42_MINOR_REVISION 15:12 /* R-XVF */
#define NV_PMC_BOOT_42_MAJOR_REVISION 19:16 /* R-XVF */
#define NV_PMC_BOOT_42_IMPLEMENTATION 23:20 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE 28:24 /* */
#define NV_PMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */
/* dev_arapb_misc.h */
#define NV_PAPB_MISC_GP_HIDREV_CHIPID 15:8 /* ----F */
#define NV_PAPB_MISC_GP_HIDREV_MAJORREV 7:4 /* ----F */
#endif // NV_REF_PUBLISHED_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_egress_ip_h__
#define __lr10_dev_egress_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_EGRESS_ERR_LOG_EN_0 0x00004404 /* RW-4R */
#define NV_EGRESS_ERR_LOG_EN_0_EGRESSBUFERR 0:0 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_EGRESSBUFERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_PKTROUTEERR 1:1 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_PKTROUTEERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_SEQIDERR 2:2 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_SEQIDERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOCCREDITOVFL__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR 10:10 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR 11:11 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR 12:12 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */
#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_LOG_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0 0x00004410 /* RW-4R */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_EGRESSBUFERR 0:0 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_EGRESSBUFERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PKTROUTEERR 1:1 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PKTROUTEERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_SEQIDERR 2:2 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_SEQIDERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOCCREDITOVFL__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_URRSPERR 10:10 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_URRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PRIVRSPERR 11:11 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PRIVRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_HWRSPERR 12:12 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_HWRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CORRECTABLE_REPORT_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_TIMESTAMP_LOG 0x00004450 /* R--4R */
#define NV_EGRESS_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-IVF */
#define NV_EGRESS_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_ERR_HEADER_LOG_VALID 0x0000444c /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0 0:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0_INVALID 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0_VALID 0x00000001 /* R---V */
#define NV_EGRESS_ERR_MISC_LOG_0 0x00004454 /* R--4R */
#define NV_EGRESS_ERR_MISC_LOG_0_SPORT 5:0 /* R-IVF */
#define NV_EGRESS_ERR_MISC_LOG_0_SPORT_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_ERR_MISC_LOG_0_ENCODEDVC 10:8 /* R-IVF */
#define NV_EGRESS_ERR_MISC_LOG_0_ENCODEDVC_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_ERR_HEADER_LOG_0 0x00004420 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_0_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_0_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_1 0x00004424 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_1_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_1_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_2 0x00004428 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_2_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_2_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_3 0x0000442c /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_3_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_3_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_4 0x00004430 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_4_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_4_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_5 0x00004434 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_5_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_5_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_6 0x00004438 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_6_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_6_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_7 0x0000443c /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_7_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_7_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_8 0x00004440 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_8_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_8_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_9 0x00004444 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_9_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_9_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_HEADER_LOG_10 0x00004448 /* R--4R */
#define NV_EGRESS_ERR_HEADER_LOG_10_DW 31:0 /* R-DVF */
#define NV_EGRESS_ERR_HEADER_LOG_10_DW_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS 0x00004494 /* R--4R */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_ERROR_ADDRESS 7:0 /* R-DVF */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_FIRST_0 0x0000441c /* RW-4R */
#define NV_EGRESS_ERR_FIRST_0_EGRESSBUFERR 0:0 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_EGRESSBUFERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_EGRESSBUFERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_PKTROUTEERR 1:1 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_PKTROUTEERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_PKTROUTEERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_SEQIDERR 2:2 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_SEQIDERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_SEQIDERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_RAM_OUT_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_NCISOCCREDITOVFL 7:7 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_NCISOCCREDITOVFL_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_NCISOCCREDITOVFL_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_REQTGTIDMISMATCHERR 8:8 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_REQTGTIDMISMATCHERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_REQTGTIDMISMATCHERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_RSPREQIDMISMATCHERR 9:9 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_RSPREQIDMISMATCHERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_RSPREQIDMISMATCHERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_URRSPERR 10:10 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_URRSPERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_URRSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_PRIVRSPERR 11:11 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_PRIVRSPERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_PRIVRSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_HWRSPERR 12:12 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_HWRSPERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_HWRSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_HDR_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_NCISOC_CREDIT_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_NCISOC_CREDIT_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_FLITTYPE_MISMATCH_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_NXBAR_FLITTYPE_MISMATCH_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FIRST_0_CREDIT_TIME_OUT_ERR 16:16 /* RWDVF */
#define NV_EGRESS_ERR_FIRST_0_CREDIT_TIME_OUT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_FIRST_0_CREDIT_TIME_OUT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0 0x00004414 /* RW-4R */
#define NV_EGRESS_ERR_CONTAIN_EN_0_EGRESSBUFERR 0:0 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_EGRESSBUFERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PKTROUTEERR 1:1 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PKTROUTEERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_SEQIDERR 2:2 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_SEQIDERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOCCREDITOVFL__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR 10:10 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PRIVRSPERR 11:11 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PRIVRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR 12:12 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */
#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_CONTAIN_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_BUFFER_POINTERS0 0x00004310 /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS0_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS0_WRITE_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS0_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS0_READ_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS1 0x00004314 /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS1_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS1_WRITE_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS1_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS1_READ_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS2 0x00004318 /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS2_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS2_WRITE_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS2_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS2_READ_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS3 0x0000431c /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS3_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS3_WRITE_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS3_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS3_READ_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS4 0x00004320 /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS4_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS4_WRITE_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS4_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS4_READ_INIT 0x00000000 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS5 0x00004324 /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS5_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS5_WRITE_INIT 0x00000040 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS5_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS5_READ_INIT 0x00000040 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS6 0x00004328 /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS6_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS6_WRITE_INIT 0x00000080 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS6_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS6_READ_INIT 0x00000080 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS7 0x0000432c /* R--4R */
#define NV_EGRESS_BUFFER_POINTERS7_WRITE 7:0 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS7_WRITE_INIT 0x000000c0 /* R-E-V */
#define NV_EGRESS_BUFFER_POINTERS7_READ 23:16 /* R-EVF */
#define NV_EGRESS_BUFFER_POINTERS7_READ_INIT 0x000000c0 /* R-E-V */
#define NV_EGRESS_ERR_STATUS_0 0x00004400 /* RW-4R */
#define NV_EGRESS_ERR_STATUS_0_EGRESSBUFERR 0:0 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_EGRESSBUFERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_EGRESSBUFERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_PKTROUTEERR 1:1 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_PKTROUTEERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_PKTROUTEERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_SEQIDERR 2:2 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_SEQIDERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_SEQIDERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_RAM_OUT_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_NCISOCCREDITOVFL 7:7 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_NCISOCCREDITOVFL_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_NCISOCCREDITOVFL_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_REQTGTIDMISMATCHERR 8:8 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_REQTGTIDMISMATCHERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_REQTGTIDMISMATCHERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_RSPREQIDMISMATCHERR 9:9 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_RSPREQIDMISMATCHERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_RSPREQIDMISMATCHERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_URRSPERR 10:10 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_URRSPERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_URRSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_PRIVRSPERR 11:11 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_PRIVRSPERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_PRIVRSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_HWRSPERR 12:12 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_HWRSPERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_HWRSPERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_HDR_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_NCISOC_CREDIT_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_NCISOC_CREDIT_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_FLITTYPE_MISMATCH_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_NXBAR_FLITTYPE_MISMATCH_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_STATUS_0_CREDIT_TIME_OUT_ERR 16:16 /* RWDVF */
#define NV_EGRESS_ERR_STATUS_0_CREDIT_TIME_OUT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_STATUS_0_CREDIT_TIME_OUT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_EGRESS_NCISOC_CREDIT0 0x00004370 /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT0_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT0_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT1 0x00004374 /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT1_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT1_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT2 0x00004378 /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT2_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT2_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT3 0x0000437c /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT3_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT3_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT4 0x00004380 /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT4_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT4_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT5 0x00004384 /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT5_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT5_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT6 0x00004388 /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT6_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT6_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_NCISOC_CREDIT7 0x0000438c /* R--4R */
#define NV_EGRESS_NCISOC_CREDIT7_NUM 9:0 /* R-IVF */
#define NV_EGRESS_NCISOC_CREDIT7_NUM_INIT 0x00000000 /* R-I-V */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER 0x00004480 /* RW-4R */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_LIMIT 0x00004484 /* RW-4R */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER 0x0000448c /* RW-4R */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_LIMIT 0x00004490 /* RW-4R */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_EGRESS_CTRL 0x00004040 /* RW-4R */
#define NV_EGRESS_CTRL_DESTINATIONIDCHECKENB 0:0 /* RWEVF */
#define NV_EGRESS_CTRL_DESTINATIONIDCHECKENB_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_CTRL_DESTINATIONIDCHECKENB_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_CTRL_DESTINATIONIDCHECKENB__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_CTRL_ZERO_OUT_SWXATTR_DISABLE 1:1 /* RWEVF */
#define NV_EGRESS_CTRL_ZERO_OUT_SWXATTR_DISABLE_OFF 0x00000000 /* RWE-V */
#define NV_EGRESS_CTRL_ZERO_OUT_SWXATTR_DISABLE_SET 0x00000001 /* RW--V */
#define NV_EGRESS_CTRL_CTO_ENB 9:9 /* RWEVF */
#define NV_EGRESS_CTRL_CTO_ENB_ON 0x00000001 /* RW--V */
#define NV_EGRESS_CTRL_CTO_ENB_OFF 0x00000000 /* RWE-V */
#define NV_EGRESS_CTRL_CTO_ENB__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_CTO_TIMER_LIMIT 0x00004048 /* RW-4R */
#define NV_EGRESS_CTO_TIMER_LIMIT_LIMIT 19:0 /* RWEVF */
#define NV_EGRESS_CTO_TIMER_LIMIT_LIMIT_INIT 0x000fffff /* RWE-V */
#define NV_EGRESS_CTO_TIMER_LIMIT_LIMIT__PROD 0x00004000 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0 0x00004408 /* RW-4R */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_EGRESSBUFERR 0:0 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_EGRESSBUFERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PKTROUTEERR 1:1 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PKTROUTEERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_SEQIDERR 2:2 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_SEQIDERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOCCREDITOVFL__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR 10:10 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PRIVRSPERR 11:11 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PRIVRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR 12:12 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0 0x0000440c /* RW-4R */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_EGRESSBUFERR 0:0 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_EGRESSBUFERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_EGRESSBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_EGRESSBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PKTROUTEERR 1:1 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PKTROUTEERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PKTROUTEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PKTROUTEERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_SEQIDERR 2:2 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_SEQIDERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_SEQIDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_SEQIDERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR 6:6 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RAM_OUT_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOCCREDITOVFL 7:7 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOCCREDITOVFL__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOCCREDITOVFL_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOCCREDITOVFL_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR 8:8 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_REQTGTIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR 9:9 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_RSPREQIDMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_URRSPERR 10:10 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_URRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_URRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_URRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR 11:11 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_PRIVRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_HWRSPERR 12:12 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_HWRSPERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_HWRSPERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_HWRSPERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR 13:13 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_HDR_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR 14:14 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_CREDIT_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR 15:15 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_NXBAR_FLITTYPE_MISMATCH_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR 16:16 /* RWEVF */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR__PROD 0x00000000 /* RW--V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_NON_FATAL_REPORT_EN_0_CREDIT_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL 0x00004470 /* RW-4R */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_ECC_ENABLE 0:0 /* RWEVF */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_PARITY_ENABLE 1:1 /* RWEVF */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_ECC_CTRL_NXBAR_PARITY_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_RAM_OUT_ECC_ENABLE 8:8 /* RWEVF */
#define NV_EGRESS_ERR_ECC_CTRL_RAM_OUT_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_RAM_OUT_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_ECC_CTRL_RAM_OUT_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE 9:9 /* RWEVF */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE 10:10 /* RWEVF */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_EGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID 0x00004498 /* R--4R */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_EGRESS_ERR_RAM_OUT_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#endif // __lr10_dev_egress_ip_h__

30
src/common/inc/swref/published/nvswitch/lr10/dev_ext_devices.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_ext_devices_h__
#define __lr10_dev_ext_devices_h__
/* This file is autogenerated. Do not edit */
#define NV_PROM_DATA(i) (0x00300000+(i)) /* RW-1A */
#define NV_PROM_DATA__SIZE_1 1048576 /* */
#define NV_PROM_DATA_VALUE 7:0 /* RW-VF */
#endif // __lr10_dev_ext_devices_h__

461
src/common/inc/swref/published/nvswitch/lr10/dev_falcon_v4.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_falcon_v4_h__
#define __lr10_dev_falcon_v4_h__
/* This file is autogenerated. Do not edit */
#define NV_PFALCON_FALCON_INTR_RETRIGGER(i) (0x000003e8+(i)*4) /* -W-4A */
#define NV_PFALCON_FALCON_INTR_RETRIGGER__SIZE_1 2 /* */
#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */
#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_HWCFG1 0x0000012c /* R--4R */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_INIT 0x00000006 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_1_0 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_2_0 0x00000002 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_3_0 0x00000003 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_4_0 0x00000004 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_5_0 0x00000005 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_6_0 0x00000006 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_7_0 0x00000007 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x00000003 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x00000002 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x00000003 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x00000002 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x00000003 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_IMEM_PORTS_INIT 0x00000001 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_PORTS_INIT 0x00000001 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_TAG_WIDTH_INIT 0x00000010 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00000010 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x00000001 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x00000001 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */
#define NV_PFALCON_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x00000001 /* R-I-V */
#define NV_PFALCON_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_IRQSSET 0x00000000 /* -W-4R */
#define NV_PFALCON_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_HALT 4:4 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_EXT 15:8 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_DMA 16:16 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_SHA 17:17 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_SHA_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_MEMERR 18:18 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_MEMERR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_FALCON 19:19 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_FALCON_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_RISCV 20:20 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_RISCV_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSSET_TRACE 21:21 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSSET_TRACE_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_TRACEPC 0x0000014c /* R--4R */
#define NV_PFALCON_FALCON_TRACEPC_PC 23:0 /* R--VF */
#define NV_PFALCON_FALCON_TRACEIDX 0x00000148 /* RW-4R */
#define NV_PFALCON_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */
#define NV_PFALCON_FALCON_TRACEIDX_CNT_INIT 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */
#define NV_PFALCON_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */
#define NV_PFALCON_FALCON_TRACEIDX_IDX_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQSCLR 0x00000004 /* -W-4R */
#define NV_PFALCON_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_EXT 15:8 /* */
#define NV_PFALCON_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_SHA 17:17 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_SHA_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_MEMERR 18:18 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_MEMERR_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_FALCON 19:19 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_FALCON_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_RISCV 20:20 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_RISCV_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IRQSCLR_TRACE 21:21 /* -WXVF */
#define NV_PFALCON_FALCON_IRQSCLR_TRACE_SET 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_IMEMT(i) (0x00000188+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMT__SIZE_1 4 /* */
#define NV_PFALCON_FALCON_IMEMT_TAG 15:0 /* RW-VF */
#define NV_PFALCON_FALCON_IMEMD(i) (0x00000184+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMD__SIZE_1 4 /* */
#define NV_PFALCON_FALCON_IMEMD_DATA 31:0 /* RW-VF */
#define NV_PFALCON_FALCON_IMEMC(i) (0x00000180+(i)*16) /* RW-4A */
#define NV_PFALCON_FALCON_IMEMC__SIZE_1 4 /* */
#define NV_PFALCON_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IMEMC_BLK 23:8 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_AINCR 25:25 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
#define NV_PFALCON_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */
#define NV_PFALCON_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */
#define NV_PFALCON_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */
#define NV_PFALCON_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_DMEMC(i) (0x000001c0+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMC__SIZE_1 8 /* */
#define NV_PFALCON_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_OFFS 7:2 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_BLK 23:8 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCR 25:25 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_VA 28:28 /* RWIVF */
#define NV_PFALCON_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMEMC_MISS 29:29 /* R-IVF */
#define NV_PFALCON_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */
#define NV_PFALCON_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */
#define NV_PFALCON_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */
#define NV_PFALCON_FALCON_DMEMD__SIZE_1 8 /* */
#define NV_PFALCON_FALCON_DMEMD_DATA 31:0 /* RW-VF */
#define NV_PFALCON_FALCON_DMACTL 0x0000010c /* RW-4R */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_DMACTL_DMAQ_NUM 6:3 /* R--VF */
#define NV_PFALCON_FALCON_DMACTL_SECURE_STAT 7:7 /* R--VF */
#define NV_PFALCON_FALCON_BOOTVEC 0x00000104 /* RW-4R */
#define NV_PFALCON_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_CPUCTL 0x00000100 /* RW-4R */
#define NV_PFALCON_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
#define NV_PFALCON_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */
#define NV_PFALCON_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS 0x00000130 /* -W-4R */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */
#define NV_PFALCON_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQSTAT 0x00000008 /* R--4R */
#define NV_PFALCON_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_EXT 15:8 /* */
#define NV_PFALCON_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_MEMERR 18:18 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_MEMERR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_MEMERR_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_FALCON 19:19 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_FALCON_TURE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_FALCON_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_RISCV 20:20 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_RISCV_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_RISCV_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQSTAT_TRACE 21:21 /* R-IVF */
#define NV_PFALCON_FALCON_IRQSTAT_TRACE_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQSTAT_TRACE_FALSE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */
#define NV_PFALCON_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_HALT 4:4 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_EXT 15:8 /* */
#define NV_PFALCON_FALCON_IRQMASK_DMA 16:16 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_SHA 17:17 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_SHA_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_SHA_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_MEMERR 18:18 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_MEMERR_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_MEMERR_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_FALCON 19:19 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_FALCON_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_FALCON_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_RISCV 20:20 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_RISCV_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_RISCV_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQMASK_TRACE 21:21 /* R-IVF */
#define NV_PFALCON_FALCON_IRQMASK_TRACE_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FALCON_IRQMASK_TRACE_DISABLE 0x00000000 /* R-I-V */
#define NV_PFALCON_FALCON_IRQDEST 0x0000001c /* RW-4R */
#define NV_PFALCON_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_HOST_EXT 15:8 /* */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXT 31:24 /* */
#define NV_PFALCON_FALCON_OS 0x00000080 /* RW-4R */
#define NV_PFALCON_FALCON_OS_VERSION 31:0 /* RWIVF */
#define NV_PFALCON_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */
#endif // __lr10_dev_falcon_v4_h__

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src/common/inc/swref/published/nvswitch/lr10/dev_ingress_ip.h Normal file
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@@ -0,0 +1,928 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_ingress_ip_h__
#define __lr10_dev_ingress_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_INGRESS_ERR_LOG_EN_0 0x00001404 /* RW-4R */
#define NV_INGRESS_ERR_LOG_EN_0_CMDDECODEERR 0:0 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_CMDDECODEERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL 3:3 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET 6:6 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTABCFGERR 8:8 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTABCFGERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTABCFGERR 9:9 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTABCFGERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR 17:17 /* RWEVF */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_LOG_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0 0x00001410 /* RW-4R */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_CMDDECODEERR 0:0 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_CMDDECODEERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQCONTEXTMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ACLFAIL 3:3 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ACLFAIL__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_INVALIDVCSET 6:6 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_INVALIDVCSET__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRBOUNDSERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTABCFGERR 8:8 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTABCFGERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTABCFGERR 9:9 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTABCFGERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRTYPEERR 17:17 /* RWEVF */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRTYPEERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CORRECTABLE_REPORT_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_TIMESTAMP_LOG 0x00001450 /* R--4R */
#define NV_INGRESS_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-IVF */
#define NV_INGRESS_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-I-V */
#define NV_INGRESS_ERR_HEADER_LOG_VALID 0x0000144c /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0 0:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0_INVALID 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_VALID_HEADERVALID0_VALID 0x00000001 /* R---V */
#define NV_INGRESS_ERR_MISC_LOG_0 0x00001454 /* R--4R */
#define NV_INGRESS_ERR_MISC_LOG_0_SPORT 5:0 /* R-IVF */
#define NV_INGRESS_ERR_MISC_LOG_0_SPORT_INIT 0x00000000 /* R-I-V */
#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC 10:8 /* R-IVF */
#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC_CREQ0 0x00000000 /* R-I-V */
#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC_RSP0 0x00000005 /* R---V */
#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC_CREQ1 0x00000006 /* R---V */
#define NV_INGRESS_ERR_MISC_LOG_0_ENCODEDVC_RSP1 0x00000007 /* R---V */
#define NV_INGRESS_ERR_HEADER_LOG_0 0x00001420 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_0_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_0_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_1 0x00001424 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_1_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_1_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_2 0x00001428 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_2_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_2_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_3 0x0000142c /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_3_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_3_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_4 0x00001430 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_4_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_4_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_5 0x00001434 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_5_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_5_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_6 0x00001438 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_6_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_6_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_7 0x0000143c /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_7_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_7_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_8 0x00001440 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_8_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_8_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_9 0x00001444 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_9_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_9_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_HEADER_LOG_10 0x00001448 /* R--4R */
#define NV_INGRESS_ERR_HEADER_LOG_10_DW 31:0 /* R-DVF */
#define NV_INGRESS_ERR_HEADER_LOG_10_DW_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0 0x00001414 /* RW-4R */
#define NV_INGRESS_ERR_CONTAIN_EN_0_CMDDECODEERR 0:0 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_CMDDECODEERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REQCONTEXTMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ACLFAIL 3:3 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ACLFAIL__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET 6:6 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRBOUNDSERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTABCFGERR 8:8 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTABCFGERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTABCFGERR 9:9 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTABCFGERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRTYPEERR 17:17 /* RWEVF */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRTYPEERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_CONTAIN_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER 0x00001480 /* RW-4R */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS 0x00001488 /* R--4R */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID 0x0000148c /* R--4R */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER 0x00001490 /* RW-4R */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS 0x00001498 /* R--4R */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID 0x0000149c /* R--4R */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER 0x000014a0 /* RW-4R */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS 0x000014a8 /* R--4R */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID 0x000014ac /* R--4R */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_INGRESS_ERR_FIRST_0 0x0000141c /* RW-4R */
#define NV_INGRESS_ERR_FIRST_0_CMDDECODEERR 0:0 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_CMDDECODEERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_CMDDECODEERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_REQCONTEXTMISMATCHERR 2:2 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_REQCONTEXTMISMATCHERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_REQCONTEXTMISMATCHERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_ACLFAIL 3:3 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_ACLFAIL_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_ACLFAIL_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_INVALIDVCSET 6:6 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_INVALIDVCSET_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_INVALIDVCSET_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_ADDRBOUNDSERR 7:7 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_ADDRBOUNDSERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_ADDRBOUNDSERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_RIDTABCFGERR 8:8 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_RIDTABCFGERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_RIDTABCFGERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_RLANTABCFGERR 9:9 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_RLANTABCFGERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_RLANTABCFGERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_PARITY_ERR 13:13 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_REMAPTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_RIDTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_RLANTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FIRST_0_ADDRTYPEERR 17:17 /* RWDVF */
#define NV_INGRESS_ERR_FIRST_0_ADDRTYPEERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_FIRST_0_ADDRTYPEERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0 0x00001400 /* RW-4R */
#define NV_INGRESS_ERR_STATUS_0_CMDDECODEERR 0:0 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_CMDDECODEERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_CMDDECODEERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_REQCONTEXTMISMATCHERR 2:2 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_REQCONTEXTMISMATCHERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_REQCONTEXTMISMATCHERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_ACLFAIL 3:3 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_ACLFAIL_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_ACLFAIL_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_INVALIDVCSET 6:6 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_INVALIDVCSET_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_INVALIDVCSET_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_ADDRBOUNDSERR 7:7 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_ADDRBOUNDSERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_ADDRBOUNDSERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_RIDTABCFGERR 8:8 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_RIDTABCFGERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_RIDTABCFGERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_RLANTABCFGERR 9:9 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_RLANTABCFGERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_RLANTABCFGERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_PARITY_ERR 13:13 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_REMAPTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_RIDTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_RLANTAB_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_STATUS_0_ADDRTYPEERR 17:17 /* RWDVF */
#define NV_INGRESS_ERR_STATUS_0_ADDRTYPEERR_NONE 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_STATUS_0_ADDRTYPEERR_CLEAR 0x00000001 /* RW--V */
#define NV_INGRESS_REMAPTABDATA0 0x00001090 /* RW-4R */
#define NV_INGRESS_REMAPTABDATA0_RMAP_ADDR 10:0 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA0_RMAP_ADDR_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA0_IRL_SEL 16:15 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA0_IRL_SEL_SELECTNONE 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA0_IRL_SEL_SELECTIRL0 0x00000001 /* RW--V */
#define NV_INGRESS_REMAPTABDATA0_IRL_SEL_SELECTIRL1 0x00000002 /* RW--V */
#define NV_INGRESS_REMAPTABDATA0_IRL_SEL_ENABLEERRRSP 0x00000003 /* RW--V */
#define NV_INGRESS_REMAPTABDATA0_ECC 30:22 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA0_ECC_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA0_ACLVALID 31:31 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA0_ACLVALID_INVALID 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA0_ACLVALID_VALID 0x00000001 /* RW--V */
#define NV_INGRESS_REMAPTABDATA1 0x00001094 /* RW-4R */
#define NV_INGRESS_REMAPTABDATA1_REQCTXT_MSK 15:0 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA1_REQCTXT_MSK_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA1_REQCTXT_CHK 31:16 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA1_REQCTXT_CHK_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA2 0x00001098 /* RW-4R */
#define NV_INGRESS_REMAPTABDATA2_REQCTXT_REP 15:0 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA2_REQCTXT_REP_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA2_ADR_OFFSET 31:16 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA2_ADR_OFFSET_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA3 0x0000109c /* RW-4R */
#define NV_INGRESS_REMAPTABDATA3_ADR_BASE 15:0 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA3_ADR_BASE_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA3_ADR_LIMIT 31:16 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA3_ADR_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4 0x000010a0 /* RW-4R */
#define NV_INGRESS_REMAPTABDATA4_TGTID 10:0 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_TGTID_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4_P2R_SWIZ 12:12 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_P2R_SWIZ_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4_PLANE_SELECT 13:13 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_PLANE_SELECT_EVEN 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4_PLANE_SELECT_ODD 0x00000001 /* RW--V */
#define NV_INGRESS_REMAPTABDATA4_MULT2 14:14 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_MULT2_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4_RFUNC 21:15 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_RFUNC_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4_GPU_DIV 26:24 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_GPU_DIV_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REMAPTABDATA4_RSVD 31:27 /* RWEVF */
#define NV_INGRESS_REMAPTABDATA4_RSVD_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0 0x000010b0 /* RW-4R */
#define NV_INGRESS_RIDTABDATA0_GSIZE 3:0 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_GSIZE_16X 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_1X 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_2X 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_3X 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_4X 0x00000004 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_5X 0x00000005 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_6X 0x00000006 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_7X 0x00000007 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_8X 0x00000008 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_9X 0x00000009 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_10X 0x0000000a /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_11X 0x0000000b /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_12X 0x0000000c /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_13X 0x0000000d /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_14X 0x0000000e /* RW--V */
#define NV_INGRESS_RIDTABDATA0_GSIZE_15X 0x0000000f /* RW--V */
#define NV_INGRESS_RIDTABDATA0_PORT0 10:5 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_PORT0_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE0 13:12 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_VC_MODE0_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE0_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE0_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE0_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_PORT1 19:14 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_PORT1_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE1 22:21 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_VC_MODE1_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE1_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE1_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE1_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_PORT2 28:23 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_PORT2_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE2 31:30 /* RWEVF */
#define NV_INGRESS_RIDTABDATA0_VC_MODE2_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE2_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE2_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA0_VC_MODE2_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA1 0x000010b4 /* RW-4R */
#define NV_INGRESS_RIDTABDATA1_PORT3 5:0 /* RWEVF */
#define NV_INGRESS_RIDTABDATA1_PORT3_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE3 8:7 /* RWEVF */
#define NV_INGRESS_RIDTABDATA1_VC_MODE3_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE3_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE3_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE3_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_PORT4 14:9 /* RWEVF */
#define NV_INGRESS_RIDTABDATA1_PORT4_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE4 17:16 /* RWEVF */
#define NV_INGRESS_RIDTABDATA1_VC_MODE4_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE4_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE4_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE4_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_PORT5 23:18 /* RWEVF */
#define NV_INGRESS_RIDTABDATA1_PORT5_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE5 26:25 /* RWEVF */
#define NV_INGRESS_RIDTABDATA1_VC_MODE5_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE5_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE5_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA1_VC_MODE5_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA2 0x000010b8 /* RW-4R */
#define NV_INGRESS_RIDTABDATA2_PORT6 5:0 /* RWEVF */
#define NV_INGRESS_RIDTABDATA2_PORT6_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE6 8:7 /* RWEVF */
#define NV_INGRESS_RIDTABDATA2_VC_MODE6_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE6_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE6_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE6_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_PORT7 14:9 /* RWEVF */
#define NV_INGRESS_RIDTABDATA2_PORT7_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE7 17:16 /* RWEVF */
#define NV_INGRESS_RIDTABDATA2_VC_MODE7_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE7_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE7_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE7_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_PORT8 23:18 /* RWEVF */
#define NV_INGRESS_RIDTABDATA2_PORT8_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE8 26:25 /* RWEVF */
#define NV_INGRESS_RIDTABDATA2_VC_MODE8_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE8_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE8_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA2_VC_MODE8_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA3 0x000010bc /* RW-4R */
#define NV_INGRESS_RIDTABDATA3_PORT9 5:0 /* RWEVF */
#define NV_INGRESS_RIDTABDATA3_PORT9_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE9 8:7 /* RWEVF */
#define NV_INGRESS_RIDTABDATA3_VC_MODE9_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE9_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE9_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE9_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_PORT10 14:9 /* RWEVF */
#define NV_INGRESS_RIDTABDATA3_PORT10_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE10 17:16 /* RWEVF */
#define NV_INGRESS_RIDTABDATA3_VC_MODE10_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE10_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE10_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE10_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_PORT11 23:18 /* RWEVF */
#define NV_INGRESS_RIDTABDATA3_PORT11_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE11 26:25 /* RWEVF */
#define NV_INGRESS_RIDTABDATA3_VC_MODE11_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE11_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE11_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA3_VC_MODE11_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA4 0x000010c0 /* RW-4R */
#define NV_INGRESS_RIDTABDATA4_PORT12 5:0 /* RWEVF */
#define NV_INGRESS_RIDTABDATA4_PORT12_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE12 8:7 /* RWEVF */
#define NV_INGRESS_RIDTABDATA4_VC_MODE12_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE12_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE12_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE12_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_PORT13 14:9 /* RWEVF */
#define NV_INGRESS_RIDTABDATA4_PORT13_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE13 17:16 /* RWEVF */
#define NV_INGRESS_RIDTABDATA4_VC_MODE13_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE13_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE13_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE13_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_PORT14 23:18 /* RWEVF */
#define NV_INGRESS_RIDTABDATA4_PORT14_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE14 26:25 /* RWEVF */
#define NV_INGRESS_RIDTABDATA4_VC_MODE14_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE14_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE14_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA4_VC_MODE14_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA5 0x000010c4 /* RW-4R */
#define NV_INGRESS_RIDTABDATA5_PORT15 5:0 /* RWEVF */
#define NV_INGRESS_RIDTABDATA5_PORT15_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA5_VC_MODE15 8:7 /* RWEVF */
#define NV_INGRESS_RIDTABDATA5_VC_MODE15_SAME 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA5_VC_MODE15_INVERT 0x00000001 /* RW--V */
#define NV_INGRESS_RIDTABDATA5_VC_MODE15_ALWAYS0 0x00000002 /* RW--V */
#define NV_INGRESS_RIDTABDATA5_VC_MODE15_ALWAYS1 0x00000003 /* RW--V */
#define NV_INGRESS_RIDTABDATA5_RMOD 18:9 /* RWEVF */
#define NV_INGRESS_RIDTABDATA5_RMOD_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA5_ECC 30:22 /* RWEVF */
#define NV_INGRESS_RIDTABDATA5_ECC_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA5_ACLVALID 31:31 /* RWEVF */
#define NV_INGRESS_RIDTABDATA5_ACLVALID_INVALID 0x00000000 /* RWE-V */
#define NV_INGRESS_RIDTABDATA5_ACLVALID_VALID 0x00000001 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR 0x00001080 /* RW-4R */
#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS 13:0 /* RWEVF */
#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_REMAPTAB_DEPTH 0x000007ff /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_RID_TAB_DEPTH 0x000001ff /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS_RLAN_TAB_DEPTH 0x000001ff /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL 18:16 /* RWEVF */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSREMAPPOLICYRAM 0x00000000 /* RWE-V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSRIDROUTERAM 0x00000001 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECTSRLANROUTERAM 0x00000002 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_RSVD3 0x00000003 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_RSVD4 0x00000004 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_RSVD5 0x00000005 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_RSVD6 0x00000006 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_RSVD7 0x00000007 /* RW--V */
#define NV_INGRESS_REQRSPMAPADDR_AUTO_INCR 31:31 /* RWEVF */
#define NV_INGRESS_REQRSPMAPADDR_AUTO_INCR_ENABLE 0x00000001 /* RWE-V */
#define NV_INGRESS_REQRSPMAPADDR_AUTO_INCR_DISABLE 0x00000000 /* RW--V */
#define NV_INGRESS_RLANTABDATA0 0x000010d0 /* RW-4R */
#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_0 3:0 /* RWEVF */
#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_0_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA0_GRP_SEL_0 8:5 /* RWEVF */
#define NV_INGRESS_RLANTABDATA0_GRP_SEL_0_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_1 13:10 /* RWEVF */
#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_1_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA0_GRP_SEL_1 18:15 /* RWEVF */
#define NV_INGRESS_RLANTABDATA0_GRP_SEL_1_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_2 23:20 /* RWEVF */
#define NV_INGRESS_RLANTABDATA0_GRP_SIZE_2_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA0_GRP_SEL_2 28:25 /* RWEVF */
#define NV_INGRESS_RLANTABDATA0_GRP_SEL_2_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA1 0x000010d4 /* RW-4R */
#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_3 3:0 /* RWEVF */
#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_3_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA1_GRP_SEL_3 8:5 /* RWEVF */
#define NV_INGRESS_RLANTABDATA1_GRP_SEL_3_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_4 13:10 /* RWEVF */
#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_4_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA1_GRP_SEL_4 18:15 /* RWEVF */
#define NV_INGRESS_RLANTABDATA1_GRP_SEL_4_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_5 23:20 /* RWEVF */
#define NV_INGRESS_RLANTABDATA1_GRP_SIZE_5_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA1_GRP_SEL_5 28:25 /* RWEVF */
#define NV_INGRESS_RLANTABDATA1_GRP_SEL_5_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA2 0x000010d8 /* RW-4R */
#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_6 3:0 /* RWEVF */
#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_6_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA2_GRP_SEL_6 8:5 /* RWEVF */
#define NV_INGRESS_RLANTABDATA2_GRP_SEL_6_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_7 13:10 /* RWEVF */
#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_7_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA2_GRP_SEL_7 18:15 /* RWEVF */
#define NV_INGRESS_RLANTABDATA2_GRP_SEL_7_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_8 23:20 /* RWEVF */
#define NV_INGRESS_RLANTABDATA2_GRP_SIZE_8_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA2_GRP_SEL_8 28:25 /* RWEVF */
#define NV_INGRESS_RLANTABDATA2_GRP_SEL_8_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA3 0x000010dc /* RW-4R */
#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_9 3:0 /* RWEVF */
#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_9_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA3_GRP_SEL_9 8:5 /* RWEVF */
#define NV_INGRESS_RLANTABDATA3_GRP_SEL_9_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_10 13:10 /* RWEVF */
#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_10_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA3_GRP_SEL_10 18:15 /* RWEVF */
#define NV_INGRESS_RLANTABDATA3_GRP_SEL_10_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_11 23:20 /* RWEVF */
#define NV_INGRESS_RLANTABDATA3_GRP_SIZE_11_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA3_GRP_SEL_11 28:25 /* RWEVF */
#define NV_INGRESS_RLANTABDATA3_GRP_SEL_11_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA4 0x000010e0 /* RW-4R */
#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_12 3:0 /* RWEVF */
#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_12_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA4_GRP_SEL_12 8:5 /* RWEVF */
#define NV_INGRESS_RLANTABDATA4_GRP_SEL_12_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_13 13:10 /* RWEVF */
#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_13_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA4_GRP_SEL_13 18:15 /* RWEVF */
#define NV_INGRESS_RLANTABDATA4_GRP_SEL_13_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_14 23:20 /* RWEVF */
#define NV_INGRESS_RLANTABDATA4_GRP_SIZE_14_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA4_GRP_SEL_14 28:25 /* RWEVF */
#define NV_INGRESS_RLANTABDATA4_GRP_SEL_14_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA5 0x000010e4 /* RW-4R */
#define NV_INGRESS_RLANTABDATA5_GRP_SIZE_15 3:0 /* RWEVF */
#define NV_INGRESS_RLANTABDATA5_GRP_SIZE_15_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA5_GRP_SEL_15 8:5 /* RWEVF */
#define NV_INGRESS_RLANTABDATA5_GRP_SEL_15_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA5_RSVD 21:20 /* RWEVF */
#define NV_INGRESS_RLANTABDATA5_RSVD_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA5_ECC 30:22 /* RWEVF */
#define NV_INGRESS_RLANTABDATA5_ECC_INIT 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA5_ACLVALID 31:31 /* RWEVF */
#define NV_INGRESS_RLANTABDATA5_ACLVALID_INVALID 0x00000000 /* RWE-V */
#define NV_INGRESS_RLANTABDATA5_ACLVALID_VALID 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER 0x000014b0 /* RW-4R */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_LIMIT 0x000014b4 /* RW-4R */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0 0x00001408 /* RW-4R */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_CMDDECODEERR 0:0 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_CMDDECODEERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ACLFAIL 3:3 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ACLFAIL__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET 6:6 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRBOUNDSERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTABCFGERR 8:8 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTABCFGERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTABCFGERR 9:9 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTABCFGERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRTYPEERR 17:17 /* RWEVF */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRTYPEERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_FATAL_REPORT_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0 0x0000140c /* RW-4R */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_CMDDECODEERR 0:0 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_CMDDECODEERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_CMDDECODEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_CMDDECODEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR 2:2 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REQCONTEXTMISMATCHERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL 3:3 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ACLFAIL_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR 4:4 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 5:5 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET 6:6 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_INVALIDVCSET_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR 7:7 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRBOUNDSERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTABCFGERR 8:8 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTABCFGERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTABCFGERR 9:9 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTABCFGERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTABCFGERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTABCFGERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR 10:10 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR 11:11 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR 12:12 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 13:13 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR 14:14 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_REMAPTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR 15:15 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RIDTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR 16:16 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_RLANTAB_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR 17:17 /* RWEVF */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_NON_FATAL_REPORT_EN_0_ADDRTYPEERR_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL 0x00001470 /* RW-4R */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_HDR_ECC_ENABLE 0:0 /* RWEVF */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_HDR_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_HDR_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_HDR_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE 1:1 /* RWEVF */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_REMAPTAB_ECC_ENABLE 8:8 /* RWEVF */
#define NV_INGRESS_ERR_ECC_CTRL_REMAPTAB_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_REMAPTAB_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_ECC_CTRL_REMAPTAB_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_RIDTAB_ECC_ENABLE 9:9 /* RWEVF */
#define NV_INGRESS_ERR_ECC_CTRL_RIDTAB_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_RIDTAB_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_ECC_CTRL_RIDTAB_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_RLANTAB_ECC_ENABLE 10:10 /* RWEVF */
#define NV_INGRESS_ERR_ECC_CTRL_RLANTAB_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_ECC_CTRL_RLANTAB_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_INGRESS_ERR_ECC_CTRL_RLANTAB_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_LIMIT 0x00001484 /* RW-4R */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_LIMIT 0x00001494 /* RW-4R */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_LIMIT 0x000014a4 /* RW-4R */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#endif // __lr10_dev_ingress_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_minion_ip_h__
#define __lr10_dev_minion_ip_h__
/* This file is autogenerated. Do not edit */
// did not include the regs that weren't approved for Tegra
#define NV_CMINION_FALCON_CG2 0x00000134 /* RWI4R */
#define NV_CMINION_FALCON_CG2_SLCG 17:1 /* */
#define NV_CMINION_FALCON_CG2_SLCG_ENABLED 0 /* */
#define NV_CMINION_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */
#define NV_CMINION_FALCON_CG2_SLCG__PROD 0x10004 /* */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */
#define NV_CMINION_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_IRQMASK 0x00000018 /* R--4R */
#define NV_CMINION_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_HALT 4:4 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMASK_DMA 16:16 /* R-IVF */
#define NV_CMINION_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSCLR 0x00000004 /* -W-4R */
#define NV_CMINION_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */
#define NV_CMINION_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQSTAT 0x00000008 /* R--4R */
#define NV_CMINION_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */
#define NV_CMINION_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IRQMSET 0x00000010 /* -W-4R */
#define NV_CMINION_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_MTHD_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_HALT 4:4 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_HALT_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQMSET_DMA 16:16 /* -WXVF */
#define NV_CMINION_FALCON_IRQMSET_DMA_SET 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_IRQDEST 0x0000001c /* RW-4R */
#define NV_CMINION_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT 15:8 /* */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT 31:24 /* */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMACTL 0x0000010c /* RW-4R */
#define NV_CMINION_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
#define NV_CMINION_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
#define NV_CMINION_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
#define NV_CMINION_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
#define NV_CMINION_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
#define NV_CMINION_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_DMACTL_DMAQ_NUM 6:3 /* R--VF */
#define NV_CMINION_FALCON_DMACTL_SECURE_STAT 7:7 /* R--VF */
#define NV_CMINION_FALCON_IMEMC(i) (0x00000180+(i)*16) /* RW-4A */
#define NV_CMINION_FALCON_IMEMC__SIZE_1 4 /* */
#define NV_CMINION_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
#define NV_CMINION_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IMEMC_BLK 23:8 /* RWIVF */
#define NV_CMINION_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
#define NV_CMINION_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IMEMC_AINCR 25:25 /* RWIVF */
#define NV_CMINION_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
#define NV_CMINION_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */
#define NV_CMINION_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */
#define NV_CMINION_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */
#define NV_CMINION_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_IMEMT(i) (0x00000188+(i)*16) /* RW-4A */
#define NV_CMINION_FALCON_IMEMT__SIZE_1 4 /* */
#define NV_CMINION_FALCON_IMEMT_TAG 15:0 /* RW-VF */
#define NV_CMINION_FALCON_IMEMD(i) (0x00000184+(i)*16) /* RW-4A */
#define NV_CMINION_FALCON_IMEMD__SIZE_1 4 /* */
#define NV_CMINION_FALCON_IMEMD_DATA 31:0 /* RW-VF */
#define NV_CMINION_FALCON_DMEMC(i) (0x000001c0+(i)*8) /* RW-4A */
#define NV_CMINION_FALCON_DMEMC__SIZE_1 8 /* */
#define NV_CMINION_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_OFFS 7:2 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_BLK 23:8 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_AINCR 25:25 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_VA 28:28 /* RWIVF */
#define NV_CMINION_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_DMEMC_MISS 29:29 /* R-IVF */
#define NV_CMINION_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */
#define NV_CMINION_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */
#define NV_CMINION_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */
#define NV_CMINION_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */
#define NV_CMINION_FALCON_DMEMD__SIZE_1 8 /* */
#define NV_CMINION_FALCON_DMEMD_DATA 31:0 /* RW-VF */
#define NV_CMINION_FALCON_OS 0x00000080 /* RW-4R */
#define NV_CMINION_FALCON_OS_VERSION 31:0 /* RWIVF */
#define NV_CMINION_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_MAILBOX1 0x00000044 /* RW-4R */
#define NV_CMINION_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
#define NV_CMINION_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_SCTL 0x00000240 /* RW-4R */
#define NV_CMINION_FALCON_SCTL_LSMODE 0:0 /* RWIVF */
#define NV_CMINION_FALCON_SCTL_LSMODE_FALSE 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_SCTL_LSMODE_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_SCTL_HSMODE 1:1 /* R--VF */
#define NV_CMINION_FALCON_SCTL_HSMODE_FALSE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_SCTL_HSMODE_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */
#define NV_CMINION_FALCON_SCTL_LSMODE_LEVEL_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_SCTL_UCODE_LEVEL 5:4 /* */
#define NV_CMINION_FALCON_SCTL_UCODE_LEVEL_INIT 0 /* */
#define NV_CMINION_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */
#define NV_CMINION_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */
#define NV_CMINION_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */
#define NV_CMINION_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x00000001 /* RWI-V */
#define NV_CMINION_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */
#define NV_CMINION_FALCON_SCTL_AUTH_EN_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_SCTL_AUTH_EN_FALSE 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_SCTL1 0x00000250 /* RW-4R */
#define NV_CMINION_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */
#define NV_CMINION_FALCON_SCTL1_CSBLVL_MASK_INIT 0x00000003 /* RWI-V */
#define NV_CMINION_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */
#define NV_CMINION_FALCON_SCTL1_EXTLVL_MASK_INIT 0x00000003 /* RWI-V */
#define NV_CMINION_FALCON_BOOTVEC 0x00000104 /* RW-4R */
#define NV_CMINION_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */
#define NV_CMINION_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_FALCON_CPUCTL 0x00000100 /* RW-4R */
#define NV_CMINION_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */
#define NV_CMINION_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
#define NV_CMINION_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */
#define NV_CMINION_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */
#define NV_CMINION_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */
#define NV_CMINION_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
#define NV_CMINION_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */
#define NV_CMINION_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */
#define NV_CMINION_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */
#define NV_CMINION_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
#define NV_CMINION_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
#define NV_CMINION_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
#define NV_CMINION_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */
#define NV_CMINION_SCP_CTL_STAT 0x00000608 /* R--4R */
#define NV_CMINION_SCP_CTL_STAT_DEBUG_MODE 20:20 /* R--VF */
#define NV_CMINION_SCP_CTL_STAT_DEBUG_MODE_DISABLED 0x00000000 /* R---V */
#define NV_CMINION_SCP_CTL_STAT_AES_SCC_DIS 2:2 /* R--VF */
#define NV_CMINION_SCP_CTL_STAT_AES_SCC_DIS_TRUE 0x00000001 /* R---V */
#define NV_CMINION_SCP_CTL_STAT_AES_SCC_DIS_FALSE 0x00000000 /* R---V */
#define NV_CMINION_SCP_CTL_STAT_HSMODE 1:1 /* R--VF */
#define NV_CMINION_SCP_CTL_STAT_HSMODE_TRUE 0x00000001 /* R---V */
#define NV_CMINION_SCP_CTL_STAT_HSMODE_FALSE 0x00000000 /* R---V */
#define NV_CMINION_SCP_CTL_STAT_SBOOT 0:0 /* R--VF */
#define NV_CMINION_SCP_CTL_STAT_SBOOT_TRUE 0x00000001 /* R---V */
#define NV_CMINION_SCP_CTL_STAT_SBOOT_FALSE 0x00000000 /* R---V */
#define NV_MINION_NVLINK_DL_STAT(i) (0x00000980+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_DL_STAT__SIZE_1 4 /* */
#define NV_MINION_NVLINK_DL_STAT_ARGS 15:0 /* RWEVF */
#define NV_MINION_NVLINK_DL_STAT_ARGS_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_STAT_STATUSIDX 23:16 /* RWEVF */
#define NV_MINION_NVLINK_DL_STAT_STATUSIDX_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_STAT_READY 31:31 /* RWEVF */
#define NV_MINION_NVLINK_DL_STAT_READY_TRUE 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_STAT_READY_FALSE 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_STATDATA(i) (0x000009c0+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_DL_STATDATA__SIZE_1 4 /* */
#define NV_MINION_NVLINK_DL_STATDATA_DATA 31:0 /* RWEVF */
#define NV_MINION_NVLINK_DL_STATDATA_DATA_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_LINK_INTR(i) (0x00000a00+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_LINK_INTR__SIZE_1 4 /* */
#define NV_MINION_NVLINK_LINK_INTR_CODE 7:0 /* RWEVF */
#define NV_MINION_NVLINK_LINK_INTR_CODE_NA 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_SWREQ 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_DLREQ 0x00000002 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_PMDISABLED 0x00000003 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_DLCMDFAULT 0x00000004 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_TLREQ 0x00000005 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_NOINIT 0x00000010 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_NOTIFY 0x00000017 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_LOCAL_CONFIG_ERR 0x00000018 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_NEGOTIATION_CONFIG_ERR 0x00000019 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_BADINIT 0x00000020 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_CODE_PMFAIL 0x00000021 /* RW--V */
#define NV_MINION_NVLINK_LINK_INTR_SUBCODE 15:8 /* RWEVF */
#define NV_MINION_NVLINK_LINK_INTR_SUBCODE_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_LINK_INTR_STATE 31:31 /* RWEVF */
#define NV_MINION_NVLINK_LINK_INTR_STATE_INIT 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR 0x00000810 /* RW-4R */
#define NV_MINION_MINION_INTR_FATAL 0:0 /* RWEVF */
#define NV_MINION_MINION_INTR_FATAL_INIT 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONFATAL 1:1 /* RWEVF */
#define NV_MINION_MINION_INTR_NONFATAL_INIT 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_FALCON_STALL 2:2 /* R-EVF */
#define NV_MINION_MINION_INTR_FALCON_STALL_INIT 0x00000000 /* R-E-V */
#define NV_MINION_MINION_INTR_FALCON_NOSTALL 3:3 /* R-EVF */
#define NV_MINION_MINION_INTR_FALCON_NOSTALL_INIT 0x00000000 /* R-E-V */
#define NV_MINION_MINION_INTR_LINK 31:16 /* R-EVF */
#define NV_MINION_MINION_INTR_LINK_INIT 0x00000000 /* R-E-V */
#define NV_MINION_MINION_INTR_STALL_EN 0x00000818 /* RW-4R */
#define NV_MINION_MINION_INTR_STALL_EN_FATAL 0:0 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_FATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_FATAL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_STALL_EN_NONFATAL 1:1 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_NONFATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_NONFATAL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_STALL 2:2 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_STALL_DISABLE 0x00000000 /* RW--V */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_STALL_ENABLE 0x00000001 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_NOSTALL 3:3 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_NOSTALL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_FALCON_NOSTALL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_STALL_EN_LINK 31:16 /* RWEVF */
#define NV_MINION_MINION_INTR_STALL_EN_LINK_DISABLE_ALL 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_STALL_EN_LINK_ENABLE_ALL 0x0000ffff /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN 0x0000081c /* RW-4R */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FATAL 0:0 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FATAL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_NONFATAL 1:1 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_NONFATAL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_NONFATAL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_STALL 2:2 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_STALL_DISABLE 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_STALL_ENABLE 0x00000001 /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_NOSTALL 3:3 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_NOSTALL_DISABLE 0x00000000 /* RW--V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_FALCON_NOSTALL_ENABLE 0x00000001 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_LINK 31:16 /* RWEVF */
#define NV_MINION_MINION_INTR_NONSTALL_EN_LINK_DISABLE_ALL 0x00000000 /* RWE-V */
#define NV_MINION_MINION_INTR_NONSTALL_EN_LINK_ENABLE_ALL 0x0000ffff /* RW--V */
#define NV_MINION_MINION_STATUS 0x00000830 /* RW-4R */
#define NV_MINION_MINION_STATUS_STATUS 7:0 /* RWEVF */
#define NV_MINION_MINION_STATUS_STATUS_INIT 0x00000000 /* RWE-V */
#define NV_MINION_MINION_STATUS_STATUS_BOOT 0x00000001 /* RW--V */
#define NV_MINION_MINION_STATUS_INTR_CODE 31:8 /* RWEVF */
#define NV_MINION_MINION_STATUS_INTR_CODE_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD(i) (0x00000900+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_DL_CMD__SIZE_1 4 /* */
#define NV_MINION_NVLINK_DL_CMD_COMMAND 7:0 /* RWEVF */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_NOP 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHY 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SWINTR 0x00000002 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITLANEENABLE 0x00000003 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITDLPL 0x00000004 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITRXTERM 0x00000005 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITTL 0x00000006 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPLL 0x00000007 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_LANEDISABLE 0x00000008 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_LANESHUTDOWN 0x0000000c /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE1 0x0000000d /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITNEGOTIATE 0x0000000e /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITOPTIMIZE 0x0000000f /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_ENABLEPM 0x00000010 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DISABLEPM 0x00000011 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_TXCLKSWITCH_PLL 0x00000014 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_TXCLKSWITCH_ALT 0x00000015 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_CLEARRESTORESTATE 0x00000017 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SAVESTATE 0x00000018 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_READ_PHY_TRAINING_PARAMS 0x00000020 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_WRITE_PHY_TRAINING_PARAMS 0x00000021 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_CONFIGEOM 0x00000040 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEA 0x00000041 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEDR 0x00000042 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETNEDW 0x00000043 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_XAVIER_PLLOVERRIDE_ON 0x00000050 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_XAVIER_PLLOVERRIDE_OFF 0x00000051 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_XAVIER_CALIBRATEPLL 0x00000052 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_TURING_RXDET 0x00000058 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLERRCNT 0x00000070 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLLPCNT 0x00000071 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLTHROUGHPUTCNT 0x00000072 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_DBG_PROTECTIONS_OFF 0x000000f0 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_ALWAYSFAULT 0x000000ff /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_FAULT 30:30 /* RWEVF */
#define NV_MINION_NVLINK_DL_CMD_FAULT_FAULT_CLEAR 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_FAULT_NOFAULT_NOCLEAR 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD_READY 31:31 /* RWEVF */
#define NV_MINION_NVLINK_DL_CMD_READY_TRUE 0x00000001 /* RW--V */
#define NV_MINION_NVLINK_DL_CMD_READY_FALSE 0x00000000 /* RWE-V */
#define NV_MINION_MISC_0 0x000008b0 /* RW-4R */
#define NV_MINION_MISC_0_SCRATCH_SWRW_0 31:0 /* RWEVF */
#define NV_MINION_MISC_0_SCRATCH_SWRW_0_INIT 0x00000000 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD_DATA(i) (0x00000920+(i)*0x4) /* RW-4A */
#define NV_MINION_NVLINK_DL_CMD_DATA__SIZE_1 4 /* */
#define NV_MINION_NVLINK_DL_CMD_DATA_DATA 31:0 /* RWEVF */
#define NV_MINION_NVLINK_DL_CMD_DATA_DATA_INIT 0x00000000 /* RWE-V */
#endif // __lr10_dev_minion_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_minion_ip_addendum_h__
#define __lr10_dev_minion_ip_addendum_h__
#define NV_NVLSTAT 0x00000103:0x00000000 /* RW--D */
#define NV_NVLSTAT_UC01 0x00000001 /* R--4R */
#define NV_NVLSTAT_UC01_PM_STATE 31:31 /* R---F */
#define NV_NVLSTAT_UC01_ACMODE_STATE 30:30 /* R---F */
#define NV_NVLSTAT_UC01_LANES_ENABLED 29:29 /* R---F */
#define NV_NVLSTAT_UC01_LANES_ENABLED_TRUE 0x1 /* R---V */
#define NV_NVLSTAT_UC01_LANES_ENABLED_FALSE 0x0 /* R---V */
#define NV_NVLSTAT_UC01_TRAINING_BUFFER_STATUS 23:20 /* R---F */
#define NV_NVLSTAT_UC01_SEARCH_ERROR 19:19 /* R---F */
#define NV_NVLSTAT_UC01_TRAINING_GOOD 18:18 /* R---F */
#define NV_NVLSTAT_UC01_TRAINING_GOOD_SUCCESS 0x1 /* R---V */
#define NV_NVLSTAT_UC01_TRAINING_GOOD_UNKNOWN 0x0 /* R---V */
#define NV_NVLSTAT_UC01_CONFIG_GOOD 16:16 /* R---F */
#define NV_NVLSTAT_UC01_CONFIG_GOOD_SUCCESS 0x1 /* R---V */
#define NV_NVLSTAT_UC01_CONFIG_GOOD_UNKNOWN 0x0 /* R---V */
#define NV_NVLSTAT_UC01_LINK_STATE 15:0 /* R---F */
#define NV_NVLSTAT_LNK0 0x00000010 /* R--4R */
#define NV_NVLSTAT_LNK0_INTR_TX_FAULT_RAM 4:4 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_TX_FAULT_INTERFACE 5:5 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_TX_FAULT_SUBLINK_CHANGE 8:8 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_SUBLINK_CHANGE 16:16 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_DL_PROTOCOL 20:20 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_SHORT_ERROR_RATE 21:21 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_RX_FAULT_LONG_ERROR_RATE 22:22 /* R---F */
#define NV_NVLSTAT_LNK0_INTR_LTSSM_PROTOCOL 29:29 /* R---F */
#define NV_NVLSTAT_LNK1 0x00000011 /* R--4R */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_VALUE_SRCOVF 0x000003ff /* R---V */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_LNK1_ERROR_COUNT1_RECOVERY_EVENTS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_LNK2 0x00000012 /* R--4R */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS 9:8 /* R---F */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_UNINITIALIZED 0x0 /* R---V */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_SEARCH 0x1 /* R---V */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_FOUND 0x2 /* R---V */
#define NV_NVLSTAT_LNK2_RXDET_LINK_STATUS_TIMEOUT 0x3 /* R---V */
#define NV_NVLSTAT_LNK2_RXDET_LANE_STATUS 7:0 /* R---F */
#define NV_NVLSTAT_LNK2_RXDET_LANE_STATUS_FOUND 0x0f /* R---V */
#define NV_NVLSTAT_LNK3 0x00000013 /* R--4R */
#define NV_NVLSTAT_LNK3_LINERATE 23:0 /* R---F */
#define NV_NVLSTAT_LNK4 0x00000014 /* R--4R */
#define NV_NVLSTAT_LNK4_LINKCLOCK 15:0 /* R---F */
#define NV_NVLSTAT_LNK5 0x00000015 /* R--4R */
#define NV_NVLSTAT_LNK5_DATARATE 31:0 /* R---F */
#define NV_NVLSTAT_TX00 0x00000020 /* R--4R */
#define NV_NVLSTAT_TX00_COUNT_TX_STATE_EIGHTH_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX00_COUNT_TX_STATE_EIGHTH_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX00_COUNT_TX_STATE_EIGHTH_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX00_COUNT_TX_STATE_EIGHTH_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX00_COUNT_TX_STATE_EIGHTH_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX01 0x00000021 /* R--4R */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX01_COUNT_TX_STATE_NVHS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX02 0x00000022 /* R--4R */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX02_COUNT_TX_STATE_OTHER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX03 0x00000023 /* R--4R */
#define NV_NVLSTAT_TX03_DELAY_TX_STATE_LP_ENTER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX03_DELAY_TX_STATE_LP_ENTER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX03_DELAY_TX_STATE_LP_ENTER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX03_DELAY_TX_STATE_LP_ENTER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX03_DELAY_TX_STATE_LP_ENTER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX04 0x00000024 /* R--4R */
#define NV_NVLSTAT_TX04_DELAY_TX_STATE_LP_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX04_DELAY_TX_STATE_LP_EXIT_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX04_DELAY_TX_STATE_LP_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX04_DELAY_TX_STATE_LP_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX04_DELAY_TX_STATE_LP_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX05 0x00000025 /* R--4R */
#define NV_NVLSTAT_TX05_NUM_TX_STATE_LP_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX05_NUM_TX_STATE_LP_EXIT_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX05_NUM_TX_STATE_LP_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX05_NUM_TX_STATE_LP_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX05_NUM_TX_STATE_LP_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX06 0x00000026 /* R--4R */
#define NV_NVLSTAT_TX06_NUM_TX_STATE_LP_ENTER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX06_NUM_TX_STATE_LP_ENTER_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_TX06_NUM_TX_STATE_LP_ENTER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX06_NUM_TX_STATE_LP_ENTER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX06_NUM_TX_STATE_LP_ENTER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX07 0x00000027 /* R--4R */
#define NV_NVLSTAT_TX07_DELAY_TX_FB_EXIT_OTHER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX07_DELAY_TX_FB_EXIT_OTHER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX07_DELAY_TX_FB_EXIT_OTHER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX07_DELAY_TX_FB_EXIT_OTHER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX07_DELAY_TX_FB_EXIT_OTHER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX08 0x00000028 /* R--4R */
#define NV_NVLSTAT_TX08_DELAY_TX_FB_ENTER_OTHER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX08_DELAY_TX_FB_ENTER_OTHER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX08_DELAY_TX_FB_ENTER_OTHER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX08_DELAY_TX_FB_ENTER_OTHER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX08_DELAY_TX_FB_ENTER_OTHER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX09 0x00000029 /* R--4R */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_TX09_REPLAY_EVENTS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TX12 0x0000002c /* R--4R */
#define NV_NVLSTAT_TX12_TX_LPOCC_HIST 31:0 /* R---F */
#define NV_NVLSTAT_TX13 0x0000002d /* R--4R */
#define NV_NVLSTAT_TX13_TX_LPOCC_HIST 31:0 /* R---F */
#define NV_NVLSTAT_TX14 0x0000002e /* R--4R */
#define NV_NVLSTAT_TX14_TX_LPEXIT_HIST 31:0 /* R---F */
#define NV_NVLSTAT_TX15 0x0000002f /* R--4R */
#define NV_NVLSTAT_TX15_TX_LPEXIT_HIST 31:0 /* R---F */
#define NV_NVLSTAT_RX00 0x00000040 /* R--4R */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX00_REPLAY_EVENTS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX01 0x00000041 /* R--4R */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX01_FLIT_CRC_ERRORS_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX03 0x00000043 /* R--4R */
#define NV_NVLSTAT_RX03_DELAY_RX_LP_ENTER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX03_DELAY_RX_LP_ENTER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_RX03_DELAY_RX_LP_ENTER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX03_DELAY_RX_LP_ENTER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX03_DELAY_RX_LP_ENTER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX04 0x00000044 /* R--4R */
#define NV_NVLSTAT_RX04_DELAY_RX_LP_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX04_DELAY_RX_LP_EXIT_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_RX04_DELAY_RX_LP_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX04_DELAY_RX_LP_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX04_DELAY_RX_LP_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX05 0x00000045 /* R--4R */
#define NV_NVLSTAT_RX05_DELAY_RX_FB_ENTER_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX05_DELAY_RX_FB_ENTER_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_RX05_DELAY_RX_FB_ENTER_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX05_DELAY_RX_FB_ENTER_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX05_DELAY_RX_FB_ENTER_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX06 0x00000046 /* R--4R */
#define NV_NVLSTAT_RX06_DELAY_RX_FB_EXIT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX06_DELAY_RX_FB_EXIT_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_RX06_DELAY_RX_FB_EXIT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX06_DELAY_RX_FB_EXIT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX06_DELAY_RX_FB_EXIT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX08 0x00000048 /* R--4R */
#define NV_NVLSTAT_RX08_ERRORLOG_ERR_CNT_MULTI 7:0 /* R---F */
#define NV_NVLSTAT_RX09 0x00000049 /* R--4R */
#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_7 31:24 /* R---F */
#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_6 23:16 /* R---F */
#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_5 15:8 /* R---F */
#define NV_NVLSTAT_RX09_ERRORLOG_ERR_CNT_4 7:0 /* R---F */
#define NV_NVLSTAT_RX10 0x0000004a /* R--4R */
#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_3 31:24 /* R---F */
#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_2 23:16 /* R---F */
#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_1 15:8 /* R---F */
#define NV_NVLSTAT_RX10_ERRORLOG_ERR_CNT_0 7:0 /* R---F */
#define NV_NVLSTAT_RX12 0x0000004c /* R--4R */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX12_ECC_CORRECTED_ERR_L0_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX13 0x0000004d /* R--4R */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX13_ECC_CORRECTED_ERR_L1_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX14 0x0000004e /* R--4R */
#define NV_NVLSTAT_RX14_ECC_CORRECTED_ERR_L2_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX14_ECC_CORRECTED_ERR_L2_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX14_ECC_CORRECTED_ERR_L2_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX14_ECC_CORRECTED_ERR_L2_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX14_ECC_CORRECTED_ERR_L2_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_RX15 0x0000004f /* R--4R */
#define NV_NVLSTAT_RX15_ECC_CORRECTED_ERR_L3_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_RX15_ECC_CORRECTED_ERR_L3_VALUE_SRCOVF 0x0000ffff /* R---V */
#define NV_NVLSTAT_RX15_ECC_CORRECTED_ERR_L3_OVER 31:31 /* R---F */
#define NV_NVLSTAT_RX15_ECC_CORRECTED_ERR_L3_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_RX15_ECC_CORRECTED_ERR_L3_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_TR00 0x00000090 /* R--4R */
#define NV_NVLSTAT_TR00_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR01 0x00000091 /* R--4R */
#define NV_NVLSTAT_TR01_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR02 0x00000092 /* R--4R */
#define NV_NVLSTAT_TR02_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR03 0x00000093 /* R--4R */
#define NV_NVLSTAT_TR03_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR04 0x00000094 /* R--4R */
#define NV_NVLSTAT_TR04_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR05 0x00000095 /* R--4R */
#define NV_NVLSTAT_TR05_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR06 0x00000096 /* R--4R */
#define NV_NVLSTAT_TR06_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR07 0x00000097 /* R--4R */
#define NV_NVLSTAT_TR07_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR08 0x00000098 /* R--4R */
#define NV_NVLSTAT_TR08_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR09 0x00000099 /* R--4R */
#define NV_NVLSTAT_TR09_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR10 0x0000009a /* R--4R */
#define NV_NVLSTAT_TR10_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR11 0x0000009b /* R--4R */
#define NV_NVLSTAT_TR11_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR12 0x0000009c /* R--4R */
#define NV_NVLSTAT_TR12_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR13 0x0000009d /* R--4R */
#define NV_NVLSTAT_TR13_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR14 0x0000009e /* R--4R */
#define NV_NVLSTAT_TR14_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR15 0x0000009f /* R--4R */
#define NV_NVLSTAT_TR15_DATA 31:0 /* R---F */
#define NV_NVLSTAT_TR16 0x000000a0 /* R--4R */
#define NV_NVLSTAT_TR16_L0FOM 15:0 /* R---F */
#define NV_NVLSTAT_TR16_L1FOM 31:16 /* R---F */
#define NV_NVLSTAT_TR17 0x000000a1 /* R--4R */
#define NV_NVLSTAT_TR17_L2FOM 15:0 /* R---F */
#define NV_NVLSTAT_TR17_L3FOM 31:16 /* R---F */
#define NV_NVLSTAT_DB00 0x00000080 /* R--4R */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_VALUE_SRCOVF 0x7fffffff /* R---V */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_OVER 31:31 /* R---F */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_DB00_ERRORS_INJECTED_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_DB01 0x00000081 /* R--4R */
#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L3 31:24 /* R---F */
#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L2 23:16 /* R---F */
#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L1 15:8 /* R---F */
#define NV_NVLSTAT_DB01_ERROR_COUNT_ERR_LANECRC_L0 7:0 /* R---F */
#define NV_NVLSTAT_DB02 0x00000082 /* R--4R */
#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L7 31:24 /* R---F */
#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L6 23:16 /* R---F */
#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L5 15:8 /* R---F */
#define NV_NVLSTAT_DB02_ERROR_COUNT_ERR_LANECRC_L4 7:0 /* R---F */
#define NV_NVLSTAT_DB03 0x00000083 /* R--4R */
#define NV_NVLSTAT_DB03_RXSLSM_ERR_CNTL_CLK_SWITCH_ERR 31:31 /* R---F */
#define NV_NVLSTAT_DB03_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR 2:2 /* R---F */
#define NV_NVLSTAT_DB03_RXSLSM_ERR_CNTL_CONST_DET_ERR 1:1 /* R---F */
#define NV_NVLSTAT_DB04 0x00000084 /* R--4R */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_E2S_STROBE_NO_LD_ERR 23:23 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_H2S_STROBE_NO_LD_ERR 22:22 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_02S_STROBE_NO_LD_ERR 21:21 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_E2S_SD_NO_LD_ERR 20:20 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR 19:19 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR 18:18 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR 15:15 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_RC_TXPWR_ERR 14:14 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_RC_RXPWR_ERR 13:13 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_E2SAFE_LD_ERR 12:12 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SAFE_NO_LD_ERR 11:11 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_FENCE_ERR 10:10 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR 9:9 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR 8:8 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR 7:7 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR 6:6 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SYM_LOCK_ERR 5:5 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR 4:4 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_SAFE2NO_LINK_DET_ERR 3:3 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR 2:2 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_CONST_DET_ERR 1:1 /* R---F */
#define NV_NVLSTAT_DB04_RXSLSM_ERR_CNTL_FIFO_DRAIN_ERR 0:0 /* R---F */
#define NV_NVLSTAT_DB05 0x00000085 /* R--4R */
#define NV_NVLSTAT_DB05_TIMEOUT_LOG_SYM_LOCK_LANE 31:24 /* R---F */
#define NV_NVLSTAT_DB05_TIMEOUT_LOG_SCRAM_LOCK_LANE 23:16 /* R---F */
#define NV_NVLSTAT_DB05_TIMEOUT_LOG_CONST_DET_LANE 15:8 /* R---F */
#define NV_NVLSTAT_DB05_TIMEOUT_LOG_FIFO_DRAIN_LANE 7:0 /* R---F */
#define NV_NVLSTAT_DB06 0x00000086 /* R--4R */
#define NV_NVLSTAT_DB06_TIMEOUT_LOG_SYM_ALIGN_END_LANE 31:24 /* R---F */
#define NV_NVLSTAT_DB06_TIMEOUT_LOG_FIFO_SKEW_LANE 23:16 /* R---F */
#define NV_NVLSTAT_DB07 0x00000087 /* R--4R */
#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_3 29:24 /* R---F */
#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_2 21:16 /* R---F */
#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_1 13:8 /* R---F */
#define NV_NVLSTAT_DB07_FIFO_STATUS_RX_0_ENTRIES_USED_0 5:0 /* R---F */
#define NV_NVLSTAT_DB08 0x00000088 /* R--4R */
#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_7 29:24 /* R---F */
#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_6 21:16 /* R---F */
#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_5 13:8 /* R---F */
#define NV_NVLSTAT_DB08_FIFO_STATUS_RX_0_ENTRIES_USED_4 5:0 /* R---F */
#define NV_NVLSTAT_DB09 0x00000089 /* R--4R */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_VALUE 30:0 /* R---F */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_VALUE_SRCOVF 0x000000ff /* R---V */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_OVER 31:31 /* R---F */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_OVER_OVER 0x1 /* R---V */
#define NV_NVLSTAT_DB09_SLSM_STATUS_RX_SURPRISE_LD_CNT_OVER_OKAY 0x0 /* R---V */
#define NV_NVLSTAT_DB10 0x0000008a /* R--4R */
#define NV_NVLSTAT_DB10_DATA 31:0 /* R---F */
#define NV_NVLSTAT_MN00 0x000000ff /* R--4R */
#define NV_NVLSTAT_MN00_LINK_INTR_SUBCODE 15:8 /* R---F */
#define NV_NVLSTAT_MN00_LINK_INTR_CODE 7:0 /* R---F */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_FORCE_EQ_OVERRIDE_1 0x00000060 /* RWE-V */
#define NV_MINION_NVLINK_DL_CMD_COMMAND_RELEASE_EQ_OVERRIDE_1 0x00000061 /* RWE-V */
#endif // __lr10_dev_minion_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_npg_ip_h__
#define __lr10_dev_npg_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NPG_NPG_INTERRUPT_STATUS 0x00000400 /* R--4R */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_FNC_OR 0:0 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_FNC_OR_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS 3:1 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_FATAL 0x00000001 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_NONFATAL 0x00000002 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV0_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_FNC_OR 4:4 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_FNC_OR_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS 7:5 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_FATAL 0x00000001 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_NONFATAL 0x00000002 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV1_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_FNC_OR 8:8 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_FNC_OR_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS 11:9 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_FATAL 0x00000001 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_NONFATAL 0x00000002 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV2_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_FNC_OR 12:12 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_FNC_OR_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS 15:13 /* R-EVF */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_FATAL 0x00000001 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_NONFATAL 0x00000002 /* R---V */
#define NV_NPG_NPG_INTERRUPT_STATUS_DEV3_INT_STATUS_CORRECTABLE 0x00000004 /* R---V */
#define NV_NPG_WARMRESET 0x00000140 /* RW-4R */
#define NV_NPG_WARMRESET_NPORTWARMRESET 11:8 /* RWEVF */
#define NV_NPG_WARMRESET_NPORTWARMRESET_INIT 0x0000000f /* RWE-V */
#define NV_NPG_WARMRESET_NPORTWARMRESET_ASSERT 0x00000000 /* RW--V */
#define NV_NPG_WARMRESET_NPORTWARMRESET_DEASSERT 0x00000001 /* RW--V */
#define NV_NPG_DEBUG_CLEAR 0x00000144 /* RW-4R */
#define NV_NPG_DEBUG_CLEAR_CLEAR 3:0 /* RWIVF */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_NPORT_0 0x00000001 /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_NPORT_1 0x00000002 /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_NPORT_2 0x00000004 /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_NPORT_3 0x00000008 /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_ASSERT_ALL 0x0000000f /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CLEAR_DEASSERT 0x00000000 /* RWI-V */
#define NV_NPG_DEBUG_CLEAR_CMN_CLEAR 31:31 /* RWIVF */
#define NV_NPG_DEBUG_CLEAR_CMN_CLEAR_ASSERT 0x00000001 /* RW--V */
#define NV_NPG_DEBUG_CLEAR_CMN_CLEAR_DEASSERT 0x00000000 /* RWI-V */
#define NV_NPG_CTRL_PRI_MULTICAST 0x000000c0 /* RW-4R */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE 5:0 /* RWEVF */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_NO_NPORT_ENABLED 0x00000000 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT0_NPORT_ENABLED 0x00000001 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT1_NPORT_ENABLED 0x00000002 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT01_NPORT_ENABLED 0x00000003 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT2_NPORT_ENABLED 0x00000004 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT02_NPORT_ENABLED 0x00000005 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_PORT3_NPORT_ENABLED 0x00000008 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_NPORT_ENABLE_ALL_NPORT_ENABLED 0x0000000f /* RWE-V */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE 7:6 /* RWEVF */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE_LOW_SELECTED_BUS 0x00000000 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE_OR_ALL_BUSSES 0x00000001 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE_AND_ALL_BUSSES 0x00000002 /* RWE-V */
#define NV_NPG_CTRL_PRI_MULTICAST_READ_MODE_ZEROS 0x00000003 /* RW--V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED 13:8 /* R-EVF */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_NO_MCAST_ENABLED 0x00000000 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT0_MCAST_ENABLED 0x00000001 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT1_MCAST_ENABLED 0x00000002 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT01_MCAST_ENABLED 0x00000003 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT2_MCAST_ENABLED 0x00000004 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT02_MCAST_ENABLED 0x00000005 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_PORT3_MCAST_ENABLED 0x00000008 /* R---V */
#define NV_NPG_CTRL_PRI_MULTICAST_MCAST_ENABLED_ALL_MCAST_ENABLED 0x0000000f /* R-E-V */
#endif // __lr10_dev_npg_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_npgperf_ip_h__
#define __lr10_dev_npgperf_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NPGPERF_CTRL_CLOCK_GATING 0x000000c8 /* RW-4R */
#define NV_NPGPERF_CTRL_CLOCK_GATING_CG1_SLCG 3:0 /* RWEVF */
#define NV_NPGPERF_CTRL_CLOCK_GATING_CG1_SLCG_INIT 0x0000000f /* RWE-V */
#define NV_NPGPERF_CTRL_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING 0x000000cc /* RW-4R */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG 3:0 /* RWEVF */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG_INIT 0x0000000f /* RWE-V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE 7:4 /* RWEVF */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE_DISABLED 0x00000000 /* RWE-V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE_ENABLED 0x00000001 /* RW--V */
#define NV_NPGPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE__PROD 0x00000000 /* RW--V */
#define NV_NPGPERF_CTRL_PRI_MULTICAST 0x000000c0 /* RW-4R */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_NPORT_ENABLE 5:0 /* RWEVF */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_NPORT_ENABLE_INIT 0x0000000f /* RWE-V */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_READ_MODE 7:6 /* RWEVF */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_READ_MODE_LOW_SELECTED_BUS 0x00000000 /* RW--V */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_READ_MODE_OR_ALL_BUSSES 0x00000001 /* RW--V */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_READ_MODE_AND_ALL_BUSSES 0x00000002 /* RWE-V */
#define NV_NPGPERF_CTRL_PRI_MULTICAST_READ_MODE_ZEROS 0x00000003 /* RW--V */
#endif // __lr10_dev_npgperf_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nport_ip_h__
#define __lr10_dev_nport_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_0 0x0000010c /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_0_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_0_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_0_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0 0x00000110 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_0_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0 0x00000114 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_0_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_CTRL_SLCG 0x00000050 /* RW-4R */
#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS 0:0 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_INGRESS__PROD 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE 1:1 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_ROUTE__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS 2:2 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_EGRESS__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK 3:3 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_STRACK__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE 4:4 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TAGSTATE__PROD 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX 5:5 /* RWEVF */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_SLCG_DIS_CG_TREX__PROD 0x00000000 /* RW--V */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_0 0x00000120 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_1 0x00000124 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_1_PACKETCOUNT 15:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_0_1_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_0 0x00000128 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_1 0x0000012c /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_1_PACKETCOUNT 15:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_0_1_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_0 0x00000130 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_1 0x00000134 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_1_PACKETCOUNT 15:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_0_1_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_0 0x00000138 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_1 0x0000013c /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_1_PACKETCOUNT 15:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_0_1_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_0 0x00000118 /* R--4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_1 0x0000011c /* R--4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_1_PACKETCOUNT 15:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_0_1_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_CONTROL 0x00000100 /* RW-4R */
#define NV_NPORT_PORTSTAT_CONTROL_SWEEPMODE 1:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_CONTROL_SWEEPMODE_SINGLE 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_CONTROL_SWEEPMODE_CONTINUOUS 0x00000001 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_SWEEPMODE_SWONDEMAND 0x00000002 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT 7:4 /* RWEVF */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS13TO0 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS15TO2 0x00000001 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS17TO4 0x00000002 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS19TO6 0x00000003 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS21TO8 0x00000004 /* RW--V */
#define NV_NPORT_PORTSTAT_CONTROL_RANGESELECT_BITS23TO10 0x00000005 /* RW--V */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_0 0x000002ac /* RW-4R */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_0_SRCFILTERBIT 31:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_0_SRCFILTERBIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_1 0x000002b0 /* RW-4R */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_1_SRCFILTERBIT 3:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_SOURCE_FILTER_1_SRCFILTERBIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_WINDOW_LIMIT 0x00000108 /* RW-4R */
#define NV_NPORT_PORTSTAT_WINDOW_LIMIT_WINDOWLIMIT 31:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_WINDOW_LIMIT_WINDOWLIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL 0x00000104 /* RW-4R */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_STARTCOUNTER 0:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_STARTCOUNTER_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_STARTCOUNTER_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_SNAPONDEMAND 4:4 /* RWEVF */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_SNAPONDEMAND_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_PORTSTAT_SNAP_CONTROL_SNAPONDEMAND_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_BUFFER_READY 0x00000044 /* RW-4R */
#define NV_NPORT_CTRL_BUFFER_READY_BUFFERRDY 0:0 /* RWEVF */
#define NV_NPORT_CTRL_BUFFER_READY_BUFFERRDY_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_BUFFER_READY_BUFFERRDY_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_REQLINKID 0x00000054 /* RW-4R */
#define NV_NPORT_REQLINKID_REQROUTINGID 8:0 /* RWEVF */
#define NV_NPORT_REQLINKID_REQROUTINGID_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_REQLINKID_REQROUTINGLAN 18:15 /* RWEVF */
#define NV_NPORT_REQLINKID_REQROUTINGLAN_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_REQLINKID_REQROUTINGIDREMAP 21:21 /* RWEVF */
#define NV_NPORT_REQLINKID_REQROUTINGIDREMAP_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_REQLINKID_REQROUTINGIDREMAP_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_REQLINKID_REQROUTINGLANREMAP 22:22 /* RWEVF */
#define NV_NPORT_REQLINKID_REQROUTINGLANREMAP_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_REQLINKID_REQROUTINGLANREMAP_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_REQLINKID_MASKS 0x00000058 /* RW-4R */
#define NV_NPORT_REQLINKID_MASKS_REQROUTINGID_MASK 8:0 /* RWEVF */
#define NV_NPORT_REQLINKID_MASKS_REQROUTINGID_MASK_INIT 0x000001ff /* RWE-V */
#define NV_NPORT_REQLINKID_MASKS_REQROUTINGLAN_MASK 18:15 /* RWEVF */
#define NV_NPORT_REQLINKID_MASKS_REQROUTINGLAN_MASK_INIT 0x0000000f /* RWE-V */
#define NV_NPORT_CTRL 0x00000040 /* RW-4R */
#define NV_NPORT_CTRL_TRUNKLINKENB 0:0 /* RWEVF */
#define NV_NPORT_CTRL_TRUNKLINKENB_TRUNKLINK 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_TRUNKLINKENB_ACCESSLINK 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_EGDRAINENB 1:1 /* RWEVF */
#define NV_NPORT_CTRL_EGDRAINENB_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_EGDRAINENB_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_RTDRAINENB 2:2 /* RWEVF */
#define NV_NPORT_CTRL_RTDRAINENB_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_RTDRAINENB_DISABLE 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_ENDPOINT_COUNT 5:4 /* RWEVF */
#define NV_NPORT_CTRL_ENDPOINT_COUNT_512 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_ENDPOINT_COUNT_1024 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_ENDPOINT_COUNT_2048 0x00000003 /* RW--V */
#define NV_NPORT_CTRL_INHIBITRAMLOAD 8:8 /* RWEVF */
#define NV_NPORT_CTRL_INHIBITRAMLOAD_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_SPARE 13:9 /* RWEVF */
#define NV_NPORT_CTRL_SPARE_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_ENROUTEDBI 16:16 /* RWEVF */
#define NV_NPORT_CTRL_ENROUTEDBI_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_ENROUTEDBI_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_CTRL_ENEGRESSDBI 17:17 /* RWEVF */
#define NV_NPORT_CTRL_ENEGRESSDBI_ENABLE 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_ENEGRESSDBI_DISABLE 0x00000000 /* RW--V */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT 0x00000470 /* RW-4R */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_CORRECTABLEENABLE 0:0 /* RWEVF */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_CORRECTABLEENABLE_INIT 0x00000001 /* RWE-V */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_FATALENABLE 1:1 /* RWEVF */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_FATALENABLE_INIT 0x00000001 /* RWE-V */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_NONFATALENABLE 2:2 /* RWEVF */
#define NV_NPORT_ERR_CONTROL_COMMON_NPORT_NONFATALENABLE_INIT 0x00000001 /* RWE-V */
#define NV_NPORT_CTRL_STOP 0x00000048 /* RW-4R */
#define NV_NPORT_CTRL_STOP_INGRESS_STOP 0:0 /* RWEVF */
#define NV_NPORT_CTRL_STOP_INGRESS_STOP_STOP 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_STOP_INGRESS_STOP_ALLOWTRAFFIC 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_STOP_EGRESS_STOP 8:8 /* RWEVF */
#define NV_NPORT_CTRL_STOP_EGRESS_STOP_STOP 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_STOP_EGRESS_STOP_ALLOWTRAFFIC 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC 23:16 /* RWEVF */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_ALLOWTRAFFIC 0x00000000 /* RWE-V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC0 0x00000001 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC1 0x00000002 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC2 0x00000004 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC3 0x00000008 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC4 0x00000010 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC5 0x00000020 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC6 0x00000040 /* RW--V */
#define NV_NPORT_CTRL_STOP_ROUTE_STOP_VC_STOPVC7 0x00000080 /* RW--V */
#define NV_NPORT_CONTAIN_AND_DRAIN 0x0000005c /* RW-4R */
#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR 18:18 /* RWIVF */
#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR_ENABLE 0x00000001 /* RW--V */
#define NV_NPORT_CONTAIN_AND_DRAIN_CLEAR_DISABLE 0x00000000 /* RWI-V */
#define NV_NPORT_INITIALIZATION 0x0000004c /* RW-4R */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0 0:0 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_0_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1 1:1 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_1_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2 2:2 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_2_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3 3:3 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_3_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4 4:4 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_4_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5 5:5 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_5_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6 6:6 /* RWEVF */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_TAGPOOLINIT_6_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_LINKTABLEINIT 8:8 /* RWEVF */
#define NV_NPORT_INITIALIZATION_LINKTABLEINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_LINKTABLEINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_REMAPTABINIT 9:9 /* RWEVF */
#define NV_NPORT_INITIALIZATION_REMAPTABINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_REMAPTABINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_RIDTABINIT 10:10 /* RWEVF */
#define NV_NPORT_INITIALIZATION_RIDTABINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_RIDTABINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_INITIALIZATION_RLANTABINIT 11:11 /* RWEVF */
#define NV_NPORT_INITIALIZATION_RLANTABINIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_INITIALIZATION_RLANTABINIT_HWINIT 0x00000001 /* RW--V */
#define NV_NPORT_SCRATCH_WARM 0x00000fc0 /* RW-4R */
#define NV_NPORT_SCRATCH_WARM_DATA 31:0 /* RWEVF */
#define NV_NPORT_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
#define NV_NPORT_PORTSTAT_COUNT_LOW_1_0 0x00000154 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_LOW_1_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_LOW_1_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_0 0x0000015c /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_MEDIUM_1_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_0 0x00000164 /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_HIGH_1_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_0 0x0000016c /* R--4R */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_COUNT_PANIC_1_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_0 0x0000014c /* R--4R */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_0_PACKETCOUNT 31:0 /* R-EVF */
#define NV_NPORT_PORTSTAT_PACKET_COUNT_1_0_PACKETCOUNT_INIT 0x00000000 /* R-E-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1 0x00000140 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1 0x00000144 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1 0x00000148 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1 0x00000140 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_1_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1 0x00000144 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_1_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1 0x00000148 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_1_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_2 0x00000174 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_2_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_2_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_2_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2 0x00000178 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_2_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2 0x0000017c /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_2_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_3 0x000001a8 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_3_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_3_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_3_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3 0x000001ac /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_3_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3 0x000001b0 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_3_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_4 0x000001dc /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_4_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_4_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_4_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4 0x000001e0 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_4_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4 0x000001e4 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_4_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_5 0x00000210 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_5_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_5_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_5_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5 0x00000214 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_5_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5 0x00000218 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_5_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_6 0x00000244 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_6_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_6_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_6_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6 0x00000248 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_6_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6 0x0000024c /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_6_LIMIT__PROD 0x00000680 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_7 0x00000278 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_7_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_7_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_LOW_7_LIMIT__PROD 0x000000c0 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7 0x0000027c /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_MEDIUM_7_LIMIT__PROD 0x00000140 /* RW--V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7 0x00000280 /* RW-4R */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7_LIMIT 23:0 /* RWEVF */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7_LIMIT_INIT 0x00000000 /* RWE-V */
#define NV_NPORT_PORTSTAT_LIMIT_HIGH_7_LIMIT__PROD 0x00000680 /* RW--V */
#endif // __lr10_dev_nport_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nport_ip_addendum_h__
#define __lr10_dev_nport_ip_addendum_h__
// VC mapping
// IAS section 8.2.4.5 Table 40. LimeRock VC Error Encoding
#define NV_NPORT_VC_MAPPING_CREQ0 0x0
#define NV_NPORT_VC_MAPPING_RSP0 0x5
#define NV_NPORT_VC_MAPPING_CREQ1 0x6
#define NV_NPORT_VC_MAPPING_RSP1 0x7
#define NV_NPORT_SCRATCH_WARM_PORT_RESET_REQUIRED 0:0
#endif // __lr10_dev_nport_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nv_xp_h__
#define __lr10_dev_nv_xp_h__
/* This file is autogenerated. Do not edit */
#define NV_XP_LANE_ERROR_STATUS 0x0008D400 /* RW-4R */
#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_CODING_ERR 0:0 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_CODING_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_CODING_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_ORDER_ERR 1:1 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_ORDER_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_ORDER_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_OS_DATA_SEQ_ERR 2:2 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_OS_DATA_SEQ_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_OS_DATA_SEQ_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_TSX_DATA_SEQ_ERR 3:3 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_TSX_DATA_SEQ_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_TSX_DATA_SEQ_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_SKPOS_LFSR_ERR 4:4 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_SKPOS_LFSR_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_SKPOS_LFSR_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_RX_CLK_FIFO_OVERFLOW 5:5 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_RX_CLK_FIFO_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_RX_CLK_FIFO_OVERFLOW_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_ELASTIC_FIFO_OVERFLOW 6:6 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_ELASTIC_FIFO_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_ELASTIC_FIFO_OVERFLOW_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_RCVD_LINK_NUM_ERR 7:7 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_RCVD_LINK_NUM_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_RCVD_LINK_NUM_ERR_ACTIVE 0x00000000 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_RCVD_LANE_NUM_ERR 8:8 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_RCVD_LANE_NUM_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_RCVD_LANE_NUM_ERR_ACTIVE 0x00000000 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_SKP_RCV_SYM_ERR 9:9 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_SKP_RCV_SYM_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_SKP_RCV_SYM_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_SKPOS_PARITY_ERR 10:10 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_SKPOS_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_SKPOS_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_LOCAL_DATA_PARITY_ERR 11:11 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_LOCAL_DATA_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_LOCAL_DATA_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_FIRST_RETIMER_DATA_PARITY_ERR 12:12 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_FIRST_RETIMER_DATA_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_FIRST_RETIMER_DATA_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_SECOND_RETIMER_DATA_PARITY_ERR 13:13 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_SECOND_RETIMER_DATA_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_SECOND_RETIMER_DATA_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_CRC_ERR 14:14 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_CRC_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_CRC_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_PARITY_ERR 15:15 /* RWIVF */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XP_LANE_ERRORS_COUNT_0 0x0008D40C /* R--4R */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_0_VALUE 7:0 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_0_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_1_VALUE 15:8 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_1_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_2_VALUE 23:16 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_2_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_3_VALUE 31:24 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_0_LANE_3_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_1 0x0008D410 /* R--4R */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_4_VALUE 7:0 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_4_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_5_VALUE 15:8 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_5_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_6_VALUE 23:16 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_6_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_7_VALUE 31:24 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_7_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_2 0x0008D414 /* R--4R */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_8_VALUE 7:0 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_8_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_9_VALUE 15:8 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_9_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_10_VALUE 23:16 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_10_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_11_VALUE 31:24 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_11_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_3 0x0008D418 /* R--4R */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_12_VALUE 7:0 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_12_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_13_VALUE 15:8 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_13_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_14_VALUE 23:16 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_14_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_15_VALUE 31:24 /* R-IVF */
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_15_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_1_ENTRY_COUNT(i) (0x0008D910+(i)*4) /* R--4A */
#define NV_XP_L1_1_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_1_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_1_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_2_ENTRY_COUNT(i) (0x0008D950+(i)*4) /* R--4A */
#define NV_XP_L1_2_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_2_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_2_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_2_ABORT_COUNT(i) (0x0008D990+(i)*4) /* R--4A */
#define NV_XP_L1_2_ABORT_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_2_ABORT_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_2_ABORT_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT(i) (0x0008D9D0+(i)*4) /* R--4A */
#define NV_XP_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_SHORT_DURATION_COUNT(i) (0x0008E0C4+(i)*4) /* R--4A */
#define NV_XP_L1_SHORT_DURATION_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_SHORT_DURATION_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_SHORT_DURATION_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_RECEIVER_ERRORS_COUNT(i) (0x0008D440+(i)*4) /* R--4A */
#define NV_XP_RECEIVER_ERRORS_COUNT__SIZE_1 1 /* */
#define NV_XP_RECEIVER_ERRORS_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_RECEIVER_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_REPLAY_ROLLOVER_COUNT(i) (0x0008D5C0+(i)*4) /* R--4A */
#define NV_XP_REPLAY_ROLLOVER_COUNT__SIZE_1 1 /* */
#define NV_XP_REPLAY_ROLLOVER_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_REPLAY_ROLLOVER_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_BAD_DLLP_COUNT(i) (0x0008D6C0+(i)*4) /* R--4A */
#define NV_XP_BAD_DLLP_COUNT__SIZE_1 1 /* */
#define NV_XP_BAD_DLLP_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_BAD_DLLP_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_BAD_TLP_COUNT(i) (0x0008D700+(i)*4) /* R--4A */
#define NV_XP_BAD_TLP_COUNT__SIZE_1 1 /* */
#define NV_XP_BAD_TLP_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_BAD_TLP_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP__8B10B_ERRORS_COUNT 0x0008D404 /* R--4R */
#define NV_XP__8B10B_ERRORS_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP__8B10B_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_SYNC_HEADER_ERRORS_COUNT 0x0008D408 /* R--4R */
#define NV_XP_SYNC_HEADER_ERRORS_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_SYNC_HEADER_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_LCRC_ERRORS_COUNT(i) (0x0008D480+(i)*4) /* R--4A */
#define NV_XP_LCRC_ERRORS_COUNT__SIZE_1 1 /* */
#define NV_XP_LCRC_ERRORS_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_LCRC_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_FAILED_L0S_EXITS_COUNT(i) (0x0008D4C0+(i)*4) /* R--4A */
#define NV_XP_FAILED_L0S_EXITS_COUNT__SIZE_1 1 /* */
#define NV_XP_FAILED_L0S_EXITS_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_FAILED_L0S_EXITS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_NAKS_SENT_COUNT(i) (0x0008D500+(i)*4) /* R--4A */
#define NV_XP_NAKS_SENT_COUNT__SIZE_1 1 /* */
#define NV_XP_NAKS_SENT_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_NAKS_SENT_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_NAKS_RCVD_COUNT(i) (0x0008D540+(i)*4) /* R--4A */
#define NV_XP_NAKS_RCVD_COUNT__SIZE_1 1 /* */
#define NV_XP_NAKS_RCVD_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_NAKS_RCVD_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_NAKS_RCVD_COUNT_ILLOGICAL_VALUE 23:16 /* R-IVF */
#define NV_XP_NAKS_RCVD_COUNT_ILLOGICAL_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_TO_RECOVERY_COUNT(i) (0x0008D600+(i)*4) /* R--4A */
#define NV_XP_L1_TO_RECOVERY_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_TO_RECOVERY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_TO_RECOVERY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L0_TO_RECOVERY_COUNT(i) (0x0008D640+(i)*4) /* R--4A */
#define NV_XP_L0_TO_RECOVERY_COUNT__SIZE_1 1 /* */
#define NV_XP_L0_TO_RECOVERY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L0_TO_RECOVERY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_RECOVERY_COUNT(i) (0x0008D680+(i)*4) /* R--4A */
#define NV_XP_RECOVERY_COUNT__SIZE_1 1 /* */
#define NV_XP_RECOVERY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_RECOVERY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_CHIPSET_XMIT_L0S_ENTRY_COUNT(i) (0x0008D740+(i)*4) /* R--4A */
#define NV_XP_CHIPSET_XMIT_L0S_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_CHIPSET_XMIT_L0S_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_CHIPSET_XMIT_L0S_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_GPU_XMIT_L0S_ENTRY_COUNT(i) (0x0008D780+(i)*4) /* R--4A */
#define NV_XP_GPU_XMIT_L0S_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_GPU_XMIT_L0S_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_GPU_XMIT_L0S_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1_ENTRY_COUNT(i) (0x0008D7C0+(i)*4) /* R--4A */
#define NV_XP_L1_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_L1_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_L1P_ENTRY_COUNT(i) (0x0008D800+(i)*4) /* R--4A */
#define NV_XP_L1P_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_L1P_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_L1P_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_DEEP_L1_ENTRY_COUNT(i) (0x0008D840+(i)*4) /* R--4A */
#define NV_XP_DEEP_L1_ENTRY_COUNT__SIZE_1 1 /* */
#define NV_XP_DEEP_L1_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_DEEP_L1_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_ASLM_COUNT(i) (0x0008D880+(i)*4) /* R--4A */
#define NV_XP_ASLM_COUNT__SIZE_1 1 /* */
#define NV_XP_ASLM_COUNT_VALUE 15:0 /* R-IVF */
#define NV_XP_ASLM_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_XP_ERROR_COUNTER_RESET 0x0008D900 /* RWI4R */
#define NV_XP_ERROR_COUNTER_RESET_8B10B_ERRORS_COUNT 0:0 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_8B10B_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_8B10B_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_SYNC_HEADER_ERRORS_COUNT 1:1 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_SYNC_HEADER_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_SYNC_HEADER_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_LANE_ERRORS_COUNT 2:2 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_LANE_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_LANE_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_RECEIVER_ERRORS_COUNT 3:3 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_RECEIVER_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_RECEIVER_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_LCRC_ERRORS_COUNT 4:4 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_LCRC_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_LCRC_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_FAILED_L0S_EXITS_COUNT 5:5 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_FAILED_L0S_EXITS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_FAILED_L0S_EXITS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_NAKS_SENT_COUNT 6:6 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_NAKS_SENT_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_NAKS_SENT_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_NAKS_RCVD_COUNT 7:7 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_NAKS_RCVD_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_NAKS_RCVD_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_REPLAY_COUNT 8:8 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_REPLAY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_REPLAY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_REPLAY_ROLLOVER_COUNT 9:9 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_REPLAY_ROLLOVER_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_REPLAY_ROLLOVER_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_TO_RECOVERY_COUNT 10:10 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_TO_RECOVERY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_TO_RECOVERY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L0_TO_RECOVERY_COUNT 11:11 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L0_TO_RECOVERY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L0_TO_RECOVERY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_RECOVERY_COUNT 12:12 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_RECOVERY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_RECOVERY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_BAD_DLLP_COUNT 13:13 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_BAD_DLLP_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_BAD_DLLP_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_BAD_TLP_COUNT 14:14 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_BAD_TLP_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_BAD_TLP_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_CHIPSET_XMIT_L0S_ENTRY_COUNT 15:15 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_CHIPSET_XMIT_L0S_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_CHIPSET_XMIT_L0S_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_GPU_XMIT_L0S_ENTRY_COUNT 16:16 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_GPU_XMIT_L0S_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_GPU_XMIT_L0S_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_ENTRY_COUNT 17:17 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1P_ENTRY_COUNT 18:18 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1P_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1P_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_DEEP_L1_ENTRY_COUNT 19:19 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_DEEP_L1_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_DEEP_L1_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_ASLM_COUNT 20:20 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_ASLM_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_ASLM_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_SKPOS_ERRORS_COUNT 21:21 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_SKPOS_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_SKPOS_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_1_ENTRY_COUNT 22:22 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_1_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_1_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_2_ENTRY_COUNT 23:23 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_2_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_2_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_2_ABORT_COUNT 24:24 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_2_ABORT_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_2_ABORT_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT 25:25 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_ERROR_COUNTER_RESET_L1_SHORT_DURATION_COUNT 26:26 /* RWIVF */
#define NV_XP_ERROR_COUNTER_RESET_L1_SHORT_DURATION_COUNT_DONE 0x00000000 /* RWI-V */
#define NV_XP_ERROR_COUNTER_RESET_L1_SHORT_DURATION_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XP_PRI_XP3G_CG 0x0008E000 /* RWI4R */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_DLY_CNT__PROD 0x0000000B /* RW--V */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_EN 6:6 /* RWIVF */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XP_PRI_XP3G_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_XP_PRI_XP3G_CG_STATE_CG_EN 7:7 /* */
#define NV_XP_PRI_XP3G_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_XP_PRI_XP3G_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_XP_PRI_XP3G_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_STALL_CG_EN 14:14 /* RWIVF */
#define NV_XP_PRI_XP3G_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XP_PRI_XP3G_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XP_PRI_XP3G_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XP_PRI_XP3G_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_XP_PRI_XP3G_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_XP_PRI_XP3G_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
#define NV_XP_PRI_XP3G_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
#define NV_XP_PRI_XP3G_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_CNT 23:20 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_XP_PRI_XP3G_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_EN 28:28 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_PAUSE_CG_EN 30:30 /* */
#define NV_XP_PRI_XP3G_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_XP_PRI_XP3G_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_HALT_CG_EN 31:31 /* */
#define NV_XP_PRI_XP3G_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_XP_PRI_XP3G_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_XP_PRI_XP3G_CG1 0x0008E004 /* RWI4R */
#define NV_XP_PRI_XP3G_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_XP_PRI_XP3G_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XP_PRI_XP3G_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XP_PRI_XP3G_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XP_REPLAY_COUNT(i) (0x0008D580+(i)*4) /* R--4A */
#define NV_XP_REPLAY_COUNT__SIZE_1 1 /* */
#define NV_XP_REPLAY_COUNT_VALUE 31:0 /* R-IVF */
#define NV_XP_REPLAY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
#endif // __lr10_dev_nv_xp_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nv_xve_h__
#define __lr10_dev_nv_xve_h__
/* This file is autogenerated. Do not edit */
#define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */
#define NV_XVE_ERROR_COUNTER1 0x00000854 /* R--4R */
#define NV_XVE_ERROR_COUNTER1_CORR_ERROR_COUNT_VALUE 15:0 /* R-XVF */
#define NV_XVE_ERROR_COUNTER 0x000004AC /* R--4R */
#define NV_XVE_ERROR_COUNTER_RSVD_CORR_ERROR_COUNT_VALUE 7:0 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RSVD_CORR_ERROR_COUNT_VALUE_INIT 0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_NON_FATAL_ERROR_COUNT_VALUE 15:8 /* R-XVF */
#define NV_XVE_ERROR_COUNTER_FATAL_ERROR_COUNT_VALUE 23:16 /* R-XVF */
#define NV_XVE_ERROR_COUNTER_UNSUPP_REQ_COUNT_VALUE 31:24 /* R-XVF */
#define NV_XVE_PRI_XVE_CG 0x000004E8 /* RWI4R */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_EN 6:6 /* RWIVF */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG_STATE_CG_EN 7:7 /* */
#define NV_XVE_PRI_XVE_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_XVE_PRI_XVE_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_XVE_PRI_XVE_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_STALL_CG_EN 14:14 /* RWIVF */
#define NV_XVE_PRI_XVE_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PRI_XVE_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
#define NV_XVE_PRI_XVE_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_CNT 23:20 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_XVE_PRI_XVE_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_EN 28:28 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN 30:30 /* */
#define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_HALT_CG_EN 31:31 /* */
#define NV_XVE_PRI_XVE_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_XVE_PRI_XVE_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_XVE_PRI_XVE_CG1 0x000004EC /* RWI4R */
#define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG1_SLCG 17:1 /* RWIVF */
#define NV_XVE_PRI_XVE_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG1_SLCG_DISABLED 0x0001FFFF /* RWI-V */
#define NV_XVE_PRI_XVE_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_XVE_CYA_2 0x00000704 /* RW-4R */
#define NV_XVE_CYA_2_RSVD 31:0 /* RWCVF */
#define NV_XVE_CYA_2_RSVD_INIT 0x00000000 /* RWC-V */
#endif // __lr10_dev_nv_xve_h__

113
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvlctrl_ip_h__
#define __lr10_dev_nvlctrl_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLCTRL_LINK_INTR_0_STATUS(i) (0x00000304+(i)*0x40) /* R--4A */
#define NV_NVLCTRL_LINK_INTR_0_STATUS__SIZE_1 4 /* */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_FATAL 0:0 /* R-EVF */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_FATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_NONFATAL 1:1 /* R-EVF */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_CORRECTABLE 2:2 /* R-EVF */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_INTR0 3:3 /* R-EVF */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_INTR1 4:4 /* R-EVF */
#define NV_NVLCTRL_LINK_INTR_0_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
#define NV_NVLCTRL_PLL_PRI_CLOCK_GATING 0x00000604 /* RW-4R */
#define NV_NVLCTRL_PLL_PRI_CLOCK_GATING_CG1_SLCG 0:0 /* RWEVF */
#define NV_NVLCTRL_PLL_PRI_CLOCK_GATING_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_NVLCTRL_PLL_PRI_CLOCK_GATING_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */
#define NV_NVLCTRL_PLL_PRI_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_NVLCTRL_COMMON_INTR_0_MASK 0x00000220 /* RW-4R */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_FATAL 0:0 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_FATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_NONFATAL 1:1 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_CORRECTABLE 2:2 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_INTR0 3:3 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_INTR0_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_INTR1 4:4 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_0_MASK_INTR1_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_1_MASK 0x00000228 /* RW-4R */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_FATAL 0:0 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_FATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_NONFATAL 1:1 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_CORRECTABLE 2:2 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_INTR0 3:3 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_INTR0_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_INTR1 4:4 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_1_MASK_INTR1_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_2_MASK 0x00000230 /* RW-4R */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_FATAL 0:0 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_FATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_NONFATAL 1:1 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_CORRECTABLE 2:2 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_INTR0 3:3 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_INTR0_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_INTR1 4:4 /* RWIVF */
#define NV_NVLCTRL_COMMON_INTR_2_MASK_INTR1_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_0_MASK(i) (0x00000300+(i)*0x40) /* RW-4A */
#define NV_NVLCTRL_LINK_INTR_0_MASK__SIZE_1 4 /* */
#define NV_NVLCTRL_LINK_INTR_0_MASK_FATAL 0:0 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_0_MASK_FATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_0_MASK_NONFATAL 1:1 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_0_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_0_MASK_CORRECTABLE 2:2 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_0_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_0_MASK_INTR0 3:3 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_0_MASK_INTR0_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_0_MASK_INTR1 4:4 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_0_MASK_INTR1_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_1_MASK(i) (0x00000308+(i)*0x40) /* RW-4A */
#define NV_NVLCTRL_LINK_INTR_1_MASK__SIZE_1 4 /* */
#define NV_NVLCTRL_LINK_INTR_1_MASK_FATAL 0:0 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_1_MASK_FATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_1_MASK_NONFATAL 1:1 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_1_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_1_MASK_CORRECTABLE 2:2 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_1_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_1_MASK_INTR0 3:3 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_1_MASK_INTR0_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_1_MASK_INTR1 4:4 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_1_MASK_INTR1_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_2_MASK(i) (0x00000310+(i)*0x40) /* RW-4A */
#define NV_NVLCTRL_LINK_INTR_2_MASK__SIZE_1 4 /* */
#define NV_NVLCTRL_LINK_INTR_2_MASK_FATAL 0:0 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_2_MASK_FATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_2_MASK_NONFATAL 1:1 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_2_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_2_MASK_CORRECTABLE 2:2 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_2_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_2_MASK_INTR0 3:3 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_2_MASK_INTR0_INIT 0x00000000 /* RWI-V */
#define NV_NVLCTRL_LINK_INTR_2_MASK_INTR1 4:4 /* RWIVF */
#define NV_NVLCTRL_LINK_INTR_2_MASK_INTR1_INIT 0x00000000 /* RWI-V */
#endif // __lr10_dev_nvlctrl_ip_h__

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src/common/inc/swref/published/nvswitch/lr10/dev_nvldl_ip.h Normal file
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@@ -0,0 +1,350 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvldl_ip_h__
#define __lr10_dev_nvldl_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLDL_TOP_LINK_STATE 0x00000000 /* R--4R */
#define NV_NVLDL_TOP_LINK_STATE_STATE 7:0 /* R-XVF */
#define NV_NVLDL_TOP_LINK_STATE_STATE_INIT 0x00000000 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_HWCFG 0x00000001 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_SWCFG 0x00000002 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_ACTIVE 0x00000003 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_FAULT 0x00000004 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_SLEEP 0x00000005 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_RCVY_AC 0x00000008 /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_RCVY_RX 0x0000000a /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_STATE_TRAIN 0x0000000b /* R---V */
#define NV_NVLDL_TOP_LINK_STATE_AN0_BUSY 12:12 /* R-XVF */
#define NV_NVLDL_TOP_LINK_STATE_TL_BUSY 13:13 /* R-XVF */
#define NV_NVLDL_TOP_LINK_STATE_DBG_SUBSTATE 31:16 /* R-XVF */
#define NV_NVLDL_TOP_LINK_CHANGE 0x00000040 /* RW-4R */
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS 1:0 /* R-XVF */
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS_DONE 0x00000000 /* R---V */
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS_BUSY 0x00000001 /* R---V */
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS_FAULT 0x00000002 /* R---V */
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS_ABORT 0x00000003 /* R---V */
#define NV_NVLDL_TOP_LINK_CHANGE_ACTION 3:2 /* -WXVF */
#define NV_NVLDL_TOP_LINK_CHANGE_ACTION_LTSSM_CHANGE 0x00000001 /* -W--V */
#define NV_NVLDL_TOP_LINK_CHANGE_ACTION_LTSSM_FORCE 0x00000003 /* -W--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE 7:4 /* RWEVF */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_HWCFG 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_SWCFG 0x00000002 /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_ACTIVE 0x00000003 /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_RCVY_AC 0x00000008 /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_FAULT 0x00000004 /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_RCVY_RX 0x0000000a /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_SLEEP 0x00000005 /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_TRAIN 0x0000000b /* RW--V */
#define NV_NVLDL_TOP_LINK_CHANGE_OLDSTATE_MASK 19:16 /* RWEVF */
#define NV_NVLDL_TOP_LINK_CHANGE_OLDSTATE_MASK_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_LINK_CHANGE_OLDSTATE_MASK_DONTCARE 0x0000000f /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE 0x00000044 /* RW-4R */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS 1:0 /* R-EVF */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS_DONE 0x00000000 /* R-E-V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS_BUSY 0x00000001 /* R---V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS_FAULT 0x00000002 /* R---V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS_ABORT 0x00000003 /* R---V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_ACTION 3:2 /* -WEVF */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_ACTION_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_ACTION_SLSM_CHANGE 0x00000001 /* -W--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_ACTION_SLSM_FORCE 0x00000003 /* -W--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE 7:4 /* RWEUF */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_HS 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_EIGHTH 0x00000004 /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_TRAIN 0x00000005 /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_SAFE 0x00000006 /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_OFF 0x00000007 /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_SUBLINK 15:12 /* RWEUF */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_SUBLINK_TX 0x00000000 /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_SUBLINK_RX 0x00000001 /* RWE-V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_OLDSTATE_MASK 19:16 /* RWEUF */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_OLDSTATE_MASK_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_OLDSTATE_MASK_DONTCARE 0x0000000f /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_COUNTDOWN 31:20 /* RWEUF */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_COUNTDOWN_MAXIMUM 0x0000007f /* RW--V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_COUNTDOWN_MINIMUM 0x00000008 /* RWE-V */
#define NV_NVLDL_TOP_SUBLINK_CHANGE_COUNTDOWN_IMMEDIATE 0x00000000 /* RW--V */
#define NV_NVLDL_TOP_LINK_TEST 0x00000048 /* RW-4R */
#define NV_NVLDL_TOP_LINK_TEST_MODE 0:0 /* RWEVF */
#define NV_NVLDL_TOP_LINK_TEST_MODE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_LINK_TEST_MODE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_LINK_TEST_AUTO_HWCFG 30:30 /* RWEVF */
#define NV_NVLDL_TOP_LINK_TEST_AUTO_HWCFG_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_LINK_TEST_AUTO_HWCFG_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_LINK_TEST_AUTO_NVHS 31:31 /* RWEVF */
#define NV_NVLDL_TOP_LINK_TEST_AUTO_NVHS_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_LINK_TEST_AUTO_NVHS_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR 0x00000050 /* RW-4R */
#define NV_NVLDL_TOP_INTR_TX_REPLAY 0:0 /* RWXVF */
#define NV_NVLDL_TOP_INTR_TX_RECOVERY_SHORT 1:1 /* RWXVF */
#define NV_NVLDL_TOP_INTR_TX_FAULT_RAM 4:4 /* RWXVF */
#define NV_NVLDL_TOP_INTR_TX_FAULT_INTERFACE 5:5 /* RWXVF */
#define NV_NVLDL_TOP_INTR_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWXVF */
#define NV_NVLDL_TOP_INTR_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWXVF */
#define NV_NVLDL_TOP_INTR_RX_FAULT_DL_PROTOCOL 20:20 /* RWXVF */
#define NV_NVLDL_TOP_INTR_RX_SHORT_ERROR_RATE 21:21 /* RWXVF */
#define NV_NVLDL_TOP_INTR_RX_LONG_ERROR_RATE 22:22 /* RWXVF */
#define NV_NVLDL_TOP_INTR_RX_ILA_TRIGGER 23:23 /* RWXVF */
#define NV_NVLDL_TOP_INTR_RX_CRC_COUNTER 24:24 /* RWXVF */
#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_DOWN 27:27 /* RWXVF */
#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_UP 28:28 /* RWXVF */
#define NV_NVLDL_TOP_INTR_LTSSM_PROTOCOL 29:29 /* RWXVF */
#define NV_NVLDL_TOP_INTR_MINION_REQUEST 30:30 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2 0x00000054 /* RW-4R */
#define NV_NVLDL_TOP_INTR_SW2_TX_REPLAY 0:0 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_RECOVERY_SHORT 1:1 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_RAM 4:4 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_INTERFACE 5:5 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_DL_PROTOCOL 20:20 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_SHORT_ERROR_RATE 21:21 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_LONG_ERROR_RATE 22:22 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_ILA_TRIGGER 23:23 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_RX_CRC_COUNTER 24:24 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_DOWN 27:27 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_UP 28:28 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_PROTOCOL 29:29 /* RWXVF */
#define NV_NVLDL_TOP_INTR_SW2_MINION_REQUEST 30:30 /* RWXVF */
#define NV_NVLDL_TOP_INTR_STALL_EN 0x00000058 /* RW-4R */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_REPLAY 0:0 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_REPLAY_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT 1:1 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM 4:4 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE 5:5 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE 22:22 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER 23:23 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER 24:24 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN 27:27 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP 28:28 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL 29:29 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST 30:30 /* RWEVF */
#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN 0x0000005c /* RW-4R */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_REPLAY 0:0 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_REPLAY_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT 1:1 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM 4:4 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE 5:5 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE 22:22 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER 23:23 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER 24:24 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN 27:27 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP 28:28 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL 29:29 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST 30:30 /* RWEVF */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL 0x00000080 /* -W-4R */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_CLEAR_RECOVERY 2:2 /* -WXVF */
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_CLEAR_RECOVERY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_TX_TRAIN0_TX 0x00002018 /* RW-4R */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0 10:0 /* RWEVF */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_INIT 0x00000260 /* RWE-V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_MINIMUM 0x00000001 /* RW--V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0__PROD_ISSC 0x00000648 /* RW--V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_SCL 15:11 /* RWEVF */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_SCL_INIT 0x00000004 /* RWE-V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_SCL_MINIMUM 0x00000000 /* RW--V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_SCL__PROD_ISSC 0x00000005 /* RW--V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_INFINITE 31:31 /* RWEVF */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_INFINITE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_INFINITE_ON 0x00000001 /* RW--V */
#define NV_NVLDL_TX_SLSM_STATUS_TX 0x00002024 /* R--4R */
#define NV_NVLDL_TX_SLSM_STATUS_TX_SUBSTATE 3:0 /* R-XVF */
#define NV_NVLDL_TX_SLSM_STATUS_TX_SUBSTATE_STABLE 0x00000000 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE 7:4 /* R-XVF */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_HS 0x00000000 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_EIGHTH 0x00000004 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN 0x00000005 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_SAFE 0x00000006 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_OFF 0x00000007 /* R---V */
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_UNKNOWN 0x0000000d /* R---V */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL 0x00002280 /* -W-4R */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY 8:8 /* -WXVF */
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_CONFIG_RX 0x00003000 /* RW-4R */
#define NV_NVLDL_RX_CONFIG_RX_HW_POLARITY_INVERT 3:0 /* R-EVF */
#define NV_NVLDL_RX_CONFIG_RX_HW_POLARITY_INVERT_NONE 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_CONFIG_RX_HW_POLARITY_INVERT_ALL 0x0000000f /* R---V */
#define NV_NVLDL_RX_CONFIG_RX_FIFO_WR_REQ_DELAY 7:4 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_FIFO_WR_REQ_DELAY_INIT 0x0000000a /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_HW_LANE_REVERSE 8:8 /* R-EVF */
#define NV_NVLDL_RX_CONFIG_RX_HW_LANE_REVERSE_OFF 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_CONFIG_RX_HW_LANE_REVERSE_ON 0x00000001 /* R---V */
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_INVERT 19:16 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_INVERT_NONE 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_INVERT_ALL 0x0000000f /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_ECC_MODE 23:22 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_ECC_MODE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_ECC_MODE_ECC96 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_ECC_MODE_ECC88 0x00000002 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_LANE_REVERSE 24:24 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_LANE_REVERSE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_LANE_REVERSE_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_IOBIST_EN 25:25 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_IOBIST_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_IOBIST_EN_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_PHY_NO_ADJUST 26:26 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_PHY_NO_ADJUST_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_PHY_NO_ADJUST_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_PHY_ADJUST_OVERRIDE 27:27 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_PHY_ADJUST_OVERRIDE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_PHY_ADJUST_OVERRIDE_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_OVERRIDE 28:28 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_OVERRIDE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_OVERRIDE_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_REVERSAL_OVERRIDE 29:29 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_REVERSAL_OVERRIDE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_REVERSAL_OVERRIDE_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_SKIP_TOGGLE_CONST 30:30 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_SKIP_TOGGLE_CONST_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_SKIP_TOGGLE_CONST_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_CONFIG_RX_DEBUG_ENABLE 31:31 /* RWEVF */
#define NV_NVLDL_RX_CONFIG_RX_DEBUG_ENABLE_OFF 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_CONFIG_RX_DEBUG_ENABLE_ON 0x00000001 /* RW--V */
#define NV_NVLDL_RX_SLSM_STATUS_RX 0x00003014 /* R--4R */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE 3:0 /* R-EVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE_STABLE 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE 7:4 /* R-XVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_HS 0x00000000 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_EIGHTH 0x00000004 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN 0x00000005 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_SAFE 0x00000006 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_OFF 0x00000007 /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_UNKNOWN 0x0000000d /* R---V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SURPRISE_LD_CNT 15:8 /* R-EVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_SURPRISE_LD_CNT_INIT 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS 31:31 /* R-EVF */
#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS_OFF 0x00000000 /* R-E-V */
#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS_ON 0x00000001 /* R---V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL 0x00003280 /* RW-4R */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC 0:0 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC 1:1 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES 2:2 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY 3:3 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS 4:4 /* -WEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS_INIT 0x00000000 /* -WE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS_CLEAR 0x00000001 /* -W--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE 8:8 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE 9:9 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE 10:10 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE_FLIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE_SEQUENCE 0x00000001 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE 11:11 /* RWEVF */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE_FLIT 0x00000000 /* RW--V */
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE_SEQUENCE 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL 0x00003284 /* RW-4R */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN 2:0 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_EXP 3:3 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_EXP_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_MAN 6:4 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_MAN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP 11:8 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP_INIT 0x00000006 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_MAN 18:16 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_MAN_INIT 0x00000001 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_EXP 19:19 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_EXP_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_MAN 22:20 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_MAN_INIT 0x00000000 /* RWE-V */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_EXP 28:24 /* RWEUF */
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_EXP_INIT 0x00000006 /* RWE-V */
#endif // __lr10_dev_nvldl_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvldl_ip_addendum_h__
#define __lr10_dev_nvldl_ip_addendum_h__
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK1_INITPLL_LINK_STATE 0:0
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK1_INITPLL_LINK_STATE_DONE 0x1
#endif // __lr10_dev_nvldl_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvlipt_ip_h__
#define __lr10_dev_nvlipt_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLIPT_COMMON_ERR_STATUS_0 0x00000280 /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_CLKCTL_ILLEGAL_REQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_RSTSEQ_PLL_TIMEOUT 1:1 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_RSTSEQ_PLL_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_RSTSEQ_PLL_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_RSTSEQ_PHYARB_TIMEOUT 2:2 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_RSTSEQ_PHYARB_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_STATUS_0_RSTSEQ_PHYARB_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0 0x00000288 /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_CLKCTL_ILLEGAL_REQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PLL_TIMEOUT 1:1 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PLL_TIMEOUT__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PLL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PLL_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYARB_TIMEOUT 2:2 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYARB_TIMEOUT__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYARB_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYARB_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0 0x00000294 /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_CLKCTL_ILLEGAL_REQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PLL_TIMEOUT 1:1 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PLL_TIMEOUT__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PLL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PLL_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PHYARB_TIMEOUT 2:2 /* RWEVF */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PHYARB_TIMEOUT__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PHYARB_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_ERR_CONTAIN_EN_0_RSTSEQ_PHYARB_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0 0x00000298 /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_CLKCTL_ILLEGAL_REQUEST_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_CLKCTL_ILLEGAL_REQUEST_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_RSTSEQ_PLL_TIMEOUT 1:1 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_RSTSEQ_PLL_TIMEOUT_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_RSTSEQ_PLL_TIMEOUT_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_RSTSEQ_PHYARB_TIMEOUT 2:2 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_RSTSEQ_PHYARB_TIMEOUT_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_REPORT_INJECT_0_RSTSEQ_PHYARB_TIMEOUT_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0 0x0000029c /* RW-4R */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST 0:0 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_CLKCTL_ILLEGAL_REQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_RSTSEQ_PLL_TIMEOUT 1:1 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_RSTSEQ_PLL_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_RSTSEQ_PLL_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_RSTSEQ_PHYARB_TIMEOUT 2:2 /* RWIVF */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_RSTSEQ_PHYARB_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_COMMON_ERR_FIRST_0_RSTSEQ_PHYARB_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON 0x00000300 /* RW-4R */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT0_EN 0:0 /* RWEVF */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT0_EN_INIT 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT1_EN 1:1 /* RWEVF */
#define NV_NVLIPT_COMMON_INTR_CONTROL_COMMON_INT1_EN_INIT 0x00000000 /* RWE-V */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_LO 0x00000108 /* R--4R */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_LO_SID_31_0 31:0 /* R-IVF */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_LO_SID_31_0_INIT 0x00000000 /* R-I-V */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_HI 0x0000010c /* R--4R */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_HI_SID_63_32 31:0 /* R-IVF */
#define NV_NVLIPT_COMMON_TOPOLOGY_LOCAL_CHIP_SID_HI_SID_63_32_INIT 0x00000000 /* R-I-V */
#endif // __lr10_dev_nvlipt_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvlipt_lnk_ip_h__
#define __lr10_dev_nvlipt_lnk_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL 0x00000090 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL 1:0 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL_L0 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL_L3 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL_TX 0x00000002 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_SEL_OFF 0x00000003 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_SEL 4:3 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_SEL_PLL_CLK 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_SEL_ALT_CLK 0x00000001 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_SEL_OFF 0x00000003 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS 17:16 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS_L0 0x00000000 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS_L3 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS_TX 0x00000002 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_STS_OFF 0x00000003 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_STS 20:19 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_STS_PLL_CLK 0x00000000 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_STS_ALT_CLK 0x00000001 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_TXCLK_STS_OFF 0x00000003 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR 24:24 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_OFF 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_ON 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_STS 25:25 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_STS_OFF 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_PLL_PWR_STS_ON 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_HW_DISABLE 31:31 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_HW_DISABLE_OFF 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_CLK_CTRL_RXCLK_HW_DISABLE_ON 0x00000001 /* RWE-V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE 0x00000104 /* RW-4R */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE 7:0 /* RWIVF */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV2P1TUR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV3P0AMP 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_NV3P0LRK 0x00000003 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_BB3P0P9P 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_TYPE_TYPE_BB3P0P10 0x00000005 /* RW--V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_LINK_INFO 0x00000110 /* RW-4R */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_LINK_INFO_LINK_NUMBER 7:0 /* RWIVF */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_LINK_INFO_LINK_NUMBER_INIT 0x000000ff /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0 0x00000280 /* RW-4R */
#define NV_NVLIPT_LNK_ERR_STATUS_0_SLEEPWHILEACTIVELINK 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_SLEEPWHILEACTIVELINK_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_SLEEPWHILEACTIVELINK_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_ILLEGALLINKSTATEREQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_ILLEGALLINKSTATEREQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_FAILEDMINIONREQUEST 2:2 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_FAILEDMINIONREQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_FAILEDMINIONREQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RESERVEDREQUESTVALUE 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RESERVEDREQUESTVALUE_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RESERVEDREQUESTVALUE_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINKSTATEWRITEWHILEBUSY_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINKSTATEWRITEWHILEBUSY_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINK_STATE_REQUEST_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_LINK_STATE_REQUEST_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_PHYCTL_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_PHYCTL_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_CLKCTL_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_STATUS_0_RSTSEQ_CLKCTL_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0 0x00000288 /* RW-4R */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK 0:0 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST 2:2 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE 3:3 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0 0x0000028c /* RW-4R */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK 0:0 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_SLEEPWHILEACTIVELINK_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_ILLEGALLINKSTATEREQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST 2:2 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_FAILEDMINIONREQUEST_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE 3:3 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RESERVEDREQUESTVALUE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINKSTATEWRITEWHILEBUSY_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_LINK_STATE_REQUEST_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR__PROD 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_PHYCTL_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWEVF */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_ERR_NON_FATAL_REPORT_EN_0_RSTSEQ_CLKCTL_TIMEOUT_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0 0x00000298 /* RW-4R */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_SLEEPWHILEACTIVELINK 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_SLEEPWHILEACTIVELINK_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_SLEEPWHILEACTIVELINK_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_ILLEGALLINKSTATEREQUEST_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_ILLEGALLINKSTATEREQUEST_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_FAILEDMINIONREQUEST 2:2 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_FAILEDMINIONREQUEST_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_FAILEDMINIONREQUEST_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_RESERVEDREQUESTVALUE 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_RESERVEDREQUESTVALUE_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_RESERVEDREQUESTVALUE_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_LINKSTATEWRITEWHILEBUSY_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_LINKSTATEWRITEWHILEBUSY_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_LINK_STATE_REQUEST_TIMEOUT_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_LINK_STATE_REQUEST_TIMEOUT_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_RSTSEQ_PHYCTL_TIMEOUT_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_RSTSEQ_PHYCTL_TIMEOUT_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_RSTSEQ_CLKCTL_TIMEOUT_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_REPORT_INJECT_0_RSTSEQ_CLKCTL_TIMEOUT_INSERT 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0 0x0000029c /* RW-4R */
#define NV_NVLIPT_LNK_ERR_FIRST_0_SLEEPWHILEACTIVELINK 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_SLEEPWHILEACTIVELINK_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_SLEEPWHILEACTIVELINK_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_ILLEGALLINKSTATEREQUEST 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_ILLEGALLINKSTATEREQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_ILLEGALLINKSTATEREQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_FAILEDMINIONREQUEST 2:2 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_FAILEDMINIONREQUEST_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_FAILEDMINIONREQUEST_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RESERVEDREQUESTVALUE 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RESERVEDREQUESTVALUE_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RESERVEDREQUESTVALUE_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINKSTATEWRITEWHILEBUSY 4:4 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINKSTATEWRITEWHILEBUSY_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINKSTATEWRITEWHILEBUSY_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINK_STATE_REQUEST_TIMEOUT 5:5 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINK_STATE_REQUEST_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_LINK_STATE_REQUEST_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR 6:6 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_WRITE_TO_LOCKED_SYSTEM_REG_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_PHYCTL_TIMEOUT 7:7 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_PHYCTL_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_PHYCTL_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_CLKCTL_TIMEOUT 8:8 /* RWIVF */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_CLKCTL_TIMEOUT_NONE 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_ERR_FIRST_0_RSTSEQ_CLKCTL_TIMEOUT_CLEAR 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK 0x00000300 /* RW-4R */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT0_EN 0:0 /* RWEVF */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT0_EN_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT0_EN_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT1_EN 1:1 /* RWEVF */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT1_EN_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_INTR_CONTROL_LINK_INT1_EN_ENABLE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET 0x00000380 /* RW-4R */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET 0:0 /* RWEVF */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_DEASSERT 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_ASSERT 0x00000001 /* RWE-V */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_STATUS 1:1 /* R-EVF */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_STATUS_DEASSERTED 0x00000000 /* R---V */
#define NV_NVLIPT_LNK_RESET_RSTSEQ_LINK_RESET_LINK_RESET_STATUS_ASSERTED 0x00000001 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST 0x00000480 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST 3:0 /* RWEVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_NOP 0x00000000 /* RWE-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_ACTIVE 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_L2 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_EMPTY 0x00000008 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET 0x00000009 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS 15:8 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_INIT 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_REQUEST_SUCCESSFUL 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_ILLEGAL_STATE_REQUEST 0x00000002 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_RESET_SEQ_TIMEOUT 0x00000003 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_NOT_ENABLED 0x00000004 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_REQUEST_TIMEOUT 0x00000005 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL 0x00000080 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_ERR 30:30 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_ERR_NOERR 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_ERR_ERR 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_READY 31:31 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_READY_INIT 0x00000001 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS 0x00000484 /* R--4R */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE 3:0 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_ACTIVE 0x00000001 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_L2 0x00000002 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_EMPTY 0x00000008 /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_RESET 0x00000009 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_CONTAIN 0x0000000e /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_DISABLE 0x0000000f /* R---V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_TXTLBUFFEREMPTY 8:8 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_TXTLBUFFEREMPTY_INIT 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_TXREPLAYBUFFEREMPTY 9:9 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_TXREPLAYBUFFEREMPTY_INIT 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RXTLBUFFEREMPTY 11:11 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RXTLBUFFEREMPTY_INIT 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RMTTXBUFFEREMPTY 13:13 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RMTTXBUFFEREMPTY_INIT 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RMTRXBUFFEREMPTY 14:14 /* R-EVF */
#define NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_RMTRXBUFFEREMPTY_INIT 0x00000000 /* R-E-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL 0x00000600 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_LINK_DISABLE 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_LINK_DISABLE_ENABLED 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_LINK_DISABLE_DISABLED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_1 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_1_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_2 2:2 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_2_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_3 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_3_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_4 4:4 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_4_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_5 5:5 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_5_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_6 6:6 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_6_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_7 7:7 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_7_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_8 8:8 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_8_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_9 9:9 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_9_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_10 10:10 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_10_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_11 11:11 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_11_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_12 12:12 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_12_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_13 13:13 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_13_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_14 14:14 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_14_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_15 15:15 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_MODE_CTRL_RESERVED_15_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL 0x0000060c /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_REFERENCE_CLOCK_MODE 1:0 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_REFERENCE_CLOCK_MODE_COMMON 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_REFERENCE_CLOCK_MODE_RESERVED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_REFERENCE_CLOCK_MODE_NON_COMMON_NO_SS 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_REFERENCE_CLOCK_MODE_NON_COMMON_SS 0x00000003 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_REFERENCE_CLOCK_FREQUENCY 5:4 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_REFERENCE_CLOCK_FREQUENCY_156_25_MHZ 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_REFERENCE_CLOCK_FREQUENCY_150_00_MHZ 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE 15:8 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_50_00000_GBPS 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_16_00000_GBPS 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_20_00000_GBPS 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_25_00000_GBPS 0x00000003 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_25_78125_GBPS 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_32_00000_GBPS 0x00000005 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_40_00000_GBPS 0x00000006 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_53_12500_GBPS 0x00000007 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CLK_CTRL_LINE_RATE_ILLEGAL_LINE_RATE 0x000000ff /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL 0x00000618 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_AC_DC_MODE 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_AC_DC_MODE_AC 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_AC_DC_MODE_DC 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_LINE_CODE_MODE 2:1 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_LINE_CODE_MODE_NRZ 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_LINE_CODE_MODE_NRZ_128B130 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_LINE_CODE_MODE_PAM4 0x00000003 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_RECEIVER_DETECT_ENABLE 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_RECEIVER_DETECT_ENABLE_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_RECEIVER_DETECT_ENABLE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_BLOCK_CODE_MODE 7:6 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_BLOCK_CODE_MODE_OFF 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_BLOCK_CODE_MODE_ECC96_ENABLED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_BLOCK_CODE_MODE_ECC88_ENABLED 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT 10:8 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT_INIT 0x00000005 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT_FOMA 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT_FOMB 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_FOM_FORMAT_FOMC 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM 18:11 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_INIT 0x00000017 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A0 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A1 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A2 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A3 0x00000008 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A4 0x00000010 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A5 0x00000020 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A6 0x00000040 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_OPTIMIZATION_ALGORITHM_A7 0x00000080 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM 23:19 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_INIT 0x00000003 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_B0 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_B1 0x00000002 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_B2 0x00000004 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_ADJUSTMENT_ALGORITHM_B3 0x00000008 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA 27:24 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_MINIMUM_TRAIN_TIME_MANTISSA_INIT 0x00000002 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT 31:28 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT_INIT 0x00000003 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2 0x00000624 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESTORE_PHY_TRAINING_PARAMS 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESTORE_PHY_TRAINING_PARAMS_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESTORE_PHY_TRAINING_PARAMS_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_1 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_1_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_2 2:2 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_2_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_3 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_3_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_4 4:4 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_4_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_5 5:5 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_5_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_6 6:6 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_6_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_7 7:7 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_7_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_8 8:8 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_8_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_9 9:9 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_9_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_10 10:10 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_10_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_11 11:11 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_11_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_12 12:12 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_12_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_13 13:13 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_13_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_14 14:14 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_14_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_15 15:15 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_15_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_16 16:16 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_16_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_17 17:17 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_17_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_18 18:18 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_18_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_19 19:19 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_19_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_20 20:20 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_20_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_21 21:21 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_21_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_22 22:22 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_22_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_23 23:23 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_23_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_24 24:24 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_24_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_25 25:25 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_25_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_26 26:26 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_26_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_27 27:27 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_27_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_28 28:28 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_28_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_29 29:29 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_29_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_30 30:30 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_30_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_31 31:31 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_CHANNEL_CTRL2_RESERVED_31_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL 0x00000638 /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_SL_ENABLE 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_SL_ENABLE_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_SL_ENABLE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_1 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_1_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L2_ENABLE 2:2 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L2_ENABLE_ENABLE 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_PWRM_L2_ENABLE_DISABLE 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_3 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SYSTEM_LINK_AN1_CTRL_RESERVED_3_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_LO 0x00000108 /* RW-4R */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_LO_SID_31_0 31:0 /* RWIVF */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_LO_SID_31_0_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_HI 0x0000010c /* RW-4R */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_HI_SID_63_32 31:0 /* RWIVF */
#define NV_NVLIPT_LNK_TOPOLOGY_REMOTE_CHIP_SID_HI_SID_63_32_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL 0x0000064c /* RW-4R */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_LINK_DISABLE 0:0 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_LINK_DISABLE_ENABLED 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_LINK_DISABLE_DISABLED 0x00000001 /* RW--V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_1 1:1 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_1_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_2 2:2 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_2_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_3 3:3 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_3_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_4 4:4 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_4_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_5 5:5 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_5_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_6 6:6 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_6_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_7 7:7 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_7_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_8 8:8 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_8_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_9 9:9 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_9_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_10 10:10 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_10_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_11 11:11 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_11_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_12 12:12 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_12_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_13 13:13 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_13_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_14 14:14 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_14_INIT 0x00000000 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_SW_LINK_MODE_CTRL_RESERVED_15 15:15 /* RWIVF */
#endif // __lr10_dev_nvlipt_lnk_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvlperf_ip_h__
#define __lr10_dev_nvlperf_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLPERF_CTRL_CLOCK_GATING 0x000000c8 /* RW-4R */
#define NV_NVLPERF_CTRL_CLOCK_GATING_CG1_SLCG 11:0 /* RWEVF */
#define NV_NVLPERF_CTRL_CLOCK_GATING_CG1_SLCG_INIT 0x00000fff /* RWE-V */
#define NV_NVLPERF_CTRL_CLOCK_GATING_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_NVLPERF_CTRL_CLOCK_GATING_CG1_SLCG_DISABLED 0x00000001 /* RW--V */
#define NV_NVLPERF_CTRL_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_NVLPERF_CTRL_CLOCK_GATING_CG1_SLCG_CTRL 12:12 /* RWEVF */
#define NV_NVLPERF_CTRL_CLOCK_GATING_CG1_SLCG_CTRL_ENABLED 0x00000000 /* RW--V */
#define NV_NVLPERF_CTRL_CLOCK_GATING_CG1_SLCG_CTRL_DISABLED 0x00000001 /* RWE-V */
#define NV_NVLPERF_CTRL_CLOCK_GATING_CG1_SLCG_CTRL__PROD 0x00000000 /* RW--V */
#define NV_NVLPERF_PERF_CTRL_CLOCK_GATING 0x000000cc /* RW-4R */
#define NV_NVLPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG 11:0 /* RWEVF */
#define NV_NVLPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG_INIT 0x00000fff /* RWE-V */
#define NV_NVLPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_NVLPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG_DISABLED 0x00000001 /* RW--V */
#define NV_NVLPERF_PERF_CTRL_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_NVLPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE 23:12 /* RWEVF */
#define NV_NVLPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE_DISABLED 0x00000000 /* RWE-V */
#define NV_NVLPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPERF_PERF_CTRL_CLOCK_GATING_CONTEXT_FREEZE__PROD 0x00000000 /* RW--V */
#endif // __lr10_dev_nvlperf_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvlphyctl_ip_h__
#define __lr10_dev_nvlphyctl_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6 0x0000281c /* RW-4R */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_RXCAL 0:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_RXCAL_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_RXCAL_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_INIT_TRAIN 3:3 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_INIT_TRAIN_NOT_COMPLETE 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_INIT_TRAIN_COMPLETE 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY 26:16 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY_ZERO 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY_SCL 31:27 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY_SCL_ZERO 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0 0x00002838 /* R--4R */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_IDDQ_DIS_STS 0:0 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_SLEEP_DIS_STS 1:1 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RXCAL_DONE 2:2 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_DATA_READY_STS 3:3 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_DATA_EN_STS 4:4 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RX_IDDQ_DIS_STS 5:5 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RX_SLEEP_DIS_STS 6:6 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RX_DATA_EN_STS 7:7 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4(i) (0x0000284c+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_EN 0:0 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_DONE 1:1 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_EN 4:4 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_DONE 5:5 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EOM_DONE 9:9 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_OVRD 12:12 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_OVRD 13:13 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_OVRD 14:14 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_EN 15:15 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EOM_STATUS 31:16 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8(i) (0x00002864+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_OVRD 0:0 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_EN 1:1 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_TRAIN_MODE 27:27 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_TRAIN_MODE_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OVRD 28:28 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OVRD 29:29 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET 30:30 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OFF 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_ON 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET 31:31 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OFF 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_ON 0x00000001 /* RWE-V */
#endif // __lr10_dev_nvlphyctl_ip_h__

590
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvlsaw_ip_h__
#define __lr10_dev_nvlsaw_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLSAW_SW_SCRATCH_3 0x000004ec /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_3_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_3_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_13 0x00000514 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_13_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_13_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_15 0x0000051c /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_15_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_15_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_2 0x000004e8 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_2_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_2_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_LEGACY 0x00000864 /* -W-4R */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_LEGACY_PTIMER_0 20:20 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_LEGACY_PTIMER_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_LEGACY_PTIMER_1 21:21 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_LEGACY_PTIMER_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_LEGACY_PMGR_0 22:22 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_LEGACY_PMGR_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_LEGACY_PMGR_1 23:23 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_LEGACY_PMGR_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_LEGACY_SMBUS_MSGBOX 24:24 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_LEGACY_SMBUS_MSGBOX_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE 0x00000880 /* -W-4R */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_0 0:0 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_1 1:1 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_2 2:2 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_2_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_3 3:3 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_3_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_4 4:4 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_4_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_5 5:5 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_5_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_6 6:6 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_6_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_7 7:7 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_7_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_8 8:8 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NVLIPT_8_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_0 9:9 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_1 10:10 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_2 11:11 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_2_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_3 12:12 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_3_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_4 13:13 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_4_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_5 14:14 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_5_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_6 15:15 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_6_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_7 16:16 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_7_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_8 17:17 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_NPG_8_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_SAW_WRITE_LOCKED 25:25 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_SAW_WRITE_LOCKED_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_SOE_SHIM_FLUSH 26:26 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_SOE_SHIM_FLUSH_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_SOE_SHIM_ILLEGAL 27:27 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_SOE_SHIM_ILLEGAL_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_SMR_0 28:28 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_SMR_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_SMR_1 29:29 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_SMR_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_OVER_TEMP_ALERT 30:30 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_OVER_TEMP_ALERT_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_OVER_TEMP 31:31 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_CLR_CORRECTABLE_OVER_TEMP_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE 0x00000870 /* -W-4R */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_0 0:0 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_1 1:1 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_2 2:2 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_2_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_3 3:3 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_3_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_4 4:4 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_4_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_5 5:5 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_5_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_6 6:6 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_6_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_7 7:7 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_7_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_8 8:8 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NVLIPT_8_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_0 9:9 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_1 10:10 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_2 11:11 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_2_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_3 12:12 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_3_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_4 13:13 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_4_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_5 14:14 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_5_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_6 15:15 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_6_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_7 16:16 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_7_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_8 17:17 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_NPG_8_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_SAW_WRITE_LOCKED 25:25 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_SAW_WRITE_LOCKED_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_SOE_SHIM_FLUSH 26:26 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_SOE_SHIM_FLUSH_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_SOE_SHIM_ILLEGAL 27:27 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_SOE_SHIM_ILLEGAL_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_SMR_0 28:28 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_SMR_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_SMR_1 29:29 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_SMR_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_OVER_TEMP_ALERT 30:30 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_OVER_TEMP_ALERT_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_OVER_TEMP 31:31 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_CORRECTABLE_OVER_TEMP_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL 0x00000868 /* -W-4R */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_0 0:0 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_1 1:1 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_2 2:2 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_2_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_3 3:3 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_3_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_4 4:4 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_4_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_5 5:5 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_5_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_6 6:6 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_6_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_7 7:7 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_7_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_8 8:8 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NVLIPT_8_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_0 9:9 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_1 10:10 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_2 11:11 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_2_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_3 12:12 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_3_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_4 13:13 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_4_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_5 14:14 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_5_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_6 15:15 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_6_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_7 16:16 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_7_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_8 17:17 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NPG_8_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_SOE 18:18 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_SOE_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NXBAR_0 20:20 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NXBAR_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NXBAR_1 21:21 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NXBAR_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NXBAR_2 22:22 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NXBAR_2_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NXBAR_3 23:23 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_FATAL_NXBAR_3_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL 0x0000086c /* -W-4R */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_0 0:0 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_1 1:1 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_2 2:2 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_2_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_3 3:3 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_3_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_4 4:4 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_4_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_5 5:5 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_5_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_6 6:6 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_6_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_7 7:7 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_7_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_8 8:8 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NVLIPT_8_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_0 9:9 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_0_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_1 10:10 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_1_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_2 11:11 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_2_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_3 12:12 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_3_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_4 13:13 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_4_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_5 14:14 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_5_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_6 15:15 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_6_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_7 16:16 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_7_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_8 17:17 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_NPG_8_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_SOE 18:18 /* -WXVF */
#define NV_NVLSAW_NVSPMC_INTR_EN_SET_NONFATAL_SOE_ENABLE 0x00000001 /* -W--V */
#define NV_NVLSAW_NVSPMC_INTR_LEGACY 0x00000840 /* R--4R */
#define NV_NVLSAW_NVSPMC_INTR_LEGACY_PTIMER_0 20:20 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_LEGACY_PTIMER_1 21:21 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_LEGACY_PMGR_0 22:22 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_LEGACY_PMGR_1 23:23 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_LEGACY_SMBUS_MSGBOX 24:24 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL 0x00000848 /* R--4R */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NVLIPT_0 0:0 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NVLIPT_1 1:1 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NVLIPT_2 2:2 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NVLIPT_3 3:3 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NVLIPT_4 4:4 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NVLIPT_5 5:5 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NVLIPT_6 6:6 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NVLIPT_7 7:7 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NVLIPT_8 8:8 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NPG_0 9:9 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NPG_1 10:10 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NPG_2 11:11 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NPG_3 12:12 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NPG_4 13:13 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NPG_5 14:14 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NPG_6 15:15 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NPG_7 16:16 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_NPG_8 17:17 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_NONFATAL_SOE 18:18 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL 0x00000844 /* R--4R */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NVLIPT_0 0:0 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NVLIPT_1 1:1 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NVLIPT_2 2:2 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NVLIPT_3 3:3 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NVLIPT_4 4:4 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NVLIPT_5 5:5 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NVLIPT_6 6:6 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NVLIPT_7 7:7 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NVLIPT_8 8:8 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NPG_0 9:9 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NPG_1 10:10 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NPG_2 11:11 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NPG_3 12:12 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NPG_4 13:13 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NPG_5 14:14 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NPG_6 15:15 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NPG_7 16:16 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NPG_8 17:17 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_SOE 18:18 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NXBAR_0 20:20 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NXBAR_1 21:21 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NXBAR_2 22:22 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_FATAL_NXBAR_3 23:23 /* R--VF */
#define NV_NVLSAW_NVSPMC_ENABLE 0x000008d0 /* RW-4R */
#define NV_NVLSAW_NVSPMC_ENABLE_NXBAR 0:0 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NXBAR_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NXBAR_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT 0x000008c8 /* RW-4R */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_0 0:0 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_0_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_0_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_1 1:1 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_1_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_1_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_2 2:2 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_2_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_2_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_3 3:3 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_3_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_3_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_4 4:4 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_4_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_4_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_5 5:5 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_5_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_5_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_6 6:6 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_6_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_6_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_7 7:7 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_7_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_7_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_8 8:8 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_8_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NVLIPT_NVLIPT_8_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG 0x000008cc /* RW-4R */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_0 0:0 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_0_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_0_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_1 1:1 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_1_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_1_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_2 2:2 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_2_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_2_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_3 3:3 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_3_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_3_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_4 4:4 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_4_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_4_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_5 5:5 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_5_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_5_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_6 6:6 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_6_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_6_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_7 7:7 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_7_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_7_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_8 8:8 /* RWEVF */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_8_DISABLE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_ENABLE_NPG_NPG_8_ENABLE 0x00000001 /* RWE-V */
#define NV_NVLSAW_GLBLLATENCYTIMERCTRL 0x00000040 /* RW-4R */
#define NV_NVLSAW_GLBLLATENCYTIMERCTRL_ENABLE 0:0 /* RWEVF */
#define NV_NVLSAW_GLBLLATENCYTIMERCTRL_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_NVLSAW_GLBLLATENCYTIMERCTRL_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_NVLSAW_GLBLLATENCYTIMERCTRL_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_NVLSAW_SW_SCRATCH_6 0x000004f8 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_6_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_6_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_7 0x000004fc /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_7_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_7_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_8 0x00000500 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_8_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_8_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_9 0x00000504 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_9_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_9_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_10 0x00000508 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_10_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_10_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SW_SCRATCH_11 0x0000050c /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_11_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_11_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_SCRATCH_COLD 0x000007c4 /* RW-4R */
#define NV_NVLSAW_SCRATCH_COLD_DATA 31:0 /* RWIVF */
#define NV_NVLSAW_SCRATCH_COLD_DATA_INIT 0xdeadbaad /* RWI-V */
#define NV_NVLSAW_SW_SCRATCH_12 0x00000510 /* RW-4R */
#define NV_NVLSAW_SW_SCRATCH_12_VALUE 31:0 /* RWEVF */
#define NV_NVLSAW_SW_SCRATCH_12_VALUE_INIT 0x00000000 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY 0x000008d4 /* RW-4R */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_PTIMER_0 20:20 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_PTIMER_0_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_PTIMER_0_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_PTIMER_1 21:21 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_PTIMER_1_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_PTIMER_1_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_PMGR_0 22:22 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_PMGR_0_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_PMGR_0_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_PMGR_1 23:23 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_PMGR_1_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_PMGR_1_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_SMBUS_MSGBOX 24:24 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_SMBUS_MSGBOX_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_LEGACY_SMBUS_MSGBOX_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE 0x000008e0 /* RW-4R */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_0 0:0 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_0_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_0_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_1 1:1 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_1_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_1_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_2 2:2 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_2_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_2_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_3 3:3 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_3_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_3_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_4 4:4 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_4_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_4_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_5 5:5 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_5_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_5_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_6 6:6 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_6_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_6_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_7 7:7 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_7_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_7_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_8 8:8 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_8_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NVLIPT_8_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_0 9:9 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_0_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_0_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_1 10:10 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_1_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_1_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_2 11:11 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_2_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_2_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_3 12:12 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_3_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_3_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_4 13:13 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_4_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_4_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_5 14:14 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_5_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_5_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_6 15:15 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_6_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_6_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_7 16:16 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_7_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_7_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_8 17:17 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_8_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_NPG_8_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SAW_WRITE_LOCKED 25:25 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SAW_WRITE_LOCKED_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SAW_WRITE_LOCKED_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SOE_SHIM_FLUSH 26:26 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SOE_SHIM_FLUSH_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SOE_SHIM_FLUSH_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SOE_SHIM_ILLEGAL 27:27 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SOE_SHIM_ILLEGAL_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SOE_SHIM_ILLEGAL_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SMR_0 28:28 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SMR_0_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SMR_0_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SMR_1 29:29 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SMR_1_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_SMR_1_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_OVER_TEMP_ALERT 30:30 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_OVER_TEMP_ALERT_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_OVER_TEMP_ALERT_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_OVER_TEMP 31:31 /* RWEVF */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_OVER_TEMP_HOST 0x00000001 /* RWE-V */
#define NV_NVLSAW_NVSPMC_STEER_INTR_CORRECTABLE_OVER_TEMP_SOE 0x00000000 /* RW--V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY 0x00000898 /* R--4R */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_PTIMER_0 20:20 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_PTIMER_0_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_PTIMER_0_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_PTIMER_1 21:21 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_PTIMER_1_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_PTIMER_1_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_PMGR_0 22:22 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_PMGR_0_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_PMGR_0_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_PMGR_1 23:23 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_PMGR_1_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_PMGR_1_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_SMBUS_MSGBOX 24:24 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_SMBUS_MSGBOX_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_LEGACY_SMBUS_MSGBOX_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE 0x000008a4 /* R--4R */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_0 0:0 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_0_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_0_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_1 1:1 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_1_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_1_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_2 2:2 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_2_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_2_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_3 3:3 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_3_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_3_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_4 4:4 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_4_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_4_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_5 5:5 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_5_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_5_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_6 6:6 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_6_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_6_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_7 7:7 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_7_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_7_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_8 8:8 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_8_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NVLIPT_8_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_0 9:9 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_0_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_0_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_1 10:10 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_1_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_1_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_2 11:11 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_2_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_2_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_3 12:12 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_3_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_3_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_4 13:13 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_4_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_4_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_5 14:14 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_5_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_5_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_6 15:15 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_6_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_6_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_7 16:16 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_7_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_7_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_8 17:17 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_8_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_NPG_8_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SAW_WRITE_LOCKED 25:25 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SAW_WRITE_LOCKED_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SAW_WRITE_LOCKED_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SOE_SHIM_FLUSH 26:26 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SOE_SHIM_FLUSH_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SOE_SHIM_FLUSH_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SOE_SHIM_ILLEGAL 27:27 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SOE_SHIM_ILLEGAL_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SOE_SHIM_ILLEGAL_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SMR_0 28:28 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SMR_0_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SMR_0_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SMR_1 29:29 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SMR_1_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_SMR_1_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_OVER_TEMP_ALERT 30:30 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_OVER_TEMP_ALERT_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_OVER_TEMP_ALERT_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_OVER_TEMP 31:31 /* R-EVF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_OVER_TEMP_DISABLE 0x00000000 /* R-E-V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_EN_CORRECTABLE_OVER_TEMP_ENABLE 0x00000001 /* R---V */
#define NV_NVLSAW_NVSPMC_INTR_SOE_LEGACY 0x00000884 /* R--4R */
#define NV_NVLSAW_NVSPMC_INTR_SOE_LEGACY_PTIMER_0 20:20 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_LEGACY_PTIMER_1 21:21 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_LEGACY_PMGR_0 22:22 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_LEGACY_PMGR_1 23:23 /* R--VF */
#define NV_NVLSAW_NVSPMC_INTR_SOE_LEGACY_SMBUS_MSGBOX 24:24 /* R--VF */
#endif // __lr10_dev_nvlsaw_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* @file dev_nvlsaw_ip_addendum.h
* @brief NVSwitch specific defines that are missing in the dev_nvlsaw_ip.h manual.
*/
#ifndef __lr10_dev_nvlsaw_ip_addendum_h__
#define __lr10_dev_nvlsaw_ip_addendum_h__
#define NV_NVLSAW_SW_SCRATCH_0_ERASE_LEDGER_CARVEOUT_OFFSET 11:0
#define NV_NVLSAW_SW_SCRATCH_0_ERASE_LEDGER_CARVEOUT_SIZE 23:12
// VBIOS write protect mode for nvflash
#define NV_NVLSAW_SW_SCRATCH_0_WRITE_PROTECT_MODE 24:24
#define NV_NVLSAW_SW_SCRATCH_0_WRITE_PROTECT_MODE_DISABLED 0x00000000
#define NV_NVLSAW_SW_SCRATCH_0_WRITE_PROTECT_MODE_ENABLED 0x00000001
#define NV_NVLSAW_SW_SCRATCH_7_BIOS_OEM_VERSION 7:0
#define NV_NVLSAW_SW_SCRATCH_7_RESERVED 31:8
#define NV_NVLSAW_SW_SCRATCH_2_INFOROM_WRITE_PROTECT_MODE 0:0
#define NV_NVLSAW_SW_SCRATCH_2_INFOROM_WRITE_PROTECT_MODE_DISABLED 0x00000000
#define NV_NVLSAW_SW_SCRATCH_2_INFOROM_WRITE_PROTECT_MODE_ENABLED 0x00000001
#define NV_NVLSAW_SW_SCRATCH_2_INFOROM_CARVEOUT_OFFSET 19:8
#define NV_NVLSAW_SW_SCRATCH_2_INFOROM_CARVEOUT_SIZE 31:20
#define NV_NVLSAW_SCRATCH_COLD_OOB_BLACKLIST_DEVICE_REQUESTED 0:0
#define NV_NVLSAW_SCRATCH_COLD_OOB_BLACKLIST_DEVICE_REQUESTED_ENABLE 0x00000000
#define NV_NVLSAW_SCRATCH_COLD_OOB_BLACKLIST_DEVICE_REQUESTED_DISABLE 0x00000001
// SCRATCH_12 is used to communicate fabric state to SOE. Bit fields:
#define NV_NVLSAW_SW_SCRATCH_12_DEVICE_RESET_REQUIRED 0:0
#define NV_NVLSAW_SW_SCRATCH_12_DEVICE_BLACKLIST_REASON 5:1
#define NV_NVLSAW_SW_SCRATCH_12_DEVICE_FABRIC_STATE 8:6
#define NV_NVLSAW_SW_SCRATCH_12_DRIVER_FABRIC_STATE 11:9
#define NV_NVLSAW_SW_SCRATCH_12_FABRIC_MANAGER_ERROR 18:12
#define NV_NVLSAW_SW_SCRATCH_12_EVENT_MESSAGE_COUNT 26:19
#define NV_NVLSAW_SCRATCH_COLD_OOB_BLACKLIST_DEVICE_REQUESTED 0:0
#endif //__lr10_dev_nvlsaw_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvs_h__
#define __lr10_dev_nvs_h__
/* This file is autogenerated. Do not edit */
#define NV_PBUS_PRI_TIMEOUT_SAVE_1 0x00001988 /* RW-4R */
#define NV_PBUS_PRI_TIMEOUT_SAVE_1_DATA 31:0 /* RWXVF */
#define NV_PBUS_PRI_TIMEOUT_SAVE_1_DATA_WAS_READ 0x0 /* RW--V */
#define NV_PBUS_PRI_TIMEOUT_SAVE_3 0x00001990 /* R--4R */
#define NV_PBUS_PRI_TIMEOUT_SAVE_3_SUBID 3:0 /* R-XVF */
#define NV_PBUS_PRI_TIMEOUT_FECS_ERRCODE 0x0000198C /* RW-4R */
#define NV_PBUS_PRI_TIMEOUT_FECS_ERRCODE_DATA 31:0 /* RWXVF */
#define NV_PBUS_PRI_TIMEOUT_SAVE_0 0x00001984 /* RW-4R */
#define NV_PBUS_PRI_TIMEOUT_SAVE_0_TO 0:0 /* RWXVF */
#define NV_PBUS_PRI_TIMEOUT_SAVE_0_TO_ERROR 0x1 /* RW--V */
#define NV_PBUS_PRI_TIMEOUT_SAVE_0_TO_CLEAR 0x0 /* -W--V */
#define NV_PBUS_PRI_TIMEOUT_SAVE_0_TO_NONE 0x0 /* RW--V */
#define NV_PBUS_PRI_TIMEOUT_SAVE_0_WRITE 1:1 /* RWXVF */
#define NV_PBUS_PRI_TIMEOUT_SAVE_0_WRITE_TRUE 0x1 /* RW--V */
#define NV_PBUS_PRI_TIMEOUT_SAVE_0_WRITE_FALSE 0x0 /* RW--V */
#define NV_PBUS_PRI_TIMEOUT_SAVE_0_ADDR 25:2 /* RWXVF */
#define NV_PBUS_PRI_TIMEOUT_SAVE_0_FECS_TGT 31:31 /* RWXVF */
#define NV_PBUS_PRI_TIMEOUT_SAVE_0_FECS_TGT_TRUE 0x1 /* RW--V */
#define NV_PBUS_PRI_TIMEOUT_SAVE_0_FECS_TGT_FALSE 0x0 /* RW--V */
#define NV_PBUS_EXT_CG1 0x00001C04 /* RW-4R */
#define NV_PBUS_EXT_CG1_SLCG 9:1 /* */
#define NV_PBUS_EXT_CG1_SLCG_ENABLED 0x00000000 /* */
#define NV_PBUS_EXT_CG1_SLCG_DISABLED 0x000001ff /* */
#define NV_PBUS_EXT_CG1_SLCG__PROD 0x00000000 /* */
#define NV_PBUS_EXT_CG1_SLCG_C11 2:2 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_C11_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_C11_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_C11__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_PRI 4:4 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_PRI_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_PRI_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_PRI__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_UNROLL 5:5 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_UNROLL_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_UNROLL_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_UNROLL__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_ROLL 7:7 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_ROLL_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_ROLL_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_ROLL__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_IFR 8:8 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_IFR_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_IFR_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_IFR__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_PMC 10:10 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_PMC_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_PMC_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_PMC__PROD 0x00000000 /* RW--V */
#define NV_PBUS_INTR_EN_0 0x00001140 /* RW-4R */
#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 /* RWIVF */
#define NV_PBUS_INTR_EN_0_PRI_SQUASH_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_PRI_SQUASH_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 /* RWIVF */
#define NV_PBUS_INTR_EN_0_PRI_FECSERR_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_PRI_FECSERR_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 /* RWIVF */
#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_0_SW 26:26 /* RWIVF */
#define NV_PBUS_INTR_EN_0_SW_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_SW_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_0 0x00001100 /* RW-4R */
#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 /* RWIVF */
#define NV_PBUS_INTR_0_PRI_SQUASH_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_PRI_SQUASH_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_PRI_SQUASH_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 /* RWIVF */
#define NV_PBUS_INTR_0_PRI_FECSERR_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_PRI_FECSERR_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_PRI_FECSERR_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 /* RWIVF */
#define NV_PBUS_INTR_0_PRI_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_PRI_TIMEOUT_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_PRI_TIMEOUT_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_SW 26:26 /* RWIVF */
#define NV_PBUS_INTR_0_SW_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_SW_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_SW_RESET 0x00000001 /* -W--C */
#endif // __lr10_dev_nvs_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvs_master_h__
#define __lr10_dev_nvs_master_h__
/* This file is autogenerated. Do not edit */
#define NV_PSMC_BOOT_2 0x00000008 /* R--4R */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION 3:0 /* R-XVF */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_0 0x00000000 /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_1 0x00000001 /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_2 0x00000002 /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_3 0x00000003 /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_4 0x00000004 /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_5 0x00000005 /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_6 0x00000006 /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_7 0x00000007 /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_8 0x00000008 /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_9 0x00000009 /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_A 0x0000000A /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_B 0x0000000B /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_C 0x0000000C /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_D 0x0000000D /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_E 0x0000000E /* R---V */
#define NV_PSMC_BOOT_2_MINOR_EXTENDED_REVISION_F 0x0000000F /* R---V */
#define NV_PSMC_BOOT_2_FMODEL 30:30 /* R---F */
#define NV_PSMC_BOOT_2_FMODEL_NO 0x00000000 /* R---V */
#define NV_PSMC_BOOT_2_FMODEL_YES 0x00000001 /* R---V */
#define NV_PSMC_BOOT_2_EMULATION 31:31 /* R-XVF */
#define NV_PSMC_BOOT_2_EMULATION_NO 0x00000000 /* R---V */
#define NV_PSMC_BOOT_2_EMULATION_YES 0x00000001 /* R---V */
#define NV_PSMC_BOOT_42 0x00000A00 /* R--4R */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION 11:8 /* R-XVF */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_0 0x00000000 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_1 0x00000001 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_2 0x00000002 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_3 0x00000003 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_4 0x00000004 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_5 0x00000005 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_6 0x00000006 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_7 0x00000007 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_8 0x00000008 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_9 0x00000009 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_A 0x0000000A /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_B 0x0000000B /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_C 0x0000000C /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_D 0x0000000D /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_E 0x0000000E /* R---V */
#define NV_PSMC_BOOT_42_MINOR_EXTENDED_REVISION_F 0x0000000F /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION 15:12 /* R-XVF */
#define NV_PSMC_BOOT_42_MINOR_REVISION_1 0x00000001 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_2 0x00000002 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_3 0x00000003 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_4 0x00000004 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_5 0x00000005 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_6 0x00000006 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_7 0x00000007 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_8 0x00000008 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_9 0x00000009 /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_10 0x0000000A /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_11 0x0000000B /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_12 0x0000000C /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_13 0x0000000D /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_14 0x0000000E /* R---V */
#define NV_PSMC_BOOT_42_MINOR_REVISION_15 0x0000000F /* R---V */
#define NV_PSMC_BOOT_42_MAJOR_REVISION 19:16 /* R-XVF */
#define NV_PSMC_BOOT_42_MAJOR_REVISION_A 0x0000000A /* R---V */
#define NV_PSMC_BOOT_42_MAJOR_REVISION_B 0x0000000B /* R---V */
#define NV_PSMC_BOOT_42_MAJOR_REVISION_C 0x0000000C /* R---V */
#define NV_PSMC_BOOT_42_MAJOR_REVISION_D 0x0000000D /* R---V */
#define NV_PSMC_BOOT_42_MAJOR_REVISION_E 0x0000000E /* R---V */
#define NV_PSMC_BOOT_42_MAJOR_REVISION_F 0x0000000F /* R---V */
#define NV_PSMC_BOOT_42_ARCHITECTURE 28:24 /* */
#define NV_PSMC_BOOT_42_ARCHITECTURE_SVNP01 0x00000000 /* */
#define NV_PSMC_BOOT_42_ARCHITECTURE_LR10 0x00000000 /* */
#define NV_PSMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */
#define NV_PSMC_BOOT_42_CHIP_ID_SVNP01 0x00000005 /* R---V */
#define NV_PSMC_BOOT_42_CHIP_ID_LR10 0x00000006 /* R---V */
#define NV_PSMC_BOOT_0 0x00000000 /* R--4R */
#define NV_PSMC_BOOT_0_ID 31:0 /* */
#define NV_PSMC_BOOT_0_MINOR_REVISION 3:0 /* R--VF */
#define NV_PSMC_BOOT_0_MINOR_REVISION_1 0x00000001 /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_2 0x00000002 /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_3 0x00000003 /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_4 0x00000004 /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_5 0x00000005 /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_6 0x00000006 /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_7 0x00000007 /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_8 0x00000008 /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_9 0x00000009 /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_10 0x0000000A /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_11 0x0000000B /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_12 0x0000000C /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_13 0x0000000D /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_14 0x0000000E /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_15 0x0000000F /* R---V */
#define NV_PSMC_BOOT_0_MINOR_REVISION_INIT 0x00000001 /* R---V */
#define NV_PSMC_BOOT_0_MAJOR_REVISION 7:4 /* R--VF */
#define NV_PSMC_BOOT_0_MAJOR_REVISION_A 0x0000000A /* R---V */
#define NV_PSMC_BOOT_0_MAJOR_REVISION_B 0x0000000B /* R---V */
#define NV_PSMC_BOOT_0_MAJOR_REVISION_C 0x0000000C /* R---V */
#define NV_PSMC_BOOT_0_MAJOR_REVISION_D 0x0000000D /* R---V */
#define NV_PSMC_BOOT_0_MAJOR_REVISION_E 0x0000000E /* R---V */
#define NV_PSMC_BOOT_0_MAJOR_REVISION_F 0x0000000F /* R---V */
#define NV_PSMC_BOOT_0_MAJOR_REVISION_INIT 0x00000000 /* R---V */
#define NV_PSMC_BOOT_0_RESERVED_0 11:8 /* */
#define NV_PSMC_BOOT_0_ARCHITECTURE 28:24 /* R--VF */
#define NV_PSMC_BOOT_0_ARCHITECTURE_SVNP01 0x00000000 /* R---V */
#define NV_PSMC_BOOT_0_ARCHITECTURE_LR10 0x00000000 /* R---V */
#define NV_PSMC_INTR_LEGACY 0x00000100 /* R--4R */
#define NV_PSMC_INTR_LEGACY_PTIMER 20:20 /* R--VF */
#define NV_PSMC_INTR_LEGACY_PMGR 21:21 /* R--VF */
#define NV_PSMC_INTR_LEGACY_SAW 22:22 /* R--VF */
#define NV_PSMC_INTR_LEGACY_DECODE_TRAP_PRIV_LEVEL_VIOLATION 24:24 /* R--VF */
#define NV_PSMC_INTR_LEGACY_DECODE_TRAP_WRITE_DROPPED 25:25 /* R--VF */
#define NV_PSMC_INTR_LEGACY_RING_MANAGE_SUCCESS 26:26 /* R--VF */
#define NV_PSMC_INTR_LEGACY_PBUS 28:28 /* R--VF */
#define NV_PSMC_INTR_LEGACY_XVE 29:29 /* R--VF */
#define NV_PSMC_INTR_LEGACY_PRIV_RING 30:30 /* R--VF */
#define NV_PSMC_INTR_EN_SET_LEGACY 0x00000160 /* -W-4R */
#define NV_PSMC_INTR_EN_SET_LEGACY_PTIMER 20:20 /* -W-VF */
#define NV_PSMC_INTR_EN_SET_LEGACY_PMGR 21:21 /* -W-VF */
#define NV_PSMC_INTR_EN_SET_LEGACY_SAW 22:22 /* -W-VF */
#define NV_PSMC_INTR_EN_SET_LEGACY_DECODE_TRAP_PRIV_LEVEL_VIOLATION 24:24 /* -W-VF */
#define NV_PSMC_INTR_EN_SET_LEGACY_DECODE_TRAP_WRITE_DROPPED 25:25 /* -W-VF */
#define NV_PSMC_INTR_EN_SET_LEGACY_RING_MANAGE_SUCCESS 26:26 /* -W-VF */
#define NV_PSMC_INTR_EN_SET_LEGACY_PBUS 28:28 /* -W-VF */
#define NV_PSMC_INTR_EN_SET_LEGACY_XVE 29:29 /* -W-VF */
#define NV_PSMC_INTR_EN_SET_LEGACY_PRIV_RING 30:30 /* -W-VF */
#define NV_PSMC_INTR_EN_CLR_LEGACY 0x00000180 /* -W-4R */
#define NV_PSMC_INTR_EN_CLR_LEGACY_PTIMER 20:20 /* -W-VF */
#define NV_PSMC_INTR_EN_CLR_LEGACY_PMGR 21:21 /* -W-VF */
#define NV_PSMC_INTR_EN_CLR_LEGACY_SAW 22:22 /* -W-VF */
#define NV_PSMC_INTR_EN_CLR_LEGACY_DECODE_TRAP_PRIV_LEVEL_VIOLATION 24:24 /* -W-VF */
#define NV_PSMC_INTR_EN_CLR_LEGACY_DECODE_TRAP_WRITE_DROPPED 25:25 /* -W-VF */
#define NV_PSMC_INTR_EN_CLR_LEGACY_RING_MANAGE_SUCCESS 26:26 /* -W-VF */
#define NV_PSMC_INTR_EN_CLR_LEGACY_PBUS 28:28 /* -W-VF */
#define NV_PSMC_INTR_EN_CLR_LEGACY_XVE 29:29 /* -W-VF */
#define NV_PSMC_INTR_EN_CLR_LEGACY_PRIV_RING 30:30 /* -W-VF */
#endif // __lr10_dev_nvs_master_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nvs_top_h__
#define __lr10_dev_nvs_top_h__
/* This file is autogenerated. Do not edit */
#define NV_SWPTOP /* R--4P */
#define NV_SWPTOP_TABLE_BASE_ADDRESS_OFFSET 0x0002c000 /* */
#define NV_SWPTOP_ENTRY 1:0 /* R-EVF */
#define NV_SWPTOP_ENTRY_INVALID 0x00000000 /* R-E-V */
#define NV_SWPTOP_ENTRY_ENUM 0x00000001 /* R---V */
#define NV_SWPTOP_ENTRY_DATA1 0x00000002 /* R---V */
#define NV_SWPTOP_ENTRY_DATA2 0x00000003 /* R---V */
#define NV_SWPTOP_CONTENTS 30:2 /* R-EVF */
#define NV_SWPTOP_CONTENTS_INIT 0x00000000 /* R-E-V */
#define NV_SWPTOP_CHAIN 31:31 /* R-EVF */
#define NV_SWPTOP_CHAIN_DISABLE 0x00000000 /* R-E-V */
#define NV_SWPTOP_CHAIN_ENABLE 0x00000001 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE 9:2 /* R--UF */
#define NV_SWPTOP_ENUM_DEVICE_INVALID 0x0 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PTOP 0x1 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SIOCTRL 0x2 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SIOCTRL_BCAST 0x3 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_NPG 0x4 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_NPG_BCAST 0x5 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SWX 0x6 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SWX_BCAST 0x7 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_CLKS 0x8 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_FUSE 0x9 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_JTAG 0xa /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PMGR 0xb /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SAW 0xc /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_XP3G 0xd /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_XVE 0xe /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_ROM 0xf /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_EXTDEV 0x10 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PRIVMAIN 0x11 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PRIVLOC 0x12 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_NVLW 0x13 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_NVLW_BCAST 0x14 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_NXBAR 0x15 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_NXBAR_BCAST 0x16 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PXBAR 0x17 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PXBAR_BCAST 0x18 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PCIE 0x19 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PCIE_BCAST 0x1a /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_PTIMER 0x1b /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_TSENSE 0x1c /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SOE 0x1d /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SMR 0x1e /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_I2C 0x1f /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SMBPBI 0x20 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_SE 0x21 /* R---V */
#define NV_SWPTOP_ENUM_DEVICE_THERM 0x22 /* R---V */
#define NV_SWPTOP_ENUM_ID 17:10 /* R--UF */
#define NV_SWPTOP_ENUM_RESERVED 19:18 /* R--UF */
#define NV_SWPTOP_ENUM_VERSION 30:20 /* R--UF */
#define NV_SWPTOP_DATA1_RESET 6:2 /* R--UF */
#define NV_SWPTOP_DATA1_INTR 11:7 /* R--UF */
#define NV_SWPTOP_DATA1_RESERVED2 11:2 /* R--UF */
#define NV_SWPTOP_DATA1_CLUSTER_TYPE 16:12 /* R--UF */
#define NV_SWPTOP_DATA1_CLUSTER_TYPE_INVALID 0x0 /* R---V */
#define NV_SWPTOP_DATA1_CLUSTER_TYPE_SYS 0x1 /* R---V */
#define NV_SWPTOP_DATA1_CLUSTER_TYPE_PRT 0x2 /* R---V */
#define NV_SWPTOP_DATA1_CLUSTER_NUMBER 21:17 /* R--UF */
#define NV_SWPTOP_DATA1_RESERVED 30:22 /* R--UF */
#define NV_SWPTOP_DATA1_PTOP_LENGTH 30:2 /* R--UF */
#define NV_SWPTOP_DATA2_TYPE 30:26 /* R--UF */
#define NV_SWPTOP_DATA2_TYPE_INVALID 0x0 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_RESERVED 0x1 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_RESETREG 0x2 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_INTRREG 0x3 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_DISCOVERY 0x4 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_UNICAST 0x5 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_BROADCAST 0x6 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_MULTICAST0 0x7 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_MULTICAST1 0x8 /* R---V */
#define NV_SWPTOP_DATA2_TYPE_MULTICAST2 0x9 /* R---V */
#define NV_SWPTOP_DATA2_ADDR 25:2 /* R--UF */
#endif // __lr10_dev_nvs_top_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nxbar_tc_global_ip_h__
#define __lr10_dev_nxbar_tc_global_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST 0x00000240 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_LOG_VC 15:13 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_LOG_DST 19:16 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_LOG_SRC 25:24 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_LOG_TILE_SRC 31:28 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FIRST_LOG_TILE_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST 0x00000440 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_LOG_VC 15:13 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_LOG_DST 19:16 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_LOG_SRC 25:24 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_LOG_TILE_SRC 31:28 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FIRST_LOG_TILE_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST 0x00000640 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_LOG_VC 15:13 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_LOG_DST 19:16 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_LOG_SRC 25:24 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_LOG_TILE_SRC 31:28 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FIRST_LOG_TILE_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST 0x00000840 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_LOG_VC 15:13 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_LOG_DST 19:16 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_LOG_SRC 25:24 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_LOG_TILE_SRC 31:28 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FIRST_LOG_TILE_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST 0x00000a40 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_LOG_VC 15:13 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_LOG_DST 19:16 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_LOG_SRC 25:24 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_LOG_TILE_SRC 31:28 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FIRST_LOG_TILE_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST 0x00000c40 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_LOG_VC 15:13 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_LOG_DST 19:16 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_LOG_SRC 25:24 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_LOG_TILE_SRC 31:28 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FIRST_LOG_TILE_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST 0x00000e40 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_LOG_VC 15:13 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_LOG_DST 19:16 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_LOG_SRC 25:24 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_LOG_TILE_SRC 31:28 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FIRST_LOG_TILE_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST 0x00001040 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_LOG_VC 15:13 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_LOG_DST 19:16 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_LOG_SRC 25:24 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_LOG_TILE_SRC 31:28 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FIRST_LOG_TILE_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST 0x00001240 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_LOG_VC 15:13 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_LOG_DST 19:16 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_LOG_SRC 25:24 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_LOG_TILE_SRC 31:28 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FIRST_LOG_TILE_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN 0x0000023c /* RW-4R */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN 0x0000043c /* RW-4R */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN 0x0000063c /* RW-4R */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN 0x0000083c /* RW-4R */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN 0x00000a3c /* RW-4R */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN 0x00000c3c /* RW-4R */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN 0x00000e3c /* RW-4R */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN 0x0000103c /* RW-4R */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN 0x0000123c /* RW-4R */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_FATAL_INTR_EN_EGRESS_CDT_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS 0x00000234 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_STATUS_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS 0x00000434 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_STATUS_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS 0x00000634 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_STATUS_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS 0x00000834 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_STATUS_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS 0x00000a34 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_STATUS_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS 0x00000c34 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_STATUS_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS 0x00000e34 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_STATUS_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS 0x00001034 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_STATUS_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS 0x00001234 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_EGRESS_CDT_PARITY_ERROR 7:7 /* RWIVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_STATUS_EGRESS_CDT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_CYA 0x00000230 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT0_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL 0:0 /* RWEVF */
#define NV_NXBAR_TC_TILEOUT0_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_ENABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT0_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_DISABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_TILEOUT0_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT1_ERR_CYA 0x00000430 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT1_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL 0:0 /* RWEVF */
#define NV_NXBAR_TC_TILEOUT1_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_ENABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT1_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_DISABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_TILEOUT1_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT2_ERR_CYA 0x00000630 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT2_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL 0:0 /* RWEVF */
#define NV_NXBAR_TC_TILEOUT2_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_ENABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT2_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_DISABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_TILEOUT2_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT3_ERR_CYA 0x00000830 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT3_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL 0:0 /* RWEVF */
#define NV_NXBAR_TC_TILEOUT3_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_ENABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT3_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_DISABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_TILEOUT3_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT4_ERR_CYA 0x00000a30 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT4_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL 0:0 /* RWEVF */
#define NV_NXBAR_TC_TILEOUT4_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_ENABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT4_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_DISABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_TILEOUT4_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT5_ERR_CYA 0x00000c30 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT5_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL 0:0 /* RWEVF */
#define NV_NXBAR_TC_TILEOUT5_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_ENABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT5_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_DISABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_TILEOUT5_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT6_ERR_CYA 0x00000e30 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT6_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL 0:0 /* RWEVF */
#define NV_NXBAR_TC_TILEOUT6_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_ENABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT6_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_DISABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_TILEOUT6_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT7_ERR_CYA 0x00001030 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT7_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL 0:0 /* RWEVF */
#define NV_NXBAR_TC_TILEOUT7_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_ENABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT7_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_DISABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_TILEOUT7_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT8_ERR_CYA 0x00001230 /* RW-4R */
#define NV_NXBAR_TC_TILEOUT8_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL 0:0 /* RWEVF */
#define NV_NXBAR_TC_TILEOUT8_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_ENABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TC_TILEOUT8_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_DISABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_TILEOUT8_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_ERROR_STATUS 0x00000090 /* R--4R */
#define NV_NXBAR_TC_ERROR_STATUS_TILE0 0:0 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILE0_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_ERROR_STATUS_TILE1 1:1 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILE1_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_ERROR_STATUS_TILE2 2:2 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILE2_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_ERROR_STATUS_TILE3 3:3 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILE3_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT0 16:16 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT0_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT1 17:17 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT1_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT2 18:18 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT2_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT3 19:19 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT3_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT4 20:20 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT4_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT5 21:21 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT5_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT6 22:22 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT6_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT7 23:23 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT7_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT8 24:24 /* R--VF */
#define NV_NXBAR_TC_ERROR_STATUS_TILEOUT8_DEFAULT 0x00000000 /* R---V */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG 0x00000048 /* RWE4R */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_IDLE_CG_EN 6:6 /* RWEVF */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_STATE_CG_EN 7:7 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_STALL_CG_EN 14:14 /* RWEVF */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_THROT_CLK_CNT 23:20 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_THROT_CLK_EN 28:28 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_PAUSE_CG_EN 30:30 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_HALT_CG_EN 31:31 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TC_PRI_NXBAR_TC_CG_HALT_CG_EN__PROD 0x00000000 /* */
#endif // __lr10_dev_nxbar_tc_global_ip_h__

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@@ -0,0 +1,156 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_nxbar_tile_ip_h__
#define __lr10_dev_nxbar_tile_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NXBAR_TILE_ERR_STATUS 0x00000064 /* RW-4R */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_PKT_INVALID_DST 7:7 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_PKT_INVALID_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_PKT_PARITY_ERROR 8:8 /* RWIVF */
#define NV_NXBAR_TILE_ERR_STATUS_INGRESS_PKT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN 0x0000006c /* RW-4R */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BUFFER_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_OVERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_EGRESS_CREDIT_UNDERFLOW__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_BURSTY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_NON_STICKY_PKT__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_BURST_GT_9_DATA_VC__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_INVALID_DST 7:7 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_INVALID_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_INVALID_DST__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_PARITY_ERROR 8:8 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FATAL_INTR_EN_INGRESS_PKT_PARITY_ERROR__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_FIRST 0x00000070 /* RW-4R */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BUFFER_OVERFLOW 0:0 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BUFFER_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW 1:1 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BUFFER_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_EGRESS_CREDIT_OVERFLOW 2:2 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_EGRESS_CREDIT_OVERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW 3:3 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_EGRESS_CREDIT_UNDERFLOW_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_NON_BURSTY_PKT 4:4 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_NON_BURSTY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_NON_STICKY_PKT 5:5 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_NON_STICKY_PKT_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC 6:6 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_BURST_GT_9_DATA_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_PKT_INVALID_DST 7:7 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_PKT_INVALID_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_PKT_PARITY_ERROR 8:8 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_INGRESS_PKT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_LOG_VC 15:13 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_LOG_VC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_LOG_SRC 19:16 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_LOG_SRC_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_FIRST_LOG_DST 27:24 /* RWIVF */
#define NV_NXBAR_TILE_ERR_FIRST_LOG_DST_INIT 0x00000000 /* RWI-V */
#define NV_NXBAR_TILE_ERR_CYA 0x00000060 /* RW-4R */
#define NV_NXBAR_TILE_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL 0:0 /* RWEVF */
#define NV_NXBAR_TILE_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_DISABLE 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL_ENABLE 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_ERR_CYA_SRCID_UPDATE_AT_EGRESS_CTRL__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG 0x00000048 /* RWE4R */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_EN 6:6 /* RWEVF */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STATE_CG_EN 7:7 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_EN 14:14 /* RWEVF */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_CNT 23:20 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_EN 28:28 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_PAUSE_CG_EN 30:30 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_HALT_CG_EN 31:31 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_NXBAR_TILE_PRI_NXBAR_TILE_CG_HALT_CG_EN__PROD 0x00000000 /* */
#endif // __lr10_dev_nxbar_tile_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_pmgr_h__
#define __lr10_dev_pmgr_h__
/* This file is autogenerated. Do not edit */
#define NV_PMGR_GPIO_OUTPUT_CNTL(i) 0x0000D610 +(i) * (0x0000D614 - 0x0000D610) /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL__SIZE_1 31 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL 7:0 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_INIT 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_NORMAL 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_RASTER_SYNC_0 0x00000040 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_RASTER_SYNC_1 0x00000041 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_RASTER_SYNC_2 0x00000042 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_RASTER_SYNC_3 0x00000043 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_RASTER_SYNC(i) ((i) + 0x40) /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_RASTER_SYNC__SIZE_1 4 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_STEREO_0 0x00000048 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_STEREO_1 0x00000049 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_STEREO_2 0x0000004A /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_STEREO_3 0x0000004B /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_STEREO(i) ((i) + 0x48) /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_STEREO__SIZE_1 4 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SWAP_READY_OUT_0 0x00000050 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SWAP_READY_OUT_1 0x00000051 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SWAP_READY_OUT_2 0x00000052 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SWAP_READY_OUT_3 0x00000053 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SWAP_READY_OUT(i) ((i) + 0x50) /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SWAP_READY_OUT__SIZE_1 4 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_VID_PWM_3 0x00000055 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_VID_PWM_2 0x00000056 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_VID_PWM_1 0x00000057 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_FAN_ALERT 0x00000059 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_ADC_MUX_SEL 0x0000005A /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_BA_METER 0x0000005B /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_PWM_OUTPUT 0x0000005C /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_VID_PWM 0x0000005D /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_THERMAL_PWM 0x0000005E /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_THERMAL_SLOWDOWN 0x0000005F /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_0 0x00000060 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_1 0x00000061 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_2 0x00000062 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_3 0x00000063 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_4 0x00000064 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_5 0x00000065 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_6 0x00000066 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_7 0x00000067 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_8 0x00000068 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_9 0x00000069 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_A 0x0000006A /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_B 0x0000006B /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_C 0x0000006C /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_D 0x0000006D /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_E 0x0000006E /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_F 0x0000006F /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SPI_CS_1 0x00000071 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SPI_CS_2 0x00000072 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SPI_CS_3 0x00000073 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SPI_CS(i) ((i)+0x70) /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SPI_CS__SIZE_1 4 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR0_TMDS_OUT_PWM 0x00000080 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR0_TMDS_OUT_PINA 0x00000081 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR0_TMDS_OUT_PINB 0x00000082 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR1_TMDS_OUT_PWM 0x00000084 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR1_TMDS_OUT_PINA 0x00000085 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR1_TMDS_OUT_PINB 0x00000086 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR2_TMDS_OUT_PWM 0x00000088 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR2_TMDS_OUT_PINA 0x00000089 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR2_TMDS_OUT_PINB 0x0000008A /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR3_TMDS_OUT_PWM 0x0000008C /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR3_TMDS_OUT_PINA 0x0000008D /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR3_TMDS_OUT_PINB 0x0000008E /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR_TMDS_OUT_PWM(i) (((i)*4) + 0x80)/* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR_TMDS_OUT_PWM__SIZE_1 8 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR_TMDS_OUT_PINA(i) (((i)*4) + 0x81)/* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR_TMDS_OUT_PINA__SIZE_1 8 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR_TMDS_OUT_PINB(i) (((i)*4) + 0x82)/* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_SEL_SOR_TMDS_OUT_PINB__SIZE_1 8 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_OUTPUT 12:12 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_OUTPUT_INIT 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_OUTPUT_0 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_OUTPUT_1 0x00000001 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_OUT_EN 13:13 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_OUT_EN_INIT 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_OUT_EN_NO 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_OUT_EN_YES 0x00000001 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_INPUT 14:14 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_INPUT_0 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_INPUT_1 0x00000001 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_OUT_INV 15:15 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_OUT_INV_INIT 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_OUT_INV_DISABLE 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_IO_OUT_INV_ENABLE 0x00000001 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_PULLUD 17:16 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_PULLUD_INIT 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_PULLUD_NONE 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_PULLUD_UP 0x00000001 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_PULLUD_DOWN 0x00000002 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_PULLUD_RESERVED 0x00000003 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_OPEN_DRAIN 18:18 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_OPEN_DRAIN_INIT 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_OPEN_DRAIN_DISABLE 0x00000000 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_OPEN_DRAIN_ENABLE 0x00000001 /* */
#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER 0x0000D604 /* RWI4R */
#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER_UPDATE 0:0 /* RWIVF */
#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER_UPDATE_INIT 0x00000000 /* R-I-V */
#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER_UPDATE_DONE 0x00000000 /* R---V */
#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER_UPDATE_TRIGGER 0x00000001 /* -W--T */
#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER_UPDATE_PENDING 0x00000001 /* R---V */
#define NV_PMGR_ROM_WINDOW_XVE 0x0000E218 /* RW-4R */
#define NV_PMGR_ROM_WINDOW_XVE_OFFSET 11:0 /* RWHVF */
#define NV_PMGR_ROM_WINDOW_XVE_OFFSET_MIN 0x00000000 /* RWH-V */
#define NV_PMGR_ROM_WINDOW_XVE_OFFSET_MAX 0x00000FFF /* RW--V */
#define NV_PMGR_ROM_WINDOW_XVE_LIMIT 27:16 /* RWHVF */
#define NV_PMGR_ROM_WINDOW_XVE_LIMIT_MIN 0x00000000 /* RW--V */
#define NV_PMGR_ROM_WINDOW_XVE_LIMIT_MAX 0x00000FFF /* RWH-V */
#define NV_PMGR_GPIO_INPUT_CNTL_1 0x0000D740 /* RW-4R */
#define NV_PMGR_GPIO_INPUT_CNTL_1_PINNUM 7:0 /* RWIVF */
#define NV_PMGR_GPIO_INPUT_CNTL_1_PINNUM_INIT 0x00000001 /* RWI-V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_INV 8:8 /* RWIVF */
#define NV_PMGR_GPIO_INPUT_CNTL_1_INV_NO 0x00000000 /* RWI-V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_INV_YES 0x00000001 /* RW--V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_READ 9:9 /* R--VF */
#define NV_PMGR_GPIO_INPUT_CNTL_1_READ_0 0x00000000 /* R---V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_READ_1 0x00000001 /* R---V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER 10:10 /* RWIVF */
#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER_NO 0x00000000 /* RW--V */
#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER_YES 0x00000001 /* RW--V */
#define NV_PMGR_I2C_TIMING(i) (0x0000D008 + (i) * 0x20) /* RW-4A */
#define NV_PMGR_I2C_TIMING__SIZE_1 10 /* */
#define NV_PMGR_I2C_TIMING_SCL_PERIOD 11:0 /* RWIVF */
#define NV_PMGR_I2C_TIMING_SCL_PERIOD_INIT 0x0000010E /* RWI-V */
#define NV_PMGR_I2C_TIMING_SCL_PERIOD_100KHZ 0x000003E8 /* RW--V */
#define NV_PMGR_I2C_TIMING_SCL_PERIOD_200KHZ 0x000001F4 /* RW--V */
#define NV_PMGR_I2C_TIMING_SCL_PERIOD_300KHZ 0x0000014E /* RW--V */
#define NV_PMGR_I2C_TIMING_SCL_PERIOD_400KHZ 0x00000103 /* RW--V */
#define NV_PMGR_I2C_TIMING_SCL_PERIOD_500KHZ 0x000000C8 /* RW--V */
#define NV_PMGR_I2C_TIMING_SCL_PERIOD_600KHZ 0x000000A7 /* RW--V */
#define NV_PMGR_I2C_TIMING_SCL_PERIOD_800KHZ 0x0000007D /* RW--V */
#define NV_PMGR_I2C_TIMING_SCL_PERIOD_1000KHZ 0x00000064 /* RW--V */
#define NV_PMGR_I2C_TIMING_IGNORE_ACK 15:15 /* RWIVF */
#define NV_PMGR_I2C_TIMING_IGNORE_ACK_INIT 0x00000000 /* RWI-V */
#define NV_PMGR_I2C_TIMING_IGNORE_ACK_DISABLE 0x00000000 /* RW--V */
#define NV_PMGR_I2C_TIMING_IGNORE_ACK_ENABLE 0x00000001 /* RW--V */
#define NV_PMGR_I2C_TIMING_TIMEOUT_CLK_CNT 23:16 /* RWIVF */
#define NV_PMGR_I2C_TIMING_TIMEOUT_CLK_CNT_INIT 0x00000001 /* R-I-V */
#define NV_PMGR_I2C_TIMING_TIMEOUT_CHECK 24:24 /* RWIVF */
#define NV_PMGR_I2C_TIMING_TIMEOUT_CHECK_INIT 0x00000000 /* RWI-V */
#define NV_PMGR_I2C_TIMING_TIMEOUT_CHECK_DISABLE 0x00000000 /* RW--V */
#define NV_PMGR_I2C_TIMING_TIMEOUT_CHECK_ENABLE 0x00000001 /* RW--V */
#endif // __lr10_dev_pmgr_h__

76
src/common/inc/swref/published/nvswitch/lr10/dev_pri_ringmaster.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_pri_ringmaster_h__
#define __lr10_dev_pri_ringmaster_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_MASTER_CG1 0x001200a8 /* RW-4R */
#define NV_PPRIV_MASTER_CG1_SLCG 0:0 /* RWBVF */
#define NV_PPRIV_MASTER_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_CG1_SLCG_DISABLED 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_RING_COMMAND 0x0012004c /* RW-4R */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 0x00000002 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 0x00000003 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_AND_START_RING 0x00000004 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_TAG_ENUMERATE_AND_START_RING 0x00000005 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 9:6 /* RWBVF */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_GPC 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_FBP 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_SYS 0x00000003 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ROP_L2 0x00000004 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_ALL 0x00000008 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_GPC 0x00000009 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_FBP 0x0000000a /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_SYS 0x0000000b /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_ROP_L2 0x0000000c /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x00120048 /* RW-4R */
#define NV_PPRIV_MASTER_RING_COMMAND_DATA_START_RING_SEED 7:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_COMMAND_DATA_START_RING_SEED_INIT 0x00000053 /* RWB-V */
#define NV_PPRIV_MASTER_RING_START_RESULTS 0x00120050 /* R--4R */
#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 0x00000001 /* R---V */
#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_FAIL 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x00120058 /* R--4R */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_FBP 31:16 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_FBP_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYS 8:8 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYS_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_START_CONN_FAULT 0:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_START_CONN_FAULT_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DISCONNECT_FAULT 1:1 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DISCONNECT_FAULT_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_OVERFLOW_FAULT 2:2 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_OVERFLOW_FAULT_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_ENUMERATION_FAULT 3:3 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_ENUMERATION_FAULT_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GPC_RS_MAP_CONFIG_FAULT 4:4 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GPC_RS_MAP_CONFIG_FAULT_V 0x00000000 /* R-B-V */
#endif // __lr10_dev_pri_ringmaster_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_pri_ringstation_prt_h__
#define __lr10_dev_pri_ringstation_prt_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_PRT_PRT0_CG1 0x00128250 /* RW-4R */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_UCODE_TRAP 7:7 /* RWBVF */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_UCODE_TRAP_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_UCODE_TRAP_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_UCODE_TRAP__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV 8:8 /* RWBVF */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT0_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1 0x00128a50 /* RW-4R */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_UCODE_TRAP 7:7 /* RWBVF */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_UCODE_TRAP_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_UCODE_TRAP_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_UCODE_TRAP__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV 8:8 /* RWBVF */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT1_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1 0x00129250 /* RW-4R */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_UCODE_TRAP 7:7 /* RWBVF */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_UCODE_TRAP_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_UCODE_TRAP_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_UCODE_TRAP__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV 8:8 /* RWBVF */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT2_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1 0x00129a50 /* RW-4R */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_UCODE_TRAP 7:7 /* RWBVF */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_UCODE_TRAP_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_UCODE_TRAP_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_UCODE_TRAP__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV 8:8 /* RWBVF */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT3_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1 0x0012a250 /* RW-4R */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_UCODE_TRAP 7:7 /* RWBVF */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_UCODE_TRAP_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_UCODE_TRAP_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_UCODE_TRAP__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV 8:8 /* RWBVF */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT4_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1 0x0012aa50 /* RW-4R */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_UCODE_TRAP 7:7 /* RWBVF */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_UCODE_TRAP_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_UCODE_TRAP_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_UCODE_TRAP__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV 8:8 /* RWBVF */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT5_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1 0x0012b250 /* RW-4R */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_UCODE_TRAP 7:7 /* RWBVF */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_UCODE_TRAP_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_UCODE_TRAP_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_UCODE_TRAP__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV 8:8 /* RWBVF */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT6_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1 0x0012ba50 /* RW-4R */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_UCODE_TRAP 7:7 /* RWBVF */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_UCODE_TRAP_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_UCODE_TRAP_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_UCODE_TRAP__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV 8:8 /* RWBVF */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT7_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1 0x0012c250 /* RW-4R */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_UCODE_TRAP 7:7 /* RWBVF */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_UCODE_TRAP_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_UCODE_TRAP_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_UCODE_TRAP__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV 8:8 /* RWBVF */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_PRT8_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_ADR 0x00128120 /* R--4R */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_ADR_ADDRESS 25:0 /* R-BVF */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_ADR_ADDRESS_I 0x0000000 /* R-B-V */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_ADR_MOD 0x0012811c /* R--4R */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_ADR_MOD_ADDRESS 25:0 /* R-BVF */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_ADR_MOD_ADDRESS_I 0x0000000 /* R-B-V */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_ADR 0x00128920 /* R--4R */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_ADR_ADDRESS 25:0 /* R-BVF */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_ADR_ADDRESS_I 0x0000000 /* R-B-V */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_ADR_MOD 0x0012891c /* R--4R */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_ADR_MOD_ADDRESS 25:0 /* R-BVF */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_ADR_MOD_ADDRESS_I 0x0000000 /* R-B-V */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_WRDAT 0x00128124 /* R--4R */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_WRDAT_DATA 31:0 /* R-BVF */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_WRDAT_DATA_I 0x00000000 /* R-B-V */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_WRDAT 0x00128924 /* R--4R */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_WRDAT_DATA 31:0 /* R-BVF */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_WRDAT_DATA_I 0x00000000 /* R-B-V */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO 0x00128128 /* R--4R */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_SUBID 31:24 /* R-BVF */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_SUBID_I 0x00 /* R-B-V */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_LOCAL_ORDERING 22:22 /* R-BVF */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_LOCAL_ORDERING_I 0x0 /* R-B-V */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_PRIV_LEVEL 21:20 /* R-BVF */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_PRIV_LEVEL_I 0x0 /* R-B-V */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_SENDING_RS 17:12 /* R-BVF */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_SENDING_RS_I 0x00 /* R-B-V */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_PENDING 9:9 /* R-BVF */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_PENDING_I 0x0 /* R-B-V */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_ORPHAN 8:8 /* R-BVF */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_ORPHAN_I 0x0 /* R-B-V */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_PRIV_MASTER 7:0 /* R-BVF */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_INFO_PRIV_MASTER_I 0x00 /* R-B-V */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO 0x00128928 /* R--4R */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_SUBID 31:24 /* R-BVF */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_SUBID_I 0x00 /* R-B-V */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_LOCAL_ORDERING 22:22 /* R-BVF */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_LOCAL_ORDERING_I 0x0 /* R-B-V */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_PRIV_LEVEL 21:20 /* R-BVF */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_PRIV_LEVEL_I 0x0 /* R-B-V */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_SENDING_RS 17:12 /* R-BVF */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_SENDING_RS_I 0x00 /* R-B-V */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_PENDING 9:9 /* R-BVF */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_PENDING_I 0x0 /* R-B-V */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_ORPHAN 8:8 /* R-BVF */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_ORPHAN_I 0x0 /* R-B-V */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_PRIV_MASTER 7:0 /* R-BVF */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_INFO_PRIV_MASTER_I 0x00 /* R-B-V */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_CODE 0x0012812c /* R--4R */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_CODE_VALUE 31:0 /* R-BVF */
#define NV_PPRIV_PRT_PRT0_PRIV_ERROR_CODE_VALUE_I 0x00000000 /* R-B-V */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_CODE 0x0012892c /* R--4R */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_CODE_VALUE 31:0 /* R-BVF */
#define NV_PPRIV_PRT_PRT1_PRIV_ERROR_CODE_VALUE_I 0x00000000 /* R-B-V */
#define NV_PPRIV_PRT_CG1 0x00000250 /* RW-4R */
#define NV_PPRIV_PRT_CG1_SLCG_SLOWCLK 0:0 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_SLOWCLK_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_SLOWCLK_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_SLOWCLK__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_CONFIG_REGS 1:1 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_CONFIG_REGS_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_CONFIG_REGS_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_CONFIG_REGS__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_DECODER 2:2 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_DECODER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_DECODER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_DECODER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_ARB 3:3 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_ARB_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_ARB_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_FUNNEL_ARB__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_HISTORY_BUFFER 4:4 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_HISTORY_BUFFER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_HISTORY_BUFFER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_HISTORY_BUFFER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_MASTER 5:5 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_MASTER_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_MASTER_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_MASTER__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_SLAVE 6:6 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_SLAVE_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_SLAVE_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_SLAVE__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_UCODE_TRAP 7:7 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_UCODE_TRAP_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_UCODE_TRAP_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_UCODE_TRAP__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV 8:8 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_LOC_PRIV 9:9 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_LOC_PRIV_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_LOC_PRIV_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_LOC_PRIV__PROD 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PM 10:10 /* RWBVF */
#define NV_PPRIV_PRT_CG1_SLCG_PM_ENABLED 0x0 /* RW--V */
#define NV_PPRIV_PRT_CG1_SLCG_PM_DISABLED 0x1 /* RWB-V */
#define NV_PPRIV_PRT_CG1_SLCG_PM__PROD 0x0 /* RW--V */
#endif // __lr10_dev_pri_ringstation_prt_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_pri_ringstation_sys_h__
#define __lr10_dev_pri_ringstation_sys_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_SYS_PRIV_ERROR_ADR 0x00122120 /* R--4R */
#define NV_PPRIV_SYS_PRIV_ERROR_ADR_ADDRESS 25:0 /* R-BVF */
#define NV_PPRIV_SYS_PRIV_ERROR_ADR_ADDRESS_I 0x00000000 /* R-B-V */
#define NV_PPRIV_SYS_PRIV_ERROR_ADR_MOD 0x0012211c /* R--4R */
#define NV_PPRIV_SYS_PRIV_ERROR_ADR_MOD_ADDRESS 25:0 /* R-BVF */
#define NV_PPRIV_SYS_PRIV_ERROR_ADR_MOD_ADDRESS_I 0x00000000 /* R-B-V */
#define NV_PPRIV_SYS_PRIV_ERROR_WRDAT 0x00122124 /* R--4R */
#define NV_PPRIV_SYS_PRIV_ERROR_WRDAT_DATA 31:0 /* R-BVF */
#define NV_PPRIV_SYS_PRIV_ERROR_WRDAT_DATA_I 0x00000000 /* R-B-V */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO 0x00122128 /* R--4R */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_SUBID 31:24 /* R-BVF */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_SUBID_I 0x00000000 /* R-B-V */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_LOCAL_ORDERING 22:22 /* R-BVF */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_LOCAL_ORDERING_I 0x00000000 /* R-B-V */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_PRIV_LEVEL 21:20 /* R-BVF */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_PRIV_LEVEL_I 0x00000000 /* R-B-V */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_SENDING_RS 17:12 /* R-BVF */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_SENDING_RS_I 0x00000000 /* R-B-V */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_PENDING 9:9 /* R-BVF */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_PENDING_I 0x00000000 /* R-B-V */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_ORPHAN 8:8 /* R-BVF */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_ORPHAN_I 0x00000000 /* R-B-V */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_PRIV_MASTER (8-1):0 /* R-BVF */
#define NV_PPRIV_SYS_PRIV_ERROR_INFO_PRIV_MASTER_I 0x00000000 /* R-B-V */
#define NV_PPRIV_SYS_PRIV_ERROR_CODE 0x0012212c /* R--4R */
#define NV_PPRIV_SYS_PRIV_ERROR_CODE_VALUE 31:0 /* R-BVF */
#define NV_PPRIV_SYS_PRIV_ERROR_CODE_VALUE_I 0x00000000 /* R-B-V */
#endif // __lr10_dev_pri_ringstation_sys_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_route_ip_h__
#define __lr10_dev_route_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS 0x00005488 /* RW-4R */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_ERROR_ADDRESS 8:0 /* RWIVF */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_VALID 0x0000548c /* R--4R */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_ROUTE_ERR_LOG_EN_0 0x00005404 /* RW-4R */
#define NV_ROUTE_ERR_LOG_EN_0_ROUTEBUFERR 0:0 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_ROUTEBUFERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_NOPORTDEFINEDERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_INVALIDROUTEPOLICYERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_TRANSDONERESVERR 5:5 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_TRANSDONERESVERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_TRANSDONERESVERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_TRANSDONERESVERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_PDCTRLPARERR 6:6 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_PDCTRLPARERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_CDTPARERR 9:9 /* RWEVF */
#define NV_ROUTE_ERR_LOG_EN_0_CDTPARERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_LOG_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_LOG_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0 0x00005410 /* RW-4R */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_ROUTEBUFERR 0:0 /* RWEVF */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_ROUTEBUFERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_NOPORTDEFINEDERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_INVALIDROUTEPOLICYERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_GLT_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_GLT_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_TRANSDONERESVERR 5:5 /* RWEVF */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_TRANSDONERESVERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_TRANSDONERESVERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_TRANSDONERESVERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_PDCTRLPARERR 6:6 /* RWEVF */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_PDCTRLPARERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_NVS_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_NVS_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_CDTPARERR 9:9 /* RWEVF */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_CDTPARERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CORRECTABLE_REPORT_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_TIMESTAMP_LOG 0x00005450 /* R--4R */
#define NV_ROUTE_ERR_TIMESTAMP_LOG_TIMESTAMP 23:0 /* R-IVF */
#define NV_ROUTE_ERR_TIMESTAMP_LOG_TIMESTAMP_INIT 0x00000000 /* R-I-V */
#define NV_ROUTE_ERR_HEADER_LOG_VALID 0x0000544c /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_VALID_HEADERVALID0 0:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_VALID_HEADERVALID0_INVALID 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_VALID_HEADERVALID0_VALID 0x00000001 /* R---V */
#define NV_ROUTE_ERR_MISC_LOG_0 0x00005454 /* R--4R */
#define NV_ROUTE_ERR_MISC_LOG_0_SPORT 5:0 /* R-IVF */
#define NV_ROUTE_ERR_MISC_LOG_0_SPORT_INIT 0x00000000 /* R-I-V */
#define NV_ROUTE_ERR_MISC_LOG_0_ENCODEDVC 10:8 /* R-IVF */
#define NV_ROUTE_ERR_MISC_LOG_0_ENCODEDVC_INIT 0x00000000 /* R-I-V */
#define NV_ROUTE_ERR_HEADER_LOG_0 0x00005420 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_0_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_0_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_1 0x00005424 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_1_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_1_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_2 0x00005428 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_2_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_2_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_3 0x0000542c /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_3_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_3_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_4 0x00005430 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_4_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_4_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_5 0x00005434 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_5_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_5_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_6 0x00005438 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_6_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_6_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_7 0x0000543c /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_7_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_7_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_8 0x00005440 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_8_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_8_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_9 0x00005444 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_9_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_9_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_HEADER_LOG_10 0x00005448 /* R--4R */
#define NV_ROUTE_ERR_HEADER_LOG_10_DW 31:0 /* R-DVF */
#define NV_ROUTE_ERR_HEADER_LOG_10_DW_INIT 0x00000000 /* R-D-V */
#define NV_ROUTE_ERR_STATUS_0 0x00005400 /* RW-4R */
#define NV_ROUTE_ERR_STATUS_0_ROUTEBUFERR 0:0 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_ROUTEBUFERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_ROUTEBUFERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_NOPORTDEFINEDERR 1:1 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_NOPORTDEFINEDERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_NOPORTDEFINEDERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_INVALIDROUTEPOLICYERR 2:2 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_INVALIDROUTEPOLICYERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_INVALIDROUTEPOLICYERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_LIMIT_ERR 3:3 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_DBE_ERR 4:4 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_GLT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_TRANSDONERESVERR 5:5 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_TRANSDONERESVERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_TRANSDONERESVERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_PDCTRLPARERR 6:6 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_PDCTRLPARERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_PDCTRLPARERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_LIMIT_ERR 7:7 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_DBE_ERR 8:8 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_NVS_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_STATUS_0_CDTPARERR 9:9 /* RWDVF */
#define NV_ROUTE_ERR_STATUS_0_CDTPARERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_STATUS_0_CDTPARERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0 0x0000541c /* RW-4R */
#define NV_ROUTE_ERR_FIRST_0_ROUTEBUFERR 0:0 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_ROUTEBUFERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_ROUTEBUFERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_NOPORTDEFINEDERR 1:1 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_NOPORTDEFINEDERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_NOPORTDEFINEDERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_INVALIDROUTEPOLICYERR 2:2 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_INVALIDROUTEPOLICYERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_INVALIDROUTEPOLICYERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_LIMIT_ERR 3:3 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_DBE_ERR 4:4 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_GLT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_TRANSDONERESVERR 5:5 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_TRANSDONERESVERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_TRANSDONERESVERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_PDCTRLPARERR 6:6 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_PDCTRLPARERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_PDCTRLPARERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_LIMIT_ERR 7:7 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_DBE_ERR 8:8 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_NVS_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FIRST_0_CDTPARERR 9:9 /* RWDVF */
#define NV_ROUTE_ERR_FIRST_0_CDTPARERR_NONE 0x00000000 /* RWD-V */
#define NV_ROUTE_ERR_FIRST_0_CDTPARERR_CLEAR 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0 0x00005414 /* RW-4R */
#define NV_ROUTE_ERR_CONTAIN_EN_0_ROUTEBUFERR 0:0 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_ROUTEBUFERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NOPORTDEFINEDERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALIDROUTEPOLICYERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_TRANSDONERESVERR 5:5 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_TRANSDONERESVERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_TRANSDONERESVERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_TRANSDONERESVERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_PDCTRLPARERR 6:6 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_PDCTRLPARERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_CDTPARERR 9:9 /* RWEVF */
#define NV_ROUTE_ERR_CONTAIN_EN_0_CDTPARERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_CONTAIN_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_REG_TABLE_ADDRESS 0x00005080 /* RW-4R */
#define NV_ROUTE_REG_TABLE_ADDRESS_INDEX 8:0 /* RWEVF */
#define NV_ROUTE_REG_TABLE_ADDRESS_INDEX_MIN 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_ADDRESS_INDEX_GLTAB_DEPTH 0x000001ff /* RW--V */
#define NV_ROUTE_REG_TABLE_ADDRESS_AUTO_INCR 31:31 /* RWEVF */
#define NV_ROUTE_REG_TABLE_ADDRESS_AUTO_INCR_DISABLE 0x00000000 /* RW--V */
#define NV_ROUTE_REG_TABLE_ADDRESS_AUTO_INCR_ENABLE 0x00000001 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0 0x00005090 /* RW-4R */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_0 3:0 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_0_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_1 7:4 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_1_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_2 11:8 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_2_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_3 15:12 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_3_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_4 19:16 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_4_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_5 23:20 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_5_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_6 27:24 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_6_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_7 31:28 /* RWEVF */
#define NV_ROUTE_REG_TABLE_DATA0_GLX_7_INIT 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER 0x00005490 /* RW-4R */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWIVF */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWI-V */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_LIMIT 0x00005494 /* RW-4R */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWEVF */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWE-V */
#define NV_ROUTE_ERR_NVS_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL 0x00005470 /* RW-4R */
#define NV_ROUTE_ERR_ECC_CTRL_GLT_ECC_ENABLE 0:0 /* RWEVF */
#define NV_ROUTE_ERR_ECC_CTRL_GLT_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_GLT_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_ECC_CTRL_GLT_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_NVS_ECC_ENABLE 2:2 /* RWEVF */
#define NV_ROUTE_ERR_ECC_CTRL_NVS_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_ECC_CTRL_NVS_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_ECC_CTRL_NVS_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0 0x000050a0 /* RW-4R */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0 1:0 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN0_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1 5:4 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN1_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2 9:8 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN2_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3 13:12 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN3_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4 17:16 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN4_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5 21:20 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN5_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6 25:24 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN6_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7 29:28 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE0_RFUN7_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1 0x000050a4 /* RW-4R */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8 1:0 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN8_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9 5:4 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN9_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10 9:8 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN10_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11 13:12 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN11_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12 17:16 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN12_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13 21:20 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN13_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14 25:24 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN14_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15 29:28 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE1_RFUN15_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2 0x000050a8 /* RW-4R */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16 1:0 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN16_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17 5:4 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN17_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18 9:8 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN18_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19 13:12 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN19_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20 17:16 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN20_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21 21:20 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN21_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22 25:24 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN22_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23 29:28 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE2_RFUN23_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3 0x000050ac /* RW-4R */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24 1:0 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN24_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25 5:4 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN25_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26 9:8 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN26_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27 13:12 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN27_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28 17:16 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN28_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29 21:20 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN29_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30 25:24 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN30_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31 29:28 /* RWEVF */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31_SPRAY 0x00000000 /* RWE-V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31_FIXED 0x00000001 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31_RANDOM 0x00000002 /* RW--V */
#define NV_ROUTE_CMD_ROUTE_TABLE3_RFUN31_ALTERNATE 0x00000003 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL 0x00005040 /* RW-4R */
#define NV_ROUTE_ROUTE_CONTROL_SWECCENB 0:0 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_SWECCENB_HWGEN 0x00000000 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_SWECCENB_SWGEN 0x00000001 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_ECCWRITEBACKENB 1:1 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_ECCWRITEBACKENB_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_ECCWRITEBACKENB_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_URRESPERRVCMAP 3:2 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_URRESPERRVCMAP_SAME 0x00000000 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_URRESPERRVCMAP_INVERT 0x00000001 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_URRESPERRVCMAP_ALWAYS0 0x00000002 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_URRESPERRVCMAP_ALWAYS1 0x00000003 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_DEBUGENB 4:4 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_DEBUGENB_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_DEBUGENB_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_REQPORTDBGMODE 6:5 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_REQPORTDBGMODE_ERROR 0x00000000 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_REQPORTDBGMODE_ERROR2 0x00000001 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_REQPORTDBGMODE_ADDRESS 0x00000002 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_REQPORTDBGMODE_DBGPORT 0x00000003 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_VCDBGMODE 8:7 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_VCDBGMODE_SAME 0x00000000 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_VCDBGMODE_INVERT 0x00000001 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_VCDBGMODE_ALWAYS0 0x00000002 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_VCDBGMODE_ALWAYS1 0x00000003 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_RSPPORTDBGMODE 10:9 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_RSPPORTDBGMODE_ERROR 0x00000000 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_RSPPORTDBGMODE_ERROR2 0x00000001 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_RSPPORTDBGMODE_ADDRESS 0x00000002 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_RSPPORTDBGMODE_DBGPORT 0x00000003 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_URRESPENB 11:11 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_URRESPENB_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_URRESPENB_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_URRESPENB__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_KILLURTD 12:12 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_KILLURTD_DISABLE 0x00000000 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_KILLURTD_ENABLE 0x00000001 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_TRANSDONERESVOVERRIDE 13:13 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_TRANSDONERESVOVERRIDE_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_TRANSDONERESVOVERRIDE_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_TRANSDONERESVENABLE 14:14 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_TRANSDONERESVENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_TRANSDONERESVENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_PASSPING 15:15 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_PASSPING_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_PASSPING_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_HOPINNXBAR 19:19 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_HOPINNXBAR_DISABLE 0x00000000 /* RW--V */
#define NV_ROUTE_ROUTE_CONTROL_HOPINNXBAR_ENABLE 0x00000001 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_STOREANDFORWARD 24:24 /* RWEVF */
#define NV_ROUTE_ROUTE_CONTROL_STOREANDFORWARD_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ROUTE_CONTROL_STOREANDFORWARD_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0 0x00005408 /* RW-4R */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_ROUTEBUFERR 0:0 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_ROUTEBUFERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NOPORTDEFINEDERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_TRANSDONERESVERR 5:5 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_TRANSDONERESVERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_TRANSDONERESVERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_TRANSDONERESVERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_PDCTRLPARERR 6:6 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_PDCTRLPARERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_CDTPARERR 9:9 /* RWEVF */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_CDTPARERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_FATAL_REPORT_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0 0x0000540c /* RW-4R */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_ROUTEBUFERR 0:0 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_ROUTEBUFERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_ROUTEBUFERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_ROUTEBUFERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NOPORTDEFINEDERR 1:1 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NOPORTDEFINEDERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NOPORTDEFINEDERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NOPORTDEFINEDERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR 2:2 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_INVALIDROUTEPOLICYERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR 3:3 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR 4:4 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_GLT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_TRANSDONERESVERR 5:5 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_TRANSDONERESVERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_TRANSDONERESVERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_TRANSDONERESVERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_PDCTRLPARERR 6:6 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_PDCTRLPARERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_PDCTRLPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_PDCTRLPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_NVS_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_CDTPARERR 9:9 /* RWEVF */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_CDTPARERR__PROD 0x00000000 /* RW--V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_CDTPARERR_DISABLE 0x00000000 /* RWE-V */
#define NV_ROUTE_ERR_NON_FATAL_REPORT_EN_0_CDTPARERR_ENABLE 0x00000001 /* RW--V */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_LIMIT 0x00005484 /* RW-4R */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWEVF */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWE-V */
#define NV_ROUTE_ERR_GLT_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#endif // __lr10_dev_route_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_route_ip_addendum_h__
#define __lr10_dev_route_ip_addendum_h__
// NV_ROUTE_REG_TABLE_DATA0 definition in the manuals have no indexing.
#define NV_ROUTE_REG_TABLE_DATA0_GLX(i) 4*(i)+3:4*(i)+0
#endif // __lr10_dev_route_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_soe_ip_addendum_h__
#define __lr10_dev_soe_ip_addendum_h__
//
// The detail description about each of the mutex can be found in
// <branch>/drivers/resman/arch/nvalloc/common/inc/nv_mutex.h
//
// Enums in the following file will also need to be updated:
// <branch>/drivers/nvswitch/common/inc/soemutexreservation.h
//
#define NV_SOE_MUTEX_DEFINES \
NV_MUTEX_ID_SOE_EMEM_ACCESS, \
#define NV_SOE_EMEM_ACCESS_PORT_NVSWITCH (0)
#define NV_SOE_EMEM_ACCESS_PORT_NVWATCH (1)
#define UNUSED_EMEM_ACCESS_PORT_2 (2)
#define UNUSED_EMEM_ACCESS_PORT_3 (3)
#define NUM_SAW_ENGINE 1
#define NUM_NVLINK_ENGINE 9
#define NUM_TLC_ENGINE 36
#define NUM_NVLIPT_LNK_ENGINE 36
#define NV_PRIV_OFFSET_NVLSAW 0x00028000
#define NV_GFW_SOE_EXIT_AND_HALT (NV_PRIV_OFFSET_NVLSAW + NV_NVLSAW_SW_SCRATCH_15)
#define NV_GFW_SOE_EXIT_AND_HALT_REQUESTED 0:0
#define NV_GFW_SOE_EXIT_AND_HALT_REQUESTED_YES 0x1
#define NV_GFW_SOE_EXIT_AND_HALT_REQUESTED_NO 0x0
#define NV_GFW_SOE_EXIT_AND_HALT_TIMEOUT 150000 //150ms
#define NV_GFW_SOE_BOOT (NV_PRIV_OFFSET_NVLSAW + NV_NVLSAW_SW_SCRATCH_3)
#define NV_GFW_SOE_BOOT_PROGRESS 7:0
#define NV_GFW_SOE_BOOT_PROGRESS_NOT_STARTED 0x00000000
#define NV_GFW_SOE_BOOT_PROGRESS_STARTED 0x00000001
#define NV_GFW_SOE_BOOT_PROGRESS_SECURE_DATA_VERIFY_DONE 0x00000002
#define NV_GFW_SOE_BOOT_PROGRESS_SYSTEM_VALIDITY_DONE 0x00000003
#define NV_GFW_SOE_BOOT_PROGRESS_PRELTSSM_OVERRIDES_DONE 0x00000004
#define NV_GFW_SOE_BOOT_PROGRESS_REPORT_INFOROM_CARVEOUT_DONE 0x00000005
#define NV_GFW_SOE_BOOT_PROGRESS_REPORT_ROMDIR_DONE 0x00000006
#define NV_GFW_SOE_BOOT_PROGRESS_REPORT_ERASE_LEDGER_DONE 0x00000007
#define NV_GFW_SOE_BOOT_PROGRESS_FW_SECURITY_INIT_DONE 0x00000008
#define NV_GFW_SOE_BOOT_PROGRESS_POSTLTSSM_OVERRIDES_DONE 0x00000009
#define NV_GFW_SOE_BOOT_PROGRESS_IMAGE_VERIFY_DONE 0x0000000A
#define NV_GFW_SOE_BOOT_PROGRESS_COMPLETED 0x000000FF
#define NV_GFW_SOE_BOOT_VALIDATION_STATUS 10:8
#define NV_GFW_SOE_BOOT_VALIDATION_STATUS_UNSUPPORTED 0x00000000
#define NV_GFW_SOE_BOOT_VALIDATION_STATUS_IN_PROGRESS 0x00000001
#define NV_GFW_SOE_BOOT_VALIDATION_STATUS_PASS_NO_TRUST 0x00000002
#define NV_GFW_SOE_BOOT_VALIDATION_STATUS_PASS_TRUSTED 0x00000003
#define NV_GFW_SOE_BOOT_VALIDATION_STATUS_FAIL 0x00000004
#define NV_GFW_SOE_BOOT_VALIDATION_STATUS_PASS_UNTRUSTED 0x00000005
#define NV_GFW_SOE_BOOT_VALIDATION_STATUS_WARN_NO_TRUST 0x00000006
#define NV_GFW_SOE_BOOT_VALIDATION_STATUS_WARN_TRUSTED 0x00000007
#define NV_GFW_SOE_PROGRESS_CODE (NV_PRIV_OFFSET_NVLSAW + NV_NVLSAW_SW_SCRATCH_13)
#define NV_GFW_SOE_PROGRESS_CODE_VALUE 3:0
#define NV_GFW_SOE_PROGRESS_CODE_VALUE_NOT_STARTED 0x00000000
#define NV_GFW_SOE_PROGRESS_CODE_VALUE_STARTED 0x00000001
#define NV_GFW_SOE_PROGRESS_CODE_VALUE_EXIT 0x00000002
#define NV_GFW_SOE_PROGRESS_CODE_VALUE_EXIT_SECUREMODE 0x00000003
#define NV_GFW_SOE_PROGRESS_CODE_VALUE_ABORTED 0x00000004
#define NV_GFW_SOE_PROGRESS_CODE_VALUE_COMPLETED 0x00000005
#define NV_SOE_RESET_SEQUENCE (NV_PRIV_OFFSET_NVLSAW + NV_NVLSAW_SW_SCRATCH_15)
#define NV_SOE_RESET_SEQUENCE_REQUESTED 0:0
#define NV_SOE_RESET_SEQUENCE_REQUESTED_YES 0x00000001
#define NV_SOE_RESET_SEQUENCE_REQUESTED_NO 0x00000000
#define NUM_NPG_ENGINE 9
#define NUM_NPG_BCAST_ENGINE 1
#define NUM_NPORT_ENGINE 36
#define NUM_NPORT_MULTICAST_BCAST_ENGINE 1
#define NUM_NXBAR_ENGINE 4
#define NUM_NXBAR_BCAST_ENGINE 1
#define NUM_TILE_ENGINE 16
#define NUM_TILE_MULTICAST_BCAST_ENGINE 1
#define NUM_NVLW_ENGINE 9
#define NUM_BUS_ENGINE 1
#define NUM_GIN_ENGINE 0
#define NUM_SYS_PRI_HUB 0
#define NUM_PRI_MASTER_RS 0
#define NUM_MINION_ENGINE NUM_NVLW_ENGINE
#endif // __lr10_dev_soe_ip_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_sourcetrack_ip_h__
#define __lr10_dev_sourcetrack_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_ADDRESS 0x000064a8 /* R--4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS 9:0 /* R-DVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID 0x000064ac /* R--4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS 0x00006488 /* R--4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS 9:0 /* R-DVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID 0x0000648c /* R--4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_TD_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT 0x00006494 /* RW-4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_TD_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_TD_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_TD_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0 0x00006404 /* RW-4R */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR 13:13 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR 15:15 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR 28:28 /* RWEVF */
#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_LOG_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0 0x00006410 /* RW-4R */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR 13:13 /* RWEVF */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR 15:15 /* RWEVF */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR 28:28 /* RWEVF */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CORRECTABLE_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0 0x00006414 /* RW-4R */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR 13:13 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR 15:15 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR 28:28 /* RWEVF */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_CONTAIN_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_STATUS_0 0x00006400 /* RW-4R */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR 5:5 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR 7:7 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 8:8 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR 13:13 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR 15:15 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_STATUS_0_SOURCETRACK_TIME_OUT_ERR 28:28 /* RWDVF */
#define NV_SOURCETRACK_ERR_STATUS_0_SOURCETRACK_TIME_OUT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_STATUS_0_SOURCETRACK_TIME_OUT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0 0x0000641c /* RW-4R */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR 5:5 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR 7:7 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 8:8 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR 13:13 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR 15:15 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FIRST_0_SOURCETRACK_TIME_OUT_ERR 28:28 /* RWDVF */
#define NV_SOURCETRACK_ERR_FIRST_0_SOURCETRACK_TIME_OUT_ERR_NONE 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_FIRST_0_SOURCETRACK_TIME_OUT_ERR_CLEAR 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER 0x00006480 /* RW-4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT 0x00006484 /* RW-4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_COUNTER 0x000064a0 /* RW-4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT 0x000064a4 /* RW-4R */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
#define NV_SOURCETRACK_ERR_CREQ_TCEN1_CRUMBSTORE_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT__PROD 0x007fffff /* RW--V */
#define NV_SOURCETRACK_ERR_ECC_CTRL 0x00006470 /* RW-4R */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE 0:0 /* RWEVF */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_TD_CRUMBSTORE_ECC_ENABLE 5:5 /* RWEVF */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_TD_CRUMBSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_TD_CRUMBSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN0_TD_CRUMBSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN1_CRUMBSTORE_ECC_ENABLE 7:7 /* RWEVF */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN1_CRUMBSTORE_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN1_CRUMBSTORE_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_ECC_CTRL_CREQ_TCEN1_CRUMBSTORE_ECC_ENABLE__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_CTRL 0x00006040 /* RW-4R */
#define NV_SOURCETRACK_CTRL_COL_RSP_DIS 0:0 /* RWEVF */
#define NV_SOURCETRACK_CTRL_COL_RSP_DIS_OFF 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_CTRL_COL_RSP_DIS_ON 0x00000001 /* RW--V */
#define NV_SOURCETRACK_CTRL_STO_ENB 9:9 /* RWEVF */
#define NV_SOURCETRACK_CTRL_STO_ENB_ON 0x00000001 /* RWE-V */
#define NV_SOURCETRACK_CTRL_STO_ENB_OFF 0x00000000 /* RW--V */
#define NV_SOURCETRACK_MULTISEC_TIMER0 0x00006044 /* RW-4R */
#define NV_SOURCETRACK_MULTISEC_TIMER0_TIMERVAL0 19:0 /* RWEVF */
#define NV_SOURCETRACK_MULTISEC_TIMER0_TIMERVAL0_INIT 0x00002710 /* RWE-V */
#define NV_SOURCETRACK_MULTISEC_TIMER0_TIMERVAL0__PROD 0x00004000 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0 0x00006408 /* RW-4R */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR 13:13 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR 15:15 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR 28:28 /* RWEVF */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0 0x0000640c /* RW-4R */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR 0:0 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR 5:5 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR 7:7 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR__PROD 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR 8:8 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR 13:13 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR 15:15 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR 28:28 /* RWEVF */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR__PROD 0x00000000 /* RW--V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_DISABLE 0x00000000 /* RWE-V */
#define NV_SOURCETRACK_ERR_NON_FATAL_REPORT_EN_0_SOURCETRACK_TIME_OUT_ERR_ENABLE 0x00000001 /* RW--V */
#endif // __lr10_dev_sourcetrack_ip_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_therm_h__
#define __lr10_dev_therm_h__
/* This file is autogenerated. Do not edit */
#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES 0x00066f44 /* RW-4R */
#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES_WARNING_TEMPERATURE 13:0 /* RWIVF */
#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES_WARNING_TEMPERATURE_INIT 0x00000e60 /* RWI-V */
#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES_OVERTEMP_TEMPERATURE 29:16 /* RWIVF */
#define NV_THERM_TSENSE_THRESHOLD_TEMPERATURES_OVERTEMP_TEMPERATURE_INIT 0x000012c0 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS 0x00066f28 /* RW-4R */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET 13:0 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OFFSET_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE 29:16 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN 31:31 /* RWIVF */
#define NV_THERM_TSENSE_U2_A_0_BJT_0_TEMPERATURE_MODIFICATIONS_TEMPERATURE_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */
#define NV_THERM_TSENSE_MAXIMUM_TEMPERATURE 0x00066f40 /* R--4R */
#define NV_THERM_TSENSE_MAXIMUM_TEMPERATURE_MAXIMUM_TEMPERATURE 13:0 /* R--VF */
#define NV_THERM_TSENSE_MAXIMUM_TEMPERATURE_MAX_TEMP_SENSE_NUMBER 21:16 /* R--VF */
#define NV_THERM_MSGBOX_COMMAND 0x000660e0 /* RW-4R */
#define NV_THERM_MSGBOX_COMMAND_DATA 30:0 /* RWIVF */
#define NV_THERM_MSGBOX_COMMAND_DATA_INIT 0x00000000 /* RWI-V */
#define NV_THERM_MSGBOX_COMMAND_INTR 31:31 /* RWIVF */
#define NV_THERM_MSGBOX_COMMAND_INTR_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_THERM_MSGBOX_COMMAND_INTR_PENDING 0x00000001 /* RW--V */
#endif // __lr10_dev_therm_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_timer_h__
#define __lr10_dev_timer_h__
/* This file is autogenerated. Do not edit */
#define NV_PTIMER_PRI_TMR_CG1 0x00029600 /* RW-4R */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG 1:1 /* RWIVF */
#define NV_PTIMER_PRI_TMR_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG__PROD 0x00000000 /* RW--V */
#endif // __lr10_dev_timer_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_trim_h__
#define __lr10_dev_trim_h__
/* This file is autogenerated. Do not edit */
#define NV_PCLOCK_NVSW_CLK_DIST_MODE 0x0002402C /* RW-4R */
#define NV_PCLOCK_NVSW_CLK_DIST_MODE_SWITCH2CLK_DIST_MODE 0:0 /* RWAUF */
#define NV_PCLOCK_NVSW_CLK_DIST_MODE_SWITCH2CLK_DIST_MODE_1XCLK 0x00000000 /* RW--V */
#define NV_PCLOCK_NVSW_CLK_DIST_MODE_SWITCH2CLK_DIST_MODE_2XCLK 0x00000001 /* RW--V */
#define NV_PCLOCK_NVSW_CLK_DIST_MODE_SWITCH2CLK_DIST_MODE_INIT 0x00000000 /* RWA-V */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF 0x00024004 /* RW-4R */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF_MDIV 7:0 /* RWAUF */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF_MDIV_INIT 0x00000003 /* RWA-V */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF_NDIV 15:8 /* RWAUF */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF_NDIV_INIT 0x00000050 /* RWA-V */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF_NDIV_MIN 0x00000001 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF_PLDIV 21:16 /* RWAUF */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF_PLDIV_INIT 0x00000002 /* RWA-V */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF_PLDIV_MAX 0x0000001F /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG 0x00024000 /* RW-4R */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_ENABLE 0:0 /* RWAUF */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_ENABLE_INIT 0x00000000 /* RWA-V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_IDDQ 1:1 /* RWAUF */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_IDDQ_INIT 0x00000001 /* RWA-V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_SYNC_MODE 2:2 /* RWAUF */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_SYNC_MODE_INIT 0x00000001 /* RWA-V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_PLL_LOCK 17:17 /* R--UF */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_PLL_SSA 18:18 /* R--UF */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_PLL_SSD 19:19 /* R--UF */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_BYPASSPLL_CYA 21:21 /* RWAUF */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_BYPASSPLL_CYA_INIT 0x00000000 /* RWA-V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_LOOP_CTRL 23:22 /* RWAUF */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_LOOP_CTRL_INIT 0x00000000 /* RWA-V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_PLL_FREQLOCK 24:24 /* R--UF */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_PLL_FREQLOCK_NO 0x00000000 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_PLL_FREQLOCK_YES 0x00000001 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_RESETB 25:25 /* RWAUF */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_RESETB_INIT 0x00000000 /* RWA-V */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_SEL_TESTOUT 28:26 /* RWAUF */
#define NV_PCLOCK_NVSW_SWITCHPLL_CFG_SEL_TESTOUT_INIT 0x00000000 /* RWA-V */
#define NV_PCLOCK_NVSW_SWITCHCLK 0x00024050 /* RW-4R */
#define NV_PCLOCK_NVSW_SWITCHCLK_MUX 7:0 /* RWAUF */
#define NV_PCLOCK_NVSW_SWITCHCLK_MUX_INIT 0x00000001 /* RWA-V */
#define NV_PCLOCK_NVSW_SWITCHCLK_MUX_NVLINK_TXREFCLK 0x00000010 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHCLK_MUX_PCIE_TXREFCLK 0x00000004 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHCLK_MUX_PEX_REFCLK 0x00000001 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHCLK_MUX_PEX_REFCLK_FILLER1 0x00000020 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHCLK_MUX_PEX_REFCLK_FILLER2 0x00000040 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHCLK_MUX_PEX_REFCLK_FILLER3 0x00000080 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHCLK_MUX_SWITCHPLL 0x00000008 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHCLK_MUX_TESTCLK 0x00000002 /* RW--V */
#define NV_PCLOCK_NVSW_SWITCHCLK_RDY_PEX_REFCLK 8:8 /* R--UF */
#define NV_PCLOCK_NVSW_SWITCHCLK_RDY_TESTCLK 9:9 /* R--UF */
#define NV_PCLOCK_NVSW_SWITCHCLK_RDY_PCIE_TXREFCLK 10:10 /* R--UF */
#define NV_PCLOCK_NVSW_SWITCHCLK_RDY_SWITCHPLL 11:11 /* R--UF */
#define NV_PCLOCK_NVSW_SWITCHCLK_RDY_NVLINK_TXREFCLK 12:12 /* R--UF */
#define NV_PCLOCK_NVSW_SWITCHCLK_RDY_PEX_REFCLK_FILLER1 13:13 /* R--UF */
#define NV_PCLOCK_NVSW_SWITCHCLK_RDY_PEX_REFCLK_FILLER2 14:14 /* R--UF */
#define NV_PCLOCK_NVSW_SWITCHCLK_RDY_PEX_REFCLK_FILLER3 15:15 /* R--UF */
#define NV_PCLOCK_NVSW_SYSTEMCLK 0x00024080 /* RW-4R */
#define NV_PCLOCK_NVSW_SYSTEMCLK_MUX 7:0 /* RWAUF */
#define NV_PCLOCK_NVSW_SYSTEMCLK_MUX_INIT 0x00000001 /* RWA-V */
#define NV_PCLOCK_NVSW_SYSTEMCLK_MUX_NVLINK_TXREFCLK 0x00000010 /* RW--V */
#define NV_PCLOCK_NVSW_SYSTEMCLK_MUX_PCIE_TXREFCLK 0x00000004 /* RW--V */
#define NV_PCLOCK_NVSW_SYSTEMCLK_MUX_PEX_REFCLK 0x00000001 /* RW--V */
#define NV_PCLOCK_NVSW_SYSTEMCLK_MUX_PEX_REFCLK_FILLER 0x00000002 /* RW--V */
#define NV_PCLOCK_NVSW_SYSTEMCLK_MUX_PEX_REFCLK_FILLER1 0x00000020 /* RW--V */
#define NV_PCLOCK_NVSW_SYSTEMCLK_MUX_PEX_REFCLK_FILLER2 0x00000040 /* RW--V */
#define NV_PCLOCK_NVSW_SYSTEMCLK_MUX_PEX_REFCLK_FILLER3 0x00000080 /* RW--V */
#define NV_PCLOCK_NVSW_SYSTEMCLK_MUX_SWITCHPLL 0x00000008 /* RW--V */
#define NV_PCLOCK_NVSW_SYSTEMCLK_SYSTEMCLK_RDY_PEX_REFCLK 8:8 /* R--UF */
#define NV_PCLOCK_NVSW_SYSTEMCLK_SYSTEMCLK_RDY_PEX_REFCLK_FILLER 9:9 /* R--UF */
#define NV_PCLOCK_NVSW_SYSTEMCLK_SYSTEMCLK_RDY_PCIE_TXREFCLK 10:10 /* R--UF */
#define NV_PCLOCK_NVSW_SYSTEMCLK_SYSTEMCLK_RDY_SWITCHPLL 11:11 /* R--UF */
#define NV_PCLOCK_NVSW_SYSTEMCLK_SYSTEMCLK_RDY_NVLINK_TXREFCLK 12:12 /* R--UF */
#define NV_PCLOCK_NVSW_SYSTEMCLK_SYSTEMCLK_RDY_PEX_REFCLK_FILLER1 13:13 /* R--UF */
#define NV_PCLOCK_NVSW_SYSTEMCLK_SYSTEMCLK_RDY_PEX_REFCLK_FILLER2 14:14 /* R--UF */
#define NV_PCLOCK_NVSW_SYSTEMCLK_SYSTEMCLK_RDY_PEX_REFCLK_FILLER3 15:15 /* R--UF */
#define NV_PCLOCK_NVSW_JTAGINTFC 0x00024030 /* RW-4R */
#define NV_PCLOCK_NVSW_JTAGINTFC_CLK_DIVSEL 2:0 /* RWAUF */
#define NV_PCLOCK_NVSW_JTAGINTFC_CLK_DIVSEL_INIT 0x00000001 /* RWA-V */
#define NV_PCLOCK_NVSW_JTAGINTFC_JTAGTM_INTFC_CLK_EN 3:3 /* RWAUF */
#define NV_PCLOCK_NVSW_JTAGINTFC_JTAGTM_INTFC_CLK_EN_INIT 0x00000001 /* RWA-V */
#define NV_PCLOCK_NVSW_JTAGINTFC_JTAGTM_INTFC_CLK_EN_OFF 0x00000000 /* RW--V */
#define NV_PCLOCK_NVSW_JTAGINTFC_JTAGTM_INTFC_CLK_EN_ON 0x00000001 /* RW--V */
#define NV_PCLOCK_NVSW_RX_BYPASS_REFCLK 0x00024090 /* RW-4R */
#define NV_PCLOCK_NVSW_RX_BYPASS_REFCLK_DISABLE 0:0 /* RWAUF */
#define NV_PCLOCK_NVSW_RX_BYPASS_REFCLK_DISABLE_INIT 0x00000000 /* RWA-V */
#define NV_PCLOCK_NVSW_RX_BYPASS_REFCLK_DIV_SYNC_WAIT 3:1 /* RWAUF */
#define NV_PCLOCK_NVSW_RX_BYPASS_REFCLK_DIV_SYNC_WAIT_INIT 0x00000001 /* RWA-V */
#define NV_PCLOCK_NVSW_RX_BYPASS_REFCLK_DIV 13:4 /* RWAUF */
#define NV_PCLOCK_NVSW_RX_BYPASS_REFCLK_DIV_INIT 0x0000000C /* RWA-V */
#define NV_PCLOCK_NVSW_RX_BYPASS_REFCLK_REFCLK_BUF_EN_CYA 14:14 /* RWAUF */
#define NV_PCLOCK_NVSW_RX_BYPASS_REFCLK_REFCLK_BUF_EN_CYA_INIT 0x00000000 /* RWA-V */
#define NV_PCLOCK_NVSW_RX_BYPASS_REFCLK_REFCLK_BUF_EN_OVERRIDE 15:15 /* RWAUF */
#define NV_PCLOCK_NVSW_RX_BYPASS_REFCLK_REFCLK_BUF_EN_OVERRIDE_INIT 0x00000000 /* RWA-V */
#endif // __lr10_dev_trim_h__

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