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Andy Ritger
2022-05-09 13:18:59 -07:00
commit 1739a20efc
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86
src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* @brief Defines for simplifying SW accesses to the dev_ctrl interrupt tree.
* These are generic defines ued in addition to architecure-specific
* defines in dev_vm_addendum.h
*
*/
//
// Notes on the terms used below:
// Subtree: The HW tree is a 64-way tree that consists of 2 TOP level interrupt
// registers, 32 bits each. Each of these 64 is referred to as a subtree.
// Leaf: Each of these 64 subtrees are associated with a pair of LEAF registers
// giving us a total of 128 LEAF registers.
// GPU vector: The 128 LEAF registers give us a total of (128*32) GPU vectors
// giving us a total of 4096 GPU vectors
//
//
// Given a subtree index, the below macros give us the index of the TOP level
// register and the bit within the TOP level register to program for that
// subtree.
//
#define NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i) ((i) / 32)
#define NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(i) ((i) % 32)
//
// Given a subtree index, the below macros give us the two LEAF register indices
// that correspond to that subtree.
//
#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(i) ((i)*2)
#define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(i) (((i)*2) + 1)
//
// Given a LEAF register index, the below macros give us the range of GPU
// interrupt vectors that correspond to those leafs.
//
#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START(i) ((i)*32)
#define NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_END(i) (((i)*32) + 31)
//
// Given a GPU interrupt vector, the below macros give us the index of the
// LEAF register and the bit within the LEAF register to program for that
// GPU interrupt vector.
//
#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i) ((i) / 32)
#define NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(i) ((i) % 32)
//
// Given a GPU interrupt vector, the below macro gives us the subtree in which
// it belongs.
//
#define NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(i) ((NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2)
//
// The max number of leaf registers we expect
// This is enforced to be greater than or equal to
// (NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_STALL_SUBTREE_LAST) + 1)
// for the largest NV_CPU_INTR_STALL_SUBTREE_LAST
//
#define NV_MAX_INTR_LEAVES 12
// In SW, this specifies an invalid interrupt vector
#define NV_INTR_VECTOR_INVALID (NV_U32_MAX)

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src/nvidia/arch/nvalloc/common/inc/flcnifcmn.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* flcn Command/Message Interfaces - Common
*/
#ifndef FLCNIFCMN_H
#define FLCNIFCMN_H
#include "nvtypes.h"
#include "flcnretval.h"
#ifndef NV_SIZEOF32
#define NV_SIZEOF32(v) (sizeof(v))
#endif
#ifndef NV_ARRAY_ELEMENTS
#define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0])))
#endif
/*!
* @ref NvU64_ALIGN32 , NvU64_ALIGN32_PACK, NvU64_ALIGN32_UNPACK
* TODO: Use NV types directly
*/
typedef NvU64_ALIGN32 RM_FLCN_U64;
typedef NvU64_ALIGN32 *PRM_FLCN_U64;
#define RM_FLCN_U64_IS_ZERO NvU64_ALIGN32_IS_ZERO
#define RM_FLCN_U64_PACK NvU64_ALIGN32_PACK
#define RM_FLCN_U64_UNPACK NvU64_ALIGN32_UNPACK
/*!
* @brief Header preceding each CMD/MSG exchanged through falcon's queues.
*
* @note Data package sent to falcon are referred as CMDs (commands).
* Data package sent by falcon are referred as MSGs (messages).
*/
typedef struct
{
/*!
* Unit ID identifies falcon's task/unit receiving/issuing this message.
*/
NvU8 unitId;
/*!
* Total CMD/MSG size (including header).
*/
NvU8 size;
/*!
* Flags identifying state of CMD/MSG.
*/
NvU8 ctrlFlags;
/*!
* Sequence # ID to track each request sent to falcon (where applicable).
*/
NvU8 seqNumId;
} RM_FLCN_QUEUE_HDR,
*PRM_FLCN_QUEUE_HDR;
/*!
* Convenience macro for determining the size of the falcon's queue header:
*/
#define RM_FLCN_QUEUE_HDR_SIZE sizeof(RM_FLCN_QUEUE_HDR)
/*!
* Generic Falcon rewind unit ID.
*/
#define RM_FLCN_UNIT_ID_REWIND (0x00U)
/*!
* Generic CMD structure to hold the header.
*/
typedef struct
{
RM_FLCN_QUEUE_HDR hdr;
NvU32 cmd;
} RM_FLCN_CMD_GEN;
/*!
* Generic MSG structure to hold the header.
*/
typedef struct
{
RM_FLCN_QUEUE_HDR hdr;
NvU32 msg;
} RM_FLCN_MSG_GEN;
/*!
* Convenience macros for determining the size of body for a command or message:
*/
#define RM_FLCN_CMD_BODY_SIZE(u,t) sizeof(RM_FLCN_##u##_CMD_##t)
#define RM_FLCN_MSG_BODY_SIZE(u,t) sizeof(RM_FLCN_##u##_MSG_##t)
/*!
* Convenience macros for determining the size of a command or message:
*/
#define RM_FLCN_CMD_SIZE(u,t) \
(RM_FLCN_QUEUE_HDR_SIZE + RM_FLCN_CMD_BODY_SIZE(u,t))
#define RM_FLCN_MSG_SIZE(u,t) \
(RM_FLCN_QUEUE_HDR_SIZE + RM_FLCN_MSG_BODY_SIZE(u,t))
/*!
* Convenience macros for determining the type of a command or message
* (intended to be used symmetrically with the CMD and MSG _SIZE macros):
*/
#define RM_FLCN_CMD_TYPE(u,t) RM_FLCN_##u##_CMD_ID_##t
#define RM_FLCN_MSG_TYPE(u,t) RM_FLCN_##u##_MSG_ID_##t
/*!
* @brief Falcons' queue header flags (@ref RM_FLCN_QUEUE_HDR::ctrlFlags).
*
* RM_FLCN_QUEUE_FLAGS_STATUS
* Set by command's sender to request back message confirming the completion of
* command's execution. In RM->FLCN communication response is required to free
* command related data tracked within RM (***_SEQ_INFO).
*
* RM_FLCN_QUEUE_HDR_FLAGS_EVENT
* Set by the falcon to distinguish messages sent to RM from command responses.
*
* RM_FLCN_QUEUE_HDR_FLAGS_UNIT_ACK
* Used internally within the falcon to track completed commands when updating
* get (tail) command queue pointers.
*/
#define RM_FLCN_QUEUE_HDR_FLAGS_STATUS NVBIT(0)
#define RM_FLCN_QUEUE_HDR_FLAGS_EVENT NVBIT(2)
#define RM_FLCN_QUEUE_HDR_FLAGS_UNIT_ACK NVBIT(5)
#endif // FLCNIFCMN_H

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src/nvidia/arch/nvalloc/common/inc/flcnretval.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* @file flcnretval.h
* @brief Defines various status codes that are convenient to relay status
* information in functions.
*/
#ifndef FLCNRETVAL_H
#define FLCNRETVAL_H
#include "nvtypes.h"
/*!
* Defines a generic type that may be used to convey status information. This
* is very similar to the RM_STATUS type but smaller in width to save DMEM and
* stack space.
*/
typedef NvU8 FLCN_STATUS;
#define FLCN_OK (0x00U)
#define FLCN_ERR_BINARY_NOT_STARTED (0xFEU)
#define FLCN_ERROR (0xFFU)
#define FLCN_ERR_NOT_SUPPORTED (0x01U)
#define FLCN_ERR_INVALID_ARGUMENT (0x02U)
#define FLCN_ERR_ILLEGAL_OPERATION (0x03U)
#define FLCN_ERR_TIMEOUT (0x04U)
#define FLCN_ERR_NO_FREE_MEM (0x05U)
#define FLCN_ERR_HDCP_INVALID_SRM (0x06U)
#define FLCN_ERR_HDCP_RECV_REVOKED (0x07U)
#define FLCN_ERR_RPC_INVALID_INPUT (0x08U)
#define FLCN_ERR_DMA_SUSPENDED (0x09U)
#define FLCN_ERR_MUTEX_ACQUIRED (0x10U)
#define FLCN_ERR_MUTEX_ID_NOT_AVAILABLE (0x11U)
#define FLCN_ERR_OBJECT_NOT_FOUND (0x12U)
#define FLCN_ERR_MSGBOX_TIMEOUT (0x13U)
#define FLCN_ERR_INVALID_INDEX (0x14U)
#define FLCN_ERR_INVALID_FUNCTION (0x15U)
#define FLCN_ERR_INSUFFICIENT_PMB_PLM_PROTECTION (0x16U)
#define FLCN_ERR_DMA_NACK (0x17U)
#define FLCN_ERR_CHIP_NOT_SUPPORTED_FOR_PR (0x18U)
#define FLCN_ERR_BAR0_PRIV_READ_ERROR (0x19U)
#define FLCN_ERR_BAR0_PRIV_WRITE_ERROR (0x1AU)
#define FLCN_ERR_HDCP22_ABORT_AUTHENTICATION (0x1BU)
#define FLCN_ERR_DPU_IS_BUSY (0x1CU)
#define FLCN_ERR_DPU_TIMEOUT_FOR_HDCP_TYPE1_LOCK_REQUEST (0x1DU)
#define FLCN_ERR_HDCP_TYPE1_LOCK_FAILED (0x1EU)
#define FLCN_ERR_HDCP_TYPE1_LOCK_UNKNOWN (0x1FU)
#define FLCN_ERR_WAIT_FOR_BAR0_IDLE_FAILED (0x20U)
#define FLCN_ERR_CSB_PRIV_READ_ERROR (0x21U)
#define FLCN_ERR_CSB_PRIV_WRITE_ERROR (0x22U)
#define FLCN_ERR_DMA_UNEXPECTED_DMAIDX (0x23U)
#define FLCN_ERR_PRIV_SEC_VIOLATION (0x24U)
#define FLCN_ERR_INVALID_VERSION (0x25U)
#define FLCN_ERR_PR_SHARED_STRUCT_INIT_FAILED (0x26U)
#define FLCN_ERR_GPU_IN_DEBUG_MODE (0x27U)
#define FLCN_ERR_HPD_UNPLUG (0x28U)
#define FLCN_ERR_HDCP22_DELAY_ABORT_AUTHENTICATION (0x29U)
#define FLCN_ERR_SECUREBUS_REGISTER_READ_ERROR (0x2AU)
#define FLCN_ERR_SECUREBUS_REGISTER_WRITE_ERROR (0x2BU)
#define FLCN_ERR_HDCP22_FLUSH_TYPE_LOCK_ACTIVE (0x2CU)
#define FLCN_ERR_HDCP22_FLUSH_TYPE_IN_PROGRESS (0x2DU)
#define FLCN_ERR_FEATURE_NOT_ENABLED (0x2EU)
#define FLCN_ERR_OUT_OF_RANGE (0x2FU)
// I2C Errors
#define FLCN_ERR_I2C_BUSY (0x30U)
#define FLCN_ERR_I2C_NACK_ADDRESS (0x31U)
#define FLCN_ERR_I2C_NACK_BYTE (0x32U)
#define FLCN_ERR_I2C_SIZE (0x33U)
#define FLCN_ERR_I2C_BUS_INVALID (0x34U)
#define FLCN_ERR_INVALID_STATE (0x35U)
#define FLCN_ERR_RECURSION_LIMIT_EXCEEDED (0x36U)
#define FLCN_ERR_INVALID_CAST (0x37U)
// AUX Errors
#define FLCN_ERR_AUX_ERROR (0x3AU)
#define FLCN_ERR_AUX_SEMA_ACQUIRED (0x3BU)
#define FLCN_ERR_AUX_SEMA_INVALID_RELEASE (0x3CU)
#define FLCN_ERR_MORE_PROCESSING_REQUIRED (0x3EU)
#define FLCN_ERR_DMA_ALIGN (0x3FU)
// Power-Device Errors
#define FLCN_ERR_PWR_DEVICE_TAMPERED (0x40U)
#define FLCN_ERR_ITERATION_END (0x41U)
// Perf change sequence Errors
#define FLCN_ERR_LOCK_NOT_AVAILABLE (0x42U)
#define FLCN_ERR_STATE_RESET_NEEDED (0x43U)
#define FLCN_ERR_DMA_GENERIC (0x44U)
#define FLCN_ERR_LS_CHK_UCODE_REVOKED (0x45U)
#define FLCN_ERR_ACC_SEQ_MISMATCH (0x46U)
#define FLCN_ERR_SSP_STACK_CHECK_FAILED (0x47U)
#define FLCN_ERR_SE_TRNG_FAILED (0x48U)
#define FLCN_ERR_PROD_MODE_NOT_YET_SUPPORTED (0x49U)
// SHA HW errors
#define FLCN_ERR_SHA_HW_CHECK_INT_STATUS (0x4AU)
#define FLCN_ERR_SHA_HW_SOFTRESET_REQUIRED (0x4BU)
#define FLCN_ERR_SHA_HW_SOFTRESET_FAILED (0x4CU)
#define FLCN_ERR_SHA_HW_BUSY (0x4DU)
//
// Add new generic error codes here, do not changes values of exiting error codes,
// because that will affect other binaries and their signatures
//
#define FLCN_ERR_CTXSW_ERROR (0x4EU)
// VPR SEC2 task errors
#define FLCN_ERR_VPR_APP_INVALID_REQUEST_END_ADDR (0x51U)
#define FLCN_ERR_VPR_APP_INVALID_REQUEST_START_ADDR (0x52U)
#define FLCN_ERR_VPR_APP_SCRUB_VERIF_FAILED (0x53U)
#define FLCN_ERR_VPR_APP_MEMLOCK_ALREADY_SET (0x54U)
#define FLCN_ERR_VPR_APP_INVALID_INDEX (0x55U)
#define FLCN_ERR_VPR_APP_UNEXPECTED_VPR_HANDOFF_FROM_SCRUBBER (0x56U)
#define FLCN_ERR_VPR_APP_CBC_RANGE_CLASH (0x57U)
#define FLCN_ERR_VPR_APP_NOT_SUPPORTED_BY_HW (0x58U)
#define FLCN_ERR_VPR_APP_NOT_SUPPORTED_BY_SW (0x59U)
#define FLCN_ERR_VPR_APP_DISPLAY_VERSION_NOT_SUPPORTED (0x5AU)
#define FLCN_ERR_VPR_APP_VPR_WPR_WRITE_FAILED (0x5BU)
#define FLCN_ERR_VPR_APP_NOTHING_TO_DO (0x5CU)
#define FLCN_ERR_VPR_APP_DISPLAY_NOT_PRESENT (0x5DU)
#define FLCN_ERR_VPR_APP_PREVIOUS_CMD_FAILED_AS_MAX_VPR_IS_0 (0x5EU)
#define FLCN_ERR_VPR_APP_PLM_PROTECTION_NOT_RAISED (0x5FU)
#define FLCN_ERR_VPR_APP_PLM_PROTECTION_ALREADY_RAISED (0x60U)
#define FLCN_ERR_VPR_APP_DISP_FALCON_IS_NOT_IN_LS_MODE (0x61U)
#define FLCN_ERR_VPR_APP_VPR_IS_ALREADY_ENABLED (0x62U)
#define FLCN_ERR_VPR_APP_UNEXPECTEDLY_RUNNING_ON_RISCV (0x63U)
// Clocks Errors
#define FLCN_ERR_CYCLE_DETECTED (0x70U)
#define FLCN_ERR_INVALID_PATH (0x71U)
#define FLCN_ERR_MISMATCHED_TARGET (0x72U)
#define FLCN_ERR_FREQ_NOT_SUPPORTED (0x73U)
#define FLCN_ERR_INVALID_SOURCE (0x74U)
#define FLCN_ERR_NOT_INITIALIZED (0x75U)
// HDCP2.2 Errors
#define FLCN_ERR_HDCP22_GETDKEY_FAILED (0x80U)
#define FLCN_ERR_HDCP22_H_PRIME (0x81U)
#define FLCN_ERR_HDCP22_CERT_RX (0x82U)
#define FLCN_ERR_HDCP22_PAIRING (0x83U)
#define FLCN_ERR_HDCP22_L_PRIME (0x84U)
#define FLCN_ERR_HDCP22_V_PRIME (0x85U)
#define FLCN_ERR_HDCP22_INVALID_RXIDLIST (0x86U)
#define FLCN_ERR_HDCP22_M_PRIME (0x87U)
#define FLCN_ERR_HDCP22_SEQ_ROLLOVER (0x88U)
#define FLCN_ERR_HDCP22_RSA_HW (0x89U)
#define FLCN_ERR_HDCP22_ECF_TIMESLOT_MISMATCH (0x90U)
// LibCCC Errors
#define FLCN_ERR_INIT_CRYPTO_DEVICE_FAILED (0x91U)
#define FLCN_ERR_NVPKA_SELECT_ENGINE_FAILED (0x92U)
#define FLCN_ERR_NVPKA_ACQUIRE_MUTEX_FAILED (0x93U)
#define FLCN_ERR_NVPKA_MODULAR_EXP_LOCK_FAILED (0x94U)
#define FLCN_ERR_NVRNG_INIT_CRYPTO_DEVICE_FAILED (0x95U)
#define FLCN_ERR_NVRNG_SELECT_ENGINE_FAILED (0x96U)
#define FLCN_ERR_NVRNG_GENERATE_FAILED (0x97U)
// Heavy Secure Errors
#define FLCN_ERR_HS_CHK_INVALID_INPUT (0xA0U)
#define FLCN_ERR_HS_CHK_CHIP_NOT_SUPPORTED (0xA1U)
#define FLCN_ERR_HS_CHK_UCODE_REVOKED (0xA2U)
#define FLCN_ERR_HS_CHK_NOT_IN_LSMODE (0xA3U)
#define FLCN_ERR_HS_CHK_INVALID_LS_PRIV_LEVEL (0xA4U)
#define FLCN_ERR_HS_CHK_INVALID_REGIONCFG (0xA5U)
#define FLCN_ERR_HS_CHK_PRIV_SEC_DISABLED_ON_PROD (0xA6U)
#define FLCN_ERR_HS_CHK_SW_FUSING_ALLOWED_ON_PROD (0xA7U)
#define FLCN_ERR_HS_CHK_INTERNAL_SKU_ON_PROD (0xA8U)
#define FLCN_ERR_HS_CHK_DEVID_OVERRIDE_ENABLED_ON_PROD (0xA9U)
#define FLCN_ERR_HS_CHK_INCONSISTENT_PROD_MODES (0xAAU)
#define FLCN_ERR_HS_CHK_HUB_ENCRPTION_DISABLED (0xABU)
#define FLCN_ERR_HS_PR_ILLEGAL_LASSAHS_STATE_AT_HS_ENTRY (0xACU)
#define FLCN_ERR_HS_PR_ILLEGAL_LASSAHS_STATE_AT_MPK_DECRYPT (0xADU)
#define FLCN_ERR_HS_PR_ILLEGAL_LASSAHS_STATE_AT_HS_EXIT (0xAEU)
#define FLCN_ERR_HS_PROD_MODE_NOT_YET_SUPPORTED (0xAFU)
#define FLCN_ERR_HS_DEV_VERSION_ON_PROD (0xB0U)
#define FLCN_ERR_HS_PR_LASSAHS_LS_SIG_GRP_MISMATCH (0xB1U)
#define FLCN_ERR_HS_PR_LASSAHS_LS_SIG_GRP_OVERLAYS_CNT (0xB2U)
#define FLCN_ERR_HS_PR_LASSAHS_LS_SIG_GRP_INVALID_VA (0xB3U)
#define FLCN_ERR_HS_MUTEX_ACQUIRE_FAILED (0xB4U)
#define FLCN_ERR_HS_MUTEX_RELEASE_FAILED (0xB5U)
#define FLCN_ERR_HS_PR_MPK_DEC_NEEDS_NEWER_ACR_UDE_SCRUBBER (0xB6U)
#define FLCN_ERR_HS_CHK_ENGID_MISMATCH (0xB7U)
#define FLCN_ERR_HS_OPT_INTERNAL_SKU_CHECK_FAILED (0xB8U)
#define FLCN_ERR_HS_CHK_BOARD_MISMATCH (0xB9U)
#define FLCN_ERR_HS_CHK_DISP_ENG_DISABLED (0xBAU)
#define FLCN_ERR_HS_GEN_RANDOM (0xBBU)
#define FLCN_ERR_HS_CHK_IMPROPERLY_FUSED_BOARD (0xBCU)
#define FLCN_ERR_HS_CHK_HDCP_DISABLED (0xBDU)
#define FLCN_ERR_HS_CHK_HDCP_BLACKLISTED_SKU (0XBEU)
#define FLCN_ERR_HS_SECURE_ACTION_ARG_CHECK_FAILED (0xBFU)
#define FLCN_ERR_HS_CHK_RETURN_PC_AT_HS_ENTRY_IS_OF_HS (0xC0U)
#define FLCN_ERR_HS_CHK_HS_LIB_ENTRY_CALLED_BY_NON_HS (0xC1U)
#define FLCN_ERR_HS_DECODE_TRAP_ALREADY_IN_USE (0xC2U)
#define FLCN_ERR_HS_REGISTER_READ_WRITE_ERROR (0xC3U)
#define FLCN_ERR_HS_CHK_CPUCTL_ALIAS_FALSE (0xC4U)
#define FLCN_ERR_HS_UPDATE_RESET_PLM_ERROR (0xC5U)
#define FLCN_ERR_HS_RNG_CONFIG_ERROR (0xC6U)
#define FLCN_ERR_HS_CHK_NOT_IN_HSMODE (0xC7U)
#define FLCN_ERR_HS_CHK_GFW_CHAIN_OF_TRUST_BROKEN (0xC8U)
#define FLCN_ERR_HS_HDCP22_WRONG_SEQUENCE (0xC9U)
#define FLCN_ERR_HS_HDCP22_INTEGRITY_ERROR (0xCAU)
#define FLCN_ERR_HS_HDCP22_WRONG_TYPE (0xCBU)
#define FLCN_ERR_HS_APM_NOT_ENABLED (0xCCU)
#define FLCN_ERR_HS_APM_SMC_ENABLED (0xCDU)
#define FLCN_ERR_HS_APM_FECS_NOT_HALTED (0xCEU)
#define FLCN_ERR_HS_APM_SCRATCH_PLM_INVALID (0xCFU)
#define FLCN_ERR_HS_APM_SCRATCH_INIT_INVALID (0xD0U)
//
// BAR0/CSB Priv Read/Write Error Handling Defines
// These need to be defined by HW - NV Bug 200198584
//
#define FLCN_BAR0_PRIV_PRI_ERROR_MASK 0xFFF00000U
#define FLCN_BAR0_PRIV_PRI_ERROR_CODE 0xBAD00000U
#define FLCN_BAR0_PRIV_PRI_RETURN_VAL 0x00BADBADU
#define FLCN_CSB_PRIV_PRI_ERROR_MASK 0xFFFF0000U
#define FLCN_CSB_PRIV_PRI_ERROR_CODE 0xBADF0000U
//
// Macro to check FALCON return status
//
#define CHECK_FLCN_STATUS(expr) do { \
flcnStatus = (expr); \
if (flcnStatus != FLCN_OK) \
{ \
goto ErrorExit; \
} \
} while (NV_FALSE)
// Warnings.
#define FLCN_WARN_NOTHING_TO_DO (0xD0U)
#define FLCN_WARN_NOT_QUERIED (0xD1U)
// Queue handling Errors
#define FLCN_ERR_QUEUE_MGMT_INVALID_UNIT_ID (0xE0U)
#define FLCN_ERR_QUEUE_MGMT_HEAP_MIRROR_ERR (0xE1U)
#define FLCN_ERR_QUEUE_TASK_INVALID_EVENT_TYPE (0xE2U)
#define FLCN_ERR_QUEUE_TASK_INVALID_UNIT_ID (0xE3U)
#define FLCN_ERR_QUEUE_TASK_INVALID_CMD_TYPE (0xE4U)
// Posted write errors
#define FLCN_ERR_POSTED_WRITE_FAILURE (0xF0U)
#define FLCN_ERR_POSTED_WRITE_INTERRUPTS_ENABLED (0xF1U)
#define FLCN_ERR_POSTED_WRITE_PRI_CLUSTER_COUNT_MISMATCH (0xF2U)
#define FLCN_ERR_POSTED_WRITE_INCORRECT_PARAMS (0xF3U)
// Lane Margining errors
#define FLCN_ERR_LM_INVALID_RECEIVER_NUMBER (0xF5U)
#endif // FLCNRETVAL_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GSP_ERROR_H
#define GSP_ERROR_H
// Definitions for GSP-RM to report errors to CPU-RM via mailbox
#define NV_GSP_ERROR_CODE 7:0
#define NV_GSP_ERROR_REASON 15:8
#define NV_GSP_ERROR_TASK 23:16
#define NV_GSP_ERROR_SKIPPED 27:24
#define NV_GSP_ERROR_TAG 31:28
#define NV_GSP_ERROR_TAG_VAL 0xE
#endif // GSP_ERROR_H

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/*
* SPDX-FileCopyrightText: Copyright (c) <year> NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _IFR_DEM_H_
#define _IFR_DEM_H_
#define INFOROM_DEM_OBJECT_V1_00_PACKED_SIZE 4144
#define INFOROM_DEM_OBJECT_V1_00_FIFO_SIZE 4096
struct INFOROM_DEM_OBJECT_V1_00
{
INFOROM_OBJECT_HEADER_V1_00 header;
inforom_U032 seqNumber;
inforom_U016 writeOffset;
inforom_U016 readOffset;
inforom_X008 fifoBuffer[INFOROM_DEM_OBJECT_V1_00_FIFO_SIZE];
inforom_U032 reserved[8];
};
#define INFOROM_DEM_OBJECT_V1_00_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d2w4096x8d"
typedef struct INFOROM_DEM_OBJECT_V1_00 INFOROM_DEM_OBJECT_V1_00;
#endif // _IFR_DEM_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _IFRECC_H_
#define _IFRECC_H_
#include "nvtypes.h"
#include "inforom/types.h"
// NVSwitch ECC v6 object definition
#define INFOROM_ECC_OBJECT_V6_S0_PACKED_SIZE 3808
//Used to determine if the entry is empty or not
#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_VALID 0:0
#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_VALID_FALSE 0
#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_VALID_TRUE 1
#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_CORRUPT_TIMEDATA 1:1
#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_CORRUPT_TIMEDATA_FALSE 0
#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_CORRUPT_TIMEDATA_TRUE 1
#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_ADDR_VALID 2:2
#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_ADDR_VALID_FALSE 0
#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_HEADER_ADDR_VALID_TRUE 1
#define NV_INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_LOCATION_LINK_ID 7:0
typedef struct INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER
{
inforom_U008 header;
inforom_U032 errId;
inforom_U032 lastErrorTimestamp;
inforom_U032 averageEventDelta;
inforom_U016 location;
inforom_U016 sublocation;
inforom_U032 correctedCount;
inforom_U032 uncorrectedCount;
inforom_U032 address;
} INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER;
#define INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_MAX_COUNT 128
typedef struct INFOROM_ECC_OBJECT_V6_S0
{
INFOROM_OBJECT_HEADER_V1_00 header;
NvU64_ALIGN32 uncorrectedTotal;
NvU64_ALIGN32 correctedTotal;
inforom_U032 lastClearedTimestamp;
INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER errorEntries[INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_MAX_COUNT];
inforom_U008 padding[68];
} INFOROM_ECC_OBJECT_V6_S0;
#define INFOROM_ECC_OBJECT_V6_S0_HEADER_FMT INFOROM_OBJECT_HEADER_V1_00_FMT
#define INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_FMT "b3d2w3d"
#define INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_ARRAY_FMT \
INFOROM_FMT_REP128(INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_FMT)
#define INFOROM_ECC_OBJECT_V6_S0_PADDING_FMT "68b"
#define INFOROM_ECC_OBJECT_V6_S0_FMT INFOROM_ECC_OBJECT_V6_S0_HEADER_FMT "qqd" \
INFOROM_ECC_OBJECT_V6_S0_ERROR_COUNTER_ARRAY_FMT \
INFOROM_ECC_OBJECT_V6_S0_PADDING_FMT
// Error event structure for NVSwitch ECC errors
typedef struct
{
NvU32 sxid;
NvU32 linkId;
NvBool bAddressValid;
NvU32 address;
// The timestamp is filled in by the inforom ECC error logging API
NvU32 timestamp;
NvBool bUncErr;
NvU32 errorCount;
} INFOROM_NVS_ECC_ERROR_EVENT;
typedef union
{
INFOROM_OBJECT_HEADER_V1_00 header;
INFOROM_ECC_OBJECT_V6_S0 v6s;
} INFOROM_ECC_OBJECT;
typedef struct
{
const char *pFmt;
NvU8 *pPackedObject;
INFOROM_ECC_OBJECT *pEcc;
// Signals if there are pending updates to be flushed to InfoROM
NvBool bDirty;
} INFOROM_ECC_STATE, *PINFOROM_ECC_STATE;
#endif // _IFRECC_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _IFRSTRUCT_H_
#define _IFRSTRUCT_H_
#include "inforom/types.h"
#include "inforom/ifrecc.h"
#include "inforom/ifrdem.h"
#define INFOROM_OBD_OBJECT_V1_XX_PACKED_SIZE 128
struct INFOROM_OBD_OBJECT_V1_XX
{
INFOROM_OBJECT_HEADER_V1_00 header;
inforom_U032 buildDate;
inforom_U008 marketingName[24];
inforom_U008 serialNumber[16];
inforom_U008 memoryManufacturer;
inforom_U008 memoryPartID[20];
inforom_U008 memoryDateCode[6];
inforom_U008 productPartNumber[20];
inforom_U008 boardRevision[3];
inforom_U008 boardType;
inforom_U008 board699PartNumber[20];
inforom_U008 reserved[5];
};
#define INFOROM_OBD_OBJECT_V1_XX_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d116b"
typedef struct INFOROM_OBD_OBJECT_V1_XX INFOROM_OBD_OBJECT_V1_XX;
//
// OEM 1.0
//
#define INFOROM_OEM_OBJECT_V1_00_PACKED_SIZE 512
#define INFOROM_OEM_OBJECT_HEADER_VERSION 1
struct INFOROM_OEM_OBJECT_V1_00
{
INFOROM_OBJECT_HEADER_V1_00 header;
inforom_U008 oemInfo[504];
};
#define INFOROM_OEM_OBJECT_V1_00_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "504b"
typedef struct INFOROM_OEM_OBJECT_V1_00 INFOROM_OEM_OBJECT_V1_00;
#define INFOROM_IMG_OBJECT_V1_00_PACKED_SIZE 64
#define INFOROM_IMG_OBJECT_V1_00_VERSION_LENGTH 16
struct INFOROM_IMG_OBJECT_V1_00
{
INFOROM_OBJECT_HEADER_V1_00 header;
inforom_U008 version[INFOROM_IMG_OBJECT_V1_00_VERSION_LENGTH];
inforom_U016 pciDeviceId;
inforom_U016 pciVendorId;
inforom_U016 pciSubsystemId;
inforom_U016 pciSubsystemVendorId;
inforom_U008 reserved[32];
};
#define INFOROM_IMG_OBJECT_V1_00_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "16b4w32b"
typedef struct INFOROM_IMG_OBJECT_V1_00 INFOROM_IMG_OBJECT_V1_00;
#endif // _IFRSTRUCT_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _INFOROM_OMSDEF_H_
#define _INFOROM_OMSDEF_H_
#include "inforom/types.h"
#define INFOROM_OMS_OBJECT_V1_PACKED_SIZE 112
#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_ENTRY_AVAILABLE 0:0
#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_ENTRY_AVAILABLE_NO 0
#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_ENTRY_AVAILABLE_YES 1
#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE 1:1
#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE_NO 0
#define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE_YES 1
#define INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY_DATA_RESERVED 7:2
#define INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY_DATA_ENTRY_CHECKSUM 15:8
typedef struct INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY
{
inforom_U016 data;
} INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY;
#define INFOROM_OMS_OBJECT_V1S_NUM_SETTINGS_ENTRIES 50
typedef struct INFOROM_OMS_OBJECT_V1S
{
INFOROM_OBJECT_HEADER_V1_00 header;
inforom_U032 lifetimeRefreshCount;
INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY settings[
INFOROM_OMS_OBJECT_V1S_NUM_SETTINGS_ENTRIES];
} INFOROM_OMS_OBJECT_V1S;
#define INFOROM_OMS_OBJECT_V1S_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d50w"
typedef struct INFOROM_OMS_V1S_DATA
{
INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY *pIter;
INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY prev;
INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY *pNext;
} INFOROM_OMS_V1S_DATA;
typedef union
{
INFOROM_OBJECT_HEADER_V1_00 header;
INFOROM_OMS_OBJECT_V1S v1s;
} INFOROM_OMS_OBJECT;
typedef union
{
INFOROM_OMS_V1S_DATA v1s;
} INFOROM_OMS_DATA;
typedef struct
{
const char *pFmt;
NvU8 *pPackedObject;
INFOROM_OMS_OBJECT *pOms;
INFOROM_OMS_DATA omsData;
} INFOROM_OMS_STATE;
#endif /* _INFOROM_OMSDEF_H_ */

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _INFOROM_TYPES_H_
#define _INFOROM_TYPES_H_
/*!
* @file types.h
* @brief Common types and definitions used by InfoROM objects
*/
typedef NvS32 inforom_S008;
typedef NvU32 inforom_U004;
typedef NvU32 inforom_U008;
typedef NvU32 inforom_U016;
typedef NvU32 inforom_U024;
typedef NvU32 inforom_U032;
typedef NvU64 inforom_U064;
typedef NvU8 inforom_X008;
#define INFOROM_FMT_S08 's'
#define INFOROM_FMT_U04 'n'
#define INFOROM_FMT_U08 'b'
#define INFOROM_FMT_U16 'w'
#define INFOROM_FMT_U24 't'
#define INFOROM_FMT_U32 'd'
#define INFOROM_FMT_U64 'q'
#define INFOROM_FMT_BINARY 'x'
// Helper macros for generating repeating format sequences
#define INFOROM_FMT_REP02(fmt) fmt fmt
#define INFOROM_FMT_REP04(fmt) INFOROM_FMT_REP02(fmt) INFOROM_FMT_REP02(fmt)
#define INFOROM_FMT_REP08(fmt) INFOROM_FMT_REP04(fmt) INFOROM_FMT_REP04(fmt)
#define INFOROM_FMT_REP16(fmt) INFOROM_FMT_REP08(fmt) INFOROM_FMT_REP08(fmt)
#define INFOROM_FMT_REP32(fmt) INFOROM_FMT_REP16(fmt) INFOROM_FMT_REP16(fmt)
#define INFOROM_FMT_REP64(fmt) INFOROM_FMT_REP32(fmt) INFOROM_FMT_REP32(fmt)
#define INFOROM_FMT_REP128(fmt) INFOROM_FMT_REP64(fmt) INFOROM_FMT_REP64(fmt)
#define INFOROM_FMT_REP256(fmt) INFOROM_FMT_REP128(fmt) INFOROM_FMT_REP128(fmt)
#define INFOROM_FMT_REP512(fmt) INFOROM_FMT_REP256(fmt) INFOROM_FMT_REP256(fmt)
#define INFOROM_OBJECT_SUBVERSION_SUPPORTS_NVSWITCH(sv) \
((((sv) & 0xF0) == 0) || (((sv) & 0xF0) == 0x20))
#define INFOROM_OBJECT_HEADER_V1_00_SIZE_OFFSET 0x05
#define INFOROM_OBJECT_HEADER_V1_00_CHECKSUM_OFFSET 0x07
#define INFOROM_OBJECT_HEADER_V1_00_PACKED_SIZE 8
typedef struct INFOROM_OBJECT_HEADER_V1_00
{
inforom_S008 type[3];
inforom_U008 version;
inforom_U008 subversion;
inforom_U016 size;
inforom_U008 checksum;
} INFOROM_OBJECT_HEADER_V1_00;
#define INFOROM_OBJECT_HEADER_V1_00_FMT "3s2bwb"
#endif // _INFOROM_TYPES_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVCST_H
#define NVCST_H
#include <platform/chipset/chipset.h>
#include <platform/chipset/chipset_info.h>
#include <nvpcie.h>
#define CHIPSET_SETUP_FUNC(name) static NV_STATUS name(OBJCL *pCl);
CHIPSET_SETUP_FUNC(Intel_25XX_setupFunc)
CHIPSET_SETUP_FUNC(Intel_27XX_setupFunc)
CHIPSET_SETUP_FUNC(Intel_2A40_setupFunc)
CHIPSET_SETUP_FUNC(Intel_0040_setupFunc)
CHIPSET_SETUP_FUNC(Intel_2E00_setupFunc)
CHIPSET_SETUP_FUNC(Intel_25E0_setupFunc)
CHIPSET_SETUP_FUNC(Intel_29XX_setupFunc)
CHIPSET_SETUP_FUNC(Intel_29X0_setupFunc)
CHIPSET_SETUP_FUNC(Intel_29E0_setupFunc)
CHIPSET_SETUP_FUNC(Intel_359E_setupFunc)
CHIPSET_SETUP_FUNC(Intel_4000_setupFunc)
CHIPSET_SETUP_FUNC(Intel_4003_setupFunc)
CHIPSET_SETUP_FUNC(Intel_3400_setupFunc)
CHIPSET_SETUP_FUNC(Intel_3B42_setupFunc)
CHIPSET_SETUP_FUNC(Intel_1C46_setupFunc)
CHIPSET_SETUP_FUNC(Intel_1C10_setupFunc)
CHIPSET_SETUP_FUNC(Intel_1C4B_setupFunc)
CHIPSET_SETUP_FUNC(Intel_1C49_setupFunc)
CHIPSET_SETUP_FUNC(Intel_1D40_setupFunc)
CHIPSET_SETUP_FUNC(Intel_8D47_setupFunc)
CHIPSET_SETUP_FUNC(Intel_8D44_setupFunc)
CHIPSET_SETUP_FUNC(Intel_1E10_setupFunc)
CHIPSET_SETUP_FUNC(Intel_8C4B_setupFunc)
CHIPSET_SETUP_FUNC(Intel_8CC4_setupFunc)
CHIPSET_SETUP_FUNC(Intel_A145_setupFunc)
CHIPSET_SETUP_FUNC(Intel_A2C5_setupFunc)
CHIPSET_SETUP_FUNC(Intel_A242_setupFunc)
CHIPSET_SETUP_FUNC(Intel_A2D2_setupFunc)
CHIPSET_SETUP_FUNC(Intel_A2C9_setupFunc)
CHIPSET_SETUP_FUNC(Intel_A301_setupFunc)
CHIPSET_SETUP_FUNC(Intel_0685_setupFunc)
CHIPSET_SETUP_FUNC(Intel_4381_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc)
CHIPSET_SETUP_FUNC(SiS_656_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RS400_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RS480_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RD870_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RD890_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RX780_setupFunc)
CHIPSET_SETUP_FUNC(ATI_FX990_setupFunc)
CHIPSET_SETUP_FUNC(AMD_RS780_setupFunc)
CHIPSET_SETUP_FUNC(AMD_FX790_setupFunc)
CHIPSET_SETUP_FUNC(AMD_FX890_setupFunc)
CHIPSET_SETUP_FUNC(AMD_X370_setupFunc)
CHIPSET_SETUP_FUNC(VIA_VX900_setupFunc)
CHIPSET_SETUP_FUNC(APM_Storm_setupFunc)
CHIPSET_SETUP_FUNC(ARMV8_generic_setupFunc)
CHIPSET_SETUP_FUNC(Marvell_ThunderX2_setupFunc)
CHIPSET_SETUP_FUNC(QEMU_setupFunc)
CHIPSET_SETUP_FUNC(Ampere_eMag_setupFunc)
CHIPSET_SETUP_FUNC(Huawei_Kunpeng920_setupFunc)
CHIPSET_SETUP_FUNC(Mellanox_BlueField_setupFunc)
CHIPSET_SETUP_FUNC(Amazon_Gravitron2_setupFunc)
CHIPSET_SETUP_FUNC(Fujitsu_A64FX_setupFunc)
CHIPSET_SETUP_FUNC(Phytium_FT2000_setupFunc)
CHIPSET_SETUP_FUNC(Ampere_Altra_setupFunc)
CHIPSET_SETUP_FUNC(Arm_NeoverseN1_setupFunc)
CHIPSET_SETUP_FUNC(Nvidia_T210_setupFunc)
CHIPSET_SETUP_FUNC(Nvidia_T194_setupFunc)
// Keep string length <=32 (including termination) to avoid string copy overflow
CSINFO chipsetInfo[] =
{
// PCI Express chipset
{PCI_VENDOR_ID_INTEL, 0x2580, CS_INTEL_2580, "Grantsdale", Intel_25XX_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x2584, CS_INTEL_2584, "Alderwood", Intel_25XX_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x2588, CS_INTEL_2588, "Intel2588", Intel_25XX_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x2590, CS_INTEL_2590, "Alviso", Intel_25XX_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x25C0, CS_INTEL_25E0, "Greencreek", Intel_25E0_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x25E0, CS_INTEL_25E0, "Greencreek", Intel_25E0_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x29B0, CS_INTEL_29X0, "IntelQ35", Intel_29X0_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x29C0, CS_INTEL_29X0, "BearlakeB", Intel_29X0_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x29D0, CS_INTEL_29X0, "IntelQ33", Intel_29X0_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x29E0, CS_INTEL_29E0, "BearlakeX", Intel_29E0_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x359E, CS_INTEL_359E, "Tumwater", Intel_359E_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x4000, CS_INTEL_4000, "Stoakley", Intel_4000_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x4003, CS_INTEL_4003, "SkullTrail", Intel_4003_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x3400, CS_INTEL_3400, "IntelX58", Intel_3400_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x3403, CS_INTEL_3400, "IntelX58", Intel_3400_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x3405, CS_INTEL_3400, "IntelX58", Intel_3400_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x3406, CS_INTEL_3400, "Tylersburg", Intel_3400_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x2770, CS_INTEL_2770, "Lakeport", Intel_25XX_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x2774, CS_INTEL_2774, "Glenwood", Intel_27XX_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x277C, CS_INTEL_277C, "Glenwood", Intel_27XX_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x2A40, CS_INTEL_2A40, "Montevina", Intel_2A40_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x2E00, CS_INTEL_2E00, "Eaglelake", Intel_2E00_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x2E10, CS_INTEL_2E00, "Eaglelake", Intel_2E00_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x2E20, CS_INTEL_2E00, "Eaglelake", Intel_2E00_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x2E30, CS_INTEL_2E00, "Eaglelake", Intel_2E00_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x0044, CS_INTEL_0040, "Arrandale/Auburndale", Intel_0040_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x0062, CS_INTEL_0040, "Arrandale/Auburndale", Intel_0040_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xD130, CS_INTEL_3B42, "Clarksfield", Intel_3B42_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xD132, CS_INTEL_3B42, "Clarksfield", Intel_3B42_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x3B42, CS_INTEL_3B42, "P55/PM55/H57", Intel_3B42_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1C46, CS_INTEL_1C46, "IntelP67-CougarPoint", Intel_1C46_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1C4B, CS_INTEL_1C46, "HuronRiver-HM67", Intel_1C4B_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1C4F, CS_INTEL_1C46, "HuronRiver-QM67", Intel_1C4B_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1C49, CS_INTEL_1C49, "HuronRiver-HM65", Intel_1C49_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1C44, CS_INTEL_1C46, "IntelZ68", Intel_1C46_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1C10, CS_INTEL_1C10, "IntelP67", Intel_1C10_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1D40, CS_INTEL_1D40, "IntelX79", Intel_1D40_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1D41, CS_INTEL_1D40, "IntelX79", Intel_1D40_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1E10, CS_INTEL_1E10, "IntelZ75", Intel_1E10_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x0150, CS_INTEL_1E10, "IntelZ77A-GD55", Intel_1E10_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x0151, CS_INTEL_1E10, "IntelZ77A-GD55", Intel_1E10_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x0100, CS_INTEL_1E10, "IntelZ77A-GD55", Intel_1E10_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x8C4B, CS_INTEL_8C4B, "SharkBay-HM87", Intel_8C4B_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x8C44, CS_INTEL_8C4B, "SharkBay-Z87", Intel_8C4B_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x8C41, CS_INTEL_8C4B, "SharkBay-H8x/P8x", Intel_8C4B_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x8C49, CS_INTEL_8C4B, "SharkBay-HM86", Intel_8C4B_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x8C52, CS_INTEL_8C4B, "SharkBay-E3", Intel_8C4B_setupFunc}, // Does not support SLI
{PCI_VENDOR_ID_INTEL, 0x8CC4, CS_INTEL_8CC4, "IntelZ97", Intel_8CC4_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x8CC3, CS_INTEL_8CC4, "IntelHM97", Intel_8CC4_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA145, CS_INTEL_A145, "IntelZ170", Intel_A145_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA14E, CS_INTEL_A145, "IntelHM170", Intel_A145_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA150, CS_INTEL_A145, "IntelHM170", Intel_A145_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA149, CS_INTEL_A145, "SkyLake C236", Intel_A145_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA14A, CS_INTEL_A145, "SkyLake C232", Intel_A145_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA14D, CS_INTEL_A145, "SkyLake-H", Intel_A145_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA244, CS_INTEL_A145, "SkyLake C620", Intel_A145_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x8D47, CS_INTEL_8D47, "IntelX99", Intel_8D47_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x8D44, CS_INTEL_8D47, "IntelC612", Intel_8D44_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA2C5, CS_INTEL_A2C5, "IntelZ270", Intel_A2C5_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA154, CS_INTEL_A2C5, "IntelZ270", Intel_A2C5_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA152, CS_INTEL_A2C5, "IntelRX9S", Intel_A2C5_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA242, CS_INTEL_A242, "IntelC422", Intel_A242_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA241, CS_INTEL_A242, "IntelC422", Intel_A242_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA243, CS_INTEL_A242, "IntelC422", Intel_A242_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA2D2, CS_INTEL_A2D2, "IntelX299", Intel_A2D2_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA2D3, CS_INTEL_A242, "IntelC422", Intel_A242_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA1C1, CS_INTEL_A242, "IntelC621", Intel_A242_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA1C2, CS_INTEL_A242, "IntelC622", Intel_A242_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA1C3, CS_INTEL_A242, "IntelC624", Intel_A242_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA1C4, CS_INTEL_A242, "IntelC625", Intel_A242_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA1C5, CS_INTEL_A242, "IntelC626", Intel_A242_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA1C6, CS_INTEL_A242, "IntelC627", Intel_A242_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA1C7, CS_INTEL_A242, "IntelC628", Intel_A242_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA2C9, CS_INTEL_A2C9, "IntelZ370", Intel_A2C9_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA310, CS_INTEL_A2C9, "IntelZ370", Intel_A2C9_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA30E, CS_INTEL_A2C9, "IntelZ370", Intel_A2C9_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA305, CS_INTEL_A2C9, "IntelZ390", Intel_A2C9_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA30D, CS_INTEL_A2C9, "IntelH370", Intel_A2C9_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA301, CS_INTEL_A301, "Intel-CannonLake", Intel_A301_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x0685, CS_INTEL_0685, "Intel-CometLake", Intel_0685_setupFunc},
{PCI_VENDOR_ID_INTEL, 0xA1CB, CS_INTEL_C620, "Intel-IceLake", NULL},
{PCI_VENDOR_ID_INTEL, 0x4381, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x4385, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x0FAE, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x0FAF, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x10E5, CS_NVIDIA_T186, "T186", Nvidia_T210_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x10E6, CS_NVIDIA_T186, "T186", Nvidia_T210_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x1AD0, CS_NVIDIA_T194, "T194", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x1AD1, CS_NVIDIA_T194, "T194", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x1AD2, CS_NVIDIA_T194, "T194", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x229A, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x229C, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234, "T234", Nvidia_T194_setupFunc},
{PCI_VENDOR_ID_SIS, 0x0649, CS_SIS_649, "649", SiS_656_setupFunc},
{PCI_VENDOR_ID_SIS, 0x0656, CS_SIS_656, "656", SiS_656_setupFunc},
{PCI_VENDOR_ID_ATI, 0x5A31, CS_ATI_RS400, "RS400", ATI_RS400_setupFunc},
{PCI_VENDOR_ID_ATI, 0x5A33, CS_ATI_RS400, "RS400", ATI_RS400_setupFunc},
{PCI_VENDOR_ID_ATI, 0x5950, CS_ATI_RS480, "RS480", ATI_RS480_setupFunc},
{PCI_VENDOR_ID_ATI, 0x5951, CS_ATI_RS480, "RS480", ATI_RS480_setupFunc},
{PCI_VENDOR_ID_ATI, 0x5956, CS_ATI_FX790, "FX790" ,AMD_FX790_setupFunc},
{PCI_VENDOR_ID_ATI, 0x5A11, CS_ATI_FX890, "FX890" ,AMD_FX890_setupFunc},
{PCI_VENDOR_ID_ATI, 0x5a13, CS_ATI_RD850, "RD850" ,ATI_RD870_setupFunc},
{PCI_VENDOR_ID_ATI, 0x5a12, CS_ATI_RD870, "RD870" ,ATI_RD870_setupFunc},
{PCI_VENDOR_ID_ATI, 0x5a10, CS_ATI_RD890, "RD890" ,ATI_RD890_setupFunc},
{PCI_VENDOR_ID_ATI, 0x5957, CS_ATI_RX780, "RX780" ,ATI_RX780_setupFunc},
{PCI_VENDOR_ID_ATI, 0x5A14, CS_ATI_FX990, "FX990/X990/970",ATI_FX990_setupFunc},
{PCI_VENDOR_ID_AMD, 0x9601, CS_AMD_GX890, "GX890" ,AMD_FX890_setupFunc},
{PCI_VENDOR_ID_AMD, 0x9600, CS_AMD_RS780, "RS780" ,AMD_RS780_setupFunc},
{PCI_VENDOR_ID_AMD, 0x790e, CS_AMD_X370, "X370/X399/X470/ TRX40/X570/WRX80", AMD_X370_setupFunc },
{PCI_VENDOR_ID_VIA, 0x0308, CS_VIA_VT8369B, "VT8369B", NULL},
{PCI_VENDOR_ID_VIA, 0x0410, CS_VIA_VX900, "VX900", VIA_VX900_setupFunc},
{PCI_VENDOR_ID_APM, 0xe004, CS_APM_STORM, "X-Gene Storm", APM_Storm_setupFunc},
{PCI_VENDOR_ID_IBM, 0x03DC, CS_IBM_VENICE, "Venice", NULL},
{PCI_VENDOR_ID_MARVELL, 0xAF00, CS_MARVELL_THUNDERX2, "Marvell ThunderX2", Marvell_ThunderX2_setupFunc},
{PCI_VENDOR_ID_REDHAT, 0x0008, CS_REDHAT_QEMU, "QEMU Redhat", QEMU_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE005, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE006, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE007, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE008, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE009, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE00A, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE00B, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE00C, CS_AMPERE_EMAG, "AMPERE eMag", Ampere_eMag_setupFunc},
{PCI_VENDOR_ID_HUAWEI, 0xA120, CS_HUAWEI_KUNPENG920, "Huawei Kunpeng920", Huawei_Kunpeng920_setupFunc},
{PCI_VENDOR_ID_MELLANOX, 0xA2D0, CS_MELLANOX_BLUEFIELD, "Mellanox BlueField", Mellanox_BlueField_setupFunc},
{PCI_VENDOR_ID_MELLANOX, 0xA2D4, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2", NULL},
{PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2, "Mellanox BlueField 2 Crypto disabled", NULL},
{PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2, "Amazon Gravitron2", Amazon_Gravitron2_setupFunc},
{PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX, "Fujitsu A64FX", Fujitsu_A64FX_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_FT2000, "Phytium FT2000", Phytium_FT2000_setupFunc},
{PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500, "Phytium S2500", NULL},
{PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_S2500, "Phytium S2500", NULL},
{PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500, "Phytium S2500", NULL},
{PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_S2500, "Phytium S2500", NULL},
{PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_S2500, "Phytium S2500", NULL},
{PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_S2500, "Phytium S2500", NULL},
{PCI_VENDOR_ID_AMPERE, 0xE000, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE00D, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE00E, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE010, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE100, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc},
{PCI_VENDOR_ID_AMPERE, 0xE110, CS_AMPERE_ALTRA, "Ampere Altra", Ampere_Altra_setupFunc},
{PCI_VENDOR_ID_ARM, 0x0100, CS_ARM_NEOVERSEN1, "Arm Neoverse N1", Arm_NeoverseN1_setupFunc},
{PCI_VENDOR_ID_HYGON, 0x790E, CS_HYGON_C86, "Hygon-C86-7151", NULL},
{PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX, "Marvell Octeon CN96xx", ARMV8_generic_setupFunc},
{PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX, "Marvell Octeon CN98xx", ARMV8_generic_setupFunc},
///////////////////////////////////////////////////////////////////////////////////////////////////
// last element must have chipset CS_UNKNOWN (zero)
{0, 0, CS_UNKNOWN, "Unknown", NULL}
};
VENDORNAME vendorName[] =
{
{PCI_VENDOR_ID_NVIDIA, "NVIDIA"},
{PCI_VENDOR_ID_INTEL, "Intel"},
{PCI_VENDOR_ID_VIA, "VIA"},
{PCI_VENDOR_ID_RCC, "ServerWorks"},
{PCI_VENDOR_ID_MICRON_1, "Micron"},
{PCI_VENDOR_ID_MICRON_2, "Micron"},
{PCI_VENDOR_ID_APPLE, "Apple"},
{PCI_VENDOR_ID_SIS, "SiS"},
{PCI_VENDOR_ID_ATI, "ATI"},
{PCI_VENDOR_ID_TRANSMETA, "Transmeta"},
{PCI_VENDOR_ID_HP, "HP"},
{PCI_VENDOR_ID_AMD, "AMD"},
{PCI_VENDOR_ID_ALI, "ALi"},
{PCI_VENDOR_ID_APM, "AppliedMicro"},
{PCI_VENDOR_ID_IBM, "IBM"},
{PCI_VENDOR_ID_MARVELL, "MarvellThunderX2"},
{PCI_VENDOR_ID_REDHAT, "QemuRedhat"},
{PCI_VENDOR_ID_AMPERE, "AmpereComputing"},
{PCI_VENDOR_ID_HUAWEI, "Huawei"},
{PCI_VENDOR_ID_MELLANOX, "Mellanox"},
{PCI_VENDOR_ID_AMAZON, "Amazon"},
{PCI_VENDOR_ID_FUJITSU, "Fujitsu"},
{PCI_VENDOR_ID_CADENCE, "Cadence"},
{PCI_VENDOR_ID_ARM, "ARM"},
{0, "Unknown"} // Indicates end of the table
};
//
// Allowlist all chipsets with which dGPU over PCIe is supported on ARM
// (both v7 and v8) platforms
//
ARMCSALLOWLISTINFO armChipsetAllowListInfo[] =
{
{PCI_VENDOR_ID_NVIDIA, 0x0FAE, CS_NVIDIA_T210}, // NVIDIA Tegra X1 RP0
{PCI_VENDOR_ID_NVIDIA, 0x0FAF, CS_NVIDIA_T210}, // NVIDIA Tegra X1 RP1
{PCI_VENDOR_ID_NVIDIA, 0x10E5, CS_NVIDIA_T186}, // NVIDIA Tegra P1 RP0
{PCI_VENDOR_ID_NVIDIA, 0x10E6, CS_NVIDIA_T186}, // NVIDIA Tegra P1 RP1
{PCI_VENDOR_ID_NVIDIA, 0x1AD0, CS_NVIDIA_T194}, // NVIDIA Tegra V1 RP0
{PCI_VENDOR_ID_NVIDIA, 0x1AD1, CS_NVIDIA_T194}, // NVIDIA Tegra V1 RP1
{PCI_VENDOR_ID_NVIDIA, 0x1AD2, CS_NVIDIA_T194}, // NVIDIA Tegra V1 RP2
{PCI_VENDOR_ID_NVIDIA, 0x229A, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP0
{PCI_VENDOR_ID_NVIDIA, 0x229C, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP1
{PCI_VENDOR_ID_NVIDIA, 0x229E, CS_NVIDIA_T234}, // NVIDIA Tegra Orin RP2
{PCI_VENDOR_ID_APM, 0xe004, CS_APM_STORM}, // Applied Micro X-Gene "Storm"
{PCI_VENDOR_ID_MARVELL, 0xAF00, CS_MARVELL_THUNDERX2}, // Marvell ThunderX2
{PCI_VENDOR_ID_REDHAT, 0x0008, CS_REDHAT_QEMU}, // Redhat QEMU
{PCI_VENDOR_ID_AMPERE, 0xE005, CS_AMPERE_EMAG}, // Ampere eMag
{PCI_VENDOR_ID_AMPERE, 0xE006, CS_AMPERE_EMAG}, // Ampere eMag
{PCI_VENDOR_ID_AMPERE, 0xE007, CS_AMPERE_EMAG}, // Ampere eMag
{PCI_VENDOR_ID_AMPERE, 0xE008, CS_AMPERE_EMAG}, // Ampere eMag
{PCI_VENDOR_ID_AMPERE, 0xE009, CS_AMPERE_EMAG}, // Ampere eMag
{PCI_VENDOR_ID_AMPERE, 0xE00A, CS_AMPERE_EMAG}, // Ampere eMag
{PCI_VENDOR_ID_AMPERE, 0xE00B, CS_AMPERE_EMAG}, // Ampere eMag
{PCI_VENDOR_ID_AMPERE, 0xE00C, CS_AMPERE_EMAG}, // Ampere eMag
{PCI_VENDOR_ID_HUAWEI, 0xA120, CS_HUAWEI_KUNPENG920}, // Huawei Kunpeng 920
{PCI_VENDOR_ID_MELLANOX, 0xA2D0, CS_MELLANOX_BLUEFIELD}, // Mellanox BlueField
{PCI_VENDOR_ID_MELLANOX, 0xA2D4, CS_MELLANOX_BLUEFIELD2},// Mellanox BlueField 2
{PCI_VENDOR_ID_MELLANOX, 0xA2D5, CS_MELLANOX_BLUEFIELD2},// Mellanox BlueField 2 Crypto disabled
{PCI_VENDOR_ID_AMAZON, 0x0200, CS_AMAZON_GRAVITRON2}, // Amazon Gravitron2
{PCI_VENDOR_ID_FUJITSU, 0x1952, CS_FUJITSU_A64FX}, // Fujitsu A64FX
{PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_FT2000}, // Phytium FT2000
{PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_FT2000}, // Phytium FT2000
{PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_FT2000}, // Phytium FT2000
{PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_FT2000}, // Phytium FT2000
{PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_FT2000}, // Phytium FT2000
{PCI_VENDOR_ID_CADENCE, 0xFC16, CS_PHYTIUM_FT2000}, // Phytium FT2000
{PCI_VENDOR_ID_CADENCE, 0xDC01, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_CADENCE, 0xDC08, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_CADENCE, 0xFC01, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_CADENCE, 0xFC08, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_CADENCE, 0xDC16, CS_PHYTIUM_S2500}, // Phytium S2500
{PCI_VENDOR_ID_AMPERE, 0xE000, CS_AMPERE_ALTRA}, // Ampere Altra
{PCI_VENDOR_ID_AMPERE, 0xE00D, CS_AMPERE_ALTRA}, // Ampere Altra
{PCI_VENDOR_ID_AMPERE, 0xE00E, CS_AMPERE_ALTRA}, // Ampere Altra
{PCI_VENDOR_ID_AMPERE, 0xE010, CS_AMPERE_ALTRA}, // Ampere Altra
{PCI_VENDOR_ID_AMPERE, 0xE100, CS_AMPERE_ALTRA}, // Ampere Altra
{PCI_VENDOR_ID_AMPERE, 0xE110, CS_AMPERE_ALTRA}, // Ampere Altra
{PCI_VENDOR_ID_ARM, 0x0100, CS_ARM_NEOVERSEN1}, // Arm Neoverse N1
{PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX}, // Marvell OCTEON CN96xx
{PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX}, // Marvell OCTEON CN98xx
// last element must have chipset CS_UNKNOWN (zero)
{0, 0, CS_UNKNOWN}
};
#endif /* NVCST_H */

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src/nvidia/arch/nvalloc/common/inc/nvdevid.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 200-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVDEVID_H
#define NVDEVID_H
/**************** Resource Manager Defines and Structures ******************\
* *
* Private device ids defines - only defines ! *
* *
\***************************************************************************/
///////////////////////////////////////////////////////////////////////////////////////////
//
// VENDOR/SUBVENDOR IDS
// XXX Cleanup to do: change PCI_VENDOR_* to NV_PCI_SUBID_VENDOR_*
//
///////////////////////////////////////////////////////////////////////////////////////////
#define NV_PCI_SUBID_VENDOR 15:0 /* RW--F */
#define NV_PCI_SUBID_VENDOR_AMD 0x1022
#define NV_PCI_SUBID_VENDOR_ALI 0x10B9
#define NV_PCI_SUBID_VENDOR_NVIDIA 0x10DE
#define NV_PCI_SUBID_VENDOR_INTEL 0x8086
#define NV_PCI_SUBID_VENDOR_VIA 0x1106
#define NV_PCI_SUBID_VENDOR_RCC 0x1166
#define NV_PCI_SUBID_VENDOR_MICRON_1 0x1042
#define NV_PCI_SUBID_VENDOR_MICRON_2 0x1344
#define NV_PCI_SUBID_VENDOR_APPLE 0x106B
#define NV_PCI_SUBID_VENDOR_SIS 0x1039
#define NV_PCI_SUBID_VENDOR_ATI 0x1002
#define NV_PCI_SUBID_VENDOR_TRANSMETA 0x1279
#define NV_PCI_SUBID_VENDOR_HP 0x103C
#define NV_PCI_SUBID_VENDOR_DELL 0x1028
#define NV_PCI_SUBID_VENDOR_FUJITSU 0x10cf
#define NV_PCI_SUBID_VENDOR_ASUS 0x1043
#define NV_PCI_SUBID_VENDOR_MSI 0x1462
#define NV_PCI_SUBID_VENDOR_FOXCONN 0x105B
#define NV_PCI_SUBID_VENDOR_ECS 0x1019
#define NV_PCI_SUBID_VENDOR_DFI_1 0x106E
#define NV_PCI_SUBID_VENDOR_TOSHIBA 0x1179
#define NV_PCI_SUBID_VENDOR_DFI_2 0x15BD
#define NV_PCI_SUBID_VENDOR_ACER 0x1025
#define NV_PCI_SUBID_VENDOR_GIGABYTE 0x1458
#define NV_PCI_SUBID_VENDOR_EVGA 0x3842
#define NV_PCI_SUBID_VENDOR_BROADCOM 0x1166
#define NV_PCI_SUBID_VENDOR_SUPERMICRO 0x15D9
#define NV_PCI_SUBID_VENDOR_BIOSTAR 0x1565
#define NV_PCI_SUBID_VENDOR_XFX 0x1682
#define NV_PCI_SUBID_VENDOR_PCPARTNER 0x19DA
#define NV_PCI_SUBID_VENDOR_LENOVO 0x17AA
#define NV_PCI_SUBID_VENDOR_FSC 0x1734
#define NV_PCI_SUBID_VENDOR_FTS 0x1734
#define NV_PCI_SUBID_VENDOR_COLORFUL 0x7377
#define NV_PCI_SUBID_VENDOR_ASROCK 0x1849
#define NV_PCI_SUBID_VENDOR_SHUTTLE 0x1297
#define NV_PCI_SUBID_VENDOR_CLEVO 0x1558
#define NV_PCI_SUBID_VENDOR_PEGATRON 0x1B0A
#define NV_PCI_SUBID_VENDOR_JETWAY 0x16F3
#define NV_PCI_SUBID_VENDOR_HIGHGRADE 0x1C6C
#define NV_PCI_SUBID_VENDOR_GALAXY 0x1B4C
#define NV_PCI_SUBID_VENDOR_ZOTAC 0x19DA
#define NV_PCI_SUBID_VENDOR_ARIMA 0x161F
#define NV_PCI_SUBID_VENDOR_BFG 0x19F1
#define NV_PCI_SUBID_VENDOR_SONY 0x104D
#define NV_PCI_SUBID_VENDOR_BITLAND 0x1642
#define NV_PCI_SUBID_VENDOR_PC_PARTNER 0x174B
#define NV_PCI_SUBID_VENDOR_NZXT 0x1D96
// XXX CKEANUP TO REMOVE IN FAVOR OF NV_PCI_SUBID_VENDOR_*
#define PCI_VENDOR_ID_AMD 0x1022
#define PCI_VENDOR_ID_ALI 0x10B9
#define PCI_VENDOR_ID_NVIDIA 0x10DE
#define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_VENDOR_ID_VIA 0x1106
#define PCI_VENDOR_ID_RCC 0x1166
#define PCI_VENDOR_ID_MICRON_1 0x1042
#define PCI_VENDOR_ID_MICRON_2 0x1344
#define PCI_VENDOR_ID_APPLE 0x106B
#define PCI_VENDOR_ID_SIS 0x1039
#define PCI_VENDOR_ID_ATI 0x1002
#define PCI_VENDOR_ID_TRANSMETA 0x1279
#define PCI_VENDOR_ID_HP 0x103C
#define PCI_VENDOR_ID_DELL 0x1028
#define PCI_VENDOR_ID_FUJITSU 0x10cf
#define PCI_VENDOR_ID_ASUS 0x1043
#define PCI_VENDOR_ID_MSI 0x1462
#define PCI_VENDOR_ID_FOXCONN 0x105B
#define PCI_VENDOR_ID_ECS 0x1019
#define PCI_VENDOR_ID_DFI_1 0x106E
#define PCI_VENDOR_ID_TOSHIBA 0x1179
#define PCI_VENDOR_ID_DFI_2 0x15BD
#define PCI_VENDOR_ID_ACER 0x1025
#define PCI_VENDOR_ID_GIGABYTE 0x1458
#define PCI_VENDOR_ID_EVGA 0x3842
#define PCI_VENDOR_ID_BROADCOM 0x1166
#define PCI_VENDOR_ID_SUPERMICRO 0x15D9
#define PCI_VENDOR_ID_BIOSTAR 0x1565
#define PCI_VENDOR_ID_XFX 0x1682
#define PCI_VENDOR_ID_PCPARTNER 0x19DA
#define PCI_VENDOR_ID_LENOVO 0x17AA
#define PCI_VENDOR_ID_FSC 0x1734
#define PCI_VENDOR_ID_FTS 0x1734
#define PCI_VENDOR_ID_COLORFUL 0x7377
#define PCI_VENDOR_ID_ASROCK 0x1849
#define PCI_VENDOR_ID_SHUTTLE 0x1297
#define PCI_VENDOR_ID_CLEVO 0x1558
#define PCI_VENDOR_ID_PEGATRON 0x1B0A
#define PCI_VENDOR_ID_JETWAY 0x16F3
#define PCI_VENDOR_ID_HIGHGRADE 0x1C6C
#define PCI_VENDOR_ID_GALAXY 0x1B4C
#define PCI_VENDOR_ID_ZOTAC 0x19DA
#define PCI_VENDOR_ID_ARIMA 0x161F
#define PCI_VENDOR_ID_PC_PARTNER 0x174B
#define PCI_VENDOR_ID_APM 0x10E8
#define PCI_VENDOR_ID_IBM 0x1014
#define PCI_VENDOR_ID_NZXT 0x1D96
#define PCI_VENDOR_ID_MARVELL 0x177D
#define PCI_VENDOR_ID_REDHAT 0x1B36
#define PCI_VENDOR_ID_AMPERE 0x1DEF
#define PCI_VENDOR_ID_HUAWEI 0x19E5
#define PCI_VENDOR_ID_MELLANOX 0x15B3
#define PCI_VENDOR_ID_AMAZON 0x1D0F
#define PCI_VENDOR_ID_CADENCE 0x17CD
#define PCI_VENDOR_ID_ARM 0x13B5
#define PCI_VENDOR_ID_HYGON 0x1D94
#define NV_PCI_DEVID_DEVICE 31:16 /* RW--F */
#define NV_PCI_SUBID_DEVICE 31:16 /* RW--F */
///////////////////////////////////////////////////////////////////////////////////////////
//
// GPU DEVICE IDS
//
///////////////////////////////////////////////////////////////////////////////////////////
#define NV_PCI_DEVID_DEVICE_PG171_SKU200_PG179_SKU220 0x25B6 /* NVIDIA A16 / NVIDIA A2 */
///////////////////////////////////////////////////////////////////////////////////////////
//
// SUBDEVICE IDs
//
///////////////////////////////////////////////////////////////////////////////////////////
// A16
#define NV_PCI_SUBID_DEVICE_PG171_SKU200 0x14A9
///////////////////////////////////////////////////////////////////////////////////////////
//
// CHIPSET IDs
//
///////////////////////////////////////////////////////////////////////////////////////////
// Desktop flavor of X58
#define X58_DESKTOP_DEVIDS 0x3400, 0x3405
// Mobile version of X58
#define X58_MOBILE_DEVID 0x3405
#define X58_MOBILE_CLEVO_7200_SSDEVID 0x7200
// Sandy bridge CLEVO platform
#define SANDYBRIDGE_P180HM_SSDEVID 0x8000
#define SandyBridge_E_X79_P270WM_SSDEVID 0x270
#define IvyBridge_Z75_P370EM_SSDEVID 0x371
// Device ID's of Devices present on Patsburg's PCIE bus.
#define PATSBURG_PCIE_DEVICE_MIN_DEVID 0x1D10
#define PATSBURG_PCIE_DEVICE_MAX_DEVID 0x1D1F
#define PATSBURG_PCIE_DEVICE_DEVID 0x244E
//Tylersburg Congurations
#define TYLERSBURG_DEVID 0x3406
// Intel Grantsdale definitions
#define DEVICE_ID_INTEL_2580_HOST_BRIDGE 0x2580
#define DEVICE_ID_INTEL_2581_ROOT_PORT 0x2581
// Intel Alderwood definitions
#define DEVICE_ID_INTEL_2584_HOST_BRIDGE 0x2584
#define DEVICE_ID_INTEL_2585_ROOT_PORT 0x2585
// Intel Alviso definitions
#define DEVICE_ID_INTEL_2590_HOST_BRIDGE 0x2590
#define DEVICE_ID_INTEL_2591_ROOT_PORT 0x2591
// Intel Tumwater definitions
#define DEVICE_ID_INTEL_359E_HOST_BRIDGE 0x359E
#define DEVICE_ID_INTEL_3597_ROOT_PORT 0x3597
// Intel Stoakley definitions
#define INTEL_4000_SUBDEVICE_ID 0x021D
// Intel SkullTrail definitions
#define INTEL_4003_SUBDEVICE_ID 0x5358
// Intel Core I7 CPU
#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I7 0x2C01
// Intel Core I5 CPU Lynnfield
#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I5_L 0x2C81
#define INTEL_LYNNFIELD_ROOTPORT_CPU1 0xD138
#define INTEL_LYNNFIELD_ROOTPORT_CPU2 0xD13A
// Intel Core I5 CPU Auburndale
#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I5_A 0x2D41
// Intel Core I5 CPU 650
#define INTEL_QUICKPATH_SYSTEM_ADDRESS_DECODER_I5_6 0x2D01
// Intel Poulsbo definitions
#define DEVICE_ID_INTEL_8100_HOST_BRIDGE 0x8100
#define DEVICE_ID_INTEL_8110_ROOT_PORT 0x8110
#define DEVICE_ID_INTEL_8112_ROOT_PORT 0x8112
// Intel TunnelCreek definitions
#define DEVICE_ID_INTEL_8180_ROOT_PORT 0x8180
#define DEVICE_ID_INTEL_8181_ROOT_PORT 0x8181
#define DEVICE_ID_INTEL_8184_ROOT_PORT 0x8184
#define DEVICE_ID_INTEL_8185_ROOT_PORT 0x8185
// Intel I/O Hub definitions
#define DEVICE_ID_INTEL_3408_ROOT_PORT 0x3408
#define DEVICE_ID_INTEL_3411_ROOT_PORT 0x3411
#define DEVICE_ID_INTEL_3420_ROOT_PORT 0x3420
#define DEVICE_ID_INTEL_3421_ROOT_PORT 0x3421
// Intel SandyBridge IIO definitions
#define DEVICE_ID_INTEL_3C02_ROOT_PORT 0x3c02
#define DEVICE_ID_INTEL_3C03_ROOT_PORT 0x3c03
#define DEVICE_ID_INTEL_3C04_ROOT_PORT 0x3c04
#define DEVICE_ID_INTEL_3C05_ROOT_PORT 0x3c05
#define DEVICE_ID_INTEL_3C06_ROOT_PORT 0x3c06
#define DEVICE_ID_INTEL_3C07_ROOT_PORT 0x3c07
#define DEVICE_ID_INTEL_3C08_ROOT_PORT 0x3c08
#define DEVICE_ID_INTEL_3C09_ROOT_PORT 0x3c09
#define DEVICE_ID_INTEL_3C0A_ROOT_PORT 0x3c0a
#define DEVICE_ID_INTEL_3C0B_ROOT_PORT 0x3c0b
// Intel Haswell-E definitions
#define DEVICE_ID_INTEL_2F00_HOST_BRIDGE 0x2f00
#define DEVICE_ID_INTEL_2F01_ROOT_PORT 0x2f01
#define DEVICE_ID_INTEL_2F02_ROOT_PORT 0x2f02
#define DEVICE_ID_INTEL_2F03_ROOT_PORT 0x2f03
#define DEVICE_ID_INTEL_2F04_ROOT_PORT 0x2f04
#define DEVICE_ID_INTEL_2F05_ROOT_PORT 0x2f05
#define DEVICE_ID_INTEL_2F06_ROOT_PORT 0x2f06
#define DEVICE_ID_INTEL_2F07_ROOT_PORT 0x2f07
#define DEVICE_ID_INTEL_2F08_ROOT_PORT 0x2f08
#define DEVICE_ID_INTEL_2F09_ROOT_PORT 0x2f09
#define DEVICE_ID_INTEL_2F0A_ROOT_PORT 0x2f0a
#define DEVICE_ID_INTEL_2F0B_ROOT_PORT 0x2f0b
#define DEVICE_ID_INTEL_0C01_ROOT_PORT 0x0c01
// Intel IvyTown definitions
#define DEVICE_ID_INTEL_0E02_ROOT_PORT 0x0e02
#define DEVICE_ID_INTEL_0E03_ROOT_PORT 0x0e03
#define DEVICE_ID_INTEL_0E04_ROOT_PORT 0x0e04
#define DEVICE_ID_INTEL_0E05_ROOT_PORT 0x0e05
#define DEVICE_ID_INTEL_0E06_ROOT_PORT 0x0e06
#define DEVICE_ID_INTEL_0E07_ROOT_PORT 0x0e07
#define DEVICE_ID_INTEL_0E08_ROOT_PORT 0x0e08
#define DEVICE_ID_INTEL_0E09_ROOT_PORT 0x0e09
#define DEVICE_ID_INTEL_0E0A_ROOT_PORT 0x0e0a
#define DEVICE_ID_INTEL_0E0B_ROOT_PORT 0x0e0b
// Intel Ivy Bridge E definitions
#define DEVICE_ID_INTEL_0E00_HOST_BRIDGE 0x0E00
// Intel Haswell definitions
#define DEVICE_ID_INTEL_0C00_HASWELL_HOST_BRIDGE 0x0C00
#define DEVICE_ID_INTEL_0C04_HASWELL_HOST_BRIDGE 0x0C04
// Intel PCH definitions
#define DEVICE_ID_INTEL_9D10_PCH_BRIDGE 0x9d10
#define DEVICE_ID_INTEL_9D18_PCH_BRIDGE 0x9d18
#define DEVICE_ID_INTEL_A117_PCH_BRIDGE 0xa117
#define DEVICE_ID_INTEL_A118_PCH_BRIDGE 0xa118
#define DEVICE_ID_INTEL_9C98_PCH_BRIDGE 0x9c98
// Intel Broadwell definitions
#define DEVICE_ID_INTEL_6F00_HOST_BRIDGE 0x6f00
#define DEVICE_ID_INTEL_6F01_ROOT_PORT 0x6f01
#define DEVICE_ID_INTEL_6F02_ROOT_PORT 0x6f02
#define DEVICE_ID_INTEL_6F03_ROOT_PORT 0x6f03
#define DEVICE_ID_INTEL_6F04_ROOT_PORT 0x6f04
#define DEVICE_ID_INTEL_6F05_ROOT_PORT 0x6f05
#define DEVICE_ID_INTEL_6F06_ROOT_PORT 0x6f06
#define DEVICE_ID_INTEL_6F07_ROOT_PORT 0x6f07
#define DEVICE_ID_INTEL_6F08_ROOT_PORT 0x6f08
#define DEVICE_ID_INTEL_6F09_ROOT_PORT 0x6f09
#define DEVICE_ID_INTEL_6F0A_ROOT_PORT 0x6f0A
#define DEVICE_ID_INTEL_6F0B_ROOT_PORT 0x6f0B
#define DEVICE_ID_INTEL_1601_ROOT_PORT 0x1601
#define DEVICE_ID_INTEL_1605_ROOT_PORT 0x1605
#define DEVICE_ID_INTEL_1609_ROOT_PORT 0x1609
#define DEVICE_ID_INTEL_BROADWELL_U_HOST_BRIDGE 0x1604
#define DEVICE_ID_INTEL_BROADWELL_H_HOST_BRIDGE 0x1614
// Intel Skylake definitions
#define DEVICE_ID_INTEL_1901_ROOT_PORT 0x1901
#define DEVICE_ID_INTEL_1905_ROOT_PORT 0x1905
#define DEVICE_ID_INTEL_1909_ROOT_PORT 0x1909
#define DEVICE_ID_INTEL_SKYLAKE_U_HOST_BRIDGE 0x1904
#define DEVICE_ID_INTEL_SKYLAKE_S_HOST_BRIDGE 0x191F
#define DEVICE_ID_INTEL_SKYLAKE_H_HOST_BRIDGE 0x1910
// Intel Skylake-E definitions
#define DEVICE_ID_INTEL_2030_ROOT_PORT 0x2030
#define DEVICE_ID_INTEL_2033_ROOT_PORT 0x2033
// Intel Kabylake definitions
#define DEVICE_ID_INTEL_KABYLAKE_U_HOST_BRIDGE 0x5904
#define DEVICE_ID_INTEL_KABYLAKE_H_HOST_BRIDGE 0x5910
// AMD Matisse, Rome definitions
#define DEVICE_ID_AMD_1483_ROOT_PORT 0x1483
// AMD Castle Peak definition
#define DEVICE_ID_AMD_1480_ROOT_PORT 0x1480
// AMD Renoir-H definition
#define DEVICE_ID_AMD_1630_ROOT_PORT 0x1630
// Dell SkullTrail definitions
#define DELL_4003_SUBDEVICE_ID 0x021D
// Dell Quicksilver MLK definitions
#define DELL_0040_SUBDEVICE_ID 0x043a
// HP Tylersburg definitions
#define TYLERSBURG_Z800_SSDEVID 0x130B
// HP Romley definitions
#define ROMLEY_Z820_SSDEVID 0x158B
#define ROMLEY_Z620_SSDEVID 0x158A
#define ROMLEY_Z420_SSDEVID 0x1589
// HP Grantley definitions
#define GRANTLEY_Z840_SSDEVID 0x2129
#define GRANTLEY_Z640_SSDEVID 0x212A
#define GRANTLEY_Z440_SSDEVID 0x212B
// HP PURELY definitions
#define HP_QUADRO_Z4GEN4_DEVID 0xA2D2
#define PURLEY_Z8GEN4_SSDEVID 0x81C7
#define PURLEY_Z6GEN4_SSDEVID 0x81C6
#define PURLEY_Z4GEN4_SSDEVID 0x81C5
// Lenovo Romley definitions
#define ROMLEY_C30_SSDEVID 0x1028
#define ROMLEY_D30_SSDEVID 0x1027
#define ROMLEY_S30_SSDEVID 0x1026
// Dell Romley definitions
#define ROMLEY_T7600_SSDEVID 0x0495
#define ROMLEY_T5600_SSDEVID 0x0496
#define ROMLEY_T3600_SSDEVID 0x0497
// Dell Romley + IVB-EP CPU Refresh
#define IVYTOWN_T7610_SSDEVID 0x05D4
#define IVYTOWN_T5610_SSDEVID 0x05D3
// Dell Romley (Ipanema)
#define ROMLEY_R7610_SSDEVID 0x05A1
// FTS Romley definitions
#define ROMLEY_R920_SSDEVID 0x11B6
// Lenovo Grantley (Messi, Pele, Ronaldo)
#define GRANTLEY_V40_SSDEVID 0x1031
#define GRANTLEY_D40_SSDEVID 0x1030
#define GRANTLEY_S40_SSDEVID 0x102F
// Dell Grantley (Avalon)
#define GRANTLEY_T7810_SSDEVID 0x0618
#define GRANTLEY_T7910_SSDEVID 0x0619
// Lenovo Purley (Nile, Volga)
#define PURLEY_P920_SSDEVID 0x1038
#define PURLEY_P720_SSDEVID 0x1037
#define PURLEY_P520_SSDEVID 0x1036
// Lenovo P520c
#define LENOVO_P520C_SSDEVID 0x103C
// Dell Purley(Matira)
#define PURLEY_MATIRA3X_DEVID 0xA2D2
#define PURLEY_MATIRA3X_SSDEVID 0x08B1
#define PURLEY_MATIRA3_SSDEVID 0x0738
#define PURLEY_MATIRA5_SSDEVID 0x0739
#define PURLEY_MATIRA7_SSDEVID 0x073A
//FTS Grantley
#define GRANTLEY_R940_SSDEVID 0x1201
//FTS Purley
#define PURLEY_R970_SSDEVID 0x1230
#define PURLEY_M770_SSDEVID 0x1231
// HP Arrandale, Clarksfield, X58 workstation definitions
#define ARRANDALE_Z200SFF_SSDEVID 0x304A
#define CLARKSFIELD_Z200_SSDEVID 0x170B
#define X58_Z400_SSDEVID 0x1309
// GIGABYTE Sniper 3 (Z77)
#define GIGABYTE_SNIPER_3_SSDEVID_1 0x5000
#define GIGABYTE_SNIPER_3_SSDEVID_2 0x5001
// Supermicro Quadro VCA definitions
#define SUPERMICRO_QUADRO_VCA_DEVID 0x8D44
#define SUPERMICRO_QUADRO_VCA_SSDEVID 0x7270
// Supermicro SYS-4027GR-TRT
#define SUPERMICRO_SYS_4027GR_TRT_DEVID 0x1D41
#define SUPERMICRO_SYS_4027GR_TRT_SSDEVID 0x0732
// Supermicro SYS-4029GP-TRT2
#define SUPERMICRO_SYS_4029GP_TRT2_DEVID 0xA1C2
#define SUPERMICRO_SYS_4029GP_TRT2_SSDEVID 0x7270
// Asus Quadro BOXX definitions
#define ASUS_QUADRO_BOXX_DEVID 0x8D44
#define ASUS_QUADRO_BOXX_SSDEVID 0x85F6
// APEXX8 Quadro BOXX definitions
#define APEXX8_QUADRO_BOXX_DEVID 0xA2D3
#define APEXX8_QUADRO_BOXX_SSDEVID 0x098e
// APEXX5 Quadro BOXX definitions
#define APEXX5_QUADRO_BOXX_DEVID 0xA2D3
#define APEXX5_QUADRO_BOXX_SSDEVID 0x1000
// ASUS X99-E-10G
#define ASUS_X99_E_10G_SSDEVID 0x8600
// VIA definitions
#define DEVICE_ID_VIA_VT8369B_HOST_BRIDGE 0x0308
// Foxconn Einstein 64 [8086:a1c1][105b:7270]
#define FOXCONN_EINSTEIN_64_DEVID 0xA1C1
#define FOXCONN_EINSTEIN_64_SSDEVID 0x7270
// Tyan Workstation
#define TYAN_B7100_DEVID 0xA1C1
#define TYAN_B7100_SSDEVID 0x7270
// ESC 4000 Series Workstation
#define ESC_4000_G4_DEVID 0xA1C1
#define ESC_4000_G4_SSDEVID 0x871E
// NVIDIA C51
#define NVIDIA_C51_DEVICE_ID_MIN 0x2F0
#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_0 0x2F0
#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_1 0x2F1
#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_2 0x2F2
#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_3 0x2F3
#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_0 0x2F4
#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_1 0x2F5
#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_2 0x2F6
#define NVIDIA_C51_ULDT_CFG_0_DEVICE_ID_IGPU_DISABLE_3 0x2F7
#define NVIDIA_C51_DEVICE_ID_MAX 0x2F7
// NVIDIA MCP55
#define NVIDIA_MCP55_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0369
// NVIDIA MCP61
#define NVIDIA_MCP61_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x03EA
#define NVIDIA_MCP61_ULDT_CFG_0_DEVICE_ID_PA 0x03E2
// NVIDIA C55
#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_PRO 0x03A0
#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_PRO 0x03A0
#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_SLIX16 0x03A1
#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_SLI 0x03A3
#define NVIDIA_C55_CPU_PCI_0_DEVICE_ID_U 0x03A2
// NVIDIA MCP65
#define NVIDIA_MCP65_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0444
// NVIDIA MCP67/MCP68
#define NVIDIA_MCP67_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0547
// NVIDIA MCP73
#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_PV 0x07C0
#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_O 0x07C1
#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_S 0x07C2
#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_V 0x07C3
#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_RSVD_0 0x07C4
#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_RSVD_1 0x07C5
#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_RSVD_2 0x07C6
#define NVIDIA_MCP73_CPU_PCI_0_DEVICE_ID_D 0x07C7
// NVIDIA C73
#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_SLI2 0x0800
#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_SLI_ALL 0x0801
#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_SLIX8 0x0802
#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_U 0x0803
#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_0 0x0804
#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_1 0x0805
#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_2 0x0806
#define NVIDIA_C73_CPU_PCI_0_DEVICE_ID_RESERVED_3 0x0807
// NVIDIA MCP77/78
#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_DEFAULT 0x0754
#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_1 0x0755
#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_2 0x0756
#define NVIDIA_MCP77_ULDT_CFG_0_DEVICE_ID_3 0x0757
#define NVIDIA_MCP77_MCP_SM_CFG_0_DEVICE_ID_UNIT_SM 0x0752
// NVIDIA MCP79/7A
#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_DEFAULT 0x0A80
#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_SLIX16 0x0A81
#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_SLI 0x0A82
#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_U 0x0A83
#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_GM 0x0A84
#define NVIDIA_MCP79_CPU_PCI_0_DEVICE_ID_GVM 0x0A85
#define NVIDIA_MCP79_MCP_SM_CFG_0_DEVICE_ID_UNIT_SM 0x0AA2
// NVIDIA MCP89/P83
#define NVIDIA_MCP89_CPU_PCI_0_DEVICE_ID_DEFAULT 0x00000D60
///////////////////////////////////////////////////////////////////////////////////////////
//
// enumeration of chipset families
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// When adding a variable to the following enum, please
// add it also to the following chipset_names[].
//
enum {
CS_UNKNOWN = 0x0000,
CS_UNKNOWN_PCIE = 0x1000
, CS_INTEL_2580
, CS_INTEL_2584
, CS_INTEL_2588
, CS_INTEL_2590
, CS_INTEL_25E0
, CS_INTEL_29X0
, CS_INTEL_29E0
, CS_INTEL_359E
, CS_INTEL_4000
, CS_INTEL_4003
, CS_INTEL_3400
, CS_INTEL_3B42
, CS_INTEL_2770
, CS_INTEL_2774
, CS_INTEL_277C
, CS_INTEL_2A40
, CS_INTEL_2E00
, CS_INTEL_0040
, CS_INTEL_1C10
, CS_INTEL_1C46
, CS_INTEL_1C49
, CS_INTEL_1D40
, CS_INTEL_8D47
, CS_INTEL_1E10
, CS_INTEL_8C4B
, CS_INTEL_8CC4
, CS_INTEL_A145
, CS_INTEL_A2C5
, CS_INTEL_A242
, CS_INTEL_A2D2
, CS_INTEL_A2C9
, CS_INTEL_A301
, CS_INTEL_0685
, CS_INTEL_4381
, CS_INTEL_7A82
, CS_NVIDIA_CK804
, CS_NVIDIA_C19
, CS_NVIDIA_C51
, CS_NVIDIA_MCP55
, CS_NVIDIA_MCP61
, CS_NVIDIA_C55
, CS_NVIDIA_MCP65
, CS_NVIDIA_MCP67
, CS_NVIDIA_MCP73
, CS_NVIDIA_C73
, CS_NVIDIA_MCP77
, CS_NVIDIA_MCP79
, CS_NVIDIA_MCP89
, CS_NVIDIA_TEGRA3
, CS_SIS_649
, CS_SIS_656
, CS_ATI_RS400
, CS_ATI_RS400_A21
, CS_ATI_RS480
, CS_ATI_RS480_A21
, CS_AMD_RS780
, CS_VIA_VT8369B
, CS_ATI_FX790
, CS_ATI_RD850
, CS_ATI_RD870
, CS_ATI_RD890
, CS_ATI_FX890
, CS_ATI_RX780
, CS_ATI_FX990
, CS_AMD_GX890
, CS_AMD_X370
, CS_VIA_VX900
, CS_APM_STORM
, CS_IBM_VENICE
, CS_NVIDIA_T124
, CS_NVIDIA_T210
, CS_NVIDIA_T186
, CS_NVIDIA_T194
, CS_NVIDIA_T234
, CS_MARVELL_THUNDERX2
, CS_REDHAT_QEMU
, CS_AMPERE_EMAG
, CS_HUAWEI_KUNPENG920
, CS_MELLANOX_BLUEFIELD
, CS_AMAZON_GRAVITRON2
, CS_FUJITSU_A64FX
, CS_PHYTIUM_FT2000
, CS_AMPERE_ALTRA
, CS_ARM_NEOVERSEN1
, CS_MARVELL_OCTEON_CN96XX
, CS_MARVELL_OCTEON_CN98XX
, CS_INTEL_C620
, CS_HYGON_C86
, CS_PHYTIUM_S2500
, CS_MELLANOX_BLUEFIELD2
, CS_MAX_PCIE
};
enum {
RP_UNKNOWN = 0
, RP_BROADCOM_HT2100
, RP_INTEL_2581
, RP_INTEL_2585
, RP_INTEL_2589
, RP_INTEL_2591
, RP_INTEL_3597
, RP_INTEL_2775
, RP_INTEL_2771
, RP_INTEL_8110
, RP_INTEL_8112
, RP_INTEL_8180
, RP_INTEL_8181
, RP_INTEL_8184
, RP_INTEL_8185
, RP_INTEL_3C02
, RP_INTEL_3C03
, RP_INTEL_3C04
, RP_INTEL_3C05
, RP_INTEL_3C06
, RP_INTEL_3C07
, RP_INTEL_3C08
, RP_INTEL_3C09
, RP_INTEL_3C0A
, RP_INTEL_3C0B
, RP_INTEL_2F04
, RP_INTEL_2F08
, RP_INTEL_0C01
, RP_INTEL_1601
, RP_INTEL_1605
, RP_INTEL_1609
, RP_INTEL_1901
, RP_INTEL_1905
, RP_INTEL_1909
, RP_INTEL_5904
, RP_NVIDIA_CK804
, RP_NVIDIA_C19
, RP_NVIDIA_C51
, RP_NVIDIA_MCP55
, RP_NVIDIA_MCP61
, RP_NVIDIA_C55
, RP_NVIDIA_MCP65
};
#endif //NVDEVID_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVPCIE_H
#define NVPCIE_H
/**************** Resource Manager Defines and Structures ******************\
* *
* Private PCI Express related defines and structures. *
* *
\***************************************************************************/
#define PCI_VENDOR_ID 0x00
#ifndef PCI_DEVICE_ID
#define PCI_DEVICE_ID 0x02
#endif
#define PCI_BASE_ADDRESS_1 0x14 /* Aperture Base */
#define PCI_BASE_ADDRESS_2 0x18 /* Aperture Base */
#define PCI_CAPABILITY_LIST 0x34
#define PCI_DEVICE_SPECIFIC 0x40
#define NV_PCI_ID 0x0
#define NV_PCI_ID_VENDOR 15:0
#define NV_PCI_ID_VENDOR_NVIDIA 0x10DE
#define NV_PCI_ID_DEVICE 31:16
#define PCI_MAX_SLOTS 255
#define PCI_MAX_LANE_WIDTH 32
#define PCI_MAX_FUNCTION 8
#define PCI_INVALID_VENDORID 0xFFFF
#define PCI_INVALID_DEVICEID 0xFFFF
#define PCI_INVALID_SUBVENDORID 0xFFFF
#define PCI_INVALID_SUBDEVICEID 0xFFFF
#define PCI_CLASS_BRIDGE_DEV 0x06
#define PCI_SUBCLASS_BR_HOST 0x00
#define PCI_MULTIFUNCTION 0x80
// From PCI Local Bus Specification, Revision 3.0
#define CAP_ID_MASK 0xFF
#define CAP_ID_PMI 0x01
#define CAP_ID_AGP 0x02
#define CAP_ID_VPD 0x03
#define CAP_ID_SLOT_ID 0x04
#define CAP_ID_MSI 0x05
#define CAP_ID_HOT_SWAP 0x06
#define CAP_ID_PCI_X 0x07
#define CAP_ID_HYPER_TRANSPORT 0x08
#define CAP_ID_VENDOR_SPECIFIC 0x09
#define CAP_ID_DEBUG_PORT 0x0A
#define CAP_ID_CRC 0x0B
#define CAP_ID_HOT_PLUG 0x0C
#define CAP_ID_SUBSYSTEM_ID 0x0D
#define CAP_ID_AGP8X 0x0E
#define CAP_ID_SECURE 0x0F
#define CAP_ID_PCI_EXPRESS 0x10
#define CAP_ID_MSI_X 0x11
//
// Extended config space size is 4096 bytes.
//
#define PCI_EXTENDED_CONFIG_SPACE_LENGTH 4096
//
// From PCI Local Bus Specification, Revision 3.0
// HEADER TYPE0 Definitions - Byte offsets
//
#define PCI_HEADER_TYPE0_VENDOR_ID 0x00
#define PCI_HEADER_TYPE0_DEVICE_ID 0x02
#define PCI_HEADER_TYPE0_COMMAND 0x04
#define PCI_HEADER_TYPE0_STATUS 0x06
#define PCI_HEADER_TYPE0_REVISION_ID 0x08
#define PCI_HEADER_TYPE0_PROGIF 0x09
#define PCI_HEADER_TYPE0_SUBCLASS 0x0A
#define PCI_HEADER_TYPE0_BASECLASS 0x0B
#define PCI_HEADER_TYPE0_CACHE_LINE_SIZE 0x0C
#define PCI_HEADER_TYPE0_LATENCY_TIMER 0x0D
#define PCI_HEADER_TYPE0_HEADER_TYPE 0x0E
#define PCI_HEADER_TYPE0_BIST 0x0F
#define PCI_HEADER_TYPE0_BAR0 0x10
#define PCI_HEADER_TYPE0_BAR1 0x14
#define PCI_HEADER_TYPE0_BAR2 0x18
#define PCI_HEADER_TYPE0_BAR3 0x1C
#define PCI_HEADER_TYPE0_BAR4 0x20
#define PCI_HEADER_TYPE0_BAR5 0x24
#define PCI_HEADER_TYPE0_CBCIS_PTR 0x28
#define PCI_HEADER_TYPE0_SUBSYS_VEN_ID 0x2C
#define PCI_HEADER_TYPE0_SUBSYS_ID 0x2E
#define PCI_HEADER_TYPE0_ROMBAR 0x30
#define PCI_HEADER_TYPE0_CAP_PTR 0x34
#define PCI_HEADER_TYPE0_INT_LINE 0x3C
#define PCI_HEADER_TYPE0_INT_PIN 0x3D
#define PCI_HEADER_TYPE0_MIN_GNT 0x3E
#define PCI_HEADER_TYPE0_MAX_LAT 0x3F
//
// From PCI Express Base Specification Revision 2.0
// HEADER TYPE1 Definitions
#define PCI_HEADER_TYPE1_BRIDGE_CONTROL 0x3E
#define PCI_HEADER_TYPE1_BRIDGE_CONTROL_VGA_EN 0x08
#define PCIE_LINK_CAPABILITIES_2 0x000000A4 /* R--4R */
#define PCIE_LINK_CAPABILITIES_2_RSVD 0:0 /* C--VF */
#define PCIE_LINK_CAPABILITIES_2_RSVD_INIT 0x00000000 /* C---V */
#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED 7:1 /* R-EVF */
#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3_GEN4_GEN5 0x0000001F /* R---V */
#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_HIDDEN 0x00000000 /* R---V */
#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1 0x00000001 /* R---V */
#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2 0x00000003 /* R---V */
#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3 0x00000007 /* R-E-V */
#define PCIE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3_GEN4 0x0000000F /* R---V */
#define PCIE_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT 8:8 /* C--VF */
#define PCIE_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT_DISABLED 0x00000000 /* C---V */
#define PCIE_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP 23:23 /* R-EVF */
#define PCIE_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R-E-V */
#define PCIE_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP 24:24 /* R-EVF */
#define PCIE_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R-E-V */
#define PCIE_LINK_CAPABILITIES_2_RSVD1 31:25 /* C--VF */
#define PCIE_LINK_CAPABILITIES_2_RSVD1_INIT 0x00000000 /* C---V */
//
// PCI Express Virtual Peer-to-Peer Approval Definition
//
// These offsets are unused in hardware on existing chips and are reserved on
// future chips. Software has defined a virtual PCI capability that may be
// emulated by hypervisors at these offsets, and this capability is not tied
// to any specific hardware.
//
//
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0 0x000000C8
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_ID 7:0
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_NEXT 15:8
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_LENGTH 23:16
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_SIG_LO 31:24
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1 0x000000CC
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_SIG_HI 15:0
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_VERSION 18:16
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_PEER_CLIQUE_ID 22:19
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RSVD 31:23
#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250
// Chipset-specific definitions.
// Intel SantaRosa definitions
#define INTEL_2A00_CONFIG_SPACE_BASE 0x60
// Intel Montevina definitions
#define INTEL_2A40_CONFIG_SPACE_BASE 0x60
#define INTEL_2A40_ASLM_CAPABLE_REVID 0x05
// Intel EagleLake definitions
#define INTEL_2E00_CONFIG_SPACE_BASE 0x60
// Intel Bearlake definitions
#define INTEL_29XX_CONFIG_SPACE_BASE 0x60
// Intel BroadWater definitions
#define INTEL_29A0_CONFIG_SPACE_BASE 0x60
// Intel Grantsdale definitions
#define INTEL_25XX_CONFIG_SPACE_BASE 0x48
// Intel Tumwater definitions
#define INTEL_359E_CONFIG_SPACE_BASE 0xCC
// Intel Greencreek definitions
#define INTEL_25E0_CONFIG_SPACE_BASE_ADDRESS 0xE0000000
// Intel Stoakley definitions
#define INTEL_4000_CONFIG_SPACE_BASE_ADDRESS 0xE0000000
// Intel SkullTrail definitions
#define INTEL_4003_CONFIG_SPACE_BASE_ADDRESS_F 0xF0000000
#define INTEL_4003_CONFIG_SPACE_BASE_ADDRESS_E 0xE0000000
#define INTEL_4003_CONFIG_SPACE_BASE_ADDRESS INTEL_4003_CONFIG_SPACE_BASE_ADDRESS_F
#define INTEL_4003_CONFIG_SPACE_BASE 0x64
// SiS 656
#define SIS_656_CONFIG_SPACE_BASE 0xE0
#define SIS_656_CONFIG_SPACE_BASE_ADDRESS 3:0 // mapped to 31:28
// PCI/PCIE definitions
#define PCI_MAX_CAPS 20 // max caps to parse
#define PCI_MAX_DEVICES 32 // max devices on bus
#define PCI_MAX_FUNCTIONS 8 // max functions for a device
#define PCI_CAP_HEADER_ID 7:0 // PCI cap header id
#define PCI_CAP_HEADER_NEXT 15:8 // PCI cap header next
#define PCI_COMMON_CLASS_SUBCLASS 0x0a // PCI class/subclass (word)
#define PCI_COMMON_CLASS_SUBBASECLASS_HOST 0x0600 // Host bridge (connect PCI to CPU) [00] + Bridge Device [06]
#define PCI_COMMON_CLASS_SUBBASECLASS_P2P 0x0604 // PCI-to-PCI bridge (connects PCI buses) [04] + Bridge Device [06]
#define PCI_COMMON_CLASS_SUBBASECLASS_VGA 0x0300
#define PCI_COMMON_CLASS_SUBBASECLASS_3DCTRL 0x0302
#define PCI_COMMON_CAP_PTR 0x34 // PCI common cap ptr (byte)
#define PCI_TYPE_1_SECONDARY_BUS_NUMBER 0x19 // PCI type 1 sec bus (byte)
#define PCI_TYPE_1_SUBORDINATE_BUS_NUMBER 0x1a // PCI type 1 sub bus (byte)
#define PCIE_CAP_HEADER_ID 15:0 // PCIE cap header id
#define PCIE_CAP_HEADER_ID_INVALID 0xffff
#define PCIE_CAP_HEADER_NEXT 31:20 // PCIE cap header next
#define PCIE_BUS_SHIFT 20 // PCIE cfg space bus shift
#define PCIE_DEVICE_SHIFT 15 // PCIE cfg space dev shift
#define PCIE_FUNC_SHIFT 12 // PCIE cfg space func shift
#define PCIE_CAP_VERSION 19:16 // PCIE cap version
#define PCIE_CAP_VERSION_2P0 2 // PCIE 2.0 version
#define PCIE_LINK_CNTRL_STATUS_2_OFFSET 0x30 // PCIE Link Control/Status 2 offset
#define PCIE_LINK_STATUS_2 31:16 // PCIE Link Status 2 Register
#define PCIE_LINK_STATUS_2_DE_EMPHASIS 0:0 // PCIE De-Emphasis Level
#define PCI_COMMON_SUBSYSTEM_VENDOR_ID 0x2c // PCI subsystem Vendor Id
#define PCI_COMMON_SUBSYSTEM_ID 0x2e // PCI subsystem Id
// PCI Express Capability ID in the enhanced configuration space
#define PCIE_CAP_ID_ERROR 0x1 // PCIE Advanced Error Reporting
#define PCIE_CAP_ID_VC 0x2 // PCIE Virtual Channel (VC)
#define PCIE_CAP_ID_SERIAL 0x3 // PCIE Device Serial Number
#define PCIE_CAP_ID_POWER 0x4 // PCIE Power Budgeting
#define PCIE_CAP_ID_L1_PM_SUBSTATES 0x1E // PCIE L1 PM Substates
// Intel CPU family.
#define INTEL_CPU_FAMILY_06 0x06
#define INTEL_CPU_FAMILY_15 0x0f
#define INTEL_CPU_FAMILY_16 0x10
#define INTEL_CPU_FAMILY_21 0x15
// Intel CPU Model. Calculated as Model += (extModel << 4).
#define INTEL_CPU_MODEL_2A 0x2a
#define INTEL_CPU_MODEL_2D 0x2d
#define INTEL_CPU_MODEL_3A 0x3a
#define INTEL_CPU_MODEL_3F 0x3f
// Symbolic defines for each possible virtual channel
enum
{
RM_PCIE_VIRTUAL_CHANNEL_0 = 0,
RM_PCIE_VIRTUAL_CHANNEL_1,
RM_PCIE_VIRTUAL_CHANNEL_2,
RM_PCIE_VIRTUAL_CHANNEL_3,
RM_PCIE_VIRTUAL_CHANNEL_4,
RM_PCIE_VIRTUAL_CHANNEL_5,
RM_PCIE_VIRTUAL_CHANNEL_6,
RM_PCIE_VIRTUAL_CHANNEL_7,
RM_PCIE_VIRTUAL_CHANNEL_INVALID
};
struct OBJCL;
// root port setup functions
NV_STATUS Broadcom_HT2100_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Intel_RP25XX_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Intel_RP81XX_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Intel_RP3C0X_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Intel_RP2F0X_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Intel_RP0C0X_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Intel_Broadwell_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Intel_Skylake_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Intel_Skylake_U_Pch_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Intel_Skylake_H_Pch_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Intel_Kabylake_Y_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Nvidia_RPC19_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Nvidia_RPC51_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS Nvidia_RPC55_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS AMD_RP1480_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS AMD_RP1630_setupFunc(OBJGPU *, OBJCL*);
NV_STATUS AMD_RP1483_setupFunc(OBJGPU *, OBJCL*);
// Determines if the GPU is in a multi-GPU board based on devid checks
NvBool gpuIsMultiGpuBoard(OBJGPU *, NvBool *, NvBool *);
#endif // NVPCIE_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* @file nvrangetypes.h
* @brief Range types and operator macros
* @note #include a header to define NvUxx and NvSxx before sourcing this file.
*/
#ifndef _NVRANGETYPES_H_
#define _NVRANGETYPES_H_
//
// Define range types by convention
//
#define __NV_DEFINE_RANGE_TYPE(T) \
typedef struct NvRange ## T \
{ \
Nv ## T min; \
Nv ## T max; \
} NvRange ## T;
__NV_DEFINE_RANGE_TYPE(U64) // NvRangeU64
__NV_DEFINE_RANGE_TYPE(S64) // NvRangeS64
__NV_DEFINE_RANGE_TYPE(U32) // NvRangeU32
__NV_DEFINE_RANGE_TYPE(S32) // NvRangeS32
__NV_DEFINE_RANGE_TYPE(U16) // NvRangeU16
__NV_DEFINE_RANGE_TYPE(S16) // NvRangeS16
__NV_DEFINE_RANGE_TYPE(U8) // NvRangeU8
__NV_DEFINE_RANGE_TYPE(S8) // NvRangeS8
//
// Operator macros
//
// Macros are named xxx_RANGE (rather than xxx_RANGEU32, etc.) since they work
// properly on ranges with any number of bits, signed or unsigned.
//
#define NV_EQUAL_RANGE(r1, r2) ((r1).min == (r2).min && (r1).max == (r2).max)
#define NV_EMPTY_INCLUSIVE_RANGE(r) ((r).min > (r).max)
#define NV_EMPTY_EXCLUSIVE_RANGE(r) ((r).min + 1 > (r).max - 1)
#define NV_WITHIN_INCLUSIVE_RANGE(r, x) ((r).min <= (x) && (x) <= (r).max)
#define NV_WITHIN_EXCLUSIVE_RANGE(r, x) ((r).min < (x) && (x) < (r).max)
#define NV_IS_SUBSET_RANGE(r1, r2) ((r1).min >= (r2).min && (r2).max >= (r1).max)
#define NV_IS_SUPERSET_RANGE(r1, r2) ((r1).min <= (r2).min && (r2).max <= (r1).max)
#define NV_CENTER_OF_RANGE(r) ((r).min / 2 + ((r).max + 1) / 2) // Avoid overflow and rounding anomalies.
#define NV_IS_OVERLAPPING_RANGE(r1, r2) \
(NV_WITHIN_INCLUSIVE_RANGE((r1), (r2).min) || \
NV_WITHIN_INCLUSIVE_RANGE((r1), (r2).max))
#define NV_DISTANCE_FROM_RANGE(r, x) ((x) < (r).min? (r).min - (x): ((x) > (r).max? (x) - (r).max: 0))
#define NV_VALUE_WITHIN_INCLUSIVE_RANGE(r, x) ((x) < (r).min? (r).min : ((x) > (r).max? (r).max : (x)))
#define NV_VALUE_WITHIN_EXCLUSIVE_RANGE(r, x) ((x) <= (r).min? (r).min + 1 : ((x) >= (r).max? (r).max - 1 : (x)))
#define NV_INIT_RANGE(r, x, y) \
do \
{ \
(r).min = (x); \
(r).max = (y); \
} while(0)
#define NV_ASSIGN_DELTA_RANGE(r, x, d) \
do \
{ \
(r).min = (x) - (d); \
(r).max = (x) + (d); \
} while(0)
#define NV_ASSIGN_INTERSECTION_RANGE(r1, r2) \
do \
{ \
if ((r1).min < (r2).min) \
(r1).min = (r2).min; \
if ((r1).max > (r2).max) \
(r1).max = (r2).max; \
} while(0)
#define NV_ASSIGN_UNION_RANGE(r1, r2) \
do \
{ \
if ((r1).min > (r2).min) \
(r1).min = (r2).min; \
if ((r1).max < (r2).max) \
(r1).max = (r2).max; \
} while(0)
#define NV_MULTIPLY_RANGE(r, x) \
do \
{ \
(r).min *= (x); \
(r).max *= (x); \
} while(0)
#define NV_DIVIDE_FLOOR_RANGE(r, x) \
do \
{ \
(r).min /= (x); \
(r).max /= (x); \
} while(0)
#define NV_DIVIDE_CEILING_RANGE(r, x) \
do \
{ \
(r).min = ((r).min + (x) - 1) / (x); \
(r).max = ((r).max + (x) - 1) / (x); \
} while(0)
#define NV_DIVIDE_ROUND_RANGE(r, x) \
do \
{ \
(r).min = ((r).min + (x) / 2) / (x); \
(r).max = ((r).max + (x) / 2) / (x); \
} while(0)
#define NV_DIVIDE_WIDE_RANGE(r, x) \
do \
{ \
(r).min /= (x); \
(r).max = ((r).max + (x) - 1) / (x); \
} while(0)
#define NV_DIVIDE_NARROW_RANGE(r, x) \
do \
{ \
(r).min = ((r).min + (x) - 1) / (x); \
(r).max /= (x); \
} while(0)
#define NV_VALUE_WITHIN_INCLUSIVE_RANGE(r, x) \
((x) < (r).min? (r).min : ((x) > (r).max? (r).max : (x)))
#define NV_WITHIN_INCLUSIVE_RANGE(r, x) \
((r).min <= (x) && (x) <= (r).max)
#define NV_DISTANCE_FROM_RANGE(r, x) \
((x) < (r).min? (r).min - (x): ((x) > (r).max? (x) - (r).max: 0))
#endif // _NVRANGETYPES_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _SMBPBI_IMPL_H
#define _SMBPBI_IMPL_H
/*!
* This header file stores implementation dependent parameters of the SMBPBI server.
*/
/*!
* Maximum number of individual requests in a bundle
*/
#define NV_MSGBOX_PARAM_MAX_BUNDLE_SIZE 4
/*!
* Maximum number of Result Disposition Rules
*/
#define NV_MSGBOX_PARAM_MAX_DISP_RULES 10
/*!
* Maximum length of the Driver Event Message text string is 80, including
* the terminating NUL character.
*/
#define NV_MSGBOX_MAX_DRIVER_EVENT_MSG_TXT_SIZE 80
#endif // _SMBPBI_IMPL_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _SMBPBI_PRIV_H_
#define _SMBPBI_PRIV_H_
/*!
* This file contains NVIDIA private defines for the SMBPBI
* interface.
*/
#include "oob/smbpbi.h"
// MSGBOX command word structure
//
// Reserving opcodes above 0xC0 for internal/private functionationality.
//
// These opcodes should not be included in any documentation we release outside
// of NVIDIA!
//
//
// Only for internal use (should not be written to the command register). Used
// for internal tracking when commands are redirected to the RM from the PMU.
//
#define NV_MSGBOX_CMD_ERR_MORE_PROCESSING_REQUIRED 0x000000F0
//
// Alternative encodings of the command word
// These are distinguished by a non-zero value in the 29:29 bit,
// previously known as _RSVD.
//
#define NV_MSGBOX_CMD_ENCODING 29:29
#define NV_MSGBOX_CMD_ENCODING_STANDARD 0x00000000
#define NV_MSGBOX_CMD_ENCODING_DEBUG 0x00000001
// Debug command structure
#define NV_MSGBOX_DEBUG_CMD_OPCODE 1:0
#define NV_MSGBOX_DEBUG_CMD_OPCODE_READ_PRIV 0x00000000
#define NV_MSGBOX_DEBUG_CMD_ARG 23:2
/* Utility command constructor macros */
#define NV_MSGBOX_DEBUG_CMD(opcode, arg) \
( \
DRF_DEF(_MSGBOX, _DEBUG_CMD, _OPCODE, opcode) | \
DRF_NUM(_MSGBOX, _DEBUG_CMD, _ARG, (arg)) | \
DRF_DEF(_MSGBOX, _CMD, _STATUS, _NULL) | \
DRF_DEF(_MSGBOX, _CMD, _ENCODING, _DEBUG) | \
DRF_DEF(_MSGBOX, _CMD, _INTR, _PENDING) \
)
#define NV_MSGBOX_DEBUG_CMD_READ_PRIV(offset) \
NV_MSGBOX_DEBUG_CMD(_READ_PRIV, (offset) >> 2)
#endif // _SMBPBI_PRIV_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* << DO NOT EDIT >>
*
* This file describes the format of generated ucode binary. Please do not change the
* content unless the same change is applied to the target ucode builds.
*/
#ifndef RM_RISCV_UCODE_H
#define RM_RISCV_UCODE_H
#include "nvtypes.h"
typedef struct {
//
// Version 1
// Version 2
// Vesrion 3 = for Partition boot
// Vesrion 4 = for eb riscv boot
//
NvU32 version; // structure version
NvU32 bootloaderOffset;
NvU32 bootloaderSize;
NvU32 bootloaderParamOffset;
NvU32 bootloaderParamSize;
NvU32 riscvElfOffset;
NvU32 riscvElfSize;
NvU32 appVersion; // Changelist number associated with the image
//
// Manifest contains information about Monitor and it is
// input to BR
//
NvU32 manifestOffset;
NvU32 manifestSize;
//
// Monitor Data offset within RISCV image and size
//
NvU32 monitorDataOffset;
NvU32 monitorDataSize;
//
// Monitor Code offset withtin RISCV image and size
//
NvU32 monitorCodeOffset;
NvU32 monitorCodeSize;
NvU32 bIsMonitorEnabled;
//
// Swbrom Code offset within RISCV image and size
//
NvU32 swbromCodeOffset;
NvU32 swbromCodeSize;
//
// Swbrom Data offset within RISCV image and size
//
NvU32 swbromDataOffset;
NvU32 swbromDataSize;
} RM_RISCV_UCODE_DESC;
#endif // RM_RISCV_UCODE_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* Data structures and interfaces used for generic falcon boot-loader.
*
* This generic boot-loader is designed to load both non-secure and
* secure code taking care of signature as well. This bootloader
* should be loaded at the end of the IMEM so that it doesnt overwrite
* itself when it tries to load the code into IMEM starting at blk 0.
* The data will be loaded into DMEM offset 0.
*/
#ifndef RMFLCNBL_H
#define RMFLCNBL_H
#include "flcnifcmn.h"
/*!
* @brief Structure used by the boot-loader to load the rest of the code.
*
* This has to be filled by the GPU driver and copied into DMEM at offset
* provided in the @ref _def_rm_flcn_bl_desc.blDmemDescLoadOff.
*/
typedef struct _def_rm_flcn_bl_dmem_desc
{
/*!
* reserved should be always first element
*/
NvU32 reserved[4];
/*!
* signature should follow reserved 16B signature for secure code.
* 0s if no secure code
*/
NvU32 signature[4];
/*!
* ctxDma is used by the bootloader while loading code/data.
*/
NvU32 ctxDma;
/*!
* 256B aligned physical FB address where code is located.
*/
RM_FLCN_U64 codeDmaBase;
/*!
* Offset from codeDmaBase where the nonSecure code is located.
* The offset must be multiple of 256 to help performance.
*/
NvU32 nonSecureCodeOff;
/*!
* The size of the nonSecure code part.
*/
NvU32 nonSecureCodeSize;
/*!
* Offset from codeDmaBase where the secure code is located.
* The offset must be multiple of 256 to help performance.
*/
NvU32 secureCodeOff;
/*!
* The size of the ecure code part.
*/
NvU32 secureCodeSize;
/*!
* Code entry point which will be invoked by BL after code is loaded.
*/
NvU32 codeEntryPoint;
/*!
* 256B aligned Physical FB Address where data is located.
*/
RM_FLCN_U64 dataDmaBase;
/*!
* Size of data block. Should be multiple of 256B.
*/
NvU32 dataSize;
/*!
* Arguments to be passed to the target firmware being loaded.
*/
NvU32 argc;
/*!
* Number of arguments to be passed to the target firmware being loaded.
*/
NvU32 argv;
} RM_FLCN_BL_DMEM_DESC, *PRM_FLCN_BL_DMEM_DESC;
/*!
* @brief The header used by the GPU driver to figure out code and data
* sections of bootloader.
*/
typedef struct _def_rm_flcn_bl_img_header
{
/*!
* Offset of code section in the image.
*/
NvU32 blCodeOffset;
/*!
* Size of code section in the image.
*/
NvU32 blCodeSize;
/*!
* Offset of data section in the image.
*/
NvU32 blDataOffset;
/*!
* Size of data section in the image.
*/
NvU32 blDataSize;
} RM_FLCN_BL_IMG_HEADER, *PRM_FLCN_BL_IMG_HEADER;
/*!
* @brief The descriptor used by RM to figure out the requirements of boot loader.
*/
typedef struct _def_rm_flcn_bl_desc
{
/*!
* Starting tag of bootloader
*/
NvU32 blStartTag;
/*!
* Dmem offset where _def_rm_flcn_bl_dmem_desc to be loaded
*/
NvU32 blDmemDescLoadOff;
/*!
* Description of the image
*/
RM_FLCN_BL_IMG_HEADER blImgHeader;
} RM_FLCN_BL_DESC, *PRM_FLCN_BL_DESC;
#endif // RMFLCNBL_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* Top-level header-file that defines the GSP sequencer structures
*/
#ifndef _RMGSPSEQ_H_
#define _RMGSPSEQ_H_
/*!
* GSP sequencer structures and defines
*
* Here are the supported opcodes.
* the sequencer buffer is a stream of commands composed of
* an op-code directly followed by the exact number of arguments it needs.
*
* The supported op-codes are:
* GSP_SEQUENCER_BUFFER_OPCODE_REG_WRITE:
* arg[0]: the register offset
* arg[1]: the register value
*
* GSP_SEQUENCER_BUFFER_OPCODE_REG_MODIFY:
* arg[0]: the register offset
* arg[1]: the mask where to apply the modification
* arg[2]: the value to apply. The value needs to be shifted to fit inside the mask,
*
* GSP_SEQUENCER_BUFFER_OPCODE_REG_POLL:
* arg[0]: the register offset
* arg[1]: the mask where to apply the modification
* arg[2]: the value to apply. The value needs to be shifted to fit inside the mask.
* arg[3]: the timeout in MS
* arg[4]: an unique error code from GSP_SEQUENCER_BUFFER_ERR. Helps map to the failing GSP code.
*
* GSP_SEQUENCER_BUFFER_OPCODE_DELAY_US
* arg[0]: the delay in micoseconds.
*
* GSP_SEQUENCER_REG_STORE
* This operation stores the specified register at the specified index in
* the sequencer buffer register storage area.
* arg[0]: the reg offset to store in the save area
* arg[1]: index in save area to store value of reg offset
*
* GSP_SEQUENCER_CORE_RESET
* This operation resets the core. This operation takes no arguments.
*
* GSP_SEQUENCER_CORE_START
* This operation starts the core. This operation takes no arguments.
*
* GSP_SEQUENCER_CORE_WAIT_FOR_HALT
* This operation waits for the core to halt after completing execution.
* This operation takes no arguments.
*
* GSP_SEQUENCER_CORE_RESUME
* This operation resumes the core in preparation for switching back to
* the GSP-RM.
*/
typedef enum GSP_SEQ_BUF_OPCODE
{
GSP_SEQ_BUF_OPCODE_REG_WRITE = 0,
GSP_SEQ_BUF_OPCODE_REG_MODIFY,
GSP_SEQ_BUF_OPCODE_REG_POLL,
GSP_SEQ_BUF_OPCODE_DELAY_US,
GSP_SEQ_BUF_OPCODE_REG_STORE,
GSP_SEQ_BUF_OPCODE_CORE_RESET,
GSP_SEQ_BUF_OPCODE_CORE_START,
GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT,
GSP_SEQ_BUF_OPCODE_CORE_RESUME,
} GSP_SEQ_BUF_OPCODE;
#define GSP_SEQUENCER_PAYLOAD_SIZE_DWORDS(opcode) \
((opcode == GSP_SEQ_BUF_OPCODE_REG_WRITE) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_WRITE) / sizeof(NvU32)) : \
(opcode == GSP_SEQ_BUF_OPCODE_REG_MODIFY) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_MODIFY) / sizeof(NvU32)) : \
(opcode == GSP_SEQ_BUF_OPCODE_REG_POLL) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_POLL) / sizeof(NvU32)) : \
(opcode == GSP_SEQ_BUF_OPCODE_DELAY_US) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_DELAY_US) / sizeof(NvU32)) : \
(opcode == GSP_SEQ_BUF_OPCODE_REG_STORE) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_STORE) / sizeof(NvU32)) : \
/* GSP_SEQ_BUF_OPCODE_CORE_RESET */ \
/* GSP_SEQ_BUF_OPCODE_CORE_START */ \
/* GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT */ \
/* GSP_SEQ_BUF_OPCODE_CORE_RESUME */ \
0)
// The size of the structure must be DWord aligned!
typedef struct
{
NvU32 addr;
NvU32 val;
} GSP_SEQ_BUF_PAYLOAD_REG_WRITE;
// The size of the structure must be DWord aligned!
typedef struct
{
NvU32 addr;
NvU32 mask;
NvU32 val;
} GSP_SEQ_BUF_PAYLOAD_REG_MODIFY;
// The size of the structure must be DWord aligned!
typedef struct
{
NvU32 addr;
NvU32 mask;
NvU32 val;
NvU32 timeout;
NvU32 error;
} GSP_SEQ_BUF_PAYLOAD_REG_POLL;
// The size of the structure must be DWord aligned!
typedef struct
{
NvU32 val;
} GSP_SEQ_BUF_PAYLOAD_DELAY_US;
// The size of the structure must be DWord aligned!
typedef struct
{
NvU32 addr;
NvU32 index;
} GSP_SEQ_BUF_PAYLOAD_REG_STORE;
typedef struct GSP_SEQUENCER_BUFFER_CMD
{
GSP_SEQ_BUF_OPCODE opCode;
union
{
GSP_SEQ_BUF_PAYLOAD_REG_WRITE regWrite;
GSP_SEQ_BUF_PAYLOAD_REG_MODIFY regModify;
GSP_SEQ_BUF_PAYLOAD_REG_POLL regPoll;
GSP_SEQ_BUF_PAYLOAD_DELAY_US delayUs;
GSP_SEQ_BUF_PAYLOAD_REG_STORE regStore;
} payload;
} GSP_SEQUENCER_BUFFER_CMD;
//
// These error codes printed by the client help us
// see to which GSP uCode line it corresponds.
//
typedef enum GSP_SEQUENCER_BUFFER_ERR
{
GSP_SEQUENCER_BUFFER_ERR_OK = 0,
GSP_SEQUENCER_BUFFER_ERR_TIMEOUT1,
GSP_SEQUENCER_BUFFER_ERR_TIMEOUT2,
GSP_SEQUENCER_BUFFER_ERR_TIMEOUT3
} GSP_SEQUENCER_BUFFER_ERR;
// Sequencer implementation of FLD_WR_DRF_DEF()
#define GSP_SEQ_FLD_WR_DRF_DEF(gpu, gsp, d, r, f, c) \
{ \
GSP_SEQUENCER_BUFFER_CMD cmd; \
cmd.opCode = GSP_SEQ_BUF_OPCODE_REG_MODIFY; \
cmd.payload.regModify.addr = NV##d##r; \
cmd.payload.regModify.mask = DRF_MASK(NV##d##r##f) << DRF_SHIFT(NV##d##r##f); \
cmd.payload.regModify.val = DRF_DEF(d, r, f, c); \
(void)gspAppendToSequencerBuffer(gpu, gsp, &cmd); \
}
/*!
* Forward references
*/
struct rpc_run_cpu_sequencer_v17_00;
/*!
* Structure tracking all information relevant to GSP sequencer bufferfor GSP-RM
*/
typedef struct
{
/*! Pointer to RM-GSP CPU sequencer parameter block */
struct rpc_run_cpu_sequencer_v17_00 *pRunCpuSeqParam;
} GSP_SEQUENCER_BUFFER;
/*!
* RM-GSP sequencer buffer register macros.
* GSP_SEQ_BUF_REG_SAVE_SIZE : specifies size of save area in reg values
* GSP_SEQ_BUF_REG_SAVE_MAILBOX0 : index for saving of mailbox0 reg
* GSP_SEQ_BUF_REG_SAVE_MAILBOX1 : index for saving of mailbox1 reg
*/
#define GSP_SEQ_BUF_REG_SAVE_SIZE (8)
#define GSP_SEQ_BUF_REG_SAVE_MAILBOX0 (0)
#define GSP_SEQ_BUF_REG_SAVE_MAILBOX1 (1)
#endif // _RMGSPSEQ_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2012 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _RMIFRIF_H_
#define _RMIFRIF_H_
/*!
* @file rmifrif.h
* @brief Defines structures and interfaces common between RM and
* Init-From-Rom (IFR).
*
* For systems supporting GC6 that have on-board VBIOS ROMs, IFR is used
* to expedite several parts of GC6 exit in parallel with PEX init.
*
* After running devinit using a PMU ucode image loaded from the ROM itself,
* parts of RM stateLoad can be done using RM's ucode image. This is
* achieved by loading RM PMU ucode directly from FB. The primary difficulties
* are how to find RM's PMU ucode and how to bootstrap it.
*
* We use the simple approach of allocating a fixed buffer near the
* top of FB that contains the information required to bootstrap RM's PMU
* image. This buffer is called the RM_IFR_GC6_CTX.
*
* The buffer is allocated within RM's reserved memory space, directly before
* the VBIOS workspace (if any is present). Since the VBIOS workspace is
* always a multiple of 64K, RM enforces that the offset between top of memory
* and the end of the buffer is 64K. This way the IFR code can start
* from the top of memory and search downwards in 64K decrements.
*
* A small header is placed at the end of the buffer which contains a
* string signature identifying the buffer and other data needed to find the
* remaining context data.
*
* Top_Of-FB /---------------------\ <-
* | | \
* | (VBIOS_Workspace) | | END_OFFSET
* | | /
* |---------------------| <-
| | \
* | GSP FW (if present) | | pFbHalPvtInfo->gspFwSizeBytes
* | | /
* |---------------------| <-
* | RM_IFR_GC6_CTX_HDR | \
* |---------------------| |
* | (Padding) | | RM_IFR_GC6_CTX_HDR.bufferSize
* |---------------------| |
* | Sequence Data | /
* |---------------------| <-
* | |
* | |
* | |
* | |
* 0x00000000 \---------------------/
*
* To simplify the RM PMU bootstrap process and decrease IFR maintainence
* cost, the bootstrap process is encoded as a sequence script, leveraging
* a small subset of RM's PMU_SEQ_INST interface (see pmuseqinst.h).
* Register writes are captured during the initial (CPU-driven) RM PMU bootstrap
* and saved into a sequence for replay during GC6 exit.
*
* Only the following opcodes are supported currently:
* NV_PMU_SEQ_WRITE_REG_OPC - (multi-)register write
* NV_PMU_SEQ_EXIT_OPC - sequence done
*
*/
/*!
* Header structure which identifies the GC6 context buffer.
*/
typedef struct
{
NvU8 signature[12]; // RM_IFR_GC6_CTX_SIGNATURE
NvU32 bufferSize; // Size of the entire context buffer in bytes
NvU32 seqSizeWords; // Number of 32-bit words of sequence data
NvU32 checksum; // 32-bit chunk checksum of the sequence data
} RM_IFR_GC6_CTX_HDR, *PRM_IFR_GC6_CTX_HDR;
/*!
* String signature that IFR searches for to find the GC6 context buffer.
*/
#define RM_IFR_GC6_CTX_SIGNATURE "GC6_CTX_HDR" // 12 bytes
/*!
* Alignment of the offset between top of memory and the end of the
* GC6 context buffer (which is also the end of the header).
*/
#define RM_IFR_GC6_CTX_END_OFFSET_ALIGNMENT 0x10000 // 64KB
/*!
* Maximum offset between top of memory and the end of the
* GC6 context buffer. This is meant to be a loose upper bound preventing
* scanning of the whole of memory (e.g. when something goes wrong).
*/
#define RM_IFR_GC6_CTX_END_OFFSET_MAX 0x1000000 // 16MB
#define RM_IFR_GC6_CTX_END_OFFSET_MAX_WITH_GSP 0x10000000 // 256MB
/*!
* Maximum size of the context data in bytes.
* This is limited by FECS falcon DMEM size (4K on Kepler).
* The buffer must fit within DMEM together with stack and other global data.
*/
#define RM_IFR_GC6_CTX_DATA_MAX_SIZE 2048 // 2KB
#endif // _RMIFRIF_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef RMLSFM_H
#define RMLSFM_H
/*****************************************************************************/
/* This file is shared between ACR, SEC2 Binaries */
/* Do not update this file without updating ACR/SEC2 */
/*****************************************************************************/
/*!
* @file rmlsfm.h
* @brief Top-level header-file that defines Light Secure Falcon Managment
SW shared interfaces.
*/
/*!
* READ/WRITE masks for WPR region
*/
#define LSF_WPR_REGION_RMASK (0xCU) // Readable only from level 2 and 3 client
#define LSF_WPR_REGION_WMASK (0xCU) // Writable only from level 2 and 3 client
#define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED (0x8) // Readable only from level 3 client
#define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED (0x8) // Writable only from level 3 client
#define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO (0x0) // Disallow read mis-match for all clients
#define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0) // Disallow write mis-match for all clients
/*!
* READ mask for WPR region on Tegra
* This is required until we update tegra binaries, Bug 200281517
* TODO: dgoyal - Remove this once tegra binaries are updated
*/
#define LSF_WPR_REGION_RMASK_FOR_TEGRA (0xFU)
/*!
* Expected REGION ID to be used for the unprotected FB region (region that
* does not have read or write protections)
*/
#define LSF_UNPROTECTED_REGION_ID (0x0U)
/*!
* Expected REGION ID to be used for the WPR region for the falcon microcode (includes data).
* ACR allots client requests to each region based on read/write masks and it is supposed
* to provide first priority to requests from LSFM. Providing first priority will naturally assign
* region ID 1 to LSFM and this define will provide a way for different parties to sanity check
* this fact. Also there are other falcons (FECS/video falcons) which depends on this define, so please
* be aware while modifying this.
*/
#define LSF_WPR_EXPECTED_REGION_ID (0x1U)
/*!
* Expected REGION ID to be used for the unused WPR region.
*/
#define LSF_WPR_UNUSED_REGION_ID (0x2U)
/*!
* Invalid LS falcon subWpr ID
*/
#define LSF_SUB_WPR_ID_INVALID (0xFFFFFFFFU)
/*!
* Expected REGION ID to be used for the VPR region.
*/
#define LSF_VPR_REGION_ID (0x3U)
/*!
* Size of the separate bootloader data that could be present in WPR region.
*/
#define LSF_LS_BLDATA_EXPECTED_SIZE (0x100U)
/*!
* since we dont check signatures in GC6 exit, we need to hardcode the WPR offset
*/
#define LSF_WPR_EXPECTED_OFFSET (0x0U)
/*!
* CTXDMA to be used while loading code/data in target falcons
*/
#define LSF_BOOTSTRAP_CTX_DMA_FECS (0x0)
/*!
* Context DMA ID 6 is reserved for Video UCODE
*/
#define LSF_BOOTSTRAP_CTX_DMA_VIDEO (0x6)
#define LSF_BOOTSTRAP_CTX_DMA_BOOTSTRAP_OWNER (0x0)
#define LSF_BOOTSTRAP_CTX_DMA_FBFLCN (0x0)
/*!
* Falcon Id Defines
* Defines a common Light Secure Falcon identifier.
* Codesigning infra. assumes LSF_FALCON_ID_ prefix for units,
* Changes to the define needs to be reflected in path [1]
* For new Falcon Id adding, we need to append to the end;
* don't insert the new falcon Id in the middle.
*/
#define LSF_FALCON_ID_PMU (0U)
#define LSF_FALCON_ID_DPU (1U)
#define LSF_FALCON_ID_GSPLITE LSF_FALCON_ID_DPU
#define LSF_FALCON_ID_FECS (2U)
#define LSF_FALCON_ID_GPCCS (3U)
#define LSF_FALCON_ID_NVDEC (4U)
#define LSF_FALCON_ID_NVENC (5U)
#define LSF_FALCON_ID_NVENC0 (5U)
#define LSF_FALCON_ID_NVENC1 (6U)
#define LSF_FALCON_ID_SEC2 (7U)
#define LSF_FALCON_ID_NVENC2 (8U)
#define LSF_FALCON_ID_MINION (9U)
#define LSF_FALCON_ID_FBFALCON (10U)
#define LSF_FALCON_ID_XUSB (11U)
#define LSF_FALCON_ID_GSP_RISCV (12U)
#define LSF_FALCON_ID_PMU_RISCV (13U)
#define LSF_FALCON_ID_SOE (14U)
#define LSF_FALCON_ID_NVDEC1 (15U)
#define LSF_FALCON_ID_OFA (16U)
#define LSF_FALCON_ID_SEC2_RISCV (17U)
#define LSF_FALCON_ID_NVDEC_RISCV (18U)
#define LSF_FALCON_ID_NVDEC_RISCV_EB (19U)
#define LSF_FALCON_ID_NVJPG (20U)
#define LSF_FALCON_ID_END (21U)
#define LSF_FALCON_ID_INVALID (0xFFFFFFFFU)
//
// ************************ NOTIFICATION *********************************
// In case anyone needs to add new LSF falconId, please must calculate
// WPR header size per LSF_FALCON_ID_END. RM needs to call lsfmGetWprHeaderSizeMax_HAL
// to align with acrReadSubWprHeader_HAL in ACR. Otherwise, ACR can't get correct
// address to read sub wpr headers.
// We observer in case LSF_FALCON_ID_END > 32 will cause SEC2 IMEM tag missing error;
// but don't get the root cause yet.
//
#define LSF_FALCON_ID_END_15 (15U)
#define LSF_FALCON_ID_END_17 (17U)
#define LSF_FALCON_ID_END_18 (18U)
#define LSF_FALCON_ID_END_21 (21U)
#define LSF_FALCON_INSTANCE_DEFAULT_0 (0x0)
#define LSF_FALCON_INSTANCE_COUNT_DEFAULT_1 (0x1)
// Currently max supported instance is 8 for FECS/GPCCS SMC
#define LSF_FALCON_INSTANCE_FECS_GPCCS_MAX (0x8)
#define LSF_FALCON_INSTANCE_INVALID (0xFFFFFFFFU)
#define LSF_FALCON_INDEX_MASK_DEFAULT_0 (0x0)
/*!
* Size in entries of the ucode descriptor's dependency map.
* This used to be LSF_FALCON_ID_END, but since that had to grow and we did not want to break any
* existing binaries, they had to be split.
*
* Increasing this number should be done with care.
*/
#define LSF_FALCON_DEPMAP_SIZE (11)
/*!
* Falcon Binaries version defines
*/
#define LSF_FALCON_BIN_VERSION_INVALID (0xFFFFFFFFU)
/*!
* Light Secure Falcon Ucode Description Defines
* This stucture is prelim and may change as the ucode signing flow evolves.
*/
typedef struct
{
NvU8 prdKeys[2][16];
NvU8 dbgKeys[2][16];
NvU32 bPrdPresent;
NvU32 bDbgPresent;
NvU32 falconId;
NvU32 bSupportsVersioning;
NvU32 version;
NvU32 depMapCount;
NvU8 depMap[LSF_FALCON_DEPMAP_SIZE * 2 * 4];
NvU8 kdf[16];
} LSF_UCODE_DESC, *PLSF_UCODE_DESC;
/*!
* Light Secure WPR Header
* Defines state allowing Light Secure Falcon bootstrapping.
*
* falconId - LS falcon ID
* lsbOffset - Offset into WPR region holding LSB header
* bootstrapOwner - Bootstrap OWNER (either PMU or SEC2)
* bLazyBootstrap - Skip bootstrapping by ACR
* status - Bootstrapping status
*/
typedef struct
{
NvU32 falconId;
NvU32 lsbOffset;
NvU32 bootstrapOwner;
NvU32 bLazyBootstrap;
NvU32 binVersion;
NvU32 status;
} LSF_WPR_HEADER, *PLSF_WPR_HEADER;
/*!
* LSF shared SubWpr Header
*
* useCaseId - Shared SubWpr se case ID (updated by RM)
* startAddr - start address of subWpr (updated by RM)
* size4K - size of subWpr in 4K (updated by RM)
*/
typedef struct
{
NvU32 useCaseId;
NvU32 startAddr;
NvU32 size4K;
} LSF_SHARED_SUB_WPR_HEADER, *PLSF_SHARED_SUB_WPR_HEADER;
// Shared SubWpr use case IDs
typedef enum
{
LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1,
LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2,
LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_APM_RTS = 3
} LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_ENUM;
#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_APM_RTS
#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFFU)
#define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX
//
// Static sizes of shared subWPRs
// Minimum granularity supported is 4K
//
#define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100) // 1MB in 4K
#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1) // 4K
#define LSF_SHARED_DATA_SUB_WPR_APM_RTS_SIZE_IN_4K (0x1) // 4K
/*!
* Bootstrap Owner Defines
*/
#define LSF_BOOTSTRAP_OWNER_PMU (LSF_FALCON_ID_PMU)
#define LSF_BOOTSTRAP_OWNER_SEC2 (LSF_FALCON_ID_SEC2)
#define LSF_BOOTSTRAP_OWNER_GSPLITE (LSF_FALCON_ID_GSPLITE)
#define LSF_BOOTSTRAP_OWNER_DEFAULT LSF_BOOTSTRAP_OWNER_PMU
/*!
* Image Status Defines
*/
#define LSF_IMAGE_STATUS_NONE (0U)
#define LSF_IMAGE_STATUS_COPY (1U)
#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2U)
#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3U)
#define LSF_IMAGE_STATUS_VALIDATION_DONE (4U)
#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5U)
#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6U)
#define LSF_IMAGE_STATUS_REVOCATION_CHECK_FAILED (7U)
/*!
* Light Secure Bootstrap Header
* Defines state allowing Light Secure Falcon bootstrapping.
*
* signature - Code/data signature details for this LS falcon
* ucodeOffset - Offset into WPR region where UCODE is located
* ucodeSize - Size of ucode
* dataSize - Size of ucode data
* blCodeSize - Size of bootloader that needs to be loaded by bootstrap owner
* blImemOffset - BL starting virtual address. Need for tagging.
* blDataOffset - Offset into WPR region holding the BL data
* blDataSize - Size of BL data
* appCodeOffset - Offset into WPR region where Application UCODE is located
* appCodeSize - Size of Application UCODE
* appDataOffset - Offset into WPR region where Application DATA is located
* appDataSize - Size of Application DATA
* blLoadCodeAt0 - Load BL at 0th IMEM offset
* bSetVACtx - Make sure to set the code/data loading CTX DMA to be virtual before exiting
* bDmaReqCtx - This falcon requires a ctx before issuing DMAs
* bForcePrivLoad- Use priv loading method instead of bootloader/DMAs
*/
#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0 0:0
#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0
#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1
#define NV_FLCN_ACR_LSF_FLAG_SET_VA_CTX 1:1
#define NV_FLCN_ACR_LSF_FLAG_SET_VA_CTX_FALSE 0
#define NV_FLCN_ACR_LSF_FLAG_SET_VA_CTX_TRUE 1
#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX 2:2
#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0
#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 1
#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD 3:3
#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0
#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 1
typedef struct
{
LSF_UCODE_DESC signature;
NvU32 ucodeOffset;
NvU32 ucodeSize;
NvU32 dataSize;
NvU32 blCodeSize;
NvU32 blImemOffset;
NvU32 blDataOffset;
NvU32 blDataSize;
NvU32 appCodeOffset;
NvU32 appCodeSize;
NvU32 appDataOffset;
NvU32 appDataSize;
NvU32 flags;
/*
* TODO: Uncomment this once Sanket's changes
* of HALifying is done
NvU32 monitorCodeOffset;
NvU32 monitorDataOffset;
NvU32 manifestOffset;
*/
} LSF_LSB_HEADER, *PLSF_LSB_HEADER;
/*!
* Light Secure WPR Content Alignments
*/
#define LSF_WPR_HEADER_ALIGNMENT (256U)
#define LSF_SUB_WPR_HEADER_ALIGNMENT (256U)
#define LSF_LSB_HEADER_ALIGNMENT (256U)
#define LSF_BL_DATA_ALIGNMENT (256U)
#define LSF_BL_DATA_SIZE_ALIGNMENT (256U)
#define LSF_BL_CODE_SIZE_ALIGNMENT (256U)
#define LSF_DATA_SIZE_ALIGNMENT (256U)
#define LSF_CODE_SIZE_ALIGNMENT (256U)
// MMU excepts subWpr sizes in units of 4K
#define SUB_WPR_SIZE_ALIGNMENT (4096U)
/*!
* Maximum WPR Header size
*/
#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX (NV_ALIGN_UP((sizeof(LSF_WPR_HEADER) * LSF_FALCON_ID_END), LSF_WPR_HEADER_ALIGNMENT))
#define LSF_LSB_HEADER_TOTAL_SIZE_MAX (NV_ALIGN_UP(sizeof(LSF_LSB_HEADER), LSF_LSB_HEADER_ALIGNMENT))
//
// PMU OBJACR_ALIGNED_256 size will vary with LSF_FALCON_ID_END.
// PMU could run out of DMEM in case we increase LSF_FALCON_ID_END more and more.
// The PMU supports the ACR task on GM20X_thru_VOLTA profiles only.
// In order to prevent LSF_FALCON_ID_END changes to affect older / shipped PMU ucodes (increase of DMEM footprint)
// adding PMU specific ***_END define capturing value covering all PMU profiles that this with the ACR task.
//
#define LSF_FALCON_ID_END_PMU (LSF_FALCON_ID_FBFALCON + 1)
#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX_PMU (NV_ALIGN_UP((sizeof(LSF_WPR_HEADER) * LSF_FALCON_ID_END_PMU), LSF_WPR_HEADER_ALIGNMENT))
// Maximum SUB WPR header size
#define LSF_SUB_WPR_HEADERS_TOTAL_SIZE_MAX (NV_ALIGN_UP((sizeof(LSF_SHARED_SUB_WPR_HEADER) * LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX), LSF_SUB_WPR_HEADER_ALIGNMENT))
/*!
* For the ucode surface alignment, We align to RM_PAGE_SIZE because of
* busMapRmAperture issues, not because of Falcon ucode alignment requirements
* which currently are that it be at least 256.
*/
#define LSF_UCODE_DATA_ALIGNMENT RM_PAGE_SIZE
/*!
* ACR Descriptors used by ACR UC
*/
/*!
* Supporting maximum of 2 regions.
* This is needed to pre-allocate space in DMEM
*/
#define RM_FLCN_ACR_MAX_REGIONS (2)
#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200)
/*!
* startAddress - Starting address of region
* endAddress - Ending address of region
* regionID - Region ID
* readMask - Read Mask
* writeMask - WriteMask
* clientMask - Bit map of all clients currently using this region
* shadowMemStartAddress- FB location from where contents need to be copied to startAddress
*/
typedef struct _def_acr_dmem_region_prop
{
NvU32 startAddress;
NvU32 endAddress;
NvU32 regionID;
NvU32 readMask;
NvU32 writeMask;
NvU32 clientMask;
NvU32 shadowMemStartAddress;
} RM_FLCN_ACR_REGION_PROP, *PRM_FLCN_ACR_REGION_PROP;
/*!
* noOfRegions - Number of regions used by RM.
* regionProps - Region properties
*/
typedef struct _def_acr_regions
{
NvU32 noOfRegions;
RM_FLCN_ACR_REGION_PROP regionProps[RM_FLCN_ACR_MAX_REGIONS];
} RM_FLCN_ACR_REGIONS, *PRM_FLCN_ACR_REGIONS;
/*!
* bVprEnabled : When set, ACR_LOCKDOWN phase programs VPR range. Needs to be
: NvU32 because of alignment
* vprStartAddress : Start address of VPR region. SEC2 binary updates this value
* vprEndAddress : End address of VPR region. SEC2 binary updates this value
* hdcpPolicies : VPR display policies. SEC2 binary updates this value
*/
typedef struct _def_acr_vpr_dmem_desc
{
NvU32 bVprEnabled;
NvU32 vprStartAddress;
NvU32 vprEndAddress;
NvU32 hdcpPolicies;
} ACR_BSI_VPR_DESC, *PACR_BSI_VPR_DESC;
/*!
* reservedDmem - When the bootstrap owner has done bootstrapping other falcons,
* and need to switch into LS mode, it needs to have its own actual
* DMEM image copied into DMEM as part of LS setup. If ACR desc is at
* location 0, it will definitely get overwritten causing data corruption.
* Hence we are reserving 0x200 bytes to give room for any loading data.
* NOTE: This has to be the first member always
* signature - Signature of ACR ucode.
* wprRegionID - Region ID holding the WPR header and its details
* wprOffset - Offset from the WPR region holding the wpr header
* regions - Region descriptors
* ucodeBlobBase- Used for Tegra, stores non-WPR start address where kernel stores ucode blob
* ucodeBlobSize- Used for Tegra, stores the size of the ucode blob
*/
typedef struct _def_acr_dmem_desc
{
NvU32 signatures[4];
NvU32 wprRegionID;
NvU32 wprOffset;
NvU32 mmuMemoryRange;
RM_FLCN_ACR_REGIONS regions;
NvU32 ucodeBlobSize;
// uCodeBlobBase is moved after ucodeBlobSize to inherently align to qword (8 bytes)
NvU64 NV_DECLARE_ALIGNED(ucodeBlobBase, 8);
/*!
* Do not change the offset of this descriptor as it shared between
* ACR_REGION_LOCKDOWN HS binary and SEC2. Any change in this structure
* need recompilation of SEC2 and ACR_LOCKDOWN HS binary
*/
ACR_BSI_VPR_DESC vprDesc;
} RM_FLCN_ACR_DESC, *PRM_FLCN_ACR_DESC;
/*!
* Hub keys/nonce Structure in BSI
*/
#define MAX_SFBHUB_ENCRYPTION_REGION_KEY_SIZE 4
typedef struct _def_acr_hub_scratch_data
{
NvU32 key[MAX_SFBHUB_ENCRYPTION_REGION_KEY_SIZE];
NvU32 nonce[MAX_SFBHUB_ENCRYPTION_REGION_KEY_SIZE];
} ACR_BSI_HUB_DESC, *PACR_BSI_HUB_DESC;
#define MAX_HUB_ENCRYPTION_REGION_COUNT 3
typedef struct _def_acr_hub_scratch_array
{
ACR_BSI_HUB_DESC entries[MAX_HUB_ENCRYPTION_REGION_COUNT];
} ACR_BSI_HUB_DESC_ARRAY, *PACR_BSI_HUB_DESC_ARRAY;
typedef struct _def_acr_reserved_dmem
{
NvU32 reservedDmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; // Always first..
} ACR_RESERVED_DMEM, *PACR_RESERVED_DMEM;
#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF 0:0
#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_DISABLE 0
#define NV_FLCN_ACR_DESC_FLAGS_SIG_VERIF_ENABLE 1
/*!
* Size of ACR phase in dword
*/
#define ACR_PHASE_SIZE_DWORD sizeof(RM_FLCN_ACR_DESC)/sizeof(NvU32)
/*!
* Falcon Mode Tokens
* This is the value logged to a mailbox register to indicate that the
* falcon isn't booted in secure mode.
*/
#define LSF_FALCON_MODE_TOKEN_FLCN_INSECURE (0xDEADDEADU)
// LS encryption context, to store data to decrypt LS images.
#define LS_ENCRYPTION_AES128_CBC_IV_SIZE_BYTE (16)
typedef struct
{
NvU8 bLsEncrypted;
NvU8 rsvd[3];
NvU8 lsEncIV[LS_ENCRYPTION_AES128_CBC_IV_SIZE_BYTE];
} LSF_ENCRYPTION_CONTEXT, *PLSF_ENCRYPTION_CONTEXT;
#endif // RMLSFM_H

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/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* Shared postbox interface defines for RM and PMU.
*/
#ifndef RMPBICMDIF_H
#define RMPBICMDIF_H
/*
* Define the status of postbox interface at different instances.
*
* The values should be in accordance to the spec and must not be changed.
* A new PBI command must be submitted with the status NV_PBI_COMMAND_STATUS_UNDEFINED.
*/
#define NV_PBI_COMMAND_STATUS 7:0
#define NV_PBI_COMMAND_STATUS_UNDEFINED 0x00 // command submitted to PMU
#define NV_PBI_COMMAND_STATUS_SUCCESS 0x01 // command successfully completed by PMU
#define NV_PBI_COMMAND_STATUS_PENDING 0x02 // command accepted by PMU
#define NV_PBI_COMMAND_STATUS_BUSY 0x03 // command processing in PMU
#define NV_PBI_COMMAND_STATUS_UNSPECIFIED_FAILURE 0x04 // unknown failure or hang
#define NV_PBI_COMMAND_STATUS_INVALID_ADDRESS 0x05 // invalid address submitted to PMU
#define NV_PBI_COMMAND_STATUS_MORE_DATA 0x06 // user needs to send more data to PMU
#define NV_PBI_COMMAND_STATUS_INVALID_COMMAND 0x07 // invalid command submitted
/*
* This corresponds to reserved bits of command register
*/
#define NV_PBI_COMMAND_RSVD_0 15:8
#define NV_PBI_COMMAND_RSVD_0_VAL 0x00
/*
* This specifies the dword index if client is sending multiple dwords
* for single Dword this should be zero
*/
#define NV_PBI_COMMAND_BUFFER_INDEX 19:16
/*
* This specifies the total no. of dwords passed by client
*/
#define NV_PBI_COMMAND_BUFFER_SIZE 23:20
/*
* These corresponds the different function ID's supported out of PBI
*/
#define NV_PBI_COMMAND_FUNC_ID 27:24
#define NV_PBI_COMMAND_FUNC_ID_GET_CAPABILITIES (0)
#define NV_PBI_COMMAND_FUNC_ID_EXECUTE_ROUTINE (11)
//
// Definitions for common 'Execute Routine' calls that are
// shared across all GPUs.
//
// Common routine IDs must be in the range 0x80 to 0xff.
//
// Get GID:
#define NV_PBI_EXECUTE_ROUTINE_GET_GID 0x80
// Get Feature:
#define NV_PBI_EXECUTE_ROUTINE_GET_FEATURE 0x81
#define NV_PBI_EXECUTE_ROUTINE_GET_FEATURE_EXCLUSION 5:0
#define NV_PBI_EXECUTE_ROUTINE_GET_FEATURE_EXCLUSION_ALLOWED 0x2
/*
* This corresponds to reserved field of command register
*/
#define NV_PBI_COMMAND_RSVD_1 28:28
#define NV_PBI_COMMAND_RSVD_1_VAL 0x00
/*
* If this bit is set system will be notified on command completion
*/
#define NV_PBI_COMMAND_SYS_NOTIFY 29:29
#define NV_PBI_COMMAND_SYS_NOTIFY_TRUE 0x01
#define NV_PBI_COMMAND_SYS_NOTIFY_FALSE 0x00
/*
* If this bit is set driver will be notified of command completion status
*/
#define NV_PBI_COMMAND_DRV_NOTIFY 30:30
#define NV_PBI_COMMAND_DRV_NOTIFY_TRUE 0x01
#define NV_PBI_COMMAND_DRV_NOTIFY_FALSE 0x00
/*
* Defines the interrupt state of the PBI command
*/
#define NV_PBI_COMMAND_INTERRUPT 31:31
#define NV_PBI_COMMAND_INTERRUPT_TRUE 0x01
#define NV_PBI_COMMAND_INTERRUPT_FALSE 0x00
/*
* This sets the different fields of command register
*/
#define PBI_SET_COMMAND_PARAMS(status, r0, index, sz, cmd, r1, sys, \
drv, intr, val) \
{ \
val = DRF_NUM(_PBI, _COMMAND, _STATUS, status) | \
DRF_NUM(_PBI, _COMMAND, _RSVD_0, r0) | \
DRF_NUM(_PBI, _COMMAND, _BUFFER_INDEX, index) | \
DRF_NUM(_PBI, _COMMAND, _BUFFER_SIZE, sz) | \
DRF_NUM(_PBI, _COMMAND, _FUNC_ID, cmd) | \
DRF_NUM(_PBI, _COMMAND, _RSVD_1, r1) | \
DRF_NUM(_PBI, _COMMAND, _SYS_NOTIFY, sys) | \
DRF_NUM(_PBI, _COMMAND, _DRV_NOTIFY, drv) | \
DRF_NUM(_PBI, _COMMAND, _INTERRUPT, intr); \
}
/*
* postbox_clients_mutex_id
*
* Define the Mutex ID for different PBI clients
*/
enum postbox_clients_mutex_id
{
PBI_CLIENT_NONE = 0x00,
PBI_CLIENT_DRIVER_PCIPBI_SHIM = 0x15
};
#endif /* RMPBICMDIF_H */