mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-28 19:03:58 +00:00
535.43.08
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@@ -72,6 +72,19 @@
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* identity mapped. To use this feature, users need to pass in the
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* hVaspace with identity mapped addresses for the entire memory during
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* construct.
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* PIPELINED
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* This flag allows the copy/memset operation to be pipelined with previous dma operations on the same channel
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* It means that its reads/writes are allowed happen before writes of preceding operations are tlb-acked
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* The flag can be useful when dealing with non-inersecting async operations,
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* but it can result in races when 2 async CE operations target the same allocation, and the second operation uses the flag
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* Race example:
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* 1. async copy A -> B
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* 2. pipelined copy B -> C
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* Here copy 2 can read B before copy finishes writing it, which will result in C containing invalid data
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* Technical details:
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* By default, first _LAUNCH_DMA method of a CE operation is marked has _TRANSFER_TYPE_NON_PIPELINED, which the flag overrides
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* Subsequent _LAUNCH_DMA methods belonging to the same operation use _TRANSFER_TYPE_PIPELINED, as each of these methods should
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* target different addresses
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*
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* submittedWorkId [OUT]
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* The work submission token users can poll on to wait for work
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@@ -79,8 +92,9 @@
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*/
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#define NV0050_CTRL_MEMSET_FLAGS_DEFAULT 0
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#define NV0050_CTRL_MEMSET_FLAGS_ASYNC NVBIT(0)
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#define NV0050_CTRL_MEMSET_FLAGS_VIRTUAL NVBIT(1)
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#define NV0050_CTRL_MEMSET_FLAGS_ASYNC NVBIT(0)
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#define NV0050_CTRL_MEMSET_FLAGS_VIRTUAL NVBIT(1)
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#define NV0050_CTRL_MEMSET_FLAGS_PIPELINED NVBIT(2)
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#define NV0050_CTRL_CMD_MEMSET (0x500101U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8) | NV0050_CTRL_MEMSET_PARAMS_MESSAGE_ID" */
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@@ -98,7 +112,7 @@ typedef struct NV0050_CTRL_MEMSET_PARAMS {
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/*
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* NV0050_CTRL_CMD_MEMCOPY
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*
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* Copies from a source memoryto ssdestination memory and releases a semaphore
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* Copies from a source memoryto ssdestination memory and releases a semaphore
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* on completion
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*
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* hDstMemory [IN]
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@@ -131,6 +145,19 @@ typedef struct NV0050_CTRL_MEMSET_PARAMS {
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* identity mapped. To use this feature, users need to pass in the
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* hVaspace with identity mapped addresses for the entire memory during
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* construct.
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* PIPELINED
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* This flag allows the copy/memset operation to be pipelined with previous dma operations on the same channel
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* It means that its reads/writes are allowed happen before writes of preceding operations are tlb-acked
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* The flag can be useful when dealing with non-inersecting async operations,
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* but it can result in races when 2 async CE operations target the same allocation, and the second operation uses the flag
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* Race example:
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* 1. async copy A -> B
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* 2. pipelined copy B -> C
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* Here copy 2 can read B before copy finishes writing it, which will result in C containing invalid data
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* Technical details:
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* By default, first _LAUNCH_DMA method of a CE operation is marked has _TRANSFER_TYPE_NON_PIPELINED, which the flag overrides
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* Subsequent _LAUNCH_DMA methods belonging to the same operation use _TRANSFER_TYPE_PIPELINED, as each of these methods should
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* target different addresses
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*
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* submittedWorkId [OUT]
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* The work submission token users can poll on to wait for work
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@@ -138,8 +165,9 @@ typedef struct NV0050_CTRL_MEMSET_PARAMS {
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*/
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#define NV0050_CTRL_MEMCOPY_FLAGS_DEFAULT 0
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#define NV0050_CTRL_MEMCOPY_FLAGS_ASYNC NVBIT(1)
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#define NV0050_CTRL_MEMCOPY_FLAGS_VIRTUAL NVBIT(2)
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#define NV0050_CTRL_MEMCOPY_FLAGS_ASYNC NVBIT(0)
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#define NV0050_CTRL_MEMCOPY_FLAGS_VIRTUAL NVBIT(1)
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#define NV0050_CTRL_MEMCOPY_FLAGS_PIPELINED NVBIT(2)
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#define NV0050_CTRL_CMD_MEMCOPY (0x500102U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8 | NV0050_CTRL_MEMCOPY_PARAMS_MESSAGE_ID)" */
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@@ -157,12 +185,12 @@ typedef struct NV0050_CTRL_MEMCOPY_PARAMS {
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/*
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* NV0050_CTRL_CMD_CHECK_PROGRESS
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*
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*
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* Check if a previously submitted work item has been completed by HW.
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*
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* submittedWorkId [IN]
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* The work submission token users can poll on to wait for work
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* completed by CE.
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* completed by CE.
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*
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*/
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#define NV0050_CTRL_CHECK_PROGRESS_RESULT_DEFAULT 0
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