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This commit is contained in:
Andy Ritger
2023-06-14 12:37:59 -07:00
parent eb5c7665a1
commit 26458140be
120 changed files with 83370 additions and 81507 deletions
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223
src/nvidia/inc/kernel/gpu/conf_compute/ccsl.h
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@@ -1,224 +1,3 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef CCSL_H
#define CCSL_H
#include "g_ccsl_nvoc.h"
#include "nvstatus.h"
#include "nvmisc.h"
#include "kernel/gpu/conf_compute/conf_compute.h"
typedef struct ccslContext_t *pCcslContext;
/*
* Initializes a context by providing client and channel information.
*
* ccslContext [in / out]
* hClient [in]
* hChannel [in]
*/
NV_STATUS
ccslContextInitViaChannel
(
pCcslContext *ppCtx,
NvHandle hClient,
NvHandle hChannel
);
/*
* Initializes a context by providing key ID information.
*
* ConfidentialCompute [in]
* ccslContext [in / out]
* globalKeyId [in]
*/
NV_STATUS
ccslContextInitViaKeyId
(
ConfidentialCompute *pConfCompute,
pCcslContext *ppCtx,
NvU32 globalKeyId
);
/*
* Clears the context and erases sensitive material such as keys.
*
* ccslContext [in / out]
*/
void
ccslContextClear
(
pCcslContext ctx
);
/* To be called before library client triggers a Device-side encryption.
* Attempts to increment the library's Device-side message counter and returns an error if it will overflow.
*
* ccslContext [in]
* decryptIv [in]
*
* Returns NV_ERR_INSUFFICIENT_RESOURCES if the next Device-side encryption will overflow.
* Returns NV_OK otherwise.
*/
NV_STATUS
ccslLogDeviceEncryption
(
pCcslContext ctx,
NvU8 *decryptIv
);
/* Request the next IV to be used in encryption. Storing it explicitly enables the caller
* to perform encryption out of order using EncryptWithIv
*
* ccslContext [in / out]
* encryptIv [out]
*
* Returns NV_ERR_INSUFFICIENT_RESOURCES if the next encryption will overflow.
* Returns NV_OK otherwise.
*/
NV_STATUS
ccslAcquireEncryptionIv
(
pCcslContext ctx,
NvU8 *encryptIv
);
/* Rotate the IV for the given direction.
*
* ccslContext [in / out]
* direction [in]
*/
NV_STATUS
ccslRotateIv
(
pCcslContext ctx,
NvU8 direction
);
/*
* Encrypt and sign data using provided IV
*
* ccslContext [in]
* bufferSize [in] - Size of buffer to be encrypted in units of bytes.
* inputBuffer [in] - Address of plaintext input buffer. For performance it should be 16-byte aligned.
* encryptionIv [in/out] - IV to use for encryption. The IV will be "dirtied" after this operation.
* outputBuffer [in/out] - Address of ciphertext output buffer.
* authTagBuffer [in/out] - Address of authentication tag. In APM it is 32 bytes. In HCC it is 16 bytes.
*
* Returns NV_OK.
*/
NV_STATUS
ccslEncryptWithIv
(
pCcslContext ctx,
NvU32 bufferSize,
NvU8 const *inputBuffer,
NvU8 *encryptIv,
NvU8 *outputBuffer,
NvU8 *authTagBuffer
);
/*
* If message counter will not overflow then encrypt and sign data.
*
* ccslContext [in]
* bufferSize [in] - Size of buffer to be encrypted in units of bytes.
* inputBuffer [in] - Address of plaintext input buffer. For performance it should be 16-byte aligned.
* outputBuffer [in/out] - Address of ciphertext output buffer.
* authTagBuffer [in/out] - Address of authentication tag. In APM it is 32 bytes. In HCC it is 16 bytes.
*
* Returns NV_ERR_INSUFFICIENT_RESOURCES if message counter will overflow.
* Returns NV_OK otherwise.
*/
NV_STATUS
ccslEncrypt
(
pCcslContext ctx,
NvU32 bufferSize,
NvU8 const *inputBuffer,
NvU8 *outputBuffer,
NvU8 *authTagBuffer
);
/*
* First verify authentication tag. If authentication passes then the data is decrypted.
*
* ccslContext [in]
* bufferSize [in] - Size of buffer to be decrypted in units of bytes.
* inputBuffer [in] - Address of ciphertext input buffer. For performance it should be 16-byte aligned.
* outputBuffer [in/out] - Address of plaintext output buffer.
* authTagBuffer [in] - Address of authentication tag. In APM it is 32 bytes. In HCC it is 16 bytes.
*
* Returns NV_ERR_INVALID_DATA if verification of the authentication tag fails.
* Returns NV_OK otherwise.
*/
NV_STATUS
ccslDecrypt
(
pCcslContext ctx,
NvU32 bufferSize,
NvU8 const *inputBuffer,
NvU8 const *decryptIv,
NvU8 *outputBuffer,
NvU8 const *authTagBuffer
);
/*
* Sign the plaintext message.
*
* ccslContext [in]
* bufferSize [in] - Size of buffer to be signed in units of bytes.
* inputBuffer [in] - Address of input buffer. For performance it should be 16-byte aligned.
* authTagBuffer [in/out] - Address of authentication tag. In HCC it is 32 bytes.
*
* Returns NV_OK
*/
NV_STATUS
ccslSign
(
pCcslContext ctx,
NvU32 bufferSize,
NvU8 const *inputBuffer,
NvU8 *authTagBuffer
);
#define CCSL_DIR_HOST_TO_DEVICE 0
#define CCSL_DIR_DEVICE_TO_HOST 1
/*
* Returns the number of messages that can be encrypted by the CPU (CCSL_DIR_HOST_TO_DEVICE)
* or encrypted by the GPU (CCSL_DIR_DEVICE_TO_HOST) before the message counter will overflow.
*
* ccslContext [in]
* direction [in] - Either CCSL_DIR_HOST_TO_DEVICE or CCSL_DIR_DEVICE_TO_HOST.
* messageNum [out] - Number of messages that can be encrypted before overflow.
*/
NV_STATUS
ccslQueryMessagePool
(
pCcslContext ctx,
NvU8 direction,
NvU64 *messageNum
);
#endif // CCSL_H

14
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
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@@ -42,6 +42,19 @@
#include "platform/chipset/chipset.h" // BUSINFO
#include "gpu/nvbitmask.h" // NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX
// VF related info for GSP-RM
typedef struct GSP_VF_INFO
{
NvU32 totalVFs;
NvU32 firstVFOffset;
NvU64 FirstVFBar0Address;
NvU64 FirstVFBar1Address;
NvU64 FirstVFBar2Address;
NvBool b64bitBar0;
NvBool b64bitBar1;
NvBool b64bitBar2;
} GSP_VF_INFO;
typedef struct GspSMInfo_t
{
NvU32 version;
@@ -163,6 +176,7 @@ typedef struct GspSystemInfo
NvU32 hypervisorType;
NvBool bIsPassthru;
NvU64 sysTimerOffsetNs;
GSP_VF_INFO gspVFInfo;
} GspSystemInfo;

9
src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h
View File

@@ -57,14 +57,10 @@ typedef struct
NVOC_PREFIX(ceutils) class CeUtils : Object
{
public:
NV_STATUS ceutilsConstruct(CeUtils *pCeUtils, OBJGPU *pGpu, NV0050_ALLOCATION_PARAMETERS *pAllocParams);
NV_STATUS ceutilsConstruct(CeUtils *pCeUtils, OBJGPU *pGpu, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance,
NV0050_ALLOCATION_PARAMETERS *pAllocParams);
void ceutilsDestruct(CeUtils *pCeUtils);
NV_STATUS ceutilsInitialize(CeUtils *pCeUtils, OBJGPU *pGpu, NV0050_ALLOCATION_PARAMETERS *pAllocParams);
void ceutilsDeinit(CeUtils *pCeUtils);
void ceutilsRegisterGPUInstance(CeUtils *pCeUtils, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance);
NV_STATUS ceutilsMemset(CeUtils *pCeUtils, CEUTILS_MEMSET_PARAMS *pParams);
NV_STATUS ceutilsMemcopy(CeUtils *pCeUtils, CEUTILS_MEMCOPY_PARAMS *pParams);
@@ -80,7 +76,6 @@ public:
NvHandle hSubdevice;
OBJCHANNEL *pChannel;
KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance;
OBJGPU *pGpu;
KernelCE *pKCe;

14
src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h
View File

@@ -107,17 +107,8 @@
NV_PUSH_DATA(d4); \
} while (0)
#define READ_CHANNEL_PAYLOAD_SEMA(channel) MEM_RD32((NvU8*)channel->pbCpuVA + \
channel->finishPayloadOffset)
#define READ_CHANNEL_PB_SEMA(channel) MEM_RD32((NvU8*)channel->pbCpuVA + \
channel->semaOffset)
#define WRITE_CHANNEL_PB_SEMA(channel, val) MEM_WR32((NvU8*)channel->pbCpuVA + \
channel->semaOffset, val);
#define WRITE_CHANNEL_PAYLOAD_SEMA(channel,val) MEM_WR32((NvU8*)channel->pbCpuVA + \
channel->finishPayloadOffset, val);
#define READ_CHANNEL_PAYLOAD_SEMA(channel) channelReadChannelMemdesc(channel, channel->finishPayloadOffset)
#define READ_CHANNEL_PB_SEMA(channel) channelReadChannelMemdesc(channel, channel->semaOffset)
//
// This struct contains parameters needed to send a pushbuffer for a CE
@@ -141,6 +132,7 @@ typedef struct
NV_STATUS channelSetupIDs(OBJCHANNEL *pChannel, OBJGPU *pGpu, NvBool bUseVasForCeCopy, NvBool bMIGInUse);
void channelSetupChannelBufferSizes(OBJCHANNEL *pChannel);
NvU32 channelReadChannelMemdesc(OBJCHANNEL *pChannel, NvU32 offset);
// Needed for pushbuffer management
NV_STATUS channelWaitForFreeEntry(OBJCHANNEL *pChannel, NvU32 *pPutIndex);

2
src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h
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@@ -87,7 +87,7 @@ typedef struct OBJMEMSCRUB {
PSCRUB_NODE pScrubList;
#if !defined(SRT_BUILD)
// Scrubber uses ceUtils to manage CE channel
CeUtils ceUtilsObject;
CeUtils *pCeUtils;
#endif
struct OBJGPU *pGpu;
VGPU_GUEST_PMA_SCRUB_BUFFER_RING vgpuScrubBuffRing;

2
src/nvidia/inc/kernel/gpu/spdm/libspdm_includes.h
View File

@@ -46,7 +46,7 @@
__spdmStatus = (expr); \
if (LIBSPDM_STATUS_IS_ERROR(__spdmStatus)) \
{ \
NV_PRINTF(LEVEL_INFO, "SPDM failed with status 0x%0x\n", \
NV_PRINTF(LEVEL_ERROR, "SPDM failed with status 0x%0x\n", \
__spdmStatus); \
status = NV_ERR_GENERIC; \
goto ErrorExit; \