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575.51.02

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This commit is contained in:
Bernhard Stoeckner
2025-04-17 19:35:38 +02:00
parent e8113f665d
commit 4159579888
1142 changed files with 309085 additions and 272273 deletions
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9
src/common/displayport/inc/dp_configcaps.h
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@@ -571,6 +571,8 @@ namespace DisplayPort
virtual void initialize() = 0;
virtual AuxRetry::status setMainLinkChannelCoding(MainLinkChannelCoding channelCoding) = 0;
virtual void setConnectorTypeC(bool bTypeC) = 0;
virtual void setUSBCCableIDInfo(NV0073_CTRL_DP_USBC_CABLEID_INFO *cableIDInfo) = 0;
virtual void setCableVconnSourceUnknown() = 0;
virtual ~DPCDHAL() {}
};
@@ -677,6 +679,9 @@ namespace DisplayPort
// If all the LTTPRs supports FEC
bool bFECSupported;
bool bAuxlessALPMSupported; // DPCD offset F0009
// 0xE000D, DP Tunneling capabilities of DIA which acts as PHY Repeater
bool bDpTunnelingSupported;
bool bDpTunnelingBwAllocModeSupported;
} repeaterCaps;
struct
@@ -1489,12 +1494,14 @@ namespace DisplayPort
virtual bool isDp2xChannelCodingCapable() { return false; }
virtual void setIgnoreCableIdCaps(bool bIgnore) { return; }
virtual void overrideCableIdCap(LinkRate linkRate, bool bEnable) { return; }
virtual void setCableVconnSourceUnknown() { return; }
// implement this function if DPCDHALImpl needs updated state between hotunplug/plug
virtual void initialize(){};
virtual void initialize(){}
virtual AuxRetry::status setMainLinkChannelCoding(MainLinkChannelCoding channelCoding){ return AuxRetry::ack; }
virtual MainLinkChannelCoding getMainLinkChannelCoding() { return ChannelCoding8B10B; }
virtual void setConnectorTypeC(bool bTypeC) {};
virtual void setUSBCCableIDInfo(NV0073_CTRL_DP_USBC_CABLEID_INFO *cableIDInfo) {}
};
}

48
src/common/displayport/inc/dp_configcaps2x.h
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@@ -41,6 +41,7 @@ namespace DisplayPort
CableTypePassive = 1,
CableTypeLRD = 2,
CableTypeActiveReTimer = 3,
CableTypeOptical = 4,
};
struct DPCDHALImpl2x : DPCDHALImpl
@@ -72,13 +73,30 @@ namespace DisplayPort
bool bUHBR_20GSupported;
} dpInTunnelingCaps;
/*
* Cable capabilities determined on the sink end
* read by source via DPCD
*/
struct
{
bool bUHBR_10GSupported;
bool bUHBR_13_5GSupported;
bool bUHBR_20GSupported;
CableType cableType;
} cableCaps;
} rxCableCaps;
/*
* Cable capabilities determined on the source end
*/
struct
{
bool bIsSupported;
bool bUHBR_10GSupported;
bool bUHBR_13_5GSupported;
bool bUHBR_20GSupported;
CableType cableType;
bool bVconnSource;
} txCableCaps;
} caps2x;
struct
@@ -115,6 +133,21 @@ namespace DisplayPort
virtual NvU32 getUHBRSupported();
virtual void setIgnoreCableIdCaps(bool bIgnore){ bIgnoreCableIdCaps = bIgnore; }
virtual void overrideCableIdCap(LinkRate linkRate, bool bEnable);
void setCableVconnSourceUnknown()
{
bCableVconnSourceUnknown = true;
}
void resetTxCableCaps()
{
caps2x.txCableCaps.bUHBR_10GSupported = true;
caps2x.txCableCaps.bUHBR_13_5GSupported = true;
caps2x.txCableCaps.bUHBR_20GSupported = true;
caps2x.txCableCaps.bVconnSource = true;
caps2x.txCableCaps.bIsSupported = false;
}
virtual void setUSBCCableIDInfo(NV0073_CTRL_DP_USBC_CABLEID_INFO *cableIDInfo);
virtual bool parseTestRequestPhy();
virtual bool parseTestRequestTraining(NvU8 * buffer);
// DPCD offset 2230 - 2250
@@ -127,7 +160,8 @@ namespace DisplayPort
// class fields that need re-initialization
bool bIgnoreCableIdCaps;
bool bConnectorIsTypeC;
bool bCableVconnSourceUnknown;
virtual void initialize()
{
setIgnoreCableIdCaps(false);
@@ -145,9 +179,13 @@ namespace DisplayPort
caps2x.bUHBR_13_5GSupported = true;
caps2x.bUHBR_20GSupported = true;
caps2x.cableCaps.bUHBR_10GSupported = true;
caps2x.cableCaps.bUHBR_13_5GSupported = true;
caps2x.cableCaps.bUHBR_20GSupported = true;
caps2x.rxCableCaps.bUHBR_10GSupported = true;
caps2x.rxCableCaps.bUHBR_13_5GSupported = true;
caps2x.rxCableCaps.bUHBR_20GSupported = true;
// txCableCaps are set only if data from connector
// is available to be read
resetTxCableCaps();
};
};
}

22
src/common/displayport/inc/dp_connectorimpl.h
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@@ -321,6 +321,12 @@ namespace DisplayPort
//
bool bDisableDscMaxBppLimit;
//
// Set to true when we want to force head shutdown
// when DSC mode or bpc is changed but LT is still same
//
bool bForceHeadShutdownOnModeTransition;
bool bReportDeviceLostBeforeNew;
bool bDisableSSC;
bool bEnableFastLT;
@@ -335,8 +341,6 @@ namespace DisplayPort
// On eDP, do not cache the source OUI if it reads 0. See bug 4793112
bool bSkipZeroOuiCache;
bool bDisable5019537Fix;
bool bForceHeadShutdownFromRegkey;
bool bForceHeadShutdownPerMonitor;
@@ -383,6 +387,7 @@ namespace DisplayPort
NvU64 allocatedDpTunnelBw;
NvU64 allocatedDpTunnelBwShadow;
bool bForceDisableTunnelBwAllocation;
bool bDisableEffBppSST8b10b;
Group *perHeadAttachedGroup[NV_MAX_HEADS];
NvU32 inTransitionHeadMask;
@@ -514,6 +519,14 @@ namespace DisplayPort
DscParams *pDscParams = NULL, // DSC parameters
DP_IMP_ERROR *pErrorCode = NULL); // Error Status code
virtual bool compoundQueryAttachSSTIsDscPossible(const DpModesetParams &modesetParams,
DscParams *pDscParams = NULL);
virtual bool compoundQueryAttachSSTDsc(const DpModesetParams &modesetParams,
LinkConfiguration lc,
DscParams *pDscParams = NULL,
DP_IMP_ERROR *pErrorCode = NULL);
//
// Timer callback tags.
@@ -622,8 +635,8 @@ namespace DisplayPort
}
bool trainLinkOptimized(LinkConfiguration lConfig);
bool trainLinkOptimizedSingleHeadMultipleSST(GroupImpl * group);
bool getValidLowestLinkConfig(LinkConfiguration &lConfig, LinkConfiguration &lowestSelected,
ModesetInfo queryModesetInfo, const DscParams *pDscParams = NULL);
virtual bool getValidLowestLinkConfig(LinkConfiguration &lConfig, LinkConfiguration &lowestSelected,
ModesetInfo queryModesetInfo, const DscParams *pDscParams = NULL);
bool postLTAdjustment(const LinkConfiguration &, bool force);
void populateUpdatedLaneSettings(NvU8* voltageSwingLane, NvU8* preemphasisLane, NvU32 *data);
void populateDscCaps(DSC_INFO* dscInfo, DeviceImpl * dev, DSC_INFO::FORCED_DSC_PARAMS* forcedParams);
@@ -737,6 +750,7 @@ namespace DisplayPort
}
void getCurrentLinkConfig(unsigned &laneCount, NvU64 &linkRate); // CurrentLink Configuration
void getCurrentLinkConfigWithFEC(unsigned &laneCount, NvU64 &linkRate, bool &bFECEnabled);
unsigned getPanelDataClockMultiplier();
unsigned getGpuDataClockMultiplier();
void configurePowerState(bool bPowerUp);

2
src/common/displayport/inc/dp_connectorimpl2x.h
View File

@@ -69,6 +69,8 @@ namespace DisplayPort
bool willLinkSupportMode(const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo,
NvU32 headIndex = 0, Watermark *watermark = NULL, const DscParams *pDscParams = NULL);
virtual bool getValidLowestLinkConfig(LinkConfiguration &lConfig, LinkConfiguration &lowestSelected,
ModesetInfo queryModesetInfo, const DscParams *pDscParams = NULL);
virtual bool handlePhyPatternRequest();
virtual bool handleTestLinkTrainRequest();

2
src/common/displayport/inc/dp_deviceimpl.h
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@@ -135,7 +135,7 @@ namespace DisplayPort
bool multistream;
bool videoSink, audioSink;
bool plugged;
bool bApplyPclkWarBug4949066;
AuxRetry friendlyAux;
bool payloadAllocated; // did the allocate payload go through?

2
src/common/displayport/inc/dp_edid.h
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@@ -168,7 +168,9 @@ namespace DisplayPort
bool bIgnoreDscCap; // Ignore DSC even if sink reports DSC capability
bool bDisableDownspread;
bool bForceHeadShutdown;
bool bDP2XPreferNonDSCForLowPClk;
bool bDisableDscMaxBppLimit;
bool bForceHeadShutdownOnModeTransition;
bool bSkipCableIdCheck;
bool bAllocateManualTimeslots;
}_WARFlags;

15
src/common/displayport/inc/dp_evoadapter.h
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@@ -135,7 +135,6 @@ namespace DisplayPort
{
private:
NvU32 _maxLinkRateSupportedGpu;
NvU32 _minPClkForCompressed;
NvU32 _maxLinkRateSupportedDfp;
bool _hasIncreasedWatermarkLimits;
bool _hasMultistream;
@@ -161,6 +160,8 @@ namespace DisplayPort
bool _isLTPhyRepeaterSupported;
bool _isMSTPCONCapsReadDisabled;
bool _isDownspreadSupported;
bool _bAvoidHBR3;
bool _bAvoidHBR3DisabledByRegkey;
//
// LTTPR count reported by RM, it might not be the same with DPLib probe
// For example, some Intel LTTPR might not be ready to response 0xF0000 probe
@@ -213,11 +214,6 @@ namespace DisplayPort
return _isPC2Disabled;
}
virtual NvU32 getMinPClkForCompressed()
{
return _minPClkForCompressed;
}
virtual NvU32 getGpuDpSupportedVersions()
{
return _gpuSupportedDpVersions;
@@ -275,6 +271,11 @@ namespace DisplayPort
return _isDownspreadSupported;
}
virtual bool isAvoidHBR3WAREnabled()
{
return _bAvoidHBR3 && !_bAvoidHBR3DisabledByRegkey;
}
// Get GPU DSC capabilities
virtual void getDscCaps(bool *pbDscSupported,
unsigned *pEncoderColorFormatMask,
@@ -344,6 +345,7 @@ namespace DisplayPort
DP_ASSERT(0 && "DP1x should never get this request.");
return false;
}
virtual bool getUSBCCableIDInfo(NV0073_CTRL_DP_USBC_CABLEID_INFO *cableIDInfo) { return false; }
virtual void preLinkTraining(NvU32 head);
virtual void postLinkTraining(NvU32 head);
virtual NvU32 getRegkeyValue(const char *key);
@@ -355,6 +357,7 @@ namespace DisplayPort
unsigned phyRepeaterCount = 0);
virtual bool retrieveRingBuffer(NvU8 dpRingBuffertype, NvU32 numRecords);
virtual void getLinkConfig(unsigned & laneCount, NvU64 & linkRate);
void getLinkConfigWithFEC(unsigned & laneCount, NvU64 & linkRate, bool &bFECEnabled);
virtual bool getMaxLinkConfigFromUefi(NvU8 &linkRate, NvU8 &laneCount);
virtual bool setDpMSAParameters(bool bStereoEnable, const NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS &msaparams);
virtual bool setDpStereoMSAParameters(bool bStereoEnable, const NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS &msaparams);

8
src/common/displayport/inc/dp_evoadapter2x.h
View File

@@ -90,6 +90,7 @@ namespace DisplayPort
{
DP2X_RESET_LINK_REASON reason;
bool bForce;
bool bSkipLt;
} DP2XResetParam;
class EvoMainLink2x : public EvoMainLink
@@ -106,8 +107,10 @@ namespace DisplayPort
bool bSupportUHBR2_50; // Support UHBR2.5 for internal testing.
bool bSupportUHBR2_70; // Support UHBR2.7 for internal testing.
bool bSupportUHBR5_00; // Support UHBR5.0 for internal testing.
bool bEnable5147205Fix; // Enable 5147205 fix.
bool bConnectorIsUSBTypeC;
bool bCableVconnSourceUnknown;
// Start time of DP2.x LT Channel Eqaulization phase.
NvU64 channelEqualizationStartTimeUs;
@@ -178,7 +181,12 @@ namespace DisplayPort
{
return bConnectorIsUSBTypeC;
}
virtual bool isCableVconnSourceUnknown()
{
return bCableVconnSourceUnknown;
}
virtual void invalidateLinkRatesInFallbackTable(const LinkRate linkRate);
virtual bool getUSBCCableIDInfo(NV0073_CTRL_DP_USBC_CABLEID_INFO *cableIDInfo);
};
}

8
src/common/displayport/inc/dp_mainlink.h
View File

@@ -135,6 +135,7 @@ namespace DisplayPort
public:
virtual bool physicalLayerSetTestPattern(PatternInfo * patternInfo) = 0;
virtual bool physicalLayerSetDP2xTestPattern(DP2xPatternInfo * patternInfo) = 0;
virtual bool getUSBCCableIDInfo(NV0073_CTRL_DP_USBC_CABLEID_INFO *cableIDInfo) = 0;
//
// Wrappers for existing link training RM control calls
//
@@ -194,7 +195,9 @@ namespace DisplayPort
// we cannot rely on the DPCD registers being correct or sane)
//
virtual void getLinkConfig(unsigned &laneCount, NvU64 & linkRate) = 0;
// Get the current link config with FEC
virtual void getLinkConfigWithFEC(unsigned &laneCount, NvU64 &linkRate, bool &bFECEnable) {};
// Get the max link config from UEFI.
virtual bool getMaxLinkConfigFromUefi(NvU8 &linkRate, NvU8 &laneCount) = 0;
//
@@ -209,7 +212,6 @@ namespace DisplayPort
virtual NvU32 getUHBRSupported() {return 0;}
virtual bool isRgFlushSequenceUsed() {return false;}
virtual bool isStreamCloningEnabled() = 0;
virtual NvU32 getMinPClkForCompressed() = 0;
virtual NvU32 maxLinkRateSupported() = 0;
virtual bool isLttprSupported() = 0;
virtual bool isFECSupported() = 0;
@@ -278,9 +280,11 @@ namespace DisplayPort
virtual NvU32 allocDisplayId() = 0;
virtual bool freeDisplayId(NvU32 displayId) = 0;
virtual bool queryGPUCapability() {return false;}
virtual bool isAvoidHBR3WAREnabled() = 0;
virtual bool queryAndUpdateDfpParams() = 0;
virtual void updateFallbackMap(NvU32 maxLaneCount, LinkRate maxLinkRate, NvU32 sinkUhbrCaps = 0) { return; }
virtual bool isConnectorUSBTypeC() { return false; }
virtual bool isCableVconnSourceUnknown() { return false; }
virtual void invalidateLinkRatesInFallbackTable(const LinkRate linkRate) { return; }
virtual bool setFlushMode(FlushModePhase phase) { return false; }

22
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -63,12 +63,6 @@
// Message to power down video stream before power down link (set D3)
#define NV_DP_REGKEY_POWER_DOWN_PHY "DP_POWER_DOWN_PHY"
//
// Regkey to re-assess max link if the first assessed link config
// is lower than the panel max
//
#define NV_DP_REGKEY_REASSESS_MAX_LINK "DP_REASSESS_MAX_LINK"
//
// DSC capability of downstream device should be decided based on device's own
// and its parent's DSC capability.
@@ -87,17 +81,22 @@
#define NV_DP2X_IGNORE_CABLE_ID_CAPS "DP2X_IGNORE_CABLE_ID_CAPS"
#define NV_DP2X_REGKEY_DISABLE_EFF_BPP_SST_8b10b "DP2X_REGKEY_DISABLE_EFF_BPP_SST_8b10b"
#define NV_DP2X_REGKEY_VCONN_SOURCE_UNKNOWN_WAR "DP2X_VCONN_SOURCE_UNKNOWN_WAR"
//
// Bug 4388987 : This regkey will disable reading PCON caps for MST.
//
#define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED "DP_BUG_4388987_WAR"
#define NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION "DP_DISABLE_TUNNEL_BW_ALLOCATION"
#define NV_DP_REGKEY_DISABLE_AVOID_HBR3_WAR "DP_DISABLE_AVOID_HBR3_WAR"
// Bug 4793112 : On eDP panel, do not cache source OUI if it reads zero
#define NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE "DP_SKIP_ZERO_OUI_CACHE"
#define NV_DP_REGKEY_DISABLE_FIX_FOR_5019537 "DP_DISABLE_5019537_FIX"
#define NV_DP_REGKEY_ENABLE_FIX_FOR_5147205 "DP_ENABLE_5147205_FIX"
// Bug 5088957 : Force head shutdown in DpLib
#define NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN "DP_WAR_5088957"
@@ -105,6 +104,7 @@
#define NV_DP_REGKEY_ENABLE_LOWER_BPP_CHECK_FOR_DSC "DP_ENABLE_LOWER_BPP_CHECK"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
// All entries set to 0 before initialized by the first EvoMainLink constructor.
@@ -135,14 +135,16 @@ struct DP_REGKEY_DATABASE
bool bBypassEDPRevCheck;
bool bDscMstCapBug3143315;
bool bPowerDownPhyBeforeD3;
bool bReassessMaxLink;
NvU32 supportInternalUhbrOnFpga;
bool bIgnoreCableIdCaps;
bool bDisableEffBppSST8b10b;
bool bMSTPCONCapsReadDisabled;
bool bForceDisableTunnelBwAllocation;
bool bDownspreadDisabled;
bool bDisableAvoidHBR3War;
bool bCableVconnSourceUnknownWar;
bool bSkipZeroOuiCache;
bool bDisable5019537Fix;
bool bEnable5147205Fix;
bool bForceHeadShutdown;
bool bEnableLowerBppCheckForDsc;
};

5
src/common/displayport/inc/dp_watermark.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -133,8 +133,9 @@ namespace DisplayPort
const ModesetInfo &modesetInfo,
Watermark * dpInfo
);
// Return Payload Bandwidth Number(PBN)for requested mode
unsigned pbnForMode(const ModesetInfo &modesetInfo);
unsigned pbnForMode(const ModesetInfo &modesetInfo, bool bAccountSpread = true);
}
#endif //INCLUDED_DP_WATERMARK_H

16
src/common/displayport/src/dp_configcaps.cpp
View File

@@ -424,6 +424,22 @@ void DPCDHALImpl::parseAndReadCaps()
caps.repeaterCaps.bAuxlessALPMSupported =
FLD_TEST_DRF(_DPCD20, _PHY_REPEATER_ALPM_CAPS, _AUX_LESS, _SUPPORTED, buffer[9]);
if (lttprIsAtLeastVersion(2, 0))
{
// 0xE000D, DP Tunneling capabilities for DIA which acts as LTTPR.
if (AuxRetry::ack ==
bus.read(NV_DPCD20_DP_TUNNEL_CAPABILITIES, &byte, sizeof byte))
{
caps.repeaterCaps.bDpTunnelingSupported =
FLD_TEST_DRF(_DPCD20, _DP_TUNNEL_CAPABILITIES,
_DPTUNNELING_SUPPORT, _YES, byte);
caps.repeaterCaps.bDpTunnelingBwAllocModeSupported =
FLD_TEST_DRF(_DPCD20, _DP_TUNNEL_CAPABILITIES,
_DPIN_BW_ALLOCATION_MODE_SUPPORT,
_YES, byte);
}
}
}
else
{

251
src/common/displayport/src/dp_configcaps2x.cpp
View File

@@ -37,27 +37,27 @@ using namespace DisplayPort;
void DPCDHALImpl2x::parseAndSetCableId(NvU8 cableId)
{
caps2x.cableCaps.bUHBR_10GSupported = true;
caps2x.rxCableCaps.bUHBR_10GSupported = true;
caps2x.cableCaps.bUHBR_20GSupported =
caps2x.rxCableCaps.bUHBR_20GSupported =
FLD_TEST_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _UHBR20_10_CAPABILITY, _10_AND_20_GBPS_SUPPORTED, cableId);
caps2x.cableCaps.bUHBR_13_5GSupported =
caps2x.rxCableCaps.bUHBR_13_5GSupported =
FLD_TEST_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _13_5_GBPS_SUPPORTED, _YES, cableId);
switch (DRF_VAL(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPRX, _CABLE_TYPE, cableId))
{
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_CABLE_TYPE_UNKNOWN:
caps2x.cableCaps.cableType = CableTypeUnknown;
caps2x.rxCableCaps.cableType = CableTypeUnknown;
break;
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_PASSIVE:
caps2x.cableCaps.cableType = CableTypePassive;
caps2x.rxCableCaps.cableType = CableTypePassive;
break;
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_LRD:
caps2x.cableCaps.cableType = CableTypeLRD;
caps2x.rxCableCaps.cableType = CableTypeLRD;
break;
case NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_ACTIVE_RETIMER:
caps2x.cableCaps.cableType = CableTypeActiveReTimer;
caps2x.rxCableCaps.cableType = CableTypeActiveReTimer;
break;
default:
DP_PRINTF(DP_ERROR, "Unknown cable type\n");
@@ -70,57 +70,155 @@ void DPCDHALImpl2x::performCableIdHandshakeForTypeC()
NvU8 txCableCaps = 0;
NvU8 rxCableCaps = 0;
// Write sink caps to NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX first.
if (caps2x.bUHBR_20GSupported)
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _UHBR20_10_CAPABILITY,
_10_AND_20_GBPS_SUPPORTED, txCableCaps);
}
else
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _UHBR20_10_CAPABILITY,
_10_0_GBPS_SUPPORTED, txCableCaps);
}
if (caps2x.bUHBR_13_5GSupported)
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _13_5_GBPS_SUPPORTED,
_YES, txCableCaps);
}
// Set cable type based on if any LTTPR is detected.
if (!bLttprSupported || (this->caps.phyRepeaterCount == 0))
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _CABLE_TYPE,
_PASSIVE, txCableCaps);
}
else
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _CABLE_TYPE,
_ACTIVE_RETIMER, txCableCaps);
}
if (AuxRetry::ack != bus.write(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX, &txCableCaps,
sizeof txCableCaps))
{
DP_PRINTF(DP_WARNING, "Failed to write NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX");
}
// Check Cable ID from DPRX
if (AuxRetry::ack !=
bus.read(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX, &rxCableCaps, sizeof rxCableCaps))
{
DP_PRINTF(DP_WARNING, "Failed to read NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX for updated results");
}
parseAndSetCableId(rxCableCaps);
// If no matches, reflect that to the DPRX
if (txCableCaps != rxCableCaps)
else
{
if (AuxRetry::ack !=
bus.write(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX, &rxCableCaps, sizeof rxCableCaps))
parseAndSetCableId(rxCableCaps);
}
if (caps2x.txCableCaps.bIsSupported)
{
if (caps2x.txCableCaps.bUHBR_20GSupported)
{
DP_PRINTF(DP_WARNING, "Failed to update NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX -> %02x", rxCableCaps);
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _UHBR20_10_CAPABILITY,
_10_AND_20_GBPS_SUPPORTED, txCableCaps);
}
else
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _UHBR20_10_CAPABILITY,
_10_0_GBPS_SUPPORTED, txCableCaps);
}
if (caps2x.txCableCaps.bUHBR_13_5GSupported)
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _13_5_GBPS_SUPPORTED,
_YES, txCableCaps);
}
switch (caps2x.txCableCaps.cableType)
{
case CableTypePassive:
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _CABLE_TYPE, _PASSIVE, txCableCaps);
break;
case CableTypeActiveReTimer:
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _CABLE_TYPE, _ACTIVE_RETIMER, txCableCaps);
break;
case CableTypeLRD:
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _CABLE_TYPE, _LRD, txCableCaps);
break;
case CableTypeOptical:
case CableTypeUnknown:
default:
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _CABLE_TYPE, _CABLE_TYPE_UNKNOWN, txCableCaps);
break;
}
}
else if (bCableVconnSourceUnknown)
{
if (caps2x.bUHBR_20GSupported)
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _UHBR20_10_CAPABILITY,
_10_AND_20_GBPS_SUPPORTED, txCableCaps);
}
else
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _UHBR20_10_CAPABILITY,
_10_0_GBPS_SUPPORTED, txCableCaps);
}
if (caps2x.bUHBR_13_5GSupported)
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _13_5_GBPS_SUPPORTED,
_YES, txCableCaps);
}
// Set cable type based on if any LTTPR is detected.
if (!bLttprSupported || (this->caps.phyRepeaterCount == 0))
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _CABLE_TYPE,
_PASSIVE, txCableCaps);
}
else
{
txCableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _CABLE_TYPE,
_ACTIVE_RETIMER, txCableCaps);
}
}
if (caps2x.txCableCaps.bIsSupported)
{
NvU8 cableCaps = txCableCaps;
if (caps2x.txCableCaps.bVconnSource)
{
// write the least common denominator of 0x2217 read value (rxCableCaps) and the eMarker content (txCableCaps)
if (caps2x.txCableCaps.bUHBR_20GSupported && caps2x.rxCableCaps.bUHBR_20GSupported)
{
cableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _UHBR20_10_CAPABILITY,
_10_AND_20_GBPS_SUPPORTED, cableCaps);
}
else if (caps2x.txCableCaps.bUHBR_10GSupported && caps2x.rxCableCaps.bUHBR_10GSupported)
{
cableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _UHBR20_10_CAPABILITY,
_10_0_GBPS_SUPPORTED, cableCaps);
}
else
{
cableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _UHBR20_10_CAPABILITY,
_UHBR_NOT_CAPABLE, cableCaps);
}
if (caps2x.txCableCaps.bUHBR_13_5GSupported && caps2x.rxCableCaps.bUHBR_13_5GSupported)
{
cableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _13_5_GBPS_SUPPORTED,
_YES, cableCaps);
}
else
{
cableCaps = FLD_SET_DRF(_DPCD20, _CABLE_ATTRIBUTES_UPDATED_BY_DPTX, _13_5_GBPS_SUPPORTED,
_NO, cableCaps);
}
}
else
{
cableCaps = rxCableCaps;
}
if (AuxRetry::ack != bus.write(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX, &cableCaps,
sizeof cableCaps))
{
DP_PRINTF(DP_WARNING, "Failed to write NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX");
}
}
else if (bCableVconnSourceUnknown)
{
// Write sink caps to NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX first.
if (AuxRetry::ack != bus.write(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX, &txCableCaps,
sizeof txCableCaps))
{
DP_PRINTF(DP_WARNING, "Failed to write NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX");
}
// Check Cable ID from DPRX
if (AuxRetry::ack !=
bus.read(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX, &rxCableCaps, sizeof rxCableCaps))
{
DP_PRINTF(DP_WARNING, "Failed to read NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX for updated results");
}
else
{
parseAndSetCableId(rxCableCaps);
}
// If no matches, reflect that to the DPRX
if (txCableCaps != rxCableCaps)
{
if (AuxRetry::ack !=
bus.write(NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX, &rxCableCaps, sizeof rxCableCaps))
{
DP_PRINTF(DP_WARNING, "Failed to update NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX -> %02x", rxCableCaps);
}
}
}
}
@@ -142,6 +240,42 @@ void DPCDHALImpl2x::performCableIdHandshake()
}
}
void DPCDHALImpl2x::setUSBCCableIDInfo(NV0073_CTRL_DP_USBC_CABLEID_INFO *cableIDInfo)
{
if (!cableIDInfo)
{
// Reset state as there is no limitation to be imposed from Tx Cable Info
resetTxCableCaps();
return;
}
caps2x.txCableCaps.bIsSupported = true;
caps2x.txCableCaps.bUHBR_10GSupported = cableIDInfo->uhbr10_0_capable;
caps2x.txCableCaps.bUHBR_13_5GSupported = cableIDInfo->uhbr13_5_capable;
caps2x.txCableCaps.bUHBR_20GSupported = cableIDInfo->uhbr20_0_capable;
caps2x.txCableCaps.bVconnSource = cableIDInfo->vconn_source;
switch (cableIDInfo->type)
{
case NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_PASSIVE:
caps2x.txCableCaps.cableType = CableTypePassive;
break;
case NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_ACTIVE_RETIMER:
caps2x.txCableCaps.cableType = CableTypeActiveReTimer;
break;
case NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_ACTIVE_LIN_REDRIVER:
caps2x.txCableCaps.cableType = CableTypeLRD;
break;
case NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_OPTICAL:
caps2x.txCableCaps.cableType = CableTypeOptical;
break;
case NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_UNKNOWN:
default:
caps2x.txCableCaps.cableType = CableTypeUnknown;
break;
}
return;
}
void DPCDHALImpl2x::parseAndReadCaps()
{
NvU8 buffer[16];
@@ -427,9 +561,12 @@ NvU32 DPCDHALImpl2x::getUHBRSupported()
if (!bIgnoreCableIdCaps)
{
bUHBR_10GSupported = bUHBR_10GSupported && caps2x.cableCaps.bUHBR_10GSupported;
bUHBR_13_5GSupported = bUHBR_13_5GSupported && caps2x.cableCaps.bUHBR_13_5GSupported;
bUHBR_20GSupported = bUHBR_20GSupported && caps2x.cableCaps.bUHBR_20GSupported;
bUHBR_10GSupported = bUHBR_10GSupported && caps2x.rxCableCaps.bUHBR_10GSupported
&& caps2x.txCableCaps.bUHBR_10GSupported;
bUHBR_13_5GSupported = bUHBR_13_5GSupported && caps2x.rxCableCaps.bUHBR_13_5GSupported
&& caps2x.txCableCaps.bUHBR_13_5GSupported;
bUHBR_20GSupported = bUHBR_20GSupported && caps2x.rxCableCaps.bUHBR_20GSupported
&& caps2x.txCableCaps.bUHBR_20GSupported;
}
if (caps.phyRepeaterCount > 0)
@@ -460,13 +597,13 @@ void DPCDHALImpl2x::overrideCableIdCap(LinkRate linkRate, bool bEnable)
switch (linkRate)
{
case dp2LinkRate_20_0Gbps:
caps2x.cableCaps.bUHBR_20GSupported = bEnable;
caps2x.rxCableCaps.bUHBR_20GSupported = bEnable;
break;
case dp2LinkRate_13_5Gbps:
caps2x.cableCaps.bUHBR_13_5GSupported = bEnable;
caps2x.rxCableCaps.bUHBR_13_5GSupported = bEnable;
break;
case dp2LinkRate_10_0Gbps:
caps2x.cableCaps.bUHBR_10GSupported = bEnable;
caps2x.rxCableCaps .bUHBR_10GSupported = bEnable;
break;
default:
DP_PRINTF(DP_ERROR, "DPHAL> Invalid link rate (%d) to override.", linkRate);

580
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -176,16 +176,15 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled;
this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315;
this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
this->bReassessMaxLink = dpRegkeyDatabase.bReassessMaxLink;
if (dpRegkeyDatabase.applyMaxLinkRateOverrides)
{
this->maxLinkRateFromRegkey = hal->mapLinkBandiwdthToLinkrate(dpRegkeyDatabase.applyMaxLinkRateOverrides); // BW to linkrate
}
this->bForceDisableTunnelBwAllocation = dpRegkeyDatabase.bForceDisableTunnelBwAllocation;
this->bSkipZeroOuiCache = dpRegkeyDatabase.bSkipZeroOuiCache;
this->bDisable5019537Fix = dpRegkeyDatabase.bDisable5019537Fix;
this->bForceHeadShutdownFromRegkey = dpRegkeyDatabase.bForceHeadShutdown;
this->bEnableLowerBppCheckForDsc = dpRegkeyDatabase.bEnableLowerBppCheckForDsc;
this->bDisableEffBppSST8b10b = dpRegkeyDatabase.bDisableEffBppSST8b10b;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -518,6 +517,7 @@ create:
newDev->dpcdRevisionMinor = device.dpcdRevisionMinor;
newDev->complianceDeviceEdidReadTest = isCompliance;
newDev->maxTmdsClkRate = maxTmdsClkRate;
newDev->bApplyPclkWarBug4949066 = false;
Address::NvU32Buffer addrBuffer;
dpMemZero(addrBuffer, sizeof(addrBuffer));
@@ -525,6 +525,11 @@ create:
NV_DPTRACE_INFO(NEW_SINK_DETECTED, newDev->address.size(), addrBuffer[0], addrBuffer[1], addrBuffer[2], addrBuffer[3],
newDev->multistream, newDev->rawEDID.getManufId(), newDev->rawEDID.getProductId());
if(newDev->rawEDID.getManufId() == 0x6D1E)
{
newDev->bApplyPclkWarBug4949066 = true;
}
// Apply any DPCD overrides if required
newDev->dpcdOverrides();
@@ -1337,35 +1342,6 @@ bool ConnectorImpl::compoundQueryAttachMST(Group * target,
localInfo.lc.enableFEC(isFECCapable());
}
if (bDP2XPreferNonDSCForLowPClk &&
modesetParams.modesetInfo.pixelClockHz < main->getMinPClkForCompressed())
{
if(!compoundQueryAttachMSTGeneric(target, modesetParams, &localInfo,
pDscParams, pErrorCode))
{
if (compoundQueryAttachMSTIsDscPossible(target, modesetParams, pDscParams))
{
result = compoundQueryAttachMSTDsc(target, modesetParams, &localInfo,
pDscParams, pErrorCode);
if (!result)
{
return false;
}
return compoundQueryAttachMSTGeneric(target, modesetParams, &localInfo,
pDscParams, pErrorCode);
}
else
{
return false;
}
}
else
{
return true;
}
}
if (compoundQueryAttachMSTIsDscPossible(target, modesetParams, pDscParams))
{
unsigned int forceDscBitsPerPixelX16 = pDscParams->bitsPerPixelX16;
@@ -1375,13 +1351,13 @@ bool ConnectorImpl::compoundQueryAttachMST(Group * target,
{
return false;
}
compoundQueryResult = compoundQueryAttachMSTGeneric(target, modesetParams, &localInfo,
pDscParams, pErrorCode);
pDscParams, pErrorCode);
//
// compoundQueryAttachMST Generic might fail due to the insufficient bandwidth ,
// We only check whether bpp can be fit in the available bandwidth based on the tranied link config in compoundQueryAttachMSTDsc function.
// There might be cases where the default 10 bpp might fit in the available bandwidth based on the trained link config,
// There might be cases where the default 10 bpp might fit in the available bandwidth based on the trained link config,
// however, the bandwidth might be insufficient at the actual bottleneck link between source and sink to drive the mode, causing CompoundQueryAttachMSTGeneric to fail.
// Incase of CompoundQueryAttachMSTGeneric failure, instead of returning false, check whether the mode can be supported with the max dsc compression bpp
// and return true if it can be supported.
@@ -1572,20 +1548,7 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target,
warData.dpData.linkRateHz = localInfo->lc.peakRate;
warData.dpData.bIs128b132bChannelCoding = localInfo->lc.bIs128b132bChannelCoding;
if (localInfo->lc.bIs128b132bChannelCoding)
{
//
// Dplib need to calculate effective bpp in case of 128b132b which will be more than bpp
// to accomodate padding and EOC and we need to use that to find the DSC bpp for the mode.
// Currenlty Dplib does not use effective bpp for PPS calculations. Needed changes are
// described in bug 5004872.
// As temporary WAR, are restricting available link BW to 96% of actually available link BW
// in 128b132b mode so that max DSC bpp calculated always leaves enough link bw
// to accomodate the needed effective bpp for the mode.
//
availableBandwidthBitsPerSecond = (availableBandwidthBitsPerSecond * 96)/100;
}
warData.dpData.bDisableEffBppSST8b10b = this->bDisableEffBppSST8b10b;
warData.dpData.laneCount = localInfo->lc.lanes;
warData.dpData.dpMode = DSC_DP_MST;
@@ -1664,7 +1627,7 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target,
localInfo->localModesetInfo.bEnableDsc = true;
localInfo->localModesetInfo.depth = bitsPerPixelX16;
if (modesetParams.colorFormat == dpColorFormat_YCbCr422 &&
dev->dscCaps.dscDecoderColorFormatCaps.bYCbCrNative422 &&
dev->dscCaps.dscDecoderColorFormatCaps.bYCbCrNative422 &&
(dscInfo.gpuCaps.encoderColorFormatMask & DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422) &&
(dscInfo.sinkCaps.decoderColorFormatMask & DSC_DECODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422))
{
@@ -1825,7 +1788,7 @@ bool ConnectorImpl::compoundQueryAttachMSTGeneric(Group * target,
tail->bandwidth.compound_query_state.timeslots_used_by_query -= linkConfig->slotsForPBN(base_pbn);
tail->bandwidth.compound_query_state.bandwidthAllocatedForIndex &= ~(1 << compoundQueryCount);
}
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH);
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH)
}
}
tail = (DeviceImpl*)tail->getParent();
@@ -1833,24 +1796,177 @@ bool ConnectorImpl::compoundQueryAttachMSTGeneric(Group * target,
}
// If the compoundQueryResult is false, we need to reset the compoundQueryLocalLinkPBN
if (!compoundQueryResult && this->bEnableLowerBppCheckForDsc)
if (!compoundQueryResult && this->bEnableLowerBppCheckForDsc)
{
compoundQueryLocalLinkPBN -= slots_pbn;
}
return compoundQueryResult;
}
bool ConnectorImpl::compoundQueryAttachSSTIsDscPossible
(
const DpModesetParams &modesetParams,
DscParams *pDscParams
)
{
bool bGpuDscSupported = false;
main->getDscCaps(&bGpuDscSupported);
DeviceImpl * nativeDev = this->findDeviceInList(Address());
if (bGpuDscSupported && // if GPU supports DSC
this->isFECSupported() && // If GPU supports FEC
pDscParams && // if client sent DSC info
pDscParams->bCheckWithDsc && // if client wants to check with DSC
nativeDev->isDSCPossible() && // if device supports DSC decompression
(nativeDev->isFECSupported() || main->isEDP()) && // if device supports FEC decoding or is an DSC capable eDP panel which doesn't support FEC
(modesetParams.modesetInfo.bitsPerComponent != 6)) // DSC doesn't support bpc = 6
{
return true;
}
return false;
}
bool ConnectorImpl::compoundQueryAttachSSTDsc
(
const DpModesetParams &modesetParams,
LinkConfiguration lc,
DscParams *pDscParams,
DP_IMP_ERROR *pErrorCode
)
{
DSC_INFO dscInfo;
MODESET_INFO modesetInfoDSC;
WAR_DATA warData;
NvU64 availableBandwidthBitsPerSecond = 0;
unsigned PPS[DSC_MAX_PPS_SIZE_DWORD];
unsigned bitsPerPixelX16 = pDscParams->bitsPerPixelX16;
bool result;
NVT_STATUS ppsStatus;
ModesetInfo localModesetInfo = modesetParams.modesetInfo;
DeviceImpl * nativeDev = this->findDeviceInList(Address());
if (!this->preferredLinkConfig.isValid() && nativeDev->isFECSupported())
{
lc.enableFEC(true);
}
dpMemZero(PPS, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD);
dpMemZero(&dscInfo, sizeof(DSC_INFO));
dpMemZero(&warData, sizeof(WAR_DATA));
// Populate DSC related info for PPS calculations
this->populateDscCaps(&dscInfo, nativeDev->devDoingDscDecompression, pDscParams->forcedParams);
// Populate modeset related info for PPS calculations
this->populateDscModesetInfo(&modesetInfoDSC, &modesetParams);
// checking for DSC v1.1 and YUV combination
if ( (dscInfo.sinkCaps.algorithmRevision.versionMajor == 1) &&
(dscInfo.sinkCaps.algorithmRevision.versionMinor == 1) &&
(modesetParams.colorFormat == dpColorFormat_YCbCr444 ))
{
DP_PRINTF(DP_WARNING, "WARNING: DSC v1.2 or higher is recommended for using YUV444");
DP_PRINTF(DP_WARNING, "Current version is 1.1");
}
availableBandwidthBitsPerSecond = lc.convertMinRateToDataRate() * 8 * lc.lanes;
warData.dpData.linkRateHz = lc.peakRate;
warData.dpData.bIs128b132bChannelCoding = lc.bIs128b132bChannelCoding;
warData.dpData.bDisableEffBppSST8b10b = this->bDisableEffBppSST8b10b;
warData.dpData.laneCount = lc.lanes;
warData.dpData.hBlank = modesetParams.modesetInfo.rasterWidth - modesetParams.modesetInfo.surfaceWidth;
warData.dpData.dpMode = DSC_DP_SST;
warData.connectorType = DSC_DP;
warData.dpData.bDisableDscMaxBppLimit = bDisableDscMaxBppLimit;
if (main->isEDP())
{
warData.dpData.bIsEdp = true;
}
ppsStatus = DSC_GeneratePPSWithSliceCountMask(&dscInfo,
&modesetInfoDSC,
&warData,
availableBandwidthBitsPerSecond,
(NvU32*)(PPS),
(NvU32*)(&bitsPerPixelX16),
&(pDscParams->sliceCountMask));
if (ppsStatus != NVT_STATUS_SUCCESS)
{
result = false;
SET_DP_IMP_ERROR(pErrorCode, translatePpsErrorToDpImpError(ppsStatus))
pDscParams->bEnableDsc = false;
}
else
{
localModesetInfo.bEnableDsc = true;
localModesetInfo.depth = bitsPerPixelX16;
LinkConfiguration lowestSelected;
bool bIsModeSupported = false;
if (this->preferredLinkConfig.isValid())
{
// Check if mode is possible with preferred link config
bIsModeSupported = willLinkSupportModeSST(lc, localModesetInfo, pDscParams);
}
else
{
//
// Check if mode is possible with calculated bits_per_pixel.
// Check with all possible link configs and not just highest
// assessed because with DSC, mode can fail with higher
// link config and pass for lower one. This is because
// if raster parameters are really small and DP bandwidth is
// very high then we may end up with some TU with 0 active
// symbols in SST. This may cause HW hang and so DP IMP rejects
// this mode. Refer Bug 200379426.
//
bIsModeSupported = getValidLowestLinkConfig(lc, lowestSelected, localModesetInfo, pDscParams);
}
if (!bIsModeSupported)
{
pDscParams->bEnableDsc = false;
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH_DSC)
result = false;
}
else
{
pDscParams->bEnableDsc = true;
result = true;
if (pDscParams->pDscOutParams != NULL)
{
//
// If requested then DP Library is supposed to return if mode is
// possible with DSC and calculated PPS and bits per pixel.
//
dpMemCopy(pDscParams->pDscOutParams->PPS, PPS, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD);
pDscParams->bitsPerPixelX16 = bitsPerPixelX16;
}
else
{
//
// Client only wants to know if mode is possible or not but doesn't
// need all calculated PPS parameters in case DSC is required. Do nothing.
//
}
}
}
return result;
}
bool ConnectorImpl::compoundQueryAttachSST(Group * target,
const DpModesetParams &modesetParams, // Modeset info
DscParams *pDscParams, // DSC parameters
DP_IMP_ERROR *pErrorCode)
{
ModesetInfo localModesetInfo = modesetParams.modesetInfo;
bool bGpuDscSupported;
NVT_STATUS ppsStatus;
main->getDscCaps(&bGpuDscSupported);
DeviceImpl * nativeDev = findDeviceInList(Address());
if (compoundQueryCount != 1)
@@ -1901,7 +2017,7 @@ bool ConnectorImpl::compoundQueryAttachSST(Group * target,
lc.enableFEC(false);
}
// If do not found valid native device the force lagacy DP IMP
// If a valid native DP device was not found, force legacy DP IMP
if (!nativeDev)
{
compoundQueryResult = this->willLinkSupportModeSST(lc, modesetParams.modesetInfo, pDscParams);
@@ -1910,178 +2026,68 @@ bool ConnectorImpl::compoundQueryAttachSST(Group * target,
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_WATERMARK_BLANKING)
}
}
else if ((pDscParams && (pDscParams->forceDsc == DSC_FORCE_ENABLE)) || // DD has forced DSC Enable
(modesetParams.modesetInfo.mode == DSC_DUAL) || // DD decided to use 2 Head 1 OR mode
(!this->willLinkSupportModeSST(lc, modesetParams.modesetInfo, pDscParams))) // Mode is not possible without DSC
else
{
// If DP IMP fails without DSC or client requested to force DSC
if (pDscParams && pDscParams->forceDsc != DSC_FORCE_DISABLE)
if ((lc.peakRate == dp2LinkRate_8_10Gbps) &&
(main->isAvoidHBR3WAREnabled()) &&
(compoundQueryAttachSSTIsDscPossible(modesetParams, pDscParams)))
{
// Check if panel and GPU both supports DSC or not. Also check if panel supports FEC
if (bGpuDscSupported && // if GPU supports DSC
this->isFECSupported() && // If GPU supports FEC
pDscParams && // if client sent DSC info
pDscParams->bCheckWithDsc && // if client wants to check with DSC
nativeDev->isDSCPossible() && // if device supports DSC decompression
(nativeDev->isFECSupported() || main->isEDP()) && // if device supports FEC decoding or is an DSC capable eDP panel which doesn't support FEC
(modesetParams.modesetInfo.bitsPerComponent != 6)) // DSC doesn't support bpc = 6
LinkConfiguration lowerLc = lc;
lowerLc.lowerConfig(false);
if ((pDscParams && (pDscParams->forceDsc == DSC_FORCE_ENABLE)) ||
(modesetParams.modesetInfo.mode == DSC_DUAL) ||
(!this->willLinkSupportModeSST(lowerLc, modesetParams.modesetInfo, pDscParams)))
{
DSC_INFO dscInfo;
MODESET_INFO modesetInfoDSC;
WAR_DATA warData;
NvU64 availableBandwidthBitsPerSecond = 0;
unsigned PPS[DSC_MAX_PPS_SIZE_DWORD];
unsigned bitsPerPixelX16 = pDscParams->bitsPerPixelX16;
if (!this->preferredLinkConfig.isValid() && nativeDev->isFECSupported())
if (pDscParams && pDscParams->forceDsc != DSC_FORCE_DISABLE)
{
lc.enableFEC(true);
}
dpMemZero(PPS, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD);
dpMemZero(&dscInfo, sizeof(DSC_INFO));
dpMemZero(&warData, sizeof(WAR_DATA));
// Populate DSC related info for PPS calculations
populateDscCaps(&dscInfo, nativeDev->devDoingDscDecompression, pDscParams->forcedParams);
// Populate modeset related info for PPS calculations
populateDscModesetInfo(&modesetInfoDSC, &modesetParams);
// checking for DSC v1.1 and YUV combination
if ( (dscInfo.sinkCaps.algorithmRevision.versionMajor == 1) &&
(dscInfo.sinkCaps.algorithmRevision.versionMinor == 1) &&
(modesetParams.colorFormat == dpColorFormat_YCbCr444 ))
{
DP_PRINTF(DP_WARNING, "WARNING: DSC v1.2 or higher is recommended for using YUV444");
DP_PRINTF(DP_WARNING, "Current version is 1.1");
}
availableBandwidthBitsPerSecond = lc.convertMinRateToDataRate() * 8 * lc.lanes;
warData.dpData.linkRateHz = lc.peakRate;
warData.dpData.bIs128b132bChannelCoding = lc.bIs128b132bChannelCoding;
if (lc.bIs128b132bChannelCoding)
{
//
// Dplib need to calculate effective bpp in case of 128b132b which will be more than bpp
// to accomodate padding and EOC and we need to use that to find the DSC bpp for the mode.
// Currenlty Dplib does not use effective bpp for PPS calculations. Needed changes are
// described in bug 5004872.
// As temporary WAR, are restricting available link BW to 96% of actually available link BW
// in 128b132b mode so that max DSC bpp calculated always leaves enough link bw
// to accomodate the needed effective bpp for the mode.
// Note 96.2% is 128b132b channel coding link efficiency.
//
availableBandwidthBitsPerSecond = (availableBandwidthBitsPerSecond * 96)/ 100;
}
warData.dpData.laneCount = lc.lanes;
warData.dpData.hBlank = modesetParams.modesetInfo.rasterWidth - modesetParams.modesetInfo.surfaceWidth;
warData.dpData.dpMode = DSC_DP_SST;
warData.connectorType = DSC_DP;
warData.dpData.bDisableDscMaxBppLimit = bDisableDscMaxBppLimit;
if (main->isEDP())
{
warData.dpData.bIsEdp = true;
}
ppsStatus = DSC_GeneratePPSWithSliceCountMask(&dscInfo,
&modesetInfoDSC,
&warData,
availableBandwidthBitsPerSecond,
(NvU32*)(PPS),
(NvU32*)(&bitsPerPixelX16),
&(pDscParams->sliceCountMask));
if (ppsStatus != NVT_STATUS_SUCCESS)
{
compoundQueryResult = false;
SET_DP_IMP_ERROR(pErrorCode, translatePpsErrorToDpImpError(ppsStatus))
pDscParams->bEnableDsc = false;
}
else
{
localModesetInfo.bEnableDsc = true;
localModesetInfo.depth = bitsPerPixelX16;
LinkConfiguration lowestSelected;
bool bIsModeSupported = false;
if (modesetParams.colorFormat == dpColorFormat_YCbCr422 &&
nativeDev->dscCaps.dscDecoderColorFormatCaps.bYCbCrNative422)
{
localModesetInfo.colorFormat = dpColorFormat_YCbCr422_Native;
}
if (this->preferredLinkConfig.isValid())
{
// Check if mode is possible with preferred link config
bIsModeSupported = willLinkSupportModeSST(lc, localModesetInfo, pDscParams);
}
else
{
//
// Check if mode is possible with calculated bits_per_pixel.
// Check with all possible link configs and not just highest
// assessed because with DSC, mode can fail with higher
// link config and pass for lower one. This is because
// if raster parameters are really small and DP bandwidth is
// very high then we may end up with some TU with 0 active
// symbols in SST. This may cause HW hang and so DP IMP rejects
// this mode. Refer Bug 200379426.
//
bIsModeSupported = getValidLowestLinkConfig(lc, lowestSelected, localModesetInfo, pDscParams);
}
if (!bIsModeSupported)
{
pDscParams->bEnableDsc = false;
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH_DSC)
compoundQueryResult = false;
}
else
{
pDscParams->bEnableDsc = true;
compoundQueryResult = true;
if (pDscParams->pDscOutParams != NULL)
{
//
// If requested then DP Library is supposed to return if mode is
// possible with DSC and calculated PPS and bits per pixel.
//
dpMemCopy(pDscParams->pDscOutParams->PPS, PPS, sizeof(unsigned) * DSC_MAX_PPS_SIZE_DWORD);
pDscParams->bitsPerPixelX16 = bitsPerPixelX16;
}
else
{
//
// Client only wants to know if mode is possible or not but doesn't
// need all calculated PPS parameters in case DSC is required. Do nothing.
//
}
}
bool result = compoundQueryAttachSSTDsc(modesetParams, lowerLc, pDscParams, pErrorCode);
if (result == true)
return result;
}
}
else
{
// Either GPU or Sink doesn't support DSC
// Mode was successful
return true;
}
}
if ((pDscParams && (pDscParams->forceDsc == DSC_FORCE_ENABLE)) || // DD has forced DSC Enable
(modesetParams.modesetInfo.mode == DSC_DUAL) || // DD decided to use 2 Head 1 OR mode
(!this->willLinkSupportModeSST(lc, modesetParams.modesetInfo, pDscParams))) // Mode is not possible without DSC
{
// If DP IMP fails without DSC or client requested to force DSC
if (pDscParams && pDscParams->forceDsc != DSC_FORCE_DISABLE)
{
// Check if panel and GPU both supports DSC or not. Also check if panel supports FEC
if (compoundQueryAttachSSTIsDscPossible(modesetParams, pDscParams))
{
compoundQueryResult = compoundQueryAttachSSTDsc(modesetParams,
lc,
pDscParams,
pErrorCode);
}
else
{
// Either GPU or Sink doesn't support DSC
compoundQueryResult = false;
}
}
else
{
// Client hasn't sent DSC params info or has asked to force disable DSC.
compoundQueryResult = false;
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH_NO_DSC)
}
}
else
{
// Client hasn't sent DSC params info or has asked to force disable DSC.
compoundQueryResult = false;
SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_INSUFFICIENT_BANDWIDTH_NO_DSC)
// Mode was successful
compoundQueryResult = true;
}
}
else
{
// Mode was successful
compoundQueryResult = true;
}
return compoundQueryResult;
}
@@ -2775,6 +2781,21 @@ bool ConnectorImpl::isHeadShutDownNeeded(Group * target, // Group
return true;
}
//
// In case of DSC, if bpc is changing, we need to shut down the head
// since PPS can change
// In case of mode transition (DSC <-> non-DSC), if the link config is same as previous mode, we need to shut down the head
// since VBID[6] needs to be updated accordingly
//
if ((bForceHeadShutdownOnModeTransition &&
((modesetInfo.bEnableDsc && targetImpl->lastModesetInfo.bEnableDsc) &&
(modesetInfo.bitsPerComponent != targetImpl->lastModesetInfo.bitsPerComponent))) ||
((lowestSelected.getTotalDataRate() == activeLinkConfig.getTotalDataRate()) &&
(modesetInfo.bEnableDsc != targetImpl->lastModesetInfo.bEnableDsc)))
{
return true;
}
// For dual DP while changing link config, we need to shut
// down the head
if (lowestSelected.lanes == 8)
@@ -3189,7 +3210,6 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr
Device *newDev = target->enumDevices(0);
DeviceImpl *dev = (DeviceImpl *)newDev;
if (hal->isDpTunnelBwAllocationEnabled() &&
((allocatedDpTunnelBwShadow != 0) ||
(allocatedDpTunnelBw == 0)))
@@ -4289,6 +4309,7 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType)
//
unsigned laneCount = 0;
NvU64 linkRate = 0;
bool bFECEnabled = false;
NvU8 linkRateFromUefi, laneCountFromUefi;
// Query the max link config if provided by UEFI.
@@ -4369,7 +4390,7 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType)
this->getDownspreadDisabled());
// Get the currently applied linkconfig and update SW state
getCurrentLinkConfig(laneCount, linkRate);
getCurrentLinkConfigWithFEC(laneCount, linkRate, bFECEnabled);
activeLinkConfig = LinkConfiguration (&this->linkPolicy,
laneCount, linkRate,
@@ -4454,13 +4475,10 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType)
// Find the active group(s)
GroupImpl * groupAttached = 0;
if (!this->bDisable5019537Fix)
for (ListElement * e = activeGroups.begin(); e != activeGroups.end(); e = e->next)
{
for (ListElement * e = activeGroups.begin(); e != activeGroups.end(); e = e->next)
{
DP_ASSERT(bIsUefiSystem || linkUseMultistream() || (!groupAttached && "Multiple attached heads"));
groupAttached = (GroupImpl * )e;
}
DP_ASSERT(bIsUefiSystem || linkUseMultistream() || (!groupAttached && "Multiple attached heads"));
groupAttached = (GroupImpl * )e;
}
// Disconnect heads
@@ -4477,15 +4495,9 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType)
hal->updateDPCDOffline();
// At first trial / when retraining, always start with _maxLinkConfig
// Protect with regkey for now
if (bReassessMaxLink)
{
lConfig = _maxLinkConfig;
}
lConfig = _maxLinkConfig;
if (hal->isDpcdOffline())
{
lConfig = _maxLinkConfig;
break;
}
if (!train(lConfig, false /* do not force LT */))
@@ -4504,7 +4516,7 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType)
timer->sleep(40);
} while (retryCount++ < WAR_MAX_REASSESS_ATTEMPT);
if (!activeLinkConfig.isValid() && !(this->bDisable5019537Fix))
if (!activeLinkConfig.isValid())
{
if (groupAttached && groupAttached->lastModesetInfo.pixelClockHz != 0)
{
@@ -5130,14 +5142,11 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
bSkipLt = false;
}
if ((groupAttached && groupAttached->isHeadAttached()) || !(this->bDisable5019537Fix))
// Enter flush mode/detach head before LT
if (!bSkipLt)
{
// Enter flush mode/detach head before LT
if (!bSkipLt)
{
if (!(bEnteredFlushMode = this->enableFlush()))
return false;
}
if (!(bEnteredFlushMode = this->enableFlush()))
return false;
}
bLinkTrainingSuccessful = train(lowestSelected, false);
@@ -5148,11 +5157,8 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
if (!bLinkTrainingSuccessful && bSkipLt)
{
bSkipLt = false;
if ((groupAttached && groupAttached->isHeadAttached()) || !(this->bDisable5019537Fix))
{
if (!(bEnteredFlushMode = this->enableFlush()))
return false;
}
if (!(bEnteredFlushMode = this->enableFlush()))
return false;
bLinkTrainingSuccessful = train(lowestSelected, false);
}
if (!bLinkTrainingSuccessful)
@@ -5346,7 +5352,19 @@ bool ConnectorImpl::getValidLowestLinkConfig
selectedConfig = this->allPossibleLinkCfgs[i];
selectedConfig.enableFEC(lConfig.bEnableFEC);
if (lConfig.bIs128b132bChannelCoding &&
!(selectedConfig.bIs128b132bChannelCoding) &&
!modesetInfo.bEnableDsc)
{
//
// If highest link rate is UHBR 128b132b and current selected config is 8b10b,
// FEC should not be enabled if DSC is not enabled since
// 1. This function will be called only for SST and that too when preferred
// link config is not set.
// 2. for SST and in 8b10b mode, FEC is enabled only when DSC is enabled
//
selectedConfig.enableFEC(false);
}
if (willLinkSupportModeSST(selectedConfig, modesetInfo))
{
bIsModeSupported = true;
@@ -5875,10 +5893,7 @@ bool ConnectorImpl::enableFlush()
// 2. The next link training call must not skip programming the hardware.
// Otherwise, EVO will hang if the head is still active when flush mode is disabled.
//
if (!this->bDisable5019537Fix)
{
activeLinkConfig = LinkConfiguration();
}
activeLinkConfig = LinkConfiguration();
bSkipLt = false;
sortActiveGroups(false);
@@ -6051,7 +6066,11 @@ bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup)
// Check for available timeslots
if (slot_count > freeSlots)
{
DP_PRINTF(DP_ERROR, "DP-TS> Failed to allocate timeslot!! Not enough free slots. slot_count: %d, freeSlots: %d",
slot_count, freeSlots);
return false;
}
for (ListElement * i = activeGroups.begin(); i != activeGroups.end(); i = i->next)
{
@@ -6126,14 +6145,7 @@ void ConnectorImpl::beforeDeleteStream(GroupImpl * group, bool forFlushMode)
{
if(isLinkLost())
{
if(!this->bDisable5019537Fix)
{
train(highestAssessedLC, false);
}
else
{
train(activeLinkConfig, false);
}
train(highestAssessedLC, false);
}
}
@@ -6694,6 +6706,17 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
hal->initialize();
// DP2.1 Capability info about USB-C cable
NV0073_CTRL_DP_USBC_CABLEID_INFO cableIDInfo = { 0 };
if (main->getUSBCCableIDInfo(&cableIDInfo))
{
hal->setUSBCCableIDInfo(&cableIDInfo);
}
else
{
hal->setUSBCCableIDInfo(NULL);
}
//
// Check if the panel is eDP and DPCD data for that is already parsed.
// Passing this as a parameter inside notifyHPD to skip reading of DPCD
@@ -6909,6 +6932,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
{
preferredLinkConfig.multistream = false;
}
if (AuxRetry::ack != hal->setMessagingEnable(false, true))
{
DP_PRINTF(DP_WARNING, "DP> Failed to clear messaging for singlestream panel");
@@ -7365,31 +7389,17 @@ void ConnectorImpl::notifyShortPulse()
if (main->isConnectorUSBTypeC() &&
activeLinkConfig.bIs128b132bChannelCoding &&
activeLinkConfig.peakRate > dp2LinkRate_10_0Gbps)
activeLinkConfig.peakRate > dp2LinkRate_10_0Gbps &&
main->isCableVconnSourceUnknown())
{
if (activeLinkConfig.isValid() && enableFlush())
{
if (!this->bDisable5019537Fix)
{
train(originalActiveLinkConfig, true);
}
else
{
train(activeLinkConfig, true);
}
train(originalActiveLinkConfig, true);
disableFlush();
}
if (!this->bDisable5019537Fix)
{
main->invalidateLinkRatesInFallbackTable(originalActiveLinkConfig.peakRate);
hal->overrideCableIdCap(originalActiveLinkConfig.peakRate, false);
}
else
{
main->invalidateLinkRatesInFallbackTable(activeLinkConfig.peakRate);
hal->overrideCableIdCap(activeLinkConfig.peakRate, false);
}
main->invalidateLinkRatesInFallbackTable(originalActiveLinkConfig.peakRate);
hal->overrideCableIdCap(originalActiveLinkConfig.peakRate, false);
highestAssessedLC = getMaxLinkConfig();
@@ -7403,16 +7413,7 @@ void ConnectorImpl::notifyShortPulse()
if (activeLinkConfig.isValid() && enableFlush())
{
bool bTrainSuccess = false;
if (!this->bDisable5019537Fix)
{
bTrainSuccess = train(originalActiveLinkConfig, false);
}
else
{
bTrainSuccess = train(activeLinkConfig, false);
}
if (!bTrainSuccess)
if (!train(originalActiveLinkConfig, false))
{
//
// If original link config could not be restored force
@@ -7907,6 +7908,10 @@ void ConnectorImpl::getCurrentLinkConfig(unsigned & laneCount, NvU64 & linkRate)
main->getLinkConfig(laneCount, linkRate);
}
void ConnectorImpl::getCurrentLinkConfigWithFEC(unsigned & laneCount, NvU64 & linkRate, bool &bFECEnabled)
{
main->getLinkConfigWithFEC(laneCount, linkRate, bFECEnabled);
}
unsigned ConnectorImpl::getPanelDataClockMultiplier()
{
LinkConfiguration linkConfig = getMaxLinkConfig();
@@ -8285,9 +8290,10 @@ void ConnectorImpl::configInit()
bForceClearPendingMsg = false;
allocatedDpTunnelBw = 0;
allocatedDpTunnelBwShadow = 0;
bDP2XPreferNonDSCForLowPClk = false;
bForceHeadShutdownPerMonitor = false;
bDP2XPreferNonDSCForLowPClk = false;
bDisableDscMaxBppLimit = false;
bForceHeadShutdownOnModeTransition = false;
}
bool ConnectorImpl::dpUpdateDscStream(Group *target, NvU32 dscBpp)

150
src/common/displayport/src/dp_connectorimpl2x.cpp
View File

@@ -36,6 +36,18 @@
#include "ctrl/ctrl0073/ctrl0073dp.h"
#include "dp_printf.h"
#define LOGICAL_LANES 4U
#define EFF_BPP_NON_DSC_SCALER 256U
#define EFF_BPP_DSC_SCALER 16U
//
// DP1: 8b/10b, 1 symbol is 8 bits.
// DP2: 128b/132b, 1 symbol is 32 bits.
//
#define DP1_SYMBOL_SIZE 8U
#define DP2_SYMBOL_SIZE 32U
#define GET_SYMBOL_SIZE(bIsDp2xChannelCoding) ((bIsDp2xChannelCoding) ? DP2_SYMBOL_SIZE : DP1_SYMBOL_SIZE)
using namespace DisplayPort;
//
// The regkey value is available in connector, so using a global variable
@@ -63,6 +75,44 @@ void ConnectorImpl2x::applyDP2xRegkeyOverrides()
{
hal->setIgnoreCableIdCaps(true);
}
if (dpRegkeyDatabase.bCableVconnSourceUnknownWar)
{
hal->setCableVconnSourceUnknown();
}
}
bool ConnectorImpl2x::getValidLowestLinkConfig
(
LinkConfiguration &lConfig,
LinkConfiguration &lowestSelected,
ModesetInfo modesetInfo,
const DscParams *pDscParams
)
{
bool bIsModeSupported = ConnectorImpl::getValidLowestLinkConfig(lConfig, lowestSelected, modesetInfo, pDscParams);
bool bAvoidHBR3 = main->isAvoidHBR3WAREnabled() && (lowestSelected.peakRate == dp2LinkRate_8_10Gbps);
unsigned i = 0;
if (!bIsModeSupported || !bAvoidHBR3)
{
return bIsModeSupported;
}
for (i = 0; i < numPossibleLnkCfg; i++)
{
if ((this->allPossibleLinkCfgs[i].lanes != lowestSelected.lanes) ||
(this->allPossibleLinkCfgs[i].peakRate != lowestSelected.peakRate))
{
continue;
}
// check if it's the max possible link
if ((this->allPossibleLinkCfgs[i].lanes != highestAssessedLC.lanes) ||
(this->allPossibleLinkCfgs[i].peakRate != highestAssessedLC.peakRate))
{
// Get next entry.
lowestSelected = this->allPossibleLinkCfgs[i+1];
lowestSelected.enableFEC(lConfig.bEnableFEC);
}
}
return bIsModeSupported;
}
bool ConnectorImpl2x::willLinkSupportModeSST
@@ -130,6 +180,7 @@ bool ConnectorImpl2x::willLinkSupportMode
impParams.linkConfig.bDp2xChannelCoding = linkConfig.bIs128b132bChannelCoding;
impParams.linkConfig.bFECEnabled = linkConfig.bEnableFEC;
impParams.linkConfig.bMultiStreamTopology = linkConfig.multistream;
impParams.linkConfig.bDisableEffBppSST8b10b = this->bDisableEffBppSST8b10b;
if (pDscParams != NULL && pDscParams->forcedParams != NULL)
{
@@ -444,6 +495,26 @@ bool ConnectorImpl2x::compoundQueryAttachMSTGeneric(Group * target,
DscParams *pDscParams, // DSC parameters
DP_IMP_ERROR *pErrorCode)
{
if (!pDscParams || (pDscParams && !pDscParams->bEnableDsc))
{
NvU32 symbolSize = GET_SYMBOL_SIZE(activeLinkConfig.bIs128b132bChannelCoding);
NvU32 hActive = localInfo->localModesetInfo.surfaceWidth;
NvU32 bpp = localInfo->localModesetInfo.depth;
NvU32 bitsPerLane = (NvU32)NV_CEIL(hActive, LOGICAL_LANES) * bpp;
NvU32 totalSymbolsPerLane = (NvU32)NV_CEIL(bitsPerLane, symbolSize);
NvU32 totalSymbols = totalSymbolsPerLane * LOGICAL_LANES;
localInfo->localModesetInfo.depth = (NvU32)NV_CEIL((totalSymbols * symbolSize * EFF_BPP_NON_DSC_SCALER), hActive);
}
else
{
//
// If DSC is enabled bpp will already be multiplied by 16, we need to mulitply by another 16
// to match scalar of 256 which is used in non-DSC case.
//
localInfo->localModesetInfo.depth = localInfo->localModesetInfo.depth * EFF_BPP_DSC_SCALER;
}
// I. Evaluate use of local link bandwidth
// Calculate the PBN required
@@ -640,15 +711,14 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
pixelClockHz, rasterWidth, rasterHeight,
(rasterBlankStartX - rasterBlankEndX), modesetParams.modesetInfo.surfaceHeight,
depth, rasterBlankStartX, rasterBlankEndX, bEnableDsc, modesetParams.modesetInfo.mode,
false, dpColorFormat_YCbCr422_Native);
false, modesetParams.colorFormat);
}
else
{
targetImpl->lastModesetInfo = ModesetInfo(twoChannelAudioHz, eightChannelAudioHz,
pixelClockHz, rasterWidth, rasterHeight,
(rasterBlankStartX - rasterBlankEndX), modesetParams.modesetInfo.surfaceHeight,
depth, rasterBlankStartX, rasterBlankEndX, bEnableDsc, modesetParams.modesetInfo.mode,
false, modesetParams.colorFormat);
depth, rasterBlankStartX, rasterBlankEndX, bEnableDsc, modesetParams.modesetInfo.mode);
}
targetImpl->headIndex = modesetParams.headIndex;
@@ -707,6 +777,24 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
}
}
if (linkUseMultistream())
{
unsigned symbolSize = GET_SYMBOL_SIZE(activeLinkConfig.bIs128b132bChannelCoding);
if (bEnableDsc)
{
targetImpl->lastModesetInfo.depth *= EFF_BPP_DSC_SCALER;
}
else
{
NvU32 bitsPerLane = (NvU32)NV_CEIL(modesetParams.modesetInfo.surfaceWidth, LOGICAL_LANES) * depth;
NvU32 totalSymbolsPerLane = (NvU32)NV_CEIL(bitsPerLane, symbolSize);
NvU32 totalSymbols = totalSymbolsPerLane * LOGICAL_LANES;
targetImpl->lastModesetInfo.depth = (NvU32)NV_CEIL((totalSymbols * symbolSize * EFF_BPP_NON_DSC_SCALER),
modesetParams.modesetInfo.surfaceWidth);
}
}
beforeAddStream(targetImpl);
if (!linkUseMultistream() || main->supportMSAOverMST())
@@ -742,7 +830,20 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
// Move the group to intransistion since we are at the end of notifyAttachBegin
intransitionGroups.insertFront(targetImpl);
if (dev && dev->bApplyPclkWarBug4949066 == true)
{
EvoInterface *provider = ((EvoMainLink *)main)->getProvider();
NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS params = {0};
params.subDeviceInstance = provider->getSubdeviceIndex();
params.head = modesetParams.headIndex;
params.bEnable = NV_TRUE;
NvU32 ret = provider->rmControl0073(NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR, &params, sizeof(params));
if (ret != NVOS_STATUS_SUCCESS)
{
DP_PRINTF(DP_ERROR, "Failed to enable the WAR for bug4949066!");
}
}
bFromResumeToNAB = false;
return bLinkTrainingStatus;
}
@@ -1088,6 +1189,7 @@ void ConnectorImpl2x::beforeDeleteStream(GroupImpl * group, bool forFlushMode)
// Delete the stream
hal->payloadTableClearACT();
hal->payloadAllocate(group->streamIndex, group->timeslot.begin, 0);
main->triggerACT();
}
}
@@ -1103,7 +1205,7 @@ void ConnectorImpl2x::afterDeleteStream(GroupImpl * group)
return ConnectorImpl::afterDeleteStream(group);
DP_ASSERT(!group->isTimeslotAllocated());
main->triggerACT();
if (group->isHeadAttached() && group->bWaitForDeAllocACT)
{
if (!hal->payloadWaitForACTReceived())
@@ -1135,9 +1237,11 @@ bool ConnectorImpl2x::train(const LinkConfiguration &lConfig, bool force, LinkTr
firstFreeSlot = 0;
}
// Invalidate the UHBR if the connector is a USB-C to DP/USB-C.
// Invalidate the UHBR if the connector is a USB-C to DP/USB-C
// and VCONN source is unknown.
if (!trainResult && main->isConnectorUSBTypeC() &&
lConfig.bIs128b132bChannelCoding && lConfig.peakRate > dp2LinkRate_10_0Gbps)
lConfig.bIs128b132bChannelCoding && lConfig.peakRate > dp2LinkRate_10_0Gbps &&
main->isCableVconnSourceUnknown())
{
hal->overrideCableIdCap(lConfig.peakRate, false);
}
@@ -1155,6 +1259,24 @@ void ConnectorImpl2x::notifyDetachBegin(Group *target)
if (!target)
target = firmwareGroup;
Device *newDev = target->enumDevices(0);
DeviceImpl *dev = (DeviceImpl *)newDev;
GroupImpl *group = (GroupImpl*)target;
if (dev != NULL && dev->bApplyPclkWarBug4949066 == true)
{
EvoInterface *provider = ((EvoMainLink *)main)->getProvider();
NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS params = {0};
params.subDeviceInstance = provider->getSubdeviceIndex();
params.head = group->headIndex;
params.bEnable = NV_FALSE;
NvU32 ret = provider->rmControl0073(NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR, &params, sizeof(params));
if (ret != NVOS_STATUS_SUCCESS)
{
DP_PRINTF(DP_ERROR, "Failed to Disable the WAR for bug4949066!");
}
}
return ConnectorImpl::notifyDetachBegin(target);
}
@@ -1368,10 +1490,7 @@ bool ConnectorImpl2x::enableFlush()
}
// Reset activeLinkConfig to indicate the link is now lost
if (!this->bDisable5019537Fix)
{
activeLinkConfig = LinkConfiguration();
}
activeLinkConfig = LinkConfiguration();
return true;
}
@@ -1701,7 +1820,6 @@ void ConnectorImpl2x::handleEdidWARs(Edid & edid, DiscoveryManager::Device & dev
{
// Samsung G9 Monitor is behind internal branch, allocate one more timeslot
bApplyManualTimeslotBug4968411 = true;
bDP2XPreferNonDSCForLowPClk = true;
}
}
@@ -1714,9 +1832,19 @@ void ConnectorImpl2x::handleEdidWARs(Edid & edid, DiscoveryManager::Device & dev
}
}
if (edid.WARFlags.bDP2XPreferNonDSCForLowPClk)
{
bDP2XPreferNonDSCForLowPClk = true;
}
if (edid.WARFlags.bDisableDscMaxBppLimit)
{
bDisableDscMaxBppLimit = true;
}
if (edid.WARFlags.bForceHeadShutdownOnModeTransition)
{
bForceHeadShutdownOnModeTransition = true;
}
}

46
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -96,14 +96,15 @@ const struct
{NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL},
{NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT, &dpRegkeyDatabase.supportInternalUhbrOnFpga, DP_REG_VAL_U32},
{NV_DP2X_IGNORE_CABLE_ID_CAPS, &dpRegkeyDatabase.bIgnoreCableIdCaps, DP_REG_VAL_BOOL},
{NV_DP2X_REGKEY_DISABLE_EFF_BPP_SST_8b10b, &dpRegkeyDatabase.bDisableEffBppSST8b10b, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION, &dpRegkeyDatabase.bForceDisableTunnelBwAllocation, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_DOWNSPREAD, &dpRegkeyDatabase.bDownspreadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_AVOID_HBR3_WAR, &dpRegkeyDatabase.bDisableAvoidHBR3War, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_FIX_FOR_5019537, &dpRegkeyDatabase.bDisable5019537Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FIX_FOR_5147205, &dpRegkeyDatabase.bEnable5147205Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_LOWER_BPP_CHECK_FOR_DSC, &dpRegkeyDatabase.bEnableLowerBppCheckForDsc, DP_REG_VAL_BOOL}
};
@@ -282,11 +283,10 @@ bool EvoMainLink::queryGPUCapability()
_useDfpMaxLinkRateCaps = (dpParams.bOverrideLinkBw == NV_TRUE) ? true : false;
_isLTPhyRepeaterSupported = (dpParams.bIsTrainPhyRepeater == NV_TRUE) ? true : false;
_isDownspreadSupported = (dpParams.bSupportDPDownSpread == NV_TRUE) ? true : false;
_bAvoidHBR3 = (dpParams.bAvoidHBR3 == NV_TRUE) ? true : false;
_gpuSupportedDpVersions = dpParams.dpVersionsSupported;
_minPClkForCompressed = dpParams.minPClkForCompressed;
if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _1_62, dpParams.maxLinkRate))
_maxLinkRateSupportedGpu = dp2LinkRate_1_62Gbps; // in 10Mbps
else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _2_70, dpParams.maxLinkRate))
@@ -917,6 +917,7 @@ void EvoMainLink::applyRegkeyOverrides()
_enableMSAOverrideOverMST = dpRegkeyDatabase.bMsaOverMstEnabled;
_isMSTPCONCapsReadDisabled = dpRegkeyDatabase.bMSTPCONCapsReadDisabled;
_isDownspreadDisabledByRegkey = dpRegkeyDatabase.bDownspreadDisabled;
_bAvoidHBR3DisabledByRegkey = dpRegkeyDatabase.bDisableAvoidHBR3War;
}
NvU32 EvoMainLink::getRegkeyValue(const char *key)
@@ -1348,7 +1349,6 @@ void EvoMainLink::getLinkConfig(unsigned &laneCount, NvU64 & linkRate)
if (code == NVOS_STATUS_SUCCESS)
{
laneCount = params.laneCount;
if (params.linkBW != 0)
{
DP_ASSERT((params.dp2LinkBW == 0) && "dp2LinkBW should be zero if linkBw is not zero");
@@ -1644,6 +1644,42 @@ bool EvoMainLink::getDpLaneData(NvU32 *numLanes, NvU32 *data)
return false;
}
void EvoMainLink::getLinkConfigWithFEC(unsigned &laneCount, NvU64 & linkRate, bool &bFECEnabled)
{
NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS params;
dpMemZero(&params, sizeof(params));
params.subDeviceInstance = subdeviceIndex;
params.displayId = displayId;
NvU32 code = provider->rmControl0073(NV0073_CTRL_CMD_DP_GET_LINK_CONFIG, &params, sizeof(params));
if (code == NVOS_STATUS_SUCCESS)
{
laneCount = params.laneCount;
if (params.bFECEnabled)
{
bFECEnabled = true;
}
if (params.linkBW != 0)
{
DP_ASSERT((params.dp2LinkBW == 0) && "dp2LinkBW should be zero if linkBw is not zero");
linkRate = LINK_RATE_270MHZ_TO_10MHZ((NvU64)params.linkBW);
}
else
{
// No link rate available.
linkRate = 0;
}
}
else
{
laneCount = 0;
linkRate = 0;
}
}
bool EvoMainLink::setDpLaneData(NvU32 numLanes, NvU32 *data)
{
NV0073_CTRL_DP_LANE_DATA_PARAMS params = {0};

41
src/common/displayport/src/dp_evoadapter2x.cpp
View File

@@ -109,6 +109,8 @@ void EvoMainLink2x::applyDP2xRegkeyOverrides()
this->bSupportUHBR2_50 = dpRegkeyDatabase.supportInternalUhbrOnFpga & NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_2_5G;
this->bSupportUHBR2_70 = dpRegkeyDatabase.supportInternalUhbrOnFpga & NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_2_7G;
this->bSupportUHBR5_00 = dpRegkeyDatabase.supportInternalUhbrOnFpga & NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_5_0G;
this->bEnable5147205Fix = dpRegkeyDatabase.bEnable5147205Fix;
this->bCableVconnSourceUnknown = dpRegkeyDatabase.bCableVconnSourceUnknownWar;
}
NvU32 EvoMainLink2x::headToStream(NvU32 head, bool bSidebandMessageSupported,
@@ -452,6 +454,7 @@ bool EvoMainLink2x::train(const LinkConfiguration & link, bool force,
DP2XResetParam resetParam;
dpMemZero(&resetParam, sizeof(resetParam));
resetParam.bForce = force;
resetParam.bSkipLt = bSkipLt;
// Get the original skipFallback setting.
bSkipFallback = requestRmLC.policy.skipFallback();
@@ -521,10 +524,12 @@ bool EvoMainLink2x::train(const LinkConfiguration & link, bool force,
{
if (this->isConnectorUSBTypeC() &&
requestRmLC.bIs128b132bChannelCoding &&
requestRmLC.peakRate > dp2LinkRate_10_0Gbps)
requestRmLC.peakRate > dp2LinkRate_10_0Gbps &&
bCableVconnSourceUnknown)
{
//
// Invalidate the link rate from fallback table if the connector type is USB-C to DP.
// Invalidate the link rate from fallback table if the connector type is USB-C to DP
// and VCONN source is unknown.
// Source will not retry the same link rate if fallback LT fails again.
//
invalidateLinkRatesInFallbackTable(requestRmLC.peakRate);
@@ -1110,6 +1115,11 @@ bool EvoMainLink2x::resetDPRXLink(DP2XResetParam resetParam)
ltRmParams.cmd |= DRF_DEF(0073_CTRL, _DP2X_CMD, _FAKE_LINK_TRAINING, _DONOT_TOGGLE_TRANSMISSION);
}
if (resetParam.bSkipLt && bEnable5147205Fix)
{
ltRmParams.cmd |= DRF_DEF(0073_CTRL, _DP2X_CMD, _SKIP_HW_PROGRAMMING, _YES);
}
switch (resetParam.reason)
{
case DP2X_ResetLinkForPreLT:
@@ -1403,3 +1413,30 @@ bool EvoMainLink2x::physicalLayerSetDP2xTestPattern(DP2xPatternInfo *patternInfo
return (code == NVOS_STATUS_SUCCESS);
}
bool EvoMainLink2x::getUSBCCableIDInfo(NV0073_CTRL_DP_USBC_CABLEID_INFO *cableIDInfo)
{
if (!cableIDInfo)
{
return false;
}
NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS params = { 0 };
// Setup input parameters for RM Control call to get details from PHY
params.subDeviceInstance = this->subdeviceIndex;
params.displayId = this->displayId;
NvU32 code = provider->rmControl0073(NV0073_CTRL_CMD_DP_GET_CABLEID_INFO_FROM_MACRO, &params, sizeof(params));
bool success = (code == NVOS_STATUS_SUCCESS);
if (success)
{
cableIDInfo->uhbr10_0_capable = params.cableIDInfo.uhbr10_0_capable;
cableIDInfo->uhbr13_5_capable = params.cableIDInfo.uhbr13_5_capable;
cableIDInfo->uhbr20_0_capable = params.cableIDInfo.uhbr20_0_capable;
cableIDInfo->type = params.cableIDInfo.type;
cableIDInfo->vconn_source = params.cableIDInfo.vconn_source;
}
return success;
}

11
src/common/displayport/src/dp_linkconfig.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -170,7 +170,14 @@ NvU32 LinkConfiguration::slotsForPBN(NvU32 allocatedPBN, bool usable)
void LinkConfiguration::pbnRequired(const ModesetInfo & modesetInfo, unsigned & base_pbn, unsigned & slots, unsigned & slots_pbn)
{
base_pbn = pbnForMode(modesetInfo);
if (bIs128b132bChannelCoding)
{
base_pbn = pbnForMode(modesetInfo, false);
}
else
{
base_pbn = pbnForMode(modesetInfo, true);
}
if (!bIs128b132bChannelCoding)
{

13
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -600,12 +600,18 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
{
this->WARFlags.bDisableDscMaxBppLimit = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Disable DSC max BPP limit of 16 for DSC.");
}
else if (ProductID == 0x5CA7)
{
this->WARFlags.bForceHeadShutdownOnModeTransition = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Force head shutdown on Mode transition.");
}
break;
case 0xB306:
if (ProductID == 0x3228)
// Gigabyte
case 0x541C:
if (ProductID == 0x3215)
{
// ASUS PG32UQXR does not set DPCD 0x2217 to reflect correct CableID.
// Gigabyte AORUS FO32U2P does not set DPCD 0x2217 to reflect correct CableID.
this->WARFlags.bSkipCableIdCheck = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Panel does not expose cable capability. Ignoring it. Bug 4968411");
}
@@ -629,6 +635,7 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
// Do not allocate manual timeslot when under a separate branch. This is checked with branch OUI.
//
this->WARFlags.bAllocateManualTimeslots = true;
this->WARFlags.bDP2XPreferNonDSCForLowPClk = true;
DP_PRINTF(DP_NOTICE, "DP-WAR> Panel needs allocation of manual timeslot. Bug 4958974");
}
if (ProductID == 0x7256)

39
src/common/displayport/src/dp_watermark.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -838,25 +838,44 @@ bool DisplayPort::isModePossibleMSTWithFEC
return true;
}
unsigned DisplayPort::pbnForMode(const ModesetInfo & modesetInfo)
unsigned DisplayPort::pbnForMode(const ModesetInfo & modesetInfo, bool bAccountSpread)
{
// When DSC is enabled consider depth will multiplied by 16
unsigned dsc_factor = 1;
unsigned bpp_factor;
NvU64 pbn_numerator, pbn_denominator;
if (modesetInfo.bEnableDsc)
{
if(modesetInfo.colorFormat == dpColorFormat_YCbCr422_Native)
if (modesetInfo.depth > 512U)
{
dsc_factor = 32;
bpp_factor = 256U;
}
else
{
dsc_factor = 16;
// Pre-Blackwell, depth will have bppx16
bpp_factor = 16U;
}
}
else
{
if (modesetInfo.depth > 36U)
{
// Blackwell and later, depth will have effectiveBppx256
bpp_factor = 256U;
}
else
{
bpp_factor = 1U;
}
}
unsigned pbnForMode = (NvU32)(divide_ceil(modesetInfo.pixelClockHz * modesetInfo.depth * 1006 * 64 / 8,
(NvU64)54000000 * 1000 * dsc_factor));
pbn_numerator = modesetInfo.pixelClockHz * modesetInfo.depth * 64 / 8;
pbn_denominator = 54000000ULL * bpp_factor;
return pbnForMode;
if (bAccountSpread)
{
pbn_numerator *= 1006;
pbn_denominator *= 1000;
}
return (NvU32)(divide_ceil(pbn_numerator, pbn_denominator));
}

22
src/common/inc/nvBldVer.h
View File

@@ -36,26 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r572_77
#define NV_BUILD_BRANCH r575_92
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r572_77
#define NV_PUBLIC_BRANCH r575_92
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r572_77-389"
#define NV_BUILD_CHANGELIST_NUM (35826456)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r575/r575_92-147"
#define NV_BUILD_CHANGELIST_NUM (35813551)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r570/r572_77-389"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35826456)
#define NV_BUILD_NAME "rel/gpu_drv/r575/r575_92-147"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35813551)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r572_77-4"
#define NV_BUILD_CHANGELIST_NUM (35784913)
#define NV_BUILD_BRANCH_VERSION "r575_92-4"
#define NV_BUILD_CHANGELIST_NUM (35813551)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "572.95"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35784913)
#define NV_BUILD_BRANCH_BASE_VERSION R570
#define NV_BUILD_NAME "575.98"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35813551)
#define NV_BUILD_BRANCH_BASE_VERSION R575
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "570.133.20"
#define NV_VERSION_STRING "575.51.02"
#else

25
src/common/unix/common/utils/interface/nv_smg.h → src/common/inc/nv_mig_types.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -20,8 +20,8 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NV_SMG_H__
#define __NV_SMG_H__
#ifndef __NV_MIG_TYPES_H__
#define __NV_MIG_TYPES_H__
#ifdef __cplusplus
extern "C" {
@@ -29,25 +29,12 @@ extern "C" {
#include "nvtypes.h"
/*
* The simplest required abstraction for accessing RM independent of the
* calling component which may be a kernel module or userspace driver.
*/
typedef NvU32 (*NVSubdevSMGRMControl) (void *ctx, NvU32 object, NvU32 cmd, void *params, NvU32 paramsSize);
typedef NvU32 (*NVSubdevSMGRMAlloc) (void *ctx, NvU32 parent, NvU32 object, NvU32 cls, void *allocParams);
typedef NvU32 (*NVSubdevSMGRMFree) (void *ctx, NvU32 parent, NvU32 object);
typedef NvU32 MIGDeviceId;
NvBool NVSubdevSMGSetPartition(void *ctx,
NvU32 subdevHandle,
const char *computeInstUuid,
NvU32 gpuInstSubscriptionHdl,
NvU32 computeInstSubscriptionHdl,
NVSubdevSMGRMControl rmControl,
NVSubdevSMGRMAlloc rmAlloc,
NVSubdevSMGRMFree rmFree);
#define NO_MIG_DEVICE 0L
#ifdef __cplusplus
}
#endif
#endif /* __NV_SMG_H__ */
#endif /* __NV_MIG_TYPES_H__ */

97
src/common/inc/nv_smg.h Normal file
View File

@@ -0,0 +1,97 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NV_SMG_H__
#define __NV_SMG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#include "nvlimits.h"
#include "nvrmcontext.h"
#include "nv_mig_types.h"
/*
* In the context of SMG a MIG device description is the global identity or
* fingerprint for one MIG device partition that the system has available.
* These are queried through RM and thus they will be the same in
* kernelspace and userspace, and remain immutable and cached for the
* lifetime of the process or kernel module.
*
* For now, the graphics driver does NOT support SMG if the MIG partitions
* change on the fly. RM supports reconfiguring partitions that are not in
* use but, for now, the kernel and userspace graphics drivers expect the
* topology of all physical and MIG devices to remain unchanged throughout
* so that they can agree on the same set of known MIG devices. This is not
* an unreasonable requirement.
*
* Each MIG device description is referred to by a semi-opaque MIGDeviceId.
* The device id is actually the 0-based index to the table of MIG device
* descriptions but with bits flipped so that null value is an invalid
* device. This makes boolean interpretation work more naturally and makes
* structs from calloc() initialize to an invalid device by default.
*/
typedef struct nvMIGDeviceDescriptionRec {
/* The globally unique MIG device ID */
MIGDeviceId migDeviceId;
/* RM sub/device instance of the physical device hosting the MIG device */
NvU32 deviceInstance;
NvU32 subDeviceInstance;
/* These three uniquely identify a particular MIG device */
NvU32 gpuId;
NvU32 gpuInstanceId;
NvU32 computeInstanceId;
/* Whether this device is accessible to the calling process */
NvBool migAccessOk;
/* MIG exec partition UUID string */
char migUuid[NV_MIG_DEVICE_UUID_STR_LENGTH];
} nvMIGDeviceDescription;
NvBool nvSMGSubscribeSubDevToPartition(nvRMContextPtr rmctx,
NvU32 subdevHandle,
MIGDeviceId migDevice,
NvU32 gpuInstSubscriptionHdl,
NvU32 computeInstSubscriptionHdl);
NvU32 nvSMGGetDeviceByUUID(nvRMContextPtr rmctx,
const char *migUuid,
const nvMIGDeviceDescription **uniDev);
NvU32 nvSMGGetDeviceById(nvRMContextPtr rmctx,
MIGDeviceId migDev,
const nvMIGDeviceDescription **uniDev);
NvU32 nvSMGGetDeviceList(nvRMContextPtr rmctx,
nvMIGDeviceDescription **devices,
NvU32 *deviceCount);
NvU32 nvSMGGetDefaultDeviceForDeviceInstance(nvRMContextPtr rmctx,
NvU32 deviceInstance,
const nvMIGDeviceDescription **uniDev);
#ifdef __cplusplus
}
#endif
#endif /* __NV_SMG_H__ */

2
src/common/inc/nvlog_defs.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2012-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

73
src/common/inc/nvrmcontext.h Normal file
View File

@@ -0,0 +1,73 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NVRMCONTEXT_H__
#define __NVRMCONTEXT_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#include "rs_access.h"
/*
* An RM wrapping structure to make RMAPI accessible from the RM abstraction
* in one location/context to other locations/contexts in a unified way.
*
* An nvRMContext can be created on the fly or stored preinitialized in
* objects. It has no mutable state, it's just a collection of static
* parameters to make access to RM possible.
*
* This is a C interface for maximal compatibility, and it is intended to be
* used both in kernel and userspace.
*
*/
typedef struct nvRMContextRec nvRMContext, *nvRMContextPtr;
struct nvRMContextRec {
/*
* The RM client of the calling context. In normal circumstances, the
* callee should pass this as the hClient argument.
*/
NvU32 clientHandle;
/* User data field for the caller: to be freely used. */
void *owner;
/*
* RMAPI function wrappers: it's enough to only fill in those functions
* that the caller will know that will be needed in each case. For now,
* we list function pointers needed by nv_smg.c -- feel free to add more
* RMAPI functions when necessary.
*/
NvU32 (*allocRoot) (nvRMContextPtr rmctx, NvU32 *phClient);
NvU32 (*alloc) (nvRMContextPtr rmctx, NvU32 hClient, NvU32 hParent, NvU32 hObject, NvU32 hClass, void *pAllocParms);
NvU32 (*free) (nvRMContextPtr rmctx, NvU32 hClient, NvU32 hParent, NvU32 hObject);
NvU32 (*control) (nvRMContextPtr rmctx, NvU32 hClient, NvU32 hObject, NvU32 cmd, void *pParams, NvU32 paramsSize);
};
#ifdef __cplusplus
} // extern "C"
#endif
#endif // __NVRMCONTEXT_H__

4
src/common/inc/swref/published/ampere/ga100/dev_fuse.h
View File

@@ -23,6 +23,10 @@
#ifndef __ga100_dev_fuse_h__
#define __ga100_dev_fuse_h__
#define NV_FUSE_FEATURE_READOUT 0x00823814 /* R--4R */
#define NV_FUSE_FEATURE_READOUT_ECC_DRAM 16:16 /* R--VF */
#define NV_FUSE_FEATURE_READOUT_ECC_DRAM_ENABLED 0x00000001 /* R---V */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS 0x0082074C /* RW-4R */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA 0:0 /* RWIVF */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */

3
src/common/inc/swref/published/ampere/ga100/dev_vm.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -128,5 +128,6 @@
#define NV_VIRTUAL_FUNCTION_TIME_0_NSEC 31:5 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_TIME_1 0x30084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_1_NSEC 28:0 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL 0x30090 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH(i) (0x2100+(i)*4) /* RW-4A */
#endif // __ga100_dev_vm_h__

2
src/common/inc/swref/published/ampere/ga10b/dev_ram.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

3
src/common/inc/swref/published/blackwell/gb100/dev_boot_addendum.h
View File

@@ -31,5 +31,8 @@
#define NV_PMC_SCRATCH_RESET_2_CC_DEV_ENABLED 1:1
#define NV_PMC_SCRATCH_RESET_2_CC_DEV_ENABLED_TRUE 0x1
#define NV_PMC_SCRATCH_RESET_2_CC_DEV_ENABLED_FALSE 0x0
#define NV_PMC_SCRATCH_RESET_2_CC_NVLE_MODE_ENABLED 6:6
#define NV_PMC_SCRATCH_RESET_2_CC_NVLE_MODE_ENABLED_TRUE 0x1
#define NV_PMC_SCRATCH_RESET_2_CC_NVLE_MODE_ENABLED_FALSE 0x0
#endif // gb100_dev_boot_addendum_h

2
src/common/inc/swref/published/blackwell/gb100/dev_fsp_pri.h
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@@ -34,4 +34,6 @@
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_MNOC_BASE (0x008f1e00) /* -W-4A */
#endif // __gb100_dev_fsp_pri_h__

79
src/common/inc/swref/published/blackwell/gb100/dev_mnoc_pri_zb.h Normal file
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@@ -0,0 +1,79 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_mnoc_pri_zb_h__
#define __gb100_dev_mnoc_pri_zb_h__
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX(i) (0x00000104 + (i)*0xC) /* RW-4A */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX__SIZE_1 4 /* */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX__PRIV_LEVEL_MASK NV_MNOC_ZB_PRI_SENDMBOX_PRIV_LEVEL_MASK /* */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_MESSAGE_SIZE 19:0 /* R-IVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_MESSAGE_SIZE_INIT 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_MESSAGE_READY 24:24 /* R-IVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_MESSAGE_READY_FALSE 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_MESSAGE_READY_TRUE 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_ERR 25:25 /* R-IVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_ERR_FALSE 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_ERR_TRUE 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_ENABLE 30:30 /* RWIVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_ENABLE_DISABLED 0x00000000 /* RWI-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_STATUS 31:31 /* RWIVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_STATUS__ONWRITE "oneToClear" /* */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_STATUS_CLEARED 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_STATUS_SET 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_STATUS_W1CLR 0x00000001 /* -W--V */
#define NV_MNOC_ZB_PRI_RDATA_0_SENDMBOX(i) (0x00000108 + (i)*0xC) /* R--4A */
#define NV_MNOC_ZB_PRI_RDATA_0_SENDMBOX__SIZE_1 4 /* */
#define NV_MNOC_ZB_PRI_RDATA_0_SENDMBOX__PRIV_LEVEL_MASK NV_MNOC_ZB_PRI_SENDMBOX_PRIV_LEVEL_MASK /* */
#define NV_MNOC_ZB_PRI_RDATA_0_SENDMBOX_RDATA 31:0 /* R-IVF */
#define NV_MNOC_ZB_PRI_RDATA_0_SENDMBOX_RDATA_INIT 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX(i) (0x00000184 + (i)*0xC) /* RW-4A */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX__SIZE_1 4 /* */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX__PRIV_LEVEL_MASK NV_MNOC_ZB_PRI_RECEIVEMBOX_PRIV_LEVEL_MASK /* */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_MESSAGE_SIZE 19:0 /* RWIVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_MESSAGE_SIZE_INIT 0x00000000 /* RWI-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_MESSAGE_TRIGGER 20:20 /* -WXVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_MESSAGE_TRIGGER_SET 0x1 /* -W--V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_RECEIVE_READY 24:24 /* R-IVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_RECEIVE_READY_FALSE 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_RECEIVE_READY_TRUE 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_ERR 25:25 /* R-IVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_ERR_FALSE 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_ERR_TRUE 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_CREDIT_AVAILABLE 26:26 /* R-IVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_CREDIT_AVAILABLE_FALSE 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_CREDIT_AVAILABLE_TRUE 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_ENABLE 30:30 /* RWIVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_ENABLE_DISABLED 0x00000000 /* RWI-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_STATUS 31:31 /* RWIVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_STATUS__ONWRITE "oneToClear" /* */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_STATUS_CLEARED 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_STATUS_SET 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_STATUS_W1CLR 0x00000001 /* -W--V */
#define NV_MNOC_ZB_PRI_WDATA_0_RECEIVEMBOX(i) (0x00000188 + (i)*0xC) /* -W-4A */
#define NV_MNOC_ZB_PRI_WDATA_0_RECEIVEMBOX__SIZE_1 4 /* */
#define NV_MNOC_ZB_PRI_WDATA_0_RECEIVEMBOX__PRIV_LEVEL_MASK NV_MNOC_ZB_PRI_RECEIVEMBOX_PRIV_LEVEL_MASK /* */
#define NV_MNOC_ZB_PRI_WDATA_0_RECEIVEMBOX_WDATA 31:0 /* -WXVF */
#endif // __gb100_dev_mnoc_pri_zb_h__

6
src/common/inc/swref/published/blackwell/gb100/dev_pcfg_pf0.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -90,7 +90,11 @@
#define NV_PF0_DVSEC0_CXL_HEADER_1_DVSEC_VENDOR_ID_DEFAULT 0x00001e98 /* R-I-V */
#define NV_PF0_DVSEC0_CXL_HEADER_1_DVSEC_LENGTH_DEFAULT 0x0000003c /* R-I-V */
#define NV_PF0_DVSEC0_CAPABILITY_HEADER 0x00000af0 /* R--4R */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_1 0x00000af4 /* R--4R */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_1_NV_DVSEC0_LENGTH_DEFAULT 0x0000001c /* R-I-V */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL 0x00000af8 /* R--4R */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL_BAR_FIREWALL_STATUS 20:20 /* R-IVF */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL_BAR_FIREWALL_STATUS_DEFAULT 0x00000001 /* R-I-V */
#define NV_PF0_DVSEC8_CAP_HEADER 0x000003b8 /* R--4R */
#define NV_PF0_DVSEC8_REGISTER_BLOCK_3_REGISTER_OFFSET_HIGH 0x000003d8 /* R--4R */
#define NV_PF0_DVSEC8_HEADER_1_DVSEC_VENDOR_ID_DEFAULT 0x00001e98 /* R-I-V */

30
src/common/inc/swref/published/blackwell/gb100/dev_vm_addendum.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_vm_addendum_h__
#define __gb100_dev_vm_addendum_h__
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT_PTR NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE
#define NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI
#endif // __gb100_dev_vm_addendum_h__

31
src/common/inc/swref/published/blackwell/gb102/dev_vm.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb102_dev_vm_h__
#define __gb102_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4P */
#endif // __gb102_dev_vm_h__

31
src/common/inc/swref/published/blackwell/gb102/dev_vm_addendum.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb102_dev_vm_addendum_h__
#define __gb102_dev_vm_addendum_h__
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT_PTR NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE
#define NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI
#endif // __gb102_dev_vm_addendum_h__

31
src/common/inc/swref/published/blackwell/gb10b/dev_ce_base.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_ce_base_h__
#define __gb10b_dev_ce_base_h__
#define NV_CE_BASE_GRCE_CONFIG__SIZE_1 2
#define NV_CE_BASE_PCE2LCE_CONFIG__SIZE_1 2
#define NV_CE_BASE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#endif // __gb10b_dev_ce_base_h__

31
src/common/inc/swref/published/blackwell/gb110/dev_vm.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb110_dev_vm_h__
#define __gb110_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4P */
#endif // __gb110_dev_vm_h__

31
src/common/inc/swref/published/blackwell/gb110/dev_vm_addendum.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb110_dev_vm_addendum_h__
#define __gb110_dev_vm_addendum_h__
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT_PTR NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE
#define NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI
#endif // __gb110_dev_vm_addendum_h__

31
src/common/inc/swref/published/blackwell/gb112/dev_vm.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb112_dev_vm_h__
#define __gb112_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4P */
#endif // __gb112_dev_vm_h__

31
src/common/inc/swref/published/blackwell/gb112/dev_vm_addendum.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb112_dev_vm_addendum_h__
#define __gb112_dev_vm_addendum_h__
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT_PTR NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE
#define NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI
#endif // __gb112_dev_vm_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_boot_h__
#define __gb20b_dev_boot_h__
#define NV_PMC_SCRATCH_RESET_PLUS_2 0x000005e0 /* RW-4R */
#define NV_PMC_SCRATCH_RESET_PLUS_2__SAFETY "parity" /* */
#define NV_PMC_SCRATCH_RESET_PLUS_2__PRIV_LEVEL_MASK 0x000005e4 /* */
#define NV_PMC_SCRATCH_RESET_PLUS_2_VALUE 31:0 /* RWBVF */
#define NV_PMC_SCRATCH_RESET_PLUS_2_VALUE_INIT 0 /* RWB-V */
#define NV_SYSCTRL_SEC_FAULT 0x3:0x0 /* R---M */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_DCLS 2:2 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_L5_WDT 3:3 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_DCLS 4:4 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_L5_WDT 5:5 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_DCLS 6:6 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_L5_WDT 7:7 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GPMVDD_VMON 8:8 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GPCVDD_VMON 9:9 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SOC2GPU_SEC_FAULT_FUNCTION_LOCKDOWN_REQ 10:10 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUNCTION_LOCKDOWN 11:11 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_DEVICE_LOCKDOWN 12:12 /* R-XUF */
#endif // __gb20b_dev_boot_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_ce_base_h__
#define __gb20b_dev_ce_base_h__
#define NV_CE_BASE_GRCE_CONFIG__SIZE_1 1
#define NV_CE_BASE_PCE2LCE_CONFIG__SIZE_1 2
#define NV_CE_BASE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#endif // __gb20b_dev_ce_base_h__

50
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_mmu_h__
#define __gb20b_dev_mmu_h__
#define NV_MMU_PTE_KIND_INVALID 0x07 /* R---V */
#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY 0x6 /* R---V */
#define NV_MMU_PTE_KIND_Z16 0x1 /* R---V */
#define NV_MMU_PTE_KIND_S8 0x2 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24 0x3 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8 0x4 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8 0x5 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE 0x8 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x9 /* R---V */
#define NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC 0xA /* R---V */
#define NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC 0xB /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC 0xC /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC 0xD /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC 0xE /* R---V */
#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xF /* R---V */
#define NV_MMU_CLIENT_KIND 2:0 /* RWXVF */
#define NV_MMU_CLIENT_KIND_Z16 0x1 /* R---V */
#define NV_MMU_CLIENT_KIND_S8 0x2 /* R---V */
#define NV_MMU_CLIENT_KIND_S8Z24 0x3 /* R---V */
#define NV_MMU_CLIENT_KIND_ZF32_X24S8 0x4 /* R---V */
#define NV_MMU_CLIENT_KIND_Z24S8 0x5 /* R---V */
#define NV_MMU_CLIENT_KIND_GENERIC_MEMORY 0x6 /* R---V */
#define NV_MMU_CLIENT_KIND_INVALID 0x7 /* R---V */
#endif // __gb20b_dev_mmu_h__

30
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_perf_h__
#define __gb20b_dev_perf_h__
#define NV_PERF_PMASYS_CHANNEL_OUTBASE__SIZE_2 2 /* */
#define NV_PERF_PMASYS_CBLOCK_BPC_CONFIG_SECURE__SIZE_1 2 /* */
#endif // __gb20b_dev_perf_h__

62
src/common/inc/swref/published/blackwell/gb20b/dev_sec_pri.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_sec_pri_h__
#define __gb20b_dev_sec_pri_h__
#define NV_PSEC_EMEMC(i) (0x00840ac0+(i)*8) /* RW-4A */
#define NV_PSEC_EMEMC__SIZE_1 8 /* */
#define NV_PSEC_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PSEC_EMEMC_OFFS_INIT 0x00 /* RWI-V */
#define NV_PSEC_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PSEC_EMEMC_BLK_INIT 0x00 /* RWI-V */
#define NV_PSEC_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PSEC_EMEMC_AINCW_INIT 0x0 /* RWI-V */
#define NV_PSEC_EMEMC_AINCW_TRUE 0x1 /* RW--V */
#define NV_PSEC_EMEMC_AINCW_FALSE 0x0 /* RW--V */
#define NV_PSEC_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PSEC_EMEMC_AINCR_INIT 0x0 /* RWI-V */
#define NV_PSEC_EMEMC_AINCR_TRUE 0x1 /* RW--V */
#define NV_PSEC_EMEMC_AINCR_FALSE 0x0 /* RW--V */
#define NV_PSEC_EMEMD(i) (0x00840ac4+(i)*8) /* RW-4A */
#define NV_PSEC_EMEMD__SIZE_1 8 /* */
#define NV_PSEC_EMEMD_DATA 31:0 /* RWXVF */
#define NV_PSEC_QUEUE_HEAD(i) (0x00840c00+(i)*8) /* RW-4A */
#define NV_PSEC_QUEUE_HEAD__SIZE_1 8 /* */
#define NV_PSEC_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
#define NV_PSEC_QUEUE_HEAD_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_PSEC_QUEUE_TAIL(i) (0x00840c04+(i)*8) /* RW-4A */
#define NV_PSEC_QUEUE_TAIL__SIZE_1 8 /* */
#define NV_PSEC_QUEUE_TAIL_ADDRESS 31:0 /* RWIVF */
#define NV_PSEC_QUEUE_TAIL_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_PSEC_MSGQ_HEAD(i) (0x00840c80+(i)*8) /* RW-4A */
#define NV_PSEC_MSGQ_HEAD__SIZE_1 8 /* */
#define NV_PSEC_MSGQ_HEAD_VAL 31:0 /* RWIUF */
#define NV_PSEC_MSGQ_HEAD_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PSEC_MSGQ_TAIL(i) (0x00840c84+(i)*8) /* RW-4A */
#define NV_PSEC_MSGQ_TAIL__SIZE_1 8 /* */
#define NV_PSEC_MSGQ_TAIL_VAL 31:0 /* RWIUF */
#define NV_PSEC_MSGQ_TAIL_VAL_INIT 0x00000000 /* RWI-V */
#endif // __gb20b_dev_sec_pri_h__

36
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_xtl_ep_pcfg_gpu_h__
#define __gb20b_dev_xtl_ep_pcfg_gpu_h__
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC 0x000002B4 /* R--4R */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC__SAFETY "parity" /* */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR 15:0 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR_INIT 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR_OVERRIDEABLE 0 /* */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS 22:16 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS_INIT 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS_OVERRIDEABLE 0 /* */
#endif // __gb20b_dev_xtl_ep_pcfg_gpu_h__

36
src/common/inc/swref/published/blackwell/gb20b/kind_macros.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GB20B_KIND_MACROS_H_INCLUDED
#define GB20B_KIND_MACROS_H_INCLUDED
#define KIND_INVALID(k) ( ((k) ==NV_MMU_CLIENT_KIND_INVALID))
#define PTEKIND_PITCH(k) ( ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define PTEKIND_COMPRESSIBLE(k) ( ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_DISALLOWS_PLC(k) ( !((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE))
#define PTEKIND_SUPPORTED(k) ( ((k) ==NV_MMU_PTE_KIND_INVALID)|| ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_S8Z24)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define KIND_Z(k) ( ((k) >=NV_MMU_CLIENT_KIND_Z16 && (k) <= NV_MMU_CLIENT_KIND_Z24S8))
#define PTEKIND_Z(k) ( ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_Z24S8)|| ((k) >=NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_GENERIC_MEMORY(k) ( ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC))
#endif // GB20B_KIND_MACROS_H_INCLUDED

140
src/common/inc/swref/published/disp/v03_00/dev_disp.h
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#define NV_PDISP_CHN_NUM_WINIM__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_CURS(i) (73+(i)) /* */
#define NV_PDISP_CHN_NUM_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_CHNCTL_CORE 0x006104E0 /* RW-4R */
#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF 9:9 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN 15:15 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS(i) (0x00610604+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN(i) (0x006104E4+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION 1:1 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_CONNECT 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_DISCONNECT 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT 6:6 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP 7:7 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI 8:8 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF 9:9 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA 10:10 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM(i) (0x00610564+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNSTATUS_CORE 0x00610630 /* R--4R */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE 20:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC_LIMBO 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT1 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT2 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_OPERATION 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT1 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT2 0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_OPERATION 0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_UNCONNECTED 0x00000008 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT1 0x00000009 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT2 0x0000000A /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_IDLE 0x0000000B /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_BUSY 0x0000000C /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN1 0x0000000D /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN2 0x0000000E /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS(i) (0x00610784+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE 18:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_IDLE 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_BUSY 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN(i) (0x00610664+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_WIN__SIZE_1 32 /* */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE 19:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT1 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT2 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_IDLE 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_BUSY 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN1 0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN2 0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_UNCONNECTED 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC 31:31 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_IDLE 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM(i) (0x006106E4+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_WINIM__SIZE_1 32 /* */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE 19:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_UNCONNECTED 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT1 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT2 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_IDLE 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_BUSY 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN1 0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN2 0x00000007 /* R---V */
#define NV_PDISP_FE_DEBUG_CTL(i) (0x00610800+(i)*8) /* RW-4A */
#define NV_PDISP_FE_DEBUG_CTL__SIZE_1 73 /* */
#define NV_PDISP_FE_DEBUG_CTL_MODE 0:0 /* RWIVF */
#define NV_PDISP_FE_DEBUG_CTL_MODE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* R---V */
#define NV_PDISP_FE_PBBASE_WIN__SIZE_1 32 /* */
#define NV_PDISP_FE_PBBASE_WINIM__SIZE_1 32 /* */
#define NV_PDISP_FE_SW 0x00640FFF:0x00640000 /* RW--D */
#define NV_PDISP_SF_USER_0 0x006F03FF:0x006F0000 /* RW--D */
#define NV_UDISP_HASH_BASE 0x00000000 /* */

13
src/common/inc/swref/published/disp/v04_01/dev_disp.h
View File

@@ -43,4 +43,17 @@
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING(i) (0x00611C00+(i)*4) /* R--4A */
#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING__SIZE_1 8 /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING(i) (0x00611800+(i)*4) /* RW-4A */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING__SIZE_1 8 /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_INIT 0x00000000 /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_NOT_PENDING 0x00000000 /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_PENDING 0x00000001 /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_RESET 0x00000001 /* */
#endif // __v04_01_dev_disp_h__

6
src/common/inc/swref/published/disp/v05_01/dev_disp.h
View File

@@ -32,12 +32,6 @@
#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_HW 0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_SW 0x00000000 /* -W--V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING(i) (0x00611EF0+(i)*4) /* RW-4A */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_INTR_RETRIGGER(i) (0x00611F30+(i)*4) /* RW-4A */
#define NV_PDISP_FE_INTR_RETRIGGER_TRIGGER 0:0 /* RWIVF */
#define NV_PDISP_FE_INTR_RETRIGGER_TRIGGER_NONE 0x00000000 /* RWI-V */

33
src/common/inc/swref/published/disp/v05_02/dev_disp.h Normal file
View File

@@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __v05_02_dev_disp_h__
#define __v05_02_dev_disp_h__
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING(i) (0x00611EF0+(i)*4) /* RW-4A */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */
#endif

6
src/common/inc/swref/published/nv_arch.h
View File

@@ -108,6 +108,10 @@
#define GPU_IMPLEMENTATION_GB10B 0x0B
#define GPU_IMPLEMENTATION_GB110 0x03
#define GPU_IMPLEMENTATION_GB112 0x04
#define GPU_IMPLEMENTATION_GB202 0x02
#define GPU_IMPLEMENTATION_GB203 0x03
@@ -120,6 +124,8 @@
#define GPU_IMPLEMENTATION_GB207 0x07
#define GPU_IMPLEMENTATION_GB20B 0x0B
#define GPU_IMPLEMENTATION_T124 0x00
#define GPU_IMPLEMENTATION_T132 0x00
#define GPU_IMPLEMENTATION_T210 0x00

30
src/common/inc/swref/published/volta/gv100/dev_graphics_nobundle.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gv100_dev_graphics_nobundle_h__
#define __gv100_dev_graphics_nobundle_h__
#define NV_PGRAPH_PRI_FECS_FEATURE_READOUT 0x00409660 /* R--4R */
#define NV_PGRAPH_PRI_FECS_FEATURE_READOUT_ECC_DRAM 16:16 /* R--VF */
#define NV_PGRAPH_PRI_FECS_FEATURE_READOUT_ECC_DRAM_ENABLED 0x1 /* R---V */
#endif // __gv100_dev_graphics_nobundle_h__

12
src/common/modeset/hdmipacket/nvhdmipkt.c
View File

@@ -54,6 +54,8 @@
#include "class/clc97d.h"
#include "class/clca70.h"
#include "class/clca7d.h"
#include "class/clcb70.h"
#include "class/clcb7d.h"
#include "hdmi_spec.h"
@@ -217,6 +219,16 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] =
NVCA70_DISPLAY, // displayClass
NVCA7D_CORE_CHANNEL_DMA // coreDmaClass
},
[NVHDMIPKT_CB71_CLASS] = {// Index 12==NVHDMIPKT_CB71_CLASS
NVHDMIPKT_CB71_CLASS, // classId
NVHDMIPKT_C971_CLASS, // parentClassId
NV_FALSE, // isRootClass
initializeHdmiPktInterfaceC971, // initInterface
hdmiConstructorC971, // constructor
hdmiDestructorC971, // destructor
NVCB70_DISPLAY, // displayClass
NVCB7D_CORE_CHANNEL_DMA // coreDmaClass
},
};
/********************************** HDMI Library interfaces *************************************/

6
src/common/modeset/hdmipacket/nvhdmipkt.h
View File

@@ -278,8 +278,10 @@ typedef struct _tagNVHDMIPKT_CALLBACK
;
void
(*assert) (NvHdmiPkt_CBHandle handle,
NvBool expression);
(*assert) (const char *expression,
const char *filename,
const char *function,
unsigned int line);
} NVHDMIPKT_CALLBACK;

1
src/common/modeset/hdmipacket/nvhdmipkt_class.h
View File

@@ -51,6 +51,7 @@ typedef enum
NVHDMIPKT_C871_CLASS = 9, // T239
NVHDMIPKT_C971_CLASS = 10, // NVD5.0
NVHDMIPKT_CA71_CLASS = 11,
NVHDMIPKT_CB71_CLASS = 12,
NVHDMIPKT_INVALID_CLASS // Not to be used by client, and always the last entry here.
} NVHDMIPKT_CLASS_ID;

8
src/common/modeset/hdmipacket/nvhdmipkt_common.h
View File

@@ -80,8 +80,12 @@ struct tagNVHDMIPKT_MEM_MAP
// HDMIPKT assert define
#if defined (DEBUG)
#define NvHdmiPkt_AssertP(p, expr) ((p)->callback.assert ? \
(p)->callback.assert((p)->cbHandle, !!(expr)) : 0)
#define NvHdmiPkt_AssertP(p, expr) ((p)->callback.assert && !(expr) ? \
(p)->callback.assert(#expr, \
__FILE__, \
__FUNCTION__, \
__LINE__) \
: 0)
#define NvHdmiPkt_Assert(expr) NvHdmiPkt_AssertP(pThis, expr)
#else
#define NvHdmiPkt_AssertP(p, expr)

149
src/common/modeset/timing/nvt_dsc_pps.c
View File

@@ -2290,6 +2290,65 @@ DSC_GeneratePPSWithSliceCountMask
return NVT_STATUS_SUCCESS;
}
static NvU32
_calculateEffectiveBppForDSC
(
const DSC_INFO *pDscInfo,
const MODESET_INFO *pModesetInfo,
const WAR_DATA *pWARData,
NvU32 bpp
)
{
NvU32 LogicLaneCount, BytePerLogicLane;
NvU32 BitPerSymbol;
NvU32 slicewidth, chunkSize, sliceCount;
NvU32 chunkSymbols, totalSymbolsPerLane;
NvU32 totalSymbols;
if (pWARData->dpData.bIs128b132bChannelCoding)
{
LogicLaneCount = 4U;
BytePerLogicLane = 4U;
BitPerSymbol = 32U;
}
else if (pWARData->dpData.dpMode == DSC_DP_MST)
{
LogicLaneCount = 4U;
BytePerLogicLane = 1U;
BitPerSymbol = 8U;
}
else
{
LogicLaneCount = pWARData->dpData.laneCount;
BytePerLogicLane = 1U;
BitPerSymbol = 8U;
}
//
// Whenever this function is called, we either have forced slice
// width or slice count.
//
if (pDscInfo->forcedDscParams.sliceWidth > 0U)
{
slicewidth = pDscInfo->forcedDscParams.sliceWidth;
sliceCount = (NvU32)NV_CEIL(pModesetInfo->activeWidth, pDscInfo->forcedDscParams.sliceWidth);
}
else
{
slicewidth = (NvU32)NV_CEIL(pModesetInfo->activeWidth, pDscInfo->forcedDscParams.sliceCount);
sliceCount = pDscInfo->forcedDscParams.sliceCount;
}
chunkSize = (NvU32)NV_CEIL((bpp*slicewidth), (8U * BPP_UNIT));
chunkSymbols = (NvU32)NV_CEIL(chunkSize,(LogicLaneCount*BytePerLogicLane));
totalSymbolsPerLane = (chunkSymbols+1)*(sliceCount);
totalSymbols = totalSymbolsPerLane*LogicLaneCount;
bpp = (NvU32)NV_CEIL((totalSymbols*BitPerSymbol*BPP_UNIT),pModesetInfo->activeWidth);
return bpp;
}
/*
* @brief Calculate PPS parameters based on passed down Sink,
* GPU capability and modeset info
@@ -2325,6 +2384,7 @@ DSC_GeneratePPS
DSC_OUTPUT_PARAMS *out = NULL;
DSC_GENERATE_PPS_WORKAREA *pWorkarea = NULL;
NVT_STATUS ret = NVT_STATUS_ERR;
NvU32 eff_bpp = 0U;
if ((!pDscInfo) || (!pModesetInfo) || (!pOpaqueWorkarea) || (!pBitsPerPixelX16))
{
@@ -2404,21 +2464,29 @@ DSC_GeneratePPS
if (pWARData && (pWARData->connectorType == DSC_DP))
{
//
// In DP case, being too close to the available bandwidth caused HW to hang.
// 2 is subtracted based on issues seen in DP CTS testing. Refer to bug 200406501, comment 76
// This limitation is only on DP, not needed for HDMI DSC HW
//
in->bits_per_pixel = (NvU32)((availableBandwidthBitsPerSecond * BPP_UNIT) / pModesetInfo->pixelClockHz) - (BPP_UNIT/8);
if (pWARData->dpData.laneCount == 1U)
if(!in->multi_tile ||
(in->multi_tile && pWARData->dpData.dpMode == DSC_DP_SST
&& !pWARData->dpData.bIs128b132bChannelCoding
&& pWARData->dpData.bDisableEffBppSST8b10b
))
{
//
// SOR lane fifo might get overflown when DP 1 lane, FEC enabled and pclk*bpp > 96%*linkclk*8 i.e.
// DSC stream is consuming more than 96% of the total bandwidth. Use lower bits per pixel. Refer Bug 200561864.
// In DP case, being too close to the available bandwidth caused HW to hang.
// 2 is subtracted based on issues seen in DP CTS testing. Refer to bug 200406501, comment 76
// This limitation is only on DP, not needed for HDMI DSC HW
//
in->bits_per_pixel = (NvU32)((96U * availableBandwidthBitsPerSecond * BPP_UNIT) / (100U * pModesetInfo->pixelClockHz)) -
(BPP_UNIT / 8U);
in->bits_per_pixel = (NvU32)((availableBandwidthBitsPerSecond * BPP_UNIT) / pModesetInfo->pixelClockHz) - (BPP_UNIT/8);
if (pWARData->dpData.laneCount == 1U)
{
//
// SOR lane fifo might get overflown when DP 1 lane, FEC enabled and pclk*bpp > 96%*linkclk*8 i.e.
// DSC stream is consuming more than 96% of the total bandwidth. Use lower bits per pixel. Refer Bug 200561864.
//
in->bits_per_pixel = (NvU32)((96U * availableBandwidthBitsPerSecond * BPP_UNIT) / (100U * pModesetInfo->pixelClockHz)) -
(BPP_UNIT / 8U);
}
}
if ((pWARData->dpData.dpMode == DSC_DP_SST) && (pWARData->dpData.hBlank < 100U))
@@ -2499,6 +2567,33 @@ DSC_GeneratePPS
in->bits_per_pixel = DSC_AlignDownForBppPrecision(in->bits_per_pixel, pDscInfo->sinkCaps.bitsPerPixelPrecision);
if (pWARData && (pWARData->connectorType == DSC_DP) && in->multi_tile)
{
//
// EffectiveBpp should be used only from Blackwell, so keeping
// multi-tile check to restrict it from Blackwell.
//
if ((!pWARData->dpData.bDisableEffBppSST8b10b) ||
(pWARData->dpData.bDisableEffBppSST8b10b &&
((pWARData->dpData.dpMode == DSC_DP_MST) ||
pWARData->dpData.bIs128b132bChannelCoding)))
{
unsigned max_bpp = in->bits_per_pixel + 1;
// Algorithm in bug 5004872
do
{
max_bpp--;
eff_bpp = _calculateEffectiveBppForDSC(pDscInfo, pModesetInfo, pWARData, max_bpp);
} while ((eff_bpp * (pModesetInfo->pixelClockHz)) > (availableBandwidthBitsPerSecond*BPP_UNIT));
in->bits_per_pixel = max_bpp;
in->bits_per_pixel = DSC_AlignDownForBppPrecision(in->bits_per_pixel, pDscInfo->sinkCaps.bitsPerPixelPrecision);
}
}
// If user specified bits_per_pixel value to be used check if it is valid one
if (*pBitsPerPixelX16 != 0)
{
@@ -2522,6 +2617,17 @@ DSC_GeneratePPS
in->bits_per_pixel = *pBitsPerPixelX16;
}
if (pWARData && (pWARData->connectorType == DSC_DP) && in->multi_tile)
{
if ((!pWARData->dpData.bDisableEffBppSST8b10b) ||
(pWARData->dpData.bDisableEffBppSST8b10b &&
((pWARData->dpData.dpMode == DSC_DP_MST) ||
pWARData->dpData.bIs128b132bChannelCoding)))
{
eff_bpp = _calculateEffectiveBppForDSC(pDscInfo, pModesetInfo, pWARData, in->bits_per_pixel);
}
}
//
// For DSC Dual Mode or Multi-tile configs (NVD 5.0 and later),
// because of architectural limitation we can't use bits_per_pixel
@@ -2570,6 +2676,18 @@ DSC_GeneratePPS
// WARNING - Optimal bits per pixel value calculated is greater than what DSC decompressor can support. Forcing it to max that decompressor can support
in->bits_per_pixel = pDscInfo->sinkCaps.maxBitsPerPixelX16;
}
if (pWARData && (pWARData->connectorType == DSC_DP) && in->multi_tile)
{
if ((!pWARData->dpData.bDisableEffBppSST8b10b) ||
(pWARData->dpData.bDisableEffBppSST8b10b &&
((pWARData->dpData.dpMode == DSC_DP_MST) ||
pWARData->dpData.bIs128b132bChannelCoding)))
{
eff_bpp = _calculateEffectiveBppForDSC(pDscInfo, pModesetInfo, pWARData, in->bits_per_pixel);
}
}
}
if (pModesetInfo->bDualMode && (pDscInfo->gpuCaps.maxNumHztSlices > 4U))
@@ -2630,7 +2748,14 @@ DSC_GeneratePPS
ret = DSC_PpsDataGen(in, out, pps);
*pBitsPerPixelX16 = in->bits_per_pixel;
if (in->multi_tile && eff_bpp)
{
*pBitsPerPixelX16 = eff_bpp;
}
else
{
*pBitsPerPixelX16 = in->bits_per_pixel;
}
/* fall through */
done:

1
src/common/modeset/timing/nvt_dsc_pps.h
View File

@@ -256,6 +256,7 @@ typedef struct
NvBool bIsEdp;
NvBool bDisableDscMaxBppLimit;
NvBool bIs128b132bChannelCoding;
NvBool bDisableEffBppSST8b10b;
}dpData;
} WAR_DATA;

3
src/common/nvlink/inband/interface/nvlink_inband_msg.h
View File

@@ -157,7 +157,8 @@ typedef struct
NvU32 fabricHealthMask; /* Mask containing bits indicating various fabric health parameters */
NvU32 gpaAddressEGMHi; /* GPA Address for EGM. Don't use if EGM support is not present in GFM */
NvU8 maxRbmLinks; /* Max RBM mode supported */
NvU8 reserved[15]; /* For future use. Must be initialized to zero */
NvU32 remapTableIdx; /* remap table index for the GPU */
NvU8 reserved[11]; /* For future use. Must be initialized to zero */
} nvlink_inband_gpu_probe_rsp_t;
typedef struct

65
src/common/nvswitch/common/inc/soe/soeifcore.h
View File

@@ -126,6 +126,11 @@ enum
*/
RM_SOE_CORE_CMD_ISSUE_INGRESS_STOP = 0x10,
/*
* Issue engine interrupt counter clear
*/
RM_SOE_CORE_CMD_ISSUE_ENGINE_INTR_COUNTER_CLEAR = 0x11,
/*
* Enable ERROR reporting
*/
@@ -283,11 +288,14 @@ typedef enum
RM_SOE_CORE_ENGINE_ID_NPORT,
RM_SOE_CORE_ENGINE_ID_NVLIPT,
RM_SOE_CORE_ENGINE_ID_NVLIPT_LNK,
RM_SOE_CORE_ENGINE_ID_NVLTLC
}RM_SOE_CORE_ENGINE_ID;
RM_SOE_CORE_ENGINE_ID_NVLTLC,
RM_SOE_CORE_ENGINE_ID_NXBAR_TILE,
RM_SOE_CORE_ENGINE_ID_NXBAR_TILEOUT
} RM_SOE_CORE_ENGINE_ID;
typedef enum
{
// NPORT
RM_SOE_CORE_NPORT_ROUTE_ERR_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_ROUTE_ERR_NON_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_INGRESS_ERR_FATAL_REPORT_EN_0,
@@ -304,18 +312,64 @@ typedef enum
RM_SOE_CORE_NPORT_MULTICASTTSTATE_ERR_NON_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_MULTICASTTSTATE_ERR_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_REDUCTIONTSTATE_ERR_NON_FATAL_REPORT_EN_0,
RM_SOE_CORE_NPORT_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0
}RM_SOE_CORE_NPORT_REPORT_EN_REGISTER;
RM_SOE_CORE_NPORT_REDUCTIONTSTATE_ERR_FATAL_REPORT_EN_0,
// NXBAR
RM_SOE_CORE_NXBAR_TILE_ERR_FATAL_INTR_EN,
RM_SOE_CORE_NXBAR_TILEOUT_ERR_FATAL_INTR_EN
} RM_SOE_CORE_ENGINE_REPORT_EN_REGISTER;
typedef struct
{
NvU8 cmdType;
RM_SOE_CORE_ENGINE_ID engId;
NvU32 engInstance;
RM_SOE_CORE_NPORT_REPORT_EN_REGISTER reg;
RM_SOE_CORE_ENGINE_REPORT_EN_REGISTER reg;
NvU32 data;
} RM_SOE_CORE_CMD_ERROR_REPORT_EN;
/*
* ENGINE Interrupt Counter Types
*/
typedef enum
{
RM_SOE_CORE_EGRESS_ERR_NXBAR_ECC_ERROR_COUNTER,
RM_SOE_CORE_EGRESS_ERR_NXBAR_REDUCTION_ECC_ERROR_COUNTER,
RM_SOE_CORE_EGRESS_ERR_RAM_OUT_ECC_ERROR_COUNTER,
RM_SOE_CORE_EGRESS_ERR_MCRSPCTRLSTORE_ECC_ERROR_COUNTER,
RM_SOE_CORE_EGRESS_ERR_RBCTRLSTORE_ECC_ERROR_COUNTER,
RM_SOE_CORE_EGRESS_ERR_MCREDSGT_ECC_ERROR_COUNTER,
RM_SOE_CORE_EGRESS_ERR_MCREDBUF_ECC_ERROR_COUNTER,
RM_SOE_CORE_EGRESS_ERR_MCRSP_RAM_ECC_ERROR_COUNTER,
RM_SOE_CORE_INGRESS_ERR_REMAPTAB_ECC_ERROR_COUNTER,
RM_SOE_CORE_INGRESS_ERR_RIDTAB_ECC_ERROR_COUNTER,
RM_SOE_CORE_INGRESS_ERR_RLANTAB_ECC_ERROR_COUNTER,
RM_SOE_CORE_INGRESS_ERR_NCISOC_HDR_ECC_ERROR_COUNTER,
RM_SOE_CORE_INGRESS_ERR_EXTAREMAPTAB_ECC_ERROR_COUNTER,
RM_SOE_CORE_INGRESS_ERR_EXTBREMAPTAB_ECC_ERROR_COUNTER,
RM_SOE_CORE_INGRESS_ERR_MCREMAPTAB_ECC_ERROR_COUNTER,
RM_SOE_CORE_MULTICASTTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER,
RM_SOE_CORE_MULTICASTTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER,
RM_SOE_CORE_REDUCTIONTSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER,
RM_SOE_CORE_REDUCTIONTSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER,
RM_SOE_CORE_ROUTE_ERR_NVS_ECC_ERROR_COUNTER,
RM_SOE_CORE_ROUTE_ERR_GLT_ECC_ERROR_COUNTER,
RM_SOE_CORE_ROUTE_ERR_MCRID_ECC_ERROR_COUNTER,
RM_SOE_CORE_ROUTE_ERR_EXTMCRID_ECC_ERROR_COUNTER,
RM_SOE_CORE_ROUTE_ERR_RAM_ECC_ERROR_COUNTER,
RM_SOE_CORE_SOURCETRACK_ERR_CREQ_TCEN0_CRUMBSTORE_ECC_ERROR_COUNTER,
RM_SOE_CORE_TSTATE_ERR_CRUMBSTORE_ECC_ERROR_COUNTER,
RM_SOE_CORE_TSTATE_ERR_TAGPOOL_ECC_ERROR_COUNTER
} RM_SOE_CORE_ENGINE_INTR_COUNTER_TYPE;
typedef struct
{
NvU8 cmdType;
RM_SOE_CORE_ENGINE_ID engId;
RM_SOE_CORE_ENGINE_INTR_COUNTER_TYPE engineIntrType;
NvU32 instance;
} RM_SOE_CORE_CMD_ENGINE_INTR_COUNTER;
typedef union
{
NvU8 cmdType;
@@ -336,6 +390,7 @@ typedef union
RM_SOE_CORE_CMD_NPORT_FATAL_INTR nportDisableIntr;
RM_SOE_CORE_CMD_INGRESS_STOP ingressStop;
RM_SOE_CORE_CMD_ERROR_REPORT_EN enableErrorReport;
RM_SOE_CORE_CMD_ENGINE_INTR_COUNTER engineClearIntrCounter;
} RM_SOE_CORE_CMD;
typedef struct

13
src/common/nvswitch/interface/export_nvswitch.h
View File

@@ -665,6 +665,19 @@ nvswitch_os_print
...
);
/*
* Log the given error code via an OS-specifric programmatic API
*/
void
NVSWITCH_PRINT_ATTRIB(3, 4)
nvswitch_os_report_error
(
void *os_handle,
NvU32 error_code,
const char *fmt,
...
);
/*
* "Registry" interface for dword
*/

4
src/common/nvswitch/kernel/flcn/flcn_call_hal_nvswitch.c
View File

@@ -110,7 +110,7 @@ flcnQueueCmdPostBlocking
if (status != NV_OK)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE,
"Fatal, Failed to post command to SOE. Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n",
"Failed to post command to SOE. Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n",
pCmd->cmdGen.hdr.unitId, pCmd->cmdGen.hdr.size, pCmd->cmdGen.hdr.ctrlFlags,
pCmd->cmdGen.hdr.seqNumId, pCmd->cmdGen.cmd, (NvU8)pCmd->cmdGen.cmd);
@@ -121,7 +121,7 @@ flcnQueueCmdPostBlocking
if (status == NV_ERR_TIMEOUT)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_TIMEOUT,
"Fatal, Timed out while waiting for SOE command completion. Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n",
"Timed out while waiting for SOE command completion. Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n",
pCmd->cmdGen.hdr.unitId, pCmd->cmdGen.hdr.size, pCmd->cmdGen.hdr.ctrlFlags,
pCmd->cmdGen.hdr.seqNumId, pCmd->cmdGen.cmd, (NvU8)pCmd->cmdGen.cmd);
flcnQueueCmdCancel(device, pFlcn, *pSeqDesc);

4
src/common/nvswitch/kernel/inc/common_nvswitch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -163,6 +163,7 @@ void nvswitch_assert_log(void);
"nvidia-%s: SXid (PCI:" NVLINK_PCI_DEV_FMT "): %05d, " _fmt, \
(_d)->name, NVLINK_PCI_DEV_FMT_ARGS(&(_d)->nvlink_device->pciInfo), _sxid, \
##__VA_ARGS__); \
nvswitch_os_report_error(_d->os_handle, _sxid, _fmt, ##__VA_ARGS__); \
nvswitch_lib_smbpbi_log_sxid(_d, _sxid, _fmt, ##__VA_ARGS__); \
nvswitch_inforom_bbx_add_sxid(_d, _sxid, 0, 0, 0); \
} while(0)
@@ -175,6 +176,7 @@ void nvswitch_assert_log(void);
"nvidia-%s: SXid (PCI:" NVLINK_PCI_DEV_FMT "): %05d, " _fmt, \
(_d)->name, NVLINK_PCI_DEV_FMT_ARGS(&(_d)->nvlink_device->pciInfo), _sxid, \
##__VA_ARGS__); \
nvswitch_os_report_error(_d->os_handle, _sxid, _fmt, ##__VA_ARGS__); \
nvswitch_lib_smbpbi_log_sxid(_d, _sxid, _fmt, ##__VA_ARGS__); \
} while(0)

4
src/common/nvswitch/kernel/inc/ls10/ls10.h
View File

@@ -191,7 +191,9 @@
#define SOE_VBIOS_REVLOCK_ISSUE_INGRESS_STOP 0x4C0000
#define SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND 0x590000
#define SOE_VBIOS_REVLOCK_SOE_PRI_CHECKS 0x610000
#define SOE_VBIOS_REVLOCK_REPORT_EN 0x700000
#define SOE_VBIOS_REVLOCK_REPORT_EN 0x6A0000
#define SOE_VBIOS_REVLOCK_ENGINE_COUNTERS 0x700000
// LS10 Saved LED state
#define ACCESS_LINK_LED_STATE CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED

3
src/common/nvswitch/kernel/inc/ls10/soe_ls10.h
View File

@@ -51,7 +51,8 @@ NvlStatus nvswitch_soe_set_nport_interrupts_ls10(nvswitch_device *device, NvU32
void nvswitch_soe_disable_nport_fatal_interrupts_ls10(nvswitch_device *device, NvU32 nport,
NvU32 nportIntrEnable, NvU8 nportIntrType);
NvlStatus nvswitch_soe_issue_ingress_stop_ls10(nvswitch_device *device, NvU32 nport, NvBool bStop);
NvlStatus nvswitch_soe_update_intr_report_en_ls10(nvswitch_device *device, RM_SOE_CORE_ENGINE_ID eng_id, NvU32 eng_instance, RM_SOE_CORE_NPORT_REPORT_EN_REGISTER reg, NvU32 data);
NvlStatus nvswitch_soe_update_intr_report_en_ls10(nvswitch_device *device, RM_SOE_CORE_ENGINE_ID eng_id, NvU32 eng_instance, RM_SOE_CORE_ENGINE_REPORT_EN_REGISTER reg, NvU32 data);
NvlStatus nvswitch_soe_clear_engine_interrupt_counter_ls10(nvswitch_device *device, RM_SOE_CORE_ENGINE_ID eng_id, RM_SOE_CORE_ENGINE_INTR_COUNTER_TYPE engineIntrType, NvU32 instance);
NvlStatus nvswitch_soe_reg_wr_32_ls10(nvswitch_device *device, NvU32 offset, NvU32 data);
NvlStatus nvswitch_soe_eng_wr_32_ls10(nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast, NvU32 eng_instance, NvU32 base_addr, NvU32 offset, NvU32 data);
#endif //_SOE_LS10_H_

1020
src/common/nvswitch/kernel/ls10/intr_ls10.c
View File

File diff suppressed because it is too large Load Diff

81
src/common/nvswitch/kernel/ls10/soe_ls10.c
View File

@@ -666,6 +666,83 @@ nvswitch_soe_issue_ingress_stop_ls10
return NVL_SUCCESS;
}
/*
* @Brief : Clear Engine Interrupt Counter in SOE
*
* @param[in] device
* @param[in] eng_id
* @param[in] engineIntrType
* @param[in] instance
*/
NvlStatus
nvswitch_soe_clear_engine_interrupt_counter_ls10
(
nvswitch_device *device,
RM_SOE_CORE_ENGINE_ID eng_id,
RM_SOE_CORE_ENGINE_INTR_COUNTER_TYPE engineIntrType,
NvU32 instance
)
{
FLCN *pFlcn;
NvU32 cmdSeqDesc = 0;
NV_STATUS status;
RM_FLCN_CMD_SOE cmd;
NVSWITCH_TIMEOUT timeout;
RM_SOE_CORE_CMD_ENGINE_INTR_COUNTER *pEngineClearIntrCounter;
NVSWITCH_GET_BIOS_INFO_PARAMS params = { 0 };
if (!nvswitch_is_soe_supported(device))
{
NVSWITCH_PRINT(device, INFO,
"%s: SOE is not supported\n",
__FUNCTION__);
return NVL_SUCCESS; // -NVL_ERR_NOT_SUPPORTED
}
status = device->hal.nvswitch_ctrl_get_bios_info(device, &params);
if ((status != NVL_SUCCESS) || ((params.version & SOE_VBIOS_VERSION_MASK) <
SOE_VBIOS_REVLOCK_ENGINE_COUNTERS))
{
NVSWITCH_PRINT(device, INFO,
"%s: Skipping clearing Engine Interrupt Counter and disabiling NVLW interrupt. Update firmware "
"from .%02X to .%02X\n",
__FUNCTION__, (NvU32)((params.version & SOE_VBIOS_VERSION_MASK) >> 16),
SOE_VBIOS_REVLOCK_ENGINE_COUNTERS);
return NVL_SUCCESS; // -NVL_ERR_NOT_SUPPORTED
}
pFlcn = device->pSoe->pFlcn;
nvswitch_os_memset(&cmd, 0, sizeof(cmd));
cmd.hdr.unitId = RM_SOE_UNIT_CORE;
cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, ENGINE_INTR_COUNTER);
pEngineClearIntrCounter = &cmd.cmd.core.engineClearIntrCounter;
pEngineClearIntrCounter->cmdType = RM_SOE_CORE_CMD_ISSUE_ENGINE_INTR_COUNTER_CLEAR;
pEngineClearIntrCounter->engId = eng_id;
pEngineClearIntrCounter->engineIntrType = engineIntrType;
pEngineClearIntrCounter->instance = instance;
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&cmd,
NULL, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to send clear Engine Interrupt Counter command to SOE, status 0x%x\n",
__FUNCTION__, status);
return -NVL_ERR_GENERIC;
}
return NVL_SUCCESS;
}
/*
* @Brief : Perform register writes in SOE during TNVL
*
@@ -681,7 +758,7 @@ nvswitch_soe_update_intr_report_en_ls10
nvswitch_device *device,
RM_SOE_CORE_ENGINE_ID eng_id,
NvU32 eng_instance,
RM_SOE_CORE_NPORT_REPORT_EN_REGISTER reg,
RM_SOE_CORE_ENGINE_REPORT_EN_REGISTER reg,
NvU32 data
)
{
@@ -723,7 +800,7 @@ nvswitch_soe_update_intr_report_en_ls10
pErrorReportEnable = &cmd.cmd.core.enableErrorReport;
pErrorReportEnable->cmdType = RM_SOE_CORE_CMD_UPDATE_INTR_REPORT_EN;
pErrorReportEnable->engId = RM_SOE_CORE_ENGINE_ID_NPORT;
pErrorReportEnable->engId = eng_id;
pErrorReportEnable->engInstance = eng_instance;
pErrorReportEnable->reg = reg;
pErrorReportEnable->data = data;

8
src/common/nvswitch/kernel/ls10/tnvl_ls10.c
View File

@@ -1250,14 +1250,6 @@ nvswitch_tnvl_disable_interrupts_ls10
nvswitch_device *device
)
{
if (!nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_TNVL_ERROR,
"Failed to disable non-fatal/legacy interrupts. TNVL mode is not enabled\n");
return;
}
//
// In TNVL locked disable non-fatal NVLW, NPG, and legacy interrupt,
// disable additional non-fatals on those partitions.

4
src/common/nvswitch/kernel/smbpbi_nvswitch.c
View File

@@ -89,10 +89,10 @@ nvswitch_smbpbi_post_init
if (status == NVL_SUCCESS)
{
#if defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS)
#if defined(DEBUG) || defined(DEVELOP)
nvswitch_lib_smbpbi_log_sxid(device, NVSWITCH_ERR_NO_ERROR,
"NVSWITCH SMBPBI server is online.");
#endif // defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS)
#endif // defined(DEBUG) || defined(DEVELOP)
NVSWITCH_PRINT(device, INFO, "%s: SMBPBI POST INIT completed\n", __FUNCTION__);
}

8
src/common/sdk/nvidia/inc/class/cl0000_notification.h
View File

@@ -28,14 +28,6 @@
extern "C" {
#endif
/*event values*/
#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0)
#define NV0000_NOTIFIERS_EVENT_NONE_PENDING (1)
#define NV0000_NOTIFIERS_GPU_UNBIND_EVENT (2)
#define NV0000_NOTIFIERS_GPU_BIND_EVENT (3)
#define NV0000_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (4)
#define NV0000_NOTIFIERS_MAXCOUNT (5)
/*Status definitions for NV0000_NOTIFIERS_DISPLAY_CHANGE event*/
#define NV0000_NOTIFIERS_STATUS_ACPI_DISPLAY_DEVICE_CYCLE (0)

3
src/common/sdk/nvidia/inc/class/cl0073.h
View File

@@ -33,7 +33,8 @@ extern "C" {
/* event values */
#define NV0073_NOTIFIERS_SW (0)
#define NV0073_NOTIFIERS_MAXCOUNT (5)
#define NV0073_NOTIFIERS_LTM_CALC_TIMEOUT (5)
#define NV0073_NOTIFIERS_MAXCOUNT (6)
#define NV0073_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)

83
src/common/sdk/nvidia/inc/class/cl00de.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -52,10 +52,11 @@ extern "C" {
if (!RUSD_SEQ_DATA_VALID(RUSD_SEQ)) \
continue;
#define RUSD_SEQ_CHECK2(dataField) \
portAtomicMemoryFenceLoad(); \
if (RUSD_SEQ == (dataField)->lastModifiedTimestamp) \
break;
// Clear lastModifiedTimestamp on failure in case of reaching loop limit
#define RUSD_SEQ_CHECK2(dataField) \
portAtomicMemoryFenceLoad(); \
if (RUSD_SEQ == (dataField)->lastModifiedTimestamp) \
break; \
//
// Read RUSD data field `dataField` from NV00DE_SHARED_DATA struct `pSharedData` into destination pointer `pDst`
@@ -70,6 +71,7 @@ do {
RUSD_SEQ_CHECK1(&((pSharedData)->dataField)); \
portMemCopy((pDst), sizeof(*pDst), &((pSharedData)->dataField), sizeof(*pDst)); \
RUSD_SEQ_CHECK2(&((pSharedData)->dataField)); \
(pDst)->lastModifiedTimestamp = RUSD_TIMESTAMP_INVALID; \
} \
} while(0);
@@ -164,10 +166,32 @@ typedef struct RUSD_PERF_CURRENT_PSTATE {
NvU32 currentPstate;
} RUSD_PERF_CURRENT_PSTATE;
typedef struct RUSD_CLK_THROTTLE_REASON {
#define RUSD_CLK_VIOLATION_NUM 32
#define RUSD_PERF_POINT_MAX_CLOCK 0
#define RUSD_PERF_POINT_TURBO_BOOST 1
#define RUSD_PERF_POINT_3D_BOOST 2
#define RUSD_PERF_POINT_RATED_TDP 3
#define RUSD_PERF_POINT_MAX_CUSTOMER_BOOST 4
#define RUSD_PERF_POINT_DISPLAY_CLOCK_INTERSECT 5
#define RUSD_PERF_POINT_NUM 6
typedef struct RUSD_CLK_VIOLATION_STATUS {
NvU32 perfPointMask;
NvU64 timeNs[RUSD_PERF_POINT_NUM];
} RUSD_CLK_VIOLATION_STATUS;
typedef struct RUSD_CLK_THROTTLE_INFO {
volatile NvU64 lastModifiedTimestamp;
NvU32 reasonMask; // Bitmask of RUSD_CLK_THROTTLE_REASON_*
} RUSD_CLK_THROTTLE_REASON;
NvU64 referenceTimeNs;
NvU32 supportedViolationTimeMask;
RUSD_CLK_VIOLATION_STATUS violation[RUSD_CLK_VIOLATION_NUM];
RUSD_CLK_VIOLATION_STATUS globalViolation;
} RUSD_CLK_THROTTLE_INFO;
typedef struct RUSD_CLK_THROTTLE_INFO RUSD_CLK_THROTTLE_REASON;
typedef struct RUSD_MEM_ERROR_COUNTS {
NvU64 correctedVolatile;
@@ -197,8 +221,21 @@ typedef struct RUSD_POWER_LIMITS {
RUSD_POWER_LIMIT_INFO info;
} RUSD_POWER_LIMITS;
typedef enum RUSD_TEMPERATURE_SENSOR {
RUSD_TEMPERATURE_SENSOR_GPU,
RUSD_TEMPERATURE_SENSOR_MEMORY,
RUSD_TEMPERATURE_SENSOR_BOARD,
RUSD_TEMPERATURE_SENSOR_POWER_SUPPLY,
// Should always be last entry
RUSD_TEMPERATURE_SENSOR_MAX
} RUSD_TEMPERATURE_SENSOR;
typedef enum RUSD_TEMPERATURE_TYPE {
RUSD_TEMPERATURE_TYPE_GPU,
RUSD_TEMPERATURE_TYPE_MEMORY,
RUSD_TEMPERATURE_TYPE_BOARD,
RUSD_TEMPERATURE_TYPE_POWER_SUPPLY,
RUSD_TEMPERATURE_TYPE_HBM,
RUSD_TEMPERATURE_TYPE_MAX
} RUSD_TEMPERATURE_TYPE;
@@ -208,9 +245,6 @@ typedef struct RUSD_TEMPERATURE {
NvTemp temperature;
} RUSD_TEMPERATURE;
// Temporary until clients can migrate to using RUSD_TEMPERATURE type name
typedef RUSD_TEMPERATURE RUSD_TEMPERATURE_GENERIC;
typedef struct RUSD_MEM_ROW_REMAP_INFO {
// Provided from NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM
NvU32 histogramMax; // No remapped row is used.
@@ -252,6 +286,26 @@ typedef struct RUSD_INST_POWER_USAGE {
RUSD_INST_POWER_INFO info;
} RUSD_INST_POWER_USAGE;
typedef struct RUSD_POWER_POLICY_STATUS_INFO {
NvU32 tgpmW; // Total GPU power in mW
} RUSD_POWER_POLICY_STATUS_INFO;
typedef struct RUSD_POWER_POLICY_STATUS {
volatile NvU64 lastModifiedTimestamp;
RUSD_POWER_POLICY_STATUS_INFO info;
} RUSD_POWER_POLICY_STATUS;
#define RUSD_FAN_COOLER_MAX_COOLERS 16U
typedef struct RUSD_FAN_COOLER_INFO {
NvU32 rpmCurr[RUSD_FAN_COOLER_MAX_COOLERS];
} RUSD_FAN_COOLER_INFO;
typedef struct RUSD_FAN_COOLER_STATUS {
volatile NvU64 lastModifiedTimestamp;
RUSD_FAN_COOLER_INFO info;
} RUSD_FAN_COOLER_STATUS;
typedef struct RUSD_SHADOW_ERR_CONT {
volatile NvU64 lastModifiedTimestamp;
//
@@ -313,7 +367,7 @@ typedef struct NV00DE_SHARED_DATA {
NV_DECLARE_ALIGNED(RUSD_CLK_PUBLIC_DOMAIN_INFOS clkPublicDomainInfos, 8);
// POLL_PERF
NV_DECLARE_ALIGNED(RUSD_CLK_THROTTLE_REASON clkThrottleReason, 8);
NV_DECLARE_ALIGNED(RUSD_CLK_THROTTLE_INFO clkThrottleInfo, 8);
// POLL_PERF
NV_DECLARE_ALIGNED(RUSD_PERF_DEVICE_UTILIZATION perfDevUtil, 8);
@@ -340,8 +394,14 @@ typedef struct NV00DE_SHARED_DATA {
// POLL_POWER
NV_DECLARE_ALIGNED(RUSD_INST_POWER_USAGE instPowerUsage, 8);
// POLL_POWER
NV_DECLARE_ALIGNED(RUSD_POWER_POLICY_STATUS powerPolicyStatus, 8);
// POLL_PCI
NV_DECLARE_ALIGNED(RUSD_PCIE_DATA pciBusData, 8);
// POLL_FAN
NV_DECLARE_ALIGNED(RUSD_FAN_COOLER_STATUS fanCoolerStatus, 8);
} NV00DE_SHARED_DATA;
//
@@ -354,6 +414,7 @@ typedef struct NV00DE_SHARED_DATA {
#define NV00DE_RUSD_POLL_POWER 0x8
#define NV00DE_RUSD_POLL_THERMAL 0x10
#define NV00DE_RUSD_POLL_PCI 0x20
#define NV00DE_RUSD_POLL_FAN 0x40
typedef struct NV00DE_ALLOC_PARAMETERS {
NvU64 polledDataMask; // Bitmask of data to request polling at alloc time, 0 if not needed

39
src/common/sdk/nvidia/inc/class/cl0101.h Normal file
View File

@@ -0,0 +1,39 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0101.finn
//
/*
* LOCK_TEST_RELAXED_DUP_OBJECT
* An object used for testing the relaxed GPU lock for RMDUP operation.
* Can be allocated only if PDB_PROP_SYS_ENABLE_RM_TEST_ONLY_CODE is set.
*/
#define LOCK_TEST_RELAXED_DUP_OBJECT 0x0101U

3
src/common/sdk/nvidia/inc/class/cl2080_notification.h
View File

@@ -236,7 +236,8 @@ extern "C" {
#define NV2080_NOTIFIERS_POWER_RESUME (194)
#define NV2080_NOTIFIERS_CTXSW_UCODE_ERROR (195)
#define NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD (196)
#define NV2080_NOTIFIERS_MAXCOUNT (197)
#define NV2080_NOTIFIERS_GPU_RC_RESET (197)
#define NV2080_NOTIFIERS_MAXCOUNT (198)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))

6
src/common/sdk/nvidia/inc/class/cl90cdtrace.h
View File

@@ -31,10 +31,10 @@ typedef struct NV_RATS_GSP_TRACE_RECORD_V1
{
NvU16 seqNo;
NvU16 gspSeqNo;
NvU32 info;
NvU64 recordType;
NvU32 threadId;
NvU64 info;
NvU64 timeStamp;
NvU64 threadId;
NvU64 recordType;
} NV_RATS_GSP_TRACE_RECORD_V1;
typedef NV_RATS_GSP_TRACE_RECORD_V1 NV_RATS_GSP_TRACE_RECORD;

14
src/common/sdk/nvidia/inc/class/cla084.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -76,18 +76,6 @@ typedef struct NVA084_ALLOC_PARAMETERS {
NvBool bDisableDefaultSmcExecPartRestore;
NvU32 vgpuDeviceInstanceId;
NvHandle hPluginClient;
NvU32 numGuestFbHandles;
NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS];
NvU8 vgpuDevName[VM_UUID_SIZE];
NvHandle hPluginHeapMemory;
NvHandle hMigRmHeapMemory;
NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 kernelLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 kernelLogBuffSize, 8);
NvBool bDeviceProfilingEnabled;
NvBool bGpupLiveMigrationEnabled;
} NVA084_ALLOC_PARAMETERS;

3
src/common/sdk/nvidia/inc/class/clc370_notification.h
View File

@@ -34,8 +34,7 @@ extern "C" {
#define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT
#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_BEGIN + (0)
#define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1)
#define NVC370_NOTIFIERS_LTM_CALC_TIMEOUT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1)
#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_LTM_CALC_TIMEOUT + (1)
#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1)
#ifdef __cplusplus
}; /* extern "C" */

96
src/common/sdk/nvidia/inc/class/clc86f.h
View File

@@ -24,6 +24,8 @@
#ifndef __gh100_clc86f_h__
#define __gh100_clc86f_h__
#define HOPPER_CHANNEL_GPFIFO_A (0x0000C86F)
typedef volatile struct Nvc86fControl_struct {
NvU32 Ignored00[0x010]; /* 0000-003f*/
NvU32 Put; /* put offset, read/write 0040-0043*/
@@ -42,54 +44,7 @@ typedef volatile struct Nvc86fControl_struct {
NvU32 Ignored05[0x5c];
} Nvc86fControl, HopperAControlGPFifo;
#define HOPPER_CHANNEL_GPFIFO_A (0x0000C86F)
#define NVC86F_SET_OBJECT (0x00000000)
#define NVC86F_SEM_ADDR_LO (0x0000005c)
#define NVC86F_SEM_ADDR_LO_OFFSET 31:2
#define NVC86F_SEM_ADDR_HI (0x00000060)
#define NVC86F_SEM_ADDR_HI_OFFSET 24:0
#define NVC86F_SEM_PAYLOAD_LO (0x00000064)
#define NVC86F_SEM_PAYLOAD_HI (0x00000068)
#define NVC86F_SEM_EXECUTE (0x0000006c)
#define NVC86F_SEM_EXECUTE_OPERATION 2:0
#define NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
#define NVC86F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
#define NVC86F_SEM_EXECUTE_RELEASE_WFI 20:20
#define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
/* GPFIFO entry format */
#define NVC86F_GP_ENTRY__SIZE 8
#define NVC86F_GP_ENTRY0_FETCH 0:0
#define NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
#define NVC86F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
#define NVC86F_GP_ENTRY0_GET 31:2
#define NVC86F_GP_ENTRY0_OPERAND 31:0
#define NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8
#define NVC86F_GP_ENTRY1_GET_HI 7:0
#define NVC86F_GP_ENTRY1_LEVEL 9:9
#define NVC86F_GP_ENTRY1_LEVEL_MAIN 0x00000000
#define NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
#define NVC86F_GP_ENTRY1_LENGTH 30:10
#define NVC86F_GP_ENTRY1_SYNC 31:31
#define NVC86F_GP_ENTRY1_SYNC_PROCEED 0x00000000
#define NVC86F_GP_ENTRY1_SYNC_WAIT 0x00000001
#define NVC86F_GP_ENTRY1_OPCODE 7:0
#define NVC86F_GP_ENTRY1_OPCODE_NOP 0x00000000
#define NVC86F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
#define NVC86F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
#define NVC86F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
#define NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004
#define NVC86F_WFI (0x00000078)
#define NVC86F_WFI_SCOPE 0:0
#define NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000
#define NVC86F_WFI_SCOPE_CURRENT_VEID 0x00000000
#define NVC86F_WFI_SCOPE_ALL 0x00000001
// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
// specifying the page address for a targeted TLB invalidate and the uTLB for
// a targeted REPLAY_CANCEL for UVM.
@@ -184,6 +139,53 @@ typedef volatile struct Nvc86fControl_struct {
#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE 23:20
#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED 0x00000000
#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP 0x00000001
#define NVC86F_SEM_ADDR_LO (0x0000005c)
#define NVC86F_SEM_ADDR_LO_OFFSET 31:2
#define NVC86F_SEM_ADDR_HI (0x00000060)
#define NVC86F_SEM_ADDR_HI_OFFSET 24:0
#define NVC86F_SEM_PAYLOAD_LO (0x00000064)
#define NVC86F_SEM_PAYLOAD_HI (0x00000068)
#define NVC86F_SEM_EXECUTE (0x0000006c)
#define NVC86F_SEM_EXECUTE_OPERATION 2:0
#define NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
#define NVC86F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
#define NVC86F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003
#define NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12
#define NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001
#define NVC86F_SEM_EXECUTE_RELEASE_WFI 20:20
#define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
#define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25
#define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000
#define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001
#define NVC86F_WFI (0x00000078)
#define NVC86F_WFI_SCOPE 0:0
#define NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000
#define NVC86F_WFI_SCOPE_CURRENT_VEID 0x00000000
#define NVC86F_WFI_SCOPE_ALL 0x00000001
/* GPFIFO entry format */
#define NVC86F_GP_ENTRY__SIZE 8
#define NVC86F_GP_ENTRY0_FETCH 0:0
#define NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
#define NVC86F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
#define NVC86F_GP_ENTRY0_GET 31:2
#define NVC86F_GP_ENTRY0_OPERAND 31:0
#define NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8
#define NVC86F_GP_ENTRY1_GET_HI 7:0
#define NVC86F_GP_ENTRY1_LEVEL 9:9
#define NVC86F_GP_ENTRY1_LEVEL_MAIN 0x00000000
#define NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
#define NVC86F_GP_ENTRY1_LENGTH 30:10
#define NVC86F_GP_ENTRY1_SYNC 31:31
#define NVC86F_GP_ENTRY1_SYNC_PROCEED 0x00000000
#define NVC86F_GP_ENTRY1_SYNC_WAIT 0x00000001
#define NVC86F_GP_ENTRY1_OPCODE 7:0
#define NVC86F_GP_ENTRY1_OPCODE_NOP 0x00000000
#define NVC86F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
#define NVC86F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
#define NVC86F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
#define NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004
#endif // __gh100_clc86f_h__

38
src/common/sdk/nvidia/inc/class/clc8b5.h
View File

@@ -23,22 +23,38 @@
#ifndef __gh100_clc8b5_h__
#define __gh100_clc8b5_h__
#define HOPPER_DMA_COPY_A (0x0000C8B5)
#define HOPPER_DMA_COPY_A (0x0000C8B5)
#define NVC8B5_SET_SEMAPHORE_A (0x00000240)
#define NVC8B5_SET_SEMAPHORE_A_UPPER 24:0
#define NVC8B5_SET_SEMAPHORE_B (0x00000244)
#define NVC8B5_SET_SEMAPHORE_B_LOWER 31:0
#define NVC8B5_SET_SEMAPHORE_PAYLOAD (0x00000248)
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET 1:0
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003)
#define NVC8B5_SET_SRC_PHYS_MODE_PEER_ID 8:6
#define NVC8B5_SET_SRC_PHYS_MODE_FLA 9:9
#define NVC8B5_SET_DST_PHYS_MODE (0x00000264)
#define NVC8B5_SET_DST_PHYS_MODE_TARGET 1:0
#define NVC8B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
#define NVC8B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
#define NVC8B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003)
#define NVC8B5_LAUNCH_DMA (0x00000300)
#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0
#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000)
#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001)
#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002)
#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE 2:2
#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000)
#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001)
#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE 25:25
#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000)
#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001)
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP (0x00000001)
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP (0x00000002)
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001)
#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7
#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001)
@@ -48,18 +64,34 @@
#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000)
#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE 10:10
#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000)
#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001)
#define NVC8B5_LAUNCH_DMA_SRC_TYPE 12:12
#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001)
#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13
#define NVC8B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000)
#define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001)
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006)
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001)
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001)
#define NVC8B5_LAUNCH_DMA_COPY_TYPE 21:20
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT (0x00000000)
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_DEFAULT (0x00000000)
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_SECURE (0x00000001)
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT (0x00000002)
#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23
#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE (0x00000000)
#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001)
#define NVC8B5_LAUNCH_DMA_DISABLE_PLC 26:26
#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001)
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE 27:27
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD (0x00000000)
#define NVC8B5_OFFSET_IN_UPPER (0x00000400)
#define NVC8B5_OFFSET_IN_UPPER_UPPER 24:0
#define NVC8B5_OFFSET_IN_LOWER (0x00000404)
#define NVC8B5_OFFSET_IN_LOWER_VALUE 31:0
#define NVC8B5_OFFSET_OUT_UPPER (0x00000408)
#define NVC8B5_OFFSET_OUT_UPPER_UPPER 24:0
#define NVC8B5_OFFSET_OUT_LOWER (0x0000040C)
@@ -90,8 +122,12 @@
#define NVC8B5_SET_REMAP_COMPONENTS_DST_X 2:0
#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004)
#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005)
#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y 6:4
#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005)
#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16
#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000)
#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003)
#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24
#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000)
#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001)
#endif // __gh100_clc8b5_h__

41
src/common/sdk/nvidia/inc/class/clc96f.h
View File

@@ -24,15 +24,52 @@
#ifndef __gb100_clc96f_h__
#define __gb100_clc96f_h__
#define BLACKWELL_CHANNEL_GPFIFO_A (0x0000C96F)
typedef volatile struct Nvc96fControl_struct {
NvU32 Ignored00[0x23]; /* 0000-008b*/
NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
NvU32 Ignored01[0x5c];
} Nvc96fControl, BlackwellAControlGPFifo;
#define BLACKWELL_CHANNEL_GPFIFO_A (0x0000C96F)
#define NVC96F_SET_OBJECT (0x00000000)
#define NVC96F_MEM_OP_A (0x00000028)
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE 7:6 // only relevant for invalidates with NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE for invalidating link TLB only, or non-link TLB only or all TLBs
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 2
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12
#define NVC96F_MEM_OP_B (0x0000002c)
#define NVC96F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0
#define NVC96F_MEM_OP_C (0x00000030)
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE
#define NVC96F_MEM_OP_D (0x00000034)
#define NVC96F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE
#define NVC96F_MEM_OP_D_OPERATION 31:27
#define NVC96F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
#define NVC96F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a
#define NVC96F_SEM_ADDR_LO (0x0000005c)
#define NVC96F_SEM_ADDR_LO_OFFSET 31:2
#define NVC96F_SEM_ADDR_HI (0x00000060)

41
src/common/sdk/nvidia/inc/class/clcb70.h Normal file
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/*
* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clcb70.finn
//
#define NVCB70_DISPLAY (0xcb70U) /* finn: Evaluated from "NVCB70_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NVCB70_ALLOCATION_PARAMETERS_MESSAGE_ID (0xcb70U)
typedef struct NVCB70_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numDsis; // Number of DSIs in this chip/display
} NVCB70_ALLOCATION_PARAMETERS;

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/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcb71_h_
#define _clcb71_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCB71_DISP_SF_USER (0x000CB71)
typedef volatile struct _clcb71_tag0 {
NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */
} _NvCB71DispSfUser, NvCB71DispSfUserMap;
#define NVCB71_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVCB71_SF_HDMI_INFO_CTRL__SIZE_1 8 /* */
#define NVCB71_SF_HDMI_INFO_CTRL__SIZE_2 3 /* */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL(i,j) (0x000E0130-0x000E0000+(i)*1024+(j)*8) /* RW-4A */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL__SIZE_2 10 /* */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE 3:1 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ALWAYS 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ONCE 0x00000001 /* RW--V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ALWAYS 0x00000002 /* RW--V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ONCE 0x00000003 /* RW--V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_TRIGGER 0x00000004 /* RW--V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_LOC 5:4 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_LOC_VSYNC 0x00000001 /* RW--V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_LOC_LINE 0x00000002 /* RW--V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_OFFSET 10:6 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SIZE 18:14 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SIZE_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_BUSY 22:22 /* R-IVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_BUSY_NO 0x00000000 /* R-I-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_BUSY_YES 0x00000001 /* R---V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SENT 23:23 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SENT_NO 0x00000000 /* R-I-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SENT_YES 0x00000001 /* R---V */
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SENT_CLEAR 0x00000001 /* -W--C */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG(i,j) (0x000E0134-0x000E0000+(i)*1024+(j)*8) /* RW-4A */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_1 8 /* */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_2 10 /* */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_FID 7:0 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_FID_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID 23:8 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED 24:24 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_NO 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_YES 0x00000001 /* RW--V */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN 25:25 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_NO 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_YES 0x00000001 /* RW--V */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM 29:29 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_NO 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_YES 0x00000001 /* RW--V */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW 30:30 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW_INIT 0x00000000 /* R-I-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW_DONE 0x00000000 /* R---V */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW_PENDING 0x00000001 /* R---T */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW_TRIGGER 0x00000001 /* -W--T */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL 31:31 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ACT 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ARM 0x00000001 /* RW--V */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_CTRL(i) (0x000E03F0-0x000E0000+(i)*1024) /* RW-4A */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_CTRL__SIZE_1 8 /* */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET 4:0 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA(i) (0x000E03F4-0x000E0000+(i)*1024) /* RW-4A */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA__SIZE_1 8 /* */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE0 7:0 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE0_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE1 15:8 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE1_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE2 23:16 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE2_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE3 31:24 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE3_INIT 0x00000000 /* RWI-V */
#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL(i) (0x000E03F8-0x000E0000+(i)*1024) /* RW-4A */
#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL__SIZE_1 8 /* */
#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY 1:1 /* RWIVF */
#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_HIGH 0x00000000 /* RW--V */
#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_LOW 0x00000001 /* RWI-V */
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clcb71_h_

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src/common/sdk/nvidia/inc/class/clcb73.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcb73_h_
#define _clcb73_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCB73_DISP_CAPABILITIES 0xCB73
typedef volatile struct _clcb73_tag0 {
NvU32 dispCapabilities[0x400];
} _NvCB73DispCapabilities,NvCB73DispCapabilities_Map ;
#define NVCB73_SYS_CAP 0x0 /* RW-4R */
#define NVCB73_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */
#define NVCB73_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */
#define NVCB73_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */
#define NVCB73_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */
#define NVCB73_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */
#define NVCB73_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */
#define NVCB73_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */
#define NVCB73_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */
#define NVCB73_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCB73_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NVCB73_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */
#define NVCB73_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */
#define NVCB73_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */
#define NVCB73_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */
#define NVCB73_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */
#define NVCB73_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */
#define NVCB73_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */
#define NVCB73_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */
#define NVCB73_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */
#define NVCB73_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */
#define NVCB73_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_RISCV0_EXISTS 16:16 /* RWIVF */
#define NVCB73_SYS_CAP_RISCV0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_RISCV0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */
#define NVCB73_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */
#define NVCB73_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */
#define NVCB73_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */
#define NVCB73_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */
#define NVCB73_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */
#define NVCB73_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB 0x4 /* RW-4R */
#define NVCB73_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCB73_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */
#define NVCB73_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC 0x20 /* RW-4R */
#define NVCB73_SYS_CAPC_TILE0_EXISTS 0:0 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE1_EXISTS 1:1 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE2_EXISTS 2:2 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE3_EXISTS 3:3 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE4_EXISTS 4:4 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE5_EXISTS 5:5 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE6_EXISTS 6:6 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE7_EXISTS 7:7 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCB73_SYS_CAPC_TILE_EXISTS__SIZE_1 8 /* */
#define NVCB73_SYS_CAPC_TILE_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE 8:8 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE 9:9 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE 10:10 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE 11:11 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE 12:12 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE 13:13 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE 14:14 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE 15:15 /* RWIVF */
#define NVCB73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE(i) (8+(i)):(8+(i)) /* RWIVF */
#define NVCB73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE__SIZE_1 8 /* */
#define NVCB73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPC_MERGER_TILE_BUFFER_SIZE 31:16 /* RWIUF */
#define NVCB73_SYS_CAPD 0x2c /* RW-4R */
#define NVCB73_SYS_CAPD_NUM_TELLTALE_REGIONS 4:0 /* RWIUF */
#define NVCB73_SYS_CAPD_NUM_FROZEN_FRAME_REGIONS 12:8 /* RWIUF */
#define NVCB73_SYS_CAPD_NUM_ROI 20:16 /* RWIUF */
#define NVCB73_SYS_CAPD_AE_SDP_EXISTS 30:30 /* RWIVF */
#define NVCB73_SYS_CAPD_AE_SDP_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPD_AE_SDP_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPD_AMSS_EXISTS 31:31 /* RWIVF */
#define NVCB73_SYS_CAPD_AMSS_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPD_AMSS_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE 0x34 /* RW-4R */
#define NVCB73_SYS_CAPE_VIRWIN0_EXISTS 0:0 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN1_EXISTS 1:1 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN2_EXISTS 2:2 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN3_EXISTS 3:3 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN4_EXISTS 4:4 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN5_EXISTS 5:5 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN6_EXISTS 6:6 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN7_EXISTS 7:7 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN8_EXISTS 8:8 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN8_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN8_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN9_EXISTS 9:9 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN9_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN9_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN10_EXISTS 10:10 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN10_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN10_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN11_EXISTS 11:11 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN11_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN11_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN12_EXISTS 12:12 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN12_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN12_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN13_EXISTS 13:13 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN13_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN13_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN14_EXISTS 14:14 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN14_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN14_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN15_EXISTS 15:15 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN15_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN15_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN16_EXISTS 16:16 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN16_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN16_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN17_EXISTS 17:17 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN17_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN17_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN18_EXISTS 18:18 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN18_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN18_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN19_EXISTS 19:19 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN19_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN19_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN20_EXISTS 20:20 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN20_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN20_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN21_EXISTS 21:21 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN21_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN21_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN22_EXISTS 22:22 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN22_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN22_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN23_EXISTS 23:23 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN23_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN23_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN24_EXISTS 24:24 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN24_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN24_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN25_EXISTS 25:25 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN25_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN25_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN26_EXISTS 26:26 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN26_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN26_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN27_EXISTS 27:27 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN27_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN27_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN28_EXISTS 28:28 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN28_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN28_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN29_EXISTS 29:29 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN29_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN29_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN30_EXISTS 30:30 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN30_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN30_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN31_EXISTS 31:31 /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN31_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN31_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCB73_SYS_CAPE_VIRWIN_EXISTS__SIZE_1 32 /* */
#define NVCB73_SYS_CAPE_VIRWIN_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_SYS_CAPE_VIRWIN_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_MISC_CAPA_NUM_VMS 17:13 /* RWIUF */
#define NVCB73_LINK_CAP 0x30 /* RW-4R */
#define NVCB73_LINK_CAP_PHYCTRL0_EXISTS 0:0 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL1_EXISTS 1:1 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL2_EXISTS 2:2 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL3_EXISTS 3:3 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL4_EXISTS 4:4 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL5_EXISTS 5:5 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL6_EXISTS 6:6 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL7_EXISTS 7:7 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL8_EXISTS 8:8 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL8_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL8_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL9_EXISTS 9:9 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL9_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL9_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL10_EXISTS 10:10 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL10_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL10_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL11_EXISTS 11:11 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL11_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL11_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL12_EXISTS 12:12 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL12_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL12_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL13_EXISTS 13:13 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL13_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL13_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL14_EXISTS 14:14 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL14_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL14_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL15_EXISTS 15:15 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL15_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL15_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL16_EXISTS 16:16 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL16_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL16_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL17_EXISTS 17:17 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL17_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL17_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL18_EXISTS 18:18 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL18_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL18_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL19_EXISTS 19:19 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL19_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL19_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL20_EXISTS 20:20 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL20_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL20_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL21_EXISTS 21:21 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL21_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL21_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL22_EXISTS 22:22 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL22_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL22_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL23_EXISTS 23:23 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL23_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL23_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL24_EXISTS 24:24 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL24_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL24_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL25_EXISTS 25:25 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL25_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL25_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL26_EXISTS 26:26 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL26_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL26_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL27_EXISTS 27:27 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL27_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL27_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL28_EXISTS 28:28 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL28_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL28_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL29_EXISTS 29:29 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL29_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL29_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL30_EXISTS 30:30 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL30_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL30_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL31_EXISTS 31:31 /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL31_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL31_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCB73_LINK_CAP_PHYCTRL_EXISTS__SIZE_1 32 /* */
#define NVCB73_LINK_CAP_PHYCTRL_EXISTS_NO 0x00000000 /* RW--V */
#define NVCB73_LINK_CAP_PHYCTRL_EXISTS_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA 0x10 /* RW-4R */
#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */
#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS 26:26 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_FALSE 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_TRUE 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC 0x18 /* RW-4R */
#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION 13:13 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_FALSE 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_TRUE 0x00000001 /* RWI-V */
#define NVCB73_IHUB_COMMON_CAPE 0x24 /* RW-4R */
#define NVCB73_IHUB_COMMON_CAPE_PHYWIN_BUFFER_SIZE 15:0 /* RWIUF */
#define NVCB73_IHUB_COMMON_CAPF 0x28 /* RW-4R */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE 0:0 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE 1:1 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE 2:2 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE 3:3 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE 4:4 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE 5:5 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE 6:6 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE 7:7 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE 8:8 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE 9:9 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE 10:10 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE 11:11 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE 12:12 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE 13:13 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE 14:14 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE 15:15 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE 16:16 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE 17:17 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE 18:18 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE 19:19 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE 20:20 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE 21:21 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE 22:22 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE 23:23 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE 24:24 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE 25:25 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE 26:26 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE 27:27 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE 28:28 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE 29:29 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE 30:30 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE 31:31 /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE__SIZE_1 32 /* */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */
#define NVCB73_POSTCOMP_HDR_CAPA__SIZE_1 8 /* */
#define NVCB73_POSTCOMP_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_LTM_PRESENT 25:25 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPA_LTM_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPA_LTM_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */
#define NVCB73_POSTCOMP_HDR_CAPB__SIZE_1 8 /* */
#define NVCB73_POSTCOMP_HDR_CAPB_VGA 0:0 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_SZ 12:1 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_LOGNR 15:13 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD 17:17 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_DIRECT 18:18 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */
#define NVCB73_POSTCOMP_HDR_CAPC__SIZE_1 8 /* */
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */
#define NVCB73_POSTCOMP_HDR_CAPD__SIZE_1 8 /* */
#define NVCB73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */
#define NVCB73_POSTCOMP_HDR_CAPE__SIZE_1 8 /* */
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_MAXLINEWIDTH 15:0 /* RWIUF */
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT 18:18 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE 21:19 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_9x9x9 0x00000000 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_17x17x17 0x00000001 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_25x25x25 0x00000002 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_33x33x33 0x00000003 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_4 0x00000004 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_5 0x00000005 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_6 0x00000006 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_7 0x00000007 /* RW--V */
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_NUM_CURVES 23:22 /* RWIUF */
#define NVCB73_POSTCOMP_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */
#define NVCB73_POSTCOMP_HDR_CAPF__SIZE_1 8 /* */
#define NVCB73_POSTCOMP_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPF_LTM_MAX_PIXELS 31:16 /* RWIVF */
#define NVCB73_POSTCOMP_HDR_CAPG(i) (0x698+(i)*32) /* RW-4A */
#define NVCB73_POSTCOMP_HDR_CAPG__SIZE_1 8 /* */
#define NVCB73_POSTCOMP_HDR_CAPG_CMI_SZ 11:0 /* RWIUF */
#define NVCB73_POSTCOMP_HDR_CAPG_CMI_LOGNR 14:12 /* RWIUF */
#define NVCB73_POSTCOMP_HDR_CAPG_CMO_SZ 26:15 /* RWIUF */
#define NVCB73_POSTCOMP_HDR_CAPG_CMO_LOGNR 29:27 /* RWIUF */
#define NVCB73_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */
#define NVCB73_SOR_CAP__SIZE_1 8 /* */
#define NVCB73_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */
#define NVCB73_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */
#define NVCB73_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */
#define NVCB73_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */
#define NVCB73_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_DP_DUAL_MODE 4:4 /* RWIVF */
#define NVCB73_SOR_CAP_DP_DUAL_MODE_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_DP_DUAL_MODE_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */
#define NVCB73_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */
#define NVCB73_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */
#define NVCB73_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */
#define NVCB73_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_DP_TUNNELING_OVER_USB4 15:15 /* RWIVF */
#define NVCB73_SOR_CAP_DP_TUNNELING_OVER_USB4_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_DP_TUNNELING_OVER_USB4_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_SDI 16:16 /* RWIVF */
#define NVCB73_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_DP_DUAL_MST 23:23 /* RWIVF */
#define NVCB73_SOR_CAP_DP_DUAL_MST_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_DP_DUAL_MST_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_DP_A 24:24 /* RWIVF */
#define NVCB73_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_DP_B 25:25 /* RWIVF */
#define NVCB73_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */
#define NVCB73_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */
#define NVCB73_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */
#define NVCB73_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_HDMI_FRL_YUV422 29:29 /* RWIVF */
#define NVCB73_SOR_CAP_HDMI_FRL_YUV422_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_HDMI_FRL_YUV422_TRUE 0x00000001 /* RW--V */
#define NVCB73_SOR_CAP_DP_128B132B 30:30 /* RWIVF */
#define NVCB73_SOR_CAP_DP_128B132B_FALSE 0x00000000 /* RW--V */
#define NVCB73_SOR_CAP_DP_128B132B_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT 13:13 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT 13:13 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#define NVCB73_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */
#define NVCB73_SOR_CLK_CAP__SIZE_1 8 /* */
#define NVCB73_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */
#define NVCB73_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */
#define NVCB73_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */
#ifdef __cplusplus
};
#endif /* extern C */
#endif //_clcb73_h_

216
src/common/sdk/nvidia/inc/class/clcb7a.h Normal file
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@@ -0,0 +1,216 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcb7a__h_
#define _clcb7a__h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCB7A_CURSOR_IMM_CHANNEL_PIO (0x0000CB7A)
typedef volatile struct _clcb7a_tag0 {
NvV32 Reserved00[0x2];
NvV32 Free; // 0x00000008 - 0x0000000B
NvV32 Reserved01[0x7D];
NvV32 Update; // 0x00000200 - 0x00000203
NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207
NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F
NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213
NvV32 Reserved02[0x3F7B];
} NVCB7ADispCursorImmControlPio;
#define NVCB7A_FREE (0x00000008)
#define NVCB7A_FREE_COUNT 5:0
#define NVCB7A_UPDATE (0x00000200)
#define NVCB7A_UPDATE_RELEASE_ELV 0:0
#define NVCB7A_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVCB7A_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN 8:4
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVCB7A_UPDATE_FORCE_FULLSCREEN 12:12
#define NVCB7A_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
#define NVCB7A_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
#define NVCB7A_SET_INTERLOCK_FLAGS (0x00000204)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NVCB7A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004)
#define NVCB7A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0
#define NVCB7A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clcb7a_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcb7b_h_
#define _clcb7b_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCB7B_WINDOW_IMM_CHANNEL_DMA (0x0000CB7B)
// dma opcode instructions
#define NVCB7B_DMA
#define NVCB7B_DMA_OPCODE 31:29
#define NVCB7B_DMA_OPCODE_METHOD 0x00000000
#define NVCB7B_DMA_OPCODE_JUMP 0x00000001
#define NVCB7B_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NVCB7B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NVCB7B_DMA_METHOD_COUNT 27:18
#define NVCB7B_DMA_METHOD_OFFSET 15:2
#define NVCB7B_DMA_DATA 31:0
#define NVCB7B_DMA_DATA_NOP 0x00000000
#define NVCB7B_DMA_JUMP_OFFSET 15:2
#define NVCB7B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NVCB7B_PUT (0x00000000)
#define NVCB7B_PUT_PTR 13:0
#define NVCB7B_GET (0x00000004)
#define NVCB7B_GET_PTR 13:0
#define NVCB7B_UPDATE (0x00000200)
#define NVCB7B_UPDATE_RELEASE_ELV 0:0
#define NVCB7B_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVCB7B_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVCB7B_UPDATE_INTERLOCK_WITH_WINDOW 1:1
#define NVCB7B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVCB7B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVCB7B_UPDATE_FORCE_FULLSCREEN 4:4
#define NVCB7B_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
#define NVCB7B_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
#define NVCB7B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004)
#define NVCB7B_SET_POINT_OUT_X 15:0
#define NVCB7B_SET_POINT_OUT_Y 31:16
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clcb7b_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcb7e_h_
#define _clcb7e_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCB7E_WINDOW_CHANNEL_DMA (0x0000CB7E)
// dma opcode instructions
#define NVCB7E_DMA
#define NVCB7E_DMA_OPCODE 31:29
#define NVCB7E_DMA_OPCODE_METHOD 0x00000000
#define NVCB7E_DMA_OPCODE_JUMP 0x00000001
#define NVCB7E_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NVCB7E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NVCB7E_DMA_METHOD_COUNT 27:18
#define NVCB7E_DMA_METHOD_OFFSET 15:2
#define NVCB7E_DMA_DATA 31:0
#define NVCB7E_DMA_DATA_NOP 0x00000000
#define NVCB7E_DMA_JUMP_OFFSET 15:2
#define NVCB7E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NVCB7E_PUT (0x00000000)
#define NVCB7E_PUT_PTR 13:0
#define NVCB7E_GET (0x00000004)
#define NVCB7E_GET_PTR 13:0
#define NVCB7E_UPDATE (0x00000200)
#define NVCB7E_UPDATE_RELEASE_ELV 0:0
#define NVCB7E_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVCB7E_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN 8:4
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i))
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVCB7E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12
#define NVCB7E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000)
#define NVCB7E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001)
#define NVCB7E_UPDATE_FORCE_FULLSCREEN 16:16
#define NVCB7E_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
#define NVCB7E_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
#define NVCB7E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204)
#define NVCB7E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0
#define NVCB7E_GET_LINE (0x00000208)
#define NVCB7E_GET_LINE_LINE 15:0
#define NVCB7E_SET_SEMAPHORE_CONTROL (0x0000020C)
#define NVCB7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11
#define NVCB7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000)
#define NVCB7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001)
#define NVCB7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15
#define NVCB7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000)
#define NVCB7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001)
#define NVCB7E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12
#define NVCB7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000)
#define NVCB7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001)
#define NVCB7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002)
#define NVCB7E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14
#define NVCB7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000)
#define NVCB7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001)
#define NVCB7E_SET_SEMAPHORE_ACQUIRE (0x00000210)
#define NVCB7E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0
#define NVCB7E_SET_SEMAPHORE_RELEASE (0x00000214)
#define NVCB7E_SET_SEMAPHORE_RELEASE_VALUE 31:0
#define NVCB7E_SET_NOTIFIER_CONTROL (0x00000220)
#define NVCB7E_SET_NOTIFIER_CONTROL_MODE 0:0
#define NVCB7E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NVCB7E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NVCB7E_SET_SIZE (0x00000224)
#define NVCB7E_SET_SIZE_WIDTH 15:0
#define NVCB7E_SET_SIZE_HEIGHT 31:16
#define NVCB7E_SET_STORAGE (0x00000228)
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NVCB7E_SET_PARAMS (0x0000022C)
#define NVCB7E_SET_PARAMS_FORMAT 7:0
#define NVCB7E_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NVCB7E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F)
#define NVCB7E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NVCB7E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NVCB7E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E)
#define NVCB7E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NVCB7E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6)
#define NVCB7E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NVCB7E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9)
#define NVCB7E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
#define NVCB7E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NVCB7E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NVCB7E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NVCB7E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NVCB7E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028)
#define NVCB7E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029)
#define NVCB7E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035)
#define NVCB7E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036)
#define NVCB7E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038)
#define NVCB7E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A)
#define NVCB7E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B)
#define NVCB7E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055)
#define NVCB7E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056)
#define NVCB7E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058)
#define NVCB7E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075)
#define NVCB7E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076)
#define NVCB7E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078)
#define NVCB7E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18
#define NVCB7E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000)
#define NVCB7E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001)
#define NVCB7E_SET_PARAMS_SWAP_UV 19:19
#define NVCB7E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000)
#define NVCB7E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001)
#define NVCB7E_SET_PARAMS_FMT_ROUNDING_MODE 22:22
#define NVCB7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000)
#define NVCB7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001)
#define NVCB7E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004)
#define NVCB7E_SET_PLANAR_STORAGE_PITCH 12:0
#define NVCB7E_SET_SEMAPHORE_RELEASE_HI (0x0000023C)
#define NVCB7E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0
#define NVCB7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY (0x00000240)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY_ADDRESS_HI 31:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY (0x00000244)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ADDRESS_LO 31:4
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET 3:2
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE 0:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY (0x00000248)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY_ADDRESS_HI 31:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY (0x0000024C)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ADDRESS_LO 31:4
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET 3:2
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE 0:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004)
#define NVCB7E_SET_POINT_IN_X 15:0
#define NVCB7E_SET_POINT_IN_Y 31:16
#define NVCB7E_SET_SIZE_IN (0x00000298)
#define NVCB7E_SET_SIZE_IN_WIDTH 15:0
#define NVCB7E_SET_SIZE_IN_HEIGHT 31:16
#define NVCB7E_SET_SIZE_OUT (0x000002A4)
#define NVCB7E_SET_SIZE_OUT_WIDTH 15:0
#define NVCB7E_SET_SIZE_OUT_HEIGHT 31:16
#define NVCB7E_SET_CONTROL_INPUT_SCALER (0x000002A8)
#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0
#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001)
#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004)
#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4
#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001)
#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004)
#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE 8:8
#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE 9:9
#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC)
#define NVCB7E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0
#define NVCB7E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12
#define NVCB7E_SET_COMPOSITION_CONTROL (0x000002EC)
#define NVCB7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0
#define NVCB7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000)
#define NVCB7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001)
#define NVCB7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002)
#define NVCB7E_SET_COMPOSITION_CONTROL_DEPTH 11:4
#define NVCB7E_SET_COMPOSITION_CONTROL_BYPASS 16:16
#define NVCB7E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000)
#define NVCB7E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001)
#define NVCB7E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0)
#define NVCB7E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0
#define NVCB7E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCB7E_SET_KEY_ALPHA (0x000002F8)
#define NVCB7E_SET_KEY_ALPHA_MIN 15:0
#define NVCB7E_SET_KEY_ALPHA_MAX 31:16
#define NVCB7E_SET_KEY_RED_CR (0x000002FC)
#define NVCB7E_SET_KEY_RED_CR_MIN 15:0
#define NVCB7E_SET_KEY_RED_CR_MAX 31:16
#define NVCB7E_SET_KEY_GREEN_Y (0x00000300)
#define NVCB7E_SET_KEY_GREEN_Y_MIN 15:0
#define NVCB7E_SET_KEY_GREEN_Y_MAX 31:16
#define NVCB7E_SET_KEY_BLUE_CB (0x00000304)
#define NVCB7E_SET_KEY_BLUE_CB_MIN 15:0
#define NVCB7E_SET_KEY_BLUE_CB_MAX 31:16
#define NVCB7E_SET_PRESENT_CONTROL (0x00000308)
#define NVCB7E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0
#define NVCB7E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4
#define NVCB7E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NVCB7E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NVCB7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8
#define NVCB7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
#define NVCB7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
#define NVCB7E_SET_PRESENT_CONTROL_STEREO_MODE 13:12
#define NVCB7E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000)
#define NVCB7E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001)
#define NVCB7E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002)
#define NVCB7E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C)
#define NVCB7E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330)
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000)
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001)
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000)
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001)
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002)
#define NVCB7E_SET_ACQ_SEMAPHORE_VALUE (0x00000334)
#define NVCB7E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0
#define NVCB7E_SET_SCAN_DIRECTION (0x0000033C)
#define NVCB7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0
#define NVCB7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000)
#define NVCB7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001)
#define NVCB7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1
#define NVCB7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000)
#define NVCB7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001)
#define NVCB7E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2
#define NVCB7E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000)
#define NVCB7E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001)
#define NVCB7E_SET_TIMESTAMP_ORIGIN_LO (0x00000340)
#define NVCB7E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0
#define NVCB7E_SET_TIMESTAMP_ORIGIN_HI (0x00000344)
#define NVCB7E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0
#define NVCB7E_SET_UPDATE_TIMESTAMP_LO (0x00000348)
#define NVCB7E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0
#define NVCB7E_SET_UPDATE_TIMESTAMP_HI (0x0000034C)
#define NVCB7E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0
#define NVCB7E_SET_INTERLOCK_FLAGS (0x00000370)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
#define NVCB7E_SET_CHROMA_VER (0x00000378)
#define NVCB7E_SET_CHROMA_VER_POSITION 1:0
#define NVCB7E_SET_CHROMA_VER_POSITION_TOP (0x00000000)
#define NVCB7E_SET_CHROMA_VER_POSITION_CENTER (0x00000001)
#define NVCB7E_SET_CHROMA_VER_POSITION_BOTTOM (0x00000002)
#define NVCB7E_SET_CHROMA_VER_USE_SWPOSITION 2:2
#define NVCB7E_SET_CHROMA_VER_USE_SWPOSITION_FALSE (0x00000000)
#define NVCB7E_SET_CHROMA_VER_USE_SWPOSITION_TRUE (0x00000001)
#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD 4:3
#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD_WT_0 (0x00000000)
#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD_WT_QUARTER (0x00000001)
#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD_WT_HALF (0x00000002)
#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003)
#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN 6:5
#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_0 (0x00000000)
#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_QUARTER (0x00000001)
#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_HALF (0x00000002)
#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003)
#define NVCB7E_SET_CHROMA_VER_USE_SWWEIGHTS 7:7
#define NVCB7E_SET_CHROMA_VER_USE_SWWEIGHTS_FALSE (0x00000000)
#define NVCB7E_SET_CHROMA_VER_USE_SWWEIGHTS_TRUE (0x00000001)
#define NVCB7E_SET_CHROMA_HOR (0x0000037C)
#define NVCB7E_SET_CHROMA_HOR_REPLACE_ODD 0:0
#define NVCB7E_SET_CHROMA_HOR_REPLACE_ODD_DISABLE (0x00000000)
#define NVCB7E_SET_CHROMA_HOR_REPLACE_ODD_ENABLE (0x00000001)
#define NVCB7E_SET_CHROMA_HOR_REPLACE_EVEN 1:1
#define NVCB7E_SET_CHROMA_HOR_REPLACE_EVEN_DISABLE (0x00000000)
#define NVCB7E_SET_CHROMA_HOR_REPLACE_EVEN_ENABLE (0x00000001)
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD 3:2
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_0 (0x00000000)
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_QUARTER (0x00000001)
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_HALF (0x00000002)
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003)
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN 5:4
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_0 (0x00000000)
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_QUARTER (0x00000001)
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_HALF (0x00000002)
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003)
#define NVCB7E_SET_CHROMA_HOR_USE_SWWEIGHTS 6:6
#define NVCB7E_SET_CHROMA_HOR_USE_SWWEIGHTS_FALSE (0x00000000)
#define NVCB7E_SET_CHROMA_HOR_USE_SWWEIGHTS_TRUE (0x00000001)
#define NVCB7E_SET_EXT_PACKET_CONTROL (0x00000398)
#define NVCB7E_SET_EXT_PACKET_CONTROL_ENABLE 0:0
#define NVCB7E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_EXT_PACKET_CONTROL_LOCATION 4:4
#define NVCB7E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000)
#define NVCB7E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001)
#define NVCB7E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8
#define NVCB7E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000)
#define NVCB7E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001)
#define NVCB7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12
#define NVCB7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000)
#define NVCB7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001)
#define NVCB7E_SET_EXT_PACKET_CONTROL_SIZE 27:16
#define NVCB7E_SET_EXT_PACKET_DATA (0x0000039C)
#define NVCB7E_SET_EXT_PACKET_DATA_DB0 7:0
#define NVCB7E_SET_EXT_PACKET_DATA_DB1 15:8
#define NVCB7E_SET_EXT_PACKET_DATA_DB2 23:16
#define NVCB7E_SET_EXT_PACKET_DATA_DB3 31:24
#define NVCB7E_SET_WIN_INFOFRAME (0x000003A0)
#define NVCB7E_SET_WIN_INFOFRAME_FID 7:0
#define NVCB7E_SET_WIN_INFOFRAME_EN 16:16
#define NVCB7E_SET_WIN_INFOFRAME_EN_DISABLE (0x00000000)
#define NVCB7E_SET_WIN_INFOFRAME_EN_ENABLE (0x00000001)
#define NVCB7E_SET_FMT_COEFFICIENT_C00 (0x00000400)
#define NVCB7E_SET_FMT_COEFFICIENT_C00_VALUE 20:0
#define NVCB7E_SET_FMT_COEFFICIENT_C01 (0x00000404)
#define NVCB7E_SET_FMT_COEFFICIENT_C01_VALUE 20:0
#define NVCB7E_SET_FMT_COEFFICIENT_C02 (0x00000408)
#define NVCB7E_SET_FMT_COEFFICIENT_C02_VALUE 20:0
#define NVCB7E_SET_FMT_COEFFICIENT_C03 (0x0000040C)
#define NVCB7E_SET_FMT_COEFFICIENT_C03_VALUE 20:0
#define NVCB7E_SET_FMT_COEFFICIENT_C10 (0x00000410)
#define NVCB7E_SET_FMT_COEFFICIENT_C10_VALUE 20:0
#define NVCB7E_SET_FMT_COEFFICIENT_C11 (0x00000414)
#define NVCB7E_SET_FMT_COEFFICIENT_C11_VALUE 20:0
#define NVCB7E_SET_FMT_COEFFICIENT_C12 (0x00000418)
#define NVCB7E_SET_FMT_COEFFICIENT_C12_VALUE 20:0
#define NVCB7E_SET_FMT_COEFFICIENT_C13 (0x0000041C)
#define NVCB7E_SET_FMT_COEFFICIENT_C13_VALUE 20:0
#define NVCB7E_SET_FMT_COEFFICIENT_C20 (0x00000420)
#define NVCB7E_SET_FMT_COEFFICIENT_C20_VALUE 20:0
#define NVCB7E_SET_FMT_COEFFICIENT_C21 (0x00000424)
#define NVCB7E_SET_FMT_COEFFICIENT_C21_VALUE 20:0
#define NVCB7E_SET_FMT_COEFFICIENT_C22 (0x00000428)
#define NVCB7E_SET_FMT_COEFFICIENT_C22_VALUE 20:0
#define NVCB7E_SET_FMT_COEFFICIENT_C23 (0x0000042C)
#define NVCB7E_SET_FMT_COEFFICIENT_C23_VALUE 20:0
#define NVCB7E_SET_ILUT_CONTROL (0x00000440)
#define NVCB7E_SET_ILUT_CONTROL_INTERPOLATE 0:0
#define NVCB7E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCB7E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCB7E_SET_ILUT_CONTROL_MIRROR 1:1
#define NVCB7E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVCB7E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVCB7E_SET_ILUT_CONTROL_MODE 3:2
#define NVCB7E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000)
#define NVCB7E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001)
#define NVCB7E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002)
#define NVCB7E_SET_ILUT_CONTROL_SIZE 18:8
#define NVCB7E_SET_CSC00CONTROL (0x0000045C)
#define NVCB7E_SET_CSC00CONTROL_ENABLE 0:0
#define NVCB7E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_CSC00COEFFICIENT_C00 (0x00000460)
#define NVCB7E_SET_CSC00COEFFICIENT_C00_VALUE 20:0
#define NVCB7E_SET_CSC00COEFFICIENT_C01 (0x00000464)
#define NVCB7E_SET_CSC00COEFFICIENT_C01_VALUE 20:0
#define NVCB7E_SET_CSC00COEFFICIENT_C02 (0x00000468)
#define NVCB7E_SET_CSC00COEFFICIENT_C02_VALUE 20:0
#define NVCB7E_SET_CSC00COEFFICIENT_C03 (0x0000046C)
#define NVCB7E_SET_CSC00COEFFICIENT_C03_VALUE 20:0
#define NVCB7E_SET_CSC00COEFFICIENT_C10 (0x00000470)
#define NVCB7E_SET_CSC00COEFFICIENT_C10_VALUE 20:0
#define NVCB7E_SET_CSC00COEFFICIENT_C11 (0x00000474)
#define NVCB7E_SET_CSC00COEFFICIENT_C11_VALUE 20:0
#define NVCB7E_SET_CSC00COEFFICIENT_C12 (0x00000478)
#define NVCB7E_SET_CSC00COEFFICIENT_C12_VALUE 20:0
#define NVCB7E_SET_CSC00COEFFICIENT_C13 (0x0000047C)
#define NVCB7E_SET_CSC00COEFFICIENT_C13_VALUE 20:0
#define NVCB7E_SET_CSC00COEFFICIENT_C20 (0x00000480)
#define NVCB7E_SET_CSC00COEFFICIENT_C20_VALUE 20:0
#define NVCB7E_SET_CSC00COEFFICIENT_C21 (0x00000484)
#define NVCB7E_SET_CSC00COEFFICIENT_C21_VALUE 20:0
#define NVCB7E_SET_CSC00COEFFICIENT_C22 (0x00000488)
#define NVCB7E_SET_CSC00COEFFICIENT_C22_VALUE 20:0
#define NVCB7E_SET_CSC00COEFFICIENT_C23 (0x0000048C)
#define NVCB7E_SET_CSC00COEFFICIENT_C23_VALUE 20:0
#define NVCB7E_SET_CSC0LUT_FP_NORM_SCALE (0x00000490)
#define NVCB7E_SET_CSC0LUT_FP_NORM_SCALE_VALUE 31:0
#define NVCB7E_SET_CSC0LUT_CONTROL (0x000004A0)
#define NVCB7E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0
#define NVCB7E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCB7E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCB7E_SET_CSC0LUT_CONTROL_MIRROR 1:1
#define NVCB7E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVCB7E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVCB7E_SET_CSC0LUT_CONTROL_ENABLE 4:4
#define NVCB7E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_CSC0LUT_CONTROL_CURVE 6:5
#define NVCB7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000)
#define NVCB7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001)
#define NVCB7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002)
#define NVCB7E_SET_CSC01CONTROL (0x000004BC)
#define NVCB7E_SET_CSC01CONTROL_ENABLE 0:0
#define NVCB7E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_CSC01COEFFICIENT_C00 (0x000004C0)
#define NVCB7E_SET_CSC01COEFFICIENT_C00_VALUE 20:0
#define NVCB7E_SET_CSC01COEFFICIENT_C01 (0x000004C4)
#define NVCB7E_SET_CSC01COEFFICIENT_C01_VALUE 20:0
#define NVCB7E_SET_CSC01COEFFICIENT_C02 (0x000004C8)
#define NVCB7E_SET_CSC01COEFFICIENT_C02_VALUE 20:0
#define NVCB7E_SET_CSC01COEFFICIENT_C03 (0x000004CC)
#define NVCB7E_SET_CSC01COEFFICIENT_C03_VALUE 20:0
#define NVCB7E_SET_CSC01COEFFICIENT_C10 (0x000004D0)
#define NVCB7E_SET_CSC01COEFFICIENT_C10_VALUE 20:0
#define NVCB7E_SET_CSC01COEFFICIENT_C11 (0x000004D4)
#define NVCB7E_SET_CSC01COEFFICIENT_C11_VALUE 20:0
#define NVCB7E_SET_CSC01COEFFICIENT_C12 (0x000004D8)
#define NVCB7E_SET_CSC01COEFFICIENT_C12_VALUE 20:0
#define NVCB7E_SET_CSC01COEFFICIENT_C13 (0x000004DC)
#define NVCB7E_SET_CSC01COEFFICIENT_C13_VALUE 20:0
#define NVCB7E_SET_CSC01COEFFICIENT_C20 (0x000004E0)
#define NVCB7E_SET_CSC01COEFFICIENT_C20_VALUE 20:0
#define NVCB7E_SET_CSC01COEFFICIENT_C21 (0x000004E4)
#define NVCB7E_SET_CSC01COEFFICIENT_C21_VALUE 20:0
#define NVCB7E_SET_CSC01COEFFICIENT_C22 (0x000004E8)
#define NVCB7E_SET_CSC01COEFFICIENT_C22_VALUE 20:0
#define NVCB7E_SET_CSC01COEFFICIENT_C23 (0x000004EC)
#define NVCB7E_SET_CSC01COEFFICIENT_C23_VALUE 20:0
#define NVCB7E_SET_TMO_CONTROL (0x00000500)
#define NVCB7E_SET_TMO_CONTROL_INTERPOLATE 0:0
#define NVCB7E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCB7E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCB7E_SET_TMO_CONTROL_SAT_MODE 3:2
#define NVCB7E_SET_TMO_CONTROL_SIZE 18:8
#define NVCB7E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508)
#define NVCB7E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16
#define NVCB7E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C)
#define NVCB7E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVCB7E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVCB7E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510)
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514)
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24
#define NVCB7E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518)
#define NVCB7E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0
#define NVCB7E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C)
#define NVCB7E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVCB7E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVCB7E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24
#define NVCB7E_SET_CSC10CONTROL (0x0000053C)
#define NVCB7E_SET_CSC10CONTROL_ENABLE 0:0
#define NVCB7E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_CSC10COEFFICIENT_C00 (0x00000540)
#define NVCB7E_SET_CSC10COEFFICIENT_C00_VALUE 20:0
#define NVCB7E_SET_CSC10COEFFICIENT_C01 (0x00000544)
#define NVCB7E_SET_CSC10COEFFICIENT_C01_VALUE 20:0
#define NVCB7E_SET_CSC10COEFFICIENT_C02 (0x00000548)
#define NVCB7E_SET_CSC10COEFFICIENT_C02_VALUE 20:0
#define NVCB7E_SET_CSC10COEFFICIENT_C03 (0x0000054C)
#define NVCB7E_SET_CSC10COEFFICIENT_C03_VALUE 20:0
#define NVCB7E_SET_CSC10COEFFICIENT_C10 (0x00000550)
#define NVCB7E_SET_CSC10COEFFICIENT_C10_VALUE 20:0
#define NVCB7E_SET_CSC10COEFFICIENT_C11 (0x00000554)
#define NVCB7E_SET_CSC10COEFFICIENT_C11_VALUE 20:0
#define NVCB7E_SET_CSC10COEFFICIENT_C12 (0x00000558)
#define NVCB7E_SET_CSC10COEFFICIENT_C12_VALUE 20:0
#define NVCB7E_SET_CSC10COEFFICIENT_C13 (0x0000055C)
#define NVCB7E_SET_CSC10COEFFICIENT_C13_VALUE 20:0
#define NVCB7E_SET_CSC10COEFFICIENT_C20 (0x00000560)
#define NVCB7E_SET_CSC10COEFFICIENT_C20_VALUE 20:0
#define NVCB7E_SET_CSC10COEFFICIENT_C21 (0x00000564)
#define NVCB7E_SET_CSC10COEFFICIENT_C21_VALUE 20:0
#define NVCB7E_SET_CSC10COEFFICIENT_C22 (0x00000568)
#define NVCB7E_SET_CSC10COEFFICIENT_C22_VALUE 20:0
#define NVCB7E_SET_CSC10COEFFICIENT_C23 (0x0000056C)
#define NVCB7E_SET_CSC10COEFFICIENT_C23_VALUE 20:0
#define NVCB7E_SET_CSC1LUT_FP_SCALE (0x00000570)
#define NVCB7E_SET_CSC1LUT_FP_SCALE_VALUE 15:0
#define NVCB7E_SET_CSC1LUT_CONTROL (0x00000580)
#define NVCB7E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0
#define NVCB7E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCB7E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCB7E_SET_CSC1LUT_CONTROL_MIRROR 1:1
#define NVCB7E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVCB7E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVCB7E_SET_CSC1LUT_CONTROL_ENABLE 4:4
#define NVCB7E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_CSC1LUT_CONTROL_CURVE 6:5
#define NVCB7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000)
#define NVCB7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001)
#define NVCB7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002)
#define NVCB7E_SET_CSC11CONTROL (0x0000059C)
#define NVCB7E_SET_CSC11CONTROL_ENABLE 0:0
#define NVCB7E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_CSC11CONTROL_LEVEL 7:2
#define NVCB7E_SET_CSC11COEFFICIENT_C00 (0x000005A0)
#define NVCB7E_SET_CSC11COEFFICIENT_C00_VALUE 20:0
#define NVCB7E_SET_CSC11COEFFICIENT_C01 (0x000005A4)
#define NVCB7E_SET_CSC11COEFFICIENT_C01_VALUE 20:0
#define NVCB7E_SET_CSC11COEFFICIENT_C02 (0x000005A8)
#define NVCB7E_SET_CSC11COEFFICIENT_C02_VALUE 20:0
#define NVCB7E_SET_CSC11COEFFICIENT_C03 (0x000005AC)
#define NVCB7E_SET_CSC11COEFFICIENT_C03_VALUE 20:0
#define NVCB7E_SET_CSC11COEFFICIENT_C10 (0x000005B0)
#define NVCB7E_SET_CSC11COEFFICIENT_C10_VALUE 20:0
#define NVCB7E_SET_CSC11COEFFICIENT_C11 (0x000005B4)
#define NVCB7E_SET_CSC11COEFFICIENT_C11_VALUE 20:0
#define NVCB7E_SET_CSC11COEFFICIENT_C12 (0x000005B8)
#define NVCB7E_SET_CSC11COEFFICIENT_C12_VALUE 20:0
#define NVCB7E_SET_CSC11COEFFICIENT_C13 (0x000005BC)
#define NVCB7E_SET_CSC11COEFFICIENT_C13_VALUE 20:0
#define NVCB7E_SET_CSC11COEFFICIENT_C20 (0x000005C0)
#define NVCB7E_SET_CSC11COEFFICIENT_C20_VALUE 20:0
#define NVCB7E_SET_CSC11COEFFICIENT_C21 (0x000005C4)
#define NVCB7E_SET_CSC11COEFFICIENT_C21_VALUE 20:0
#define NVCB7E_SET_CSC11COEFFICIENT_C22 (0x000005C8)
#define NVCB7E_SET_CSC11COEFFICIENT_C22_VALUE 20:0
#define NVCB7E_SET_CSC11COEFFICIENT_C23 (0x000005CC)
#define NVCB7E_SET_CSC11COEFFICIENT_C23_VALUE 20:0
#define NVCB7E_SET_CLAMP_RANGE (0x000005D0)
#define NVCB7E_SET_CLAMP_RANGE_LOW 15:0
#define NVCB7E_SET_CLAMP_RANGE_HIGH 31:16
#define NVCB7E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004)
#define NVCB7E_SW_RESERVED_VALUE 31:0
#define NVCB7E_SET_DIRTY_RECT_SIZE (0x000005E4)
#define NVCB7E_SET_DIRTY_RECT_SIZE_WIDTH 15:0
#define NVCB7E_SET_DIRTY_RECT_SIZE_HEIGHT 31:16
#define NVCB7E_SET_DIRTY_RECT_POSITION (0x000005E8)
#define NVCB7E_SET_DIRTY_RECT_POSITION_X 15:0
#define NVCB7E_SET_DIRTY_RECT_POSITION_Y 31:16
#define NVCB7E_SET_SUPERFRAME (0x000005EC)
#define NVCB7E_SET_SUPERFRAME_ENABLE 0:0
#define NVCB7E_SET_SUPERFRAME_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_SUPERFRAME_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_SUPERFRAME_MODE 2:1
#define NVCB7E_SET_SUPERFRAME_MODE_FIXED (0x00000000)
#define NVCB7E_SET_SUPERFRAME_MODE_DYNAMIC (0x00000001)
#define NVCB7E_SET_SUPERFRAME_MODE_SW (0x00000003)
#define NVCB7E_SET_SUPERFRAME_RATIO_IN 15:8
#define NVCB7E_SET_SUPERFRAME_RATIO_OUT 23:16
#define NVCB7E_SET_SUPERFRAME_START_COUNT 31:24
#define NVCB7E_SET_INFOFRAME_CTRL(b) (0x000005F0 + (b)*0x00000004)
#define NVCB7E_SET_INFOFRAME_CTRL_ENABLE 0:0
#define NVCB7E_SET_INFOFRAME_CTRL_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_INFOFRAME_CTRL_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_INFOFRAME_CTRL_LOCATION 5:4
#define NVCB7E_SET_INFOFRAME_CTRL_LOCATION_VBLANK (0x00000000)
#define NVCB7E_SET_INFOFRAME_CTRL_LOCATION_VSYNC (0x00000001)
#define NVCB7E_SET_INFOFRAME_CTRL_LOCATION_LINE (0x00000002)
#define NVCB7E_SET_INFOFRAME_CTRL_LINE_ID 30:16
#define NVCB7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED 31:31
#define NVCB7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_DISABLE (0x00000000)
#define NVCB7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_ENABLE (0x00000001)
#define NVCB7E_SET_INFOFRAME_HEADER(b) (0x000005F8 + (b)*0x00000004)
#define NVCB7E_SET_INFOFRAME_HEADER_HB0 7:0
#define NVCB7E_SET_INFOFRAME_HEADER_HB1 15:8
#define NVCB7E_SET_INFOFRAME_HEADER_HB2 23:16
#define NVCB7E_SET_INFOFRAME_HEADER_HB3 31:24
#define NVCB7E_SET_INFOFRAME_DATA0(b) (0x00000600 + (b)*0x00000004)
#define NVCB7E_SET_INFOFRAME_DATA0_DB0 7:0
#define NVCB7E_SET_INFOFRAME_DATA0_DB1 15:8
#define NVCB7E_SET_INFOFRAME_DATA0_DB2 23:16
#define NVCB7E_SET_INFOFRAME_DATA0_DB3 31:24
#define NVCB7E_SET_INFOFRAME_DATA1(b) (0x00000608 + (b)*0x00000004)
#define NVCB7E_SET_INFOFRAME_DATA1_DB4 7:0
#define NVCB7E_SET_INFOFRAME_DATA1_DB5 15:8
#define NVCB7E_SET_INFOFRAME_DATA1_DB6 23:16
#define NVCB7E_SET_INFOFRAME_DATA1_DB7 31:24
#define NVCB7E_SET_INFOFRAME_DATA2(b) (0x00000610 + (b)*0x00000004)
#define NVCB7E_SET_INFOFRAME_DATA2_DB8 7:0
#define NVCB7E_SET_INFOFRAME_DATA2_DB9 15:8
#define NVCB7E_SET_INFOFRAME_DATA2_DB10 23:16
#define NVCB7E_SET_INFOFRAME_DATA2_DB11 31:24
#define NVCB7E_SET_INFOFRAME_DATA3(b) (0x00000618 + (b)*0x00000004)
#define NVCB7E_SET_INFOFRAME_DATA3_DB12 7:0
#define NVCB7E_SET_INFOFRAME_DATA3_DB13 15:8
#define NVCB7E_SET_INFOFRAME_DATA3_DB14 23:16
#define NVCB7E_SET_INFOFRAME_DATA3_DB15 31:24
#define NVCB7E_SET_INFOFRAME_DATA4(b) (0x00000620 + (b)*0x00000004)
#define NVCB7E_SET_INFOFRAME_DATA4_DB16 7:0
#define NVCB7E_SET_INFOFRAME_DATA4_DB17 15:8
#define NVCB7E_SET_INFOFRAME_DATA4_DB18 23:16
#define NVCB7E_SET_INFOFRAME_DATA4_DB19 31:24
#define NVCB7E_SET_INFOFRAME_DATA5(b) (0x00000628 + (b)*0x00000004)
#define NVCB7E_SET_INFOFRAME_DATA5_DB20 7:0
#define NVCB7E_SET_INFOFRAME_DATA5_DB21 15:8
#define NVCB7E_SET_INFOFRAME_DATA5_DB22 23:16
#define NVCB7E_SET_INFOFRAME_DATA5_DB23 31:24
#define NVCB7E_SET_INFOFRAME_DATA6(b) (0x00000630 + (b)*0x00000004)
#define NVCB7E_SET_INFOFRAME_DATA6_DB24 7:0
#define NVCB7E_SET_INFOFRAME_DATA6_DB25 15:8
#define NVCB7E_SET_INFOFRAME_DATA6_DB26 23:16
#define NVCB7E_SET_INFOFRAME_DATA6_DB27 31:24
#define NVCB7E_SET_INFOFRAME_DATA7(b) (0x00000638 + (b)*0x00000004)
#define NVCB7E_SET_INFOFRAME_DATA7_DB28 7:0
#define NVCB7E_SET_INFOFRAME_DATA7_DB29 15:8
#define NVCB7E_SET_INFOFRAME_DATA7_DB30 23:16
#define NVCB7E_SET_INFOFRAME_DATA7_DB31 31:24
#define NVCB7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE (0x00000640)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE_ADDRESS_HI 31:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE (0x00000644)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ADDRESS_LO 31:4
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET 3:2
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_IOVA (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE 0:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE (0x00000648)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE_ADDRESS_HI 31:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE (0x0000064C)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ADDRESS_LO 31:4
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET 3:2
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_IOVA (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE 0:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000650)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000654)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_ISO(b) (0x00000658 + (b)*0x00000004)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_ISO_ADDRESS_HI 31:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO(b) (0x00000670 + (b)*0x00000004)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_ADDRESS_LO 31:4
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET 3:2
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_IOVA (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_KIND 1:1
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE 0:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_ILUT (0x00000688)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_ILUT_ADDRESS_HI 31:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT (0x0000068C)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_ADDRESS_LO 31:4
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET 3:2
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_IOVA (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE 0:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_ENABLE (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_TMO_LUT (0x00000690)
#define NVCB7E_SET_SURFACE_ADDRESS_HI_TMO_LUT_ADDRESS_HI 31:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT (0x00000694)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ADDRESS_LO 31:4
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET 3:2
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_IOVA (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE 0:0
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_DISABLE (0x00000000)
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_ENABLE (0x00000001)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clcb7e_h

1
src/common/sdk/nvidia/inc/class/clcba2.h
View File

@@ -151,6 +151,7 @@ typedef volatile struct _clcba2_tag0 {
#define NVCBA2_ERROR_SCRUBBER_INSUFFICIENT_PERMISSIONS (0x0000001b)
#define NVCBA2_ERROR_SCRUBBER_MUTEX_ACQUIRE_FAILURE (0x0000001c)
#define NVCBA2_ERROR_SCRUB_SIZE_MAX_EXCEEDED (0x0000001d)
#define NVCBA2_ERROR_SIZE_ZERO (0x0000001e)
#ifdef __cplusplus
}; /* extern "C" */

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h
View File

@@ -184,8 +184,6 @@ typedef struct NV0000_CTRL_DIAG_LOCK_METER_ENTRY {
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS (0x00000021)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA (0x00000100)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL (0x00001000)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET (0x00002000)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET (0x00002001)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX (0x00002002)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX (0x00002003)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP (0x00003000)

58
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,6 +34,13 @@
#include "ctrl/ctrlxxxx.h"
#include "class/cl0000.h"
#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0)
#define NV0000_NOTIFIERS_VGPU_UNBIND_EVENT (1)
#define NV0000_NOTIFIERS_VGPU_BIND_EVENT (2)
#define NV0000_NOTIFIERS_GPU_BIND_UNBIND_EVENT (3)
#define NV0000_NOTIFIERS_MAXCOUNT (4)
/*
* NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION
*
@@ -80,34 +87,59 @@ typedef struct NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE {
NvU32 deviceMask;
} NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE;
typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND {
NvU32 gpuId;
} NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND;
typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND {
NvU32 gpuId;
} NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND;
typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND {
NvU32 gpuId;
NvBool bBind;
} NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND;
/*
* NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS
* NV0000_CTRL_CMD_GET_SYSTEM_EVENT_DATA
*
* This command returns the status of the specified system event type.
* This command reads the client's event data queue info FIFO order.
* See the description of NV01_EVENT for details on registering events.
*
* event
* This parameter specifies the event type. Valid event type values
* can be found in cl0000.h.
* status
* This parameter returns the status for a given event type. Valid
* status values can be found in cl0000.h.
* Output only as selective event data query is not supported yet.
* Event type.
* Valid event type values can be found in this header file.
*
* data
* Data associated with the event.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_CLIENT
* NV_ERR_OBJECT_NOT_FOUND when system event queue is empty
*
*/
#define NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS (0x502) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GET_SYSTEM_EVENT_DATA (0x502) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID (0x2U)
#define NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS {
typedef struct NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS {
NvU32 event;
NvU32 status;
} NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS;
union {
NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE display;
NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND vgpuUnbind;
NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND vgpuBind;
NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND gpuBindUnbind;
} data;
} NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS;
/* _ctrl0000event_h_ */

5
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
View File

@@ -856,10 +856,6 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
NvU32 dataType; /* [out] - data union type */
union {
struct {
NvU32 newValue;
NvU32 oldValue;
} configSet;
struct {
NvU8 paramData[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA];
NvU32 paramSize;
@@ -872,7 +868,6 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
} data;
} NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS;
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001U)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002U)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003U)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004U)

49
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
View File

@@ -68,10 +68,6 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS {
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING 3:3
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE (0x00000001U)
@@ -2116,7 +2112,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS {
* NV_ERR_INVALID_REQUEST
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */
#define NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE 1U
#define NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE 32U
@@ -2143,9 +2139,12 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT {
NvU32 shortTimescaleBatteryCurrentLimitmA;
} NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT;
#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU)
#define NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU)
typedef struct NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
/*Buffer to get all the supported functions*/
NvU32 supportedFuncs;
typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
/* GPU ID */
NvU32 gpuId;
@@ -2176,6 +2175,16 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
/* Target total processing power on battery, offset, in milli-Watts. */
NvS32 targetTppBattOffsetmW;
/*
* Maximum allowed output on battery, offset, in milli-Watts.
*/
NvS32 maxOutputBattOffsetmW;
/*
* Minimum allowed output on battery, offset, in milli-Watts.
*/
NvS32 minOutputBattOffsetmW;
/*
* If value specified is larger than the statically assigned ROS reserve in
* the system power limits table, this will take affect.
@@ -2197,15 +2206,6 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
*/
NvU32 dcTspShortTimescaleLimitmA;
/* Require DB on DC to use system power limits table */
NvBool bRequireDcSysPowerLimitsTable;
/* Dynamic params can override ROS reserve used in DB-DC */
NvBool bAllowDcRestOfSystemReserveOverride;
/* Is DC-TSP supported? */
NvBool bSupportDcTsp;
/* Dynamic Boost AC support */
NvBool bEnableForAC;
@@ -2277,9 +2277,7 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
/* CPU TDP Limit to be set (milliwatts) */
NvU32 cpuTdpmw;
} NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
typedef NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
} NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
/* Define the filter types */
#define CONTROLLER_FILTER_TYPE_EMWA 0U
@@ -2305,9 +2303,16 @@ typedef NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS NV0000_CTRL_SYST
/*
* Defines for get supported sub functions bit fields
*/
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED 8:8
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED_YES 1
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED_NO 0
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED 9:9
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED_YES 1
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED_NO 0
/*!
* Config DSM 2x version specific defines

136
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -1328,11 +1328,12 @@ typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS {
#define NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID (0x60U)
typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 laneCount;
NvU32 linkBW;
NvU32 dp2LinkBW;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 laneCount;
NvU32 linkBW;
NvU32 dp2LinkBW;
NvBool bFECEnabled;
} NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS;
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT 3:0
@@ -1682,8 +1683,6 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
* Specified the DP versions supported by the GPU
* UHBRSupportedByGpu
* Bitmask to specify the UHBR link rates supported by the GPU.
* minPClkForCompressed
* Pixel clock below which we should prefer non-DSC mode.
* bIsMultistreamSupported
* Returns NV_TRUE if MST is supported by the GPU else NV_FALSE
* bIsSCEnabled
@@ -1705,6 +1704,8 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
* Returns NV_TRUE if GPU uses the new RG flush design
* bSupportDPDownSpread
* Returns NV_TRUE if GPU support downspread.
* bAvoidHBR3
* Returns if we need to avoid HBR3 as much as possible
*
* DSC caps
*
@@ -1725,7 +1726,6 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
NvU32 maxLinkRate;
NvU32 dpVersionsSupported;
NvU32 UHBRSupportedByGpu;
NvU32 minPClkForCompressed;
NvBool bIsMultistreamSupported;
NvBool bIsSCEnabled;
NvBool bHasIncreasedWatermarkLimits;
@@ -1736,6 +1736,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
NvBool bOverrideLinkBw;
NvBool bUseRgFlushSequence;
NvBool bSupportDPDownSpread;
NvBool bAvoidHBR3;
NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC;
} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS;
@@ -2041,6 +2042,27 @@ typedef struct NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS {
NvBool enable;
} NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS;
/* NV0073_CTRL_CMD_SPECIFIC_RETRIEVE_DP_RING_BUFFER
*
* These commands retrieves buffer from RM for
* DP Library to dump logs
*
*
* Possible status values returned include:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER (0x731371U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS_MESSAGE_ID (0x71U)
typedef struct NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS {
NV_DECLARE_ALIGNED(NvU8 *pDpRingBuffer, 8);
NvU8 ringBufferType;
NvU32 numRecords;
} NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS;
/*
@@ -3377,6 +3399,44 @@ typedef struct NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS {
#define NV0073_CTRL_CMD_DP2X_GET_LEVEL_INFO_TABLE_DATA (0x73138aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR
*
* This command is used to apply the WAR based on EDID.
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the digital display for which the
* data should be returned. The display ID must a digital display.
* If more than one displayId bit is set or the displayId is not a DP,
* this call will return NV_ERR_INVALID_ARGUMENT.
* bEnable
* This parameter will be used by RM to set the PDB property. Later that PDB
* property will be used for applying the WAR
* head
* This parameter specify for which head RM need to apply the WAR
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS_MESSAGE_ID (0x8BU)
typedef struct NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 bEnable;
NvU32 head;
} NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS;
#define NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR (0x73138bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS_MESSAGE_ID" */
/*
@@ -3444,7 +3504,7 @@ typedef struct NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS {
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP (0x73138bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP (0x73138cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID" */
typedef struct NV0073_CTRL_DP_IMP_LINK_CONFIGURATION {
NvU32 linkRate10M;
@@ -3453,6 +3513,7 @@ typedef struct NV0073_CTRL_DP_IMP_LINK_CONFIGURATION {
NvBool bDp2xChannelCoding;
NvBool bMultiStreamTopology;
NvBool bFECEnabled;
NvBool bDisableEffBppSST8b10b;
} NV0073_CTRL_DP_IMP_LINK_CONFIGURATION;
typedef struct NV0073_CTRL_DP_IMP_DSC_PARAMETERS {
@@ -3489,7 +3550,7 @@ typedef struct NV0073_CTRL_DP_IMP_WATERMARK {
NvBool bIsModePossible;
} NV0073_CTRL_DP_IMP_WATERMARK;
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID (0x8BU)
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID (0x8CU)
typedef struct NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS {
NvU32 subDeviceInstance;
@@ -3501,4 +3562,59 @@ typedef struct NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS {
NV0073_CTRL_DP_IMP_WATERMARK watermark;
} NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS;
/*
* NV0073_CTRL_CMD_DP_GET_CABLEID_INFO_FROM_MACRO
*
* This command is used to read cable ID Information from USB-C Cable for
* DP configuration purposes.
*
* subDeviceInstance [in]
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
*
* displayId [in]
* This parameter specifies the ID of the DP display which owns
* the Main Link to be adjusted. The display ID must a DP display
* as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
* If more than one displayId bit is set or the displayId is not a DP,
* this call will return NV_ERR_INVALID_PARAMETER.
*
* cableIDInfo [out]
* This parameter reflects the result of the cable ID read from the cable
*
* Possible status values returned are:
* NV_ERR_INVALID_PARAMETER
* NV_ERR_NOT_SUPPORTED
* NV_OK
*/
#define NV0073_CTRL_CMD_DP_GET_CABLEID_INFO_FROM_MACRO (0x73138dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS_MESSAGE_ID" */
typedef enum NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE {
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_UNKNOWN = 0,
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_PASSIVE = 1,
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_ACTIVE_RETIMER = 2,
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_ACTIVE_LIN_REDRIVER = 3,
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_OPTICAL = 4,
} NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE;
typedef struct NV0073_CTRL_DP_USBC_CABLEID_INFO {
NvBool uhbr10_0_capable;
NvBool uhbr13_5_capable;
NvBool uhbr20_0_capable;
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE type;
NvBool vconn_source;
} NV0073_CTRL_DP_USBC_CABLEID_INFO;
#define NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS_MESSAGE_ID (0x8DU)
typedef struct NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NV0073_CTRL_DP_USBC_CABLEID_INFO cableIDInfo;
} NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS;
/* _ctrl0073dp_h_ */

56
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h
View File

@@ -32,6 +32,25 @@
#include "ctrl/ctrl0073/ctrl0073base.h"
/*
* tilemask
* Tiles assocaited with calc tiemout head.
* frameActive
* New frame has started on this Head.
* histoReady
* Asserts when histogram data from all the "enabled" LTMs belonging to this head
* is ready.
* startFrameReady
* When histo_ready interrupt
* is received and HDMA is programmed and then RISCV asserts STARTFRAME_READY.
*/
typedef struct NV0073_LTM_HEAD_STATUS_PARAMS {
NvU8 tileMask;
NvBool frameActive;
NvBool histoReady;
NvBool startFrameReady;
} NV0073_LTM_HEAD_STATUS_PARAMS;
/* NV04_DISPLAY_COMMON event-related control commands and parameters */
/*
@@ -90,41 +109,4 @@ typedef struct NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001U)
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002U)
/*
* NV0073_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY
*
* hMemory
* This parameter specifies the handle of the memory object
* that identifies the memory address translation for this
* subdevice instance's notification(s). The beginning of the
* translation points to an array of notification data structures.
* The size of the translation must be at least large enough to hold the
* maximum number of notification data structures identified by
* the NV0073_MAX_NOTIFIERS value.
* Legal argument values must be instances of the following classes:
* NV01_NULL
* NV04_MEMORY
* When hMemory specifies the NV01_NULL_OBJECT value then any existing
* memory translation connection is cleared. There must not be any
* pending notifications when this command is issued.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0073_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x730303U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS {
NvU32 subDeviceInstance;
NvHandle hMemory;
} NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS;
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0U
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1U
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2U
/* _ctrl0073event_h_ */

34
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
View File

@@ -281,12 +281,10 @@ typedef struct NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS {
/* Faking Support commands */
/* some random value to enable/disable test code */
#define NV0073_FAKE_DEVICE_SUPPORT_ENABLE 0x11faU
#define NV0073_FAKE_DEVICE_SUPPORT_DISABLE 0x99ceU
#define NV0073_FAKE_DEVICE_SUPPORT_ATTACH_DEVICES 0x100U
#define NV0073_FAKE_DEVICE_SUPPORT_REMOVE_DEVICES 0x101U
#define NV0073_FAKE_DEVICE_SUPPORT_ENABLE 0x11faU
#define NV0073_FAKE_DEVICE_SUPPORT_DISABLE 0x99ceU
#define NV0073_FAKE_DEVICE_SUPPORT_ATTACH_DEVICES 0x100U
#define NV0073_FAKE_DEVICE_SUPPORT_REMOVE_DEVICES 0x101U
/*
* NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID
@@ -317,7 +315,7 @@ typedef struct NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS {
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID (0x730211U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID (0x730211U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID (0x11U)
@@ -2082,6 +2080,26 @@ typedef NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS NV0073_CTRL_SPECIFIC_
typedef NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS;
#define NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM (0x7302b0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM (0x7302b0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_CMD_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP
*
* The command returns the offset of the disp registers for sending timestamp
* directly to RISCV, so that clients may map them directly and write to this
* register which will trigger interrupt in RISCV.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP (0x7302b1U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS_MESSAGE_ID (0xB1U)
typedef struct NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS {
NvU32 subDeviceInstance;
NvU32 dispRegisterBase;
} NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS;
/* _ctrl0073specific_h_ */

198
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -1911,6 +1911,7 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_HUBCLK 0x0006
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_DISPCLK 0x0007
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_POSTRG_CLKS 0x0008
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_MSCG 0x0009
// Parameter/characteristics of Display ALPM
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_INVALID 0x0000
@@ -2031,6 +2032,66 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_GATE_TIME_US (0x0003)
/*!
* Property specifies current state of the specified clock
* i.e. Gated ot not Gated
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_STATUS (0x0004)
/*!
* @brief Parameter/characteristics of MSCG
*
* Following are the Parameter/characteristics for MSCG
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_INVALID (0x0000)
/*!
* Property specifies if DPS1 is supported
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_SUPPORT (0x0001)
/*!
* Property specifies if DPS2 is supported
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_SUPPORT (0x0002)
/*!
* Property specifies if MSCG is enabled
* (This property allows Get/SET operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_ENABLED (0x0003)
/*!
* Property specifies the time(in US) for which DPS1 was enabled
* in ACTIVE region
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_ACTIVE_TIME_US (0x0004)
/*!
* Property specifies the time(in US) for which DPS1 was enabled
* in VBLANK region
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_VBLANK_TIME_US (0x0005)
/*!
* Property specifies the time(in US) for which DPS2 was enabled
* in ACTIVE region
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_ACTIVE_TIME_US (0x0006)
/*!
* Property specifies the time(in US) for which DPS2 was enabled
* in VBLANK region
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_VBLANK_TIME_US (0x0007)
/*!
* @brief Structure to identify display low power feature
*
@@ -2203,6 +2264,143 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS {
NvBool bEnableDrr;
} NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_SET_DISPLAY_PERF_LIMIT
*
* This command sets lower and/or upper bounds for a display clock (dispclk or
* hubclk), or for the memory perf level. When this API is called, the system
* will immediately attempt to switch the clock or perf level to a value that
* meets the specified condition(s).
*
* If no lower limit is desired, the "min" input should be set to zero.
*
* If no upper limit is desired for a clock, the "max" input should be set to
* NV_U32_MAX.
*
* This API does not allow an upper limit to be specified for perf level.
*
* Any perf limit set through this API will remain in effect until it updated
* or cancelled by a subsequent call to this API. A perf limit may be
* cancelled by setting the "min" value to NV_U32_MIN (0) and the "max" value
* (for clocks) to NV_U32_MAX. Only one perf limit may be in effect for a
* given clientUsageId and type at any given time.
*
* At any given time, multiple perf limits (with different clientUsageIds) may
* be in effect for a given clock or perf level, and that clock or perf level
* will be set to a value that meets the requirements of all active perf
* limits. If there is a conflict between perf limits, the conflict will be
* resolved by the perf limit(s) with the higher priority.
*
* For example, suppose the API is called with the following parameters:
* clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS
* type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK
* data.clock.minFrequencyKHz = 800000
* data.clock.maxFrequencyKHz = 800000
* This will set dispclk to 800 MHz (or possibly a slightly higher frequency,
* if the clock dividers do not allow 800 MHz to be set exactly).
*
* Then suppose this call is made:
* clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE
* type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK
* data.clock.minFrequencyKHz = 1000000
* data.clock.maxFrequencyKHz = 0xFFFFFFFF
* After this call, dispclk will remain set to 800 MHz, because, although the
* min frequency was requested to be at least 1 GHz, this would conflict with
* the "maxFrequencyKHz = 800000" value set in the previous call, which is
* still in effect. The previous call takes priority because
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS has higher priority than
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE.
*
* Then suppose this call is made:
* clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS
* type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK
* data.clock.minFrequencyKHz = 0
* data.clock.maxFrequencyKHz = 0xFFFFFFFF
* This removes the NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS perf
* limit. At this point, dispclk will be set to 1 GHz, in accordance with the
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE perf limit,
* which is still in effect. (The remaining perf limit allows the clock to be
* higher than 1 GHz, but in practice, the clock will generally be set to the
* lowest frequency that meets the perf limit requirement, to save power. For
* perf level, perf monitors (which do not use the perf limit mechanism) may
* force a higher value in order to meet performance needs.)
*
* This API takes an array of perf limit structures, so multiple perf limits
* maybe set within the same call.
*
* This API is primarily intended for use on SOC products, where display is
* separate from the GPU. On dGPU products, this API may not be supported;
* instead, NV2080_CTRL_CMD_PERF_LIMITS_SET_STATUS_V2 may be used to set perf
* limits.
*
* subDeviceInstance (in)
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
*
* numLimits (in)
* This is the number of perf limits with lower and/or upper limits to
* apply.
*
* bWaitForCompletion (in)
* It is possible that a perf change or clock change may take some time to
* execute. If this flag is set, the API will wait for all of the changes
* to complete before returning. (However, it will not wait for completion
* of any operation that is blocked by a higher priority perf limit.)
*
* clientUsageId (in)
* This is a NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_xxx value
* indicating who the client is, and/or the purpose of the perf limit. It
* is used to establish priority between conflicting perf limits.
*
* whatIsToBeLimited (in)
* This is a NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_xxx value
* indicating which clock, or memory perf level, is to have limits applied.
*
* minLevelOrFreqKHz (in)
* maxLevelOrFreqKHz (in)
* If type is
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_PERF_LEVEL, then
* minLevelOrFreqKHz specifies the zero-based index of the minimum perf
* level to allow. maxLevelOrFreqKHz is not used.
*
* If type specifies a clock
* (NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK or
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_HUBCLK), then
* minLevelOrFreqKHz and maxLevelOrFreqKHz specify the lower and upper
* limits (respectively) for the specified clock's frequency.
*/
#define NV0073_CTRL_CMD_SYSTEM_SET_DISPLAY_PERF_LIMIT (0x73015aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS_MESSAGE_ID" */
/* valid clientUsageId values */
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE (0U)
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MCLK_SWITCH (1U)
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS (2U)
/* valid type values */
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_PERF_LEVEL (0U)
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_DISPCLK (1U)
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_HUBCLK (2U)
/* Define a structure for a single perf limit */
typedef struct NV0073_CTRL_SYSTEM_DISPLAY_PERF_LIMIT {
NvU8 clientUsageId;
NvU8 whatIsToBeLimited;
NvU32 minLevelOrFreqKHz;
NvU32 maxLevelOrFreqKHz;
} NV0073_CTRL_SYSTEM_DISPLAY_PERF_LIMIT;
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS_MESSAGE_ID (0x5AU)
typedef struct NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS {
NvU32 subDeviceInstance;
NvU32 numLimits;
NvBool bWaitForCompletion;
NV_DECLARE_ALIGNED(NvP64 limits, 8);
} NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO
*

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h
View File

@@ -226,7 +226,7 @@ typedef struct NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS {
NvU32 pteMemPfn;
NvU32 pageSize;
NvU32 startPageIndex;
NvU32 flags;
NV_DECLARE_ALIGNED(NvU64 flags, 8);
NvHandle hSrcVASpace;
NvHandle hTgtVASpace;
NvU32 peerId;

8
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
View File

@@ -596,6 +596,9 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS {
* vGPU heterogeneous mode on a GPU can only be set when the command
* is running in a vGPU host device.
*
* gpuInstanceId
* GPU Instance ID or Swizz ID
*
* bHeterogeneousMode
* This parameter set the vGPU heterogeneous mode of the device.
* Possible values are:
@@ -617,6 +620,7 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS {
typedef struct NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
NvBool bHeterogeneousMode;
NvU32 gpuInstanceId;
} NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS;
/**
@@ -625,6 +629,9 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
* This command returns a value indicating vGPU heterogeneous mode of
* the GPU.
*
* gpuInstanceId
* GPU Instance ID or Swizz ID
*
* bHeterogeneousMode
* This parameter returns the vGPU heterogeneous mode of the device.
* Possible values are:
@@ -643,6 +650,7 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
typedef struct NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS {
NvBool bHeterogeneousMode;
NvU32 gpuInstanceId;
} NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS;
/* _ctrl0080gpu_h_ */

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