mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-04 15:19:59 +00:00
575.51.02
This commit is contained in:
Bernhard Stoeckner
@@ -28,14 +28,6 @@
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extern "C" {
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#endif
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/*event values*/
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#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0)
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#define NV0000_NOTIFIERS_EVENT_NONE_PENDING (1)
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#define NV0000_NOTIFIERS_GPU_UNBIND_EVENT (2)
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#define NV0000_NOTIFIERS_GPU_BIND_EVENT (3)
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#define NV0000_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (4)
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#define NV0000_NOTIFIERS_MAXCOUNT (5)
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/*Status definitions for NV0000_NOTIFIERS_DISPLAY_CHANGE event*/
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#define NV0000_NOTIFIERS_STATUS_ACPI_DISPLAY_DEVICE_CYCLE (0)
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@@ -33,7 +33,8 @@ extern "C" {
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/* event values */
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#define NV0073_NOTIFIERS_SW (0)
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#define NV0073_NOTIFIERS_MAXCOUNT (5)
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#define NV0073_NOTIFIERS_LTM_CALC_TIMEOUT (5)
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#define NV0073_NOTIFIERS_MAXCOUNT (6)
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#define NV0073_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@@ -52,10 +52,11 @@ extern "C" {
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if (!RUSD_SEQ_DATA_VALID(RUSD_SEQ)) \
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continue;
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#define RUSD_SEQ_CHECK2(dataField) \
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portAtomicMemoryFenceLoad(); \
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if (RUSD_SEQ == (dataField)->lastModifiedTimestamp) \
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break;
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// Clear lastModifiedTimestamp on failure in case of reaching loop limit
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#define RUSD_SEQ_CHECK2(dataField) \
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portAtomicMemoryFenceLoad(); \
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if (RUSD_SEQ == (dataField)->lastModifiedTimestamp) \
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break; \
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//
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// Read RUSD data field `dataField` from NV00DE_SHARED_DATA struct `pSharedData` into destination pointer `pDst`
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@@ -70,6 +71,7 @@ do {
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RUSD_SEQ_CHECK1(&((pSharedData)->dataField)); \
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portMemCopy((pDst), sizeof(*pDst), &((pSharedData)->dataField), sizeof(*pDst)); \
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RUSD_SEQ_CHECK2(&((pSharedData)->dataField)); \
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(pDst)->lastModifiedTimestamp = RUSD_TIMESTAMP_INVALID; \
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} \
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} while(0);
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@@ -164,10 +166,32 @@ typedef struct RUSD_PERF_CURRENT_PSTATE {
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NvU32 currentPstate;
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} RUSD_PERF_CURRENT_PSTATE;
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typedef struct RUSD_CLK_THROTTLE_REASON {
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#define RUSD_CLK_VIOLATION_NUM 32
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#define RUSD_PERF_POINT_MAX_CLOCK 0
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#define RUSD_PERF_POINT_TURBO_BOOST 1
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#define RUSD_PERF_POINT_3D_BOOST 2
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#define RUSD_PERF_POINT_RATED_TDP 3
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#define RUSD_PERF_POINT_MAX_CUSTOMER_BOOST 4
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#define RUSD_PERF_POINT_DISPLAY_CLOCK_INTERSECT 5
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#define RUSD_PERF_POINT_NUM 6
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typedef struct RUSD_CLK_VIOLATION_STATUS {
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NvU32 perfPointMask;
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NvU64 timeNs[RUSD_PERF_POINT_NUM];
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} RUSD_CLK_VIOLATION_STATUS;
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typedef struct RUSD_CLK_THROTTLE_INFO {
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volatile NvU64 lastModifiedTimestamp;
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NvU32 reasonMask; // Bitmask of RUSD_CLK_THROTTLE_REASON_*
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} RUSD_CLK_THROTTLE_REASON;
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NvU64 referenceTimeNs;
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NvU32 supportedViolationTimeMask;
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RUSD_CLK_VIOLATION_STATUS violation[RUSD_CLK_VIOLATION_NUM];
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RUSD_CLK_VIOLATION_STATUS globalViolation;
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} RUSD_CLK_THROTTLE_INFO;
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typedef struct RUSD_CLK_THROTTLE_INFO RUSD_CLK_THROTTLE_REASON;
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typedef struct RUSD_MEM_ERROR_COUNTS {
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NvU64 correctedVolatile;
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@@ -197,8 +221,21 @@ typedef struct RUSD_POWER_LIMITS {
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RUSD_POWER_LIMIT_INFO info;
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} RUSD_POWER_LIMITS;
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typedef enum RUSD_TEMPERATURE_SENSOR {
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RUSD_TEMPERATURE_SENSOR_GPU,
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RUSD_TEMPERATURE_SENSOR_MEMORY,
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RUSD_TEMPERATURE_SENSOR_BOARD,
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RUSD_TEMPERATURE_SENSOR_POWER_SUPPLY,
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// Should always be last entry
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RUSD_TEMPERATURE_SENSOR_MAX
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} RUSD_TEMPERATURE_SENSOR;
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typedef enum RUSD_TEMPERATURE_TYPE {
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RUSD_TEMPERATURE_TYPE_GPU,
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RUSD_TEMPERATURE_TYPE_MEMORY,
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RUSD_TEMPERATURE_TYPE_BOARD,
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RUSD_TEMPERATURE_TYPE_POWER_SUPPLY,
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RUSD_TEMPERATURE_TYPE_HBM,
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RUSD_TEMPERATURE_TYPE_MAX
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} RUSD_TEMPERATURE_TYPE;
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@@ -208,9 +245,6 @@ typedef struct RUSD_TEMPERATURE {
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NvTemp temperature;
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} RUSD_TEMPERATURE;
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// Temporary until clients can migrate to using RUSD_TEMPERATURE type name
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typedef RUSD_TEMPERATURE RUSD_TEMPERATURE_GENERIC;
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typedef struct RUSD_MEM_ROW_REMAP_INFO {
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// Provided from NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM
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NvU32 histogramMax; // No remapped row is used.
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@@ -252,6 +286,26 @@ typedef struct RUSD_INST_POWER_USAGE {
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RUSD_INST_POWER_INFO info;
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} RUSD_INST_POWER_USAGE;
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typedef struct RUSD_POWER_POLICY_STATUS_INFO {
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NvU32 tgpmW; // Total GPU power in mW
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} RUSD_POWER_POLICY_STATUS_INFO;
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typedef struct RUSD_POWER_POLICY_STATUS {
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volatile NvU64 lastModifiedTimestamp;
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RUSD_POWER_POLICY_STATUS_INFO info;
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} RUSD_POWER_POLICY_STATUS;
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#define RUSD_FAN_COOLER_MAX_COOLERS 16U
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typedef struct RUSD_FAN_COOLER_INFO {
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NvU32 rpmCurr[RUSD_FAN_COOLER_MAX_COOLERS];
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} RUSD_FAN_COOLER_INFO;
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typedef struct RUSD_FAN_COOLER_STATUS {
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volatile NvU64 lastModifiedTimestamp;
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RUSD_FAN_COOLER_INFO info;
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} RUSD_FAN_COOLER_STATUS;
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typedef struct RUSD_SHADOW_ERR_CONT {
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volatile NvU64 lastModifiedTimestamp;
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//
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@@ -313,7 +367,7 @@ typedef struct NV00DE_SHARED_DATA {
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NV_DECLARE_ALIGNED(RUSD_CLK_PUBLIC_DOMAIN_INFOS clkPublicDomainInfos, 8);
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// POLL_PERF
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NV_DECLARE_ALIGNED(RUSD_CLK_THROTTLE_REASON clkThrottleReason, 8);
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NV_DECLARE_ALIGNED(RUSD_CLK_THROTTLE_INFO clkThrottleInfo, 8);
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// POLL_PERF
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NV_DECLARE_ALIGNED(RUSD_PERF_DEVICE_UTILIZATION perfDevUtil, 8);
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@@ -340,8 +394,14 @@ typedef struct NV00DE_SHARED_DATA {
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// POLL_POWER
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NV_DECLARE_ALIGNED(RUSD_INST_POWER_USAGE instPowerUsage, 8);
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// POLL_POWER
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NV_DECLARE_ALIGNED(RUSD_POWER_POLICY_STATUS powerPolicyStatus, 8);
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// POLL_PCI
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NV_DECLARE_ALIGNED(RUSD_PCIE_DATA pciBusData, 8);
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// POLL_FAN
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NV_DECLARE_ALIGNED(RUSD_FAN_COOLER_STATUS fanCoolerStatus, 8);
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} NV00DE_SHARED_DATA;
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//
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@@ -354,6 +414,7 @@ typedef struct NV00DE_SHARED_DATA {
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#define NV00DE_RUSD_POLL_POWER 0x8
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#define NV00DE_RUSD_POLL_THERMAL 0x10
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#define NV00DE_RUSD_POLL_PCI 0x20
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#define NV00DE_RUSD_POLL_FAN 0x40
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typedef struct NV00DE_ALLOC_PARAMETERS {
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NvU64 polledDataMask; // Bitmask of data to request polling at alloc time, 0 if not needed
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39
src/common/sdk/nvidia/inc/class/cl0101.h
Normal file
39
src/common/sdk/nvidia/inc/class/cl0101.h
Normal file
@@ -0,0 +1,39 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
|
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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||||
* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: class/cl0101.finn
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//
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/*
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* LOCK_TEST_RELAXED_DUP_OBJECT
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* An object used for testing the relaxed GPU lock for RMDUP operation.
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* Can be allocated only if PDB_PROP_SYS_ENABLE_RM_TEST_ONLY_CODE is set.
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*/
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#define LOCK_TEST_RELAXED_DUP_OBJECT 0x0101U
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@@ -236,7 +236,8 @@ extern "C" {
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#define NV2080_NOTIFIERS_POWER_RESUME (194)
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#define NV2080_NOTIFIERS_CTXSW_UCODE_ERROR (195)
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#define NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD (196)
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#define NV2080_NOTIFIERS_MAXCOUNT (197)
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#define NV2080_NOTIFIERS_GPU_RC_RESET (197)
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#define NV2080_NOTIFIERS_MAXCOUNT (198)
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// Indexed GR notifier reference
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#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))
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@@ -31,10 +31,10 @@ typedef struct NV_RATS_GSP_TRACE_RECORD_V1
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{
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NvU16 seqNo;
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NvU16 gspSeqNo;
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NvU32 info;
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NvU64 recordType;
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NvU32 threadId;
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NvU64 info;
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NvU64 timeStamp;
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NvU64 threadId;
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NvU64 recordType;
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} NV_RATS_GSP_TRACE_RECORD_V1;
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typedef NV_RATS_GSP_TRACE_RECORD_V1 NV_RATS_GSP_TRACE_RECORD;
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@@ -1,5 +1,5 @@
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/*
|
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* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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@@ -76,18 +76,6 @@ typedef struct NVA084_ALLOC_PARAMETERS {
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NvBool bDisableDefaultSmcExecPartRestore;
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NvU32 vgpuDeviceInstanceId;
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NvHandle hPluginClient;
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NvU32 numGuestFbHandles;
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NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS];
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NvU8 vgpuDevName[VM_UUID_SIZE];
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NvHandle hPluginHeapMemory;
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NvHandle hMigRmHeapMemory;
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NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8);
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NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffOffset, 8);
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NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8);
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NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8);
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NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8);
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NV_DECLARE_ALIGNED(NvU64 kernelLogBuffOffset, 8);
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NV_DECLARE_ALIGNED(NvU64 kernelLogBuffSize, 8);
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NvBool bDeviceProfilingEnabled;
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NvBool bGpupLiveMigrationEnabled;
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} NVA084_ALLOC_PARAMETERS;
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|
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@@ -34,8 +34,7 @@ extern "C" {
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#define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT
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#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_BEGIN + (0)
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#define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1)
|
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#define NVC370_NOTIFIERS_LTM_CALC_TIMEOUT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1)
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#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_LTM_CALC_TIMEOUT + (1)
|
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#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1)
|
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|
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#ifdef __cplusplus
|
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}; /* extern "C" */
|
||||
|
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@@ -24,6 +24,8 @@
|
||||
#ifndef __gh100_clc86f_h__
|
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#define __gh100_clc86f_h__
|
||||
|
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#define HOPPER_CHANNEL_GPFIFO_A (0x0000C86F)
|
||||
|
||||
typedef volatile struct Nvc86fControl_struct {
|
||||
NvU32 Ignored00[0x010]; /* 0000-003f*/
|
||||
NvU32 Put; /* put offset, read/write 0040-0043*/
|
||||
@@ -42,54 +44,7 @@ typedef volatile struct Nvc86fControl_struct {
|
||||
NvU32 Ignored05[0x5c];
|
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} Nvc86fControl, HopperAControlGPFifo;
|
||||
|
||||
#define HOPPER_CHANNEL_GPFIFO_A (0x0000C86F)
|
||||
#define NVC86F_SET_OBJECT (0x00000000)
|
||||
#define NVC86F_SEM_ADDR_LO (0x0000005c)
|
||||
#define NVC86F_SEM_ADDR_LO_OFFSET 31:2
|
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#define NVC86F_SEM_ADDR_HI (0x00000060)
|
||||
#define NVC86F_SEM_ADDR_HI_OFFSET 24:0
|
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#define NVC86F_SEM_PAYLOAD_LO (0x00000064)
|
||||
#define NVC86F_SEM_PAYLOAD_HI (0x00000068)
|
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#define NVC86F_SEM_EXECUTE (0x0000006c)
|
||||
#define NVC86F_SEM_EXECUTE_OPERATION 2:0
|
||||
#define NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
|
||||
#define NVC86F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
|
||||
#define NVC86F_SEM_EXECUTE_RELEASE_WFI 20:20
|
||||
#define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
|
||||
#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
|
||||
#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
|
||||
|
||||
/* GPFIFO entry format */
|
||||
#define NVC86F_GP_ENTRY__SIZE 8
|
||||
#define NVC86F_GP_ENTRY0_FETCH 0:0
|
||||
#define NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
|
||||
#define NVC86F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
|
||||
#define NVC86F_GP_ENTRY0_GET 31:2
|
||||
#define NVC86F_GP_ENTRY0_OPERAND 31:0
|
||||
#define NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8
|
||||
#define NVC86F_GP_ENTRY1_GET_HI 7:0
|
||||
#define NVC86F_GP_ENTRY1_LEVEL 9:9
|
||||
#define NVC86F_GP_ENTRY1_LEVEL_MAIN 0x00000000
|
||||
#define NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
|
||||
#define NVC86F_GP_ENTRY1_LENGTH 30:10
|
||||
#define NVC86F_GP_ENTRY1_SYNC 31:31
|
||||
#define NVC86F_GP_ENTRY1_SYNC_PROCEED 0x00000000
|
||||
#define NVC86F_GP_ENTRY1_SYNC_WAIT 0x00000001
|
||||
#define NVC86F_GP_ENTRY1_OPCODE 7:0
|
||||
#define NVC86F_GP_ENTRY1_OPCODE_NOP 0x00000000
|
||||
#define NVC86F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
|
||||
#define NVC86F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
|
||||
#define NVC86F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
|
||||
#define NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004
|
||||
|
||||
|
||||
#define NVC86F_WFI (0x00000078)
|
||||
#define NVC86F_WFI_SCOPE 0:0
|
||||
#define NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000
|
||||
#define NVC86F_WFI_SCOPE_CURRENT_VEID 0x00000000
|
||||
#define NVC86F_WFI_SCOPE_ALL 0x00000001
|
||||
|
||||
|
||||
// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
|
||||
// specifying the page address for a targeted TLB invalidate and the uTLB for
|
||||
// a targeted REPLAY_CANCEL for UVM.
|
||||
@@ -184,6 +139,53 @@ typedef volatile struct Nvc86fControl_struct {
|
||||
#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE 23:20
|
||||
#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED 0x00000000
|
||||
#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP 0x00000001
|
||||
#define NVC86F_SEM_ADDR_LO (0x0000005c)
|
||||
#define NVC86F_SEM_ADDR_LO_OFFSET 31:2
|
||||
#define NVC86F_SEM_ADDR_HI (0x00000060)
|
||||
#define NVC86F_SEM_ADDR_HI_OFFSET 24:0
|
||||
#define NVC86F_SEM_PAYLOAD_LO (0x00000064)
|
||||
#define NVC86F_SEM_PAYLOAD_HI (0x00000068)
|
||||
#define NVC86F_SEM_EXECUTE (0x0000006c)
|
||||
#define NVC86F_SEM_EXECUTE_OPERATION 2:0
|
||||
#define NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
|
||||
#define NVC86F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
|
||||
#define NVC86F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003
|
||||
#define NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12
|
||||
#define NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001
|
||||
#define NVC86F_SEM_EXECUTE_RELEASE_WFI 20:20
|
||||
#define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
|
||||
#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
|
||||
#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
|
||||
#define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25
|
||||
#define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000
|
||||
#define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001
|
||||
#define NVC86F_WFI (0x00000078)
|
||||
#define NVC86F_WFI_SCOPE 0:0
|
||||
#define NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000
|
||||
#define NVC86F_WFI_SCOPE_CURRENT_VEID 0x00000000
|
||||
#define NVC86F_WFI_SCOPE_ALL 0x00000001
|
||||
|
||||
/* GPFIFO entry format */
|
||||
#define NVC86F_GP_ENTRY__SIZE 8
|
||||
#define NVC86F_GP_ENTRY0_FETCH 0:0
|
||||
#define NVC86F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
|
||||
#define NVC86F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
|
||||
#define NVC86F_GP_ENTRY0_GET 31:2
|
||||
#define NVC86F_GP_ENTRY0_OPERAND 31:0
|
||||
#define NVC86F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8
|
||||
#define NVC86F_GP_ENTRY1_GET_HI 7:0
|
||||
#define NVC86F_GP_ENTRY1_LEVEL 9:9
|
||||
#define NVC86F_GP_ENTRY1_LEVEL_MAIN 0x00000000
|
||||
#define NVC86F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
|
||||
#define NVC86F_GP_ENTRY1_LENGTH 30:10
|
||||
#define NVC86F_GP_ENTRY1_SYNC 31:31
|
||||
#define NVC86F_GP_ENTRY1_SYNC_PROCEED 0x00000000
|
||||
#define NVC86F_GP_ENTRY1_SYNC_WAIT 0x00000001
|
||||
#define NVC86F_GP_ENTRY1_OPCODE 7:0
|
||||
#define NVC86F_GP_ENTRY1_OPCODE_NOP 0x00000000
|
||||
#define NVC86F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
|
||||
#define NVC86F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
|
||||
#define NVC86F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
|
||||
#define NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004
|
||||
|
||||
#endif // __gh100_clc86f_h__
|
||||
|
||||
@@ -23,22 +23,38 @@
|
||||
|
||||
#ifndef __gh100_clc8b5_h__
|
||||
#define __gh100_clc8b5_h__
|
||||
#define HOPPER_DMA_COPY_A (0x0000C8B5)
|
||||
|
||||
#define HOPPER_DMA_COPY_A (0x0000C8B5)
|
||||
#define NVC8B5_SET_SEMAPHORE_A (0x00000240)
|
||||
#define NVC8B5_SET_SEMAPHORE_A_UPPER 24:0
|
||||
#define NVC8B5_SET_SEMAPHORE_B (0x00000244)
|
||||
#define NVC8B5_SET_SEMAPHORE_B_LOWER 31:0
|
||||
#define NVC8B5_SET_SEMAPHORE_PAYLOAD (0x00000248)
|
||||
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET 1:0
|
||||
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
|
||||
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
|
||||
#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM (0x00000003)
|
||||
#define NVC8B5_SET_SRC_PHYS_MODE_PEER_ID 8:6
|
||||
#define NVC8B5_SET_SRC_PHYS_MODE_FLA 9:9
|
||||
#define NVC8B5_SET_DST_PHYS_MODE (0x00000264)
|
||||
#define NVC8B5_SET_DST_PHYS_MODE_TARGET 1:0
|
||||
#define NVC8B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
|
||||
#define NVC8B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
|
||||
#define NVC8B5_SET_DST_PHYS_MODE_TARGET_PEERMEM (0x00000003)
|
||||
#define NVC8B5_LAUNCH_DMA (0x00000300)
|
||||
#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0
|
||||
#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000)
|
||||
#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002)
|
||||
#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE 2:2
|
||||
#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000)
|
||||
#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE 25:25
|
||||
#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_SYS (0x00000000)
|
||||
#define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_GL (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3
|
||||
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP (0x00000002)
|
||||
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7
|
||||
#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001)
|
||||
@@ -48,18 +64,34 @@
|
||||
#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000)
|
||||
#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE 10:10
|
||||
#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000)
|
||||
#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_SRC_TYPE 12:12
|
||||
#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13
|
||||
#define NVC8B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000)
|
||||
#define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14
|
||||
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006)
|
||||
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18
|
||||
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19
|
||||
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_COPY_TYPE 21:20
|
||||
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT (0x00000000)
|
||||
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_DEFAULT (0x00000000)
|
||||
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_SECURE (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT (0x00000002)
|
||||
#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23
|
||||
#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE (0x00000000)
|
||||
#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_DISABLE_PLC 26:26
|
||||
#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001)
|
||||
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE 27:27
|
||||
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD (0x00000000)
|
||||
#define NVC8B5_OFFSET_IN_UPPER (0x00000400)
|
||||
#define NVC8B5_OFFSET_IN_UPPER_UPPER 24:0
|
||||
#define NVC8B5_OFFSET_IN_LOWER (0x00000404)
|
||||
#define NVC8B5_OFFSET_IN_LOWER_VALUE 31:0
|
||||
#define NVC8B5_OFFSET_OUT_UPPER (0x00000408)
|
||||
#define NVC8B5_OFFSET_OUT_UPPER_UPPER 24:0
|
||||
#define NVC8B5_OFFSET_OUT_LOWER (0x0000040C)
|
||||
@@ -90,8 +122,12 @@
|
||||
#define NVC8B5_SET_REMAP_COMPONENTS_DST_X 2:0
|
||||
#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004)
|
||||
#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005)
|
||||
#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y 6:4
|
||||
#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005)
|
||||
#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16
|
||||
#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000)
|
||||
#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003)
|
||||
#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24
|
||||
#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000)
|
||||
#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001)
|
||||
#endif // __gh100_clc8b5_h__
|
||||
|
||||
@@ -24,15 +24,52 @@
|
||||
#ifndef __gb100_clc96f_h__
|
||||
#define __gb100_clc96f_h__
|
||||
|
||||
#define BLACKWELL_CHANNEL_GPFIFO_A (0x0000C96F)
|
||||
|
||||
typedef volatile struct Nvc96fControl_struct {
|
||||
NvU32 Ignored00[0x23]; /* 0000-008b*/
|
||||
NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
|
||||
NvU32 Ignored01[0x5c];
|
||||
} Nvc96fControl, BlackwellAControlGPFifo;
|
||||
|
||||
#define BLACKWELL_CHANNEL_GPFIFO_A (0x0000C96F)
|
||||
|
||||
#define NVC96F_SET_OBJECT (0x00000000)
|
||||
#define NVC96F_MEM_OP_A (0x00000028)
|
||||
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type
|
||||
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE 7:6 // only relevant for invalidates with NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE for invalidating link TLB only, or non-link TLB only or all TLBs
|
||||
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 2
|
||||
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11
|
||||
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001
|
||||
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000
|
||||
#define NVC96F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12
|
||||
#define NVC96F_MEM_OP_B (0x0000002c)
|
||||
#define NVC96F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0
|
||||
#define NVC96F_MEM_OP_C (0x00000030)
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002
|
||||
#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE
|
||||
|
||||
#define NVC96F_MEM_OP_D (0x00000034)
|
||||
#define NVC96F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE
|
||||
#define NVC96F_MEM_OP_D_OPERATION 31:27
|
||||
#define NVC96F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
|
||||
#define NVC96F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a
|
||||
|
||||
#define NVC96F_SEM_ADDR_LO (0x0000005c)
|
||||
#define NVC96F_SEM_ADDR_LO_OFFSET 31:2
|
||||
#define NVC96F_SEM_ADDR_HI (0x00000060)
|
||||
|
||||
41
src/common/sdk/nvidia/inc/class/clcb70.h
Normal file
41
src/common/sdk/nvidia/inc/class/clcb70.h
Normal file
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <nvtypes.h>
|
||||
|
||||
//
|
||||
// This file was generated with FINN, an NVIDIA coding tool.
|
||||
// Source file: class/clcb70.finn
|
||||
//
|
||||
|
||||
#define NVCB70_DISPLAY (0xcb70U) /* finn: Evaluated from "NVCB70_ALLOCATION_PARAMETERS_MESSAGE_ID" */
|
||||
|
||||
#define NVCB70_ALLOCATION_PARAMETERS_MESSAGE_ID (0xcb70U)
|
||||
|
||||
typedef struct NVCB70_ALLOCATION_PARAMETERS {
|
||||
NvU32 numHeads; // Number of HEADs in this chip/display
|
||||
NvU32 numSors; // Number of SORs in this chip/display
|
||||
NvU32 numDsis; // Number of DSIs in this chip/display
|
||||
} NVCB70_ALLOCATION_PARAMETERS;
|
||||
|
||||
186
src/common/sdk/nvidia/inc/class/clcb71.h
Normal file
186
src/common/sdk/nvidia/inc/class/clcb71.h
Normal file
@@ -0,0 +1,186 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _clcb71_h_
|
||||
#define _clcb71_h_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define NVCB71_DISP_SF_USER (0x000CB71)
|
||||
|
||||
typedef volatile struct _clcb71_tag0 {
|
||||
NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */
|
||||
} _NvCB71DispSfUser, NvCB71DispSfUserMap;
|
||||
|
||||
#define NVCB71_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
|
||||
#define NVCB71_SF_HDMI_INFO_CTRL__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_HDMI_INFO_CTRL__SIZE_2 3 /* */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
|
||||
#define NVCB71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL(i,j) (0x000E0130-0x000E0000+(i)*1024+(j)*8) /* RW-4A */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL__SIZE_2 10 /* */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE 3:1 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ALWAYS 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ONCE 0x00000001 /* RW--V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ALWAYS 0x00000002 /* RW--V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ONCE 0x00000003 /* RW--V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_TRIGGER 0x00000004 /* RW--V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_LOC 5:4 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_LOC_VSYNC 0x00000001 /* RW--V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_LOC_LINE 0x00000002 /* RW--V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_OFFSET 10:6 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SIZE 18:14 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SIZE_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_BUSY 22:22 /* R-IVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_BUSY_NO 0x00000000 /* R-I-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_BUSY_YES 0x00000001 /* R---V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SENT 23:23 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SENT_NO 0x00000000 /* R-I-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SENT_YES 0x00000001 /* R---V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CTRL_SENT_CLEAR 0x00000001 /* -W--C */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG(i,j) (0x000E0134-0x000E0000+(i)*1024+(j)*8) /* RW-4A */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_2 10 /* */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_FID 7:0 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_FID_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID 23:8 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED 24:24 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_NO 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_YES 0x00000001 /* RW--V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN 25:25 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_NO 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_YES 0x00000001 /* RW--V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM 29:29 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_NO 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_YES 0x00000001 /* RW--V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW 30:30 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW_INIT 0x00000000 /* R-I-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW_DONE 0x00000000 /* R---V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW_PENDING 0x00000001 /* R---T */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_NEW_TRIGGER 0x00000001 /* -W--T */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL 31:31 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ACT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ARM 0x00000001 /* RW--V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_CTRL(i) (0x000E03F0-0x000E0000+(i)*1024) /* RW-4A */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_CTRL__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET 4:0 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA(i) (0x000E03F4-0x000E0000+(i)*1024) /* RW-4A */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE0 7:0 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE0_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE1 15:8 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE1_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE2 23:16 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE2_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE3 31:24 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_DATA_BYTE3_INIT 0x00000000 /* RWI-V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL(i) (0x000E03F8-0x000E0000+(i)*1024) /* RW-4A */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL__SIZE_1 8 /* */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY 1:1 /* RWIVF */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_HIGH 0x00000000 /* RW--V */
|
||||
#define NVCB71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_LOW 0x00000001 /* RWI-V */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}; /* extern "C" */
|
||||
#endif
|
||||
|
||||
#endif // _clcb71_h_
|
||||
915
src/common/sdk/nvidia/inc/class/clcb73.h
Normal file
915
src/common/sdk/nvidia/inc/class/clcb73.h
Normal file
@@ -0,0 +1,915 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _clcb73_h_
|
||||
#define _clcb73_h_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define NVCB73_DISP_CAPABILITIES 0xCB73
|
||||
|
||||
typedef volatile struct _clcb73_tag0 {
|
||||
NvU32 dispCapabilities[0x400];
|
||||
} _NvCB73DispCapabilities,NvCB73DispCapabilities_Map ;
|
||||
|
||||
|
||||
#define NVCB73_SYS_CAP 0x0 /* RW-4R */
|
||||
#define NVCB73_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
|
||||
#define NVCB73_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */
|
||||
#define NVCB73_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_RISCV0_EXISTS 16:16 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_RISCV0_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_RISCV0_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */
|
||||
#define NVCB73_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */
|
||||
#define NVCB73_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB 0x4 /* RW-4R */
|
||||
#define NVCB73_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
|
||||
#define NVCB73_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */
|
||||
#define NVCB73_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC 0x20 /* RW-4R */
|
||||
#define NVCB73_SYS_CAPC_TILE0_EXISTS 0:0 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE0_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE0_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE1_EXISTS 1:1 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE1_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE1_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE2_EXISTS 2:2 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE2_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE2_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE3_EXISTS 3:3 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE3_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE3_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE4_EXISTS 4:4 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE4_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE4_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE5_EXISTS 5:5 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE5_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE5_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE6_EXISTS 6:6 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE6_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE6_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE7_EXISTS 7:7 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE7_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE7_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE_EXISTS__SIZE_1 8 /* */
|
||||
#define NVCB73_SYS_CAPC_TILE_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE 8:8 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE 9:9 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE 10:10 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE 11:11 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE 12:12 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE 13:13 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE 14:14 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE 15:15 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE(i) (8+(i)):(8+(i)) /* RWIVF */
|
||||
#define NVCB73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE__SIZE_1 8 /* */
|
||||
#define NVCB73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPC_MERGER_TILE_BUFFER_SIZE 31:16 /* RWIUF */
|
||||
#define NVCB73_SYS_CAPD 0x2c /* RW-4R */
|
||||
#define NVCB73_SYS_CAPD_NUM_TELLTALE_REGIONS 4:0 /* RWIUF */
|
||||
#define NVCB73_SYS_CAPD_NUM_FROZEN_FRAME_REGIONS 12:8 /* RWIUF */
|
||||
#define NVCB73_SYS_CAPD_NUM_ROI 20:16 /* RWIUF */
|
||||
#define NVCB73_SYS_CAPD_AE_SDP_EXISTS 30:30 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPD_AE_SDP_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPD_AE_SDP_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPD_AMSS_EXISTS 31:31 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPD_AMSS_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPD_AMSS_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE 0x34 /* RW-4R */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN0_EXISTS 0:0 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN0_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN0_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN1_EXISTS 1:1 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN1_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN1_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN2_EXISTS 2:2 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN2_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN2_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN3_EXISTS 3:3 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN3_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN3_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN4_EXISTS 4:4 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN4_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN4_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN5_EXISTS 5:5 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN5_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN5_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN6_EXISTS 6:6 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN6_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN6_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN7_EXISTS 7:7 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN7_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN7_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN8_EXISTS 8:8 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN8_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN8_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN9_EXISTS 9:9 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN9_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN9_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN10_EXISTS 10:10 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN10_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN10_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN11_EXISTS 11:11 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN11_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN11_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN12_EXISTS 12:12 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN12_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN12_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN13_EXISTS 13:13 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN13_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN13_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN14_EXISTS 14:14 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN14_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN14_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN15_EXISTS 15:15 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN15_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN15_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN16_EXISTS 16:16 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN16_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN16_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN17_EXISTS 17:17 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN17_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN17_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN18_EXISTS 18:18 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN18_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN18_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN19_EXISTS 19:19 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN19_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN19_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN20_EXISTS 20:20 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN20_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN20_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN21_EXISTS 21:21 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN21_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN21_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN22_EXISTS 22:22 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN22_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN22_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN23_EXISTS 23:23 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN23_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN23_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN24_EXISTS 24:24 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN24_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN24_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN25_EXISTS 25:25 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN25_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN25_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN26_EXISTS 26:26 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN26_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN26_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN27_EXISTS 27:27 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN27_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN27_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN28_EXISTS 28:28 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN28_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN28_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN29_EXISTS 29:29 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN29_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN29_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN30_EXISTS 30:30 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN30_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN30_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN31_EXISTS 31:31 /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN31_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN31_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN_EXISTS__SIZE_1 32 /* */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_SYS_CAPE_VIRWIN_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_MISC_CAPA_NUM_VMS 17:13 /* RWIUF */
|
||||
#define NVCB73_LINK_CAP 0x30 /* RW-4R */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL0_EXISTS 0:0 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL0_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL0_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL1_EXISTS 1:1 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL1_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL1_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL2_EXISTS 2:2 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL2_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL2_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL3_EXISTS 3:3 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL3_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL3_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL4_EXISTS 4:4 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL4_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL4_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL5_EXISTS 5:5 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL5_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL5_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL6_EXISTS 6:6 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL6_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL6_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL7_EXISTS 7:7 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL7_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL7_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL8_EXISTS 8:8 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL8_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL8_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL9_EXISTS 9:9 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL9_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL9_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL10_EXISTS 10:10 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL10_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL10_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL11_EXISTS 11:11 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL11_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL11_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL12_EXISTS 12:12 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL12_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL12_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL13_EXISTS 13:13 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL13_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL13_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL14_EXISTS 14:14 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL14_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL14_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL15_EXISTS 15:15 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL15_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL15_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL16_EXISTS 16:16 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL16_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL16_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL17_EXISTS 17:17 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL17_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL17_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL18_EXISTS 18:18 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL18_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL18_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL19_EXISTS 19:19 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL19_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL19_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL20_EXISTS 20:20 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL20_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL20_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL21_EXISTS 21:21 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL21_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL21_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL22_EXISTS 22:22 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL22_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL22_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL23_EXISTS 23:23 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL23_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL23_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL24_EXISTS 24:24 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL24_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL24_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL25_EXISTS 25:25 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL25_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL25_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL26_EXISTS 26:26 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL26_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL26_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL27_EXISTS 27:27 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL27_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL27_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL28_EXISTS 28:28 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL28_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL28_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL29_EXISTS 29:29 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL29_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL29_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL30_EXISTS 30:30 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL30_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL30_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL31_EXISTS 31:31 /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL31_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL31_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL_EXISTS__SIZE_1 32 /* */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL_EXISTS_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_LINK_CAP_PHYCTRL_EXISTS_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA 0x10 /* RW-4R */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS 26:26 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC 0x18 /* RW-4R */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION 13:13 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_TRUE 0x00000001 /* RWI-V */
|
||||
#define NVCB73_IHUB_COMMON_CAPE 0x24 /* RW-4R */
|
||||
#define NVCB73_IHUB_COMMON_CAPE_PHYWIN_BUFFER_SIZE 15:0 /* RWIUF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF 0x28 /* RW-4R */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE 0:0 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE 1:1 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE 2:2 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE 3:3 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE 4:4 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE 5:5 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE 6:6 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE 7:7 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE 8:8 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE 9:9 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE 10:10 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE 11:11 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE 12:12 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE 13:13 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE 14:14 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE 15:15 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE 16:16 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE 17:17 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE 18:18 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE 19:19 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE 20:20 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE 21:21 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE 22:22 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE 23:23 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE 24:24 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE 25:25 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE 26:26 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE 27:27 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE 28:28 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE 29:29 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE 30:30 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE 31:31 /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE(i) (0+(i)):(0+(i)) /* RWIVF */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE__SIZE_1 32 /* */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
|
||||
#define NVCB73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA__SIZE_1 8 /* */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_LTM_PRESENT 25:25 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_LTM_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPA_LTM_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB__SIZE_1 8 /* */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB_VGA 0:0 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_SZ 12:1 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_LOGNR 15:13 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD 17:17 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_DIRECT 18:18 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC__SIZE_1 8 /* */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPD__SIZE_1 8 /* */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE__SIZE_1 8 /* */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_MAXLINEWIDTH 15:0 /* RWIUF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT 18:18 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE 21:19 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_9x9x9 0x00000000 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_17x17x17 0x00000001 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_25x25x25 0x00000002 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_33x33x33 0x00000003 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_4 0x00000004 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_5 0x00000005 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_6 0x00000006 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_7 0x00000007 /* RW--V */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPE_3DLUT_NUM_CURVES 23:22 /* RWIUF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPF__SIZE_1 8 /* */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPF_LTM_MAX_PIXELS 31:16 /* RWIVF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPG(i) (0x698+(i)*32) /* RW-4A */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPG__SIZE_1 8 /* */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPG_CMI_SZ 11:0 /* RWIUF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPG_CMI_LOGNR 14:12 /* RWIUF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPG_CMO_SZ 26:15 /* RWIUF */
|
||||
#define NVCB73_POSTCOMP_HDR_CAPG_CMO_LOGNR 29:27 /* RWIUF */
|
||||
#define NVCB73_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */
|
||||
#define NVCB73_SOR_CAP__SIZE_1 8 /* */
|
||||
#define NVCB73_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_DUAL_MODE 4:4 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_DP_DUAL_MODE_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_DUAL_MODE_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_TUNNELING_OVER_USB4 15:15 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_DP_TUNNELING_OVER_USB4_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_TUNNELING_OVER_USB4_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_SDI 16:16 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_DUAL_MST 23:23 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_DP_DUAL_MST_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_DUAL_MST_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_A 24:24 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_B 25:25 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_HDMI_FRL_YUV422 29:29 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_HDMI_FRL_YUV422_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_HDMI_FRL_YUV422_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_128B132B 30:30 /* RWIVF */
|
||||
#define NVCB73_SOR_CAP_DP_128B132B_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_SOR_CAP_DP_128B132B_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT 13:13 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT 13:13 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
|
||||
#define NVCB73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
|
||||
#define NVCB73_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */
|
||||
#define NVCB73_SOR_CLK_CAP__SIZE_1 8 /* */
|
||||
#define NVCB73_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */
|
||||
#define NVCB73_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */
|
||||
#define NVCB73_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */
|
||||
|
||||
#ifdef __cplusplus
|
||||
};
|
||||
#endif /* extern C */
|
||||
#endif //_clcb73_h_
|
||||
216
src/common/sdk/nvidia/inc/class/clcb7a.h
Normal file
216
src/common/sdk/nvidia/inc/class/clcb7a.h
Normal file
@@ -0,0 +1,216 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _clcb7a__h_
|
||||
#define _clcb7a__h_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define NVCB7A_CURSOR_IMM_CHANNEL_PIO (0x0000CB7A)
|
||||
|
||||
typedef volatile struct _clcb7a_tag0 {
|
||||
NvV32 Reserved00[0x2];
|
||||
NvV32 Free; // 0x00000008 - 0x0000000B
|
||||
NvV32 Reserved01[0x7D];
|
||||
NvV32 Update; // 0x00000200 - 0x00000203
|
||||
NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207
|
||||
NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F
|
||||
NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213
|
||||
NvV32 Reserved02[0x3F7B];
|
||||
} NVCB7ADispCursorImmControlPio;
|
||||
|
||||
#define NVCB7A_FREE (0x00000008)
|
||||
#define NVCB7A_FREE_COUNT 5:0
|
||||
#define NVCB7A_UPDATE (0x00000200)
|
||||
#define NVCB7A_UPDATE_RELEASE_ELV 0:0
|
||||
#define NVCB7A_UPDATE_RELEASE_ELV_FALSE (0x00000000)
|
||||
#define NVCB7A_UPDATE_RELEASE_ELV_TRUE (0x00000001)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN 8:4
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
|
||||
#define NVCB7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
|
||||
#define NVCB7A_UPDATE_FORCE_FULLSCREEN 12:12
|
||||
#define NVCB7A_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
|
||||
#define NVCB7A_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS (0x00000204)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004)
|
||||
#define NVCB7A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0
|
||||
#define NVCB7A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
|
||||
#define NVCB7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}; /* extern "C" */
|
||||
#endif
|
||||
#endif // _clcb7a_h
|
||||
|
||||
70
src/common/sdk/nvidia/inc/class/clcb7b.h
Normal file
70
src/common/sdk/nvidia/inc/class/clcb7b.h
Normal file
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _clcb7b_h_
|
||||
#define _clcb7b_h_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define NVCB7B_WINDOW_IMM_CHANNEL_DMA (0x0000CB7B)
|
||||
|
||||
// dma opcode instructions
|
||||
#define NVCB7B_DMA
|
||||
#define NVCB7B_DMA_OPCODE 31:29
|
||||
#define NVCB7B_DMA_OPCODE_METHOD 0x00000000
|
||||
#define NVCB7B_DMA_OPCODE_JUMP 0x00000001
|
||||
#define NVCB7B_DMA_OPCODE_NONINC_METHOD 0x00000002
|
||||
#define NVCB7B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
|
||||
#define NVCB7B_DMA_METHOD_COUNT 27:18
|
||||
#define NVCB7B_DMA_METHOD_OFFSET 15:2
|
||||
#define NVCB7B_DMA_DATA 31:0
|
||||
#define NVCB7B_DMA_DATA_NOP 0x00000000
|
||||
#define NVCB7B_DMA_JUMP_OFFSET 15:2
|
||||
#define NVCB7B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
|
||||
|
||||
// class methods
|
||||
#define NVCB7B_PUT (0x00000000)
|
||||
#define NVCB7B_PUT_PTR 13:0
|
||||
#define NVCB7B_GET (0x00000004)
|
||||
#define NVCB7B_GET_PTR 13:0
|
||||
#define NVCB7B_UPDATE (0x00000200)
|
||||
#define NVCB7B_UPDATE_RELEASE_ELV 0:0
|
||||
#define NVCB7B_UPDATE_RELEASE_ELV_FALSE (0x00000000)
|
||||
#define NVCB7B_UPDATE_RELEASE_ELV_TRUE (0x00000001)
|
||||
#define NVCB7B_UPDATE_INTERLOCK_WITH_WINDOW 1:1
|
||||
#define NVCB7B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
|
||||
#define NVCB7B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
|
||||
#define NVCB7B_UPDATE_FORCE_FULLSCREEN 4:4
|
||||
#define NVCB7B_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
|
||||
#define NVCB7B_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
|
||||
#define NVCB7B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004)
|
||||
#define NVCB7B_SET_POINT_OUT_X 15:0
|
||||
#define NVCB7B_SET_POINT_OUT_Y 31:16
|
||||
|
||||
#ifdef __cplusplus
|
||||
}; /* extern "C" */
|
||||
#endif
|
||||
#endif // _clcb7b_h
|
||||
2007
src/common/sdk/nvidia/inc/class/clcb7d.h
Normal file
2007
src/common/sdk/nvidia/inc/class/clcb7d.h
Normal file
File diff suppressed because it is too large
Load Diff
906
src/common/sdk/nvidia/inc/class/clcb7e.h
Normal file
906
src/common/sdk/nvidia/inc/class/clcb7e.h
Normal file
@@ -0,0 +1,906 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _clcb7e_h_
|
||||
#define _clcb7e_h_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define NVCB7E_WINDOW_CHANNEL_DMA (0x0000CB7E)
|
||||
|
||||
// dma opcode instructions
|
||||
#define NVCB7E_DMA
|
||||
#define NVCB7E_DMA_OPCODE 31:29
|
||||
#define NVCB7E_DMA_OPCODE_METHOD 0x00000000
|
||||
#define NVCB7E_DMA_OPCODE_JUMP 0x00000001
|
||||
#define NVCB7E_DMA_OPCODE_NONINC_METHOD 0x00000002
|
||||
#define NVCB7E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
|
||||
#define NVCB7E_DMA_METHOD_COUNT 27:18
|
||||
#define NVCB7E_DMA_METHOD_OFFSET 15:2
|
||||
#define NVCB7E_DMA_DATA 31:0
|
||||
#define NVCB7E_DMA_DATA_NOP 0x00000000
|
||||
#define NVCB7E_DMA_JUMP_OFFSET 15:2
|
||||
#define NVCB7E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
|
||||
|
||||
// class methods
|
||||
#define NVCB7E_PUT (0x00000000)
|
||||
#define NVCB7E_PUT_PTR 13:0
|
||||
#define NVCB7E_GET (0x00000004)
|
||||
#define NVCB7E_GET_PTR 13:0
|
||||
#define NVCB7E_UPDATE (0x00000200)
|
||||
#define NVCB7E_UPDATE_RELEASE_ELV 0:0
|
||||
#define NVCB7E_UPDATE_RELEASE_ELV_FALSE (0x00000000)
|
||||
#define NVCB7E_UPDATE_RELEASE_ELV_TRUE (0x00000001)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN 8:4
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i))
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
|
||||
#define NVCB7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
|
||||
#define NVCB7E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12
|
||||
#define NVCB7E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000)
|
||||
#define NVCB7E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001)
|
||||
#define NVCB7E_UPDATE_FORCE_FULLSCREEN 16:16
|
||||
#define NVCB7E_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
|
||||
#define NVCB7E_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
|
||||
#define NVCB7E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204)
|
||||
#define NVCB7E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0
|
||||
#define NVCB7E_GET_LINE (0x00000208)
|
||||
#define NVCB7E_GET_LINE_LINE 15:0
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL (0x0000020C)
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000)
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001)
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000)
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001)
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000)
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001)
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002)
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000)
|
||||
#define NVCB7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001)
|
||||
#define NVCB7E_SET_SEMAPHORE_ACQUIRE (0x00000210)
|
||||
#define NVCB7E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0
|
||||
#define NVCB7E_SET_SEMAPHORE_RELEASE (0x00000214)
|
||||
#define NVCB7E_SET_SEMAPHORE_RELEASE_VALUE 31:0
|
||||
#define NVCB7E_SET_NOTIFIER_CONTROL (0x00000220)
|
||||
#define NVCB7E_SET_NOTIFIER_CONTROL_MODE 0:0
|
||||
#define NVCB7E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
|
||||
#define NVCB7E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
|
||||
#define NVCB7E_SET_SIZE (0x00000224)
|
||||
#define NVCB7E_SET_SIZE_WIDTH 15:0
|
||||
#define NVCB7E_SET_SIZE_HEIGHT 31:16
|
||||
#define NVCB7E_SET_STORAGE (0x00000228)
|
||||
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT 3:0
|
||||
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
|
||||
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
|
||||
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
|
||||
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
|
||||
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
|
||||
#define NVCB7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
|
||||
#define NVCB7E_SET_PARAMS (0x0000022C)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT 7:0
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_I8 (0x0000001E)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076)
|
||||
#define NVCB7E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078)
|
||||
#define NVCB7E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18
|
||||
#define NVCB7E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_PARAMS_SWAP_UV 19:19
|
||||
#define NVCB7E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_PARAMS_FMT_ROUNDING_MODE 22:22
|
||||
#define NVCB7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000)
|
||||
#define NVCB7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001)
|
||||
#define NVCB7E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_PLANAR_STORAGE_PITCH 12:0
|
||||
#define NVCB7E_SET_SEMAPHORE_RELEASE_HI (0x0000023C)
|
||||
#define NVCB7E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY (0x00000240)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY_ADDRESS_HI 31:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY (0x00000244)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ADDRESS_LO 31:4
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET 3:2
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE 0:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY (0x00000248)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY_ADDRESS_HI 31:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY (0x0000024C)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ADDRESS_LO 31:4
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET 3:2
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE 0:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_POINT_IN_X 15:0
|
||||
#define NVCB7E_SET_POINT_IN_Y 31:16
|
||||
#define NVCB7E_SET_SIZE_IN (0x00000298)
|
||||
#define NVCB7E_SET_SIZE_IN_WIDTH 15:0
|
||||
#define NVCB7E_SET_SIZE_IN_HEIGHT 31:16
|
||||
#define NVCB7E_SET_SIZE_OUT (0x000002A4)
|
||||
#define NVCB7E_SET_SIZE_OUT_WIDTH 15:0
|
||||
#define NVCB7E_SET_SIZE_OUT_HEIGHT 31:16
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER (0x000002A8)
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001)
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004)
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001)
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004)
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE 8:8
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE 9:9
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC)
|
||||
#define NVCB7E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0
|
||||
#define NVCB7E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12
|
||||
#define NVCB7E_SET_COMPOSITION_CONTROL (0x000002EC)
|
||||
#define NVCB7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0
|
||||
#define NVCB7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001)
|
||||
#define NVCB7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002)
|
||||
#define NVCB7E_SET_COMPOSITION_CONTROL_DEPTH 11:4
|
||||
#define NVCB7E_SET_COMPOSITION_CONTROL_BYPASS 16:16
|
||||
#define NVCB7E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0)
|
||||
#define NVCB7E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0
|
||||
#define NVCB7E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
|
||||
#define NVCB7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
|
||||
#define NVCB7E_SET_KEY_ALPHA (0x000002F8)
|
||||
#define NVCB7E_SET_KEY_ALPHA_MIN 15:0
|
||||
#define NVCB7E_SET_KEY_ALPHA_MAX 31:16
|
||||
#define NVCB7E_SET_KEY_RED_CR (0x000002FC)
|
||||
#define NVCB7E_SET_KEY_RED_CR_MIN 15:0
|
||||
#define NVCB7E_SET_KEY_RED_CR_MAX 31:16
|
||||
#define NVCB7E_SET_KEY_GREEN_Y (0x00000300)
|
||||
#define NVCB7E_SET_KEY_GREEN_Y_MIN 15:0
|
||||
#define NVCB7E_SET_KEY_GREEN_Y_MAX 31:16
|
||||
#define NVCB7E_SET_KEY_BLUE_CB (0x00000304)
|
||||
#define NVCB7E_SET_KEY_BLUE_CB_MIN 15:0
|
||||
#define NVCB7E_SET_KEY_BLUE_CB_MAX 31:16
|
||||
#define NVCB7E_SET_PRESENT_CONTROL (0x00000308)
|
||||
#define NVCB7E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0
|
||||
#define NVCB7E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4
|
||||
#define NVCB7E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
|
||||
#define NVCB7E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
|
||||
#define NVCB7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8
|
||||
#define NVCB7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_PRESENT_CONTROL_STEREO_MODE 13:12
|
||||
#define NVCB7E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000)
|
||||
#define NVCB7E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001)
|
||||
#define NVCB7E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002)
|
||||
#define NVCB7E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C)
|
||||
#define NVCB7E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0
|
||||
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330)
|
||||
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15
|
||||
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000)
|
||||
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001)
|
||||
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12
|
||||
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000)
|
||||
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001)
|
||||
#define NVCB7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002)
|
||||
#define NVCB7E_SET_ACQ_SEMAPHORE_VALUE (0x00000334)
|
||||
#define NVCB7E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0
|
||||
#define NVCB7E_SET_SCAN_DIRECTION (0x0000033C)
|
||||
#define NVCB7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0
|
||||
#define NVCB7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000)
|
||||
#define NVCB7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001)
|
||||
#define NVCB7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1
|
||||
#define NVCB7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000)
|
||||
#define NVCB7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001)
|
||||
#define NVCB7E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2
|
||||
#define NVCB7E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000)
|
||||
#define NVCB7E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001)
|
||||
#define NVCB7E_SET_TIMESTAMP_ORIGIN_LO (0x00000340)
|
||||
#define NVCB7E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0
|
||||
#define NVCB7E_SET_TIMESTAMP_ORIGIN_HI (0x00000344)
|
||||
#define NVCB7E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0
|
||||
#define NVCB7E_SET_UPDATE_TIMESTAMP_LO (0x00000348)
|
||||
#define NVCB7E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0
|
||||
#define NVCB7E_SET_UPDATE_TIMESTAMP_HI (0x0000034C)
|
||||
#define NVCB7E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS (0x00000370)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CHROMA_VER (0x00000378)
|
||||
#define NVCB7E_SET_CHROMA_VER_POSITION 1:0
|
||||
#define NVCB7E_SET_CHROMA_VER_POSITION_TOP (0x00000000)
|
||||
#define NVCB7E_SET_CHROMA_VER_POSITION_CENTER (0x00000001)
|
||||
#define NVCB7E_SET_CHROMA_VER_POSITION_BOTTOM (0x00000002)
|
||||
#define NVCB7E_SET_CHROMA_VER_USE_SWPOSITION 2:2
|
||||
#define NVCB7E_SET_CHROMA_VER_USE_SWPOSITION_FALSE (0x00000000)
|
||||
#define NVCB7E_SET_CHROMA_VER_USE_SWPOSITION_TRUE (0x00000001)
|
||||
#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD 4:3
|
||||
#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD_WT_0 (0x00000000)
|
||||
#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD_WT_QUARTER (0x00000001)
|
||||
#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD_WT_HALF (0x00000002)
|
||||
#define NVCB7E_SET_CHROMA_VER_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003)
|
||||
#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN 6:5
|
||||
#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_0 (0x00000000)
|
||||
#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_QUARTER (0x00000001)
|
||||
#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_HALF (0x00000002)
|
||||
#define NVCB7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003)
|
||||
#define NVCB7E_SET_CHROMA_VER_USE_SWWEIGHTS 7:7
|
||||
#define NVCB7E_SET_CHROMA_VER_USE_SWWEIGHTS_FALSE (0x00000000)
|
||||
#define NVCB7E_SET_CHROMA_VER_USE_SWWEIGHTS_TRUE (0x00000001)
|
||||
#define NVCB7E_SET_CHROMA_HOR (0x0000037C)
|
||||
#define NVCB7E_SET_CHROMA_HOR_REPLACE_ODD 0:0
|
||||
#define NVCB7E_SET_CHROMA_HOR_REPLACE_ODD_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CHROMA_HOR_REPLACE_ODD_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CHROMA_HOR_REPLACE_EVEN 1:1
|
||||
#define NVCB7E_SET_CHROMA_HOR_REPLACE_EVEN_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CHROMA_HOR_REPLACE_EVEN_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD 3:2
|
||||
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_0 (0x00000000)
|
||||
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_QUARTER (0x00000001)
|
||||
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_HALF (0x00000002)
|
||||
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003)
|
||||
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN 5:4
|
||||
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_0 (0x00000000)
|
||||
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_QUARTER (0x00000001)
|
||||
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_HALF (0x00000002)
|
||||
#define NVCB7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003)
|
||||
#define NVCB7E_SET_CHROMA_HOR_USE_SWWEIGHTS 6:6
|
||||
#define NVCB7E_SET_CHROMA_HOR_USE_SWWEIGHTS_FALSE (0x00000000)
|
||||
#define NVCB7E_SET_CHROMA_HOR_USE_SWWEIGHTS_TRUE (0x00000001)
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL (0x00000398)
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_ENABLE 0:0
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_LOCATION 4:4
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000)
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001)
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000)
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001)
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_EXT_PACKET_CONTROL_SIZE 27:16
|
||||
#define NVCB7E_SET_EXT_PACKET_DATA (0x0000039C)
|
||||
#define NVCB7E_SET_EXT_PACKET_DATA_DB0 7:0
|
||||
#define NVCB7E_SET_EXT_PACKET_DATA_DB1 15:8
|
||||
#define NVCB7E_SET_EXT_PACKET_DATA_DB2 23:16
|
||||
#define NVCB7E_SET_EXT_PACKET_DATA_DB3 31:24
|
||||
#define NVCB7E_SET_WIN_INFOFRAME (0x000003A0)
|
||||
#define NVCB7E_SET_WIN_INFOFRAME_FID 7:0
|
||||
#define NVCB7E_SET_WIN_INFOFRAME_EN 16:16
|
||||
#define NVCB7E_SET_WIN_INFOFRAME_EN_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_WIN_INFOFRAME_EN_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C00 (0x00000400)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C00_VALUE 20:0
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C01 (0x00000404)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C01_VALUE 20:0
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C02 (0x00000408)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C02_VALUE 20:0
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C03 (0x0000040C)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C03_VALUE 20:0
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C10 (0x00000410)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C10_VALUE 20:0
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C11 (0x00000414)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C11_VALUE 20:0
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C12 (0x00000418)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C12_VALUE 20:0
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C13 (0x0000041C)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C13_VALUE 20:0
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C20 (0x00000420)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C20_VALUE 20:0
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C21 (0x00000424)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C21_VALUE 20:0
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C22 (0x00000428)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C22_VALUE 20:0
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C23 (0x0000042C)
|
||||
#define NVCB7E_SET_FMT_COEFFICIENT_C23_VALUE 20:0
|
||||
#define NVCB7E_SET_ILUT_CONTROL (0x00000440)
|
||||
#define NVCB7E_SET_ILUT_CONTROL_INTERPOLATE 0:0
|
||||
#define NVCB7E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_ILUT_CONTROL_MIRROR 1:1
|
||||
#define NVCB7E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_ILUT_CONTROL_MODE 3:2
|
||||
#define NVCB7E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000)
|
||||
#define NVCB7E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001)
|
||||
#define NVCB7E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002)
|
||||
#define NVCB7E_SET_ILUT_CONTROL_SIZE 18:8
|
||||
#define NVCB7E_SET_CSC00CONTROL (0x0000045C)
|
||||
#define NVCB7E_SET_CSC00CONTROL_ENABLE 0:0
|
||||
#define NVCB7E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C00 (0x00000460)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C00_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C01 (0x00000464)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C01_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C02 (0x00000468)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C02_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C03 (0x0000046C)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C03_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C10 (0x00000470)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C10_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C11 (0x00000474)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C11_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C12 (0x00000478)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C12_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C13 (0x0000047C)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C13_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C20 (0x00000480)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C20_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C21 (0x00000484)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C21_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C22 (0x00000488)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C22_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C23 (0x0000048C)
|
||||
#define NVCB7E_SET_CSC00COEFFICIENT_C23_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC0LUT_FP_NORM_SCALE (0x00000490)
|
||||
#define NVCB7E_SET_CSC0LUT_FP_NORM_SCALE_VALUE 31:0
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL (0x000004A0)
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_MIRROR 1:1
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_ENABLE 4:4
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_CURVE 6:5
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000)
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001)
|
||||
#define NVCB7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002)
|
||||
#define NVCB7E_SET_CSC01CONTROL (0x000004BC)
|
||||
#define NVCB7E_SET_CSC01CONTROL_ENABLE 0:0
|
||||
#define NVCB7E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C00 (0x000004C0)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C00_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C01 (0x000004C4)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C01_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C02 (0x000004C8)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C02_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C03 (0x000004CC)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C03_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C10 (0x000004D0)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C10_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C11 (0x000004D4)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C11_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C12 (0x000004D8)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C12_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C13 (0x000004DC)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C13_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C20 (0x000004E0)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C20_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C21 (0x000004E4)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C21_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C22 (0x000004E8)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C22_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C23 (0x000004EC)
|
||||
#define NVCB7E_SET_CSC01COEFFICIENT_C23_VALUE 20:0
|
||||
#define NVCB7E_SET_TMO_CONTROL (0x00000500)
|
||||
#define NVCB7E_SET_TMO_CONTROL_INTERPOLATE 0:0
|
||||
#define NVCB7E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_TMO_CONTROL_SAT_MODE 3:2
|
||||
#define NVCB7E_SET_TMO_CONTROL_SIZE 18:8
|
||||
#define NVCB7E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508)
|
||||
#define NVCB7E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16
|
||||
#define NVCB7E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C)
|
||||
#define NVCB7E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0
|
||||
#define NVCB7E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
|
||||
#define NVCB7E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24
|
||||
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510)
|
||||
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0
|
||||
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16
|
||||
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514)
|
||||
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0
|
||||
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
|
||||
#define NVCB7E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24
|
||||
#define NVCB7E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518)
|
||||
#define NVCB7E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0
|
||||
#define NVCB7E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C)
|
||||
#define NVCB7E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0
|
||||
#define NVCB7E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
|
||||
#define NVCB7E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24
|
||||
#define NVCB7E_SET_CSC10CONTROL (0x0000053C)
|
||||
#define NVCB7E_SET_CSC10CONTROL_ENABLE 0:0
|
||||
#define NVCB7E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C00 (0x00000540)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C00_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C01 (0x00000544)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C01_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C02 (0x00000548)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C02_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C03 (0x0000054C)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C03_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C10 (0x00000550)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C10_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C11 (0x00000554)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C11_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C12 (0x00000558)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C12_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C13 (0x0000055C)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C13_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C20 (0x00000560)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C20_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C21 (0x00000564)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C21_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C22 (0x00000568)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C22_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C23 (0x0000056C)
|
||||
#define NVCB7E_SET_CSC10COEFFICIENT_C23_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC1LUT_FP_SCALE (0x00000570)
|
||||
#define NVCB7E_SET_CSC1LUT_FP_SCALE_VALUE 15:0
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL (0x00000580)
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_MIRROR 1:1
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_ENABLE 4:4
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_CURVE 6:5
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000)
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001)
|
||||
#define NVCB7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002)
|
||||
#define NVCB7E_SET_CSC11CONTROL (0x0000059C)
|
||||
#define NVCB7E_SET_CSC11CONTROL_ENABLE 0:0
|
||||
#define NVCB7E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_CSC11CONTROL_LEVEL 7:2
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C00 (0x000005A0)
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C00_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C01 (0x000005A4)
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C01_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C02 (0x000005A8)
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C02_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C03 (0x000005AC)
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C03_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C10 (0x000005B0)
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C10_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C11 (0x000005B4)
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C11_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C12 (0x000005B8)
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C12_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C13 (0x000005BC)
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C13_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C20 (0x000005C0)
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C20_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C21 (0x000005C4)
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C21_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C22 (0x000005C8)
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C22_VALUE 20:0
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C23 (0x000005CC)
|
||||
#define NVCB7E_SET_CSC11COEFFICIENT_C23_VALUE 20:0
|
||||
#define NVCB7E_SET_CLAMP_RANGE (0x000005D0)
|
||||
#define NVCB7E_SET_CLAMP_RANGE_LOW 15:0
|
||||
#define NVCB7E_SET_CLAMP_RANGE_HIGH 31:16
|
||||
#define NVCB7E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004)
|
||||
#define NVCB7E_SW_RESERVED_VALUE 31:0
|
||||
#define NVCB7E_SET_DIRTY_RECT_SIZE (0x000005E4)
|
||||
#define NVCB7E_SET_DIRTY_RECT_SIZE_WIDTH 15:0
|
||||
#define NVCB7E_SET_DIRTY_RECT_SIZE_HEIGHT 31:16
|
||||
#define NVCB7E_SET_DIRTY_RECT_POSITION (0x000005E8)
|
||||
#define NVCB7E_SET_DIRTY_RECT_POSITION_X 15:0
|
||||
#define NVCB7E_SET_DIRTY_RECT_POSITION_Y 31:16
|
||||
#define NVCB7E_SET_SUPERFRAME (0x000005EC)
|
||||
#define NVCB7E_SET_SUPERFRAME_ENABLE 0:0
|
||||
#define NVCB7E_SET_SUPERFRAME_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_SUPERFRAME_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_SUPERFRAME_MODE 2:1
|
||||
#define NVCB7E_SET_SUPERFRAME_MODE_FIXED (0x00000000)
|
||||
#define NVCB7E_SET_SUPERFRAME_MODE_DYNAMIC (0x00000001)
|
||||
#define NVCB7E_SET_SUPERFRAME_MODE_SW (0x00000003)
|
||||
#define NVCB7E_SET_SUPERFRAME_RATIO_IN 15:8
|
||||
#define NVCB7E_SET_SUPERFRAME_RATIO_OUT 23:16
|
||||
#define NVCB7E_SET_SUPERFRAME_START_COUNT 31:24
|
||||
#define NVCB7E_SET_INFOFRAME_CTRL(b) (0x000005F0 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_INFOFRAME_CTRL_ENABLE 0:0
|
||||
#define NVCB7E_SET_INFOFRAME_CTRL_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_INFOFRAME_CTRL_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_INFOFRAME_CTRL_LOCATION 5:4
|
||||
#define NVCB7E_SET_INFOFRAME_CTRL_LOCATION_VBLANK (0x00000000)
|
||||
#define NVCB7E_SET_INFOFRAME_CTRL_LOCATION_VSYNC (0x00000001)
|
||||
#define NVCB7E_SET_INFOFRAME_CTRL_LOCATION_LINE (0x00000002)
|
||||
#define NVCB7E_SET_INFOFRAME_CTRL_LINE_ID 30:16
|
||||
#define NVCB7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED 31:31
|
||||
#define NVCB7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_INFOFRAME_HEADER(b) (0x000005F8 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_INFOFRAME_HEADER_HB0 7:0
|
||||
#define NVCB7E_SET_INFOFRAME_HEADER_HB1 15:8
|
||||
#define NVCB7E_SET_INFOFRAME_HEADER_HB2 23:16
|
||||
#define NVCB7E_SET_INFOFRAME_HEADER_HB3 31:24
|
||||
#define NVCB7E_SET_INFOFRAME_DATA0(b) (0x00000600 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_INFOFRAME_DATA0_DB0 7:0
|
||||
#define NVCB7E_SET_INFOFRAME_DATA0_DB1 15:8
|
||||
#define NVCB7E_SET_INFOFRAME_DATA0_DB2 23:16
|
||||
#define NVCB7E_SET_INFOFRAME_DATA0_DB3 31:24
|
||||
#define NVCB7E_SET_INFOFRAME_DATA1(b) (0x00000608 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_INFOFRAME_DATA1_DB4 7:0
|
||||
#define NVCB7E_SET_INFOFRAME_DATA1_DB5 15:8
|
||||
#define NVCB7E_SET_INFOFRAME_DATA1_DB6 23:16
|
||||
#define NVCB7E_SET_INFOFRAME_DATA1_DB7 31:24
|
||||
#define NVCB7E_SET_INFOFRAME_DATA2(b) (0x00000610 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_INFOFRAME_DATA2_DB8 7:0
|
||||
#define NVCB7E_SET_INFOFRAME_DATA2_DB9 15:8
|
||||
#define NVCB7E_SET_INFOFRAME_DATA2_DB10 23:16
|
||||
#define NVCB7E_SET_INFOFRAME_DATA2_DB11 31:24
|
||||
#define NVCB7E_SET_INFOFRAME_DATA3(b) (0x00000618 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_INFOFRAME_DATA3_DB12 7:0
|
||||
#define NVCB7E_SET_INFOFRAME_DATA3_DB13 15:8
|
||||
#define NVCB7E_SET_INFOFRAME_DATA3_DB14 23:16
|
||||
#define NVCB7E_SET_INFOFRAME_DATA3_DB15 31:24
|
||||
#define NVCB7E_SET_INFOFRAME_DATA4(b) (0x00000620 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_INFOFRAME_DATA4_DB16 7:0
|
||||
#define NVCB7E_SET_INFOFRAME_DATA4_DB17 15:8
|
||||
#define NVCB7E_SET_INFOFRAME_DATA4_DB18 23:16
|
||||
#define NVCB7E_SET_INFOFRAME_DATA4_DB19 31:24
|
||||
#define NVCB7E_SET_INFOFRAME_DATA5(b) (0x00000628 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_INFOFRAME_DATA5_DB20 7:0
|
||||
#define NVCB7E_SET_INFOFRAME_DATA5_DB21 15:8
|
||||
#define NVCB7E_SET_INFOFRAME_DATA5_DB22 23:16
|
||||
#define NVCB7E_SET_INFOFRAME_DATA5_DB23 31:24
|
||||
#define NVCB7E_SET_INFOFRAME_DATA6(b) (0x00000630 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_INFOFRAME_DATA6_DB24 7:0
|
||||
#define NVCB7E_SET_INFOFRAME_DATA6_DB25 15:8
|
||||
#define NVCB7E_SET_INFOFRAME_DATA6_DB26 23:16
|
||||
#define NVCB7E_SET_INFOFRAME_DATA6_DB27 31:24
|
||||
#define NVCB7E_SET_INFOFRAME_DATA7(b) (0x00000638 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_INFOFRAME_DATA7_DB28 7:0
|
||||
#define NVCB7E_SET_INFOFRAME_DATA7_DB29 15:8
|
||||
#define NVCB7E_SET_INFOFRAME_DATA7_DB30 23:16
|
||||
#define NVCB7E_SET_INFOFRAME_DATA7_DB31 31:24
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE (0x00000640)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE_ADDRESS_HI 31:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE (0x00000644)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ADDRESS_LO 31:4
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET 3:2
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_IOVA (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE 0:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE (0x00000648)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE_ADDRESS_HI 31:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE (0x0000064C)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ADDRESS_LO 31:4
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET 3:2
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_IOVA (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE 0:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000650)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000654)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_ISO(b) (0x00000658 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_ISO_ADDRESS_HI 31:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO(b) (0x00000670 + (b)*0x00000004)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_ADDRESS_LO 31:4
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET 3:2
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_IOVA (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_KIND 1:1
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE 0:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_ILUT (0x00000688)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_ILUT_ADDRESS_HI 31:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT (0x0000068C)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_ADDRESS_LO 31:4
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET 3:2
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_IOVA (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE 0:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_TMO_LUT (0x00000690)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_HI_TMO_LUT_ADDRESS_HI 31:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT (0x00000694)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ADDRESS_LO 31:4
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET 3:2
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_IOVA (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE 0:0
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCB7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_ENABLE (0x00000001)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}; /* extern "C" */
|
||||
#endif
|
||||
#endif // _clcb7e_h
|
||||
@@ -151,6 +151,7 @@ typedef volatile struct _clcba2_tag0 {
|
||||
#define NVCBA2_ERROR_SCRUBBER_INSUFFICIENT_PERMISSIONS (0x0000001b)
|
||||
#define NVCBA2_ERROR_SCRUBBER_MUTEX_ACQUIRE_FAILURE (0x0000001c)
|
||||
#define NVCBA2_ERROR_SCRUB_SIZE_MAX_EXCEEDED (0x0000001d)
|
||||
#define NVCBA2_ERROR_SIZE_ZERO (0x0000001e)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}; /* extern "C" */
|
||||
|
||||
@@ -184,8 +184,6 @@ typedef struct NV0000_CTRL_DIAG_LOCK_METER_ENTRY {
|
||||
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS (0x00000021)
|
||||
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA (0x00000100)
|
||||
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL (0x00001000)
|
||||
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET (0x00002000)
|
||||
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET (0x00002001)
|
||||
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX (0x00002002)
|
||||
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX (0x00002003)
|
||||
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP (0x00003000)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -34,6 +34,13 @@
|
||||
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "class/cl0000.h"
|
||||
|
||||
#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0)
|
||||
#define NV0000_NOTIFIERS_VGPU_UNBIND_EVENT (1)
|
||||
#define NV0000_NOTIFIERS_VGPU_BIND_EVENT (2)
|
||||
#define NV0000_NOTIFIERS_GPU_BIND_UNBIND_EVENT (3)
|
||||
#define NV0000_NOTIFIERS_MAXCOUNT (4)
|
||||
|
||||
/*
|
||||
* NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION
|
||||
*
|
||||
@@ -80,34 +87,59 @@ typedef struct NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
|
||||
#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
|
||||
#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
|
||||
|
||||
typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE {
|
||||
NvU32 deviceMask;
|
||||
} NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE;
|
||||
|
||||
typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND {
|
||||
NvU32 gpuId;
|
||||
} NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND;
|
||||
|
||||
typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND {
|
||||
NvU32 gpuId;
|
||||
} NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND;
|
||||
|
||||
typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND {
|
||||
NvU32 gpuId;
|
||||
NvBool bBind;
|
||||
} NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND;
|
||||
|
||||
/*
|
||||
* NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS
|
||||
* NV0000_CTRL_CMD_GET_SYSTEM_EVENT_DATA
|
||||
*
|
||||
* This command returns the status of the specified system event type.
|
||||
* This command reads the client's event data queue info FIFO order.
|
||||
* See the description of NV01_EVENT for details on registering events.
|
||||
*
|
||||
* event
|
||||
* This parameter specifies the event type. Valid event type values
|
||||
* can be found in cl0000.h.
|
||||
* status
|
||||
* This parameter returns the status for a given event type. Valid
|
||||
* status values can be found in cl0000.h.
|
||||
* Output only as selective event data query is not supported yet.
|
||||
* Event type.
|
||||
* Valid event type values can be found in this header file.
|
||||
*
|
||||
* data
|
||||
* Data associated with the event.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_PARAM_STRUCT
|
||||
* NV_ERR_INVALID_CLIENT
|
||||
* NV_ERR_OBJECT_NOT_FOUND when system event queue is empty
|
||||
*
|
||||
*/
|
||||
|
||||
#define NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS (0x502) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID" */
|
||||
#define NV0000_CTRL_CMD_GET_SYSTEM_EVENT_DATA (0x502) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID (0x2U)
|
||||
#define NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_MESSAGE_ID (0x2U)
|
||||
|
||||
typedef struct NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS {
|
||||
typedef struct NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS {
|
||||
NvU32 event;
|
||||
NvU32 status;
|
||||
} NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS;
|
||||
|
||||
union {
|
||||
NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE display;
|
||||
NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND vgpuUnbind;
|
||||
NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND vgpuBind;
|
||||
NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND gpuBindUnbind;
|
||||
} data;
|
||||
} NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS;
|
||||
|
||||
/* _ctrl0000event_h_ */
|
||||
|
||||
|
||||
@@ -856,10 +856,6 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
|
||||
NvU32 dataType; /* [out] - data union type */
|
||||
|
||||
union {
|
||||
struct {
|
||||
NvU32 newValue;
|
||||
NvU32 oldValue;
|
||||
} configSet;
|
||||
struct {
|
||||
NvU8 paramData[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA];
|
||||
NvU32 paramSize;
|
||||
@@ -872,7 +868,6 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
|
||||
} data;
|
||||
} NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS;
|
||||
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001U)
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002U)
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003U)
|
||||
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004U)
|
||||
|
||||
@@ -68,10 +68,6 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS {
|
||||
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U)
|
||||
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U)
|
||||
|
||||
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2
|
||||
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U)
|
||||
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U)
|
||||
|
||||
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING 3:3
|
||||
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE (0x00000000U)
|
||||
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE (0x00000001U)
|
||||
@@ -2116,7 +2112,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS {
|
||||
* NV_ERR_INVALID_REQUEST
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */
|
||||
#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */
|
||||
#define NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE 1U
|
||||
#define NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE 32U
|
||||
|
||||
@@ -2143,9 +2139,12 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT {
|
||||
NvU32 shortTimescaleBatteryCurrentLimitmA;
|
||||
} NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT;
|
||||
|
||||
#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU)
|
||||
#define NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU)
|
||||
|
||||
typedef struct NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
|
||||
/*Buffer to get all the supported functions*/
|
||||
NvU32 supportedFuncs;
|
||||
|
||||
typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
|
||||
/* GPU ID */
|
||||
NvU32 gpuId;
|
||||
|
||||
@@ -2176,6 +2175,16 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
|
||||
/* Target total processing power on battery, offset, in milli-Watts. */
|
||||
NvS32 targetTppBattOffsetmW;
|
||||
|
||||
/*
|
||||
* Maximum allowed output on battery, offset, in milli-Watts.
|
||||
*/
|
||||
NvS32 maxOutputBattOffsetmW;
|
||||
|
||||
/*
|
||||
* Minimum allowed output on battery, offset, in milli-Watts.
|
||||
*/
|
||||
NvS32 minOutputBattOffsetmW;
|
||||
|
||||
/*
|
||||
* If value specified is larger than the statically assigned ROS reserve in
|
||||
* the system power limits table, this will take affect.
|
||||
@@ -2197,15 +2206,6 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
|
||||
*/
|
||||
NvU32 dcTspShortTimescaleLimitmA;
|
||||
|
||||
/* Require DB on DC to use system power limits table */
|
||||
NvBool bRequireDcSysPowerLimitsTable;
|
||||
|
||||
/* Dynamic params can override ROS reserve used in DB-DC */
|
||||
NvBool bAllowDcRestOfSystemReserveOverride;
|
||||
|
||||
/* Is DC-TSP supported? */
|
||||
NvBool bSupportDcTsp;
|
||||
|
||||
/* Dynamic Boost AC support */
|
||||
NvBool bEnableForAC;
|
||||
|
||||
@@ -2277,9 +2277,7 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
|
||||
|
||||
/* CPU TDP Limit to be set (milliwatts) */
|
||||
NvU32 cpuTdpmw;
|
||||
} NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
|
||||
|
||||
typedef NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
|
||||
} NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
|
||||
|
||||
/* Define the filter types */
|
||||
#define CONTROLLER_FILTER_TYPE_EMWA 0U
|
||||
@@ -2305,9 +2303,16 @@ typedef NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS NV0000_CTRL_SYST
|
||||
/*
|
||||
* Defines for get supported sub functions bit fields
|
||||
*/
|
||||
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0
|
||||
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1
|
||||
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0
|
||||
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0
|
||||
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1
|
||||
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0
|
||||
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED 8:8
|
||||
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED_YES 1
|
||||
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED_NO 0
|
||||
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED 9:9
|
||||
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED_YES 1
|
||||
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED_NO 0
|
||||
|
||||
|
||||
/*!
|
||||
* Config DSM 2x version specific defines
|
||||
|
||||
@@ -1328,11 +1328,12 @@ typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS {
|
||||
#define NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID (0x60U)
|
||||
|
||||
typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 laneCount;
|
||||
NvU32 linkBW;
|
||||
NvU32 dp2LinkBW;
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 laneCount;
|
||||
NvU32 linkBW;
|
||||
NvU32 dp2LinkBW;
|
||||
NvBool bFECEnabled;
|
||||
} NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT 3:0
|
||||
@@ -1682,8 +1683,6 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
|
||||
* Specified the DP versions supported by the GPU
|
||||
* UHBRSupportedByGpu
|
||||
* Bitmask to specify the UHBR link rates supported by the GPU.
|
||||
* minPClkForCompressed
|
||||
* Pixel clock below which we should prefer non-DSC mode.
|
||||
* bIsMultistreamSupported
|
||||
* Returns NV_TRUE if MST is supported by the GPU else NV_FALSE
|
||||
* bIsSCEnabled
|
||||
@@ -1705,6 +1704,8 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
|
||||
* Returns NV_TRUE if GPU uses the new RG flush design
|
||||
* bSupportDPDownSpread
|
||||
* Returns NV_TRUE if GPU support downspread.
|
||||
* bAvoidHBR3
|
||||
* Returns if we need to avoid HBR3 as much as possible
|
||||
*
|
||||
* DSC caps
|
||||
*
|
||||
@@ -1725,7 +1726,6 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
|
||||
NvU32 maxLinkRate;
|
||||
NvU32 dpVersionsSupported;
|
||||
NvU32 UHBRSupportedByGpu;
|
||||
NvU32 minPClkForCompressed;
|
||||
NvBool bIsMultistreamSupported;
|
||||
NvBool bIsSCEnabled;
|
||||
NvBool bHasIncreasedWatermarkLimits;
|
||||
@@ -1736,6 +1736,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
|
||||
NvBool bOverrideLinkBw;
|
||||
NvBool bUseRgFlushSequence;
|
||||
NvBool bSupportDPDownSpread;
|
||||
NvBool bAvoidHBR3;
|
||||
NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC;
|
||||
} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS;
|
||||
|
||||
@@ -2041,6 +2042,27 @@ typedef struct NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS {
|
||||
NvBool enable;
|
||||
} NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS;
|
||||
|
||||
/* NV0073_CTRL_CMD_SPECIFIC_RETRIEVE_DP_RING_BUFFER
|
||||
*
|
||||
* These commands retrieves buffer from RM for
|
||||
* DP Library to dump logs
|
||||
*
|
||||
*
|
||||
* Possible status values returned include:
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER (0x731371U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS_MESSAGE_ID (0x71U)
|
||||
|
||||
typedef struct NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU8 *pDpRingBuffer, 8);
|
||||
NvU8 ringBufferType;
|
||||
NvU32 numRecords;
|
||||
} NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS;
|
||||
|
||||
|
||||
|
||||
/*
|
||||
@@ -3377,6 +3399,44 @@ typedef struct NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS {
|
||||
|
||||
#define NV0073_CTRL_CMD_DP2X_GET_LEVEL_INFO_TABLE_DATA (0x73138aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR
|
||||
*
|
||||
* This command is used to apply the WAR based on EDID.
|
||||
* subDeviceInstance
|
||||
* This parameter specifies the subdevice instance within the
|
||||
* NV04_DISPLAY_COMMON parent device to which the operation should be
|
||||
* directed. This parameter must specify a value between zero and the
|
||||
* total number of subdevices within the parent device. This parameter
|
||||
* should be set to zero for default behavior.
|
||||
* displayId
|
||||
* This parameter specifies the ID of the digital display for which the
|
||||
* data should be returned. The display ID must a digital display.
|
||||
* If more than one displayId bit is set or the displayId is not a DP,
|
||||
* this call will return NV_ERR_INVALID_ARGUMENT.
|
||||
* bEnable
|
||||
* This parameter will be used by RM to set the PDB property. Later that PDB
|
||||
* property will be used for applying the WAR
|
||||
* head
|
||||
* This parameter specify for which head RM need to apply the WAR
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_PARAM_STRUCT
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*
|
||||
*/
|
||||
#define NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS_MESSAGE_ID (0x8BU)
|
||||
|
||||
typedef struct NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 bEnable;
|
||||
NvU32 head;
|
||||
} NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR (0x73138bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS_MESSAGE_ID" */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
@@ -3444,7 +3504,7 @@ typedef struct NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS {
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
|
||||
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP (0x73138bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID" */
|
||||
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP (0x73138cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_DP_IMP_LINK_CONFIGURATION {
|
||||
NvU32 linkRate10M;
|
||||
@@ -3453,6 +3513,7 @@ typedef struct NV0073_CTRL_DP_IMP_LINK_CONFIGURATION {
|
||||
NvBool bDp2xChannelCoding;
|
||||
NvBool bMultiStreamTopology;
|
||||
NvBool bFECEnabled;
|
||||
NvBool bDisableEffBppSST8b10b;
|
||||
} NV0073_CTRL_DP_IMP_LINK_CONFIGURATION;
|
||||
|
||||
typedef struct NV0073_CTRL_DP_IMP_DSC_PARAMETERS {
|
||||
@@ -3489,7 +3550,7 @@ typedef struct NV0073_CTRL_DP_IMP_WATERMARK {
|
||||
NvBool bIsModePossible;
|
||||
} NV0073_CTRL_DP_IMP_WATERMARK;
|
||||
|
||||
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID (0x8BU)
|
||||
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID (0x8CU)
|
||||
|
||||
typedef struct NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
@@ -3501,4 +3562,59 @@ typedef struct NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS {
|
||||
NV0073_CTRL_DP_IMP_WATERMARK watermark;
|
||||
} NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS;
|
||||
|
||||
/*
|
||||
* NV0073_CTRL_CMD_DP_GET_CABLEID_INFO_FROM_MACRO
|
||||
*
|
||||
* This command is used to read cable ID Information from USB-C Cable for
|
||||
* DP configuration purposes.
|
||||
*
|
||||
* subDeviceInstance [in]
|
||||
* This parameter specifies the subdevice instance within the
|
||||
* NV04_DISPLAY_COMMON parent device to which the operation should be
|
||||
* directed. This parameter must specify a value between zero and the
|
||||
* total number of subdevices within the parent device. This parameter
|
||||
* should be set to zero for default behavior.
|
||||
*
|
||||
* displayId [in]
|
||||
* This parameter specifies the ID of the DP display which owns
|
||||
* the Main Link to be adjusted. The display ID must a DP display
|
||||
* as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
|
||||
* If more than one displayId bit is set or the displayId is not a DP,
|
||||
* this call will return NV_ERR_INVALID_PARAMETER.
|
||||
*
|
||||
* cableIDInfo [out]
|
||||
* This parameter reflects the result of the cable ID read from the cable
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_ERR_INVALID_PARAMETER
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* NV_OK
|
||||
*/
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_GET_CABLEID_INFO_FROM_MACRO (0x73138dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef enum NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE {
|
||||
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_UNKNOWN = 0,
|
||||
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_PASSIVE = 1,
|
||||
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_ACTIVE_RETIMER = 2,
|
||||
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_ACTIVE_LIN_REDRIVER = 3,
|
||||
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_OPTICAL = 4,
|
||||
} NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE;
|
||||
|
||||
typedef struct NV0073_CTRL_DP_USBC_CABLEID_INFO {
|
||||
NvBool uhbr10_0_capable;
|
||||
NvBool uhbr13_5_capable;
|
||||
NvBool uhbr20_0_capable;
|
||||
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE type;
|
||||
NvBool vconn_source;
|
||||
} NV0073_CTRL_DP_USBC_CABLEID_INFO;
|
||||
|
||||
#define NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS_MESSAGE_ID (0x8DU)
|
||||
|
||||
typedef struct NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NV0073_CTRL_DP_USBC_CABLEID_INFO cableIDInfo;
|
||||
} NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS;
|
||||
|
||||
/* _ctrl0073dp_h_ */
|
||||
|
||||
@@ -32,6 +32,25 @@
|
||||
|
||||
#include "ctrl/ctrl0073/ctrl0073base.h"
|
||||
|
||||
/*
|
||||
* tilemask
|
||||
* Tiles assocaited with calc tiemout head.
|
||||
* frameActive
|
||||
* New frame has started on this Head.
|
||||
* histoReady
|
||||
* Asserts when histogram data from all the "enabled" LTMs belonging to this head
|
||||
* is ready.
|
||||
* startFrameReady
|
||||
* When histo_ready interrupt
|
||||
* is received and HDMA is programmed and then RISCV asserts STARTFRAME_READY.
|
||||
*/
|
||||
typedef struct NV0073_LTM_HEAD_STATUS_PARAMS {
|
||||
NvU8 tileMask;
|
||||
NvBool frameActive;
|
||||
NvBool histoReady;
|
||||
NvBool startFrameReady;
|
||||
} NV0073_LTM_HEAD_STATUS_PARAMS;
|
||||
|
||||
/* NV04_DISPLAY_COMMON event-related control commands and parameters */
|
||||
|
||||
/*
|
||||
@@ -90,41 +109,4 @@ typedef struct NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
|
||||
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001U)
|
||||
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002U)
|
||||
|
||||
/*
|
||||
* NV0073_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY
|
||||
*
|
||||
* hMemory
|
||||
* This parameter specifies the handle of the memory object
|
||||
* that identifies the memory address translation for this
|
||||
* subdevice instance's notification(s). The beginning of the
|
||||
* translation points to an array of notification data structures.
|
||||
* The size of the translation must be at least large enough to hold the
|
||||
* maximum number of notification data structures identified by
|
||||
* the NV0073_MAX_NOTIFIERS value.
|
||||
* Legal argument values must be instances of the following classes:
|
||||
* NV01_NULL
|
||||
* NV04_MEMORY
|
||||
* When hMemory specifies the NV01_NULL_OBJECT value then any existing
|
||||
* memory translation connection is cleared. There must not be any
|
||||
* pending notifications when this command is issued.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_PARAM_STRUCT
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* NV_ERR_INVALID_STATE
|
||||
*/
|
||||
#define NV0073_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x730303U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U)
|
||||
|
||||
typedef struct NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvHandle hMemory;
|
||||
} NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS;
|
||||
|
||||
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0U
|
||||
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1U
|
||||
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2U
|
||||
|
||||
/* _ctrl0073event_h_ */
|
||||
|
||||
@@ -281,12 +281,10 @@ typedef struct NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS {
|
||||
|
||||
/* Faking Support commands */
|
||||
/* some random value to enable/disable test code */
|
||||
#define NV0073_FAKE_DEVICE_SUPPORT_ENABLE 0x11faU
|
||||
#define NV0073_FAKE_DEVICE_SUPPORT_DISABLE 0x99ceU
|
||||
#define NV0073_FAKE_DEVICE_SUPPORT_ATTACH_DEVICES 0x100U
|
||||
#define NV0073_FAKE_DEVICE_SUPPORT_REMOVE_DEVICES 0x101U
|
||||
|
||||
|
||||
#define NV0073_FAKE_DEVICE_SUPPORT_ENABLE 0x11faU
|
||||
#define NV0073_FAKE_DEVICE_SUPPORT_DISABLE 0x99ceU
|
||||
#define NV0073_FAKE_DEVICE_SUPPORT_ATTACH_DEVICES 0x100U
|
||||
#define NV0073_FAKE_DEVICE_SUPPORT_REMOVE_DEVICES 0x101U
|
||||
|
||||
/*
|
||||
* NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID
|
||||
@@ -317,7 +315,7 @@ typedef struct NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS {
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID (0x730211U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID" */
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID (0x730211U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID (0x11U)
|
||||
|
||||
@@ -2082,6 +2080,26 @@ typedef NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS NV0073_CTRL_SPECIFIC_
|
||||
|
||||
typedef NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM (0x7302b0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID" */
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM (0x7302b0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV0073_CTRL_CMD_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP
|
||||
*
|
||||
* The command returns the offset of the disp registers for sending timestamp
|
||||
* directly to RISCV, so that clients may map them directly and write to this
|
||||
* register which will trigger interrupt in RISCV.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
|
||||
#define NV0073_CTRL_CMD_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP (0x7302b1U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS_MESSAGE_ID (0xB1U)
|
||||
|
||||
typedef struct NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 dispRegisterBase;
|
||||
} NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS;
|
||||
/* _ctrl0073specific_h_ */
|
||||
|
||||
@@ -1911,6 +1911,7 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
|
||||
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_HUBCLK 0x0006
|
||||
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_DISPCLK 0x0007
|
||||
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_POSTRG_CLKS 0x0008
|
||||
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_MSCG 0x0009
|
||||
|
||||
// Parameter/characteristics of Display ALPM
|
||||
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_INVALID 0x0000
|
||||
@@ -2031,6 +2032,66 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
|
||||
*/
|
||||
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_GATE_TIME_US (0x0003)
|
||||
|
||||
/*!
|
||||
* Property specifies current state of the specified clock
|
||||
* i.e. Gated ot not Gated
|
||||
* (This property allows Get operation)
|
||||
*/
|
||||
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_STATUS (0x0004)
|
||||
|
||||
/*!
|
||||
* @brief Parameter/characteristics of MSCG
|
||||
*
|
||||
* Following are the Parameter/characteristics for MSCG
|
||||
*/
|
||||
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_INVALID (0x0000)
|
||||
|
||||
/*!
|
||||
* Property specifies if DPS1 is supported
|
||||
* (This property allows Get operation)
|
||||
*/
|
||||
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_SUPPORT (0x0001)
|
||||
|
||||
/*!
|
||||
* Property specifies if DPS2 is supported
|
||||
* (This property allows Get operation)
|
||||
*/
|
||||
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_SUPPORT (0x0002)
|
||||
|
||||
/*!
|
||||
* Property specifies if MSCG is enabled
|
||||
* (This property allows Get/SET operation)
|
||||
*/
|
||||
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_ENABLED (0x0003)
|
||||
|
||||
/*!
|
||||
* Property specifies the time(in US) for which DPS1 was enabled
|
||||
* in ACTIVE region
|
||||
* (This property allows Get operation)
|
||||
*/
|
||||
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_ACTIVE_TIME_US (0x0004)
|
||||
|
||||
/*!
|
||||
* Property specifies the time(in US) for which DPS1 was enabled
|
||||
* in VBLANK region
|
||||
* (This property allows Get operation)
|
||||
*/
|
||||
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_VBLANK_TIME_US (0x0005)
|
||||
|
||||
/*!
|
||||
* Property specifies the time(in US) for which DPS2 was enabled
|
||||
* in ACTIVE region
|
||||
* (This property allows Get operation)
|
||||
*/
|
||||
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_ACTIVE_TIME_US (0x0006)
|
||||
|
||||
/*!
|
||||
* Property specifies the time(in US) for which DPS2 was enabled
|
||||
* in VBLANK region
|
||||
* (This property allows Get operation)
|
||||
*/
|
||||
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_VBLANK_TIME_US (0x0007)
|
||||
|
||||
/*!
|
||||
* @brief Structure to identify display low power feature
|
||||
*
|
||||
@@ -2203,6 +2264,143 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS {
|
||||
NvBool bEnableDrr;
|
||||
} NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS;
|
||||
|
||||
/*
|
||||
* NV0073_CTRL_CMD_SYSTEM_SET_DISPLAY_PERF_LIMIT
|
||||
*
|
||||
* This command sets lower and/or upper bounds for a display clock (dispclk or
|
||||
* hubclk), or for the memory perf level. When this API is called, the system
|
||||
* will immediately attempt to switch the clock or perf level to a value that
|
||||
* meets the specified condition(s).
|
||||
*
|
||||
* If no lower limit is desired, the "min" input should be set to zero.
|
||||
*
|
||||
* If no upper limit is desired for a clock, the "max" input should be set to
|
||||
* NV_U32_MAX.
|
||||
*
|
||||
* This API does not allow an upper limit to be specified for perf level.
|
||||
*
|
||||
* Any perf limit set through this API will remain in effect until it updated
|
||||
* or cancelled by a subsequent call to this API. A perf limit may be
|
||||
* cancelled by setting the "min" value to NV_U32_MIN (0) and the "max" value
|
||||
* (for clocks) to NV_U32_MAX. Only one perf limit may be in effect for a
|
||||
* given clientUsageId and type at any given time.
|
||||
*
|
||||
* At any given time, multiple perf limits (with different clientUsageIds) may
|
||||
* be in effect for a given clock or perf level, and that clock or perf level
|
||||
* will be set to a value that meets the requirements of all active perf
|
||||
* limits. If there is a conflict between perf limits, the conflict will be
|
||||
* resolved by the perf limit(s) with the higher priority.
|
||||
*
|
||||
* For example, suppose the API is called with the following parameters:
|
||||
* clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS
|
||||
* type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK
|
||||
* data.clock.minFrequencyKHz = 800000
|
||||
* data.clock.maxFrequencyKHz = 800000
|
||||
* This will set dispclk to 800 MHz (or possibly a slightly higher frequency,
|
||||
* if the clock dividers do not allow 800 MHz to be set exactly).
|
||||
*
|
||||
* Then suppose this call is made:
|
||||
* clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE
|
||||
* type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK
|
||||
* data.clock.minFrequencyKHz = 1000000
|
||||
* data.clock.maxFrequencyKHz = 0xFFFFFFFF
|
||||
* After this call, dispclk will remain set to 800 MHz, because, although the
|
||||
* min frequency was requested to be at least 1 GHz, this would conflict with
|
||||
* the "maxFrequencyKHz = 800000" value set in the previous call, which is
|
||||
* still in effect. The previous call takes priority because
|
||||
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS has higher priority than
|
||||
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE.
|
||||
*
|
||||
* Then suppose this call is made:
|
||||
* clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS
|
||||
* type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK
|
||||
* data.clock.minFrequencyKHz = 0
|
||||
* data.clock.maxFrequencyKHz = 0xFFFFFFFF
|
||||
* This removes the NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS perf
|
||||
* limit. At this point, dispclk will be set to 1 GHz, in accordance with the
|
||||
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE perf limit,
|
||||
* which is still in effect. (The remaining perf limit allows the clock to be
|
||||
* higher than 1 GHz, but in practice, the clock will generally be set to the
|
||||
* lowest frequency that meets the perf limit requirement, to save power. For
|
||||
* perf level, perf monitors (which do not use the perf limit mechanism) may
|
||||
* force a higher value in order to meet performance needs.)
|
||||
*
|
||||
* This API takes an array of perf limit structures, so multiple perf limits
|
||||
* maybe set within the same call.
|
||||
*
|
||||
* This API is primarily intended for use on SOC products, where display is
|
||||
* separate from the GPU. On dGPU products, this API may not be supported;
|
||||
* instead, NV2080_CTRL_CMD_PERF_LIMITS_SET_STATUS_V2 may be used to set perf
|
||||
* limits.
|
||||
*
|
||||
* subDeviceInstance (in)
|
||||
* This parameter specifies the subdevice instance within the
|
||||
* NV04_DISPLAY_COMMON parent device to which the operation should be
|
||||
* directed. This parameter must specify a value between zero and the
|
||||
* total number of subdevices within the parent device. This parameter
|
||||
* should be set to zero for default behavior.
|
||||
*
|
||||
* numLimits (in)
|
||||
* This is the number of perf limits with lower and/or upper limits to
|
||||
* apply.
|
||||
*
|
||||
* bWaitForCompletion (in)
|
||||
* It is possible that a perf change or clock change may take some time to
|
||||
* execute. If this flag is set, the API will wait for all of the changes
|
||||
* to complete before returning. (However, it will not wait for completion
|
||||
* of any operation that is blocked by a higher priority perf limit.)
|
||||
*
|
||||
* clientUsageId (in)
|
||||
* This is a NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_xxx value
|
||||
* indicating who the client is, and/or the purpose of the perf limit. It
|
||||
* is used to establish priority between conflicting perf limits.
|
||||
*
|
||||
* whatIsToBeLimited (in)
|
||||
* This is a NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_xxx value
|
||||
* indicating which clock, or memory perf level, is to have limits applied.
|
||||
*
|
||||
* minLevelOrFreqKHz (in)
|
||||
* maxLevelOrFreqKHz (in)
|
||||
* If type is
|
||||
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_PERF_LEVEL, then
|
||||
* minLevelOrFreqKHz specifies the zero-based index of the minimum perf
|
||||
* level to allow. maxLevelOrFreqKHz is not used.
|
||||
*
|
||||
* If type specifies a clock
|
||||
* (NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK or
|
||||
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_HUBCLK), then
|
||||
* minLevelOrFreqKHz and maxLevelOrFreqKHz specify the lower and upper
|
||||
* limits (respectively) for the specified clock's frequency.
|
||||
*/
|
||||
#define NV0073_CTRL_CMD_SYSTEM_SET_DISPLAY_PERF_LIMIT (0x73015aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/* valid clientUsageId values */
|
||||
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE (0U)
|
||||
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MCLK_SWITCH (1U)
|
||||
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS (2U)
|
||||
|
||||
/* valid type values */
|
||||
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_PERF_LEVEL (0U)
|
||||
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_DISPCLK (1U)
|
||||
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_HUBCLK (2U)
|
||||
|
||||
/* Define a structure for a single perf limit */
|
||||
typedef struct NV0073_CTRL_SYSTEM_DISPLAY_PERF_LIMIT {
|
||||
NvU8 clientUsageId;
|
||||
NvU8 whatIsToBeLimited;
|
||||
NvU32 minLevelOrFreqKHz;
|
||||
NvU32 maxLevelOrFreqKHz;
|
||||
} NV0073_CTRL_SYSTEM_DISPLAY_PERF_LIMIT;
|
||||
|
||||
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS_MESSAGE_ID (0x5AU)
|
||||
|
||||
typedef struct NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 numLimits;
|
||||
NvBool bWaitForCompletion;
|
||||
NV_DECLARE_ALIGNED(NvP64 limits, 8);
|
||||
} NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS;
|
||||
|
||||
/*
|
||||
* NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO
|
||||
*
|
||||
|
||||
@@ -226,7 +226,7 @@ typedef struct NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS {
|
||||
NvU32 pteMemPfn;
|
||||
NvU32 pageSize;
|
||||
NvU32 startPageIndex;
|
||||
NvU32 flags;
|
||||
NV_DECLARE_ALIGNED(NvU64 flags, 8);
|
||||
NvHandle hSrcVASpace;
|
||||
NvHandle hTgtVASpace;
|
||||
NvU32 peerId;
|
||||
|
||||
@@ -596,6 +596,9 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS {
|
||||
* vGPU heterogeneous mode on a GPU can only be set when the command
|
||||
* is running in a vGPU host device.
|
||||
*
|
||||
* gpuInstanceId
|
||||
* GPU Instance ID or Swizz ID
|
||||
*
|
||||
* bHeterogeneousMode
|
||||
* This parameter set the vGPU heterogeneous mode of the device.
|
||||
* Possible values are:
|
||||
@@ -617,6 +620,7 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS {
|
||||
|
||||
typedef struct NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
|
||||
NvBool bHeterogeneousMode;
|
||||
NvU32 gpuInstanceId;
|
||||
} NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS;
|
||||
|
||||
/**
|
||||
@@ -625,6 +629,9 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
|
||||
* This command returns a value indicating vGPU heterogeneous mode of
|
||||
* the GPU.
|
||||
*
|
||||
* gpuInstanceId
|
||||
* GPU Instance ID or Swizz ID
|
||||
*
|
||||
* bHeterogeneousMode
|
||||
* This parameter returns the vGPU heterogeneous mode of the device.
|
||||
* Possible values are:
|
||||
@@ -643,6 +650,7 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
|
||||
|
||||
typedef struct NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS {
|
||||
NvBool bHeterogeneousMode;
|
||||
NvU32 gpuInstanceId;
|
||||
} NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS;
|
||||
|
||||
/* _ctrl0080gpu_h_ */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -114,4 +114,22 @@ typedef struct NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PAR
|
||||
NvHandle clientHandles[NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS];
|
||||
} NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS;
|
||||
|
||||
/*!
|
||||
* NV0080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED
|
||||
*
|
||||
* Tell Physical RM whether any ZBC-kind surfaces are allocated.
|
||||
* If PF and all VFs report false, ZBC table can be flushed by Physical RM.
|
||||
*
|
||||
* bZbcReferenced [IN]
|
||||
* NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM
|
||||
*
|
||||
*/
|
||||
#define NV0080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x80200a) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x0AU)
|
||||
|
||||
typedef struct NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS {
|
||||
NvBool bZbcSurfacesExist;
|
||||
} NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS;
|
||||
|
||||
/* ctrl0080internal_h */
|
||||
|
||||
@@ -87,3 +87,4 @@
|
||||
|
||||
#include "ctrl2080/ctrl2080unix.h"
|
||||
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
|
||||
@@ -1348,6 +1348,8 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
|
||||
* NV_TRUE if the C2C links are present and the links are up.
|
||||
* The below remaining fields are valid only if return value is
|
||||
* NV_OK and bIsLinkUp is NV_TRUE.
|
||||
* bLinkInHS[OUT]
|
||||
* NV_TRUE if the C2C links are in high speed mode.
|
||||
* nrLinks[OUT]
|
||||
* Total number of C2C links that are up.
|
||||
* maxNrLinks[OUT]
|
||||
@@ -1382,6 +1384,7 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
|
||||
|
||||
typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS {
|
||||
NvBool bIsLinkUp;
|
||||
NvBool bLinkInHS;
|
||||
NvU32 nrLinks;
|
||||
NvU32 maxNrLinks;
|
||||
NvU32 linkMask;
|
||||
@@ -1393,6 +1396,8 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS {
|
||||
#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU 1
|
||||
#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU 2
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS
|
||||
*
|
||||
@@ -1417,7 +1422,44 @@ typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS {
|
||||
NvBool bDisable;
|
||||
} NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO
|
||||
*
|
||||
* This command returns the C2C error info for a C2C links.
|
||||
*
|
||||
* errCnts[OUT]
|
||||
* Array of structure that contains the error counts for
|
||||
* number of times one of C2C fatal error interrupt has happened.
|
||||
* The array size should be NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES
|
||||
* * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE.
|
||||
*
|
||||
* nrCrcErrIntr[OUT]
|
||||
* Number of times CRC error interrupt triggered.
|
||||
* nrReplayErrIntr[OUT]
|
||||
* Number of times REPLAY error interrupt triggered.
|
||||
* nrReplayB2bErrIntr[OUT]
|
||||
* Number of times REPLAY_B2B error interrupt triggered.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_STATE
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
|
||||
#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES 2
|
||||
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE 7
|
||||
|
||||
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU)
|
||||
|
||||
typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS {
|
||||
struct {
|
||||
NvU32 nrCrcErrIntr;
|
||||
NvU32 nrReplayErrIntr;
|
||||
NvU32 nrReplayB2bErrIntr;
|
||||
} errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE];
|
||||
} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING
|
||||
@@ -1552,3 +1594,103 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS {
|
||||
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES (0x00000001)
|
||||
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO (0x00000000)
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS
|
||||
*
|
||||
* This command returns C2C low power statistics.
|
||||
* Units for residency and latency are in microsceconds.
|
||||
* c2cStateSupportMask[OUT]
|
||||
Support Mask of supplrted C2C State. CL0 will always be supported (FULL_POWER)
|
||||
* cl3EntryCount[OUT]
|
||||
* Count of the number of times CL3 state has been entered.
|
||||
* cl3ResidentTimeUs[OUT]
|
||||
* Total/Average resident time in CL3 state.
|
||||
* cl3AvgEntryLatencyUs[OUT]
|
||||
* Average entry latency for CL3 state.
|
||||
* cl3AvgExitLatencyUs[OUT]
|
||||
* Average exit latency for CL3 state.
|
||||
* cl3PstateSupportMask[OUT]
|
||||
Pstate Support Mask for CL3 state
|
||||
* cl4EntryCount[OUT]
|
||||
* Count of the number of times CL4 state has been entered.
|
||||
* cl4ResidentTimeUs[OUT]
|
||||
* Total/Average resident time in CL4 state.
|
||||
* cl4AvgEntryLatencyUs[OUT]
|
||||
* Average entry latency for CL4 state.
|
||||
* cl4AvgExitLatencyUs[OUT]
|
||||
* Average exit latency for CL4 state.
|
||||
* cl4PstateSupportMask[OUT]
|
||||
Pstate Support Mask for CL4 state
|
||||
* localPowerState[OUT]
|
||||
* Power state of the local end of the C2C link.
|
||||
* Valid values are :
|
||||
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER - Full power state
|
||||
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 - Low power state
|
||||
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 - Low power state
|
||||
* remotePowerState[OUT]
|
||||
* Power state of the remote end of the C2C link.
|
||||
* Valid values are :
|
||||
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER - Full power state
|
||||
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 - Low power state
|
||||
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 - Low power state
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_STATE
|
||||
*
|
||||
* Please also review the information below for additional information on
|
||||
* select fields:
|
||||
*
|
||||
* cl3EntryCount/cl4EntryCount[OUT]
|
||||
* These may not represent current exact count, as low power transitions could have
|
||||
* occured after reading the counter register.
|
||||
*/
|
||||
|
||||
#define NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS (0x20801831) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS_MESSAGE_ID (0x31U)
|
||||
|
||||
typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS {
|
||||
NvU32 c2cStateSupportMask;
|
||||
NvBool bCl3Support;
|
||||
NvU32 cl3EntryCount;
|
||||
NvU32 cl3ExitCount;
|
||||
NvU32 cl3ResidentTimeUs;
|
||||
NvU32 cl3AvgEntryLatencyUs;
|
||||
NvU32 cl3AvgExitLatencyUs;
|
||||
NvU32 cl3PstateSupportMask;
|
||||
NvU32 cl3DisallowReasonMask;
|
||||
NvBool bCl4Support;
|
||||
NvU32 cl4EntryCount;
|
||||
NvU32 cl4ExitCount;
|
||||
NvU32 cl4ResidentTimeUs;
|
||||
NvU32 cl4AvgEntryLatencyUs;
|
||||
NvU32 cl4AvgExitLatencyUs;
|
||||
NvU32 cl4PstateSupportMask;
|
||||
NvU32 cl4DisallowReasonMask;
|
||||
NvU32 c2cLpwrStateAllowedMask;
|
||||
NvU32 localPowerState;
|
||||
NvU32 remotePowerState;
|
||||
} NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER 0x0
|
||||
#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 0x1
|
||||
#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 0x2
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE
|
||||
*
|
||||
* This command sets the allow vote for C2C Lpwr States.
|
||||
* c2cLpwrStateId[IN]
|
||||
* C2C LowPower State Id : NV2080_CTRL_LPWR_C2C_STATE_ID_CLx
|
||||
* bAllowed[in]
|
||||
* State Allowed/disallowed flag
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE (0x20801832) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS_MESSAGE_ID (0x32U)
|
||||
|
||||
typedef struct NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS {
|
||||
NvU32 c2cLpwrStateId;
|
||||
NvBool bAllowed;
|
||||
} NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS;
|
||||
|
||||
@@ -30,3 +30,4 @@
|
||||
// Source file: ctrl/ctrl2080/ctrl2080fan.finn
|
||||
//
|
||||
|
||||
|
||||
|
||||
@@ -1811,9 +1811,8 @@ typedef struct NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS {
|
||||
*
|
||||
* Get memory alignment. Replacement for NVOS32_FUNCTION_GET_MEM_ALIGNMENT
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT (0x20801342U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT (0x20801342U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS (4U)
|
||||
#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID (0x42U)
|
||||
|
||||
typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS {
|
||||
@@ -1827,8 +1826,6 @@ typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS {
|
||||
NvU32 alignPitch;
|
||||
NvU32 alignPad;
|
||||
NvU32 alignMask;
|
||||
NvU32 alignOutputFlags[NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS];
|
||||
NvU32 alignBank[NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS];
|
||||
NvU32 alignKind;
|
||||
NvU32 alignAdjust; // Output -- If non-zero the amount we need to adjust the offset
|
||||
NvU32 alignAttr2;
|
||||
@@ -2039,6 +2036,24 @@ typedef struct NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS {
|
||||
NvU32 ropEnMask;
|
||||
} NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS;
|
||||
|
||||
/*!
|
||||
* Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_SYS_MASK.
|
||||
*/
|
||||
typedef struct NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS {
|
||||
/*!
|
||||
* [in]: swizzId
|
||||
* PartitionID associated with a created smc partition. Currently used only for a
|
||||
* device monitoring client to get the physical values of the sys. The client needs to pass
|
||||
* 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId.
|
||||
* RM will consider this request similar to a legacy case.
|
||||
*/
|
||||
NvU32 swizzId;
|
||||
/*!
|
||||
* [out]: physical/local sys mask.
|
||||
*/
|
||||
NV_DECLARE_ALIGNED(NvU64 sysEnMask, 8);
|
||||
} NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS;
|
||||
|
||||
/*!
|
||||
* Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK.
|
||||
*/
|
||||
@@ -2233,6 +2248,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS {
|
||||
#define NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK 0xFU
|
||||
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK 0x10U
|
||||
#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK 0x11U
|
||||
#define NV2080_CTRL_FB_FS_INFO_SYS_MASK 0x12U
|
||||
|
||||
typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
|
||||
NvU16 queryType;
|
||||
@@ -2257,6 +2273,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS logicalLtc, 8);
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS dmLogicalLtc, 8);
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS sysl2Lts, 8);
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS sys, 8);
|
||||
} queryParams;
|
||||
} NV2080_CTRL_FB_FS_INFO_QUERY;
|
||||
|
||||
@@ -2748,61 +2765,6 @@ typedef struct NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS {
|
||||
NvU32 newConfiguration;
|
||||
} NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_FB_GET_STATUS
|
||||
*
|
||||
* This control command is used by clients to get the FB availabilty status,
|
||||
* i.e whether the GPU Memory is ready for use or not for MIG and non-MIG cases
|
||||
*
|
||||
* fbStatus[OUT]
|
||||
* This parameter returns the various values of FB availability status.
|
||||
* Valid values include:
|
||||
* NV2080_CTRL_FB_STATUS_FAILED
|
||||
* On Non Self hosted (Non NUMA) systems - this status is not expected since
|
||||
* FB memory is available as part of GPU initialization itself.
|
||||
* On Direct connected Self hosted systems - this status is not expected since
|
||||
* FB memory is available as part of GPU initialization itself.
|
||||
* On Nvswitch connected Self hosted systems - this status indicates that either
|
||||
* the memory onlining has failed or fabric probe response has failed.
|
||||
* GPU reset maybe required in such a case.
|
||||
* NV2080_CTRL_FB_STATUS_READY
|
||||
* On Non Self hosted systems - this status is always returned as memory is ready
|
||||
* after GPU initialization is complete.
|
||||
* On Self hosted systems - this status indicates that the FB memory has been onlined
|
||||
* successfully and is available for client/user allocations.
|
||||
* NV2080_CTRL_FB_STATUS_PENDING
|
||||
* On Non Self hosted systems - this status is not expected
|
||||
* On Direct connected Self hosted systems - this status is not expected since
|
||||
* FB memory is available as part of GPU initialization itself.
|
||||
* On Nvswitch connected Self hosted systems - This status indicates memory is yet to
|
||||
* be onlined or is in progress since we are either still waiting for a fabric
|
||||
* probe response or a fabric probe request hasn't been sent yet.
|
||||
* NV2080_CTRL_FB_STATUS_NOT_APPLICABLE
|
||||
* This status indicates that this is a system with no FB memory.
|
||||
*
|
||||
*
|
||||
* @returns Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_STATE
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* NV_ERR_NOT_READY
|
||||
* NV_ERR_INVALID_LOCK_STATE
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FB_GET_STATUS (0x20801357U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
// NUMA Memory Onlining Status
|
||||
#define NV2080_CTRL_FB_STATUS_FAILED (0x00000000U)
|
||||
#define NV2080_CTRL_FB_STATUS_READY (0x00000001U)
|
||||
#define NV2080_CTRL_FB_STATUS_PENDING (0x00000002U)
|
||||
#define NV2080_CTRL_FB_STATUS_NOT_APPLICABLE (0x00000003U)
|
||||
|
||||
#define NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID (0x57U)
|
||||
|
||||
typedef struct NV2080_CTRL_FB_GET_STATUS_PARAMS {
|
||||
|
||||
NvU32 fbStatus;
|
||||
} NV2080_CTRL_FB_GET_STATUS_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT
|
||||
*
|
||||
@@ -2818,12 +2780,12 @@ typedef struct NV2080_CTRL_FB_GET_STATUS_PARAMS {
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT (0x20801358U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT (0x20801357U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED (0x00000000U)
|
||||
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED (0x00000001U)
|
||||
|
||||
#define NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID (0x58U)
|
||||
#define NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID (0x57U)
|
||||
|
||||
typedef struct NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS {
|
||||
NvU32 isSupported;
|
||||
@@ -2842,15 +2804,44 @@ typedef struct NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS {
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* NV_ERR_INVALID_STATE
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS (0x20801359U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS (0x20801358U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED (0x00000000U)
|
||||
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED (0x00000001U)
|
||||
|
||||
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID (0x59U)
|
||||
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID (0x58U)
|
||||
|
||||
typedef struct NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS {
|
||||
NvU32 currentStatus;
|
||||
} NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_FB_GET_MEMORY_BOOT_TRAINING_FLAGS
|
||||
*
|
||||
* This command returns the memory boot training flags from VBIOS table.
|
||||
*
|
||||
* flagCollectSchmooData
|
||||
* flagWrTrHybridVrefEn
|
||||
* flagWrTrHybridNonVrefEn
|
||||
* flagRdTrHybridVrefEn
|
||||
* flagRdTrHybridNonVrefEn
|
||||
* skipBootTraining
|
||||
*
|
||||
* Possible status return values are:
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FB_GET_MEMORY_BOOT_TRAINING_FLAGS (0x20801359U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS_MESSAGE_ID (0x59U)
|
||||
|
||||
typedef struct NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS {
|
||||
NvBool flagCollectSchmooData;
|
||||
NvBool flagWrTrHybridVrefEn;
|
||||
NvBool flagWrTrHybridNonVrefEn;
|
||||
NvBool flagRdTrHybridVrefEn;
|
||||
NvBool flagRdTrHybridNonVrefEn;
|
||||
NvBool skipBootTraining;
|
||||
} NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS;
|
||||
|
||||
/* _ctrl2080fb_h_ */
|
||||
|
||||
@@ -245,8 +245,7 @@ typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS {
|
||||
* @{
|
||||
*/
|
||||
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT 0U
|
||||
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON 1U
|
||||
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT 2U
|
||||
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT 1U
|
||||
/*!@}*/
|
||||
|
||||
/*!
|
||||
|
||||
@@ -111,8 +111,9 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
|
||||
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU)
|
||||
|
||||
|
||||
#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED (0x00000041U)
|
||||
|
||||
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U)
|
||||
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000042U)
|
||||
#define NV2080_CTRL_GPU_INFO_INDEX_GROUP_ID 30:24
|
||||
#define NV2080_CTRL_GPU_INFO_INDEX_RESERVED 31:31
|
||||
|
||||
@@ -223,6 +224,10 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
|
||||
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO (0x00000000U)
|
||||
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES (0x00000001U)
|
||||
|
||||
/* valid localization supported values */
|
||||
#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_NO (0x00000000U)
|
||||
#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_YES (0x00000001U)
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_GPU_GET_INFO
|
||||
*
|
||||
@@ -755,6 +760,8 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS {
|
||||
NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
|
||||
} NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS;
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST
|
||||
*
|
||||
@@ -2634,7 +2641,14 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE 8U
|
||||
|
||||
|
||||
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 40U
|
||||
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 90U
|
||||
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA 29:28
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_DEFAULT 0U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_DISABLE 1U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_ENABLE 2U
|
||||
|
||||
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U
|
||||
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U
|
||||
@@ -3131,6 +3145,7 @@ typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS {
|
||||
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB 0x08000000U
|
||||
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB 0x10000000U
|
||||
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB 0x20000000U
|
||||
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_1024MB 0x40000000U
|
||||
|
||||
|
||||
|
||||
@@ -4586,4 +4601,75 @@ typedef struct NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS {
|
||||
NvU32 tpcReconfigMask;
|
||||
} NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_GPU_RPC_GSP_TEST
|
||||
*
|
||||
* This command checks a variable sized RPC for a known pattern, then
|
||||
* fills the data field with another pattern. It also records the timestamp
|
||||
* before and after the RPC is sent to GSP.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_GENERIC
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_GPU_RPC_GSP_TEST (0x208001e8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS_MESSAGE_ID (0xe8U)
|
||||
|
||||
typedef struct NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS {
|
||||
NvU8 test;
|
||||
NvU32 dataSize;
|
||||
NV_DECLARE_ALIGNED(NvU64 startTimestamp, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 stopTimestamp, 8);
|
||||
NV_DECLARE_ALIGNED(NvP64 data, 8);
|
||||
} NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_GPU_RPC_GSP_TEST_SERIALIZED_INTEGRITY 0x1
|
||||
#define NV2080_CTRL_GPU_RPC_GSP_TEST_UNSERIALIZED 0x2
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_GPU_RPC_GSP_QUERY_SIZES
|
||||
*
|
||||
* This command returns information necessary for GSP RPC integrity tests
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_GENERIC
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_GPU_RPC_GSP_QUERY_SIZES (0x208001e9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS_MESSAGE_ID (0xe9U)
|
||||
|
||||
typedef struct NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS {
|
||||
NvU32 maxRpcSize;
|
||||
NvU32 finnRmapiSize;
|
||||
NvU32 rpcGspControlSize;
|
||||
NvU32 rpcMessageHeaderSize;
|
||||
NV_DECLARE_ALIGNED(NvU64 timestampFreq, 8);
|
||||
} NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS;
|
||||
|
||||
/*
|
||||
* RUSD features.
|
||||
* Each feature definition equates to a bit in the supportedFeatures bitmask.
|
||||
*/
|
||||
#define RUSD_FEATURE_NON_POLLING 0x1
|
||||
#define RUSD_FEATURE_POLLING 0x2
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_GPU_RUSD_GET_SUPPORTED_FEATURES
|
||||
*
|
||||
* @brief Returns bitmask of supported RUSD features.
|
||||
*
|
||||
* @param[out] supportedFeatures Bitmask of supported RUSD features
|
||||
*
|
||||
* @return NV_OK
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_RUSD_GET_SUPPORTED_FEATURES (0x208081eaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS_MESSAGE_ID (0xeaU)
|
||||
|
||||
typedef struct NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS {
|
||||
NvU32 supportedFeatures;
|
||||
} NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS;
|
||||
|
||||
/* _ctrl2080gpu_h_ */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -317,7 +317,19 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01 (0x00000A01U)
|
||||
|
||||
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_03 (0x00000A03U)
|
||||
|
||||
|
||||
/*
|
||||
* TODO Bug 4333440 is introducing versions 12_*.
|
||||
* Eventually once 12_* is tested and validated, another
|
||||
* follow up change will be needed to remove 10_04 support.
|
||||
*/
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_04 (0x00000A04U)
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_12_00 (0x00000C00U)
|
||||
|
||||
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_12_01 (0x00000C01U)
|
||||
|
||||
|
||||
|
||||
@@ -340,6 +352,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1 (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
|
||||
|
||||
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_3 (NV2080_CTRL_GR_INFO_SM_VERSION_10_03)
|
||||
|
||||
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_4 (NV2080_CTRL_GR_INFO_SM_VERSION_10_04)
|
||||
|
||||
|
||||
@@ -1172,6 +1187,9 @@ typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS {
|
||||
* This parameter specifies the routing information used to
|
||||
* disambiguate the target GR engine.
|
||||
*
|
||||
* ugpuId
|
||||
* Specifies the uGPU ID on Hopper+.
|
||||
*
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER (0x2080121bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */
|
||||
|
||||
@@ -1189,6 +1207,7 @@ typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS {
|
||||
NvU16 globalTpcId;
|
||||
NvU16 virtualGpcId;
|
||||
NvU16 migratableTpcId;
|
||||
NvU16 ugpuId;
|
||||
} globalSmId[NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT];
|
||||
|
||||
NvU16 numSm;
|
||||
@@ -1655,6 +1674,47 @@ typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS {
|
||||
NvU8 imla4;
|
||||
} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE (0xFFU)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FMLA16 (0x0U)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DP (0x1U)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FMLA32 (0x2U)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FFMA (0x3U)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA0 (0x4U)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA1 (0x5U)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA2 (0x6U)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA3 (0x7U)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA4 (0x8U)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FP16 (0x9U)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FP32 (0xAU)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DFMA (0xBU)
|
||||
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DMLA (0xCU)
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2
|
||||
*
|
||||
* This command provides an interface to retrieve the speed select values of
|
||||
* various instruction types.
|
||||
*
|
||||
* smIssueRateModifierListSize
|
||||
* This field specifies the number of entries on the caller's
|
||||
* smIssueRateModifierList.
|
||||
* When caller passes smIssueRateModifierListSize = 0, all fuse
|
||||
* values are returned.
|
||||
* smIssueRateModifierList
|
||||
* This field specifies a pointer in the caller's address space
|
||||
* to the buffer into which the speed select values are to be returned.
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2 (0x2080123cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2;
|
||||
|
||||
#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x3CU)
|
||||
|
||||
typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS {
|
||||
NvU32 smIssueRateModifierListSize;
|
||||
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierList[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE];
|
||||
} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID
|
||||
*
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -229,6 +229,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER {
|
||||
NvU16 globalTpcId;
|
||||
NvU16 virtualGpcId;
|
||||
NvU16 migratableTpcId;
|
||||
NvU16 ugpuId;
|
||||
} globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM];
|
||||
|
||||
NvU16 numSm;
|
||||
@@ -1003,7 +1004,7 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS {
|
||||
* validGfxCTSIdMask [OUT]
|
||||
* # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 60
|
||||
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 90
|
||||
|
||||
|
||||
|
||||
@@ -1671,17 +1672,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */
|
||||
|
||||
/* !
|
||||
* This command disables cuda limit activation at teardown of the client.
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */
|
||||
|
||||
/*
|
||||
* This command is cleaning up OPTP when a client is found to have
|
||||
* been terminated unexpectedly.
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR (0x20800a7c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7C" */
|
||||
|
||||
/* !
|
||||
* This command is used to get the current AUX power state of the sub-device.
|
||||
*/
|
||||
@@ -2914,6 +2904,8 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS {
|
||||
NvU32 bRasterSyncGpioDirection;
|
||||
} NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS;
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_FBSR_INIT
|
||||
*
|
||||
@@ -3438,7 +3430,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
|
||||
} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS;
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_PRH_DEPENDENCY_CHECK
|
||||
* NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK
|
||||
*
|
||||
* This command checks if all the dependant modules to PRH have been initialized.
|
||||
*
|
||||
@@ -3447,7 +3439,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
|
||||
* NV_ERR_INVALID_STATE
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_PRH_DEPENDENCY_CHECK (0x20800a18) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x18" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS
|
||||
@@ -3466,7 +3458,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU)
|
||||
|
||||
@@ -4004,8 +3996,9 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_P
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA
|
||||
*
|
||||
* @brief Initialize RM User Shared Data memory mapping on physical RM
|
||||
* @brief Initialize/Destroy RM User Shared Data memory mapping on physical RM
|
||||
*
|
||||
* @param[in] bInit If this is an init or a destroy request
|
||||
* @param[in] physAddr Physical address of memdesc to link physical to kernel
|
||||
* 0 to de-initialize
|
||||
*
|
||||
@@ -4015,6 +4008,7 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_P
|
||||
#define NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID (0xFEU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS {
|
||||
NvBool bInit;
|
||||
NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
|
||||
} NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS;
|
||||
#define NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA (0x20800afe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID" */
|
||||
@@ -4680,7 +4674,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS {
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS {
|
||||
NvU32 peerId;
|
||||
NvU32 peerLinkMask;
|
||||
NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8);
|
||||
NvBool bEgmPeer;
|
||||
NvBool bNvswitchConn;
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS;
|
||||
@@ -4796,7 +4790,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS {
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS {
|
||||
NvU32 flags;
|
||||
NvBool bSysmem;
|
||||
NvU32 peerLinkMask;
|
||||
NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8);
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS;
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY (0x20800a64U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID" */
|
||||
|
||||
@@ -4829,7 +4823,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS {
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS {
|
||||
NvU32 gpuInst;
|
||||
NvU32 peerLinkMask;
|
||||
NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8);
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK (0x20800a7dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID" */
|
||||
@@ -4962,6 +4956,8 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES {
|
||||
* Mask of links discovered from all the IOCTRLs
|
||||
* [Out] ipVerNvlink
|
||||
* IP revision of the NVLink HW
|
||||
* [Out] maxSupportedLinks
|
||||
* Maximum number of links supported for a given arch
|
||||
* [Out] linkInfo
|
||||
* Per link information
|
||||
*/
|
||||
@@ -4974,6 +4970,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS {
|
||||
NvU32 ioctrlSize;
|
||||
NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8);
|
||||
NvU32 ipVerNvlink;
|
||||
NvU32 maxSupportedLinks;
|
||||
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES linkInfo[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
|
||||
} NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS;
|
||||
|
||||
@@ -5264,6 +5261,28 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20800aabU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO
|
||||
*
|
||||
* Send CMC gsplite the address and size of log buffer allocated on sysmem
|
||||
*
|
||||
* [In] PublicId
|
||||
* ID of the gsplite engine
|
||||
* [In] logBufferSize
|
||||
* Size of the log buffer allocated on sysmem
|
||||
* [In] logBufferAddr
|
||||
* Start address of the log buffer
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID (0x89U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS {
|
||||
NvU32 PublicId;
|
||||
NV_DECLARE_ALIGNED(NvU64 logBufferSize, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 logBufferAddr, 8);
|
||||
} NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO (0x20800a89U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS
|
||||
@@ -5271,6 +5290,31 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
|
||||
* Request from CPU-RM to proccess supressed errors during boot on GSP
|
||||
* This command accepts no parameters.
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS (0x20800b01U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | 0x1" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS (0x20800b01U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | 0x1" */
|
||||
|
||||
|
||||
/*!
|
||||
* @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2 {
|
||||
NvU32 smIssueRateModifierListSize;
|
||||
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierList[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE];
|
||||
} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2;
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x02U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS {
|
||||
NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierV2[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
|
||||
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2 (0x20800b03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x03U)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
|
||||
|
||||
/* ctrl2080internal_h */
|
||||
|
||||
@@ -71,7 +71,6 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
|
||||
|
||||
/* valid architecture values */
|
||||
|
||||
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X (0xE0000023)
|
||||
|
||||
|
||||
@@ -133,17 +132,22 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 (0x00000000)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 (0x00000002)
|
||||
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB110 (0x00000003)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB112 (0x00000004)
|
||||
|
||||
|
||||
/* valid ARCHITECTURE_GB20x implementation values */
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 (0x00000000)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 (0x00000002)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 (0x00000003)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB204 (0x00000004)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 (0x00000005)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 (0x00000006)
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 (0x00000007)
|
||||
|
||||
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20B (0x0000000B)
|
||||
|
||||
|
||||
|
||||
/* Valid Chip sub revisions */
|
||||
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)
|
||||
|
||||
@@ -306,7 +306,8 @@ typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
|
||||
#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4
|
||||
#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5
|
||||
#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6
|
||||
#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7
|
||||
#define NV2080_CTRL_NOCAT_TDR_TYPE_GPU_RC_RESET 7
|
||||
#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 8
|
||||
|
||||
typedef struct NV2080CtrlNocatJournalDataTdrReason {
|
||||
NvU32 flags;
|
||||
|
||||
@@ -2574,11 +2574,17 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvBool test_mode;
|
||||
NvBool plr_vld;
|
||||
NvU8 plane_ind;
|
||||
NvU8 port_type;
|
||||
NvU8 lp_msb;
|
||||
NvU8 pnat;
|
||||
NvU8 local_port;
|
||||
NvBool plr_reject_mode_vld;
|
||||
NvBool plr_margin_th_override_to_default;
|
||||
NvU8 plr_reject_mode;
|
||||
NvU8 tx_crc_plr;
|
||||
NvU8 plr_margin_th;
|
||||
NvU8 fec_override_admin_10g_40g;
|
||||
NvU8 fec_override_admin_25g;
|
||||
NvU8 fec_override_admin_50g;
|
||||
@@ -3288,7 +3294,8 @@ typedef enum NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY {
|
||||
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL = 18,
|
||||
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL = 19,
|
||||
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL = 20,
|
||||
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = 21,
|
||||
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_FATAL = 21,
|
||||
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = 22,
|
||||
} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY;
|
||||
|
||||
#define NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID (0x89U)
|
||||
@@ -3298,6 +3305,51 @@ typedef struct NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS {
|
||||
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY severity;
|
||||
} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY
|
||||
*
|
||||
* This command is used to update the NVLE topology in GSP RM
|
||||
*
|
||||
* [in] localGpuAlid
|
||||
* ALID of local GPU in P2P object
|
||||
* [in] localGpuClid
|
||||
* CLID of local GPU in P2P object
|
||||
* [in] remoteGpuAlid
|
||||
* ALID of remote GPU in P2P object
|
||||
* [in] remoteGpuClid
|
||||
* CLID of remote GPU in P2P object
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY (0x2080308cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS_MESSAGE_ID (0x8cU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS {
|
||||
NvU32 localGpuAlid;
|
||||
NvU32 localGpuClid;
|
||||
NvU32 remoteGpuAlid;
|
||||
NvU32 remoteGpuClid;
|
||||
} NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_NVLINK_GET_NVLE_LIDS
|
||||
*
|
||||
* This command is used to get the alid and clid of a GPU from the remap table.
|
||||
*
|
||||
* [in] probeClid
|
||||
* CLID from probe response
|
||||
* [out] clid
|
||||
* CLID of GPU from remap table
|
||||
* [out] alid
|
||||
* ALID of gpu
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_GET_NVLE_LIDS (0x2080308dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS_MESSAGE_ID (0x8dU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS {
|
||||
NvU32 probeClid;
|
||||
NvU32 clid;
|
||||
NvU32 alid;
|
||||
} NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY
|
||||
*
|
||||
@@ -3353,6 +3405,23 @@ typedef struct NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS {
|
||||
NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config[NV2080_CTRL_NVLINK_MAX_LINKS];
|
||||
} NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_GET_NVLE_ENCRYPT_EN_INFO
|
||||
*
|
||||
* This command is used to get the ENCRYPT_EN register info
|
||||
*
|
||||
* [out] bEncyptEnSet
|
||||
* Boolean that shows if ENCRYPT_EN is enabled or not.
|
||||
*/
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_GET_NVLE_ENCRYPT_EN_INFO (0x2080308bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS_MESSAGE_ID (0x8bU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS {
|
||||
NvBool bEncryptEnSet;
|
||||
} NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS;
|
||||
|
||||
|
||||
/* _ctrl2080nvlink_h_ */
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
|
||||
@@ -23,8 +23,395 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <nvtypes.h>
|
||||
|
||||
//
|
||||
// This file was generated with FINN, an NVIDIA coding tool.
|
||||
// Source file: ctrl/ctrl2080/ctrl2080thermal.finn
|
||||
//
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Thermal System rmcontrol api versioning
|
||||
*/
|
||||
#define THERMAL_SYSTEM_API_VER 1U
|
||||
#define THERMAL_SYSTEM_API_REV 0U
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM constants
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_TARGET
|
||||
*
|
||||
* Targets (ie the things the thermal system can observe). Target mask
|
||||
* have to be in sync with corresponding element of NVAPI_THERMAL_TARGET
|
||||
* enum, until there is a translation layer between these two.
|
||||
*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE
|
||||
* There is no target.
|
||||
*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU
|
||||
* The GPU is the target.
|
||||
*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY
|
||||
* The memory is the target.
|
||||
*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY
|
||||
* The power supply is the target.
|
||||
*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD
|
||||
* The board (PCB) is the target.
|
||||
*/
|
||||
|
||||
|
||||
/* NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN
|
||||
* The target is unknown.
|
||||
*/
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE (0x00000000U)
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU (0x00000001U)
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY (0x00000002U)
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY (0x00000004U)
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD (0x00000008U)
|
||||
|
||||
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN (0xFFFFFFFFU)
|
||||
|
||||
/*
|
||||
* executeFlags values
|
||||
*/
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_DEFAULT (0x00000000U)
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_IGNORE_FAIL (0x00000001U)
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2
|
||||
*
|
||||
* This command will execute a list of thermal system instructions:
|
||||
*
|
||||
* clientAPIVersion
|
||||
* This field must be set by the client to THERMAL_SYSTEM_API_VER,
|
||||
* which allows the driver to determine api compatibility.
|
||||
*
|
||||
* clientAPIRevision
|
||||
* This field must be set by the client to THERMAL_SYSTEM_API_REV,
|
||||
* which allows the driver to determine api compatibility.
|
||||
*
|
||||
* clientInstructionSizeOf
|
||||
* This field must be set by the client to
|
||||
* sizeof(NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION), which allows the
|
||||
* driver to determine api compatibility.
|
||||
*
|
||||
* executeFlags
|
||||
* This field is set by the client to control instruction execution.
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_DEFAULT
|
||||
* Execute instructions normally. The first instruction
|
||||
* failure will cause execution to stop.
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_IGNORE_FAIL
|
||||
* Execute all instructions, ignoring individual instruction failures.
|
||||
*
|
||||
* successfulInstructions
|
||||
* This field is set by the driver and is the number of instructions
|
||||
* that returned NV_OK on execution. If this field
|
||||
* matches instructionListSize, all instructions executed successfully.
|
||||
*
|
||||
* instructionListSize
|
||||
* This field is set by the client to the number of instructions in
|
||||
* instruction list.
|
||||
*
|
||||
* instructionList
|
||||
* This field is set an array of thermal system instructions
|
||||
* (NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION) to execute, filled in by the
|
||||
* client.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* NV_ERR_INVALID_PARAM_STRUCT
|
||||
*/
|
||||
|
||||
#define NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2 (0x20800513U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_THERMAL_INTERFACE_ID << 8) | NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2_PHYSICAL (0x20808513U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_THERMAL_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO instructions...
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE instruction
|
||||
*
|
||||
* Get the number of available targets.
|
||||
*
|
||||
* availableTargets
|
||||
* Returns the number of available targets. Targets are
|
||||
* identified by an index, starting with 0.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
*/
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPCODE (0x00000100U)
|
||||
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS {
|
||||
NvU32 availableTargets;
|
||||
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE instruction
|
||||
*
|
||||
* Get a target's type.
|
||||
*
|
||||
* targetIndex
|
||||
* Set by the client to the desired target index.
|
||||
*
|
||||
* type
|
||||
* Returns a target's type.
|
||||
* Possible values returned are:
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPCODE (0x00000101U)
|
||||
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS {
|
||||
NvU32 targetIndex;
|
||||
NvU32 type;
|
||||
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE instruction
|
||||
*
|
||||
* Get a providers's type.
|
||||
*
|
||||
* providerIndex
|
||||
* Set by the client to the desired provider index.
|
||||
*
|
||||
* type
|
||||
* Returns a provider's type.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPCODE (0x00000301U)
|
||||
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS {
|
||||
NvU32 providerIndex;
|
||||
NvU32 type;
|
||||
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE instruction
|
||||
*
|
||||
* Get the number of available sensors.
|
||||
*
|
||||
* availableSensors
|
||||
* Returns the number of available sensors. Sensors are
|
||||
* identified by an index, starting with 0.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
*/
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPCODE (0x00000500U)
|
||||
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS {
|
||||
NvU32 availableSensors;
|
||||
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER instruction
|
||||
*
|
||||
* Get a sensor's provider index.
|
||||
*
|
||||
* sensorIndex
|
||||
* Set by the client to the desired sensor index.
|
||||
*
|
||||
* providerIndex
|
||||
* Returns a sensor's provider index.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPCODE (0x00000510U)
|
||||
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS {
|
||||
NvU32 sensorIndex;
|
||||
NvU32 providerIndex;
|
||||
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS;
|
||||
|
||||
/*!
|
||||
* Union of mode-specific arguments.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING instruction
|
||||
*
|
||||
* Get a sensor's current reading.
|
||||
*
|
||||
* sensorIndex
|
||||
* Set by the client to the desired sensor index.
|
||||
*
|
||||
* value
|
||||
* Returns a sensor's current reading.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPCODE (0x00001500U)
|
||||
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS {
|
||||
NvU32 sensorIndex;
|
||||
NvS32 value;
|
||||
} NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET instruction
|
||||
*
|
||||
* Get a sensor's target index.
|
||||
*
|
||||
* sensorIndex
|
||||
* Set by the client to the desired sensor index.
|
||||
*
|
||||
* targetIndex
|
||||
* Returns a sensor's target index.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPCODE (0x00000520U)
|
||||
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS {
|
||||
NvU32 sensorIndex;
|
||||
NvU32 targetIndex;
|
||||
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE instruction
|
||||
*
|
||||
* Get a sensor's readings range (ie min, max).
|
||||
*
|
||||
* sensorIndex
|
||||
* Set by the client to the desired sensor index.
|
||||
*
|
||||
* minimum
|
||||
* Returns a sensor's range minimum.
|
||||
*
|
||||
* maximum
|
||||
* Returns a sensor's range maximum.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPCODE (0x00000540U)
|
||||
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS {
|
||||
NvU32 sensorIndex;
|
||||
NvS32 minimum;
|
||||
NvS32 maximum;
|
||||
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS;
|
||||
|
||||
/*
|
||||
* Thermal System instruction operand
|
||||
*/
|
||||
typedef union NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS {
|
||||
|
||||
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS getInfoTargetsAvailable;
|
||||
|
||||
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS getInfoTargetType;
|
||||
|
||||
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS getInfoProviderType;
|
||||
|
||||
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS getInfoSensorsAvailable;
|
||||
|
||||
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS getInfoSensorProvider;
|
||||
|
||||
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS getInfoSensorTarget;
|
||||
|
||||
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS getInfoSensorReadingRange;
|
||||
|
||||
NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS getStatusSensorReading;
|
||||
|
||||
|
||||
NvU32 space[8];
|
||||
} NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION
|
||||
*
|
||||
* All thermal system instructions have the following layout:
|
||||
*
|
||||
* result
|
||||
* This field is set by the driver, and is the result of the
|
||||
* instruction's execution. This value is only valid if the
|
||||
* executed field is not 0 upon return.
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* NV_ERR_INVALID_PARAM_STRUCT
|
||||
*
|
||||
* executed
|
||||
* This field is set by the driver, and
|
||||
* indicates if the instruction was executed.
|
||||
* Possible status values returned are:
|
||||
* 0: Not executed
|
||||
* 1: Executed
|
||||
*
|
||||
* opcode
|
||||
* This field is set by the client to the desired instruction opcode.
|
||||
* Possible values are:
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPCODE
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPCODE
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPCODE
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPCODE
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPCODE
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPCODE
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPCODE
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* operands
|
||||
* This field is actually a union of all of the available operands.
|
||||
* The interpretation of this field is opcode context dependent.
|
||||
* Possible values are:
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS
|
||||
* NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS
|
||||
*/
|
||||
|
||||
|
||||
typedef struct NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION {
|
||||
NvU32 result;
|
||||
NvU32 executed;
|
||||
NvU32 opcode;
|
||||
NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS operands;
|
||||
} NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION;
|
||||
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_MAX_COUNT 0x20U
|
||||
#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID (0x13U)
|
||||
|
||||
typedef struct NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS {
|
||||
NvU32 clientAPIVersion;
|
||||
NvU32 clientAPIRevision;
|
||||
NvU32 clientInstructionSizeOf;
|
||||
NvU32 executeFlags;
|
||||
NvU32 successfulInstructions;
|
||||
NvU32 instructionListSize;
|
||||
NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION instructionList[NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_MAX_COUNT];
|
||||
} NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS;
|
||||
|
||||
/* _ctrl2080thermal_h_ */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -468,6 +468,9 @@ typedef struct NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS {
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_OBJECT_NOT_FOUND
|
||||
* NV_ERR_INVALID_STATE
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE (0x2080400e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0xEU)
|
||||
@@ -476,4 +479,24 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS
|
||||
NvBool bHeterogeneousMode;
|
||||
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE
|
||||
*
|
||||
* This command will set MIG timeslice mode in GSP RM
|
||||
*
|
||||
* bMigTimeslicingModeEnabled
|
||||
* Mode of MIG timeslice
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_OBJECT_NOT_FOUND
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE (0x2080400f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS_MESSAGE_ID (0xFU)
|
||||
|
||||
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS {
|
||||
NvBool bMigTimeslicingModeEnabled;
|
||||
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS;
|
||||
|
||||
|
||||
/* _ctrl2080vgpumgrinternal_h_ */
|
||||
|
||||
@@ -48,5 +48,6 @@
|
||||
#include "ctrl208f/ctrl208fdma.h"
|
||||
#include "ctrl208f/ctrl208fmmu.h"
|
||||
#include "ctrl208f/ctrl208fucodecoverage.h"
|
||||
#include "ctrl208f/ctrl208fnvlink.h"
|
||||
#include "ctrl208f/ctrl208fpmu.h"
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -31,30 +31,33 @@
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
/* NV20_SUBDEVICE_DIAG: diagnostic class control commands and parameters */
|
||||
|
||||
#define NV208F_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x208F, NV208F_CTRL_##cat, idx)
|
||||
#define NV208F_CTRL_CMD(cat, idx) NVXXXX_CTRL_CMD(0x208F, NV208F_CTRL_##cat, idx)
|
||||
|
||||
/* Subdevice diag command categories (6bits) */
|
||||
#define NV208F_CTRL_RESERVED (0x00)
|
||||
#define NV208F_CTRL_POWER (0x01)
|
||||
#define NV208F_CTRL_THERMAL (0x02)
|
||||
#define NV208F_CTRL_SEQ (0x03)
|
||||
#define NV208F_CTRL_FIFO (0x04)
|
||||
#define NV208F_CTRL_FB (0x05)
|
||||
#define NV208F_CTRL_MC (0x06)
|
||||
#define NV208F_CTRL_BIF (0x07)
|
||||
#define NV208F_CTRL_CLK (0x08)
|
||||
#define NV208F_CTRL_PERF (0x09)
|
||||
#define NV208F_CTRL_FBIO (0x0A)
|
||||
#define NV208F_CTRL_MMU (0x0B)
|
||||
#define NV208F_CTRL_PMU (0x0C)
|
||||
#define NV208F_CTRL_EVENT (0x10)
|
||||
#define NV208F_CTRL_GPU (0x11)
|
||||
#define NV208F_CTRL_GR (0x12)
|
||||
#define NV208F_CTRL_PMGR (0x13)
|
||||
#define NV208F_CTRL_DMA (0x14)
|
||||
/* Subdevice diag command categories (6 bits) */
|
||||
#define NV208F_CTRL_RESERVED (0x00)
|
||||
#define NV208F_CTRL_POWER (0x01)
|
||||
#define NV208F_CTRL_THERMAL (0x02)
|
||||
#define NV208F_CTRL_SEQ (0x03)
|
||||
#define NV208F_CTRL_FIFO (0x04)
|
||||
#define NV208F_CTRL_FB (0x05)
|
||||
#define NV208F_CTRL_MC (0x06)
|
||||
#define NV208F_CTRL_BIF (0x07)
|
||||
#define NV208F_CTRL_CLK (0x08)
|
||||
#define NV208F_CTRL_PERF (0x09)
|
||||
#define NV208F_CTRL_FBIO (0x0A)
|
||||
#define NV208F_CTRL_MMU (0x0B)
|
||||
#define NV208F_CTRL_PMU (0x0C)
|
||||
#define NV208F_CTRL_EVENT (0x10)
|
||||
#define NV208F_CTRL_GPU (0x11)
|
||||
#define NV208F_CTRL_GR (0x12)
|
||||
#define NV208F_CTRL_PMGR (0x13)
|
||||
#define NV208F_CTRL_DMA (0x14)
|
||||
// const NV208F_CTRL_TMR = (0x15); // not supported
|
||||
#define NV208F_CTRL_GSPMSGTIMING (0x16)
|
||||
#define NV208F_CTRL_BUS (0x17)
|
||||
#define NV208F_CTRL_SEC2 (0x16)
|
||||
#define NV208F_CTRL_GSPMSGTIMING (0x17)
|
||||
#define NV208F_CTRL_BUS (0x18)
|
||||
#define NV208F_CTRL_UCODE_COVERAGE (0x19)
|
||||
#define NV208F_CTRL_NVLINK (0x1A)
|
||||
|
||||
/*
|
||||
* NV208F_CTRL_CMD_NULL
|
||||
@@ -65,6 +68,6 @@
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
*/
|
||||
#define NV208F_CTRL_CMD_NULL (0x208f0000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID << 8) | 0x0" */
|
||||
#define NV208F_CTRL_CMD_NULL (0x208f0000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID << 8) | 0x0" */
|
||||
|
||||
/* _ctrl208fbase_h_ */
|
||||
|
||||
96
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fnvlink.h
Normal file
96
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fnvlink.h
Normal file
@@ -0,0 +1,96 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <nvtypes.h>
|
||||
|
||||
//
|
||||
// This file was generated with FINN, an NVIDIA coding tool.
|
||||
// Source file: ctrl/ctrl208f/ctrl208fnvlink.finn
|
||||
//
|
||||
|
||||
#include "ctrl/ctrl208f/ctrl208fbase.h"
|
||||
|
||||
/*
|
||||
* NV208F_CTRL_CMD_NVLINK_ECC_INJECT_ERROR
|
||||
*
|
||||
* This ctrl call injects NVLink SAW, RLW, and TLW ECC errors. Please see the confluence
|
||||
* page "ECC" for more information on ECC and ECC injection:
|
||||
*
|
||||
* Parameters:
|
||||
*
|
||||
* errorUnit
|
||||
* Specifies the HW unit where the injection will occur.
|
||||
*
|
||||
* errorType
|
||||
* Specifies whether the injected error will be correctable or uncorrectable.
|
||||
* Correctable errors have no effect on running programs while uncorrectable
|
||||
* errors will cause all channels to be torn down.
|
||||
*
|
||||
* linkMask
|
||||
* Specifies the mask of links to inject into where bit 0 = link 0, etc.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV208F_CTRL_CMD_NVLINK_ECC_INJECT_ERROR (0x208f1a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_NVLINK_INTERFACE_ID << 8) | NV208F_CTRL_NVLINK_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */
|
||||
|
||||
|
||||
|
||||
#define NV208F_CTRL_NVLINK_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x1U)
|
||||
|
||||
typedef struct NV208F_CTRL_NVLINK_ECC_INJECT_ERROR_PARAMS {
|
||||
NvU8 errorUnit;
|
||||
NvU8 errorType;
|
||||
NvU32 linkMask;
|
||||
} NV208F_CTRL_NVLINK_ECC_INJECT_ERROR_PARAMS;
|
||||
|
||||
/*
|
||||
* NV208F_CTRL_CMD_NVLINK_ECC_INJECTION_SUPPORTED
|
||||
*
|
||||
* Reports if error injection is supported for the NVLink
|
||||
*
|
||||
* bCorrectableSupported [out]:
|
||||
* Boolean value that shows if correcatable errors can be injected.
|
||||
*
|
||||
* bUncorrectableSupported [out]:
|
||||
* Boolean value that shows if uncorrecatable errors can be injected.
|
||||
*
|
||||
* Return values:
|
||||
* NV_OK on success
|
||||
* NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled.
|
||||
* NV_ERR_NOT_SUPPORTED otherwise
|
||||
*/
|
||||
#define NV208F_CTRL_CMD_NVLINK_ECC_INJECTION_SUPPORTED (0x208f1a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_NVLINK_INTERFACE_ID << 8) | NV208F_CTRL_NVLINK_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV208F_CTRL_NVLINK_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x2U)
|
||||
|
||||
typedef struct NV208F_CTRL_NVLINK_ECC_INJECTION_SUPPORTED_PARAMS {
|
||||
NvU8 errorUnit;
|
||||
NvBool bCorrectableSupported;
|
||||
NvBool bUncorrectableSupported;
|
||||
} NV208F_CTRL_NVLINK_ECC_INJECTION_SUPPORTED_PARAMS;
|
||||
/* _ctrl208fnvlink_h_ */
|
||||
@@ -231,6 +231,7 @@ typedef struct NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS {
|
||||
NvU32 syncStartDelay;
|
||||
NvU32 useHouseSync;
|
||||
NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS syncMulDiv;
|
||||
NvU32 syncVRR;
|
||||
} NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS;
|
||||
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x3U)
|
||||
@@ -246,30 +247,32 @@ typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PA
|
||||
*
|
||||
*/
|
||||
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE 0x0040
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE 0x0040
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_VRR 0x0080
|
||||
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_MULTIPLY_DIVIDE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_MULTIPLY_DIVIDE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_VRR NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_VRR
|
||||
|
||||
/*
|
||||
* syncPolarity values
|
||||
*
|
||||
*/
|
||||
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2
|
||||
|
||||
/*
|
||||
* syncVideoMode values
|
||||
@@ -277,23 +280,30 @@ typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PA
|
||||
*
|
||||
*/
|
||||
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3
|
||||
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV
|
||||
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4
|
||||
|
||||
/*
|
||||
* multiplyDivide values
|
||||
*
|
||||
*/
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY 0
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE 1
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY 0
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE 1
|
||||
|
||||
/*
|
||||
* VRR values
|
||||
*
|
||||
*/
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MODE_FIXED_REFRESH_RATE 0
|
||||
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MODE_VARIABLE_REFRESH_RATE 1
|
||||
|
||||
/*
|
||||
* NV30F1_CTRL_CMD_GSYNC_GET_CAPS
|
||||
@@ -366,7 +376,7 @@ typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PA
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
|
||||
#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */
|
||||
#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID (0x5U)
|
||||
|
||||
|
||||
@@ -39,7 +39,6 @@
|
||||
/* NV50_GPFIFO command categories (6bits) */
|
||||
#define NV506F_CTRL_RESERVED (0x00)
|
||||
#define NV506F_CTRL_GPFIFO (0x01)
|
||||
#define NV506F_CTRL_EVENT (0x02)
|
||||
|
||||
/*
|
||||
* NV506F_CTRL_CMD_NULL
|
||||
@@ -77,17 +76,6 @@
|
||||
|
||||
#define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL (0x506f0105) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV506F_CTRL_CMD_EVENT_SET_TRIGGER (deprecated on Fermi+)
|
||||
*
|
||||
* This command triggers a software event for the associated channel.
|
||||
* This command accepts no parameters.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
*/
|
||||
// #define NV506F_CTRL_CMD_EVENT_SET_TRIGGER NV506F_CTRL_CMD(EVENT, 0x09)
|
||||
|
||||
#define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID (0x5U)
|
||||
|
||||
typedef struct NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS {
|
||||
|
||||
@@ -42,7 +42,6 @@
|
||||
/* GF100_GPFIFO command categories (6bits) */
|
||||
#define NV906F_CTRL_RESERVED (0x00)
|
||||
#define NV906F_CTRL_GPFIFO (0x01)
|
||||
#define NV906F_CTRL_EVENT (0x02)
|
||||
|
||||
|
||||
/*
|
||||
@@ -147,50 +146,7 @@ typedef struct NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS {
|
||||
NvBool bIsRcPending;
|
||||
} NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS;
|
||||
|
||||
/*
|
||||
* NV906F_CTRL_CMD_EVENT_SET_NOTIFICATION
|
||||
*
|
||||
* This command sets event notification state for the associated channel.
|
||||
* This command requires that an instance of NV01_EVENT has been previously
|
||||
* bound to the associated channel object.
|
||||
*
|
||||
* event
|
||||
* This parameter specifies the type of event to which the specified
|
||||
* action is to be applied. This parameter must specify a valid
|
||||
* NV906F_NOTIFIERS value (see cl906f.h for more details) and should
|
||||
* not exceed one less NV906F_NOTIFIERS_MAXCOUNT.
|
||||
* action
|
||||
* This parameter specifies the desired event notification action.
|
||||
* Valid notification actions include:
|
||||
* NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_DISABLE
|
||||
* This action disables event notification for the specified
|
||||
* event for the associated channel object.
|
||||
* NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_SINGLE
|
||||
* This action enables single-shot event notification for the
|
||||
* specified event for the associated channel object.
|
||||
* NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_REPEAT
|
||||
* This action enables repeated event notification for the specified
|
||||
* event for the associated channel object.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_PARAM_STRUCT
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* NV_ERR_INVALID_STATE
|
||||
*/
|
||||
#define NV906F_CTRL_CMD_EVENT_SET_NOTIFICATION (0x906f0203) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_EVENT_INTERFACE_ID << 8) | NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x3U)
|
||||
|
||||
typedef struct NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
|
||||
NvU32 event;
|
||||
NvU32 action;
|
||||
} NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
|
||||
|
||||
/* valid action values */
|
||||
#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
|
||||
#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
|
||||
#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
|
||||
|
||||
/*
|
||||
* NV906F_CTRL_CMD_GET_DEFER_RC_STATE
|
||||
@@ -206,6 +162,7 @@ typedef struct NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
*/
|
||||
|
||||
#define NV906F_CTRL_CMD_GET_DEFER_RC_STATE (0x906f0105) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID (0x5U)
|
||||
|
||||
@@ -53,7 +53,7 @@
|
||||
*/
|
||||
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrla06f.h" /* A06C is partially derived from A06F */
|
||||
#include "ctrl/ctrla06f/ctrla06fgpfifo.h" /* A06C is partially derived from A06F */
|
||||
|
||||
#include "ctrl/ctrl2080/ctrl2080internal.h" /* For NV2080_CTRL_INTERNAL_MEMDESC_INFO */
|
||||
#include "ctrl/ctrlc36f.h" /* For NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES */
|
||||
|
||||
@@ -33,5 +33,4 @@
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrla06f/ctrla06fbase.h"
|
||||
#include "ctrl/ctrla06f/ctrla06fgpfifo.h"
|
||||
#include "ctrl/ctrla06f/ctrla06fevent.h"
|
||||
#include "ctrl/ctrla06f/ctrla06finternal.h"
|
||||
|
||||
@@ -42,7 +42,6 @@
|
||||
/* GK100_GPFIFO command categories (6bits) */
|
||||
#define NVA06F_CTRL_RESERVED (0x00)
|
||||
#define NVA06F_CTRL_GPFIFO (0x01)
|
||||
#define NVA06F_CTRL_EVENT (0x02)
|
||||
#define NVA06F_CTRL_INTERNAL (0x03)
|
||||
|
||||
/*
|
||||
|
||||
@@ -1,92 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <nvtypes.h>
|
||||
|
||||
//
|
||||
// This file was generated with FINN, an NVIDIA coding tool.
|
||||
// Source file: ctrl/ctrla06f/ctrla06fevent.finn
|
||||
//
|
||||
|
||||
#include "ctrl/ctrla06f/ctrla06fbase.h"
|
||||
|
||||
/*
|
||||
* NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION
|
||||
*
|
||||
* This command sets event notification state for the associated channel.
|
||||
* This command requires that an instance of NV01_EVENT has been previously
|
||||
* bound to the associated channel object.
|
||||
*
|
||||
* event
|
||||
* This parameter specifies the type of event to which the specified
|
||||
* action is to be applied. This parameter must specify a valid
|
||||
* NVA06F_NOTIFIERS value (see cla06f.h for more details) and should
|
||||
* not exceed one less NVA06F_NOTIFIERS_MAXCOUNT.
|
||||
* action
|
||||
* This parameter specifies the desired event notification action.
|
||||
* Valid notification actions include:
|
||||
* NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_DISABLE
|
||||
* This action disables event notification for the specified
|
||||
* event for the associated channel object.
|
||||
* NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_SINGLE
|
||||
* This action enables single-shot event notification for the
|
||||
* specified event for the associated channel object.
|
||||
* NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_REPEAT
|
||||
* This action enables repeated event notification for the specified
|
||||
* event for the associated channel object.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_PARAM_STRUCT
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* NV_ERR_INVALID_STATE
|
||||
*/
|
||||
#define NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa06f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U)
|
||||
|
||||
typedef struct NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
|
||||
NvU32 event;
|
||||
NvU32 action;
|
||||
} NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
|
||||
|
||||
/* valid action values */
|
||||
#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
|
||||
#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
|
||||
#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
|
||||
|
||||
/*
|
||||
* NVA06F_CTRL_CMD_EVENT_SET_TRIGGER
|
||||
*
|
||||
* This command triggers a software event for the associated channel.
|
||||
* This command accepts no parameters.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
*/
|
||||
#define NVA06F_CTRL_CMD_EVENT_SET_TRIGGER (0xa06f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
|
||||
|
||||
|
||||
/* _ctrla06fevent_h_ */
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2007-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2007-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -44,6 +44,18 @@
|
||||
* When set, the channel will be enabled in addition to being added to the appropriate runlist.
|
||||
* When not set, the channel will be disabled and removed from runlist.
|
||||
*
|
||||
* bSkipSubmit
|
||||
* This parameter indicates whether this channel is not to be scheduled, even though it is enabled.
|
||||
* When set, the channel will not be scheduled.
|
||||
* When not set, the channel will be scheduled.
|
||||
*
|
||||
* bSkipEnable
|
||||
* This parameter indicates whether this channel is not to be enabled, even though it is scheduled.
|
||||
* When set, the channel will not be enabled.
|
||||
* When not set, the channel will be enabled.
|
||||
*
|
||||
* When bEnable is set, both bSkipSubmit and bSkipEnable can't be set.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_OBJECT_HANDLE
|
||||
@@ -57,6 +69,7 @@
|
||||
typedef struct NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS {
|
||||
NvBool bEnable;
|
||||
NvBool bSkipSubmit;
|
||||
NvBool bSkipEnable;
|
||||
} NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS;
|
||||
|
||||
/*
|
||||
|
||||
@@ -393,12 +393,18 @@ typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS {
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS 21:21
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_FALSE (0x00000000)
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_TRUE (0x00000001)
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED 22:22
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED 22:22
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_FALSE (0x00000000)
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_TRUE (0x00000001)
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED 23:23
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED 23:23
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_FALSE (0x00000000)
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_TRUE (0x00000001)
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPM_ENABLED 24:24
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPM_ENABLED_FALSE (0x00000000)
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPM_ENABLED_TRUE (0x00000001)
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CI_MANIPULATION_ENABLED 25:25
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CI_MANIPULATION_ENABLED_FALSE (0x00000000)
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CI_MANIPULATION_ENABLED_TRUE (0x00000001)
|
||||
|
||||
/* UVM supported features */
|
||||
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED 0:0
|
||||
|
||||
@@ -33,6 +33,7 @@
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrl2080/ctrl2080gpu.h"
|
||||
#include "nv_vgpu_types.h"
|
||||
#include "nvcfg_sdk.h"
|
||||
/* NVA081_VGPU_CONFIG control commands and parameters */
|
||||
|
||||
#define NVA081_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA081, NVA081_CTRL_##cat, idx)
|
||||
@@ -42,8 +43,9 @@
|
||||
#define NVA081_CTRL_VGPU_CONFIG (0x01)
|
||||
|
||||
#define NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE 0x00
|
||||
#define NVA081_MAX_VGPU_TYPES_PER_PGPU 0x40
|
||||
#define NVA081_MAX_VGPU_TYPES_PER_PGPU 0x64
|
||||
#define NVA081_MAX_VGPU_PER_PGPU 32
|
||||
#define NVA081_MAX_VGPU_PER_GI 12
|
||||
#define NVA081_VM_UUID_SIZE 16
|
||||
#define NVA081_VGPU_STRING_BUFFER_SIZE 32
|
||||
#define NVA081_VGPU_SIGNATURE_SIZE 128
|
||||
@@ -118,6 +120,7 @@ typedef struct NVA081_CTRL_VGPU_INFO {
|
||||
NvU32 ftraceEnable;
|
||||
NvU32 gpuDirectSupported;
|
||||
NvU32 nvlinkP2PSupported;
|
||||
NvU32 maxInstancePerGI;
|
||||
NvU32 multiVgpuExclusive;
|
||||
NvU32 exclusiveType;
|
||||
NvU32 exclusiveSize;
|
||||
@@ -329,6 +332,11 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS {
|
||||
* This structure represents supported/creatable vGPU types on a pGPU
|
||||
*/
|
||||
typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS {
|
||||
/*
|
||||
* [IN] GPU Instance ID or Swizz ID
|
||||
*/
|
||||
NvU32 gpuInstanceId;
|
||||
|
||||
/*
|
||||
* [OUT] vGPU config state on a pGPU
|
||||
*/
|
||||
@@ -793,6 +801,9 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_UPDATE_PLACEMENT_INFO_PARAMS {
|
||||
*
|
||||
* Parameters:
|
||||
*
|
||||
* gpuInstanceId [IN]
|
||||
* GPU Instance ID or Swizz ID
|
||||
*
|
||||
* vgpuTypeId [IN]
|
||||
* The client provided vGPU type ID
|
||||
*
|
||||
@@ -816,6 +827,7 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_UPDATE_PLACEMENT_INFO_PARAMS {
|
||||
#define NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS_MESSAGE_ID (0x1cU)
|
||||
|
||||
typedef struct NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS {
|
||||
NvU32 gpuInstanceId;
|
||||
NvU32 vgpuTypeId;
|
||||
NvU32 placementSize;
|
||||
NvU32 count;
|
||||
@@ -855,6 +867,11 @@ typedef struct NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS {
|
||||
#define NVA081_CTRL_VGPU_CAPABILITY_FRACTIONAL_MULTI_VGPU 8
|
||||
#define NVA081_CTRL_VGPU_CAPABILITY_HOMOGENEOUS_PLACEMENT_ID 9
|
||||
|
||||
#define NVA081_CTRL_VGPU_CAPABILITY_MIG_TIMESLICING_SUPPORTED 10
|
||||
#define NVA081_CTRL_VGPU_CAPABILITY_MIG_TIMESLICING_MODE_ENABLED 11
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* NVA081_CTRL_CMD_VGPU_SET_CAPABILITY
|
||||
*
|
||||
@@ -1010,4 +1027,33 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS {
|
||||
NvU32 migrationBandwidth;
|
||||
} NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS;
|
||||
|
||||
/*
|
||||
* NVA081_CTRL_CMD_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE
|
||||
*
|
||||
* This command enumerates list of vGPU guest instances per GPU instance
|
||||
*
|
||||
* gpuInstanceId [IN]
|
||||
* This parameter specifies the GPU Instance Id or Swizz Id
|
||||
*
|
||||
* numVgpu [OUT]
|
||||
* This parameter specifies the number of virtual GPUs created on a GPU instance
|
||||
*
|
||||
* vgpuInstanceIds [OUT]
|
||||
* This parameter specifies an array of vGPU type ids active on a GPU instance
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_OBJECT_NOT_FOUND
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
#define NVA081_CTRL_CMD_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE (0xa0810124) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS_MESSAGE_ID (0x24U)
|
||||
|
||||
typedef struct NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS {
|
||||
NvU32 gpuInstanceId;
|
||||
NvU32 numVgpu;
|
||||
NvU32 vgpuInstanceIds[NVA081_MAX_VGPU_PER_GI];
|
||||
} NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS;
|
||||
|
||||
/* _ctrlA081vgpuconfig_h_ */
|
||||
|
||||
@@ -34,15 +34,11 @@
|
||||
/* GK100_GPFIFO control commands and parameters */
|
||||
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrla06f.h" /* A16F is partially derived from A06F */
|
||||
#include "ctrl/ctrl906f.h" /* A16F is partially derived from 906F */
|
||||
#define NVA16F_CTRL_CMD(cat,idx) \
|
||||
NVXXXX_CTRL_CMD(0xA16F, NVA16F_CTRL_##cat, idx)
|
||||
|
||||
/* GK100_GPFIFO command categories (6bits) */
|
||||
#define NVA16F_CTRL_RESERVED (0x00)
|
||||
#define NVA16F_CTRL_GPFIFO (0x01)
|
||||
#define NVA16F_CTRL_EVENT (0x02)
|
||||
|
||||
/*
|
||||
* NVA16F_CTRL_CMD_NULL
|
||||
@@ -55,13 +51,3 @@
|
||||
*/
|
||||
#define NVA16F_CTRL_CMD_NULL (0xa16f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID << 8) | 0x0" */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* NVA16F_CTRL_CMD_EVENT_SET_TRIGGER
|
||||
*
|
||||
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
|
||||
*/
|
||||
#define NVA16F_CTRL_CMD_EVENT_SET_TRIGGER (0xa16f0106) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x6" */
|
||||
|
||||
/* _ctrla16f.h_ */
|
||||
|
||||
@@ -34,15 +34,11 @@
|
||||
/* GK20A_GPFIFO control commands and parameters */
|
||||
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrla06f.h" /* A26F is partially derived from A06F */
|
||||
#include "ctrl/ctrl906f.h" /* A26F is partially derived from 906F */
|
||||
#define NVA26F_CTRL_CMD(cat,idx) \
|
||||
NVXXXX_CTRL_CMD(0xA26F, NVA26F_CTRL_##cat, idx)
|
||||
|
||||
/* GK20A_GPFIFO command categories (6bits) */
|
||||
#define NVA26F_CTRL_RESERVED (0x00)
|
||||
#define NVA26F_CTRL_GPFIFO (0x01)
|
||||
#define NVA26F_CTRL_EVENT (0x02)
|
||||
|
||||
/*
|
||||
* NVA26F_CTRL_CMD_NULL
|
||||
@@ -55,13 +51,3 @@
|
||||
*/
|
||||
#define NVA26F_CTRL_CMD_NULL (0xa26f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID << 8) | 0x0" */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* NVA26F_CTRL_CMD_EVENT_SET_TRIGGER
|
||||
*
|
||||
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
|
||||
*/
|
||||
#define NVA26F_CTRL_CMD_EVENT_SET_TRIGGER (0xa26f0106) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x6" */
|
||||
|
||||
/* _ctrla26f.h_ */
|
||||
|
||||
@@ -36,15 +36,12 @@
|
||||
/* MAXWELL_CHANNEL_GPFIFO_A control commands and parameters */
|
||||
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrla06f.h" /* B06F is partially derived from A06F */
|
||||
#include "ctrl/ctrl906f.h" /* B06F is partially derived from 906F */
|
||||
#define NVB06F_CTRL_CMD(cat,idx) \
|
||||
NVXXXX_CTRL_CMD(0xB06F, NVB06F_CTRL_##cat, idx)
|
||||
|
||||
/* MAXWELL_CHANNEL_GPFIFO_A command categories (6bits) */
|
||||
#define NVB06F_CTRL_RESERVED (0x00)
|
||||
#define NVB06F_CTRL_GPFIFO (0x01)
|
||||
#define NVB06F_CTRL_EVENT (0x02)
|
||||
|
||||
/*
|
||||
* NVB06F_CTRL_CMD_NULL
|
||||
@@ -366,13 +363,3 @@ typedef struct NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS {
|
||||
NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS params;
|
||||
} NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS;
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* NVB06F_CTRL_CMD_EVENT_SET_TRIGGER
|
||||
*
|
||||
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
|
||||
*/
|
||||
#define NVB06F_CTRL_CMD_EVENT_SET_TRIGGER (0xb06f0206) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
|
||||
|
||||
/* _ctrlb06f.h_ */
|
||||
|
||||
@@ -403,6 +403,7 @@ typedef enum NVB0CC_CHIPLET_TYPE {
|
||||
NVB0CC_CHIPLET_TYPE_FBP = 1,
|
||||
NVB0CC_CHIPLET_TYPE_GPC = 2,
|
||||
NVB0CC_CHIPLET_TYPE_SYS = 3,
|
||||
|
||||
} NVB0CC_CHIPLET_TYPE;
|
||||
|
||||
typedef enum NVB0CC_HS_CREDITS_CMD_STATUS {
|
||||
|
||||
@@ -34,15 +34,9 @@
|
||||
/* PASCAL_CHANNEL_GPFIFO_A control commands and parameters */
|
||||
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrla06f.h" /* C06F is partially derived from A06F */
|
||||
#include "ctrl/ctrl906f.h" /* C06F is partially derived from 906F */
|
||||
#define NVC06F_CTRL_CMD(cat,idx) \
|
||||
NVXXXX_CTRL_CMD(0xC06F, NVC06F_CTRL_##cat, idx)
|
||||
|
||||
/* PASCAL_CHANNEL_GPFIFO_B command categories (6bits) */
|
||||
#define NVC06F_CTRL_RESERVED (0x00)
|
||||
#define NVC06F_CTRL_GPFIFO (0x01)
|
||||
#define NVC06F_CTRL_EVENT (0x02)
|
||||
|
||||
/*
|
||||
* NVC06F_CTRL_CMD_NULL
|
||||
@@ -55,12 +49,3 @@
|
||||
*/
|
||||
#define NVC06F_CTRL_CMD_NULL (0xc06f0000) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* NVC06F_CTRL_CMD_EVENT_SET_TRIGGER
|
||||
*
|
||||
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
|
||||
*/
|
||||
#define NVC06F_CTRL_CMD_EVENT_SET_TRIGGER (0xc06f0106) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
|
||||
|
||||
|
||||
@@ -36,15 +36,12 @@
|
||||
/* VOLTA_CHANNEL_GPFIFO_A control commands and parameters */
|
||||
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
|
||||
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
|
||||
#define NVC36F_CTRL_CMD(cat,idx) \
|
||||
NVXXXX_CTRL_CMD(0xC36F, NVC36F_CTRL_##cat, idx)
|
||||
|
||||
/* VOLTA_CHANNEL_GPFIFO_A command categories (6bits) */
|
||||
#define NVC36F_CTRL_RESERVED (0x00)
|
||||
#define NVC36F_CTRL_GPFIFO (0x01)
|
||||
#define NVC36F_CTRL_EVENT (0x02)
|
||||
#define NVC36F_CTRL_INTERNAL (0x03)
|
||||
|
||||
/*
|
||||
@@ -142,22 +139,6 @@ typedef struct NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS {
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION
|
||||
*
|
||||
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
|
||||
*/
|
||||
#define NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc36f0205) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */
|
||||
|
||||
/*
|
||||
* NVC36F_CTRL_CMD_EVENT_SET_TRIGGER
|
||||
*
|
||||
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
|
||||
*/
|
||||
#define NVC36F_CTRL_CMD_EVENT_SET_TRIGGER (0xc36f0206) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN
|
||||
*
|
||||
|
||||
@@ -34,6 +34,17 @@
|
||||
/* C370 is partially derived from 0073 */
|
||||
#include "ctrl/ctrl0073/ctrl0073event.h"
|
||||
|
||||
/*
|
||||
* headId
|
||||
* This parameter indicates the ID of head on which we received interrupt
|
||||
* RgSemId
|
||||
* This parameter indicates the RG Semaphore Index for given head
|
||||
*/
|
||||
typedef struct NVC370_RG_SEM_NOTIFICATION_PARAMS {
|
||||
NvU32 headId;
|
||||
NvU32 rgSemId;
|
||||
} NVC370_RG_SEM_NOTIFICATION_PARAMS;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -362,7 +362,7 @@
|
||||
* if the mode will be possible or not on that head when OSLD is enabled.
|
||||
* The output is only valid if bGetOSLDOutput is set in the head input.
|
||||
* Note that bIsOSLDPossible is only valid if bIsPossible is true.
|
||||
*
|
||||
*
|
||||
* minImpVPState
|
||||
* minImpVPState returns the minimum v-pstate at which the mode is possible
|
||||
* (assuming bIsPossible is TRUE). This output is valid only on dGPU, and
|
||||
|
||||
@@ -34,8 +34,6 @@
|
||||
/* TURING_CHANNEL_GPFIFO_A control commands and parameters */
|
||||
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
|
||||
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
|
||||
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
|
||||
|
||||
#define NVC46F_CTRL_CMD(cat,idx) \
|
||||
@@ -44,7 +42,6 @@
|
||||
/* TURING_CHANNEL_GPFIFO_A command categories (6bits) */
|
||||
#define NVC46F_CTRL_RESERVED (0x00)
|
||||
#define NVC46F_CTRL_GPFIFO (0x01)
|
||||
#define NVC46F_CTRL_EVENT (0x02)
|
||||
|
||||
/*
|
||||
* NVC46F_CTRL_CMD_NULL
|
||||
|
||||
@@ -36,8 +36,6 @@
|
||||
/* AMPERE_CHANNEL_GPFIFO_A control commands and parameters */
|
||||
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
|
||||
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
|
||||
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
|
||||
|
||||
#include "cc_drv.h"
|
||||
@@ -50,7 +48,6 @@
|
||||
/* AMPERE_CHANNEL_GPFIFO_A command categories (6bits) */
|
||||
#define NVC56F_CTRL_RESERVED (0x00)
|
||||
#define NVC56F_CTRL_GPFIFO (0x01)
|
||||
#define NVC56F_CTRL_EVENT (0x02)
|
||||
|
||||
/*
|
||||
* NVC56F_CTRL_CMD_NULL
|
||||
@@ -83,6 +80,11 @@ typedef struct NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR {
|
||||
*
|
||||
* kmb [OUT] The KMB for the channel.
|
||||
* hMemory [IN] Memory handle to the encryption statistics buffer for the channel.
|
||||
* keyRotationLowerThreshold [OUT] Key rotation lower threshold.
|
||||
* keyRotationUpperThreshold [OUT] Key rotation upper threshold.
|
||||
*
|
||||
* The key rotation thresholds are in units of
|
||||
* (amount of data encrypted in units of 16 bytes + number of encryption invocations).
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
@@ -97,6 +99,8 @@ typedef struct NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR {
|
||||
typedef struct NVC56F_CTRL_CMD_GET_KMB_PARAMS {
|
||||
CC_KMB kmb;
|
||||
NvHandle hMemory;
|
||||
NV_DECLARE_ALIGNED(NvU64 keyRotationLowerThreshold, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 keyRotationUpperThreshold, 8);
|
||||
} NVC56F_CTRL_CMD_GET_KMB_PARAMS;
|
||||
|
||||
/*
|
||||
|
||||
@@ -37,8 +37,6 @@
|
||||
/* HOPPER_CHANNEL_GPFIFO_A control commands and parameters */
|
||||
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
|
||||
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
|
||||
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
|
||||
|
||||
#define NVC86F_CTRL_CMD(cat,idx) \
|
||||
@@ -47,7 +45,6 @@
|
||||
/* HOPPER_CHANNEL_GPFIFO_A command categories (6bits) */
|
||||
#define NVC86F_CTRL_RESERVED (0x00)
|
||||
#define NVC86F_CTRL_GPFIFO (0x01)
|
||||
#define NVC86F_CTRL_EVENT (0x02)
|
||||
|
||||
/*
|
||||
* NVC86F_CTRL_CMD_NULL
|
||||
|
||||
@@ -37,8 +37,6 @@
|
||||
/* BLACKWELL_CHANNEL_GPFIFO_A control commands and parameters */
|
||||
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
|
||||
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
|
||||
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
|
||||
|
||||
#define NVC96F_CTRL_CMD(cat,idx) \
|
||||
@@ -47,7 +45,6 @@
|
||||
/* BLACKWELL_CHANNEL_GPFIFO_A command categories (6bits) */
|
||||
#define NVC96F_CTRL_RESERVED (0x00)
|
||||
#define NVC96F_CTRL_GPFIFO (0x01)
|
||||
#define NVC96F_CTRL_EVENT (0x02)
|
||||
|
||||
/*
|
||||
* NVC96F_CTRL_CMD_NULL
|
||||
|
||||
@@ -37,8 +37,6 @@
|
||||
/* BLACKWELL_CHANNEL_GPFIFO_B control commands and parameters */
|
||||
|
||||
#include "ctrl/ctrlxxxx.h"
|
||||
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
|
||||
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
|
||||
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
|
||||
|
||||
#define NVCA6F_CTRL_CMD(cat,idx) \
|
||||
@@ -47,7 +45,6 @@
|
||||
/* BLACKWELL_CHANNEL_GPFIFO_B command categories (6bits) */
|
||||
#define NVCA6F_CTRL_RESERVED (0x00)
|
||||
#define NVCA6F_CTRL_GPFIFO (0x01)
|
||||
#define NVCA6F_CTRL_EVENT (0x02)
|
||||
|
||||
/*
|
||||
* NVCA6F_CTRL_CMD_NULL
|
||||
|
||||
@@ -128,6 +128,7 @@
|
||||
|
||||
#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE 0
|
||||
#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE 1
|
||||
#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NVLE 2
|
||||
|
||||
typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS {
|
||||
NvU8 cpuCapability;
|
||||
|
||||
@@ -347,6 +347,8 @@ typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_ECC;
|
||||
|
||||
#define FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID (0x208003U)
|
||||
typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_EVENT;
|
||||
#define FINN_NV20_SUBDEVICE_0_THERMAL_INTERFACE_ID (0x208005U)
|
||||
typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_THERMAL;
|
||||
|
||||
#define FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID (0x208013U)
|
||||
typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_FB;
|
||||
@@ -404,6 +406,7 @@ typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_POWER;
|
||||
|
||||
#define FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID (0x208022U)
|
||||
typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_RC;
|
||||
|
||||
#define FINN_NV20_SUBDEVICE_0_SEC2_INTERFACE_ID (0x208042U)
|
||||
typedef FINN_RM_API FINN_NV20_SUBDEVICE_0_SEC2;
|
||||
|
||||
@@ -449,6 +452,8 @@ typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_GR;
|
||||
|
||||
#define FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID (0x208f0bU)
|
||||
typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_MMU;
|
||||
#define FINN_NV20_SUBDEVICE_DIAG_NVLINK_INTERFACE_ID (0x208f1AU)
|
||||
typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_NVLINK;
|
||||
|
||||
#define FINN_NV20_SUBDEVICE_DIAG_PMU_INTERFACE_ID (0x208f0cU)
|
||||
typedef FINN_RM_API FINN_NV20_SUBDEVICE_DIAG_PMU;
|
||||
@@ -509,8 +514,6 @@ typedef FINN_RM_API FINN_FERMI_CONTEXT_SHARE_A_CWD_WATERMARK;
|
||||
typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_RESERVED;
|
||||
#define FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID (0x906f01U)
|
||||
typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_GPFIFO;
|
||||
#define FINN_GF100_CHANNEL_GPFIFO_EVENT_INTERFACE_ID (0x906f02U)
|
||||
typedef FINN_RM_API FINN_GF100_CHANNEL_GPFIFO_EVENT;
|
||||
#define FINN_GF100_DISP_SW_RESERVED_INTERFACE_ID (0x907200U)
|
||||
typedef FINN_RM_API FINN_GF100_DISP_SW_RESERVED;
|
||||
#define FINN_GF100_DISP_SW_DISP_SW_INTERFACE_ID (0x907201U)
|
||||
@@ -572,8 +575,6 @@ typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_GPFIFO;
|
||||
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GROUP_A_INTERNAL;
|
||||
#define FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xa06f00U)
|
||||
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_RESERVED;
|
||||
#define FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xa06f02U)
|
||||
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT;
|
||||
#define FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xa06f01U)
|
||||
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO;
|
||||
#define FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID (0xa06f03U)
|
||||
@@ -609,12 +610,8 @@ typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_RESERVED;
|
||||
typedef FINN_RM_API FINN_GK110_SUBDEVICE_FB_FB;
|
||||
#define FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID (0xa16f00U)
|
||||
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED;
|
||||
#define FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID (0xa16f01U)
|
||||
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT;
|
||||
#define FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID (0xa26f00U)
|
||||
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED;
|
||||
#define FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID (0xa26f01U)
|
||||
typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT;
|
||||
#define FINN_MAXWELL_FAULT_BUFFER_A_RESERVED_INTERFACE_ID (0xb06900U)
|
||||
typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_RESERVED;
|
||||
#define FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER_INTERFACE_ID (0xb06901U)
|
||||
@@ -623,8 +620,6 @@ typedef FINN_RM_API FINN_MAXWELL_FAULT_BUFFER_A_FAULTBUFFER;
|
||||
typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_RESERVED;
|
||||
#define FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xb06f01U)
|
||||
typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_GPFIFO;
|
||||
#define FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xb06f02U)
|
||||
typedef FINN_RM_API FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT;
|
||||
#define FINN_MAXWELL_PROFILER_RESERVED_INTERFACE_ID (0xb0cc00U)
|
||||
typedef FINN_RM_API FINN_MAXWELL_PROFILER_RESERVED;
|
||||
#define FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID (0xb0cc02U)
|
||||
@@ -644,8 +639,6 @@ typedef FINN_RM_API FINN_MAXWELL_PROFILER_DEVICE_RESERVED;
|
||||
typedef FINN_RM_API FINN_MAXWELL_SEC2_SEC2;
|
||||
#define FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc06f00U)
|
||||
typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED;
|
||||
#define FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc06f01U)
|
||||
typedef FINN_RM_API FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT;
|
||||
#define FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED_INTERFACE_ID (0xc0e000U)
|
||||
typedef FINN_RM_API FINN_GP100_SUBDEVICE_GRAPHICS_RESERVED;
|
||||
#define FINN_GP100_SUBDEVICE_GRAPHICS_GRAPHICS_INTERFACE_ID (0xc0e001U)
|
||||
@@ -668,8 +661,6 @@ typedef FINN_RM_API FINN_MMU_FAULT_BUFFER_MMU_FAULT_BUFFER;
|
||||
typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_RESERVED;
|
||||
#define FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID (0xc36f01U)
|
||||
typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_GPFIFO;
|
||||
#define FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID (0xc36f02U)
|
||||
typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT;
|
||||
#define FINN_VOLTA_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID (0xc36f03U)
|
||||
typedef FINN_RM_API FINN_VOLTA_CHANNEL_GPFIFO_A_INTERNAL;
|
||||
#define FINN_NVC370_DISPLAY_RESERVED_INTERFACE_ID (0xc37000U)
|
||||
|
||||
@@ -151,6 +151,9 @@
|
||||
#define NVLINK_SW_DEFINED_ERROR (155)
|
||||
#define RESOURCE_RETIREMENT_EVENT (156)
|
||||
#define RESOURCE_RETIREMENT_FAILURE (157)
|
||||
|
||||
#define GPU_FATAL_TIMEOUT (158)
|
||||
#define ROBUST_CHANNEL_CHI_NON_DATA_ERROR (159)
|
||||
#define CHANNEL_RETIREMENT_EVENT (160)
|
||||
#define CHANNEL_RETIREMENT_FAILURE (161)
|
||||
#define ROBUST_CHANNEL_LAST_ERROR (161)
|
||||
|
||||
@@ -701,11 +701,6 @@ nvPrevPow2_U64(const NvU64 x )
|
||||
} \
|
||||
}
|
||||
|
||||
//
|
||||
// Bug 4851259: Newly added functions must be hidden from certain HS-signed
|
||||
// ucode compilers to avoid signature mismatch.
|
||||
//
|
||||
#ifndef NVDEC_1_0
|
||||
/*!
|
||||
* Returns the position of nth set bit in the given mask.
|
||||
*
|
||||
@@ -735,8 +730,6 @@ nvGetNthSetBitIndex32(NvU32 mask, NvU32 n)
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif // NVDEC_1_0
|
||||
|
||||
//
|
||||
// Size to use when declaring variable-sized arrays
|
||||
//
|
||||
@@ -780,12 +773,15 @@ nvGetNthSetBitIndex32(NvU32 mask, NvU32 n)
|
||||
// Returns the offset (in bytes) of 'member' in struct 'type'.
|
||||
#ifndef NV_OFFSETOF
|
||||
#if defined(__GNUC__) && (__GNUC__ > 3)
|
||||
#define NV_OFFSETOF(type, member) ((NvU32)__builtin_offsetof(type, member))
|
||||
#define NV_OFFSETOF(type, member) ((NvUPtr) __builtin_offsetof(type, member))
|
||||
#else
|
||||
#define NV_OFFSETOF(type, member) ((NvU32)(NvU64)&(((type *)0)->member)) // shouldn't we use PtrToUlong? But will need to include windows header.
|
||||
#define NV_OFFSETOF(type, member) ((NvUPtr) &(((type *)0)->member))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Given a pointer and the member it is of the parent struct, return a pointer to the parent struct
|
||||
#define NV_CONTAINEROF(ptr, type, member) ((type *) (((NvUPtr) ptr) - NV_OFFSETOF(type, member)))
|
||||
|
||||
//
|
||||
// Performs a rounded division of b into a (unsigned). For SIGNED version of
|
||||
// NV_ROUNDED_DIV() macro check the comments in bug 769777.
|
||||
|
||||
@@ -632,25 +632,14 @@ typedef void (*BindResultFunc)(void * pVoid, NvU32 gpuMask, NvU32 bState, NvU32
|
||||
// NVOS32 function
|
||||
#define NVOS32_FUNCTION_ALLOC_SIZE 2
|
||||
#define NVOS32_FUNCTION_FREE 3
|
||||
// #define NVOS32_FUNCTION_HEAP_PURGE 4
|
||||
#define NVOS32_FUNCTION_INFO 5
|
||||
#define NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT 6
|
||||
// #define NVOS32_FUNCTION_DESTROY 7
|
||||
// #define NVOS32_FUNCTION_RETAIN 9
|
||||
// #define NVOS32_FUNCTION_REALLOC 10
|
||||
#define NVOS32_FUNCTION_DUMP 11
|
||||
// #define NVOS32_FUNCTION_INFO_TYPE_ALLOC_BLOCKS 12
|
||||
#define NVOS32_FUNCTION_ALLOC_SIZE_RANGE 14
|
||||
#define NVOS32_FUNCTION_REACQUIRE_COMPR 15
|
||||
#define NVOS32_FUNCTION_RELEASE_COMPR 16
|
||||
// #define NVOS32_FUNCTION_MODIFY_DEFERRED_TILES 17
|
||||
#define NVOS32_FUNCTION_GET_MEM_ALIGNMENT 18
|
||||
#define NVOS32_FUNCTION_HW_ALLOC 19
|
||||
#define NVOS32_FUNCTION_HW_FREE 20
|
||||
// #define NVOS32_FUNCTION_SET_OFFSET 21
|
||||
// #define NVOS32_FUNCTION_IS_TILED 22
|
||||
// #define NVOS32_FUNCTION_ENABLE_RESOURCE 23
|
||||
// #define NVOS32_FUNCTION_BIND_COMPR 24
|
||||
#define NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR 27
|
||||
|
||||
typedef struct
|
||||
@@ -659,14 +648,6 @@ typedef struct
|
||||
NvP64 gem NV_ALIGN_BYTES(8);
|
||||
} NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS;
|
||||
|
||||
#define NVOS32_FLAGS_BLOCKINFO_VISIBILITY_CPU (0x00000001)
|
||||
typedef struct
|
||||
{
|
||||
NvU64 startOffset NV_ALIGN_BYTES(8);
|
||||
NvU64 size NV_ALIGN_BYTES(8);
|
||||
NvU32 flags;
|
||||
} NVOS32_BLOCKINFO;
|
||||
|
||||
// NVOS32 IVC-heap number delimiting value
|
||||
#define NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP 0 // When IVC heaps are present,
|
||||
// IVC-heap number specified
|
||||
@@ -792,25 +773,6 @@ typedef struct
|
||||
NvU64 base NV_ALIGN_BYTES(8); // [OUT] - returned heap phys base
|
||||
} Info;
|
||||
|
||||
// NVOS32_FUNCTION_DUMP
|
||||
struct
|
||||
{
|
||||
NvU32 flags; // [IN] - see _DUMP_FLAGS
|
||||
// [IN] - if NULL, numBlocks is the returned number of blocks in
|
||||
// heap, else returns all blocks in eHeap
|
||||
// if non-NULL points to a buffer that is at least numBlocks
|
||||
// * sizeof(NVOS32_HEAP_DUMP_BLOCK) bytes.
|
||||
NvP64 pBuffer NV_ALIGN_BYTES(8);
|
||||
// [IN/OUT] - if pBuffer is NULL, will number of blocks in heap
|
||||
// if pBuffer is non-NULL, is input containing the size of
|
||||
// pBuffer in units of NVOS32_HEAP_DUMP_BLOCK. This must
|
||||
// be greater than or equal to the number of blocks in the
|
||||
// heap.
|
||||
NvU32 numBlocks;
|
||||
} Dump;
|
||||
|
||||
// NVOS32_FUNCTION_DESTROY - no extra parameters needed
|
||||
|
||||
// NVOS32_FUNCTION_ALLOC_SIZE_RANGE
|
||||
struct
|
||||
{
|
||||
@@ -835,12 +797,6 @@ typedef struct
|
||||
NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated
|
||||
} AllocSizeRange;
|
||||
|
||||
// additions for Longhorn
|
||||
#define NVAL_MAX_BANKS (4)
|
||||
#define NVAL_MAP_DIRECTION 0:0
|
||||
#define NVAL_MAP_DIRECTION_DOWN 0x00000000
|
||||
#define NVAL_MAP_DIRECTION_UP 0x00000001
|
||||
|
||||
// NVOS32_FUNCTION_GET_MEM_ALIGNMENT
|
||||
struct
|
||||
{
|
||||
@@ -853,8 +809,6 @@ typedef struct
|
||||
NvU32 alignPitch;
|
||||
NvU32 alignPad;
|
||||
NvU32 alignMask;
|
||||
NvU32 alignOutputFlags[NVAL_MAX_BANKS]; // We could compress this information but it is probably not that big of a deal
|
||||
NvU32 alignBank[NVAL_MAX_BANKS];
|
||||
NvU32 alignKind;
|
||||
NvU32 alignAdjust; // Output -- If non-zero the amount we need to adjust the offset
|
||||
NvU32 alignAttr2;
|
||||
@@ -923,16 +877,6 @@ typedef struct
|
||||
} data;
|
||||
} NVOS32_PARAMETERS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 owner; // owner id - NVOS32_BLOCK_TYPE_FREE or defined by client during heap_alloc
|
||||
NvU32 format; // arch specific format/kind
|
||||
NvU64 begin NV_ALIGN_BYTES(8); // start of allocated memory block
|
||||
NvU64 align NV_ALIGN_BYTES(8); // actual start of usable memory, aligned to chip specific boundary
|
||||
NvU64 end NV_ALIGN_BYTES(8); // end of usable memory. end - align + 1 = size of block
|
||||
} NVOS32_HEAP_DUMP_BLOCK;
|
||||
|
||||
|
||||
#define NVOS32_DELETE_RESOURCES_ALL 0
|
||||
|
||||
// type field
|
||||
@@ -1340,6 +1284,18 @@ typedef struct
|
||||
#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO 0x00000000
|
||||
#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES 0x00000001
|
||||
|
||||
//
|
||||
// Force the video memory allocation to localized allocation.
|
||||
// Same attribute can be used to choose between uGPU0 and uGPU1.
|
||||
// if set to default, RM will choose the next available uGPU memory.
|
||||
// if set to _UGPU0, RM will choose the memory from uGPU0.
|
||||
// if set to _UGPU1, RM will choose the memory from uGPU1.
|
||||
//
|
||||
#define NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY 30:29
|
||||
#define NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY_DEFAULT 0x00000000
|
||||
#define NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY_UGPU0 0x00000001
|
||||
#define NVOS32_ATTR2_ENABLE_LOCALIZED_MEMORY_UGPU1 0x00000002
|
||||
|
||||
//
|
||||
// When allocating memory, register the memory descriptor to GSP-RM
|
||||
// so that GSP-RM is aware of and can access it
|
||||
@@ -2125,6 +2081,17 @@ typedef struct
|
||||
#define NVOS46_FLAGS_DISABLE_ENCRYPTION_FALSE (0x00000000)
|
||||
#define NVOS46_FLAGS_DISABLE_ENCRYPTION_TRUE (0x00000001)
|
||||
|
||||
//
|
||||
// DEFAULT - Use the cache policy set at allocation
|
||||
// YES - Enable gpu caching
|
||||
// NO - Disable gpu caching
|
||||
//
|
||||
#define NVOS46_FLAGS_GPU_CACHEABLE 18:17
|
||||
#define NVOS46_FLAGS_GPU_CACHEABLE_DEFAULT (0x00000000)
|
||||
#define NVOS46_FLAGS_GPU_CACHEABLE_YES (0x00000001)
|
||||
#define NVOS46_FLAGS_GPU_CACHEABLE_NO (0x00000002)
|
||||
#define NVOS46_FLAGS_GPU_CACHEABLE_INVALID (0x00000003)
|
||||
|
||||
#define NVOS46_FLAGS_P2P 27:20
|
||||
|
||||
#define NVOS46_FLAGS_P2P_ENABLE 21:20
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -159,7 +159,11 @@ NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_NOT_READY, 0x00000081, "Nvlink Fabri
|
||||
NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_FAILURE, 0x00000082, "Nvlink Fabric Probe failed")
|
||||
NV_STATUS_CODE(NV_ERR_GPU_MEMORY_ONLINING_FAILURE, 0x00000083, "GPU Memory Onlining failed")
|
||||
NV_STATUS_CODE(NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE, 0x00000084, "Reduction Manager is not available")
|
||||
NV_STATUS_CODE(NV_ERR_THRESHOLD_CROSSED, 0x00000085, "A fatal threshold has been crossed")
|
||||
NV_STATUS_CODE(NV_ERR_RESOURCE_RETIREMENT_ERROR, 0x00000086, "An error occurred while trying to retire a resource")
|
||||
NV_STATUS_CODE(NV_ERR_FABRIC_STATE_OUT_OF_SYNC, 0x00000087, "NVLink fabric state cached by the driver is out of sync")
|
||||
NV_STATUS_CODE(NV_ERR_BUFFER_FULL, 0x00000088, "Buffer is full")
|
||||
NV_STATUS_CODE(NV_ERR_BUFFER_EMPTY, 0x00000089, "Buffer is empty")
|
||||
|
||||
// Warnings:
|
||||
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")
|
||||
@@ -170,5 +174,6 @@ NV_STATUS_CODE(NV_WARN_MORE_PROCESSING_REQUIRED, 0x00010005, "WARNING More
|
||||
NV_STATUS_CODE(NV_WARN_NOTHING_TO_DO, 0x00010006, "WARNING Nothing to do")
|
||||
NV_STATUS_CODE(NV_WARN_NULL_OBJECT, 0x00010007, "WARNING NULL object found")
|
||||
NV_STATUS_CODE(NV_WARN_OUT_OF_RANGE, 0x00010008, "WARNING value out of range")
|
||||
NV_STATUS_CODE(NV_WARN_THRESHOLD_CROSSED, 0x00010009, "WARNING Threshold has been crossed")
|
||||
|
||||
#endif /* SDK_NVSTATUSCODES_H */
|
||||
|
||||
@@ -130,6 +130,7 @@ typedef RmProtoBuf_RECORD *PRmProtoBuf_RECORD;
|
||||
#define NV_RM_JOURNAL_STATE_MASK_VIDMEM_FAILED_BAR0 0x00004000
|
||||
#define NV_RM_JOURNAL_STATE_MASK_VIDMEM_FAILED_BAR2 0x00008000
|
||||
#define NV_RM_JOURNAL_STATE_MASK_VIDMEM_FAILED_FBHUB 0x00010000
|
||||
#define NV_RM_JOURNAL_STATE_MASK_GSP_RM_ENABLED 0x00020000
|
||||
|
||||
|
||||
typedef struct _RmRCCommonJournal_RECORD
|
||||
|
||||
Reference in New Issue
Block a user