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This commit is contained in:
Bernhard Stoeckner
2025-04-17 19:35:38 +02:00
parent e8113f665d
commit 4159579888
1142 changed files with 309085 additions and 272273 deletions
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2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h
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@@ -184,8 +184,6 @@ typedef struct NV0000_CTRL_DIAG_LOCK_METER_ENTRY {
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RELEASE_GPUS (0x00000021)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_DATA (0x00000100)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_RMCTRL (0x00001000)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GET (0x00002000)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SET (0x00002001)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_GETEX (0x00002002)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_CFG_SETEX (0x00002003)
#define NV0000_CTRL_DIAG_LOCK_METER_TAG_VIDHEAP (0x00003000)

58
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,6 +34,13 @@
#include "ctrl/ctrlxxxx.h"
#include "class/cl0000.h"
#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0)
#define NV0000_NOTIFIERS_VGPU_UNBIND_EVENT (1)
#define NV0000_NOTIFIERS_VGPU_BIND_EVENT (2)
#define NV0000_NOTIFIERS_GPU_BIND_UNBIND_EVENT (3)
#define NV0000_NOTIFIERS_MAXCOUNT (4)
/*
* NV0000_CTRL_CMD_EVENT_SET_NOTIFICATION
*
@@ -80,34 +87,59 @@ typedef struct NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
#define NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE {
NvU32 deviceMask;
} NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE;
typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND {
NvU32 gpuId;
} NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND;
typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND {
NvU32 gpuId;
} NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND;
typedef struct NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND {
NvU32 gpuId;
NvBool bBind;
} NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND;
/*
* NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS
* NV0000_CTRL_CMD_GET_SYSTEM_EVENT_DATA
*
* This command returns the status of the specified system event type.
* This command reads the client's event data queue info FIFO order.
* See the description of NV01_EVENT for details on registering events.
*
* event
* This parameter specifies the event type. Valid event type values
* can be found in cl0000.h.
* status
* This parameter returns the status for a given event type. Valid
* status values can be found in cl0000.h.
* Output only as selective event data query is not supported yet.
* Event type.
* Valid event type values can be found in this header file.
*
* data
* Data associated with the event.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_CLIENT
* NV_ERR_OBJECT_NOT_FOUND when system event queue is empty
*
*/
#define NV0000_CTRL_CMD_GET_SYSTEM_EVENT_STATUS (0x502) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_GET_SYSTEM_EVENT_DATA (0x502) /* finn: Evaluated from "(FINN_NV01_ROOT_EVENT_INTERFACE_ID << 8) | NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS_MESSAGE_ID (0x2U)
#define NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS {
typedef struct NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS {
NvU32 event;
NvU32 status;
} NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS;
union {
NV0000_CTRL_SYSTEM_EVENT_DATA_DISPLAY_CHANGE display;
NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_UNBIND vgpuUnbind;
NV0000_CTRL_SYSTEM_EVENT_DATA_VGPU_BIND vgpuBind;
NV0000_CTRL_SYSTEM_EVENT_DATA_GPU_BIND_UNBIND gpuBindUnbind;
} data;
} NV0000_CTRL_GET_SYSTEM_EVENT_DATA_PARAMS;
/* _ctrl0000event_h_ */

5
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
View File

@@ -856,10 +856,6 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
NvU32 dataType; /* [out] - data union type */
union {
struct {
NvU32 newValue;
NvU32 oldValue;
} configSet;
struct {
NvU8 paramData[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA];
NvU32 paramSize;
@@ -872,7 +868,6 @@ typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
} data;
} NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS;
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001U)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002U)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003U)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004U)

49
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
View File

@@ -68,10 +68,6 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS {
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING 3:3
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE (0x00000001U)
@@ -2116,7 +2112,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS {
* NV_ERR_INVALID_REQUEST
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO (0x13bU) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID" */
#define NVPCF_CTRL_SYSPWRLIMIT_TYPE_BASE 1U
#define NV0000_CTRL_SYSTEM_POWER_INFO_INDEX_MAX_SIZE 32U
@@ -2143,9 +2139,12 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT {
NvU32 shortTimescaleBatteryCurrentLimitmA;
} NV0000_CTRL_CMD_SYSTEM_GET_SYSTEM_POWER_LIMIT;
#define NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU)
#define NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS_MESSAGE_ID (0x3BU)
typedef struct NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
/*Buffer to get all the supported functions*/
NvU32 supportedFuncs;
typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
/* GPU ID */
NvU32 gpuId;
@@ -2176,6 +2175,16 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
/* Target total processing power on battery, offset, in milli-Watts. */
NvS32 targetTppBattOffsetmW;
/*
* Maximum allowed output on battery, offset, in milli-Watts.
*/
NvS32 maxOutputBattOffsetmW;
/*
* Minimum allowed output on battery, offset, in milli-Watts.
*/
NvS32 minOutputBattOffsetmW;
/*
* If value specified is larger than the statically assigned ROS reserve in
* the system power limits table, this will take affect.
@@ -2197,15 +2206,6 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
*/
NvU32 dcTspShortTimescaleLimitmA;
/* Require DB on DC to use system power limits table */
NvBool bRequireDcSysPowerLimitsTable;
/* Dynamic params can override ROS reserve used in DB-DC */
NvBool bAllowDcRestOfSystemReserveOverride;
/* Is DC-TSP supported? */
NvBool bSupportDcTsp;
/* Dynamic Boost AC support */
NvBool bEnableForAC;
@@ -2277,9 +2277,7 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
/* CPU TDP Limit to be set (milliwatts) */
NvU32 cpuTdpmw;
} NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
typedef NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
} NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
/* Define the filter types */
#define CONTROLLER_FILTER_TYPE_EMWA 0U
@@ -2305,9 +2303,16 @@ typedef NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS NV0000_CTRL_SYST
/*
* Defines for get supported sub functions bit fields
*/
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED 0:0
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_YES 1
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_SUPPORTED_IS_SUPPORTED_NO 0
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED 8:8
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED_YES 1
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_GET_DC_SYSTEM_POWER_LIMITS_IS_SUPPORTED_NO 0
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED 9:9
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED_YES 1
#define NVPCF0100_CTRL_CONFIG_DSM_FUNC_CPU_TDP_LIMIT_CONTROL_IS_SUPPORTED_NO 0
/*!
* Config DSM 2x version specific defines

136
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -1328,11 +1328,12 @@ typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS {
#define NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID (0x60U)
typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 laneCount;
NvU32 linkBW;
NvU32 dp2LinkBW;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 laneCount;
NvU32 linkBW;
NvU32 dp2LinkBW;
NvBool bFECEnabled;
} NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS;
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT 3:0
@@ -1682,8 +1683,6 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
* Specified the DP versions supported by the GPU
* UHBRSupportedByGpu
* Bitmask to specify the UHBR link rates supported by the GPU.
* minPClkForCompressed
* Pixel clock below which we should prefer non-DSC mode.
* bIsMultistreamSupported
* Returns NV_TRUE if MST is supported by the GPU else NV_FALSE
* bIsSCEnabled
@@ -1705,6 +1704,8 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
* Returns NV_TRUE if GPU uses the new RG flush design
* bSupportDPDownSpread
* Returns NV_TRUE if GPU support downspread.
* bAvoidHBR3
* Returns if we need to avoid HBR3 as much as possible
*
* DSC caps
*
@@ -1725,7 +1726,6 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
NvU32 maxLinkRate;
NvU32 dpVersionsSupported;
NvU32 UHBRSupportedByGpu;
NvU32 minPClkForCompressed;
NvBool bIsMultistreamSupported;
NvBool bIsSCEnabled;
NvBool bHasIncreasedWatermarkLimits;
@@ -1736,6 +1736,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
NvBool bOverrideLinkBw;
NvBool bUseRgFlushSequence;
NvBool bSupportDPDownSpread;
NvBool bAvoidHBR3;
NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC;
} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS;
@@ -2041,6 +2042,27 @@ typedef struct NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS {
NvBool enable;
} NV0073_CTRL_CMD_DP_SET_TRIGGER_ALL_PARAMS;
/* NV0073_CTRL_CMD_SPECIFIC_RETRIEVE_DP_RING_BUFFER
*
* These commands retrieves buffer from RM for
* DP Library to dump logs
*
*
* Possible status values returned include:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER (0x731371U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS_MESSAGE_ID (0x71U)
typedef struct NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS {
NV_DECLARE_ALIGNED(NvU8 *pDpRingBuffer, 8);
NvU8 ringBufferType;
NvU32 numRecords;
} NV0073_CTRL_CMD_DP_RETRIEVE_DP_RING_BUFFER_PARAMS;
/*
@@ -3377,6 +3399,44 @@ typedef struct NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS {
#define NV0073_CTRL_CMD_DP2X_GET_LEVEL_INFO_TABLE_DATA (0x73138aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR
*
* This command is used to apply the WAR based on EDID.
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the digital display for which the
* data should be returned. The display ID must a digital display.
* If more than one displayId bit is set or the displayId is not a DP,
* this call will return NV_ERR_INVALID_ARGUMENT.
* bEnable
* This parameter will be used by RM to set the PDB property. Later that PDB
* property will be used for applying the WAR
* head
* This parameter specify for which head RM need to apply the WAR
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS_MESSAGE_ID (0x8BU)
typedef struct NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 bEnable;
NvU32 head;
} NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS;
#define NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR (0x73138bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS_MESSAGE_ID" */
/*
@@ -3444,7 +3504,7 @@ typedef struct NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS {
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP (0x73138bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP (0x73138cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID" */
typedef struct NV0073_CTRL_DP_IMP_LINK_CONFIGURATION {
NvU32 linkRate10M;
@@ -3453,6 +3513,7 @@ typedef struct NV0073_CTRL_DP_IMP_LINK_CONFIGURATION {
NvBool bDp2xChannelCoding;
NvBool bMultiStreamTopology;
NvBool bFECEnabled;
NvBool bDisableEffBppSST8b10b;
} NV0073_CTRL_DP_IMP_LINK_CONFIGURATION;
typedef struct NV0073_CTRL_DP_IMP_DSC_PARAMETERS {
@@ -3489,7 +3550,7 @@ typedef struct NV0073_CTRL_DP_IMP_WATERMARK {
NvBool bIsModePossible;
} NV0073_CTRL_DP_IMP_WATERMARK;
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID (0x8BU)
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID (0x8CU)
typedef struct NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS {
NvU32 subDeviceInstance;
@@ -3501,4 +3562,59 @@ typedef struct NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS {
NV0073_CTRL_DP_IMP_WATERMARK watermark;
} NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS;
/*
* NV0073_CTRL_CMD_DP_GET_CABLEID_INFO_FROM_MACRO
*
* This command is used to read cable ID Information from USB-C Cable for
* DP configuration purposes.
*
* subDeviceInstance [in]
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
*
* displayId [in]
* This parameter specifies the ID of the DP display which owns
* the Main Link to be adjusted. The display ID must a DP display
* as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
* If more than one displayId bit is set or the displayId is not a DP,
* this call will return NV_ERR_INVALID_PARAMETER.
*
* cableIDInfo [out]
* This parameter reflects the result of the cable ID read from the cable
*
* Possible status values returned are:
* NV_ERR_INVALID_PARAMETER
* NV_ERR_NOT_SUPPORTED
* NV_OK
*/
#define NV0073_CTRL_CMD_DP_GET_CABLEID_INFO_FROM_MACRO (0x73138dU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS_MESSAGE_ID" */
typedef enum NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE {
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_UNKNOWN = 0,
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_PASSIVE = 1,
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_ACTIVE_RETIMER = 2,
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_ACTIVE_LIN_REDRIVER = 3,
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE_OPTICAL = 4,
} NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE;
typedef struct NV0073_CTRL_DP_USBC_CABLEID_INFO {
NvBool uhbr10_0_capable;
NvBool uhbr13_5_capable;
NvBool uhbr20_0_capable;
NV0073_CTRL_DP_USBC_CABLEID_CABLETYPE type;
NvBool vconn_source;
} NV0073_CTRL_DP_USBC_CABLEID_INFO;
#define NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS_MESSAGE_ID (0x8DU)
typedef struct NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NV0073_CTRL_DP_USBC_CABLEID_INFO cableIDInfo;
} NV0073_CTRL_DP_USBC_CABLEID_INFO_PARAMS;
/* _ctrl0073dp_h_ */

56
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h
View File

@@ -32,6 +32,25 @@
#include "ctrl/ctrl0073/ctrl0073base.h"
/*
* tilemask
* Tiles assocaited with calc tiemout head.
* frameActive
* New frame has started on this Head.
* histoReady
* Asserts when histogram data from all the "enabled" LTMs belonging to this head
* is ready.
* startFrameReady
* When histo_ready interrupt
* is received and HDMA is programmed and then RISCV asserts STARTFRAME_READY.
*/
typedef struct NV0073_LTM_HEAD_STATUS_PARAMS {
NvU8 tileMask;
NvBool frameActive;
NvBool histoReady;
NvBool startFrameReady;
} NV0073_LTM_HEAD_STATUS_PARAMS;
/* NV04_DISPLAY_COMMON event-related control commands and parameters */
/*
@@ -90,41 +109,4 @@ typedef struct NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001U)
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002U)
/*
* NV0073_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY
*
* hMemory
* This parameter specifies the handle of the memory object
* that identifies the memory address translation for this
* subdevice instance's notification(s). The beginning of the
* translation points to an array of notification data structures.
* The size of the translation must be at least large enough to hold the
* maximum number of notification data structures identified by
* the NV0073_MAX_NOTIFIERS value.
* Legal argument values must be instances of the following classes:
* NV01_NULL
* NV04_MEMORY
* When hMemory specifies the NV01_NULL_OBJECT value then any existing
* memory translation connection is cleared. There must not be any
* pending notifications when this command is issued.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0073_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x730303U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS {
NvU32 subDeviceInstance;
NvHandle hMemory;
} NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS;
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0U
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1U
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2U
/* _ctrl0073event_h_ */

34
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
View File

@@ -281,12 +281,10 @@ typedef struct NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS {
/* Faking Support commands */
/* some random value to enable/disable test code */
#define NV0073_FAKE_DEVICE_SUPPORT_ENABLE 0x11faU
#define NV0073_FAKE_DEVICE_SUPPORT_DISABLE 0x99ceU
#define NV0073_FAKE_DEVICE_SUPPORT_ATTACH_DEVICES 0x100U
#define NV0073_FAKE_DEVICE_SUPPORT_REMOVE_DEVICES 0x101U
#define NV0073_FAKE_DEVICE_SUPPORT_ENABLE 0x11faU
#define NV0073_FAKE_DEVICE_SUPPORT_DISABLE 0x99ceU
#define NV0073_FAKE_DEVICE_SUPPORT_ATTACH_DEVICES 0x100U
#define NV0073_FAKE_DEVICE_SUPPORT_REMOVE_DEVICES 0x101U
/*
* NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID
@@ -317,7 +315,7 @@ typedef struct NV0073_CTRL_CMD_SPECIFIC_FAKE_DEVICE_PARAMS {
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID (0x730211U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID (0x730211U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS_MESSAGE_ID (0x11U)
@@ -2082,6 +2080,26 @@ typedef NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS NV0073_CTRL_SPECIFIC_
typedef NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS;
#define NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM (0x7302b0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM (0x7302b0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_CMD_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP
*
* The command returns the offset of the disp registers for sending timestamp
* directly to RISCV, so that clients may map them directly and write to this
* register which will trigger interrupt in RISCV.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP (0x7302b1U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS_MESSAGE_ID (0xB1U)
typedef struct NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS {
NvU32 subDeviceInstance;
NvU32 dispRegisterBase;
} NV0073_CTRL_GET_REGISTER_OFFSET_FOR_ULMB_TIMESTAMP_PARAMS;
/* _ctrl0073specific_h_ */

198
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -1911,6 +1911,7 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_HUBCLK 0x0006
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_DISPCLK 0x0007
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_POSTRG_CLKS 0x0008
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_MSCG 0x0009
// Parameter/characteristics of Display ALPM
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_INVALID 0x0000
@@ -2031,6 +2032,66 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_GATE_TIME_US (0x0003)
/*!
* Property specifies current state of the specified clock
* i.e. Gated ot not Gated
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_STATUS (0x0004)
/*!
* @brief Parameter/characteristics of MSCG
*
* Following are the Parameter/characteristics for MSCG
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_INVALID (0x0000)
/*!
* Property specifies if DPS1 is supported
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_SUPPORT (0x0001)
/*!
* Property specifies if DPS2 is supported
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_SUPPORT (0x0002)
/*!
* Property specifies if MSCG is enabled
* (This property allows Get/SET operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_ENABLED (0x0003)
/*!
* Property specifies the time(in US) for which DPS1 was enabled
* in ACTIVE region
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_ACTIVE_TIME_US (0x0004)
/*!
* Property specifies the time(in US) for which DPS1 was enabled
* in VBLANK region
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_VBLANK_TIME_US (0x0005)
/*!
* Property specifies the time(in US) for which DPS2 was enabled
* in ACTIVE region
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_ACTIVE_TIME_US (0x0006)
/*!
* Property specifies the time(in US) for which DPS2 was enabled
* in VBLANK region
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_VBLANK_TIME_US (0x0007)
/*!
* @brief Structure to identify display low power feature
*
@@ -2203,6 +2264,143 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS {
NvBool bEnableDrr;
} NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_SET_DISPLAY_PERF_LIMIT
*
* This command sets lower and/or upper bounds for a display clock (dispclk or
* hubclk), or for the memory perf level. When this API is called, the system
* will immediately attempt to switch the clock or perf level to a value that
* meets the specified condition(s).
*
* If no lower limit is desired, the "min" input should be set to zero.
*
* If no upper limit is desired for a clock, the "max" input should be set to
* NV_U32_MAX.
*
* This API does not allow an upper limit to be specified for perf level.
*
* Any perf limit set through this API will remain in effect until it updated
* or cancelled by a subsequent call to this API. A perf limit may be
* cancelled by setting the "min" value to NV_U32_MIN (0) and the "max" value
* (for clocks) to NV_U32_MAX. Only one perf limit may be in effect for a
* given clientUsageId and type at any given time.
*
* At any given time, multiple perf limits (with different clientUsageIds) may
* be in effect for a given clock or perf level, and that clock or perf level
* will be set to a value that meets the requirements of all active perf
* limits. If there is a conflict between perf limits, the conflict will be
* resolved by the perf limit(s) with the higher priority.
*
* For example, suppose the API is called with the following parameters:
* clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS
* type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK
* data.clock.minFrequencyKHz = 800000
* data.clock.maxFrequencyKHz = 800000
* This will set dispclk to 800 MHz (or possibly a slightly higher frequency,
* if the clock dividers do not allow 800 MHz to be set exactly).
*
* Then suppose this call is made:
* clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE
* type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK
* data.clock.minFrequencyKHz = 1000000
* data.clock.maxFrequencyKHz = 0xFFFFFFFF
* After this call, dispclk will remain set to 800 MHz, because, although the
* min frequency was requested to be at least 1 GHz, this would conflict with
* the "maxFrequencyKHz = 800000" value set in the previous call, which is
* still in effect. The previous call takes priority because
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS has higher priority than
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE.
*
* Then suppose this call is made:
* clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS
* type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK
* data.clock.minFrequencyKHz = 0
* data.clock.maxFrequencyKHz = 0xFFFFFFFF
* This removes the NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS perf
* limit. At this point, dispclk will be set to 1 GHz, in accordance with the
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE perf limit,
* which is still in effect. (The remaining perf limit allows the clock to be
* higher than 1 GHz, but in practice, the clock will generally be set to the
* lowest frequency that meets the perf limit requirement, to save power. For
* perf level, perf monitors (which do not use the perf limit mechanism) may
* force a higher value in order to meet performance needs.)
*
* This API takes an array of perf limit structures, so multiple perf limits
* maybe set within the same call.
*
* This API is primarily intended for use on SOC products, where display is
* separate from the GPU. On dGPU products, this API may not be supported;
* instead, NV2080_CTRL_CMD_PERF_LIMITS_SET_STATUS_V2 may be used to set perf
* limits.
*
* subDeviceInstance (in)
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
*
* numLimits (in)
* This is the number of perf limits with lower and/or upper limits to
* apply.
*
* bWaitForCompletion (in)
* It is possible that a perf change or clock change may take some time to
* execute. If this flag is set, the API will wait for all of the changes
* to complete before returning. (However, it will not wait for completion
* of any operation that is blocked by a higher priority perf limit.)
*
* clientUsageId (in)
* This is a NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_xxx value
* indicating who the client is, and/or the purpose of the perf limit. It
* is used to establish priority between conflicting perf limits.
*
* whatIsToBeLimited (in)
* This is a NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_xxx value
* indicating which clock, or memory perf level, is to have limits applied.
*
* minLevelOrFreqKHz (in)
* maxLevelOrFreqKHz (in)
* If type is
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_PERF_LEVEL, then
* minLevelOrFreqKHz specifies the zero-based index of the minimum perf
* level to allow. maxLevelOrFreqKHz is not used.
*
* If type specifies a clock
* (NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK or
* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_HUBCLK), then
* minLevelOrFreqKHz and maxLevelOrFreqKHz specify the lower and upper
* limits (respectively) for the specified clock's frequency.
*/
#define NV0073_CTRL_CMD_SYSTEM_SET_DISPLAY_PERF_LIMIT (0x73015aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS_MESSAGE_ID" */
/* valid clientUsageId values */
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE (0U)
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MCLK_SWITCH (1U)
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS (2U)
/* valid type values */
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_PERF_LEVEL (0U)
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_DISPCLK (1U)
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_HUBCLK (2U)
/* Define a structure for a single perf limit */
typedef struct NV0073_CTRL_SYSTEM_DISPLAY_PERF_LIMIT {
NvU8 clientUsageId;
NvU8 whatIsToBeLimited;
NvU32 minLevelOrFreqKHz;
NvU32 maxLevelOrFreqKHz;
} NV0073_CTRL_SYSTEM_DISPLAY_PERF_LIMIT;
#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS_MESSAGE_ID (0x5AU)
typedef struct NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS {
NvU32 subDeviceInstance;
NvU32 numLimits;
NvBool bWaitForCompletion;
NV_DECLARE_ALIGNED(NvP64 limits, 8);
} NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO
*

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h
View File

@@ -226,7 +226,7 @@ typedef struct NV0080_CTRL_DMA_FILL_PTE_MEM_PARAMS {
NvU32 pteMemPfn;
NvU32 pageSize;
NvU32 startPageIndex;
NvU32 flags;
NV_DECLARE_ALIGNED(NvU64 flags, 8);
NvHandle hSrcVASpace;
NvHandle hTgtVASpace;
NvU32 peerId;

8
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
View File

@@ -596,6 +596,9 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS {
* vGPU heterogeneous mode on a GPU can only be set when the command
* is running in a vGPU host device.
*
* gpuInstanceId
* GPU Instance ID or Swizz ID
*
* bHeterogeneousMode
* This parameter set the vGPU heterogeneous mode of the device.
* Possible values are:
@@ -617,6 +620,7 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS {
typedef struct NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
NvBool bHeterogeneousMode;
NvU32 gpuInstanceId;
} NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS;
/**
@@ -625,6 +629,9 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
* This command returns a value indicating vGPU heterogeneous mode of
* the GPU.
*
* gpuInstanceId
* GPU Instance ID or Swizz ID
*
* bHeterogeneousMode
* This parameter returns the vGPU heterogeneous mode of the device.
* Possible values are:
@@ -643,6 +650,7 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
typedef struct NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS {
NvBool bHeterogeneousMode;
NvU32 gpuInstanceId;
} NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS;
/* _ctrl0080gpu_h_ */

20
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -114,4 +114,22 @@ typedef struct NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PAR
NvHandle clientHandles[NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS];
} NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS;
/*!
* NV0080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED
*
* Tell Physical RM whether any ZBC-kind surfaces are allocated.
* If PF and all VFs report false, ZBC table can be flushed by Physical RM.
*
* bZbcReferenced [IN]
* NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM
*
*/
#define NV0080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x80200a) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x0AU)
typedef struct NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS {
NvBool bZbcSurfacesExist;
} NV0080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS;
/* ctrl0080internal_h */

1
src/common/sdk/nvidia/inc/ctrl/ctrl2080.h
View File

@@ -87,3 +87,4 @@
#include "ctrl2080/ctrl2080unix.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

142
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
View File

@@ -1348,6 +1348,8 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
* NV_TRUE if the C2C links are present and the links are up.
* The below remaining fields are valid only if return value is
* NV_OK and bIsLinkUp is NV_TRUE.
* bLinkInHS[OUT]
* NV_TRUE if the C2C links are in high speed mode.
* nrLinks[OUT]
* Total number of C2C links that are up.
* maxNrLinks[OUT]
@@ -1382,6 +1384,7 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS {
NvBool bIsLinkUp;
NvBool bLinkInHS;
NvU32 nrLinks;
NvU32 maxNrLinks;
NvU32 linkMask;
@@ -1393,6 +1396,8 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS {
#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU 1
#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU 2
/*
* NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS
*
@@ -1417,7 +1422,44 @@ typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS {
NvBool bDisable;
} NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO
*
* This command returns the C2C error info for a C2C links.
*
* errCnts[OUT]
* Array of structure that contains the error counts for
* number of times one of C2C fatal error interrupt has happened.
* The array size should be NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES
* * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE.
*
* nrCrcErrIntr[OUT]
* Number of times CRC error interrupt triggered.
* nrReplayErrIntr[OUT]
* Number of times REPLAY error interrupt triggered.
* nrReplayB2bErrIntr[OUT]
* Number of times REPLAY_B2B error interrupt triggered.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES 2
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE 7
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU)
typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS {
struct {
NvU32 nrCrcErrIntr;
NvU32 nrReplayErrIntr;
NvU32 nrReplayB2bErrIntr;
} errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE];
} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING
@@ -1552,3 +1594,103 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS {
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO (0x00000000)
/*
* NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS
*
* This command returns C2C low power statistics.
* Units for residency and latency are in microsceconds.
* c2cStateSupportMask[OUT]
Support Mask of supplrted C2C State. CL0 will always be supported (FULL_POWER)
* cl3EntryCount[OUT]
* Count of the number of times CL3 state has been entered.
* cl3ResidentTimeUs[OUT]
* Total/Average resident time in CL3 state.
* cl3AvgEntryLatencyUs[OUT]
* Average entry latency for CL3 state.
* cl3AvgExitLatencyUs[OUT]
* Average exit latency for CL3 state.
* cl3PstateSupportMask[OUT]
Pstate Support Mask for CL3 state
* cl4EntryCount[OUT]
* Count of the number of times CL4 state has been entered.
* cl4ResidentTimeUs[OUT]
* Total/Average resident time in CL4 state.
* cl4AvgEntryLatencyUs[OUT]
* Average entry latency for CL4 state.
* cl4AvgExitLatencyUs[OUT]
* Average exit latency for CL4 state.
* cl4PstateSupportMask[OUT]
Pstate Support Mask for CL4 state
* localPowerState[OUT]
* Power state of the local end of the C2C link.
* Valid values are :
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER - Full power state
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 - Low power state
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 - Low power state
* remotePowerState[OUT]
* Power state of the remote end of the C2C link.
* Valid values are :
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER - Full power state
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 - Low power state
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 - Low power state
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
*
* Please also review the information below for additional information on
* select fields:
*
* cl3EntryCount/cl4EntryCount[OUT]
* These may not represent current exact count, as low power transitions could have
* occured after reading the counter register.
*/
#define NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS (0x20801831) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS_MESSAGE_ID (0x31U)
typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS {
NvU32 c2cStateSupportMask;
NvBool bCl3Support;
NvU32 cl3EntryCount;
NvU32 cl3ExitCount;
NvU32 cl3ResidentTimeUs;
NvU32 cl3AvgEntryLatencyUs;
NvU32 cl3AvgExitLatencyUs;
NvU32 cl3PstateSupportMask;
NvU32 cl3DisallowReasonMask;
NvBool bCl4Support;
NvU32 cl4EntryCount;
NvU32 cl4ExitCount;
NvU32 cl4ResidentTimeUs;
NvU32 cl4AvgEntryLatencyUs;
NvU32 cl4AvgExitLatencyUs;
NvU32 cl4PstateSupportMask;
NvU32 cl4DisallowReasonMask;
NvU32 c2cLpwrStateAllowedMask;
NvU32 localPowerState;
NvU32 remotePowerState;
} NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS;
#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER 0x0
#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 0x1
#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 0x2
/*
* NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE
*
* This command sets the allow vote for C2C Lpwr States.
* c2cLpwrStateId[IN]
* C2C LowPower State Id : NV2080_CTRL_LPWR_C2C_STATE_ID_CLx
* bAllowed[in]
* State Allowed/disallowed flag
*/
#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE (0x20801832) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS_MESSAGE_ID (0x32U)
typedef struct NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS {
NvU32 c2cLpwrStateId;
NvBool bAllowed;
} NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS;

1
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h
View File

@@ -30,3 +30,4 @@
// Source file: ctrl/ctrl2080/ctrl2080fan.finn
//

117
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
View File

@@ -1811,9 +1811,8 @@ typedef struct NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS {
*
* Get memory alignment. Replacement for NVOS32_FUNCTION_GET_MEM_ALIGNMENT
*/
#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT (0x20801342U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT (0x20801342U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS (4U)
#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID (0x42U)
typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS {
@@ -1827,8 +1826,6 @@ typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS {
NvU32 alignPitch;
NvU32 alignPad;
NvU32 alignMask;
NvU32 alignOutputFlags[NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS];
NvU32 alignBank[NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS];
NvU32 alignKind;
NvU32 alignAdjust; // Output -- If non-zero the amount we need to adjust the offset
NvU32 alignAttr2;
@@ -2039,6 +2036,24 @@ typedef struct NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS {
NvU32 ropEnMask;
} NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS;
/*!
* Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_SYS_MASK.
*/
typedef struct NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS {
/*!
* [in]: swizzId
* PartitionID associated with a created smc partition. Currently used only for a
* device monitoring client to get the physical values of the sys. The client needs to pass
* 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId.
* RM will consider this request similar to a legacy case.
*/
NvU32 swizzId;
/*!
* [out]: physical/local sys mask.
*/
NV_DECLARE_ALIGNED(NvU64 sysEnMask, 8);
} NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS;
/*!
* Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK.
*/
@@ -2233,6 +2248,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS {
#define NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK 0xFU
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK 0x10U
#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK 0x11U
#define NV2080_CTRL_FB_FS_INFO_SYS_MASK 0x12U
typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
NvU16 queryType;
@@ -2257,6 +2273,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS logicalLtc, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS dmLogicalLtc, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS sysl2Lts, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS sys, 8);
} queryParams;
} NV2080_CTRL_FB_FS_INFO_QUERY;
@@ -2748,61 +2765,6 @@ typedef struct NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS {
NvU32 newConfiguration;
} NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_STATUS
*
* This control command is used by clients to get the FB availabilty status,
* i.e whether the GPU Memory is ready for use or not for MIG and non-MIG cases
*
* fbStatus[OUT]
* This parameter returns the various values of FB availability status.
* Valid values include:
* NV2080_CTRL_FB_STATUS_FAILED
* On Non Self hosted (Non NUMA) systems - this status is not expected since
* FB memory is available as part of GPU initialization itself.
* On Direct connected Self hosted systems - this status is not expected since
* FB memory is available as part of GPU initialization itself.
* On Nvswitch connected Self hosted systems - this status indicates that either
* the memory onlining has failed or fabric probe response has failed.
* GPU reset maybe required in such a case.
* NV2080_CTRL_FB_STATUS_READY
* On Non Self hosted systems - this status is always returned as memory is ready
* after GPU initialization is complete.
* On Self hosted systems - this status indicates that the FB memory has been onlined
* successfully and is available for client/user allocations.
* NV2080_CTRL_FB_STATUS_PENDING
* On Non Self hosted systems - this status is not expected
* On Direct connected Self hosted systems - this status is not expected since
* FB memory is available as part of GPU initialization itself.
* On Nvswitch connected Self hosted systems - This status indicates memory is yet to
* be onlined or is in progress since we are either still waiting for a fabric
* probe response or a fabric probe request hasn't been sent yet.
* NV2080_CTRL_FB_STATUS_NOT_APPLICABLE
* This status indicates that this is a system with no FB memory.
*
*
* @returns Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
* NV_ERR_NOT_READY
* NV_ERR_INVALID_LOCK_STATE
*/
#define NV2080_CTRL_CMD_FB_GET_STATUS (0x20801357U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID" */
// NUMA Memory Onlining Status
#define NV2080_CTRL_FB_STATUS_FAILED (0x00000000U)
#define NV2080_CTRL_FB_STATUS_READY (0x00000001U)
#define NV2080_CTRL_FB_STATUS_PENDING (0x00000002U)
#define NV2080_CTRL_FB_STATUS_NOT_APPLICABLE (0x00000003U)
#define NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID (0x57U)
typedef struct NV2080_CTRL_FB_GET_STATUS_PARAMS {
NvU32 fbStatus;
} NV2080_CTRL_FB_GET_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT
*
@@ -2818,12 +2780,12 @@ typedef struct NV2080_CTRL_FB_GET_STATUS_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT (0x20801358U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT (0x20801357U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED (0x00000000U)
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED (0x00000001U)
#define NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID (0x58U)
#define NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID (0x57U)
typedef struct NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS {
NvU32 isSupported;
@@ -2842,15 +2804,44 @@ typedef struct NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS (0x20801359U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS (0x20801358U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED (0x00000000U)
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED (0x00000001U)
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID (0x59U)
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID (0x58U)
typedef struct NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS {
NvU32 currentStatus;
} NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_MEMORY_BOOT_TRAINING_FLAGS
*
* This command returns the memory boot training flags from VBIOS table.
*
* flagCollectSchmooData
* flagWrTrHybridVrefEn
* flagWrTrHybridNonVrefEn
* flagRdTrHybridVrefEn
* flagRdTrHybridNonVrefEn
* skipBootTraining
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_GET_MEMORY_BOOT_TRAINING_FLAGS (0x20801359U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS_MESSAGE_ID (0x59U)
typedef struct NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS {
NvBool flagCollectSchmooData;
NvBool flagWrTrHybridVrefEn;
NvBool flagWrTrHybridNonVrefEn;
NvBool flagRdTrHybridVrefEn;
NvBool flagRdTrHybridNonVrefEn;
NvBool skipBootTraining;
} NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS;
/* _ctrl2080fb_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
View File

@@ -245,8 +245,7 @@ typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS {
* @{
*/
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT 0U
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON 1U
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT 2U
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT 1U
/*!@}*/
/*!

90
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -111,8 +111,9 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU)
#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED (0x00000041U)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000042U)
#define NV2080_CTRL_GPU_INFO_INDEX_GROUP_ID 30:24
#define NV2080_CTRL_GPU_INFO_INDEX_RESERVED 31:31
@@ -223,6 +224,10 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES (0x00000001U)
/* valid localization supported values */
#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_YES (0x00000001U)
/*
* NV2080_CTRL_CMD_GPU_GET_INFO
*
@@ -755,6 +760,8 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS {
NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
} NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST
*
@@ -2634,7 +2641,14 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE 8U
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 40U
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 90U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA 29:28
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_DEFAULT 0U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_DISABLE 1U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_ENABLE 2U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U
@@ -3131,6 +3145,7 @@ typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS {
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB 0x08000000U
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB 0x10000000U
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB 0x20000000U
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_1024MB 0x40000000U
@@ -4586,4 +4601,75 @@ typedef struct NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS {
NvU32 tpcReconfigMask;
} NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_RPC_GSP_TEST
*
* This command checks a variable sized RPC for a known pattern, then
* fills the data field with another pattern. It also records the timestamp
* before and after the RPC is sent to GSP.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_GPU_RPC_GSP_TEST (0x208001e8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS_MESSAGE_ID (0xe8U)
typedef struct NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS {
NvU8 test;
NvU32 dataSize;
NV_DECLARE_ALIGNED(NvU64 startTimestamp, 8);
NV_DECLARE_ALIGNED(NvU64 stopTimestamp, 8);
NV_DECLARE_ALIGNED(NvP64 data, 8);
} NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS;
#define NV2080_CTRL_GPU_RPC_GSP_TEST_SERIALIZED_INTEGRITY 0x1
#define NV2080_CTRL_GPU_RPC_GSP_TEST_UNSERIALIZED 0x2
/*
* NV2080_CTRL_CMD_GPU_RPC_GSP_QUERY_SIZES
*
* This command returns information necessary for GSP RPC integrity tests
*
* Possible status values returned are:
* NV_OK
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_GPU_RPC_GSP_QUERY_SIZES (0x208001e9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS_MESSAGE_ID (0xe9U)
typedef struct NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS {
NvU32 maxRpcSize;
NvU32 finnRmapiSize;
NvU32 rpcGspControlSize;
NvU32 rpcMessageHeaderSize;
NV_DECLARE_ALIGNED(NvU64 timestampFreq, 8);
} NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS;
/*
* RUSD features.
* Each feature definition equates to a bit in the supportedFeatures bitmask.
*/
#define RUSD_FEATURE_NON_POLLING 0x1
#define RUSD_FEATURE_POLLING 0x2
/*
* NV2080_CTRL_CMD_GPU_RUSD_GET_SUPPORTED_FEATURES
*
* @brief Returns bitmask of supported RUSD features.
*
* @param[out] supportedFeatures Bitmask of supported RUSD features
*
* @return NV_OK
*/
#define NV2080_CTRL_CMD_RUSD_GET_SUPPORTED_FEATURES (0x208081eaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS_MESSAGE_ID (0xeaU)
typedef struct NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS {
NvU32 supportedFeatures;
} NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS;
/* _ctrl2080gpu_h_ */

62
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -317,7 +317,19 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01 (0x00000A01U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_03 (0x00000A03U)
/*
* TODO Bug 4333440 is introducing versions 12_*.
* Eventually once 12_* is tested and validated, another
* follow up change will be needed to remove 10_04 support.
*/
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_04 (0x00000A04U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_12_00 (0x00000C00U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_12_01 (0x00000C01U)
@@ -340,6 +352,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1 (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_3 (NV2080_CTRL_GR_INFO_SM_VERSION_10_03)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_4 (NV2080_CTRL_GR_INFO_SM_VERSION_10_04)
@@ -1172,6 +1187,9 @@ typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*
* ugpuId
* Specifies the uGPU ID on Hopper+.
*
*/
#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER (0x2080121bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */
@@ -1189,6 +1207,7 @@ typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS {
NvU16 globalTpcId;
NvU16 virtualGpcId;
NvU16 migratableTpcId;
NvU16 ugpuId;
} globalSmId[NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT];
NvU16 numSm;
@@ -1655,6 +1674,47 @@ typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS {
NvU8 imla4;
} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE (0xFFU)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FMLA16 (0x0U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DP (0x1U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FMLA32 (0x2U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FFMA (0x3U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA0 (0x4U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA1 (0x5U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA2 (0x6U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA3 (0x7U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA4 (0x8U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FP16 (0x9U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FP32 (0xAU)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DFMA (0xBU)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DMLA (0xCU)
/*
* NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2
*
* This command provides an interface to retrieve the speed select values of
* various instruction types.
*
* smIssueRateModifierListSize
* This field specifies the number of entries on the caller's
* smIssueRateModifierList.
* When caller passes smIssueRateModifierListSize = 0, all fuse
* values are returned.
* smIssueRateModifierList
* This field specifies a pointer in the caller's address space
* to the buffer into which the speed select values are to be returned.
*/
#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2 (0x2080123cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID" */
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2;
#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x3CU)
typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS {
NvU32 smIssueRateModifierListSize;
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierList[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE];
} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
/*
* NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID
*

86
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -229,6 +229,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER {
NvU16 globalTpcId;
NvU16 virtualGpcId;
NvU16 migratableTpcId;
NvU16 ugpuId;
} globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM];
NvU16 numSm;
@@ -1003,7 +1004,7 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS {
* validGfxCTSIdMask [OUT]
* # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile
*/
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 60
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 90
@@ -1671,17 +1672,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS
*/
#define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */
/* !
* This command disables cuda limit activation at teardown of the client.
*/
#define NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */
/*
* This command is cleaning up OPTP when a client is found to have
* been terminated unexpectedly.
*/
#define NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR (0x20800a7c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7C" */
/* !
* This command is used to get the current AUX power state of the sub-device.
*/
@@ -2914,6 +2904,8 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS {
NvU32 bRasterSyncGpioDirection;
} NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_FBSR_INIT
*
@@ -3438,7 +3430,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_PRH_DEPENDENCY_CHECK
* NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK
*
* This command checks if all the dependant modules to PRH have been initialized.
*
@@ -3447,7 +3439,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_PRH_DEPENDENCY_CHECK (0x20800a18) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x18" */
#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */
/*
* NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS
@@ -3466,7 +3458,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU)
@@ -4004,8 +3996,9 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_P
/*
* NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA
*
* @brief Initialize RM User Shared Data memory mapping on physical RM
* @brief Initialize/Destroy RM User Shared Data memory mapping on physical RM
*
* @param[in] bInit If this is an init or a destroy request
* @param[in] physAddr Physical address of memdesc to link physical to kernel
* 0 to de-initialize
*
@@ -4015,6 +4008,7 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_P
#define NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID (0xFEU)
typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS {
NvBool bInit;
NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
} NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA (0x20800afe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID" */
@@ -4680,7 +4674,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS {
NvU32 peerId;
NvU32 peerLinkMask;
NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8);
NvBool bEgmPeer;
NvBool bNvswitchConn;
} NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS;
@@ -4796,7 +4790,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS {
NvU32 flags;
NvBool bSysmem;
NvU32 peerLinkMask;
NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8);
} NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY (0x20800a64U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID" */
@@ -4829,7 +4823,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS {
NvU32 gpuInst;
NvU32 peerLinkMask;
NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8);
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK (0x20800a7dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID" */
@@ -4962,6 +4956,8 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES {
* Mask of links discovered from all the IOCTRLs
* [Out] ipVerNvlink
* IP revision of the NVLink HW
* [Out] maxSupportedLinks
* Maximum number of links supported for a given arch
* [Out] linkInfo
* Per link information
*/
@@ -4974,6 +4970,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS {
NvU32 ioctrlSize;
NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8);
NvU32 ipVerNvlink;
NvU32 maxSupportedLinks;
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES linkInfo[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS;
@@ -5264,6 +5261,28 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20800aabU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO
*
* Send CMC gsplite the address and size of log buffer allocated on sysmem
*
* [In] PublicId
* ID of the gsplite engine
* [In] logBufferSize
* Size of the log buffer allocated on sysmem
* [In] logBufferAddr
* Start address of the log buffer
*/
#define NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS {
NvU32 PublicId;
NV_DECLARE_ALIGNED(NvU64 logBufferSize, 8);
NV_DECLARE_ALIGNED(NvU64 logBufferAddr, 8);
} NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO (0x20800a89U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS
@@ -5271,6 +5290,31 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
* Request from CPU-RM to proccess supressed errors during boot on GSP
* This command accepts no parameters.
*/
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS (0x20800b01U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | 0x1" */
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS (0x20800b01U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | 0x1" */
/*!
* @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2
*/
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2 {
NvU32 smIssueRateModifierListSize;
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierList[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE];
} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x02U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierV2[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2 (0x20800b03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x03U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
/* ctrl2080internal_h */

8
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h
View File

@@ -71,7 +71,6 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
/* valid architecture values */
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X (0xE0000023)
@@ -133,17 +132,22 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB110 (0x00000003)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB112 (0x00000004)
/* valid ARCHITECTURE_GB20x implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 (0x00000003)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB204 (0x00000004)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 (0x00000005)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 (0x00000006)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 (0x00000007)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20B (0x0000000B)
/* Valid Chip sub revisions */
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
View File

@@ -306,7 +306,8 @@ typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4
#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5
#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6
#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7
#define NV2080_CTRL_NOCAT_TDR_TYPE_GPU_RC_RESET 7
#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 8
typedef struct NV2080CtrlNocatJournalDataTdrReason {
NvU32 flags;

71
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -2574,11 +2574,17 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvBool test_mode;
NvBool plr_vld;
NvU8 plane_ind;
NvU8 port_type;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvBool plr_reject_mode_vld;
NvBool plr_margin_th_override_to_default;
NvU8 plr_reject_mode;
NvU8 tx_crc_plr;
NvU8 plr_margin_th;
NvU8 fec_override_admin_10g_40g;
NvU8 fec_override_admin_25g;
NvU8 fec_override_admin_50g;
@@ -3288,7 +3294,8 @@ typedef enum NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY {
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL = 18,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL = 19,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL = 20,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = 21,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_FATAL = 21,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = 22,
} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY;
#define NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID (0x89U)
@@ -3298,6 +3305,51 @@ typedef struct NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS {
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY severity;
} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS;
/*
* NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY
*
* This command is used to update the NVLE topology in GSP RM
*
* [in] localGpuAlid
* ALID of local GPU in P2P object
* [in] localGpuClid
* CLID of local GPU in P2P object
* [in] remoteGpuAlid
* ALID of remote GPU in P2P object
* [in] remoteGpuClid
* CLID of remote GPU in P2P object
*/
#define NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY (0x2080308cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS_MESSAGE_ID (0x8cU)
typedef struct NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS {
NvU32 localGpuAlid;
NvU32 localGpuClid;
NvU32 remoteGpuAlid;
NvU32 remoteGpuClid;
} NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS;
/*
* NV2080_CTRL_NVLINK_GET_NVLE_LIDS
*
* This command is used to get the alid and clid of a GPU from the remap table.
*
* [in] probeClid
* CLID from probe response
* [out] clid
* CLID of GPU from remap table
* [out] alid
* ALID of gpu
*/
#define NV2080_CTRL_NVLINK_GET_NVLE_LIDS (0x2080308dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS_MESSAGE_ID (0x8dU)
typedef struct NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS {
NvU32 probeClid;
NvU32 clid;
NvU32 alid;
} NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY
*
@@ -3353,6 +3405,23 @@ typedef struct NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS {
NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_GET_NVLE_ENCRYPT_EN_INFO
*
* This command is used to get the ENCRYPT_EN register info
*
* [out] bEncyptEnSet
* Boolean that shows if ENCRYPT_EN is enabled or not.
*/
#define NV2080_CTRL_CMD_NVLINK_GET_NVLE_ENCRYPT_EN_INFO (0x2080308bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS_MESSAGE_ID (0x8bU)
typedef struct NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS {
NvBool bEncryptEnSet;
} NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS;
/* _ctrl2080nvlink_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

387
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h
View File

@@ -23,8 +23,395 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080thermal.finn
//
/*
* Thermal System rmcontrol api versioning
*/
#define THERMAL_SYSTEM_API_VER 1U
#define THERMAL_SYSTEM_API_REV 0U
/*
* NV2080_CTRL_THERMAL_SYSTEM constants
*
*/
/*
* NV2080_CTRL_THERMAL_SYSTEM_TARGET
*
* Targets (ie the things the thermal system can observe). Target mask
* have to be in sync with corresponding element of NVAPI_THERMAL_TARGET
* enum, until there is a translation layer between these two.
*
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE
* There is no target.
*
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU
* The GPU is the target.
*
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY
* The memory is the target.
*
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY
* The power supply is the target.
*
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD
* The board (PCB) is the target.
*/
/* NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN
* The target is unknown.
*/
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE (0x00000000U)
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU (0x00000001U)
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY (0x00000002U)
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY (0x00000004U)
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD (0x00000008U)
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN (0xFFFFFFFFU)
/*
* executeFlags values
*/
#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_DEFAULT (0x00000000U)
#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_IGNORE_FAIL (0x00000001U)
/*
* NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2
*
* This command will execute a list of thermal system instructions:
*
* clientAPIVersion
* This field must be set by the client to THERMAL_SYSTEM_API_VER,
* which allows the driver to determine api compatibility.
*
* clientAPIRevision
* This field must be set by the client to THERMAL_SYSTEM_API_REV,
* which allows the driver to determine api compatibility.
*
* clientInstructionSizeOf
* This field must be set by the client to
* sizeof(NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION), which allows the
* driver to determine api compatibility.
*
* executeFlags
* This field is set by the client to control instruction execution.
* NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_DEFAULT
* Execute instructions normally. The first instruction
* failure will cause execution to stop.
* NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_IGNORE_FAIL
* Execute all instructions, ignoring individual instruction failures.
*
* successfulInstructions
* This field is set by the driver and is the number of instructions
* that returned NV_OK on execution. If this field
* matches instructionListSize, all instructions executed successfully.
*
* instructionListSize
* This field is set by the client to the number of instructions in
* instruction list.
*
* instructionList
* This field is set an array of thermal system instructions
* (NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION) to execute, filled in by the
* client.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2 (0x20800513U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_THERMAL_INTERFACE_ID << 8) | NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2_PHYSICAL (0x20808513U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_THERMAL_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO instructions...
*
*/
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE instruction
*
* Get the number of available targets.
*
* availableTargets
* Returns the number of available targets. Targets are
* identified by an index, starting with 0.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPCODE (0x00000100U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS {
NvU32 availableTargets;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE instruction
*
* Get a target's type.
*
* targetIndex
* Set by the client to the desired target index.
*
* type
* Returns a target's type.
* Possible values returned are:
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPCODE (0x00000101U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS {
NvU32 targetIndex;
NvU32 type;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE instruction
*
* Get a providers's type.
*
* providerIndex
* Set by the client to the desired provider index.
*
* type
* Returns a provider's type.
*/
/*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPCODE (0x00000301U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS {
NvU32 providerIndex;
NvU32 type;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE instruction
*
* Get the number of available sensors.
*
* availableSensors
* Returns the number of available sensors. Sensors are
* identified by an index, starting with 0.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPCODE (0x00000500U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS {
NvU32 availableSensors;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER instruction
*
* Get a sensor's provider index.
*
* sensorIndex
* Set by the client to the desired sensor index.
*
* providerIndex
* Returns a sensor's provider index.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPCODE (0x00000510U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS {
NvU32 sensorIndex;
NvU32 providerIndex;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS;
/*!
* Union of mode-specific arguments.
*/
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING instruction
*
* Get a sensor's current reading.
*
* sensorIndex
* Set by the client to the desired sensor index.
*
* value
* Returns a sensor's current reading.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPCODE (0x00001500U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS {
NvU32 sensorIndex;
NvS32 value;
} NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET instruction
*
* Get a sensor's target index.
*
* sensorIndex
* Set by the client to the desired sensor index.
*
* targetIndex
* Returns a sensor's target index.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPCODE (0x00000520U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS {
NvU32 sensorIndex;
NvU32 targetIndex;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE instruction
*
* Get a sensor's readings range (ie min, max).
*
* sensorIndex
* Set by the client to the desired sensor index.
*
* minimum
* Returns a sensor's range minimum.
*
* maximum
* Returns a sensor's range maximum.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPCODE (0x00000540U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS {
NvU32 sensorIndex;
NvS32 minimum;
NvS32 maximum;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS;
/*
* Thermal System instruction operand
*/
typedef union NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS {
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS getInfoTargetsAvailable;
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS getInfoTargetType;
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS getInfoProviderType;
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS getInfoSensorsAvailable;
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS getInfoSensorProvider;
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS getInfoSensorTarget;
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS getInfoSensorReadingRange;
NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS getStatusSensorReading;
NvU32 space[8];
} NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION
*
* All thermal system instructions have the following layout:
*
* result
* This field is set by the driver, and is the result of the
* instruction's execution. This value is only valid if the
* executed field is not 0 upon return.
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*
* executed
* This field is set by the driver, and
* indicates if the instruction was executed.
* Possible status values returned are:
* 0: Not executed
* 1: Executed
*
* opcode
* This field is set by the client to the desired instruction opcode.
* Possible values are:
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPCODE
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPCODE
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPCODE
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPCODE
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPCODE
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPCODE
* NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPCODE
*/
/*
* operands
* This field is actually a union of all of the available operands.
* The interpretation of this field is opcode context dependent.
* Possible values are:
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS
* NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS
*/
typedef struct NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION {
NvU32 result;
NvU32 executed;
NvU32 opcode;
NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS operands;
} NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION;
#define NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_MAX_COUNT 0x20U
#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS {
NvU32 clientAPIVersion;
NvU32 clientAPIRevision;
NvU32 clientInstructionSizeOf;
NvU32 executeFlags;
NvU32 successfulInstructions;
NvU32 instructionListSize;
NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION instructionList[NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_MAX_COUNT];
} NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS;
/* _ctrl2080thermal_h_ */

25
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -468,6 +468,9 @@ typedef struct NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS {
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE (0x2080400e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0xEU)
@@ -476,4 +479,24 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS
NvBool bHeterogeneousMode;
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE
*
* This command will set MIG timeslice mode in GSP RM
*
* bMigTimeslicingModeEnabled
* Mode of MIG timeslice
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE (0x2080400f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS_MESSAGE_ID (0xFU)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS {
NvBool bMigTimeslicingModeEnabled;
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS;
/* _ctrl2080vgpumgrinternal_h_ */

1
src/common/sdk/nvidia/inc/ctrl/ctrl208f.h
View File

@@ -48,5 +48,6 @@
#include "ctrl208f/ctrl208fdma.h"
#include "ctrl208f/ctrl208fmmu.h"
#include "ctrl208f/ctrl208fucodecoverage.h"
#include "ctrl208f/ctrl208fnvlink.h"
#include "ctrl208f/ctrl208fpmu.h"

51
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbase.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,30 +31,33 @@
#include "ctrl/ctrlxxxx.h"
/* NV20_SUBDEVICE_DIAG: diagnostic class control commands and parameters */
#define NV208F_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x208F, NV208F_CTRL_##cat, idx)
#define NV208F_CTRL_CMD(cat, idx) NVXXXX_CTRL_CMD(0x208F, NV208F_CTRL_##cat, idx)
/* Subdevice diag command categories (6bits) */
#define NV208F_CTRL_RESERVED (0x00)
#define NV208F_CTRL_POWER (0x01)
#define NV208F_CTRL_THERMAL (0x02)
#define NV208F_CTRL_SEQ (0x03)
#define NV208F_CTRL_FIFO (0x04)
#define NV208F_CTRL_FB (0x05)
#define NV208F_CTRL_MC (0x06)
#define NV208F_CTRL_BIF (0x07)
#define NV208F_CTRL_CLK (0x08)
#define NV208F_CTRL_PERF (0x09)
#define NV208F_CTRL_FBIO (0x0A)
#define NV208F_CTRL_MMU (0x0B)
#define NV208F_CTRL_PMU (0x0C)
#define NV208F_CTRL_EVENT (0x10)
#define NV208F_CTRL_GPU (0x11)
#define NV208F_CTRL_GR (0x12)
#define NV208F_CTRL_PMGR (0x13)
#define NV208F_CTRL_DMA (0x14)
/* Subdevice diag command categories (6 bits) */
#define NV208F_CTRL_RESERVED (0x00)
#define NV208F_CTRL_POWER (0x01)
#define NV208F_CTRL_THERMAL (0x02)
#define NV208F_CTRL_SEQ (0x03)
#define NV208F_CTRL_FIFO (0x04)
#define NV208F_CTRL_FB (0x05)
#define NV208F_CTRL_MC (0x06)
#define NV208F_CTRL_BIF (0x07)
#define NV208F_CTRL_CLK (0x08)
#define NV208F_CTRL_PERF (0x09)
#define NV208F_CTRL_FBIO (0x0A)
#define NV208F_CTRL_MMU (0x0B)
#define NV208F_CTRL_PMU (0x0C)
#define NV208F_CTRL_EVENT (0x10)
#define NV208F_CTRL_GPU (0x11)
#define NV208F_CTRL_GR (0x12)
#define NV208F_CTRL_PMGR (0x13)
#define NV208F_CTRL_DMA (0x14)
// const NV208F_CTRL_TMR = (0x15); // not supported
#define NV208F_CTRL_GSPMSGTIMING (0x16)
#define NV208F_CTRL_BUS (0x17)
#define NV208F_CTRL_SEC2 (0x16)
#define NV208F_CTRL_GSPMSGTIMING (0x17)
#define NV208F_CTRL_BUS (0x18)
#define NV208F_CTRL_UCODE_COVERAGE (0x19)
#define NV208F_CTRL_NVLINK (0x1A)
/*
* NV208F_CTRL_CMD_NULL
@@ -65,6 +68,6 @@
* Possible status values returned are:
* NV_OK
*/
#define NV208F_CTRL_CMD_NULL (0x208f0000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID << 8) | 0x0" */
#define NV208F_CTRL_CMD_NULL (0x208f0000) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_RESERVED_INTERFACE_ID << 8) | 0x0" */
/* _ctrl208fbase_h_ */

96
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fnvlink.h Normal file
View File

@@ -0,0 +1,96 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl208f/ctrl208fnvlink.finn
//
#include "ctrl/ctrl208f/ctrl208fbase.h"
/*
* NV208F_CTRL_CMD_NVLINK_ECC_INJECT_ERROR
*
* This ctrl call injects NVLink SAW, RLW, and TLW ECC errors. Please see the confluence
* page "ECC" for more information on ECC and ECC injection:
*
* Parameters:
*
* errorUnit
* Specifies the HW unit where the injection will occur.
*
* errorType
* Specifies whether the injected error will be correctable or uncorrectable.
* Correctable errors have no effect on running programs while uncorrectable
* errors will cause all channels to be torn down.
*
* linkMask
* Specifies the mask of links to inject into where bit 0 = link 0, etc.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV208F_CTRL_CMD_NVLINK_ECC_INJECT_ERROR (0x208f1a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_NVLINK_INTERFACE_ID << 8) | NV208F_CTRL_NVLINK_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_NVLINK_ECC_INJECT_ERROR_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV208F_CTRL_NVLINK_ECC_INJECT_ERROR_PARAMS {
NvU8 errorUnit;
NvU8 errorType;
NvU32 linkMask;
} NV208F_CTRL_NVLINK_ECC_INJECT_ERROR_PARAMS;
/*
* NV208F_CTRL_CMD_NVLINK_ECC_INJECTION_SUPPORTED
*
* Reports if error injection is supported for the NVLink
*
* bCorrectableSupported [out]:
* Boolean value that shows if correcatable errors can be injected.
*
* bUncorrectableSupported [out]:
* Boolean value that shows if uncorrecatable errors can be injected.
*
* Return values:
* NV_OK on success
* NV_ERR_INSUFFICIENT_PERMISSIONS if priv write not enabled.
* NV_ERR_NOT_SUPPORTED otherwise
*/
#define NV208F_CTRL_CMD_NVLINK_ECC_INJECTION_SUPPORTED (0x208f1a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_NVLINK_INTERFACE_ID << 8) | NV208F_CTRL_NVLINK_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_NVLINK_ECC_INJECTION_SUPPORTED_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV208F_CTRL_NVLINK_ECC_INJECTION_SUPPORTED_PARAMS {
NvU8 errorUnit;
NvBool bCorrectableSupported;
NvBool bUncorrectableSupported;
} NV208F_CTRL_NVLINK_ECC_INJECTION_SUPPORTED_PARAMS;
/* _ctrl208fnvlink_h_ */

68
src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h
View File

@@ -231,6 +231,7 @@ typedef struct NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS {
NvU32 syncStartDelay;
NvU32 useHouseSync;
NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS syncMulDiv;
NvU32 syncVRR;
} NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS;
#define NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x3U)
@@ -246,30 +247,32 @@ typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PA
*
*/
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002
#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE 0x0040
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002
#define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE 0x0040
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_VRR 0x0080
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_MULTIPLY_DIVIDE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_MULTIPLY_DIVIDE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_VRR NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_VRR
/*
* syncPolarity values
*
*/
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2
/*
* syncVideoMode values
@@ -277,23 +280,30 @@ typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PA
*
*/
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2
#define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV
#define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4
/*
* multiplyDivide values
*
*/
#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY 0
#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE 1
#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY 0
#define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE 1
/*
* VRR values
*
*/
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MODE_FIXED_REFRESH_RATE 0
#define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MODE_VARIABLE_REFRESH_RATE 1
/*
* NV30F1_CTRL_CMD_GSYNC_GET_CAPS
@@ -366,7 +376,7 @@ typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PA
* NV_ERR_INVALID_ARGUMENT
*/
#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID (0x5U)

12
src/common/sdk/nvidia/inc/ctrl/ctrl506f.h
View File

@@ -39,7 +39,6 @@
/* NV50_GPFIFO command categories (6bits) */
#define NV506F_CTRL_RESERVED (0x00)
#define NV506F_CTRL_GPFIFO (0x01)
#define NV506F_CTRL_EVENT (0x02)
/*
* NV506F_CTRL_CMD_NULL
@@ -77,17 +76,6 @@
#define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL (0x506f0105) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID" */
/*
* NV506F_CTRL_CMD_EVENT_SET_TRIGGER (deprecated on Fermi+)
*
* This command triggers a software event for the associated channel.
* This command accepts no parameters.
*
* Possible status values returned are:
* NV_OK
*/
// #define NV506F_CTRL_CMD_EVENT_SET_TRIGGER NV506F_CTRL_CMD(EVENT, 0x09)
#define NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS {

45
src/common/sdk/nvidia/inc/ctrl/ctrl906f.h
View File

@@ -42,7 +42,6 @@
/* GF100_GPFIFO command categories (6bits) */
#define NV906F_CTRL_RESERVED (0x00)
#define NV906F_CTRL_GPFIFO (0x01)
#define NV906F_CTRL_EVENT (0x02)
/*
@@ -147,50 +146,7 @@ typedef struct NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS {
NvBool bIsRcPending;
} NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS;
/*
* NV906F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* This command sets event notification state for the associated channel.
* This command requires that an instance of NV01_EVENT has been previously
* bound to the associated channel object.
*
* event
* This parameter specifies the type of event to which the specified
* action is to be applied. This parameter must specify a valid
* NV906F_NOTIFIERS value (see cl906f.h for more details) and should
* not exceed one less NV906F_NOTIFIERS_MAXCOUNT.
* action
* This parameter specifies the desired event notification action.
* Valid notification actions include:
* NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_DISABLE
* This action disables event notification for the specified
* event for the associated channel object.
* NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_SINGLE
* This action enables single-shot event notification for the
* specified event for the associated channel object.
* NV906F_CTRL_SET_EVENT_NOTIFICATION_ACTION_REPEAT
* This action enables repeated event notification for the specified
* event for the associated channel object.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV906F_CTRL_CMD_EVENT_SET_NOTIFICATION (0x906f0203) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_EVENT_INTERFACE_ID << 8) | NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
NvU32 event;
NvU32 action;
} NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
#define NV906F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
/*
* NV906F_CTRL_CMD_GET_DEFER_RC_STATE
@@ -206,6 +162,7 @@ typedef struct NV906F_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
* Possible status values returned are:
* NV_OK
*/
#define NV906F_CTRL_CMD_GET_DEFER_RC_STATE (0x906f0105) /* finn: Evaluated from "(FINN_GF100_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID" */
#define NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS_MESSAGE_ID (0x5U)

2
src/common/sdk/nvidia/inc/ctrl/ctrla06c.h
View File

@@ -53,7 +53,7 @@
*/
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrla06f.h" /* A06C is partially derived from A06F */
#include "ctrl/ctrla06f/ctrla06fgpfifo.h" /* A06C is partially derived from A06F */
#include "ctrl/ctrl2080/ctrl2080internal.h" /* For NV2080_CTRL_INTERNAL_MEMDESC_INFO */
#include "ctrl/ctrlc36f.h" /* For NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES */

1
src/common/sdk/nvidia/inc/ctrl/ctrla06f.h
View File

@@ -33,5 +33,4 @@
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrla06f/ctrla06fbase.h"
#include "ctrl/ctrla06f/ctrla06fgpfifo.h"
#include "ctrl/ctrla06f/ctrla06fevent.h"
#include "ctrl/ctrla06f/ctrla06finternal.h"

1
src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fbase.h
View File

@@ -42,7 +42,6 @@
/* GK100_GPFIFO command categories (6bits) */
#define NVA06F_CTRL_RESERVED (0x00)
#define NVA06F_CTRL_GPFIFO (0x01)
#define NVA06F_CTRL_EVENT (0x02)
#define NVA06F_CTRL_INTERNAL (0x03)
/*

92
src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fevent.h
View File

@@ -1,92 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrla06f/ctrla06fevent.finn
//
#include "ctrl/ctrla06f/ctrla06fbase.h"
/*
* NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* This command sets event notification state for the associated channel.
* This command requires that an instance of NV01_EVENT has been previously
* bound to the associated channel object.
*
* event
* This parameter specifies the type of event to which the specified
* action is to be applied. This parameter must specify a valid
* NVA06F_NOTIFIERS value (see cla06f.h for more details) and should
* not exceed one less NVA06F_NOTIFIERS_MAXCOUNT.
* action
* This parameter specifies the desired event notification action.
* Valid notification actions include:
* NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_DISABLE
* This action disables event notification for the specified
* event for the associated channel object.
* NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_SINGLE
* This action enables single-shot event notification for the
* specified event for the associated channel object.
* NVA06F_CTRL_SET_EVENT_NOTIFICATION_ACTION_REPEAT
* This action enables repeated event notification for the specified
* event for the associated channel object.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xa06f0205) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x5U)
typedef struct NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
NvU32 event;
NvU32 action;
} NVA06F_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
#define NVA06F_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
/*
* NVA06F_CTRL_CMD_EVENT_SET_TRIGGER
*
* This command triggers a software event for the associated channel.
* This command accepts no parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NVA06F_CTRL_CMD_EVENT_SET_TRIGGER (0xa06f0206) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
/* _ctrla06fevent_h_ */

15
src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2007-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -44,6 +44,18 @@
* When set, the channel will be enabled in addition to being added to the appropriate runlist.
* When not set, the channel will be disabled and removed from runlist.
*
* bSkipSubmit
* This parameter indicates whether this channel is not to be scheduled, even though it is enabled.
* When set, the channel will not be scheduled.
* When not set, the channel will be scheduled.
*
* bSkipEnable
* This parameter indicates whether this channel is not to be enabled, even though it is scheduled.
* When set, the channel will not be enabled.
* When not set, the channel will be enabled.
*
* When bEnable is set, both bSkipSubmit and bSkipEnable can't be set.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_OBJECT_HANDLE
@@ -57,6 +69,7 @@
typedef struct NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS {
NvBool bEnable;
NvBool bSkipSubmit;
NvBool bSkipEnable;
} NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS;
/*

10
src/common/sdk/nvidia/inc/ctrl/ctrla080.h
View File

@@ -393,12 +393,18 @@ typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS {
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS 21:21
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_FALSE (0x00000000)
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_TRUE (0x00000001)
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED 22:22
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED 22:22
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_FALSE (0x00000000)
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GUEST_HIBERNATION_ENABLED_TRUE (0x00000001)
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED 23:23
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED 23:23
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_FALSE (0x00000000)
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED_TRUE (0x00000001)
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPM_ENABLED 24:24
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPM_ENABLED_FALSE (0x00000000)
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_GPM_ENABLED_TRUE (0x00000001)
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CI_MANIPULATION_ENABLED 25:25
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CI_MANIPULATION_ENABLED_FALSE (0x00000000)
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_CI_MANIPULATION_ENABLED_TRUE (0x00000001)
/* UVM supported features */
#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED 0:0

48
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
View File

@@ -33,6 +33,7 @@
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl2080/ctrl2080gpu.h"
#include "nv_vgpu_types.h"
#include "nvcfg_sdk.h"
/* NVA081_VGPU_CONFIG control commands and parameters */
#define NVA081_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA081, NVA081_CTRL_##cat, idx)
@@ -42,8 +43,9 @@
#define NVA081_CTRL_VGPU_CONFIG (0x01)
#define NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE 0x00
#define NVA081_MAX_VGPU_TYPES_PER_PGPU 0x40
#define NVA081_MAX_VGPU_TYPES_PER_PGPU 0x64
#define NVA081_MAX_VGPU_PER_PGPU 32
#define NVA081_MAX_VGPU_PER_GI 12
#define NVA081_VM_UUID_SIZE 16
#define NVA081_VGPU_STRING_BUFFER_SIZE 32
#define NVA081_VGPU_SIGNATURE_SIZE 128
@@ -118,6 +120,7 @@ typedef struct NVA081_CTRL_VGPU_INFO {
NvU32 ftraceEnable;
NvU32 gpuDirectSupported;
NvU32 nvlinkP2PSupported;
NvU32 maxInstancePerGI;
NvU32 multiVgpuExclusive;
NvU32 exclusiveType;
NvU32 exclusiveSize;
@@ -329,6 +332,11 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS {
* This structure represents supported/creatable vGPU types on a pGPU
*/
typedef struct NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS {
/*
* [IN] GPU Instance ID or Swizz ID
*/
NvU32 gpuInstanceId;
/*
* [OUT] vGPU config state on a pGPU
*/
@@ -793,6 +801,9 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_UPDATE_PLACEMENT_INFO_PARAMS {
*
* Parameters:
*
* gpuInstanceId [IN]
* GPU Instance ID or Swizz ID
*
* vgpuTypeId [IN]
* The client provided vGPU type ID
*
@@ -816,6 +827,7 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_UPDATE_PLACEMENT_INFO_PARAMS {
#define NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS_MESSAGE_ID (0x1cU)
typedef struct NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS {
NvU32 gpuInstanceId;
NvU32 vgpuTypeId;
NvU32 placementSize;
NvU32 count;
@@ -855,6 +867,11 @@ typedef struct NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS {
#define NVA081_CTRL_VGPU_CAPABILITY_FRACTIONAL_MULTI_VGPU 8
#define NVA081_CTRL_VGPU_CAPABILITY_HOMOGENEOUS_PLACEMENT_ID 9
#define NVA081_CTRL_VGPU_CAPABILITY_MIG_TIMESLICING_SUPPORTED 10
#define NVA081_CTRL_VGPU_CAPABILITY_MIG_TIMESLICING_MODE_ENABLED 11
/*
* NVA081_CTRL_CMD_VGPU_SET_CAPABILITY
*
@@ -1010,4 +1027,33 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS {
NvU32 migrationBandwidth;
} NVA081_CTRL_VGPU_CONFIG_GET_MIGRATION_BANDWIDTH_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE
*
* This command enumerates list of vGPU guest instances per GPU instance
*
* gpuInstanceId [IN]
* This parameter specifies the GPU Instance Id or Swizz Id
*
* numVgpu [OUT]
* This parameter specifies the number of virtual GPUs created on a GPU instance
*
* vgpuInstanceIds [OUT]
* This parameter specifies an array of vGPU type ids active on a GPU instance
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_NOT_SUPPORTED
*/
#define NVA081_CTRL_CMD_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE (0xa0810124) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS_MESSAGE_ID (0x24U)
typedef struct NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS {
NvU32 gpuInstanceId;
NvU32 numVgpu;
NvU32 vgpuInstanceIds[NVA081_MAX_VGPU_PER_GI];
} NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_GPU_INSTANCE_PARAMS;
/* _ctrlA081vgpuconfig_h_ */

14
src/common/sdk/nvidia/inc/ctrl/ctrla16f.h
View File

@@ -34,15 +34,11 @@
/* GK100_GPFIFO control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrla06f.h" /* A16F is partially derived from A06F */
#include "ctrl/ctrl906f.h" /* A16F is partially derived from 906F */
#define NVA16F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xA16F, NVA16F_CTRL_##cat, idx)
/* GK100_GPFIFO command categories (6bits) */
#define NVA16F_CTRL_RESERVED (0x00)
#define NVA16F_CTRL_GPFIFO (0x01)
#define NVA16F_CTRL_EVENT (0x02)
/*
* NVA16F_CTRL_CMD_NULL
@@ -55,13 +51,3 @@
*/
#define NVA16F_CTRL_CMD_NULL (0xa16f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NVA16F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVA16F_CTRL_CMD_EVENT_SET_TRIGGER (0xa16f0106) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_B_EVENT_INTERFACE_ID << 8) | 0x6" */
/* _ctrla16f.h_ */

14
src/common/sdk/nvidia/inc/ctrl/ctrla26f.h
View File

@@ -34,15 +34,11 @@
/* GK20A_GPFIFO control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrla06f.h" /* A26F is partially derived from A06F */
#include "ctrl/ctrl906f.h" /* A26F is partially derived from 906F */
#define NVA26F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xA26F, NVA26F_CTRL_##cat, idx)
/* GK20A_GPFIFO command categories (6bits) */
#define NVA26F_CTRL_RESERVED (0x00)
#define NVA26F_CTRL_GPFIFO (0x01)
#define NVA26F_CTRL_EVENT (0x02)
/*
* NVA26F_CTRL_CMD_NULL
@@ -55,13 +51,3 @@
*/
#define NVA26F_CTRL_CMD_NULL (0xa26f0000) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NVA26F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVA26F_CTRL_CMD_EVENT_SET_TRIGGER (0xa26f0106) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_C_EVENT_INTERFACE_ID << 8) | 0x6" */
/* _ctrla26f.h_ */

13
src/common/sdk/nvidia/inc/ctrl/ctrlb06f.h
View File

@@ -36,15 +36,12 @@
/* MAXWELL_CHANNEL_GPFIFO_A control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrla06f.h" /* B06F is partially derived from A06F */
#include "ctrl/ctrl906f.h" /* B06F is partially derived from 906F */
#define NVB06F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xB06F, NVB06F_CTRL_##cat, idx)
/* MAXWELL_CHANNEL_GPFIFO_A command categories (6bits) */
#define NVB06F_CTRL_RESERVED (0x00)
#define NVB06F_CTRL_GPFIFO (0x01)
#define NVB06F_CTRL_EVENT (0x02)
/*
* NVB06F_CTRL_CMD_NULL
@@ -366,13 +363,3 @@ typedef struct NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS {
NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS params;
} NVB06F_CTRL_CMD_RESTORE_ENGINE_CTX_DATA_FINN_PARAMS;
/*
* NVB06F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVB06F_CTRL_CMD_EVENT_SET_TRIGGER (0xb06f0206) /* finn: Evaluated from "(FINN_MAXWELL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
/* _ctrlb06f.h_ */

1
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h
View File

@@ -403,6 +403,7 @@ typedef enum NVB0CC_CHIPLET_TYPE {
NVB0CC_CHIPLET_TYPE_FBP = 1,
NVB0CC_CHIPLET_TYPE_GPC = 2,
NVB0CC_CHIPLET_TYPE_SYS = 3,
} NVB0CC_CHIPLET_TYPE;
typedef enum NVB0CC_HS_CREDITS_CMD_STATUS {

15
src/common/sdk/nvidia/inc/ctrl/ctrlc06f.h
View File

@@ -34,15 +34,9 @@
/* PASCAL_CHANNEL_GPFIFO_A control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrla06f.h" /* C06F is partially derived from A06F */
#include "ctrl/ctrl906f.h" /* C06F is partially derived from 906F */
#define NVC06F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xC06F, NVC06F_CTRL_##cat, idx)
/* PASCAL_CHANNEL_GPFIFO_B command categories (6bits) */
#define NVC06F_CTRL_RESERVED (0x00)
#define NVC06F_CTRL_GPFIFO (0x01)
#define NVC06F_CTRL_EVENT (0x02)
/*
* NVC06F_CTRL_CMD_NULL
@@ -55,12 +49,3 @@
*/
#define NVC06F_CTRL_CMD_NULL (0xc06f0000) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NVC06F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVC06F_CTRL_CMD_EVENT_SET_TRIGGER (0xc06f0106) /* finn: Evaluated from "(FINN_PASCAL_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */

19
src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h
View File

@@ -36,15 +36,12 @@
/* VOLTA_CHANNEL_GPFIFO_A control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
#define NVC36F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xC36F, NVC36F_CTRL_##cat, idx)
/* VOLTA_CHANNEL_GPFIFO_A command categories (6bits) */
#define NVC36F_CTRL_RESERVED (0x00)
#define NVC36F_CTRL_GPFIFO (0x01)
#define NVC36F_CTRL_EVENT (0x02)
#define NVC36F_CTRL_INTERNAL (0x03)
/*
@@ -142,22 +139,6 @@ typedef struct NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS {
/*
* NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_NOTIFICATION for more information.
*/
#define NVC36F_CTRL_CMD_EVENT_SET_NOTIFICATION (0xc36f0205) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x5" */
/*
* NVC36F_CTRL_CMD_EVENT_SET_TRIGGER
*
* Please see description of NVA06F_CTRL_CMD_EVENT_SET_TRIGGER for more information.
*/
#define NVC36F_CTRL_CMD_EVENT_SET_TRIGGER (0xc36f0206) /* finn: Evaluated from "(FINN_VOLTA_CHANNEL_GPFIFO_A_EVENT_INTERFACE_ID << 8) | 0x6" */
/*
* NVC36F_CTRL_CMD_INTERNAL_GPFIFO_GET_WORK_SUBMIT_TOKEN
*

11
src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h
View File

@@ -34,6 +34,17 @@
/* C370 is partially derived from 0073 */
#include "ctrl/ctrl0073/ctrl0073event.h"
/*
* headId
* This parameter indicates the ID of head on which we received interrupt
* RgSemId
* This parameter indicates the RG Semaphore Index for given head
*/
typedef struct NVC370_RG_SEM_NOTIFICATION_PARAMS {
NvU32 headId;
NvU32 rgSemId;
} NVC370_RG_SEM_NOTIFICATION_PARAMS;

2
src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h
View File

@@ -362,7 +362,7 @@
* if the mode will be possible or not on that head when OSLD is enabled.
* The output is only valid if bGetOSLDOutput is set in the head input.
* Note that bIsOSLDPossible is only valid if bIsPossible is true.
*
*
* minImpVPState
* minImpVPState returns the minimum v-pstate at which the mode is possible
* (assuming bIsPossible is TRUE). This output is valid only on dGPU, and

3
src/common/sdk/nvidia/inc/ctrl/ctrlc46f.h
View File

@@ -34,8 +34,6 @@
/* TURING_CHANNEL_GPFIFO_A control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
#define NVC46F_CTRL_CMD(cat,idx) \
@@ -44,7 +42,6 @@
/* TURING_CHANNEL_GPFIFO_A command categories (6bits) */
#define NVC46F_CTRL_RESERVED (0x00)
#define NVC46F_CTRL_GPFIFO (0x01)
#define NVC46F_CTRL_EVENT (0x02)
/*
* NVC46F_CTRL_CMD_NULL

10
src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h
View File

@@ -36,8 +36,6 @@
/* AMPERE_CHANNEL_GPFIFO_A control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
#include "cc_drv.h"
@@ -50,7 +48,6 @@
/* AMPERE_CHANNEL_GPFIFO_A command categories (6bits) */
#define NVC56F_CTRL_RESERVED (0x00)
#define NVC56F_CTRL_GPFIFO (0x01)
#define NVC56F_CTRL_EVENT (0x02)
/*
* NVC56F_CTRL_CMD_NULL
@@ -83,6 +80,11 @@ typedef struct NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR {
*
* kmb [OUT] The KMB for the channel.
* hMemory [IN] Memory handle to the encryption statistics buffer for the channel.
* keyRotationLowerThreshold [OUT] Key rotation lower threshold.
* keyRotationUpperThreshold [OUT] Key rotation upper threshold.
*
* The key rotation thresholds are in units of
* (amount of data encrypted in units of 16 bytes + number of encryption invocations).
*
* Possible status values returned are:
* NV_OK
@@ -97,6 +99,8 @@ typedef struct NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR {
typedef struct NVC56F_CTRL_CMD_GET_KMB_PARAMS {
CC_KMB kmb;
NvHandle hMemory;
NV_DECLARE_ALIGNED(NvU64 keyRotationLowerThreshold, 8);
NV_DECLARE_ALIGNED(NvU64 keyRotationUpperThreshold, 8);
} NVC56F_CTRL_CMD_GET_KMB_PARAMS;
/*

3
src/common/sdk/nvidia/inc/ctrl/ctrlc86f.h
View File

@@ -37,8 +37,6 @@
/* HOPPER_CHANNEL_GPFIFO_A control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
#define NVC86F_CTRL_CMD(cat,idx) \
@@ -47,7 +45,6 @@
/* HOPPER_CHANNEL_GPFIFO_A command categories (6bits) */
#define NVC86F_CTRL_RESERVED (0x00)
#define NVC86F_CTRL_GPFIFO (0x01)
#define NVC86F_CTRL_EVENT (0x02)
/*
* NVC86F_CTRL_CMD_NULL

3
src/common/sdk/nvidia/inc/ctrl/ctrlc96f.h
View File

@@ -37,8 +37,6 @@
/* BLACKWELL_CHANNEL_GPFIFO_A control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
#define NVC96F_CTRL_CMD(cat,idx) \
@@ -47,7 +45,6 @@
/* BLACKWELL_CHANNEL_GPFIFO_A command categories (6bits) */
#define NVC96F_CTRL_RESERVED (0x00)
#define NVC96F_CTRL_GPFIFO (0x01)
#define NVC96F_CTRL_EVENT (0x02)
/*
* NVC96F_CTRL_CMD_NULL

3
src/common/sdk/nvidia/inc/ctrl/ctrlca6f.h
View File

@@ -37,8 +37,6 @@
/* BLACKWELL_CHANNEL_GPFIFO_B control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
#define NVCA6F_CTRL_CMD(cat,idx) \
@@ -47,7 +45,6 @@
/* BLACKWELL_CHANNEL_GPFIFO_B command categories (6bits) */
#define NVCA6F_CTRL_RESERVED (0x00)
#define NVCA6F_CTRL_GPFIFO (0x01)
#define NVCA6F_CTRL_EVENT (0x02)
/*
* NVCA6F_CTRL_CMD_NULL

1
src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h
View File

@@ -128,6 +128,7 @@
#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE 0
#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE 1
#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NVLE 2
typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS {
NvU8 cpuCapability;