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560.28.03

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This commit is contained in:
Gaurav Juvekar
2024-07-19 15:45:15 -07:00
parent 5fdf5032fb
commit 448d5cc656
859 changed files with 165424 additions and 91129 deletions
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2
src/nvidia/inc/kernel/core/thread_state.h
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@@ -138,7 +138,6 @@ typedef struct THREAD_STATE_DB
NvU32 gspIsrThreadSeqCntr;
PORT_SPINLOCK *spinlock;
ThreadStateNodeMap dbRoot;
ThreadStateNodeMap dbRootPreempted;
THREAD_STATE_NODE **ppISRDeferredIntHandlerThreadNode;
PTHREAD_STATE_ISR_LOCKLESS pIsrlocklessThreadNode;
THREAD_STATE_DB_TIMEOUT timeout;
@@ -180,7 +179,6 @@ typedef struct THREAD_STATE_DB
#define THREAD_STATE_FLAGS_IS_DEFERRED_INT_HANDLER NVBIT(2)
#define THREAD_STATE_FLAGS_IS_ISR_LOCKLESS NVBIT(3)
#define THREAD_STATE_FLAGS_TIMEOUT_INITED NVBIT(5)
#define THREAD_STATE_FLAGS_PLACED_ON_PREEMPT_LIST NVBIT(6)
#define THREAD_STATE_FLAGS_DEVICE_INIT NVBIT(7)
#define THREAD_STATE_FLAGS_STATE_FREE_CB_ENABLED NVBIT(8)

4
src/nvidia/inc/kernel/gpu/ce/kernel_ce_shared.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,6 +31,8 @@
*/
NvBool ceIsCeGrce(OBJGPU *pGpu, RM_ENGINE_TYPE ceEngineType);
NvBool ceIsPartneredWithGr(OBJGPU *pGpu, RM_ENGINE_TYPE ceEngineType, RM_ENGINE_TYPE grEngineType);
NvU32 ceCountGrCe(OBJGPU *pGpu);
NvBool ceIsDecompLce(OBJGPU *pGpu, NvU32 nv2080EngineId);
#endif

17
src/nvidia/inc/kernel/gpu/conf_compute/ccsl_context.h
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@@ -27,9 +27,18 @@
#include "nvtypes.h"
#include "cc_drv.h"
struct decryptBundle_t
{
NvU8 keyIn[CC_AES_256_GCM_KEY_SIZE_BYTES];
NvU8 ivMaskIn[CC_AES_256_GCM_IV_SIZE_BYTES];
};
typedef struct decryptBundle_t *pDecryptBundle;
struct ccslContext_t
{
NvHandle hClient;
NvHandle hSubdevice;
NvHandle hChannel;
enum {CSL_MSG_CTR_32, CSL_MSG_CTR_64} msgCounterSize;
@@ -51,11 +60,19 @@ struct ccslContext_t
NvU64 keyHandleIn;
NvU64 keyHandleOut;
NvU64 keyHandleOutFallback;
NvU32 globalKeyIdIn;
NvU32 globalKeyIdOut;
void *openrmCtx;
void *pConfCompute;
MEMORY_DESCRIPTOR *pMemDesc;
volatile CC_CRYPTOBUNDLE_STATS *pEncStatsBuffer;
pDecryptBundle pDecryptBundles;
NvU32 currDecryptBundle;
};
typedef struct ccslContext_t *pCcslContext;

3
src/nvidia/inc/kernel/gpu/dbgbuffer.h Normal file
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@@ -0,0 +1,3 @@
#include "g_dbgbuffer_nvoc.h"

3
src/nvidia/inc/kernel/gpu/disp/dispsw.h Normal file
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@@ -0,0 +1,3 @@
#include "g_dispsw_nvoc.h"

263
src/nvidia/inc/kernel/gpu/error_cont.h Normal file
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@@ -0,0 +1,263 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*!
* @file error_cont.h
* @brief Holds data structures, defines and policy table required by the
* Ampere Error Containment feature / code.
*/
#ifndef _ERROR_CONT_H_
#define _ERROR_CONT_H_
/* ------------------------ Includes ---------------------------------------- */
#include "core/core.h"
#include "kernel/gpu/gpu_engine_type.h"
#include "nverror.h"
/* ------------------------ Forward Definitions ----------------------------- */
typedef struct Device Device;
/* ------------------------ Datatypes --------------------------------------- */
/*!
* Error Containment error ID enum
*/
typedef enum _NV_ERROR_CONT_ERR_ID
{
NV_ERROR_CONT_ERR_ID_E01_FB_ECC_DED = 0, // FD Error ID: E01: FB ECC DED
NV_ERROR_CONT_ERR_ID_E02_FB_ECC_DED_IN_CBC_STORE = 1, // FD Error ID: E02: FB ECC DED in CBC
NV_ERROR_CONT_ERR_ID_E05_LTC_ECC_DSTG = 2, // FD Error ID: E05: LTC ECC in data region
NV_ERROR_CONT_ERR_ID_E06_LTC_UNSUPPORTED_CLIENT_POISON = 3, // FD Error ID: E06: LTC unsupported client poison
NV_ERROR_CONT_ERR_ID_E07_LTC_ECC_TSTG = 4, // FD Error ID: E07: LTC Tag Parity error
NV_ERROR_CONT_ERR_ID_E08_LTC_ECC_RSTG = 5, // FD Error ID: E08: LTC CBC Parity error
NV_ERROR_CONT_ERR_ID_E09_FBHUB_POISON = 6, // FD Error ID: E09: FBHUB poison error
NV_ERROR_CONT_ERR_ID_E10_SM_POISON = 7, // FD Error ID: E10: SM poison error
NV_ERROR_CONT_ERR_ID_E12A_CE_POISON_IN_USER_CHANNEL = 8, // FD Error ID: E12: CE poison error in user channel
NV_ERROR_CONT_ERR_ID_E12B_CE_POISON_IN_KERNEL_CHANNEL = 9, // FD Error ID: E12: CE poison error in kernel channel
NV_ERROR_CONT_ERR_ID_E13_MMU_POISON = 10, // FD Error ID: E13: MMU poison error
NV_ERROR_CONT_ERR_ID_E16_GCC_POISON = 11, // FD Error ID: E16: GCC poison error
NV_ERROR_CONT_ERR_ID_E17_CTXSW_POISON = 12, // FD Error ID: E17: FECS/GPCCS/TPCCS poison error
NV_ERROR_CONT_ERR_ID_E20_XALEP_EGRESS_POISON = 13, // FD Error ID: E20: XALEP EGRESS poison error
NV_ERROR_CONT_ERR_ID_E21A_XALEP_INGRESS_CONTAINED_POISON = 14, // FD Error ID: E21: XALEP INGRESS contained poison error
NV_ERROR_CONT_ERR_ID_E21B_XALEP_INGRESS_UNCONTAINED_POISON = 15, // FD Error ID: E21: XALEP INGRESS contained poison error
NV_ERROR_CONT_ERR_ID_E22_PMU_POISON = 16, // FD Error ID: E22: PMU poison error
NV_ERROR_CONT_ERR_ID_E23_SEC2_POISON = 17, // FD Error ID: E23: SEC2 poison error
NV_ERROR_CONT_ERR_ID_E24_GSP_POISON = 18, // FD Error ID: E24: GSP poison error
NV_ERROR_CONT_ERR_ID_E25_FBFALCON_POISON = 19, // FD Error ID: E25: FBFalcon poison error
NV_ERROR_CONT_ERR_ID_E26_NVDEC_POISON = 20, // FD Error ID: E26: NVDEC poison error
NV_ERROR_CONT_ERR_ID_E27_NVJPG_POISON = 21, // FD Error ID: E27: NVJPG poison error
NV_ERROR_CONT_ERR_ID_E28_OFA_POISON = 22 // FD Error ID: E28: OFA poison error
} NV_ERROR_CONT_ERR_ID;
/*!
* Error Containment settings per error ID, when SMC memory partitioning is disable or enabled.
*/
typedef struct _NV_ERROR_CONT_SMC_DIS_EN_SETTING
{
NvU32 rcErrorCode;
NvBool bGpuResetReqd;
NvBool bGpuDrainAndResetReqd;
NvBool bPrintSmcPartitionInfo;
NvU32 nv2080Notifier;
} NV_ERROR_CONT_SMC_DIS_EN_SETTING;
/*!
* Error Containment state table tracking policy settings for each error ID
*/
typedef struct _NV_ERROR_CONT_STATE_TABLE
{
NV_ERROR_CONT_ERR_ID errorCode;
NV_ERROR_CONT_SMC_DIS_EN_SETTING smcDisEnSetting[2]; // 0: SMC memory partitioning disabled,
// 1: SMC memory partitioning enabled
} NV_ERROR_CONT_STATE_TABLE;
/*!
* Struct for LTC location
*/
typedef struct _NV_ERROR_CONT_LOCATION_LTC
{
NvU32 partition;
NvU32 slice;
} NV_ERROR_CONT_LOCATION_LTC;
/*!
* Struct for DRAM location
*/
typedef struct _NV_ERROR_CONT_LOCATION_DRAM
{
NvU32 partition;
NvU32 subPartition;
NvU64 physicalAddress;
} NV_ERROR_CONT_LOCATION_DRAM;
/*!
* Struct for Engine id
*/
typedef struct _NV_ERROR_CONT_LOCATION_ENG_ID
{
RM_ENGINE_TYPE rmEngineId;
Device *pDevice;
} NV_ERROR_CONT_LOCATION_ENG_ID;
/*!
* Error Containment location type
*/
typedef enum _NV_ERROR_CONT_LOCATION_TYPE
{
NV_ERROR_CONT_LOCATION_TYPE_NONE = 0, // No location information available
NV_ERROR_CONT_LOCATION_TYPE_DRAM = 1, // DRAM location
NV_ERROR_CONT_LOCATION_TYPE_LTC = 2, // LTC location
NV_ERROR_CONT_LOCATION_TYPE_ENGINE = 3, // Engine location
NV_ERROR_CONT_LOCATION_TYPE_VF = 4 // VF location
} NV_ERROR_CONT_LOCATION_TYPE;
/*!
* Union for Error Containment location information
*/
typedef union _NV_ERROR_CONT_LOCATION_INFO
{
NV_ERROR_CONT_LOCATION_DRAM dramLoc; // DRAM location
NV_ERROR_CONT_LOCATION_LTC ltcLoc; // LTC location
NV_ERROR_CONT_LOCATION_ENG_ID engineLoc; // Engine location
NvU32 vfGfid; // VF location
} NV_ERROR_CONT_LOCATION_INFO;
typedef struct _NV_ERROR_CONT_LOCATION
{
NV_ERROR_CONT_LOCATION_TYPE locType;
NV_ERROR_CONT_LOCATION_INFO locInfo;
} NV_ERROR_CONT_LOCATION;
/* ------------------------ Macros ------------------------------------------ */
#define ROBUST_CHANNEL_CONTAINED_ERROR_STR "Contained"
#define ROBUST_CHANNEL_UNCONTAINED_ERROR_STR "Uncontained"
#define NO_XID NV_U32_MAX
#define NO_NV2080_NOTIFIER NV2080_NOTIFIERS_MAXCOUNT
#define NV_ERR_CONT_LOCATION_STRING_SIZE_MAX 64
/*!
* Error Containment error types string
*/
#define NV_ERROR_CONT_ERR_ID_STRING_PUBLIC {"FB DED", \
"DED CBC", \
"LTC Data", \
"LTC GPC", \
"LTC TAG", \
"LTC CBC", \
"FBHUB", \
"SM", \
"CE User Channel", \
"CE Kernel Channel", \
"MMU", \
"GCC", \
"CTXSW", \
"PCIE", \
"PCIE", \
"PCIE", \
"PMU", \
"SEC2", \
"GSP", \
"FB Falcon", \
"NVDEC", \
"NVJPG", \
"OFA"}
/*!
* Error Containment state table showing policy settings for each error id
*
* Where:
* RC_Recovery_Type:
* Type of RC recovery handling in response to a given error. Possible values:
*
* - NO_RC : No RC Recovery performed. Subsequent 2nd interrupt by engine
* consuming poison will determine the RC Recovery type.
* - RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE : RC Recovery compute channels of only the processes whose
* channels were loaded on halted TSG when _E10_SM_POISON or
* _E12A_CE_POISON_IN_USER_CHANNEL occurs.
* - RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION : RC Recovery compute channels of only specific MIG partition
* as that error can be attributed to a specific MIG partition.
* - RC_ALL_COMPUTE_CHANNELS : RC Recovery ALL compute channels on a GPU that saw this interrupt.
* (If MIG is enabled, then RC Recovery compute channels in all MIG partitions)
* - CE_TSG_RESET : Reset the halted CE Engine. Impacts the CE channels loaded on the TSG when the CE Halted.
* This is used in NV_ERROR_CONT_ERR_ID_E12A_CE_POISON_IN_USER_CHANNEL &
* NV_ERROR_CONT_ERR_ID_E12B_CE_POISON_IN_KERNEL_CHANNEL along with additional
* Compute Channels RC policy (either RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE or
* RC_ALL_COMPUTE_CHANNELS).
*/
#define NV_ERROR_CONT_STATE_TABLE_SETTINGS \
{ \
/* errorCode , rcErrorCode , bGpuResetReqd, bGpuDrainAndResetReqd, bPrintSmcPartitionInfo, nv2080Notifier , Dynamic Page Blacklisting , RC_Recovery_Type */ \
{ NV_ERROR_CONT_ERR_ID_E01_FB_ECC_DED , {{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , Yes(PMA but not subheap) , NO_RC */ }, \
{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , Yes(PMA but not subheap) , NO_RC */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E02_FB_ECC_DED_IN_CBC_STORE , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , Yes(PMA but not subheap) , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_TRUE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , Yes(PMA but not subheap) , RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E05_LTC_ECC_DSTG , {{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , No , NO_RC */ }, \
{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , No , NO_RC */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E06_LTC_UNSUPPORTED_CLIENT_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_TRUE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E07_LTC_ECC_TSTG , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E08_LTC_ECC_RSTG , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_TRUE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E09_FBHUB_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E10_SM_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E12A_CE_POISON_IN_USER_CHANNEL , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE + CE_TSG_RESET */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE + CE_TSG_RESET */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E12B_CE_POISON_IN_KERNEL_CHANNEL , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS + CE_TSG_RESET */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS + CE_TSG_RESET */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E13_MMU_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , NO_RC */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , NO_RC */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E16_GCC_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E17_CTXSW_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E20_XALEP_EGRESS_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E21A_XALEP_INGRESS_CONTAINED_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_CHANNELS_IN_VF */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_CHANNELS_IN_VF */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E21B_XALEP_INGRESS_UNCONTAINED_POISON, {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E22_PMU_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E23_SEC2_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E24_GSP_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , NO_RC */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , NO_RC */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E25_FBFALCON_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E26_NVDEC_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E27_NVJPG_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E28_OFA_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}} \
}
/* ------------------------ Function Prototypes ----------------------------- */
#endif // _ERROR_CONT_H_

2
src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h
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@@ -136,6 +136,8 @@ struct DACP2060EXTERNALDEVICE
NvBool bReCheck; // Enabled to verify initialDifference 1 sec after initialization.
NvBool enableFrmCmpMatchIntSlave; // Enable the frmCmpMatchInt for slave, if this bit is set.
NvBool isFrmCmpMatchIntMasterEnabled; // To enable frmCmpMatchInt for master when gsync framecount exceeds (2^24 - 1000)
TMR_EVENT *pTimerEvent; // Used for supporting gsyncFrameCountTimerService_P2060
} FrameCountData;
struct {

314
src/nvidia/inc/kernel/gpu/external_device/dev_p2060.h Normal file
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@@ -0,0 +1,314 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DEV_P2060_H
#define DEV_P2060_H
#define NV_P2060_STATUS 0x00 /* R--1R */
#define NV_P2060_STATUS_VAL 7:0 /* R-XVF */
#define NV_P2060_STATUS_VCXO 1:0 /* R-XVF */
#define NV_P2060_STATUS_VCXO_NOLOCK_TOO_FAST 0x00 /* R---V */
#define NV_P2060_STATUS_VCXO_NOLOCK_TOO_SLOW 0x01 /* R---V */
#define NV_P2060_STATUS_VCXO_LOCK 0x02 /* R---V */
#define NV_P2060_STATUS_VCXO_NOT_SERVO 0x03 /* R---V */
#define NV_P2060_STATUS_SYNC_LOSS 2:2 /* R-XVF */
#define NV_P2060_STATUS_SYNC_LOSS_FALSE 0x00 /* R---V */
#define NV_P2060_STATUS_SYNC_LOSS_TRUE 0x01 /* R---V */
#define NV_P2060_STATUS_RESERVED1 3:3 /* RWXVF */
#define NV_P2060_STATUS_GPU_STEREO 4:4 /* R-XVF */
#define NV_P2060_STATUS_GPU_STEREO_NOT_ACTIVE 0x00 /* R---V */
#define NV_P2060_STATUS_GPU_STEREO_ACTIVE 0x01 /* R---V */
#define NV_P2060_STATUS_MSTR_STEREO 5:5 /* R-XVF */
#define NV_P2060_STATUS_MSTR_STEREO_NOT_ACTIVE 0x00 /* R---V */
#define NV_P2060_STATUS_MSTR_STEREO_ACTIVE 0x01 /* R---V */
#define NV_P2060_STATUS_STEREO 6:6 /* R-XVF */
#define NV_P2060_STATUS_STEREO_NOLOCK 0x00 /* R---V */
#define NV_P2060_STATUS_STEREO_LOCK 0x01 /* R---V */
#define NV_P2060_STATUS_RESERVED2 7:7 /* RWXVF */
#define NV_P2060_STATUS2 0x01 /* RW-1R */
#define NV_P2060_STATUS2_VAL 7:0 /* R-XVF */
#define NV_P2060_STATUS2_PORT0 0:0 /* RWIVF */
#define NV_P2060_STATUS2_PORT0_INPUT 0x00 /* RWI-V */
#define NV_P2060_STATUS2_PORT0_OUTPUT 0x01 /* RW--V */
#define NV_P2060_STATUS2_PORT1 1:1 /* RWIVF */
#define NV_P2060_STATUS2_PORT1_INPUT 0x00 /* RWI-V */
#define NV_P2060_STATUS2_PORT1_OUTPUT 0x01 /* RW--V */
#define NV_P2060_STATUS2_ETHER0_DETECTED 2:2 /* RWIVF */
#define NV_P2060_STATUS2_ETHER0_DETECTED_FALSE 0x00 /* RWI-V */
#define NV_P2060_STATUS2_ETHER0_DETECTED_TRUE 0x01 /* R---V */
#define NV_P2060_STATUS2_ETHER1_DETECTED 3:3 /* RWIVF */
#define NV_P2060_STATUS2_ETHER1_DETECTED_FALSE 0x00 /* RWI-V */
#define NV_P2060_STATUS2_ETHER1_DETECTED_TRUE 0x01 /* R---V */
#define NV_P2060_STATUS2_HS_DETECT 5:4 /* RWXVF */
#define NV_P2060_STATUS2_HS_DETECT_NONE 0x00 /* R---V */
#define NV_P2060_STATUS2_HS_DETECT_TTL 0x01 /* R---V */
#define NV_P2060_STATUS2_HS_DETECT_COMPOSITE 0x02 /* R---V */
#define NV_P2060_STATUS2_HS_DETECT_NOT_IN_USE 0x03 /* R---V */
#define NV_P2060_STATUS2_GPU_PORT 7:6 /* R-XVF */
#define NV_P2060_STATUS2_GPU_PORT_CONN0 0x00 /* R---V */
#define NV_P2060_STATUS2_GPU_PORT_CONN1 0x01 /* R---V */
#define NV_P2060_STATUS2_GPU_PORT_CONN2 0x02 /* R---V */
#define NV_P2060_STATUS2_GPU_PORT_CONN3 0x03 /* R---V */
#define NV_P2060_STATUS3 0x02 /* RW-1R */
#define NV_P2060_STATUS3_VAL 7:0 /* R-XVF */
#define NV_P2060_STATUS3_RESERVED 0:0 /* R-XVF */
#define NV_P2060_STATUS3_LB_INT_FAIL 1:1 /* R-XVF */
#define NV_P2060_STATUS3_LB_INT_FAIL_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_LB_INT_FAIL_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS3_LB_VTGRST_FAIL 2:2 /* R-XVF */
#define NV_P2060_STATUS3_LB_VTGRST_FAIL_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_LB_VTGRST_FAIL_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS3_LB_GSWPRDY_FAIL 3:3 /* R-XVF */
#define NV_P2060_STATUS3_LB_GSWPRDY_FAIL_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_LB_GSWPRDY_FAIL_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS3_LB_SYNC_FAIL 4:4 /* RWXVF */
#define NV_P2060_STATUS3_LB_SYNC_FAIL_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_LB_SYNC_FAIL_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS3_LB_STEREO_FAIL 5:5 /* RWXVF */
#define NV_P2060_STATUS3_LB_STEREO_FAIL_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_LB_STEREO_FAIL_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS3_LB_SWPRDY_FAIL 6:6 /* RWXVF */
#define NV_P2060_STATUS3_LB_SWPRDY_FAIL_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_LB_SWPRDY_FAIL_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS3_GENLOCKED 7:7 /* RWXVF */
#define NV_P2060_STATUS3_GENLOCKED_FALSE 0x00 /* RW--V */
#define NV_P2060_STATUS3_GENLOCKED_TRUE 0x01 /* RW--V */
#define NV_P2060_STATUS4 0x13 /* RW-1R */
#define NV_P2060_STATUS4_VAL 7:0 /* R-XVF */
#define NV_P2060_STATUS4_INT_GROUP 7:6 /* R-XVF */
#define NV_P2060_STATUS4_INT_GROUP_LOSS 0x00 /* R-XVF */
#define NV_P2060_STATUS4_INT_GROUP_GAIN 0x01 /* R-XVF */
#define NV_P2060_STATUS4_INT_GROUP_MISC 0x02 /* R-XVF */
#define NV_P2060_STATUS4_SYNC 0:0 /* R---V */
#define NV_P2060_STATUS4_STEREO 1:1 /* R---V */
#define NV_P2060_STATUS4_HS 2:2 /* R---V */
#define NV_P2060_STATUS4_RJ45 3:3 /* R---V */
#define NV_P2060_STATUS4_RESERVED_GRP01 5:4 /* R---V */
//Value 1 in bits 0-5 indicate loss and gain depending on interrupt group 00/01 (bit 6-7)
#define NV_P2060_STATUS4_FRM_CNT_MATCH_INT 0:0 /* R-XVF */
#define NV_P2060_STATUS4_FRM_CNT_MATCH_INT_CLEAR 0x00 /* R---V */
#define NV_P2060_STATUS4_FRM_CNT_MATCH_INT_PENDING 0x01 /* R---V */
#define NV_P2060_STATUS4_SWAPRDY_INT 1:1 /* R-XVF */
#define NV_P2060_STATUS4_SWAPRDY_INT_CLEAR 0x00 /* R---V */
#define NV_P2060_STATUS4_SWAPRDY_INT_PENDING 0x01 /* R---V */
#define NV_P2060_STATUS4_ERROR_INT 2:2 /* R-XVF */
#define NV_P2060_STATUS4_ERROR_INT_CLEAR 0x00 /* R---V */
#define NV_P2060_STATUS4_ERROR_INT_PENDING 0x01 /* R---V */
#define NV_P2060_STATUS4_FRM_CNT_ROLLOVER_INT 3:3 /* R-XVF */
#define NV_P2060_STATUS4_FRM_CNT_ROLLOVER_INT_CLEAR 0x00 /* R---V */
#define NV_P2060_STATUS4_FRM_CNT_ROLLOVER_INT_PENDING 0x01 /* R---V */
#define NV_P2060_STATUS4_RESERVED_GRP10 5:4 /* R---V */
//Value 1 in bits 0-5 indicate interrupt pending depending on interrupt group 10 (bit 6-7)
#define NV_P2060_CONTROL 0x03 /* RW-1R */
#define NV_P2060_CONTROL_I_AM 0:0 /* RWXVF */
#define NV_P2060_CONTROL_I_AM_SLAVE 0x00 /* RWI-V */
#define NV_P2060_CONTROL_I_AM_MASTER 0x01 /* RWI-V */
#define NV_P2060_CONTROL_SYNC_POLARITY 2:1 /* RWXVF */
#define NV_P2060_CONTROL_SYNC_POLARITY_RISING_EDGE 0x00 /* RW--V */
#define NV_P2060_CONTROL_SYNC_POLARITY_FALLING_EDGE 0x01 /* RW--V */
#define NV_P2060_CONTROL_SYNC_POLARITY_BOTH 0x02 /* RW--V */
#define NV_P2060_CONTROL_TEST_MODE 3:3 /* RWXVF */
#define NV_P2060_CONTROL_TEST_MODE_OFF 0x00 /* RW--V */
#define NV_P2060_CONTROL_TEST_MODE_ON 0x01 /* RW--V */
#define NV_P2060_CONTROL_SYNC_SRC 5:4 /* RWXVF */
#define NV_P2060_CONTROL_SYNC_SRC_CONN0 0x00 /* RW--V */
#define NV_P2060_CONTROL_SYNC_SRC_CONN1 0x01 /* RW--V */
#define NV_P2060_CONTROL_SYNC_SRC_CONN2 0x02 /* RW--V */
#define NV_P2060_CONTROL_SYNC_SRC_CONN3 0x03 /* RW--V */
#define NV_P2060_CONTROL_INTERLACE_MODE 6:6 /* RWXVF */
#define NV_P2060_CONTROL_INTERLACE_MODE_FALSE 0x00 /* RW--V */
#define NV_P2060_CONTROL_INTERLACE_MODE_TRUE 0x01 /* RW--V */
#define NV_P2060_CONTROL_SYNC_SELECT 7:7 /* RWXVF */
#define NV_P2060_CONTROL_SYNC_SELECT_INTERNAL 0x00 /* RW--V */
#define NV_P2060_CONTROL_SYNC_SELECT_HOUSE 0x01 /* RW--V */
#define NV_P2060_CONTROL2 0x04 /* RW-1R */
#define NV_P2060_CONTROL2_LAMUX 1:0 /* RWXVF */
#define NV_P2060_CONTROL2_LAMUX_0 0x00 /* RWI-V */
#define NV_P2060_CONTROL2_FRAMERATE_RPT 3:2 /* RWXVF */
#define NV_P2060_CONTROL2_FRAMERATE_RPT_LIVE 0x00 /* RW--V */
#define NV_P2060_CONTROL2_FRAMERATE_RPT_MIN 0x02 /* RW--V */
#define NV_P2060_CONTROL2_FRAMERATE_RPT_MAX 0x03 /* RW--V */
#define NV_P2060_CONTROL2_RESET 4:4 /* RWXVF */
#define NV_P2060_CONTROL2_RESET_FALSE 0x00 /* RW--V */
#define NV_P2060_CONTROL2_RESET_TRUE 0x01 /* RW--V */
#define NV_P2060_CONTROL2_SWAP_READY 5:5 /* RWXVF */
#define NV_P2060_CONTROL2_SWAP_READY_DISABLE 0x00 /* RW--V */
#define NV_P2060_CONTROL2_SWAP_READY_ENABLE 0x01 /* RW--V */
#define NV_P2060_CONTROL2_RESERVED 6:6 /* RWXVF */
#define NV_P2060_CONTROL2_LOOPBACK_MODE 7:7 /* RWXVF */
#define NV_P2060_CONTROL2_LOOPBACK_MODE_OFF 0x00 /* RW--V */
#define NV_P2060_CONTROL2_LOOPBACK_MODE_ON 0x01 /* RW--V */
#define NV_P2060_CONTROL3 0x05 /* RW-1R */
#define NV_P2060_CONTROL3_INTERRUPT 6:0 /* RWXVF */
#define NV_P2060_CONTROL3_INTERRUPT_DISABLE 0x00 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_STEREO_CHG 0x01 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_ERROR 0x02 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_FRAME_MATCH 0x04 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_HS_CHG 0x08 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_SYNC_CHG 0x10 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_RJ45_CHG 0x20 /* RW--V */
#define NV_P2060_CONTROL3_INTERRUPT_ON_ALL 0x7f /* RW--V */
#define NV_P2060_CONTROL3_RESYNC 7:7 /* RWXVF */
#define NV_P2060_CONTROL3_RESYNC_OFF 0x00 /* RW--V */
#define NV_P2060_CONTROL3_RESYNC_ON 0x01 /* RW--V */
#define NV_P2060_CONTROL4 0x06 /* RW-1R */
#define NV_P2060_CONTROL4_SWPRDYINT_DELAY 2:0 /* RWXVF */
#define NV_P2060_CONTROL4_STEREO_LOCK_MODE 3:3 /* RWXVF */
#define NV_P2060_CONTROL4_STEREO_LOCK_MODE_OFF 0x00 /* RW--V */
#define NV_P2060_CONTROL4_STEREO_LOCK_MODE_ON 0x01 /* RW--V */
#define NV_P2060_CONTROL4_EXT_STEREO_SYNC 4:4 /* RWXVF */
#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_OFF 0x00 /* RW--V */
#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_ON 0x01 /* RW--V */
#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_POL 5:5 /* RWXVF */
#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_POL_LOW 0x00 /* RW--V */
#define NV_P2060_CONTROL4_EXT_STEREO_SYNC_POL_HI 0x01 /* RW--V */
#define NV_P2060_CONTROL4_RESERVED2 7:6 /* RWXVF */
#define NV_P2060_FPGA 0x07 /* R--1R */
#define NV_P2060_FPGA_REV 3:0 /* R-XVF */
#define NV_P2060_FPGA_ID 7:4 /* R-XVF */
#define NV_P2060_FPGA_ID_0 0x00 /* R---V */
#define NV_P2060_FPGA_ID_5 0x05 /* R---V */
#define NV_P2061_FPGA_ID 7:4 /* R-XVF */
#define NV_P2061_FPGA_ID_4 0x04 /* R---V */
#define NV_P2060_SYNC_SKEW_LOW 0x08 /* RW-1R */
#define NV_P2060_SYNC_SKEW_LOW_VAL 7:0 /* RWIVF */
#define NV_P2060_SYNC_SKEW_LOW_VAL_0 0x00 /* RWI-V */
#define NV_P2060_SYNC_SKEW_HIGH 0x09 /* RW-1R */
#define NV_P2060_SYNC_SKEW_HIGH_VAL 7:0 /* RWIVF */
#define NV_P2060_SYNC_SKEW_HIGH_VAL_0 0x00 /* RWI-V */
#define NV_P2060_SYNC_SKEW_UPPER 0x35 /* RW-1R */
#define NV_P2060_SYNC_SKEW_UPPER_VAL 7:0 /* RWIVF */
#define NV_P2060_SYNC_SKEW_UPPER_VAL_0 0x00 /* RWI-V */
#define NV_P2060_START_DELAY_LOW 0x0A /* RW-1R */
#define NV_P2060_START_DELAY_LOW_VAL 7:0 /* RWIVF */
#define NV_P2060_START_DELAY_LOW_VAL_0 0x00 /* RWI-V */
#define NV_P2060_START_DELAY_HIGH 0x0B /* RW-1R */
#define NV_P2060_START_DELAY_HIGH_VAL 7:0 /* RWIVF */
#define NV_P2060_START_DELAY_HIGH_VAL_0 0x00 /* RWI-V */
#define NV_P2060_NSYNC 0x0C /* RW-1R */
#define NV_P2060_NSYNC_FL 2:0 /* RWIVF */
#define NV_P2060_NSYNC_GPU 6:4 /* RWIVF */
#define NV_P2060_NSYNC_ALL 7:0 /* RWIVF */
#define NV_P2060_FRAMECNTR_LOW 0x0D /* R--1R */
#define NV_P2060_FRAMECNTR_LOW_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAMECNTR_LOW_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAMECNTR_MID 0x0E /* R--1R */
#define NV_P2060_FRAMECNTR_MID_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAMECNTR_MID_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAMECNTR_HIGH 0x0F /* R--1R */
#define NV_P2060_FRAMECNTR_HIGH_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAMECNTR_HIGH_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAMERATE_LOW 0x10 /* R--1R */
#define NV_P2060_FRAMERATE_LOW_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAMERATE_LOW_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAMERATE_MID 0x11 /* R--1R */
#define NV_P2060_FRAMERATE_MID_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAMERATE_MID_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAMERATE_HIGH 0x12 /* R--1R */
#define NV_P2060_FRAMERATE_HIGH_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAMERATE_HIGH_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FPGA_EXREV 0x17 /* R--1R */
#define NV_P2060_FPGA_EXREV_VAL 7:0 /* RWIVF */
#define NV_P2060_FPGA_EXREV_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FPGA_ASGN_ID_0 0x18 /* R--1R */
#define NV_P2060_FPGA_ASGN_ID_0_VAL 7:0 /* RWIVF */
#define NV_P2060_FPGA_ASGN_ID_1 0x19 /* R--1R */
#define NV_P2060_FPGA_ASGN_ID_1_VAL 7:0 /* RWIVF */
#define NV_P2060_FPGA_ASGN_ID_2 0x1A /* R--1R */
#define NV_P2060_FPGA_ASGN_ID_2_VAL 7:0 /* RWIVF */
#define NV_P2060_FPGA_ASGN_ID_3 0x1B /* R--1R */
#define NV_P2060_FPGA_ASGN_ID_3_VAL 7:0 /* RWIVF */
#define NV_P2060_FPGA_ASGN_ID(i) (0x18 + i)
#define NV_P2060_FRAME_CMPR_LOW 0x1D /* R--1R */
#define NV_P2060_FRAME_CMPR_LOW_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAME_CMPR_LOW_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAME_CMPR_MID 0x1E /* R--1R */
#define NV_P2060_FRAME_CMPR_MID_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAME_CMPR_MID_VAL_0 0x00 /* RWI-V */
#define NV_P2060_FRAME_CMPR_HIGH 0x1F /* R--1R */
#define NV_P2060_FRAME_CMPR_HIGH_VAL 7:0 /* RWIVF */
#define NV_P2060_FRAME_CMPR_HIGH_VAL_0 0x00 /* RWI-V */
#define NV_P2060_HS_FRAMERATE_LOW 0x20 /* R--1R */
#define NV_P2060_HS_FRAMERATE_LOW_VAL 7:0 /* RWIVF */
#define NV_P2060_HS_FRAMERATE_LOW_VAL_0 0x00 /* RWI-V */
#define NV_P2060_HS_FRAMERATE_MID 0x21 /* R--1R */
#define NV_P2060_HS_FRAMERATE_MID_VAL 7:0 /* RWIVF */
#define NV_P2060_HS_FRAMERATE_MID_VAL_0 0x00 /* RWI-V */
#define NV_P2060_HS_FRAMERATE_HIGH 0x22 /* R--1R */
#define NV_P2060_HS_FRAMERATE_HIGH_VAL 7:0 /* RWIVF */
#define NV_P2060_HS_FRAMERATE_HIGH_VAL_0 0x00 /* RWI-V */
#define NV_P2060_MOSAIC_MODE 0x23 /* RW-1R */
#define NV_P2060_MOSAIC_MODE_TS 1:0 /* RWIVF */
#define NV_P2060_MOSAIC_MODE_TS_CONN0 0x00 /* R---V */
#define NV_P2060_MOSAIC_MODE_TS_CONN1 0x01 /* RW--V */
#define NV_P2060_MOSAIC_MODE_TS_CONN2 0x02 /* RW--V */
#define NV_P2060_MOSAIC_MODE_TS_CONN3 0x03 /* RW--V */
#define NV_P2060_MOSAIC_MODE_GROUP 2:2 /* RWIVF */
#define NV_P2060_MOSAIC_MODE_GROUP_ZERO 0x00 /* RW--V */
#define NV_P2060_MOSAIC_MODE_GROUP_ONE 0x01 /* RW--V */
#define NV_P2060_MOSAIC_MODE_ENABLE 3:3 /* RWIVF */
#define NV_P2060_MOSAIC_MODE_ENABLE_FALSE 0x00 /* RW--V */
#define NV_P2060_MOSAIC_MODE_ENABLE_TRUE 0x01 /* RW--V */
#define NV_P2060_MOSAIC_MODE_RESERVED 7:4 /* RWIVF */
#define NV_P2060_MULTIPLIER_DIVIDER 0x2F /* RW-1R */
#define NV_P2060_MULTIPLIER_DIVIDER_VALUE_MINUS_ONE 2:0 /* RWIVF */
#define NV_P2060_MULTIPLIER_DIVIDER_VALUE_MINUS_ONE_MAX 0x7
#define NV_P2060_MULTIPLIER_DIVIDER_MODE 7:7 /* RWIVF */
#define NV_P2060_MULTIPLIER_DIVIDER_MODE_MULTIPLY 0x0 /* RWIVF */
#define NV_P2060_MULTIPLIER_DIVIDER_MODE_DIVIDE 0x1 /* RWIVF */
#endif //DEV_P2060_H

37
src/nvidia/inc/kernel/gpu/external_device/dev_p2061.h Normal file
View File

@@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef DEV_P2061_H
#define DEV_P2061_H
#define NV_P2061_CONTROL4 0x06 /* RW-1R */
#define NV_P2061_CONTROL4_HOUSE_SYNC_MODE 6:6 /* RWXVF */
#define NV_P2061_CONTROL4_HOUSE_SYNC_MODE_INPUT 0x0 /* RW--V */
#define NV_P2061_CONTROL4_HOUSE_SYNC_MODE_OUTPUT 0x1 /* RW--V */
#define NV_P2061_STATUS6 0x2E /* RW-1R */
#define NV_P2061_STATUS6_INT_PORT_DIRECTION 7:7 /* RWXVF */
#define NV_P2061_STATUS6_INT_PORT_DIRECTION_INPUT 0 /* RWXVF */
#define NV_P2061_STATUS6_INT_PORT_DIRECTION_OUTPUT 1 /* RWXVF */
#endif //DEV_P2061_H

5
src/nvidia/inc/kernel/gpu/external_device/external_device.h
View File

@@ -26,7 +26,7 @@
/* ------------------------ Includes --------------------------------------- */
#include "Nvcm.h"
#include "sweng/dispsw.h"
#include "gpu/disp/dispsw.h"
/* ------------------------ Types definitions ------------------------------ */
typedef struct DACEXTERNALDEVICE DACEXTERNALDEVICE, *PDACEXTERNALDEVICE;
@@ -103,6 +103,8 @@ struct DACEXTERNALDEVICE
struct {
NvBool Scheduled;
NvU32 TimeOut;
TMR_EVENT *pTimerEvent;
} WatchdogControl;
};
@@ -126,7 +128,6 @@ NV_STATUS readregu008_extdeviceTargeted(OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8
void extdevDestroy (OBJGPU *);
NV_STATUS extdevScheduleWatchdog(OBJGPU *, PDACEXTERNALDEVICE);
NV_STATUS extdevCancelWatchdog (OBJGPU *, PDACEXTERNALDEVICE);
NV_STATUS extdevServiceWatchdog (OBJGPU *, struct OBJTMR *, void *); // OBJTMR routine signature (TIMERPROC).
void extdevGsyncService(OBJGPU *, NvU8, NvU8, NvU8, NvBool);
#endif

10
src/nvidia/inc/kernel/gpu/falcon/falcon_common.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -63,4 +63,12 @@
*/
#define FLCN_RESET_PROPAGATION_DELAY_COUNT 10
/*!
* Used by FALCON_DMATRFCMD polling functions to wait for _FULL==FALSE or _IDLE==TRUE
*/
typedef enum {
FLCN_DMA_POLL_QUEUE_NOT_FULL = 0,
FLCN_DMA_POLL_ENGINE_IDLE = 1
} FlcnDmaPollMode;
#endif // FALCON_COMMON_H

3
src/nvidia/inc/kernel/gpu/gpu_device_mapping.h
View File

@@ -23,6 +23,7 @@
#ifndef _GPU_DEVICE_MAPPING_H_
#define _GPU_DEVICE_MAPPING_H_
// Defines the enum type DEVICE_INDEX used for identifying the device type being accessed
typedef enum
{
@@ -45,7 +46,7 @@ typedef enum
{
SOC_DEV_MAPPING_DISP = 0,
SOC_DEV_MAPPING_DPAUX0,
SOC_DEV_MAPPING_DPAUX1, // Update NV_MAX_SOC_DPAUX_NUM_DEVICES if adding new DPAUX mappings
SOC_DEV_MAPPING_DPAUX1,
SOC_DEV_MAPPING_HDACODEC,
SOC_DEV_MAPPING_MIPICAL,
SOC_DEV_MAPPING_MAX

160
src/nvidia/inc/kernel/gpu/gpu_engine_type.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,71 +31,93 @@
typedef enum
{
RM_ENGINE_TYPE_NULL = (0x00000000),
RM_ENGINE_TYPE_GR0 = (0x00000001),
RM_ENGINE_TYPE_GR1 = (0x00000002),
RM_ENGINE_TYPE_GR2 = (0x00000003),
RM_ENGINE_TYPE_GR3 = (0x00000004),
RM_ENGINE_TYPE_GR4 = (0x00000005),
RM_ENGINE_TYPE_GR5 = (0x00000006),
RM_ENGINE_TYPE_GR6 = (0x00000007),
RM_ENGINE_TYPE_GR7 = (0x00000008),
RM_ENGINE_TYPE_COPY0 = (0x00000009),
RM_ENGINE_TYPE_COPY1 = (0x0000000a),
RM_ENGINE_TYPE_COPY2 = (0x0000000b),
RM_ENGINE_TYPE_COPY3 = (0x0000000c),
RM_ENGINE_TYPE_COPY4 = (0x0000000d),
RM_ENGINE_TYPE_COPY5 = (0x0000000e),
RM_ENGINE_TYPE_COPY6 = (0x0000000f),
RM_ENGINE_TYPE_COPY7 = (0x00000010),
RM_ENGINE_TYPE_COPY8 = (0x00000011),
RM_ENGINE_TYPE_COPY9 = (0x00000012),
RM_ENGINE_TYPE_RESERVED13 = (0x00000013),
RM_ENGINE_TYPE_RESERVED14 = (0x00000014),
RM_ENGINE_TYPE_RESERVED15 = (0x00000015),
RM_ENGINE_TYPE_RESERVED16 = (0x00000016),
RM_ENGINE_TYPE_RESERVED17 = (0x00000017),
RM_ENGINE_TYPE_RESERVED18 = (0x00000018),
RM_ENGINE_TYPE_RESERVED19 = (0x00000019),
RM_ENGINE_TYPE_RESERVED1a = (0x0000001a),
RM_ENGINE_TYPE_RESERVED1b = (0x0000001b),
RM_ENGINE_TYPE_RESERVED1c = (0x0000001c),
RM_ENGINE_TYPE_NVDEC0 = (0x0000001d),
RM_ENGINE_TYPE_NVDEC1 = (0x0000001e),
RM_ENGINE_TYPE_NVDEC2 = (0x0000001f),
RM_ENGINE_TYPE_NVDEC3 = (0x00000020),
RM_ENGINE_TYPE_NVDEC4 = (0x00000021),
RM_ENGINE_TYPE_NVDEC5 = (0x00000022),
RM_ENGINE_TYPE_NVDEC6 = (0x00000023),
RM_ENGINE_TYPE_NVDEC7 = (0x00000024),
RM_ENGINE_TYPE_NVENC0 = (0x00000025),
RM_ENGINE_TYPE_NVENC1 = (0x00000026),
RM_ENGINE_TYPE_NVENC2 = (0x00000027),
RM_ENGINE_TYPE_RESERVED28 = (0x00000028),
RM_ENGINE_TYPE_VP = (0x00000029),
RM_ENGINE_TYPE_ME = (0x0000002a),
RM_ENGINE_TYPE_PPP = (0x0000002b),
RM_ENGINE_TYPE_MPEG = (0x0000002c),
RM_ENGINE_TYPE_SW = (0x0000002d),
RM_ENGINE_TYPE_TSEC = (0x0000002e),
RM_ENGINE_TYPE_VIC = (0x0000002f),
RM_ENGINE_TYPE_MP = (0x00000030),
RM_ENGINE_TYPE_SEC2 = (0x00000031),
RM_ENGINE_TYPE_HOST = (0x00000032),
RM_ENGINE_TYPE_DPU = (0x00000033),
RM_ENGINE_TYPE_PMU = (0x00000034),
RM_ENGINE_TYPE_FBFLCN = (0x00000035),
RM_ENGINE_TYPE_NVJPEG0 = (0x00000036),
RM_ENGINE_TYPE_NVJPEG1 = (0x00000037),
RM_ENGINE_TYPE_NVJPEG2 = (0x00000038),
RM_ENGINE_TYPE_NVJPEG3 = (0x00000039),
RM_ENGINE_TYPE_NVJPEG4 = (0x0000003a),
RM_ENGINE_TYPE_NVJPEG5 = (0x0000003b),
RM_ENGINE_TYPE_NVJPEG6 = (0x0000003c),
RM_ENGINE_TYPE_NVJPEG7 = (0x0000003d),
RM_ENGINE_TYPE_OFA0 = (0x0000003e),
RM_ENGINE_TYPE_RESERVED3f = (0x0000003f),
RM_ENGINE_TYPE_LAST = (0x00000040),
RM_ENGINE_TYPE_NULL = (0x00000000),
RM_ENGINE_TYPE_GR0 = (0x00000001),
RM_ENGINE_TYPE_GR1 = (0x00000002),
RM_ENGINE_TYPE_GR2 = (0x00000003),
RM_ENGINE_TYPE_GR3 = (0x00000004),
RM_ENGINE_TYPE_GR4 = (0x00000005),
RM_ENGINE_TYPE_GR5 = (0x00000006),
RM_ENGINE_TYPE_GR6 = (0x00000007),
RM_ENGINE_TYPE_GR7 = (0x00000008),
RM_ENGINE_TYPE_COPY0 = (0x00000009),
RM_ENGINE_TYPE_COPY1 = (0x0000000a),
RM_ENGINE_TYPE_COPY2 = (0x0000000b),
RM_ENGINE_TYPE_COPY3 = (0x0000000c),
RM_ENGINE_TYPE_COPY4 = (0x0000000d),
RM_ENGINE_TYPE_COPY5 = (0x0000000e),
RM_ENGINE_TYPE_COPY6 = (0x0000000f),
RM_ENGINE_TYPE_COPY7 = (0x00000010),
RM_ENGINE_TYPE_COPY8 = (0x00000011),
RM_ENGINE_TYPE_COPY9 = (0x00000012),
// removal tracking bug: 3748354
RM_ENGINE_TYPE_COPY10 = (0x00000013),
RM_ENGINE_TYPE_COPY11 = (0x00000014),
RM_ENGINE_TYPE_COPY12 = (0x00000015),
RM_ENGINE_TYPE_COPY13 = (0x00000016),
RM_ENGINE_TYPE_COPY14 = (0x00000017),
RM_ENGINE_TYPE_COPY15 = (0x00000018),
RM_ENGINE_TYPE_COPY16 = (0x00000019),
RM_ENGINE_TYPE_COPY17 = (0x0000001a),
RM_ENGINE_TYPE_COPY18 = (0x0000001b),
RM_ENGINE_TYPE_COPY19 = (0x0000001c),
RM_ENGINE_TYPE_NVDEC0 = (0x0000001d),
RM_ENGINE_TYPE_NVDEC1 = (0x0000001e),
RM_ENGINE_TYPE_NVDEC2 = (0x0000001f),
RM_ENGINE_TYPE_NVDEC3 = (0x00000020),
RM_ENGINE_TYPE_NVDEC4 = (0x00000021),
RM_ENGINE_TYPE_NVDEC5 = (0x00000022),
RM_ENGINE_TYPE_NVDEC6 = (0x00000023),
RM_ENGINE_TYPE_NVDEC7 = (0x00000024),
RM_ENGINE_TYPE_NVENC0 = (0x00000025),
RM_ENGINE_TYPE_NVENC1 = (0x00000026),
RM_ENGINE_TYPE_NVENC2 = (0x00000027),
RM_ENGINE_TYPE_RESERVED28 = (0x00000028),
RM_ENGINE_TYPE_VP = (0x00000029),
RM_ENGINE_TYPE_ME = (0x0000002a),
RM_ENGINE_TYPE_PPP = (0x0000002b),
RM_ENGINE_TYPE_MPEG = (0x0000002c),
RM_ENGINE_TYPE_SW = (0x0000002d),
RM_ENGINE_TYPE_TSEC = (0x0000002e),
RM_ENGINE_TYPE_VIC = (0x0000002f),
RM_ENGINE_TYPE_MP = (0x00000030),
RM_ENGINE_TYPE_SEC2 = (0x00000031),
RM_ENGINE_TYPE_HOST = (0x00000032),
RM_ENGINE_TYPE_DPU = (0x00000033),
RM_ENGINE_TYPE_PMU = (0x00000034),
RM_ENGINE_TYPE_FBFLCN = (0x00000035),
RM_ENGINE_TYPE_NVJPEG0 = (0x00000036),
RM_ENGINE_TYPE_NVJPEG1 = (0x00000037),
RM_ENGINE_TYPE_NVJPEG2 = (0x00000038),
RM_ENGINE_TYPE_NVJPEG3 = (0x00000039),
RM_ENGINE_TYPE_NVJPEG4 = (0x0000003a),
RM_ENGINE_TYPE_NVJPEG5 = (0x0000003b),
RM_ENGINE_TYPE_NVJPEG6 = (0x0000003c),
RM_ENGINE_TYPE_NVJPEG7 = (0x0000003d),
RM_ENGINE_TYPE_OFA0 = (0x0000003e),
// removal tracking bug: 3748354
RM_ENGINE_TYPE_OFA1 = (0x0000003f),
RM_ENGINE_TYPE_RESERVED40 = (0x00000040),
RM_ENGINE_TYPE_RESERVED41 = (0x00000041),
RM_ENGINE_TYPE_RESERVED42 = (0x00000042),
RM_ENGINE_TYPE_RESERVED43 = (0x00000043),
RM_ENGINE_TYPE_RESERVED44 = (0x00000044),
RM_ENGINE_TYPE_RESERVED45 = (0x00000045),
RM_ENGINE_TYPE_RESERVED46 = (0x00000046),
RM_ENGINE_TYPE_RESERVED47 = (0x00000047),
RM_ENGINE_TYPE_RESERVED48 = (0x00000048),
RM_ENGINE_TYPE_RESERVED49 = (0x00000049),
RM_ENGINE_TYPE_RESERVED4a = (0x0000004a),
RM_ENGINE_TYPE_RESERVED4b = (0x0000004b),
RM_ENGINE_TYPE_RESERVED4c = (0x0000004c),
RM_ENGINE_TYPE_RESERVED4d = (0x0000004d),
RM_ENGINE_TYPE_RESERVED4e = (0x0000004e),
RM_ENGINE_TYPE_RESERVED4f = (0x0000004f),
RM_ENGINE_TYPE_RESERVED50 = (0x00000050),
RM_ENGINE_TYPE_RESERVED51 = (0x00000051),
RM_ENGINE_TYPE_RESERVED52 = (0x00000052),
RM_ENGINE_TYPE_RESERVED53 = (0x00000053),
RM_ENGINE_TYPE_LAST = (0x00000054),
} RM_ENGINE_TYPE;
//
@@ -108,11 +130,13 @@ typedef enum
#define RM_ENGINE_TYPE_CIPHER RM_ENGINE_TYPE_TSEC
#define RM_ENGINE_TYPE_NVJPG RM_ENGINE_TYPE_NVJPEG0
#define RM_ENGINE_TYPE_COPY_SIZE 10
// removal tracking bug: 3748354
#define RM_ENGINE_TYPE_COPY_SIZE 20
#define RM_ENGINE_TYPE_NVENC_SIZE 3
#define RM_ENGINE_TYPE_NVJPEG_SIZE 8
#define RM_ENGINE_TYPE_NVDEC_SIZE 8
#define RM_ENGINE_TYPE_OFA_SIZE 1
// removal tracking bug: 3748354
#define RM_ENGINE_TYPE_OFA_SIZE 2
#define RM_ENGINE_TYPE_GR_SIZE 8
// Indexed engines

1
src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h
View File

@@ -55,6 +55,7 @@ NV_STATUS gpuFabricProbeGetGpaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64
NV_STATUS gpuFabricProbeGetGpaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pGpaAddressRange);
NV_STATUS gpuFabricProbeGetFlaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddress);
NV_STATUS gpuFabricProbeGetFlaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddressRange);
NV_STATUS gpuFabricProbeGetEgmGpaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pEgmGpaAddress);
NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *numProbes);
NV_STATUS gpuFabricProbeGetFabricCliqueId(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pFabricCliqueId);
NV_STATUS gpuFabricProbeGetFabricHealthStatus(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pFabricHealthStatusMask);

22
src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,7 +28,7 @@
#include "gpu/mem_mgr/mem_desc.h"
#include "class/cl00de.h"
#include "tmr.h"
#include "gpu/timer/tmr.h"
// ****************************************************************************
// Type definitions
@@ -52,15 +52,23 @@ typedef struct GpuSharedDataMap {
} GpuSharedDataMap;
/**
* Start data write, returns data struct to write into
* Start data write, updates seq to indicate write in progress and returns data struct to write into
*
* After updating data in the returned NV00DE_SHARED_DATA struct,
* call gpushareddataWriteFinish to push the new data into the user mapping
* call gpushareddataWriteFinish to mark data as valid.
*/
NV00DE_SHARED_DATA * gpushareddataWriteStart(OBJGPU *pGpu);
NV00DE_SHARED_DATA * gpushareddataWriteStart_INTERNAL(OBJGPU *pGpu, NvU64 offset);
// Finish data write, pushes data cached by above into mapped data
void gpushareddataWriteFinish(OBJGPU *pGpu);
#define gpushareddataWriteStart(pGpu, field) \
&(gpushareddataWriteStart_INTERNAL(pGpu, NV_OFFSETOF(NV00DE_SHARED_DATA, field))->field)
/**
* Finish data write, updates seq to indicate write is finished and data is valid.
*/
void gpushareddataWriteFinish_INTERNAL(OBJGPU *pGpu, NvU64 offset);
#define gpushareddataWriteFinish(pGpu, field) \
gpushareddataWriteFinish_INTERNAL(pGpu, NV_OFFSETOF(NV00DE_SHARED_DATA, field))
#endif /* GPU_SHARED_DATA_MAP_H */

12
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
View File

@@ -117,13 +117,13 @@ typedef struct GspStaticConfigInfo_t
NvBool bIsTesla;
NvBool bIsMobile;
NvBool bIsGc6Rtd3Allowed;
NvBool bIsGc8Rtd3Allowed;
NvBool bIsGcOffRtd3Allowed;
NvBool bIsGcoffLegacyAllowed;
/* "Total Board Power" refers to power requirement of GPU,
* while in GC6 state. Majority of this power will be used
* to keep V-RAM active to preserve its content.
 * Some energy maybe consumed by Always-on components on GPU chip.
* to keep V-RAM active to preserve its content.
* Some energy maybe consumed by Always-on components on GPU chip.
* This power will be provided by 3.3v voltage rail.
*/
NvU16 RTD3GC6TotalBoardPower;
@@ -165,8 +165,9 @@ typedef struct GspStaticConfigInfo_t
NvBool bAtsSupported;
NvBool bIsGpuUefi;
NvBool bIsEfiInit;
EcidManufacturingInfo ecidInfo;
EcidManufacturingInfo ecidInfo[2];
} GspStaticConfigInfo;
// Pushed from CPU-RM to GSP-RM
@@ -187,6 +188,7 @@ typedef struct GspSystemInfo
NvU32 PCIDeviceID;
NvU32 PCISubDeviceID;
NvU32 PCIRevisionID;
NvU32 pcieAtomicsCplDeviceCapMask;
NvU8 oorArch;
NvU64 clPdbProperties;
NvU32 Chipset;
@@ -198,7 +200,6 @@ typedef struct GspSystemInfo
NvBool bUpstreamL1Unsupported;
NvBool bUpstreamL1PorSupported;
NvBool bUpstreamL1PorMobileOnly;
NvBool bSystemHasMux;
NvU8 upstreamAddressValid;
BUSINFO FHBBusInfo;
BUSINFO chipsetIDInfo;
@@ -211,6 +212,9 @@ typedef struct GspSystemInfo
NvBool isGridBuild;
NvU32 gridBuildCsp;
NvBool bPreserveVideoMemoryAllocations;
NvBool bTdrEventSupported;
NvBool bFeatureStretchVblankCapable;
NvBool bClockBoostSupported;
} GspSystemInfo;

24
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
View File

@@ -61,17 +61,17 @@
#define MC_ENGINE_IDX_CE7 22
#define MC_ENGINE_IDX_CE8 23
#define MC_ENGINE_IDX_CE9 24
#define MC_ENGINE_IDX_CE_MAX MC_ENGINE_IDX_CE9
#define MC_ENGINE_IDX_RESERVED25 25
#define MC_ENGINE_IDX_RESERVED26 26
#define MC_ENGINE_IDX_RESERVED27 27
#define MC_ENGINE_IDX_RESERVED28 28
#define MC_ENGINE_IDX_RESERVED29 29
#define MC_ENGINE_IDX_RESERVED30 30
#define MC_ENGINE_IDX_RESERVED31 31
#define MC_ENGINE_IDX_RESERVED32 32
#define MC_ENGINE_IDX_RESERVED33 33
#define MC_ENGINE_IDX_RESERVED34 34
#define MC_ENGINE_IDX_CE10 25
#define MC_ENGINE_IDX_CE11 26
#define MC_ENGINE_IDX_CE12 27
#define MC_ENGINE_IDX_CE13 28
#define MC_ENGINE_IDX_CE14 29
#define MC_ENGINE_IDX_CE15 30
#define MC_ENGINE_IDX_CE16 31
#define MC_ENGINE_IDX_CE17 32
#define MC_ENGINE_IDX_CE18 33
#define MC_ENGINE_IDX_CE19 34
#define MC_ENGINE_IDX_CE_MAX MC_ENGINE_IDX_CE19
#define MC_ENGINE_IDX_VIC 35
#define MC_ENGINE_IDX_ISOHUB 36
#define MC_ENGINE_IDX_VGPU 37
@@ -123,7 +123,7 @@
#define MC_ENGINE_IDX_XBAR 79
#define MC_ENGINE_IDX_ZPW 80
#define MC_ENGINE_IDX_OFA0 81
#define MC_ENGINE_IDX_RESERVED81 82
#define MC_ENGINE_IDX_OFA1 82
#define MC_ENGINE_IDX_TEGRA 83
#define MC_ENGINE_IDX_GR 84
#define MC_ENGINE_IDX_GR0 MC_ENGINE_IDX_GR

4
src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils_sizes.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,7 +33,7 @@
#define CE_MAX_BYTES_PER_LINE 0xffffffffULL
#define CE_METHOD_SIZE_PER_BLOCK 0x64
#define FAST_SCRUBBER_METHOD_SIZE_PER_BLOCK 0x78
#define FAST_SCRUBBER_METHOD_SIZE_PER_BLOCK 0x94
// number of bytes per sec2 method-stream (including host methods)
#define SEC2_METHOD_SIZE_PER_BLOCK 0x94

8
src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h
View File

@@ -49,6 +49,8 @@
#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A
#include "class/clc9b5.h" // BLACKWELL_DMA_COPY_A
#include "gpu/conf_compute/ccsl.h"
#include "nvctassert.h"
@@ -130,6 +132,12 @@ typedef struct
NV_ADDRESS_SPACE srcAddressSpace;
NvU32 dstCpuCacheAttrib;
NvU32 srcCpuCacheAttrib;
NvBool bSecureCopy; // The copy encrypts/decrypts protected memory
NvBool bEncrypt; // encrypt/decrypt
NvU64 authTagAddr;
NvU64 encryptIvAddr;
} CHANNEL_PB_INFO;
NV_STATUS channelSetupIDs(OBJCHANNEL *pChannel, OBJGPU *pGpu, NvBool bUseVasForCeCopy, NvBool bMIGInUse);

2
src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h
View File

@@ -99,7 +99,7 @@ typedef struct OBJMEMSCRUB {
struct OBJGPU *pGpu;
VGPU_GUEST_PMA_SCRUB_BUFFER_RING vgpuScrubBuffRing;
NvBool bVgpuScrubberEnabled;
} OBJMEMSCRUB, *POBJMEMSCRUB;
} OBJMEMSCRUB;
ct_assert(VGPU_GUEST_PMA_MAX_SCRUB_ITEMS == MAX_SCRUB_ITEMS);

6
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -58,7 +58,7 @@ extern "C" {
typedef struct OBJMEMSCRUB OBJMEMSCRUB;
typedef struct SCRUB_NODE SCRUB_NODE;
#define PMA_REGION_SIZE 64
#define PMA_REGION_SIZE 32
#define PMA_ADDR2FRAME(addr, base) (((addr) - (base)) >> PMA_PAGE_SHIFT)
#define PMA_FRAME2ADDR(frame, base) ((base) + ((frame) << PMA_PAGE_SHIFT))
@@ -189,9 +189,11 @@ typedef void (*pmaMapChangeBlockStateAttrib_t)(void *pMap, NvU64 frameNum, NvU6
typedef PMA_PAGESTATUS (*pmaMapRead_t)(void *pMap, NvU64 frameNum, NvBool readAttrib);
typedef NV_STATUS (*pmaMapScanContiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 stride, NvU32 strideStart,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
typedef NV_STATUS (*pmaMapScanDiscontiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 stride, NvU32 strideStart,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
typedef void (*pmaMapGetSize_t)(void *pMap, NvU64 *pBytesTotal);
typedef void (*pmaMapGetLargestFree_t)(void *pMap, NvU64 *pLargestFree);

6
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -179,7 +179,7 @@ PMA_PAGESTATUS pmaRegmapRead(void *pMap, NvU64 frameNum, NvBool readAttrib);
*/
NV_STATUS pmaRegmapScanContiguous(
void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, NvU64 stride, NvU32 strideStart,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
/*!
@@ -206,7 +206,7 @@ NV_STATUS pmaRegmapScanContiguous(
*/
NV_STATUS pmaRegmapScanDiscontiguous(
void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, NvU64 stride, NvU32 strideStart,
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
/*!

7
src/nvidia/inc/kernel/gpu/mem_mgr/rm_page_size.h
View File

@@ -55,6 +55,11 @@
#define RM_PAGE_SIZE_512M (1ULL << RM_PAGE_SHIFT_512M)
#define RM_PAGE_MASK_512M (RM_PAGE_SIZE_512M - 1)
// 256GB page size
#define RM_PAGE_SHIFT_256G 38
#define RM_PAGE_SIZE_256G (1ULL << RM_PAGE_SHIFT_256G)
#define RM_PAGE_MASK_256G (RM_PAGE_SHIFT_256G - 1)
//---------------------------------------------------------------------------
//
// Memory page attributes.
@@ -63,6 +68,7 @@
// Big pages can be of 64/128KB[Fermi/Kepler/Pascal]
// Huge page is 2 MB[Pascal+]
// 512MB page is Ampere+
// 256GB page is for Blackwell+
// Default page attribute lets driver decide the optimal page size
//
//---------------------------------------------------------------------------
@@ -73,6 +79,7 @@ typedef enum
RM_ATTR_PAGE_SIZE_BIG,
RM_ATTR_PAGE_SIZE_HUGE,
RM_ATTR_PAGE_SIZE_512MB,
RM_ATTR_PAGE_SIZE_256GB,
RM_ATTR_PAGE_SIZE_INVALID
}
RM_ATTR_PAGE_SIZE;

3
src/nvidia/inc/kernel/gpu/objsweng.h Normal file
View File

@@ -0,0 +1,3 @@
#include "g_objsweng_nvoc.h"

2
src/nvidia/inc/kernel/gpu/perf/kern_perf_boost.h
View File

@@ -26,7 +26,7 @@
/* ------------------------ Includes --------------------------------------- */
#include "gpu/gpu_resource.h"
#include "objtmr.h"
#include "gpu/timer/objtmr.h"
/* ------------------------ Macros ----------------------------------------- */
/*!

3
src/nvidia/inc/kernel/gpu/power/syncgpuboost.h Normal file
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@@ -0,0 +1,3 @@
#include "g_syncgpuboost_nvoc.h"

152
src/nvidia/inc/kernel/gpu/rpc/objrpc.h Normal file
View File

@@ -0,0 +1,152 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
// #ifndef NVOC
// #include "g_objrpc_nvoc.h"
// #endif
#ifndef _OBJRPC_H_
#define _OBJRPC_H_
#include "vgpu/rpc_headers.h"
#include "diagnostics/nv_debug_dump.h"
#include "ctrl/ctrl2080/ctrl2080event.h" // rmcontrol params (from hal)
#include "ctrl/ctrl2080/ctrl2080gpu.h" // rmcontrol params (from hal)
#include "ctrl/ctrl2080/ctrl2080rc.h" // rmcontrol params (from hal)
#include "ctrl/ctrl2080/ctrl2080perf.h" // rmcontrol params (from hal)
#include "ctrl/ctrl0080/ctrl0080fb.h" // rmcontrol params (from hal)
#include "ctrl/ctrl0080/ctrl0080dma.h" // rmcontrol params (from hal)
#include "gpu/gsp/message_queue.h"
#include "libraries/utils/nvbitvector.h"
#include "gpu/rpc/objrpcstructurecopy.h"
typedef struct GSP_FIRMWARE GSP_FIRMWARE;
typedef struct _object_vgpu OBJVGPU, *POBJVGPU;
TYPEDEF_BITVECTOR(MC_ENGINE_BITVECTOR);
#include "g_rpc_hal.h" // For RPC_HAL_IFACES
#include "g_rpc_odb.h" // For RPC_HAL_IFACES
#define RPC_TIMEOUT_LIMIT_PRINT_RATE_THRESH 3 // rate limit after 3 prints
#define RPC_TIMEOUT_LIMIT_PRINT_RATE_SKIP 29 // skip 29 of 30 prints
#define RPC_HISTORY_DEPTH 128
typedef struct RpcHistoryEntry
{
NvU32 function;
NvU64 data[2];
NvU64 ts_start;
NvU64 ts_end;
} RpcHistoryEntry;
struct OBJRPC{
OBJECT_BASE_DEFINITION(RPC);
struct {
NvU32 ipVersion;
}__nvoc_pbase_Object[1]; // This nested structure mechanism is to bypass NVOC
// Message buffer fields
NvU32 *message_buffer;
NvU32 *message_buffer_priv;
MEMORY_DESCRIPTOR *pMemDesc_mesg;
NvU32 maxRpcSize;
NvU32 largeRpcSize;
// UVM Message buffer fields
NvU32 *message_buffer_uvm;
NvU32 *message_buffer_priv_uvm;
MEMORY_DESCRIPTOR *pMemDesc_mesg_uvm;
/* Message Queue */
struct _message_queue_info *pMessageQueueInfo;
RpcHistoryEntry rpcHistory[RPC_HISTORY_DEPTH];
NvU32 rpcHistoryCurrent;
RpcHistoryEntry rpcEventHistory[RPC_HISTORY_DEPTH];
NvU32 rpcEventHistoryCurrent;
NvU32 timeoutCount;
NvBool bQuietPrints;
OBJRPCSTRUCTURECOPY rpcStructureCopy;
};
//
// Utility macros for composing RPC messages.
// See <vgpu/dev_vgpu.h> for message formats.
// A message has a fixed-format header and optionally a variable length
// parameter after the header.
//
#define vgpu_rpc_message_header_v ((rpc_message_header_v*)(pRpc->message_buffer))
#define rpc_message (vgpu_rpc_message_header_v->rpc_message_data)
static inline void _objrpcStructureCopyAssignIpVersion(struct OBJRPCSTRUCTURECOPY* pRpcStructureCopy, NvU32 ipVersion)
{
pRpcStructureCopy->__nvoc_pbase_Object->ipVersion = ipVersion;
}
static inline void _objrpcAssignIpVersion(struct OBJRPC* pRpc, NvU32 ipVersion)
{
pRpc->__nvoc_pbase_Object->ipVersion = ipVersion;
}
OBJRPC *initRpcObject(OBJGPU *pGpu);
void rpcSetIpVersion(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 ipVersion);
void rpcObjIfacesSetup(OBJRPC *pRpc);
NV_STATUS rpcWriteCommonHeader(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 func, NvU32 paramLength);
NV_STATUS rpcWriteCommonHeaderSim(OBJGPU *pGpu);
NV_STATUS vgpuGspSetupBuffers(OBJGPU *pGpu);
void vgpuGspTeardownBuffers(OBJGPU *pGpu);
NV_STATUS vgpuReinitializeRpcInfraOnStateLoad(OBJGPU *pGpu);
// Initialize and free RPC infrastructure
NV_STATUS initRpcInfrastructure_VGPU(OBJGPU *pGpu);
NV_STATUS freeRpcInfrastructure_VGPU(OBJGPU *pGpu);
NV_STATUS _allocRpcMemDesc(OBJGPU *pGpu, NvU64 size, NvBool bContig, NV_ADDRESS_SPACE addrSpace, NvU32 memFlags,
MEMORY_DESCRIPTOR **ppMemDesc, void **ppMemBuffer, void **ppMemBufferPriv);
void _freeRpcMemDesc(OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, void **ppMemBuffer, void **ppMemBufferPriv);
NV_STATUS rpcDmaControl_wrapper(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd,
void *pParamStructPtr, NvU32 paramSize);
//
// OBJGPU RPC member accessors.
// Historically, they have been defined inline by the following macros.
// These definitions were migrated to gpu.c in order to avoid having to include object headers in
// this file.
//
OBJRPC *gpuGetGspClientRpc(OBJGPU*);
OBJRPC *gpuGetVgpuRpc(OBJGPU*);
OBJRPC *gpuGetRpc(OBJGPU*);
#define GPU_GET_GSPCLIENT_RPC(u) gpuGetGspClientRpc(u)
#define GPU_GET_VGPU_RPC(u) gpuGetVgpuRpc(u)
#define GPU_GET_RPC(u) gpuGetRpc(u)
#endif // _OBJRPC_H_

42
src/nvidia/inc/kernel/gpu/rpc/objrpcstructurecopy.h Normal file
View File

@@ -0,0 +1,42 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _OBJRPCSTRUCTURECOPY_H_
#define _OBJRPCSTRUCTURECOPY_H_
#include "vgpu/sdk-structures.h"
#include "ctrl/ctrl0080/ctrl0080bsp.h" // rmcontrol params (from hal)
#include "ctrl/ctrl2080/ctrl2080gr.h" // rmcontrol params (from hal)
#include "ctrl/ctrl2080/ctrl2080clk.h" // rmcontrol params (from hal)
#include "g_rpcstructurecopy_hal.h" // For RPCSTRUCTURECOPY_HAL_IFACES
#include "g_rpcstructurecopy_odb.h" // For RPCSTRUCTURECOPY_HAL_IFACES
struct OBJRPCSTRUCTURECOPY{
OBJECT_BASE_DEFINITION(RPCSTRUCTURECOPY);
struct {
NvU32 ipVersion;
}__nvoc_pbase_Object[1]; // This nested structure mechanism is to bypass NVOC
};
#endif //_OBJRPCSTRUCTURECOPY_H_

3
src/nvidia/inc/kernel/gpu/spdm/libspdm_includes.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,6 +34,7 @@
#include "internal/libspdm_common_lib.h"
#include "internal/libspdm_secured_message_lib.h"
#include "library/spdm_requester_lib.h"
#include "nvspdm_cryptlib_extensions.h"
/* ------------------------ Macros and Defines ----------------------------- */
//

61
src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_event.h
View File

@@ -1,61 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
RMCTRL_EXPORT(NV2080_CTRL_CMD_EVENT_SET_TRIGGER,
RMCTRL_FLAGS(NON_PRIVILEGED))
NV_STATUS subdeviceCtrlCmdEventSetTrigger(Subdevice *pSubdevice);
RMCTRL_EXPORT(NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO,
RMCTRL_FLAGS(NO_GPUS_LOCK, NON_PRIVILEGED))
NV_STATUS subdeviceCtrlCmdEventSetTriggerFifo(Subdevice *pSubdevice,
NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS *pTriggerFifoParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION,
RMCTRL_FLAGS(NON_PRIVILEGED, API_LOCK_READONLY, GPU_LOCK_DEVICE_ONLY))
NV_STATUS subdeviceCtrlCmdEventSetNotification(Subdevice *pSubdevice,
NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS *pSetEventParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES,
RMCTRL_FLAGS(NON_PRIVILEGED))
NV_STATUS subdeviceCtrlCmdEventSetMemoryNotifies(Subdevice *pSubdevice,
NV2080_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS *pSetMemoryNotifiesParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_EVENT_SET_SEMAPHORE_MEMORY,
RMCTRL_FLAGS(NON_PRIVILEGED))
NV_STATUS subdeviceCtrlCmdEventSetSemaphoreMemory(Subdevice *pSubdevice,
NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS *pSetSemMemoryParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_EVENT_SET_SEMA_MEM_VALIDATION,
RMCTRL_FLAGS(NON_PRIVILEGED))
NV_STATUS subdeviceCtrlCmdEventSetSemaMemValidation(Subdevice *pSubdevice,
NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS *pSetSemaMemValidationParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_EVENT_VIDEO_BIND_EVTBUF,
RMCTRL_FLAGS(NON_PRIVILEGED, API_LOCK_READONLY, GPU_LOCK_DEVICE_ONLY))
NV_STATUS subdeviceCtrlCmdEventVideoBindEvtbuf(Subdevice *pSubdevice,
NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS *pBindParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF,
RMCTRL_FLAGS(PRIVILEGED))
NV_STATUS subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf(Subdevice *pSubdevice,
NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS *pBindParams);

97
src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_rc.h
View File

@@ -1,97 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM,
RMCTRL_FLAGS(KERNEL_PRIVILEGED))
NV_STATUS subdeviceCtrlCmdRcReadVirtualMem(Subdevice *pSubdevice,
NV2080_CTRL_RC_READ_VIRTUAL_MEM_PARAMS *pReadVirtMemParam);
//
// Note that if SMC is enabled, mig/monitor capability must be acquired
// to query Xids
//
// These two calls must be NON_PRIVILEGED, and should NOT ROUTE_TO_PHYSICAL.
// MIG monitor capability checks are performed on kernel side and the calls
// are manually RPCed to physical RM.
//
// Physical RM checks if the call it received was an internal call. In
// future, this should be migrated to a separate internal ctrl cmd.
//
RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_GET_ERROR_COUNT,
RMCTRL_FLAGS(NON_PRIVILEGED))
NV_STATUS subdeviceCtrlCmdRcGetErrorCount(Subdevice *pSubdevice,
NV2080_CTRL_RC_GET_ERROR_COUNT_PARAMS *pErrorCount);
RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_GET_ERROR_V2, RMCTRL_FLAGS(NON_PRIVILEGED))
NV_STATUS subdeviceCtrlCmdRcGetErrorV2(Subdevice *pSubdevice,
NV2080_CTRL_RC_GET_ERROR_V2_PARAMS *pErrorParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_SET_CLEAN_ERROR_HISTORY,
RMCTRL_FLAGS(PRIVILEGED, ROUTE_TO_PHYSICAL))
NV_STATUS subdeviceCtrlCmdRcSetCleanErrorHistory(Subdevice *pSubdevice);
RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO,
RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY, API_LOCK_READONLY))
NV_STATUS subdeviceCtrlCmdRcGetWatchdogInfo(Subdevice *pSubdevice,
NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS *pWatchdogInfoParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_DISABLE_WATCHDOG,
RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY))
NV_STATUS subdeviceCtrlCmdRcDisableWatchdog(Subdevice *pSubdevice);
RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG,
RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY))
NV_STATUS subdeviceCtrlCmdRcSoftDisableWatchdog(Subdevice *pSubdevice);
RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_ENABLE_WATCHDOG,
RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY))
NV_STATUS subdeviceCtrlCmdRcEnableWatchdog(Subdevice *pSubdevice);
RMCTRL_EXPORT(NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS,
RMCTRL_FLAGS(NON_PRIVILEGED, GPU_LOCK_DEVICE_ONLY))
NV_STATUS subdeviceCtrlCmdRcReleaseWatchdogRequests(Subdevice *pSubdevice);
RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT,
RMCTRL_FLAGS(KERNEL_PRIVILEGED, INTERNAL, ROUTE_TO_PHYSICAL))
NV_STATUS subdeviceCtrlCmdInternalRcWatchdogTimeout(Subdevice *pSubdevice);
RMCTRL_EXPORT(NV2080_CTRL_CMD_SET_RC_RECOVERY,
RMCTRL_FLAGS(PRIVILEGED, ROUTE_TO_PHYSICAL))
NV_STATUS subdeviceCtrlCmdSetRcRecovery(Subdevice *pSubdevice,
NV2080_CTRL_CMD_RC_RECOVERY_PARAMS *pRcRecovery);
RMCTRL_EXPORT(NV2080_CTRL_CMD_GET_RC_RECOVERY,
RMCTRL_FLAGS(PRIVILEGED, ROUTE_TO_PHYSICAL))
NV_STATUS subdeviceCtrlCmdGetRcRecovery(Subdevice *pSubdevice,
NV2080_CTRL_CMD_RC_RECOVERY_PARAMS *pRcRecovery);
RMCTRL_EXPORT(NV2080_CTRL_CMD_GET_RC_INFO,
RMCTRL_FLAGS(PRIVILEGED, ROUTE_TO_PHYSICAL))
NV_STATUS subdeviceCtrlCmdGetRcInfo(Subdevice *pSubdevice,
NV2080_CTRL_CMD_RC_INFO_PARAMS *pParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_SET_RC_INFO,
RMCTRL_FLAGS(PRIVILEGED, ROUTE_TO_PHYSICAL))
NV_STATUS subdeviceCtrlCmdSetRcInfo(Subdevice *pSubdevice,
NV2080_CTRL_CMD_RC_INFO_PARAMS *pParams);

3
src/nvidia/inc/kernel/gpu/timer/objtmr.h Normal file
View File

@@ -0,0 +1,3 @@
#include "g_objtmr_nvoc.h"

3
src/nvidia/inc/kernel/gpu/timer/tmr.h Normal file
View File

@@ -0,0 +1,3 @@
#include "g_tmr_nvoc.h"

1
src/nvidia/inc/kernel/mem_mgr/pool_alloc.h
View File

@@ -48,6 +48,7 @@ typedef enum
{
POOL_CONFIG_GMMU_FMT_1, // configure pool for client page tables with version = GMMU_FMT_VERSION_1
POOL_CONFIG_GMMU_FMT_2, // configure pool for client page tables with version = GMMU_FMT_VERSION_2
POOL_CONFIG_CTXBUF_256G, // configure pool for RM internal allocations like ctx buffers with 256GB page size
POOL_CONFIG_CTXBUF_512M, // configure pool for RM internal allocations like ctx buffers with 512MB page size
POOL_CONFIG_CTXBUF_2M, // configure pool for RM internal allocations like ctx buffers with 2MB page size
POOL_CONFIG_CTXBUF_64K, // configure pool for RM internal allocations like ctx buffers with 64KB page size

3
src/nvidia/inc/kernel/mem_mgr/syncpoint_mem.h Normal file
View File

@@ -0,0 +1,3 @@
#include "g_syncpoint_mem_nvoc.h"

28
src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h → src/nvidia/inc/kernel/os/nv_memory_area.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,19 +21,19 @@
* DEALINGS IN THE SOFTWARE.
*/
RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_MAP,
RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL))
NV_STATUS subdeviceCtrlCmdCcuMap(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *pParams);
#ifndef NV_MEMORY_AREA_H
#define NV_MEMORY_AREA_H
RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP,
RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL))
NV_STATUS subdeviceCtrlCmdCcuUnmap(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_UNMAP_INFO_PARAMS *pParams);
typedef struct MemoryRange
{
NvU64 start;
NvU64 size;
} MemoryRange;
RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_SET_STREAM_STATE,
RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL))
NV_STATUS subdeviceCtrlCmdCcuSetStreamState(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_STREAM_STATE_PARAMS *pParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_GET_SAMPLE_INFO,
RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL))
NV_STATUS subdeviceCtrlCmdCcuGetSampleInfo(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS *pParams);
typedef struct MemoryArea
{
MemoryRange *pRanges;
NvU64 numRanges;
} MemoryArea;
#endif /* NV_MEMORY_AREA_H */

5
src/nvidia/inc/kernel/os/os_stub.h
View File

@@ -36,12 +36,7 @@
// Each of these stub functions returns a different type. Used to
// stub out function pointers in OBJOS.
//
OSnv_rdcr4 stubOsnv_rdcr4;
OSnv_rdxcr0 stubOsnv_rdxcr0;
OSnv_cpuid stubOsnv_cpuid;
OSSpinLoop stubOsSpinLoop;
OSSetSurfaceName stubOsSetSurfaceName;
OSObjectEventNotification stubOsObjectEventNotification;
#endif // OS_STUB_H

3
src/nvidia/inc/kernel/platform/hwbc.h
View File

@@ -24,7 +24,7 @@
#ifndef HWBC_H
#define HWBC_H
#include "gpu/gpu.h" // NBADDR, POBJGPU
#include "gpu/gpu.h" // NBADDR, OBJGPU
/**************** Resource Manager Defines and Structures ******************\
* *
@@ -33,7 +33,6 @@
* *
\***************************************************************************/
struct OBJCL;
typedef struct OBJHWBC *POBJHWBC;
typedef struct OBJHWBC OBJHWBC;

439
src/nvidia/inc/kernel/platform/nvpcf.h Normal file
View File

@@ -0,0 +1,439 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVPCF_H
#define NVPCF_H
#include "ctrl/ctrl0000/ctrl0000system.h"
/*
* Definitions for the static params table.
*/
/*!
* Layout of SysDev 2x data used for static config
*/
#define NVPCF_SYSDEV_STATIC_TABLE_VERSION_2X (0x20)
#define NVPCF_SYSDEV_STATIC_TABLE_HEADER_2X_SIZE_03 (0x03U)
#define NVPCF_SYSDEV_STATIC_TABLE_HEADER_2X_FMT_SIZE_03 ("3b")
#define NVPCF_SYSDEV_STATIC_TABLE_COMMON_2X_SIZE_01 (0x01U)
#define NVPCF_SYSDEV_STATIC_TABLE_COMMON_2X_FMT_SIZE_01 ("1b")
/*!
* Static system dev header table, unpacked
*/
typedef struct
{
/*
* System device Table Version.
*/
NvU32 version;
/*
* Size of device Table Header in bytes .
*/
NvU32 headerSize;
/*
* Size of common entry in bytes.
*/
NvU32 commonSize;
} SYSDEV_STATIC_TABLE_HEADER_2X;
/*!
* Static system dev common entry
*/
typedef struct
{
NvU32 param0;
} SYSDEV_STATIC_TABLE_COMMON_2X;
#define NVPCF_SYSDEV_STATIC_TABLE_COMMON_2X_PARAM0_CPU_TYPE 3:0
#define NVPCF_SYSDEV_STATIC_TABLE_COMMON_2X_PARAM0_CPU_TYPE_INTEL (0x00000000)
#define NVPCF_SYSDEV_STATIC_TABLE_COMMON_2X_PARAM0_CPU_TYPE_AMD (0x00000001)
#define NVPCF_SYSDEV_STATIC_TABLE_COMMON_2X_PARAM0_CPU_TYPE_NVIDIA (0x00000002)
#define NVPCF_SYSDEV_STATIC_TABLE_COMMON_2X_PARAM0_GPU_TYPE 7:4
#define NVPCF_SYSDEV_STATIC_TABLE_COMMON_2X_PARAM0_GPU_TYPE_NVIDIA (0x00000000)
/*!
* Layout of Controller 2x data used for static config
*/
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_20 (0x20)
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_21 (0x21)
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_22 (0x22)
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_23 (0x23)
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_24 (0x24)
#define NVPCF_CONTROLLER_STATIC_TABLE_MAX_ENTRIES (8)
// format for 2.0 and 2.1
#define NVPCF_CONTROLLER_STATIC_TABLE_HEADER_V20_SIZE_05 (0x05U)
#define NVPCF_CONTROLLER_STATIC_TABLE_HEADER_V20_FMT_SIZE_05 ("5b")
#define NVPCF_CONTROLLER_STATIC_TABLE_COMMON_V20_SIZE_02 (0x02U)
#define NVPCF_CONTROLLER_STATIC_TABLE_COMMON_V20_FMT_SIZE_02 ("1w")
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_SIZE_0F (0x0FU)
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_FMT_SIZE_0F ("1b1w3d")
/*!
* Static system controller header table v2.0/2.1, unpacked
*/
typedef struct
{
/*
* System controller Table Version.
*/
NvU32 version;
/*
* Size of controller Table Header in bytes .
*/
NvU32 headerSize;
/*
* Size of controller Table Common/Global Entry in bytes.
*/
NvU32 commonSize;
/*
* Size of controller Table Entry in bytes.
*/
NvU32 entrySize;
/*
* Number of controller Entries
*/
NvU32 entryCount;
} CONTROLLER_STATIC_TABLE_HEADER_V20;
/*!
* Static system controller common/global entry v2.0/2.1, unpacked
*/
typedef struct
{
/*
* Base sampling period in ms
*/
NvU32 samplingPeriodms;
} CONTROLLER_STATIC_TABLE_COMMON_V20;
/*!
* Static system controller entry v2.0/2.1, unpacked
*/
typedef struct
{
/*
* System controller entry type specific flag (Flags0).
*/
NvU32 flags0;
/*
* Sampling Multiplier.
*/
NvU32 samplingMulti;
/*
* System controller entry filter parameters.
*/
NvU32 filterParams;
/*
* System controller entry Usage-Specific Parameter (Param0).
*/
NvU32 param0;
/*
* System controller entry Usage-Specific Parameter (Param1).
*/
NvU32 param1;
} CONTROLLER_STATIC_TABLE_ENTRY_V20;
// FLAGS0
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_FLAGS0_CLASS 3:0
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_FLAGS0_CLASS_DISABLED (0x00000000)
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_FLAGS0_CLASS_PPAB (0x00000001)
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_FLAGS0_CLASS_CTGP (0x00000002)
// Filter
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_FILTER_TYPE 7:0
// filterType = EWMA
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_FILTERPARAM_EWMA_WEIGHT 15:8
// filterType = MAX, others
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_FILTERPARAM_WINDOW_SIZE 15:8
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_FILTER_RESERVED 31:16
// Param0
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_PARAM0_QBOOST_INCREASE_GAIN 15:0
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_PARAM0_QBOOST_DECREASE_GAIN 31:16
// Param1
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_PARAM1_QBOOST_DC_SUPPORT 0:0
// format for 2.2
#define NVPCF_CONTROLLER_STATIC_TABLE_HEADER_V22_SIZE_04 (0x04U)
#define NVPCF_CONTROLLER_STATIC_TABLE_HEADER_V22_FMT_SIZE_04 ("4b")
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_SIZE_05 (0x05U)
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_FMT_SIZE_05 ("1b1d")
/*!
* Static system controller header table v2.2, unpacked
*/
typedef struct
{
/*
* System controller Table Version.
*/
NvU32 version;
/*
* Size of controller Table Header in bytes .
*/
NvU32 headerSize;
/*
* Size of controller Table Entry in bytes.
*/
NvU32 entrySize;
/*
* Number of controller Entries
*/
NvU32 entryCount;
} CONTROLLER_STATIC_TABLE_HEADER_V22;
/*!
* Static system controller entry v2.2, unpacked
*/
typedef struct
{
/*
* System controller entry type specific flag (Flags0).
*/
NvU32 flags0;
/*
* System controller entry Usage-Specific Parameter (Param0).
*/
NvU32 param0;
} CONTROLLER_STATIC_TABLE_ENTRY_V22;
// FLAGS0
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_FLAGS0_CLASS 3:0
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_FLAGS0_CLASS_DISABLED (0x00000000)
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_FLAGS0_CLASS_PPAB (0x00000001)
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_FLAGS0_CLASS_CTGP (0x00000002)
// Param0
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_PARAM0_QBOOST_DC_SUPPORT 0:0
/*
* Definitions for the dynamic params table.
*/
#define NVPCF0100_CTRL_DYNAMIC_TABLE_1X_VERSION (0x10)
#define NVPCF0100_CTRL_DYNAMIC_TABLE_1X_ENTRY_SIZE (4U)
//
// This is set to 32UL in windows NVPCF driver. Set it to 2UL which is good
// enough for now to save space
//
#define NVPCF0100_CTRL_DYNAMIC_TABLE_1X_ENTRY_MAX (2UL)
#define NVPCF0100_CTRL_DYNAMIC_TABLE_1X_INPUT_CMD_GET_TPP (0x04)
/*
* Dynamic Params Table Header, v1.x.
*/
typedef struct
{
NvU8 version;
NvU8 size;
//
// Number of entries in the entire table.
//
NvU8 entryCnt;
NvU8 reserved;
} NVPCF0100_CTRL_DYNAMIC_TABLE_1X_HEADER,
*PNVPCF0100_CTRL_DYNAMIC_TABLE_1X_HEADER;
/*
* Define the dynamic params table header and entries used by the ACPI call.
*/
typedef struct
{
NVPCF0100_CTRL_DYNAMIC_TABLE_1X_HEADER header;
NvU32 entries[NVPCF0100_CTRL_DYNAMIC_TABLE_1X_ENTRY_MAX];
} CONTROLLER_DYNAMIC_TABLE_1X_ACPI,
*PCONTROLLER_DYNAMIC_TABLE_1X_ACPI;
/*!
* Config DSM NVPCF 2x version specific defines
*/
/*
* Definitions for the dynamic params table.
*/
#define NVPCF_DYNAMIC_PARAMS_20_VERSION (0x20)
#define NVPCF_DYNAMIC_PARAMS_21_VERSION (0x21)
#define NVPCF_DYNAMIC_PARAMS_22_VERSION (0x22)
#define NVPCF_DYNAMIC_PARAMS_23_VERSION (0x23)
#define NVPCF_DYNAMIC_PARAMS_2X_HEADER_SIZE_05 (0x05U)
#define NVPCF_DYNAMIC_PARAMS_2X_HEADER_FMT_SIZE_05 ("5b")
#define NVPCF_DYNAMIC_PARAMS_2X_COMMON_SIZE_10 (0x10U)
#define NVPCF_DYNAMIC_PARAMS_2X_COMMON_FMT_SIZE_10 ("4d")
#define NVPCF_DYNAMIC_PARAMS_2X_ENTRY_SIZE_1C (0x1CU)
#define NVPCF_DYNAMIC_PARAMS_2X_ENTRY_FMT_SIZE_1C ("7d")
#define NVPCF_DYNAMIC_PARAMS_2X_ENTRY_MAX (8)
// Power unit used, 125 milli-watts
#define NVPCF_DYNAMIC_PARAMS_2X_POWER_UNIT_MW (125)
/*!
* Dynamic params header, unpacked.
*/
typedef struct
{
/*
* Dynamic params table Version.
*/
NvU32 version;
/*
* Size of dynamic params table header in bytes.
*/
NvU32 headerSize;
/*
* Size of global/common entry in bytes.
*/
NvU32 commonSize;
/*
* Size of each controller entry in bytes.
*/
NvU32 entrySize;
/*
* Number of controller entries.
*/
NvU32 entryCount;
} DYNAMIC_PARAMS_HEADER_2X;
/*!
* Dynamic params table global/common, unpacked.
*/
typedef struct
{
NvU32 param0;
NvU32 param1;
NvU32 param2;
NvU32 param3;
} DYNAMIC_PARAMS_COMMON_2X;
/*!
* Dynamic params table controller entry, unpacked.
*/
typedef struct
{
NvU32 param0;
NvU32 param1;
NvU32 param2;
NvU32 param3;
NvU32 param4;
NvU32 param5;
NvU32 param6;
} DYNAMIC_PARAMS_ENTRY_2X;
/*!
* Dynamic params table header, packed.
*/
typedef struct
{
NvU8 version;
NvU8 headerSize;
NvU8 commonSize;
NvU8 entrySize;
NvU8 entryCount;
} DYNAMIC_PARAMS_HEADER_2X_PACKED;
/*!
* Dynamic params table global/common, packed.
*/
typedef struct
{
NvU32 param0;
NvU32 param1;
NvU32 param2;
NvU32 param3;
} DYNAMIC_PARAMS_COMMON_2X_PACKED;
/*!
* Dynamic params table controller entry, packed.
*/
typedef struct
{
NvU32 param0;
NvU32 param1;
NvU32 param2;
NvU32 param3;
NvU32 param4;
NvU32 param5;
NvU32 param6;
} DYNAMIC_PARAMS_ENTRY_2X_PACKED;
// Input Commands (Input Param0)
#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_INPUT_PARAM0_CMD 1:0
#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_INPUT_PARAM0_CMD_GET (0)
#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_INPUT_PARAM0_CMD_SET (1)
//
// Input Command 0 (Get Controller Parameters)
//
// Global/Common Entry, Output Param0
#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_OUTPUT_PARAM0_CMD0_CTGP_AC_OFFSET 15:0
#define NVPCF_DYNAMIC_PARAMS_COMMON_2X_OUTPUT_PARAM0_CMD0_CTGP_DC_OFFSET 31:16
// Controller Entry, Output Param0
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM0_CMD0_IDX 7:0
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM0_CMD0_DISABLE_AC 8:8
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM0_CMD0_DISABLE_DC 9:9
// Controller Entry, Output Params1
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM1_CMD0_SIGNED0 15:0
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM1_CMD0_SIGNED1 31:16
// Controller Entry, Output Params2
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM2_CMD0_SIGNED0 15:0
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM2_CMD0_SIGNED1 31:16
// Controller Entry, Output Params3
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM3_CMD0_SIGNED0 15:0
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM3_CMD0_SIGNED1 31:16
// Controller Entry, Output Params4
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM4_CMD0_UNSIGNED 31:0
// Controller Entry, Output Params5
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM5_CMD0_UNSIGNED 31:0
// Controller Entry, Output Params6
#define NVPCF_DYNAMIC_PARAMS_ENTRY_2X_OUTPUT_PARAM6_CMD0_UNSIGNED 31:0
#endif // NVPCF_H

15
src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2013-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -279,15 +279,12 @@ NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(gpuFaultInfo *pFaultInfo,
NV_STATUS nvGpuOpsTogglePrefetchFaults(gpuFaultInfo *pFaultInfo,
NvBool bEnable);
NV_STATUS nvGpuOpsKeyRotationChannelDisable(struct gpuChannel *channelList[],
NvU32 channelListCount);
// Interface used for CCSL
NV_STATUS nvGpuOpsCcslContextInit(struct ccslContext_t **ctx,
gpuChannelHandle channel);
NV_STATUS nvGpuOpsCcslContextClear(struct ccslContext_t *ctx);
NV_STATUS nvGpuOpsCcslContextUpdate(UvmCslContext *contextList[],
NvU32 contextListCount);
NV_STATUS nvGpuOpsCcslRotateKey(UvmCslContext *contextList[],
NvU32 contextListCount);
NV_STATUS nvGpuOpsCcslRotateIv(struct ccslContext_t *ctx,
NvU8 direction);
NV_STATUS nvGpuOpsCcslEncrypt(struct ccslContext_t *ctx,
@@ -305,6 +302,7 @@ NV_STATUS nvGpuOpsCcslDecrypt(struct ccslContext_t *ctx,
NvU32 bufferSize,
NvU8 const *inputBuffer,
NvU8 const *decryptIv,
NvU32 keyRotationId,
NvU8 *outputBuffer,
NvU8 const *addAuthData,
NvU32 addAuthDataSize,
@@ -320,7 +318,8 @@ NV_STATUS nvGpuOpsIncrementIv(struct ccslContext_t *ctx,
NvU8 direction,
NvU64 increment,
NvU8 *iv);
NV_STATUS nvGpuOpsLogDeviceEncryption(struct ccslContext_t *ctx,
NvU32 bufferSize);
NV_STATUS nvGpuOpsLogEncryption(struct ccslContext_t *ctx,
NvU8 direction,
NvU32 bufferSize);
#endif /* _NV_GPU_OPS_H_*/

117
src/nvidia/inc/kernel/vgpu/rm_plugin_shared_code.h
View File

@@ -271,6 +271,26 @@ return_t deserialize_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00(NV9096_CTRL_S
return SUCCESS_T;
}
static
return_t deserialize_NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06(NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06 *src = (void*)(buffer);
NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS *dest = pParams;
if (src && dest) {
dest->stencil = src->stencil;
dest->format = src->format;
dest->bSkipL2Table = src->bSkipL2Table;
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t deserialize_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00(NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *pParams,
NvU8 *buffer,
@@ -2916,6 +2936,26 @@ return_t serialize_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00(NV9096_CTRL_SET
return SUCCESS_T;
}
static
return_t serialize_NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06(NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS *src = pParams;
NV9096_CTRL_SET_ZBC_STENCIL_CLEAR_PARAMS_v27_06 *dest = (void*)(buffer);
if (src && dest) {
dest->stencil = src->stencil;
dest->format = src->format;
dest->bSkipL2Table = src->bSkipL2Table;
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t serialize_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00(NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *pParams,
NvU8 *buffer,
@@ -5416,6 +5456,68 @@ return_t deserialize_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A(NV2080_CTRL_FB_GET
return SUCCESS_T;
}
static
return_t serialize_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00(NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV2080_CTRL_FB_GET_INFO_V2_PARAMS *src = pParams;
NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00 *dest = (void*)(buffer);
if (src && dest)
{
NvU32 i;
if ((src->fbInfoListSize == 0) ||
(src->fbInfoListSize > NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_27_00)) {
return FAILURE_T;
}
dest->fbInfoListSize = src->fbInfoListSize;
for (i = 0; i < src->fbInfoListSize; i++) {
dest->fbInfoList[i].index = src->fbInfoList[i].index;
dest->fbInfoList[i].data = src->fbInfoList[i].data;
}
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t deserialize_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00(NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00 *src = (void*)(buffer);
NV2080_CTRL_FB_GET_INFO_V2_PARAMS *dest = pParams;
if (src && dest)
{
NvU32 i;
if ((src->fbInfoListSize == 0) ||
(src->fbInfoListSize > NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_27_00)) {
return FAILURE_T;
}
dest->fbInfoListSize = src->fbInfoListSize;
for (i = 0; i < src->fbInfoListSize; i++) {
dest->fbInfoList[i].index = src->fbInfoList[i].index;
dest->fbInfoList[i].data = src->fbInfoList[i].data;
}
}
else
return FAILURE_T;
return SUCCESS_T;
}
#endif // defined(BUILD_COMMON_RPCS)
#ifdef BUILD_COMMON_RPCS
@@ -6081,21 +6183,6 @@ NvU32 serialize_engineType(NvU32 inEngineType)
return host_to_guest_enginetype_v1A_00[inEngineType].outType;
}
// Convert a host engineList to a guest engineList.
NvU64 searilize_engineCap(NvU64 inEngineCap)
{
if (vgx_internal_version_curr.major_number >= 0x1B) {
return inEngineCap;
}
NvU64 outEngineCap= 0, i = 0;
FOR_EACH_INDEX_IN_MASK(64, i, inEngineCap)
{
outEngineCap = outEngineCap | NVBIT64(serialize_engineType(i));
} FOR_EACH_INDEX_IN_MASK_END;
return outEngineCap;
}
// Convert a host notifier index to a guest notifier index.
NvU32 serialize_notifier(NvU32 inNotifier)
{

2
src/nvidia/inc/kernel/vgpu/rpc.h
View File

@@ -36,7 +36,7 @@
#include "class/cl84a0.h"
#include "vgpu/rpc_headers.h"
#include "gpu/dce_client/dce_client.h"
#include "objrpc.h"
#include "gpu/rpc/objrpc.h"
#include "rpc_vgpu.h"
#include "vgpu_events.h"

5
src/nvidia/inc/kernel/vgpu/rpc_global_enums.h
View File

@@ -219,7 +219,10 @@ enum {
X(RM, CTRL_GPU_GET_INFO_V2, 209)
X(RM, GET_BRAND_CAPS, 210)
X(RM, CTRL_CMD_NVLINK_INBAND_SEND_DATA, 211)
X(RM, NUM_FUNCTIONS, 212)
X(RM, UPDATE_GPM_GUEST_BUFFER_INFO, 212)
X(RM, RESERVED_213, 213)
X(RM, CTRL_SET_ZBC_STENCIL_CLEAR, 214)
X(RM, NUM_FUNCTIONS, 215)
#ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H
};
# undef X

12
src/nvidia/inc/kernel/vgpu/rpc_vgpu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -181,4 +181,14 @@ static NV_INLINE void NV_RM_RPC_UPDATE_GPU_PDES(OBJGPU *pGpu, ...) { }
status = NV_ERR_INSUFFICIENT_RESOURCES; \
} while (0)
#define NV_RM_RPC_UPDATE_GPM_GUEST_BUFFER_INFO(pGpu, status, gpfn, swizzId, computeId, \
bufSize, bMap) \
do \
{ \
OBJRPC *pRpc = GPU_GET_RPC(pGpu); \
if ((status == NV_OK) && (pRpc != NULL)) \
status = rpcUpdateGpmGuestBufferInfo_HAL(pGpu, pRpc, gpfn, swizzId, computeId, \
bufSize, bMap); \
} while(0)
#endif // __vgpu_dev_nv_rpc_vgpu_h__

39
src/nvidia/inc/kernel/vgpu/sdk-structures.h
View File

@@ -200,9 +200,11 @@ typedef struct VGPU_BSP_CAPS
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v20_03 (0x00000018)
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06 (0x00000019)
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v26_02 (0x0000001E)
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT_v27_04 (0x0000001F)
#define NV2080_ENGINE_TYPE_LAST_v18_01 (0x0000002a)
#define NV2080_ENGINE_TYPE_LAST_v1C_09 (0x00000034)
#define NV2080_ENGINE_TYPE_LAST_v27_02 (0x00000054)
#define NV2080_ENGINE_TYPE_LAST_v1A_00 (0x2a)
@@ -232,6 +234,7 @@ typedef struct VGPU_BSP_CAPS
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1E_01 0x35
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_1F_0F 0x36
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A 0x37
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_27_00 0x39
#define NV2080_CTRL_PERF_MAX_LIMITS_v1C_0B 0x100
@@ -266,6 +269,29 @@ typedef struct VGPU_BSP_CAPS
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11 0x00000041
#define NV2080_CTRL_BOARDOBJGRP_E255_MAX_OBJECTS_v06_01 (255U)
#define NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX 4
#define NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX_v27_01 4
#define NVGPU_VGPU_ENGINE_LIST_MASK_BITS_SHIFT 6
#define NVGPU_VGPU_ENGINE_LIST_MASK_BITS (1 << NVGPU_VGPU_ENGINE_LIST_MASK_BITS_SHIFT)
#define NVGPU_VGPU_ENGINE_LIST_MASK_BITS_MASK (NVGPU_VGPU_ENGINE_LIST_MASK_BITS - 1)
#define NVGPU_VGPU_ENGINE_LIST_LAST (NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX * \
NVGPU_VGPU_ENGINE_LIST_MASK_BITS)
//
// Engine Type capability mask bit-array helper MACROS to support on growing number of engine types
// The enginelist is defined as
// NvU64 engineList[NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX_v27_01]
//
// To check whether the bit is set for the particular ID in enginelist.
#define NVGPU_VGPU_GET_ENGINE_LIST_MASK(enginelist, id) \
(enginelist[(id) >> NVGPU_VGPU_ENGINE_LIST_MASK_BITS_SHIFT] & NVBIT64((id) & NVGPU_VGPU_ENGINE_LIST_MASK_BITS_MASK))
// To set the bit for the particular ID in enginelist.
#define NVGPU_VGPU_SET_ENGINE_LIST_MASK(enginelist, id) \
(enginelist[(id) >> NVGPU_VGPU_ENGINE_LIST_MASK_BITS_SHIFT] |= NVBIT64((id) & NVGPU_VGPU_ENGINE_LIST_MASK_BITS_MASK))
// To unset the bit for the particular ID in the enginelist.
#define NVGPU_VGPU_UNSET_ENGINE_LIST_MASK(enginelist, id) \
(enginelist[(id) >> NVGPU_VGPU_ENGINE_LIST_MASK_BITS_SHIFT] &= ~NVBIT64((id) & NVGPU_VGPU_ENGINE_LIST_MASK_BITS_MASK))
typedef struct _GPU_PARTITION_INFO
{
@@ -340,7 +366,7 @@ struct _vgpu_static_info
NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS vgxSystemInfo;
NVA080_CTRL_VGPU_GET_CONFIG_PARAMS vgpuConfig;
NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo;
NvU64 engineList;
NvU64 engineList[NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX];
NvU32 pcieGpuLinkCaps;
NvBool bFlaSupported;
NV2080_CTRL_FLA_GET_RANGE_PARAMS flaInfo;
@@ -381,7 +407,7 @@ struct _vgpu_static_info
NvU64 fbLength;
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams;
NvU32 grBufferSize[RPC_GR_BUFFER_TYPE_GRAPHICS_MAX];
NvU32 fbioMask;
NvU64 fbioMask;
NvBool bSplitVasBetweenServerClientRm;
NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH];
NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH];
@@ -393,7 +419,7 @@ struct _vgpu_static_info
VGPU_P2P_CAPABILITY_PARAMS p2pCaps;
NvU32 fbBusWidth;
NvU32 fbpMask;
NvU32 ltcMask;
NvU64 ltcMask;
NvU32 ltsCount;
NvU32 sizeL2Cache;
NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS zbcTableSizes[NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT];
@@ -414,8 +440,8 @@ typedef NV2080_CTRL_CE_GET_CAPS_V2_PARAMS VGPU_CE_GET_CAPS_V2[NV2080_ENGINE_TYPE
typedef struct GSP_FIRMWARE GSP_FIRMWARE;
ct_assert(NV2080_CTRL_GPU_ECC_UNIT_COUNT == NV2080_CTRL_GPU_ECC_UNIT_COUNT_v26_02);
ct_assert(NV2080_ENGINE_TYPE_LAST == 0x40);
ct_assert(NV2080_CTRL_GPU_ECC_UNIT_COUNT == NV2080_CTRL_GPU_ECC_UNIT_COUNT_v27_04);
ct_assert(NV2080_ENGINE_TYPE_LAST == 0x54);
ct_assert(NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE == NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09);
ct_assert(NV2080_CTRL_FB_FS_INFO_MAX_QUERIES == NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00);
ct_assert(NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE == NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D);
@@ -431,7 +457,7 @@ ct_assert(NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT == NV2080_CTRL_INTERNAL_MAX
ct_assert(NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS == NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F);
ct_assert(NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL == NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL_v16_03);
ct_assert(VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06 < NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL_v16_03);
ct_assert(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE == NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A);
ct_assert(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE == NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_27_00);
ct_assert(NV2080_CTRL_GPU_MAX_SMC_IDS == 8);
ct_assert(NV2080_GPU_MAX_GID_LENGTH == 0x000000100);
ct_assert(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES == 16);
@@ -467,5 +493,6 @@ ct_assert(RPC_GR_BUFFER_TYPE_GRAPHICS_MAX_v25_0E == RPC_GR_BUFFER_TYPE_GRAPHICS_
ct_assert(NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT_v1A_07 == NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT);
ct_assert(NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05 == NVC637_CTRL_MAX_EXEC_PARTITIONS);
ct_assert(NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11 == NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE);
ct_assert(NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX_v27_01 == NVGPU_VGPU_ENGINE_LIST_MASK_ARRAY_MAX);
#endif /*_RPC_SDK_STRUCTURES_H_*/

1
src/nvidia/inc/kernel/vgpu/vgpu_util.h
View File

@@ -41,6 +41,7 @@ NV_STATUS vgpuAllocSysmemPfnBitMapNode(OBJGPU *pGpu, VGPU_SYSMEM_PFN_BITMAP_NODE
NvU64 vgpuGspSysmemPfnMakeBufferAddress(MEMORY_DESCRIPTOR *pMemDesc, NvU64 pfn);
void vgpuFreeSysmemPfnBitMapNode(VGPU_SYSMEM_PFN_BITMAP_NODE_P node);
NV_STATUS vgpuUpdateSysmemPfnBitMap(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvBool bAlloc);
NV_STATUS vgpuUpdateGuestSysmemPfnBitMap(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvBool bAlloc);
static inline NvBool vgpuIsGuestManagedHwAlloc(OBJGPU *pGpu)
{

7
src/nvidia/inc/kernel/vgpu/vgpu_version.h
View File

@@ -30,8 +30,8 @@
#define RPC_VERSION_FROM_VGX_VERSION(major, minor) ( DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \
DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor))
#define VGX_MAJOR_VERSION_NUMBER 0x26
#define VGX_MINOR_VERSION_NUMBER 0x05
#define VGX_MAJOR_VERSION_NUMBER 0x27
#define VGX_MINOR_VERSION_NUMBER 0x06
#define VGX_MAJOR_VERSION_NUMBER_VGPU_12_0 0x1A
#define VGX_MINOR_VERSION_NUMBER_VGPU_12_0 0x18
@@ -51,6 +51,7 @@
* 2. This is the first break in migration compatibility after a release.
*/
#define NV_VGPU_GRIDSW_INTERNAL_TO_EXTERNAL_VERSION_MAPPING \
{{0x27, 0x0}, {0x27, 0x06}, {0x16, 0x1}}, \
{{0x26, 0x0}, {0x26, 0x05}, {0x15, 0x1}}, \
{{0x25, 0x0}, {0x25, 0x1B}, {0x14, 0x1}}, \
{{0x24, 0x0}, {0x24, 0x0A}, {0x13, 0x1}}, \
@@ -100,7 +101,7 @@
/* WARNING: Should be updated with each vGPU release, if there is a break in
* migration compatibility during the development of that release. */
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x15
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x16
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1
/* WARNING: Should be updated with each vGPU release, if minimum supported