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This commit is contained in:
Bernhard Stoeckner
2025-01-27 19:36:56 +01:00
parent 9d0b0414a5
commit 54d69484da
1166 changed files with 318863 additions and 182687 deletions
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73
src/common/displayport/inc/dp_configcaps.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -119,6 +119,12 @@ namespace DisplayPort
ITU709,
} ;
enum MainLinkChannelCoding
{
ChannelCoding8B10B = 0,
ChannelCoding128B132B,
};
#define HDCP_BCAPS_SIZE (0x1)
#define HDCP_VPRIME_SIZE (0x14)
#define HDCP_KSV_FIFO_SIZE (0xF)
@@ -162,6 +168,7 @@ namespace DisplayPort
//
virtual bool getLaneStatusClockRecoveryDone(int lane) = 0; // DPCD offset 202, 203
virtual bool getLaneStatusSymbolLock(int lane)= 0;
virtual bool getLaneStatusChannelEqualizationDone(int lane)= 0;
virtual bool getInterlaneAlignDone() = 0;
virtual bool getDownStreamPortStatusChange() = 0;
};
@@ -219,6 +226,7 @@ namespace DisplayPort
virtual AuxRetry::status setIgnoreMSATimingParamters(bool msaTimingParamIgnoreEn) = 0;
virtual AuxRetry::status setLinkQualLaneSet(unsigned lane, LinkQualityPatternType linkQualPattern) = 0;
virtual AuxRetry::status setLinkQualPatternSet(LinkQualityPatternType linkQualPattern, unsigned laneCount = 0) = 0;
virtual AuxRetry::status setLinkQualPatternSet(DP2xPatternInfo& patternInfo, unsigned laneCount = 0) = 0;
};
class LinkCapabilities
@@ -230,6 +238,12 @@ namespace DisplayPort
//
virtual NvU64 getMaxLinkRate() = 0; // Maximum byte-block in Hz
virtual unsigned getMaxLaneCount() = 0; // DPCD offset 0x0002h
//
// Bit mask for sink side (sink and LTTPR) supported UHBR Link Rates.
// Defines the same as NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS.UHBRSupportedByGpu and
// NV0073_CTRL_DFP_GET_INFO_PARAMS.UHBRSupportedByDfp
//
virtual NvU32 getUHBRSupported() = 0; // DPCD offset 0x2215h
virtual unsigned getMaxLaneCountSupportedAtLinkRate(LinkRate linkRate) = 0;
virtual bool getEnhancedFraming() = 0;
virtual bool getSupportsNoHandshakeTraining() = 0;
@@ -331,7 +345,7 @@ namespace DisplayPort
if (lttprGetRevisionMajor() > major)
return true;
if (lttprGetRevisionMinor() < major)
if (lttprGetRevisionMajor() < major)
return false;
return lttprGetRevisionMinor() >= minor;
@@ -432,7 +446,7 @@ namespace DisplayPort
// If set to HPD mode we'll always receive an HPD whenever the topology changes.
// The library supports using both modes.
//
virtual AuxRetry::status setMultistreamHotplugMode(MultistreamHotplugMode notifyType) = 0;
virtual AuxRetry::status setMultistreamHotplugMode(MultistreamHotplugMode notifyType) = 0;
//
// Interrupts
@@ -474,6 +488,10 @@ namespace DisplayPort
// DPCD offset 250 - 259
virtual void get80BitsCustomTestPattern(NvU8 *testPattern) = 0;
// DPCD offset 2230 - 2250
virtual void get264BitsCustomTestPattern(NvU8 *testPattern) = 0;
// DPCD offset 249
virtual void getSquarePatternNum(NvU8 *sqNum) = 0;
//
// Message Boxes
//
@@ -546,8 +564,12 @@ namespace DisplayPort
virtual bool clearDpTunnelingEstimatedBwStatus() = 0;
virtual bool clearDpTunnelingBwAllocationCapStatus() = 0;
virtual AuxRetry::status notifySDPErrDetectionCapability() = 0;
virtual bool isDp2xChannelCodingCapable() = 0;
virtual void setIgnoreCableIdCaps(bool bIgnore) = 0;
virtual void initialize() = 0;
virtual AuxRetry::status setMainLinkChannelCoding(MainLinkChannelCoding channelCoding) = 0;
virtual ~DPCDHAL() {}
};
//
@@ -652,7 +674,7 @@ namespace DisplayPort
bool bFECSupportedRepeater[NV_DPCD14_PHY_REPEATER_CNT_MAX];
// If all the LTTPRs supports FEC
bool bFECSupported;
bool bAuxlessALPMSupported; // DPCD offset F0009
} repeaterCaps;
struct
@@ -845,6 +867,10 @@ namespace DisplayPort
virtual LinkRate getMaxLinkRate();
virtual NvU32 getUHBRSupported()
{
return 0;
}
// DPCD offset 2
virtual unsigned getMaxLaneCount();
@@ -997,6 +1023,7 @@ namespace DisplayPort
virtual AuxRetry::status setIgnoreMSATimingParamters(bool msaTimingParamIgnoreEn);
virtual AuxRetry::status setLinkQualPatternSet(LinkQualityPatternType linkQualPattern, unsigned laneCount);
virtual AuxRetry::status setLinkQualPatternSet(DP2xPatternInfo& patternInfo, unsigned laneCount);
virtual AuxRetry::status setLinkQualLaneSet(unsigned lane, LinkQualityPatternType linkQualPattern);
virtual AuxRetry::status setMessagingEnable(bool _uprequestEnable, bool _upstreamIsSource);
@@ -1171,6 +1198,11 @@ namespace DisplayPort
return interrupts.laneStatusIntr.laneStatus[lane].clockRecoveryDone;
}
virtual bool getLaneStatusChannelEqualizationDone(int lane)
{
return interrupts.laneStatusIntr.laneStatus[lane].channelEqualizationDone;
}
virtual bool getInterlaneAlignDone() // DPCD offset 204
{
return interrupts.laneStatusIntr.interlaneAlignDone;
@@ -1225,6 +1257,20 @@ namespace DisplayPort
}
}
// DPCD offset 2230 - 2250
virtual void get264BitsCustomTestPattern(NvU8 *testPattern)
{
DP_ASSERT(0 && "DP1x should never get this request.");
return;
}
// DPCD offset 249h
virtual void getSquarePatternNum(NvU8 *sqNum)
{
DP_ASSERT(0 && "DP1x should never get this request.");
return;
}
virtual bool getBKSV(NvU8 *bKSV);
virtual bool getBCaps(BCaps &bCaps, NvU8 * rawByte);
virtual bool getHdcp22BCaps(BCaps &bCaps, NvU8 *rawByte);
@@ -1437,6 +1483,23 @@ namespace DisplayPort
bool clearDpTunnelingEstimatedBwStatus();
bool clearDpTunnelingBwAllocationCapStatus();
virtual AuxRetry::status notifySDPErrDetectionCapability()
{
return AuxRetry::ack;
}
virtual bool isDp2xChannelCodingCapable()
{
return false;
}
virtual void setIgnoreCableIdCaps(bool bIgnore)
{
return;
}
// implement this function if DPCDHALImpl needs updated state between hotunplug/plug
virtual void initialize(){};
virtual AuxRetry::status setMainLinkChannelCoding(MainLinkChannelCoding channelCoding){ return AuxRetry::ack; }
virtual MainLinkChannelCoding getMainLinkChannelCoding() { return ChannelCoding8B10B; }
};
}

148
src/common/displayport/inc/dp_configcaps2x.h Normal file
View File

@@ -0,0 +1,148 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort *******************************\
* *
* Module: dp_configcaps2x.h *
* Abstraction for DP2x caps registers *
* *
\***************************************************************************/
#ifndef INCLUDED_DP_CONFIGCAPS_2X_H
#define INCLUDED_DP_CONFIGCAPS_2X_H
#include "dp_configcaps.h"
namespace DisplayPort
{
enum CableType
{
CableTypeUnknown = 0,
CableTypePassive = 1,
CableTypeLRD = 2,
CableTypeActiveReTimer = 3,
};
struct DPCDHALImpl2x : DPCDHALImpl
{
struct
{
// 0x2206, if the sink supports 128b/132b
bool bDP2xChannelCodingSupported;
// 0x2215
bool bUHBR_10GSupported;
bool bUHBR_13_5GSupported;
bool bUHBR_20GSupported;
struct
{
// 0xF0006, if the PHY Repeater supports 128b/132b
bool bDP2xChannelCodingSupported;
// 0xF0007
bool bUHBR_10GSupported;
bool bUHBR_13_5GSupported;
bool bUHBR_20GSupported;
} repeaterCaps;
struct
{
bool bDP2xChannelCodingSupported;
bool bUHBR_10GSupported;
bool bUHBR_13_5GSupported;
bool bUHBR_20GSupported;
} dpInTunnelingCaps;
struct
{
bool bUHBR_10GSupported;
bool bUHBR_13_5GSupported;
bool bUHBR_20GSupported;
CableType cableType;
} cableCaps;
} caps2x;
struct
{
// DPCD offset 2230 - 2250
NvU8 cstm264Bits[NV_DPCD20_TEST_264BIT_CUSTOM_PATTERN__SIZE];
struct
{
bool testRequestPhyCompliance; // DPCD offset 218
LinkQualityPatternType phyTestPattern; // DPCD offset 248
//
// Only valid when phyTestPattern is
// LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON
// LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON
// LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF
// LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF
//
NvU32 sqNum; // DPCD offset 249
} testPhyCompliance2x;
} interrupts2x;
virtual AuxRetry::status notifySDPErrDetectionCapability();
virtual AuxRetry::status setMainLinkChannelCoding(MainLinkChannelCoding channelCoding);
virtual MainLinkChannelCoding getMainLinkChannelCoding();
void performCableIdHandshake();
virtual void setGpuDPSupportedVersions(NvU32 _gpuDPSupportedVersions);
virtual bool isDp2xChannelCodingCapable();
virtual void parseAndReadCaps();
virtual LinkRate getMaxLinkRate();
virtual NvU32 getUHBRSupported();
virtual void setIgnoreCableIdCaps(bool bIgnore){ bIgnoreCableIdCaps = bIgnore; }
virtual bool parseTestRequestPhy();
virtual bool parseTestRequestTraining(NvU8 * buffer);
// DPCD offset 2230 - 2250
virtual void get264BitsCustomTestPattern(NvU8 *testPattern);
// DPCD offset 249h
virtual void getSquarePatternNum(NvU8 *sqNum);
virtual AuxRetry::status setLinkQualLaneSet(unsigned lane, LinkQualityPatternType linkQualPattern);
virtual AuxRetry::status setLinkQualPatternSet(DP2xPatternInfo& patternInfo, unsigned laneCount);
// class fields that need re-initialization
bool bIgnoreCableIdCaps;
virtual void initialize()
{
setIgnoreCableIdCaps(false);
}
DPCDHALImpl2x(AuxBus * bus, Timer * timer) : DPCDHALImpl(bus, timer), bIgnoreCableIdCaps(false)
{
dpMemZero(&caps2x, sizeof(caps2x));
dpMemZero(&interrupts2x, sizeof(interrupts2x));
caps2x.bDP2xChannelCodingSupported = true;
caps2x.bUHBR_10GSupported = true;
caps2x.bUHBR_13_5GSupported = true;
caps2x.bUHBR_20GSupported = true;
caps2x.cableCaps.bUHBR_10GSupported = true;
caps2x.cableCaps.bUHBR_13_5GSupported = true;
caps2x.cableCaps.bUHBR_20GSupported = true;
};
};
}
#endif //INCLUDED_DP_CONFIGCAPS_2X_H

20
src/common/displayport/inc/dp_connector.h
View File

@@ -336,6 +336,18 @@ namespace DisplayPort
virtual bool setModeList(DisplayPort::DpModesetParams *pModeList, unsigned numModes) = 0;
virtual NvBool isSelectiveUpdateSupported(void) = 0;
virtual NvBool isEarlyRegionTpSupported(void) = 0;
virtual NvBool enableAdaptiveSyncSdp(NvBool enable) = 0;
virtual SelectiveUpdateCaps getSelectiveUpdateCaps(void) = 0;
virtual NvBool isAdaptiveSyncSdpNotSupportedInPr(void) = 0;
virtual NvBool isdscDecodeNotSupportedInPr(void) = 0;
virtual NvBool isLinkOffSupportedAfterAsSdpInPr(void) = 0;
virtual void getAlpmCaps(void) = 0;
virtual NvBool setAlpmConfig(AlpmConfig alpmcfg) = 0;
virtual NvBool getAlpmStatus(AlpmStatus *pAlpmStatus) = 0;
virtual NvBool isAuxLessAlpmSupported(void) = 0;
protected:
virtual ~Device() {}
@@ -731,6 +743,10 @@ namespace DisplayPort
// "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
virtual bool setLaneConfig(NvU32 numLanes, NvU32 *data) = 0;
// "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
virtual bool getDp2xLaneConfig(NvU32 *numLanes, NvU32 *data) = 0;
// "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
virtual bool setDp2xLaneConfig(NvU32 numLanes, NvU32 *data) = 0;
virtual DP_TESTMESSAGE_STATUS sendDPTestMessage(void *pBuffer,
NvU32 requestSize,
NvU32 *pDpStatus) = 0;
@@ -752,7 +768,9 @@ namespace DisplayPort
virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo) = 0;
virtual void enableDpTunnelingBwAllocationSupport() = 0;
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo) = 0;
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
const DscParams *pDscParams = NULL) = 0;
protected:
virtual ~Connector() {}

51
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -197,6 +197,8 @@ namespace DisplayPort
unsigned compoundQueryLocalLinkPBN;
NvU64 compoundQueryUsedTunnelingBw;
bool compoundQueryForceEnableFEC;
// WAR
bool bDP2XPreferNonDSCForLowPClk;
unsigned freeSlots;
unsigned maximumSlots;
@@ -262,7 +264,7 @@ namespace DisplayPort
bool bSkipLt;
// Flag to make sure that zombie gets triggred when a powerChange event happens
bool bMitigateZombie;
bool bMitigateZombie;
//
// HP Valor QHD+ N15P-Q3 EDP needs 50ms delay after D3
@@ -324,6 +326,9 @@ namespace DisplayPort
//
NvU32 LT2FecLatencyMs;
// On eDP, do not cache the source OUI if it reads 0. See bug 4793112
bool bSkipZeroOuiCache;
//
// Dual SST Partner connector object pointer
ConnectorImpl *pCoupledConnector;
@@ -384,8 +389,9 @@ namespace DisplayPort
DwnStreamPortAttribute portAttribute,
bool isCompliance = false);
void applyEdidWARs(Edid &edid, DiscoveryManager::Device device);
void applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatabase);
void applyEdidWARs(Edid &edid, DiscoveryManager::Device &device);
virtual void handleEdidWARs(Edid &edid, DiscoveryManager::Device &device){};
void applyRegkeyOverrides(const DP_REGKEY_DATABASE &dpRegkeyDatabase);
ResStatusNotifyMessage ResStatus;
@@ -406,13 +412,14 @@ namespace DisplayPort
bool detectSinkCountChange();
virtual bool handlePhyPatternRequest();
void applyOuiWARs();
virtual bool handleTestLinkTrainRequest();
virtual void applyOuiWARs();
bool linkUseMultistream()
{
return (linkState == DP_TRANSPORT_MODE_MULTI_STREAM);
}
void populateAllDpConfigs();
virtual void populateAllDpConfigs();
virtual LinkRates* importDpLinkRates();
//
@@ -564,7 +571,9 @@ namespace DisplayPort
virtual void notifyAttachEnd(bool modesetCancelled);
virtual void notifyDetachBegin(Group * target);
virtual void notifyDetachEnd(bool bKeepOdAlive = false);
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo);
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
const DscParams *pDscParams = NULL);
bool performIeeeOuiHandshake();
void setIgnoreSourceOuiHandshake(bool bIgnore);
@@ -599,7 +608,8 @@ namespace DisplayPort
}
bool trainLinkOptimized(LinkConfiguration lConfig);
bool trainLinkOptimizedSingleHeadMultipleSST(GroupImpl * group);
bool getValidLowestLinkConfig(LinkConfiguration &lConfig, LinkConfiguration &lowestSelected, ModesetInfo queryModesetInfo);
bool getValidLowestLinkConfig(LinkConfiguration &lConfig, LinkConfiguration &lowestSelected,
ModesetInfo queryModesetInfo, const DscParams *pDscParams = NULL);
bool postLTAdjustment(const LinkConfiguration &, bool force);
void populateUpdatedLaneSettings(NvU8* voltageSwingLane, NvU8* preemphasisLane, NvU32 *data);
void populateDscCaps(DSC_INFO* dscInfo, DeviceImpl * dev, DSC_INFO::FORCED_DSC_PARAMS* forcedParams);
@@ -634,6 +644,7 @@ namespace DisplayPort
bool deleteAllVirtualChannels();
void clearTimeslices();
virtual void applyTimeslotWAR(unsigned &slot_count){};
virtual bool allocateTimeslice(GroupImpl * targetGroup);
void freeTimeslice(GroupImpl * targetGroup);
void flushTimeslotsToHardware();
@@ -647,9 +658,9 @@ namespace DisplayPort
void handleDpTunnelingIrq();
void handleHdmiLinkStatusChanged();
void sortActiveGroups(bool ascending);
void configInit();
void handlePanelReplayError();
virtual void configInit();
virtual DeviceImpl* findDeviceInList(const Address &address);
virtual void disconnectDeviceList();
void notifyLongPulseInternal(bool statusConnected);
@@ -666,7 +677,7 @@ namespace DisplayPort
virtual bool isFECSupported();
virtual bool isFECCapable();
virtual NvU32 maxLinkRateSupported();
bool setPreferredLinkConfig(LinkConfiguration &lc, bool commit,
bool setPreferredLinkConfig(LinkConfiguration &lc, bool commit,
bool force = false,
LinkTrainingType trainType = NORMAL_LINK_TRAINING,
bool forcePreferredLinkConfig = false);
@@ -689,6 +700,28 @@ namespace DisplayPort
bool setTestPattern(NV0073_CTRL_DP_TESTPATTERN testPattern, NvU8 laneMask, NV0073_CTRL_DP_CSTM cstm, NvBool bIsHBR2, NvBool bSkipLaneDataOverride = false);
bool getLaneConfig(NvU32 *numLanes, NvU32 *data); // "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
bool setLaneConfig(NvU32 numLanes, NvU32 *data); // "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
// "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
virtual bool getDp2xLaneConfig(NvU32 *numLanes, NvU32 *data)
{
// The function is only for Connector class 2x (or later) that supports 128b/132b channel coding.
return false;
}
// "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
virtual bool setDp2xLaneConfig(NvU32 numLanes, NvU32 *data)
{
// The function is only for Connector class 2x (or later) that supports 128b/132b channel coding.
return false;
}
virtual void setDisableDownspread(bool _bDisableDownspread)
{
return;
}
virtual bool getDownspreadDisabled()
{
return false;
}
void getCurrentLinkConfig(unsigned &laneCount, NvU64 &linkRate); // CurrentLink Configuration
unsigned getPanelDataClockMultiplier();
unsigned getGpuDataClockMultiplier();

111
src/common/displayport/inc/dp_connectorimpl2x.h Normal file
View File

@@ -0,0 +1,111 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* DisplayPort********************************\
* *
* Module: dp_connectorimpl2x.cpp *
* DP connector implementation for DP2.x *
* *
\***************************************************************************/
#ifndef INCLUDED_DP_CONNECTORIMPL2X_H
#define INCLUDED_DP_CONNECTORIMPL2X_H
#include "dp_connector.h"
#include "ctrl/ctrl0073/ctrl0073dp.h"
namespace DisplayPort
{
struct ConnectorImpl2x : public ConnectorImpl
{
virtual void configInit();
virtual void populateAllDpConfigs();
virtual LinkRates* importDpLinkRates();
virtual LinkConfiguration getMaxLinkConfig();
virtual bool train(const LinkConfiguration & lConfig, bool force,
LinkTrainingType trainType = NORMAL_LINK_TRAINING);
virtual bool allocateTimeslice(GroupImpl * targetGroup);
virtual bool checkIsModePossibleMST(GroupImpl * group);
virtual bool compoundQueryAttachMSTGeneric(Group * target,
const DpModesetParams &modesetParams, // Modeset info
CompoundQueryAttachMSTInfo * info, // local info with updates for DSC
DscParams *pDscParams = NULL, // DSC parameters
DP_IMP_ERROR *pErrorCode = NULL); // Error Status code
virtual bool notifyAttachBegin(Group *target, const DpModesetParams &modesetParams);
virtual void notifyAttachEnd(bool modesetCancelled);
virtual void notifyDetachBegin(Group *target);
virtual void notifyDetachEnd(bool bKeepOdAlive);
virtual bool beforeAddStream(GroupImpl * group, bool test = false, bool forFlushMode = false);
virtual void afterAddStream(GroupImpl * group);
virtual void beforeDeleteStream(GroupImpl * group, bool forFlushMode);
virtual void afterDeleteStream(GroupImpl * group);
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo,
const DscParams *pDscParams = NULL);
bool willLinkSupportMode(const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo,
NvU32 headIndex = 0, Watermark *watermark = NULL, const DscParams *pDscParams = NULL);
virtual bool handlePhyPatternRequest();
virtual bool handleTestLinkTrainRequest();
ConnectorImpl2x(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink);
bool validateLinkConfiguration(const LinkConfiguration & lConfig);
bool enableFlush();
void disableFlush(bool test = false);
// "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
virtual bool getDp2xLaneConfig(NvU32 *numLanes, NvU32 *data);
virtual bool setDp2xLaneConfig(NvU32 numLanes, NvU32 *data);
void applyDP2xRegkeyOverrides();
virtual void applyOuiWARs();
virtual void handleEdidWARs(Edid &edid, DiscoveryManager::Device &device);
virtual void applyTimeslotWAR(unsigned &slot_count);
bool bSupportUHBR2_50; // Support UHBR2.5 for internal testing.
bool bSupportUHBR2_70; // Support UHBR2.7 for internal testing.
bool bSupportUHBR5_00; // Support UHBR5.0 for internal testing.
bool bFlushSkipped;
bool bMstTimeslotBug4968411;
bool bApplyManualTimeslotBug4968411;
// Do not enable downspread while link training.
bool bDisableDownspread;
virtual void setDisableDownspread(bool _bDisableDownspread)
{
this->bDisableDownspread = _bDisableDownspread;
}
virtual bool getDownspreadDisabled()
{
return this->bDisableDownspread;
}
};
}
#endif //INCLUDED_DP_CONNECTORIMPL2X_H

13
src/common/displayport/inc/dp_deviceimpl.h
View File

@@ -172,6 +172,8 @@ namespace DisplayPort
// Panel replay Caps
PanelReplayCaps prCaps;
// ALPM caps
AlpmCaps alpmCaps;
bool bIsFakedMuxDevice;
bool bIsPreviouslyFakedMuxDevice;
bool bisMarkedForDeletion;
@@ -455,6 +457,17 @@ namespace DisplayPort
bool setPanelReplayConfig(panelReplayConfig prcfg);
bool getPanelReplayConfig(panelReplayConfig *pPrcfg);
bool getPanelReplayStatus(PanelReplayStatus *pPrStatus);
NvBool isSelectiveUpdateSupported(void);
NvBool isEarlyRegionTpSupported(void);
NvBool enableAdaptiveSyncSdp(NvBool enable);
SelectiveUpdateCaps getSelectiveUpdateCaps(void);
NvBool isAdaptiveSyncSdpNotSupportedInPr(void);
NvBool isdscDecodeNotSupportedInPr(void);
NvBool isLinkOffSupportedAfterAsSdpInPr(void);
void getAlpmCaps(void);
NvBool setAlpmConfig(AlpmConfig alpmcfg);
NvBool getAlpmStatus(AlpmStatus *pAlpmStatus);
NvBool isAuxLessAlpmSupported(void);
NvBool getDSCSupport();
bool getFECSupport();

3
src/common/displayport/inc/dp_edid.h
View File

@@ -166,6 +166,9 @@ namespace DisplayPort
bool keepLinkAlive;
bool useLegacyAddress;
bool bIgnoreDscCap; // Ignore DSC even if sink reports DSC capability
bool bDisableDownspread;
bool bSkipCableIdCheck;
bool bAllocateManualTimeslots;
}_WARFlags;
_WARFlags WARFlags;

33
src/common/displayport/inc/dp_evoadapter.h
View File

@@ -135,8 +135,8 @@ namespace DisplayPort
{
private:
NvU32 _maxLinkRateSupportedGpu;
NvU32 _minPClkForCompressed;
NvU32 _maxLinkRateSupportedDfp;
unsigned allHeadMask;
bool _hasIncreasedWatermarkLimits;
bool _hasMultistream;
bool _isPC2Disabled;
@@ -188,10 +188,13 @@ namespace DisplayPort
NvU32 displayId;
NvU32 subdeviceIndex;
unsigned allHeadMask;
NV0073_CTRL_DFP_GET_INFO_PARAMS dfpParams;
NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS dpParams;
bool _isDownspreadDisabledByRegkey;
public:
EvoMainLink(EvoInterface * provider, Timer * timer);
@@ -210,10 +213,19 @@ namespace DisplayPort
return _isPC2Disabled;
}
virtual NvU32 getMinPClkForCompressed()
{
return _minPClkForCompressed;
}
virtual NvU32 getGpuDpSupportedVersions()
{
return _gpuSupportedDpVersions;
}
virtual NvU32 getUHBRSupported()
{
return 0U;
}
virtual bool isFECSupported()
{
return _isFECSupported;
@@ -235,9 +247,9 @@ namespace DisplayPort
if ((_applyLinkBwOverrideWarRegVal || _useDfpMaxLinkRateCaps) &&
(_maxLinkRateSupportedDfp < _maxLinkRateSupportedGpu))
{
return (LINK_RATE_TO_DATA_RATE_8B_10B(_maxLinkRateSupportedDfp));
return _maxLinkRateSupportedDfp;
}
return (LINK_RATE_TO_DATA_RATE_8B_10B(_maxLinkRateSupportedGpu));
return _maxLinkRateSupportedGpu;
}
virtual bool isForceRmEdidRequired()
@@ -326,9 +338,12 @@ namespace DisplayPort
// Return the current mux state. Returns false if device is not mux capable
bool getDynamicMuxState(NvU32 *muxState);
virtual bool aquireSema();
virtual void releaseSema();
virtual bool physicalLayerSetTestPattern(PatternInfo * patternInfo);
virtual bool physicalLayerSetDP2xTestPattern(DP2xPatternInfo *patternInfo)
{
DP_ASSERT(0 && "DP1x should never get this request.");
return false;
}
virtual void preLinkTraining(NvU32 head);
virtual void postLinkTraining(NvU32 head);
virtual NvU32 getRegkeyValue(const char *key);
@@ -354,9 +369,7 @@ namespace DisplayPort
void configureHDCPGetHDCPState(HDCPState &hdcpState);
bool rmUpdateDynamicDfpCache(NvU32 headIndex, RmDfpCache * dfpCache, NvBool bResetDfp);
virtual NvU32 streamToHead(NvU32 streamId, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
virtual NvU32 headToStream(NvU32 head, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
virtual NvU32 headToStream(NvU32 head, bool bSidebandMessageSupported, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
void configureSingleStream(NvU32 head,
NvU32 hBlankSym,
@@ -412,6 +425,10 @@ namespace DisplayPort
bool freeDisplayId(NvU32 displayId);
virtual bool queryAndUpdateDfpParams();
virtual bool queryGPUCapability();
virtual void updateFallbackMap(NvU32 maxLaneCount, LinkRate maxLinkRate, NvU32 sinkUhbrCaps = 0)
{
return;
}
bool getEdpPowerData(bool *panelPowerOn, bool *dpcdPowerStateD0);
virtual bool vrrRunEnablementStage(unsigned stage, NvU32 *status);

176
src/common/displayport/inc/dp_evoadapter2x.h Normal file
View File

@@ -0,0 +1,176 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************* List **************************************\
* *
* Module: dp_evoadapter2x.h *
* Interface for low level access to the aux bus for dp2x. *
* This is the synchronous version of the interface. *
* *
\***************************************************************************/
#ifndef INCLUDED_DP_EVOADAPTER2X_H
#define INCLUDED_DP_EVOADAPTER2X_H
#include "dp_evoadapter.h"
#include "dp_timeout.h"
#include "dp_linkconfig.h"
// For channel equalization, total poll time is 450ms. Set it to 500ms for timer granularity
#define NV_DP2X_LT_MAX_TIME_POLL_CHNL_EQ_MS (500U)
// For channel equalization, max loop count is 20 when waiting CHANNEL_EQ_DONE set.
#define NV_DP2X_LT_MAX_LOOP_COUNT_POLL_CHNL_EQ_DONE (20U)
// For channel equalization, polling interval is 3 when waiting INTERLANE_ALIGN_DONE.
#define NV_DP2X_LT_CHNL_EQ_INTERLANE_ALIGN_POLLING_INTERVAL (3U)
// Unit definitions for Aux Read Intervals
#define NV_DP2X_LT_CHNL_EQ_TRAINING_AUX_RD_INTERVAL_UNIT_1MS (1U)
#define NV_DP2X_LT_CHNL_EQ_TRAINING_AUX_RD_INTERVAL_UNIT_2MS (2U)
// For phase CDS, total time is (LTTPR + 1) * 20
#define NV_DP2X_LT_MAX_POLL_TIME_CDS_MS(i) ((i+1) * 20)
#define NV_DP2X_LT_CDS_POLLING_INTERVAL 3U
//
// Total possible link configurations for DP2.x fallback table.
// Total number of link rates supported is 15:
// 3 UHBR: UHBR20, UHBR13.5, UHBR10
// 3 UHBR for internal test:
// UHBR2.5, UHBR2.7, UHBR5.0
// 4 Legacy: HBR3, HBR2, HBR, RBR
// 5 ILR: 2.16G, 2.43G, 3.24G, 4.32G, 6.75G
// Total number of lane count supported is 3 (1, 2, 4)
// Total possible link configurations => 15 * 3 = 45.
//
#define NV_DP2X_VALID_LINK_CONFIGURATION_COUNT 45U
namespace DisplayPort
{
// Simplified LinkConfiguration for fallback map
typedef struct
{
NvU32 laneCount;
// 10M unit
LinkRate linkRate;
//
// The flag indicates if the link configuration is avaiable on the setup.
// Both link count and link rate have to be supported.
//
bool bSupported;
//
// The flag indicates if the link rate can be trained with 128b/132b channel
// coding. Default false for non-UHBR link rates.
//
bool bUseDP2xChannelCoding;
} SIMPLIFIED_DP2X_LINKCONFIG;
typedef struct
{
DP2X_RESET_LINK_REASON reason;
bool bForce;
} DP2XResetParam;
class EvoMainLink2x : public EvoMainLink
{
//
// Bit mask for GPU/DFP supported UHBR Link Rates.
// Defines the same as NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS.UHBRSupportedByGpu and
// NV0073_CTRL_DFP_GET_INFO_PARAMS.UHBRSupportedByDfp
//
NvU32 gpuUhbrCaps;
NvU32 dfpUhbrCaps;
bool bUseRgFlushSequence;
bool bSupportUHBR2_50; // Support UHBR2.5 for internal testing.
bool bSupportUHBR2_70; // Support UHBR2.7 for internal testing.
bool bSupportUHBR5_00; // Support UHBR5.0 for internal testing.
// Start time of DP2.x LT Channel Eqaulization phase.
NvU64 channelEqualizationStartTimeUs;
bool pollDP2XLinkTrainingStageDone(NvU32 stage, NvU32 laneCount,
NvU32 phyRepeaterCount, NvU32 pollingInterval, bool force);
//
// Find next available link configuration in fallback mandate.
// Return false if not available
//
bool getFallbackForDP2xLinkTraining(LinkConfiguration *link);
//
// Check if the link configuration is supported on the system,
// and with correct channel encoding.
// Return false if not.
//
bool isSupportedDPLinkConfig(LinkConfiguration &link);
// Before link training start, reset DPRX link and make sure it's ready.
bool resetDPRXLink(DP2XResetParam param);
SIMPLIFIED_DP2X_LINKCONFIG fallbackMandateTable[NV_DP2X_VALID_LINK_CONFIGURATION_COUNT];
NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS ltRmParams;
public:
virtual bool queryGPUCapability();
virtual bool queryAndUpdateDfpParams();
virtual void updateFallbackMap(NvU32 maxLaneCount, LinkRate maxLinkRate, NvU32 uhbrCaps = 0);
virtual bool configureLinkRateTable(const NvU16 *pLinkRateTable, LinkRates *pLinkRates);
void validateIlrInFallbackMap(LinkRate ilr, bool bUseDP2xChannelCoding);
virtual NvU32 maxLinkRateSupported();
virtual bool setFlushMode(FlushModePhase phase);
virtual bool clearFlushMode(FlushModePhase phase, NvU32 attachFailedHeadMask = 0, NvU32 headIndex = 0);
virtual bool isRgFlushSequenceUsed() {return bUseRgFlushSequence;}
void applyDP2xRegkeyOverrides();
virtual NvU32 headToStream(NvU32 head, bool bSidebandMessageSupported, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY);
// Link Rate will return the value with 10M convention!
virtual void getLinkConfig(unsigned &laneCount, NvU64 & linkRate);
virtual NvU32 getUHBRSupported(void)
{
return (gpuUhbrCaps & dfpUhbrCaps);
}
virtual bool train(const LinkConfiguration & link, bool force,
LinkTrainingType linkTrainingType,
LinkConfiguration *retLink, bool bSkipLt = false,
bool isPostLtAdjRequestGranted = false,
unsigned phyRepeaterCount = 0);
bool trainDP2xChannelCoding(LinkConfiguration & link, bool force,
LinkTrainingType linkTrainingType,
LinkConfiguration *retLink,
bool bSkipLt, bool isPostLtAdjRequestGranted,
unsigned phyRepeaterCount);
EvoMainLink2x(EvoInterface *provider, Timer * timer);
virtual bool getDp2xLaneData(NvU32 *numLanes, NvU32 *data);
virtual bool setDp2xLaneData(NvU32 numLanes, NvU32 *data);
virtual bool physicalLayerSetDP2xTestPattern(DP2xPatternInfo *patternInfo);
};
}
#endif // INCLUDED_DP_EVOADAPTER_H

12
src/common/displayport/inc/dp_groupimpl.h
View File

@@ -74,13 +74,13 @@ namespace DisplayPort
headInFirmware(false),
bIsHeadShutdownNeeded(true),
hdcpEnabled(false),
hdcpPreviousStatus(false),
hdcpPreviousStatus(false),
bWaitForDeAllocACT(false),
dscModeRequest(DSC_MODE_NONE),
dscModeActive(DSC_MODE_NONE),
singleHeadMultiStreamID(DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY),
singleHeadMultiStreamMode(DP_SINGLE_HEAD_MULTI_STREAM_MODE_NONE),
headAttached(false)
headAttached(false), timeslotAllocated(false)
{
timeslot.count = 0;
}
@@ -96,7 +96,7 @@ namespace DisplayPort
virtual Device * enumDevices(Device * previousDevice);
void updateVbiosScratchRegister(Device * lastDevice); // Update the VBIOS scratch register with last lit display
//
// Timer callback tags.
// (we pass the address of these variables as context to ::expired)
@@ -114,8 +114,12 @@ namespace DisplayPort
bool isHeadAttached() { return headAttached; }
void setHeadAttached(bool attached);
bool isTimeslotAllocated() { return timeslotAllocated; }
void setTimeslotAllocated(bool allocated) {timeslotAllocated = allocated;}
private:
bool headAttached; // True if modeset started (during NAB). Sets back to False during NDE
bool headAttached; // True if modeset started (during NAB). Sets back to False during NDE
bool timeslotAllocated; // True if timeslot is allocated for the group (beforeAddStream). Sets back to False during afterDeleteStream
};
}

198
src/common/displayport/inc/dp_linkconfig.h
View File

@@ -36,7 +36,9 @@
#include "ctrl/ctrl0073/ctrl0073specific.h" // NV0073_CTRL_HDCP_VPRIME_SIZE
#include "displayport.h"
#define NV_SUPPORTED_DP_LINK_RATES__SIZE NV_SUPPORTED_DP1X_LINK_RATES__SIZE
#include "displayport2x.h"
#define NV_SUPPORTED_DP_LINK_RATES__SIZE NV_SUPPORTED_DP2X_LINK_RATES__SIZE
extern NvU32 bSupportInternalUhbrOnFpga;
namespace DisplayPort
{
typedef NvU64 LinkRate;
@@ -66,9 +68,11 @@ namespace DisplayPort
}
}
// Only use import if element can be added at the end
// given element list needs to be sorted
bool import(NvU16 linkBw)
{
if (!IS_VALID_LINKBW_10M(linkBw))
if (!IS_VALID_DP2_X_LINKBW(linkBw))
{
DP_ASSERT(0 && "Unsupported Link Bandwidth");
return false;
@@ -84,6 +88,48 @@ namespace DisplayPort
return false;
}
// Use insert to import to the right spot in the sorted
// element list if you are not sure of where linkBw is compared
// to existing entries in the element list
bool insert(NvU16 linkBw)
{
if (!IS_VALID_DP2_X_LINKBW(linkBw))
{
DP_ASSERT(0 && "Unsupported Link Bandwidth");
return false;
}
for (int i = 0; i < entries; i++)
{
if (element[i] == linkBw)
{
// element already present, nothing to do here
return true;
}
else if (element[i] > linkBw)
{
// make space for the new element
if (entries >= NV_SUPPORTED_DP_LINK_RATES__SIZE) {
DP_ASSERT(0 && "No more space for adding additional link rate");
return false;
}
for (int j = entries-1; j >= i; j--)
{
element[j+1] = element[j];
}
entries++;
// space is made, insert linkBw to the right spot
element[i] = linkBw;
return true;
}
}
// if we are here and not returned, that means linkBw is bigger than
// the current entries, just import
return import(linkBw);
}
LinkRate getLowerRate(LinkRate rate)
{
int i;
@@ -173,7 +219,14 @@ namespace DisplayPort
EDP_3_24GHZ = 324000000,
EDP_4_32GHZ = 432000000,
HBR2 = 540000000,
HBR3 = 810000000
EDP_6_75GHZ = 675000000,
HBR3 = 810000000,
UHBR_2_50GHZ = 303030303, // 2.5G * (128 / 132) / 8
UHBR_2_70GHZ = 327272727, // 2.7G * (128 / 132) / 8
UHBR_5_00GHZ = 606060606, // 5.0G * (128 / 132) / 8
UHBR_10_0GHZ = 1212121212, // 10.0G * (128 / 132) / 8
UHBR_13_5GHZ = 1636363636, // 13.5G * (128 / 132) / 8
UHBR_20_0GHZ = 2424242424 // 20.0G * (128 / 132) / 8
};
struct HDCPState
@@ -222,6 +275,8 @@ namespace DisplayPort
bool disablePostLTRequest;
bool bEnableFEC;
bool bDisableLTTPR;
bool bDisableDownspread;
bool bIs128b132bChannelCoding;
//
// The counter to record how many times link training happens.
// Client can reset the counter by calling setLTCounter(0)
@@ -231,12 +286,16 @@ namespace DisplayPort
LinkConfiguration() :
lanes(0), peakRatePossible(0), peakRate(0), minRate(0),
enhancedFraming(false), multistream(false), disablePostLTRequest(false),
bEnableFEC(false), bDisableLTTPR(false),
bEnableFEC(false), bDisableLTTPR(false), bDisableDownspread(false),
bIs128b132bChannelCoding(false),
linkTrainCounter(0) {};
LinkConfiguration(LinkPolicy * p, unsigned lanes, LinkRate peakRate,
bool enhancedFraming, bool MST, bool disablePostLTRequest = false,
bool bEnableFEC = false, bool bDisableLTTPR = false);
bool enhancedFraming, bool MST,
bool disablePostLTRequest = false,
bool bEnableFEC = false,
bool bDisableLTTPR = false,
bool bDisableDownspread = false);
void setLTCounter(unsigned counter)
{
@@ -252,7 +311,14 @@ namespace DisplayPort
NvU64 convertLinkRateToDataRate(LinkRate linkRate) const
{
NvU64 dataRate;
dataRate = LINK_RATE_TO_DATA_RATE_8B_10B(linkRate);
if (bIs128b132bChannelCoding)
{
dataRate = LINK_RATE_TO_DATA_RATE_128B_132B(linkRate);
}
else
{
dataRate = LINK_RATE_TO_DATA_RATE_8B_10B(linkRate);
}
return dataRate;
}
@@ -260,7 +326,14 @@ namespace DisplayPort
NvU64 convertMinRateToDataRate() const
{
NvU64 dataRate;
dataRate = DP_LINK_RATE_BITSPS_TO_BYTESPS(OVERHEAD_8B_10B(minRate));
if (bIs128b132bChannelCoding)
{
dataRate = DP_LINK_RATE_BITSPS_TO_BYTESPS(DATA_BW_EFF_128B_132B(minRate));
}
else
{
dataRate = DP_LINK_RATE_BITSPS_TO_BYTESPS(OVERHEAD_8B_10B(minRate));
}
return dataRate;
}
@@ -269,22 +342,28 @@ namespace DisplayPort
return (convertLinkRateToDataRate(peakRate) * lanes);
}
NvU64 linkOverhead(NvU64 rate)
NvU64 linkOverhead(NvU64 rate10M)
{
if(IS_VALID_LINKBW_10M(rate))
NvU64 rate;
if(IS_VALID_DP2_X_LINKBW(rate10M))
{
// Converting here so that minRate from 10M is converted to bps
rate = DP_LINK_RATE_10M_TO_BPS(rate);
rate = DP_LINK_RATE_10M_TO_BPS(rate10M);
}
else
{
// Convert from data rate to bps
rate = DATA_RATE_8B_10B_TO_LINK_RATE_BPS(rate);
rate = DATA_RATE_8B_10B_TO_LINK_RATE_BPS(rate10M);
}
if(IS_DP2_X_UHBR_LINKBW(rate10M))
{
// Consider downspread only. FEC is already considered
// in 128b/132b channel encoding
return rate - 6 * rate/ 1000;
}
if(bEnableFEC)
{
// if FEC is enabled, we have to account for 3% overhead
// for FEC+downspread according to DP 1.4 spec
@@ -295,7 +374,6 @@ namespace DisplayPort
// if FEC is not enabled, link overhead comprises only of
// 0.6% downspread.
return rate - 6 * rate/ 1000;
}
}
@@ -312,6 +390,8 @@ namespace DisplayPort
disablePostLTRequest(false),
bEnableFEC(false),
bDisableLTTPR(false),
bDisableDownspread(false),
bIs128b132bChannelCoding(false),
linkTrainCounter(0)
{
//
@@ -432,6 +512,42 @@ namespace DisplayPort
minRate = linkOverhead(dp2LinkRate_8_10Gbps);
lanes = 4;
}
else if (TotalLinkPBN <= 3878)
{
peakRatePossible = dp2LinkRate_13_5Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_13_5Gbps);
lanes = 2;
bEnableFEC = true;
bIs128b132bChannelCoding = true;
}
else if (TotalLinkPBN <= 5746)
{
peakRatePossible = dp2LinkRate_10_0Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_10_0Gbps);
lanes = 4;
bEnableFEC = true;
bIs128b132bChannelCoding = true;
}
else if (TotalLinkPBN <= 7757)
{
peakRatePossible = dp2LinkRate_13_5Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_13_5Gbps);
lanes = 4;
bEnableFEC = true;
bIs128b132bChannelCoding = true;
}
else if (TotalLinkPBN <= 11492)
{
peakRatePossible = dp2LinkRate_20_0Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_20_0Gbps);
lanes = 4;
bEnableFEC = true;
bIs128b132bChannelCoding = true;
}
else
{
peakRatePossible = dp2LinkRate_1_62Gbps;
@@ -454,11 +570,19 @@ namespace DisplayPort
bool lowerConfig(bool bReduceLaneCnt = false);
void setChannelCoding();
void setChannelCoding(bool bIs128b132bChannelCoding)
{
this->bIs128b132bChannelCoding = bIs128b132bChannelCoding;
}
void setLaneRate(LinkRate newRate, unsigned newLanes)
{
peakRate = newRate;
lanes = newLanes;
minRate = linkOverhead(peakRate);
setChannelCoding();
}
unsigned pbnTotal()
@@ -466,45 +590,13 @@ namespace DisplayPort
return PBNForSlots(totalUsableTimeslots);
}
void pbnRequired(const ModesetInfo & modesetInfo, unsigned & base_pbn, unsigned & slots, unsigned & slots_pbn)
{
base_pbn = pbnForMode(modesetInfo);
if (bEnableFEC)
{
// IF FEC is enabled, we need to consider 3% overhead as per DP1.4 spec.
base_pbn = (NvU32)(divide_ceil(base_pbn * 100, 97));
}
slots = slotsForPBN(base_pbn);
slots_pbn = PBNForSlots(slots);
}
NvU64 getBytesPerTimeslot();
NvU32 slotsForPBN(NvU32 allocatedPBN, bool usable = false)
{
NvU64 bytes_per_pbn = 54 * 1000000 / 64; // this comes out exact
NvU64 bytes_per_timeslot = getTotalDataRate() / 64;
void pbnRequired(const ModesetInfo & modesetInfo, unsigned & base_pbn, unsigned & slots, unsigned & slots_pbn);
if (bytes_per_timeslot == 0)
return (NvU32)-1;
NvU32 slotsForPBN(NvU32 allocatedPBN, bool usable = false);
if (usable)
{
// round down to find the usable integral slots for a given value of PBN.
NvU32 slots = (NvU32)divide_floor(allocatedPBN * bytes_per_pbn, bytes_per_timeslot);
DP_ASSERT(slots <= 64);
return slots;
}
else
return (NvU32)divide_ceil(allocatedPBN * bytes_per_pbn, bytes_per_timeslot);
}
NvU32 PBNForSlots(NvU32 slots) // Rounded down
{
NvU64 bytes_per_pbn = 54 * 1000000 / 64; // this comes out exact
NvU64 bytes_per_timeslot = getTotalDataRate() / 64;
return (NvU32)(bytes_per_timeslot * slots/ bytes_per_pbn);
}
NvU32 PBNForSlots(NvU32 slots);
bool operator!= (const LinkConfiguration & right) const
{
@@ -536,5 +628,11 @@ namespace DisplayPort
}
};
#define IS_DP2X_UHBR_LINK_DATA_RATE(val) (((NvU32)(val) == dp2LinkRate_2_50Gbps) || \
((NvU32)(val) == dp2LinkRate_2_70Gbps && bSupportInternalUhbrOnFpga) || \
((NvU32)(val) == dp2LinkRate_5_00Gbps) || \
((NvU32)(val) == dp2LinkRate_10_0Gbps) || \
((NvU32)(val) == dp2LinkRate_13_5Gbps) || \
((NvU32)(val) == dp2LinkRate_20_0Gbps))
}
#endif //INCLUDED_DP_LINKCONFIG_H

50
src/common/displayport/inc/dp_mainlink.h
View File

@@ -67,6 +67,18 @@ namespace DisplayPort
LINK_QUAL_80BIT_CUST,
LINK_QUAL_HBR2_COMPLIANCE_EYE,
LINK_QUAL_CP2520PAT3,
LINK_QUAL_128B132B_TPS1,
LINK_QUAL_128B132B_TPS2,
LINK_QUAL_PRBS9,
LINK_QUAL_PRBS11,
LINK_QUAL_PRBS15,
LINK_QUAL_PRBS23,
LINK_QUAL_PRBS31,
LINK_QUAL_264BIT_CUST,
LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON,
LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON,
LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF,
LINK_QUAL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF,
};
typedef struct
@@ -84,6 +96,19 @@ namespace DisplayPort
int ctsmUpper;
} PatternInfo;
typedef struct
{
LinkQualityPatternType lqsPattern;
//
// DP CSTM Test Pattern data
// For 264 bits: ctsmData[0]-ctsmData[32]
// padding: ctsmData[33-35]
//
NvU8 ctsmData[36];
NvU8 sqNum;
} DP2xPatternInfo;
typedef struct
{
unsigned char bcaps;
@@ -99,10 +124,17 @@ namespace DisplayPort
FAST_LINK_TRAINING,
}LinkTrainingType;
typedef enum
{
FlushModePhase1,
FlushModePhase2,
} FlushModePhase;
class MainLink : virtual public Object
{
public:
virtual bool physicalLayerSetTestPattern(PatternInfo * patternInfo) = 0;
virtual bool physicalLayerSetDP2xTestPattern(DP2xPatternInfo * patternInfo) = 0;
//
// Wrappers for existing link training RM control calls
//
@@ -174,7 +206,10 @@ namespace DisplayPort
virtual bool hasMultistream() = 0;
virtual bool isPC2Disabled() = 0;
virtual NvU32 getGpuDpSupportedVersions() = 0;
virtual NvU32 getUHBRSupported() {return 0;}
virtual bool isRgFlushSequenceUsed() {return false;}
virtual bool isStreamCloningEnabled() = 0;
virtual NvU32 getMinPClkForCompressed() = 0;
virtual NvU32 maxLinkRateSupported() = 0;
virtual bool isLttprSupported() = 0;
virtual bool isFECSupported() = 0;
@@ -191,9 +226,7 @@ namespace DisplayPort
virtual void triggerACT() = 0;
virtual void configureHDCPGetHDCPState(HDCPState &hdcpState) = 0;
virtual NvU32 streamToHead(NvU32 streamId,
DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY) = 0;
virtual NvU32 headToStream(NvU32 head,
virtual NvU32 headToStream(NvU32 head, bool bSidebandMessageSupported,
DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY) = 0;
virtual void configureSingleStream(NvU32 head,
@@ -246,6 +279,17 @@ namespace DisplayPort
virtual bool freeDisplayId(NvU32 displayId) = 0;
virtual bool queryGPUCapability() {return false;}
virtual bool queryAndUpdateDfpParams() = 0;
virtual void updateFallbackMap(NvU32 maxLaneCount, LinkRate maxLinkRate, NvU32 sinkUhbrCaps = 0) { return; }
virtual bool setFlushMode(FlushModePhase phase) { return false; }
virtual bool clearFlushMode(FlushModePhase phase, NvU32 attachFailedHeadMask = 0, NvU32 headIndex = 0) { return false; }
virtual bool getDp2xLaneData(NvU32 *numLanes, NvU32 *data)
{
return false;
}
virtual bool setDp2xLaneData(NvU32 numLanes, NvU32 *data)
{
return false;
}
virtual bool getEdpPowerData(bool *panelPowerOn, bool *bDPCDPowerStateD0) = 0;
virtual bool vrrRunEnablementStage(unsigned stage, NvU32 *status) = 0;

30
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -35,7 +35,7 @@
// Regkey Names
#define NV_DP_REGKEY_OVERRIDE_DPCD_REV "OVERRIDE_DPCD_REV"
#define NV_DP_REGKEY_DISABLE_SSC "DISABLE_SSC"
#define NV_DP_REGKEY_DISABLE_SSC "DISABLE_SSC" // SSC (Stream Status Changed)
#define NV_DP_REGKEY_ENABLE_FAST_LINK_TRAINING "ENABLE_FAST_LINK_TRAINING"
#define NV_DP_REGKEY_DISABLE_MST "DISABLE_MST"
#define NV_DP_REGKEY_ENABLE_INBAND_STEREO_SIGNALING "ENABLE_INBAND_STEREO_SIGNALING"
@@ -49,6 +49,7 @@
#define NV_DP_REGKEY_SKIP_ASSESSLINK_FOR_EDP "HP_WAR_2189772"
#define NV_DP_REGKEY_HDCP_AUTH_ONLY_ON_DEMAND "DP_HDCP_AUTH_ONLY_ON_DEMAND"
#define NV_DP_REGKEY_ENABLE_MSA_OVER_MST "ENABLE_MSA_OVER_MST"
#define NV_DP_REGKEY_DISABLE_DOWNSPREAD "DISABLE_DOWNSPREAD"
// Keep link alive for SST and MST
#define NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE "DP_KEEP_OPT_LINK_ALIVE"
@@ -62,12 +63,31 @@
// Message to power down video stream before power down link (set D3)
#define NV_DP_REGKEY_POWER_DOWN_PHY "DP_POWER_DOWN_PHY"
//
// Regkey to re-assess max link if the first assessed link config
// is lower than the panel max
//
#define NV_DP_REGKEY_REASSESS_MAX_LINK "DP_REASSESS_MAX_LINK"
//
// DSC capability of downstream device should be decided based on device's own
// and its parent's DSC capability.
//
#define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315"
//
// This regkey is controlling the if DPLib supports FPGA-specific Test UHBR.
// The link rates are for internal test only.
// This regkey is also used in RM. Both must be kept in sync.
//
#define NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT "DP2X_FPGA_UHBR_SUPPORT"
#define NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_2_5G NVBIT(0)
#define NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_2_7G NVBIT(1)
#define NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_5_0G NVBIT(2)
#define NV_DP2X_IGNORE_CABLE_ID_CAPS "DP2X_IGNORE_CABLE_ID_CAPS"
//
// Bug 4388987 : This regkey will disable reading PCON caps for MST.
//
@@ -75,6 +95,9 @@
#define NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION "DP_DISABLE_TUNNEL_BW_ALLOCATION"
// Bug 4793112 : On eDP panel, do not cache source OUI if it reads zero
#define NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE "DP_SKIP_ZERO_OUI_CACHE"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -106,8 +129,13 @@ struct DP_REGKEY_DATABASE
bool bBypassEDPRevCheck;
bool bDscMstCapBug3143315;
bool bPowerDownPhyBeforeD3;
bool bReassessMaxLink;
NvU32 supportInternalUhbrOnFpga;
bool bIgnoreCableIdCaps;
bool bMSTPCONCapsReadDisabled;
bool bForceDisableTunnelBwAllocation;
bool bDownspreadDisabled;
bool bSkipZeroOuiCache;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;

43
src/common/displayport/inc/dp_watermark.h
View File

@@ -32,8 +32,6 @@
#include "displayport.h"
#define WAR_AUDIOCLAMPING_FREQ 48000 // Audio freq. more than 48KHz are currently clamped due to bug 925211
namespace DisplayPort
{
class LinkConfiguration;
@@ -46,16 +44,18 @@ namespace DisplayPort
NvU64 pixelClockHz; // Requested pixel clock for the mode
unsigned rasterWidth;
unsigned rasterHeight;
unsigned surfaceWidth; // RasterBlankStartX - newRasterBlankEndX
unsigned surfaceWidth; // RasterBlankStartX - RasterBlankEndX
unsigned surfaceHeight; // Active region height
unsigned depth;
unsigned rasterBlankStartX;
unsigned rasterBlankEndX;
unsigned bitsPerComponent; // Bits per component
bool bEnableDsc; // bEnableDsc=1 indicates DSC would be enabled for the mode
DSC_MODE mode; // DSC Mode
bool bEnablePassThroughForPCON;
DSC_MODE mode; // DSC Mode
DP_COLORFORMAT colorFormat;
ModesetInfo(): twoChannelAudioHz(0),
eightChannelAudioHz(0),
pixelClockHz(0),
@@ -68,14 +68,16 @@ namespace DisplayPort
rasterBlankEndX(0),
bitsPerComponent(0),
bEnableDsc(false),
bEnablePassThroughForPCON(false),
mode(DSC_SINGLE),
bEnablePassThroughForPCON(false) {}
colorFormat(dpColorFormat_Unknown) {}
ModesetInfo(unsigned newTwoChannelAudioHz, unsigned newEightChannelAudioHz, NvU64 newPixelClockHz,
unsigned newRasterWidth, unsigned newRasterHeight,
unsigned newSurfaceWidth, unsigned newSurfaceHeight, unsigned newDepth,
unsigned newRasterBlankStartX=0, unsigned newRasterBlankEndX=0, bool newBEnableDsc = false,
DSC_MODE newMode = DSC_SINGLE, bool newBEnablePassThroughForPCON = false):
DSC_MODE newMode = DSC_SINGLE, bool newBEnablePassThroughForPCON = false,
DP_COLORFORMAT dpColorFormat = dpColorFormat_Unknown):
twoChannelAudioHz(newTwoChannelAudioHz),
eightChannelAudioHz(newEightChannelAudioHz),
pixelClockHz(newPixelClockHz),
@@ -88,8 +90,9 @@ namespace DisplayPort
rasterBlankEndX(newRasterBlankEndX),
bitsPerComponent(0),
bEnableDsc(newBEnableDsc),
bEnablePassThroughForPCON(newBEnablePassThroughForPCON),
mode(newMode),
bEnablePassThroughForPCON(newBEnablePassThroughForPCON) {}
colorFormat(dpColorFormat) {}
};
struct Watermark
@@ -103,43 +106,35 @@ namespace DisplayPort
bool isModePossibleSST
(
const LinkConfiguration & linkConfig,
const ModesetInfo & modesetInfo,
const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
Watermark * dpInfo,
bool bUseIncreasedWatermarkLimits = false
);
bool isModePossibleMST
(
const LinkConfiguration & linkConfig,
const ModesetInfo & modesetInfo,
const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
Watermark * dpInfo
);
bool isModePossibleSSTWithFEC
(
const LinkConfiguration & linkConfig,
const ModesetInfo & modesetInfo,
const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
Watermark * dpInfo,
bool bUseIncreasedWatermarkLimits = false
);
bool isModePossibleMSTWithFEC
(
const LinkConfiguration & linkConfig,
const ModesetInfo & modesetInfo,
const LinkConfiguration &linkConfig,
const ModesetInfo &modesetInfo,
Watermark * dpInfo
);
bool dp2xIsModePossibleMSTWithFEC
(
const LinkConfiguration & linkConfig,
const ModesetInfo & modesetInfo,
Watermark * dpInfo
);
// Return Payload Bandwidth Number(PBN)for requested mode
unsigned pbnForMode(const ModesetInfo & modesetInfo);
unsigned pbnForMode(const ModesetInfo &modesetInfo);
}
#endif //INCLUDED_DP_WATERMARK_H