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This commit is contained in:
Bernhard Stoeckner
2025-01-27 19:36:56 +01:00
parent 9d0b0414a5
commit 54d69484da
1166 changed files with 318863 additions and 182687 deletions
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1
src/common/sdk/nvidia/inc/alloc/alloc_channel.h
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@@ -338,6 +338,7 @@ typedef struct NV_CHANNEL_ALLOC_PARAMS {
NvU32 decryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved
// Nonce used CPU-side signing / GPU-side signature verification.
NvU32 hmacNonce[CC_CHAN_ALLOC_NONCE_SIZE_DWORD]; // reserved
NvU32 tpcConfigID; // TPC Configuration Id as supported by DTD-PG Feature
} NV_CHANNEL_ALLOC_PARAMS;
typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS;

3
src/common/sdk/nvidia/inc/class/cl0000.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2001-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -48,5 +48,6 @@ typedef struct NV0000_ALLOC_PARAMETERS {
NvHandle hClient; /* CORERM-2934: hClient must remain the first member until all allocations use these params */
NvU32 processID;
char processName[NV_PROC_NAME_MAX_LENGTH];
NV_DECLARE_ALIGNED(NvP64 pOsPidInfo, 8);
} NV0000_ALLOC_PARAMETERS;

16
src/common/sdk/nvidia/inc/class/cl00de.h
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@@ -197,16 +197,20 @@ typedef struct RUSD_POWER_LIMITS {
RUSD_POWER_LIMIT_INFO info;
} RUSD_POWER_LIMITS;
typedef struct RUSD_TEMPERATURE_INFO {
NvTemp gpuTemperature;
NvTemp hbmTemperature;
} RUSD_TEMPERATURE_INFO;
typedef enum RUSD_TEMPERATURE_TYPE {
RUSD_TEMPERATURE_TYPE_GPU,
RUSD_TEMPERATURE_TYPE_HBM,
RUSD_TEMPERATURE_TYPE_MAX
} RUSD_TEMPERATURE_TYPE;
typedef struct RUSD_TEMPERATURE {
volatile NvU64 lastModifiedTimestamp;
RUSD_TEMPERATURE_INFO info;
NvTemp temperature;
} RUSD_TEMPERATURE;
// Temporary until clients can migrate to using RUSD_TEMPERATURE type name
typedef RUSD_TEMPERATURE RUSD_TEMPERATURE_GENERIC;
typedef struct RUSD_MEM_ROW_REMAP_INFO {
// Provided from NV2080_CTRL_CMD_FB_GET_ROW_REMAPPER_HISTOGRAM
NvU32 histogramMax; // No remapped row is used.
@@ -325,7 +329,7 @@ typedef struct NV00DE_SHARED_DATA {
NV_DECLARE_ALIGNED(RUSD_POWER_LIMITS powerLimitGpu, 8);
// POLL_THERMAL
NV_DECLARE_ALIGNED(RUSD_TEMPERATURE temperature, 8);
NV_DECLARE_ALIGNED(RUSD_TEMPERATURE temperatures[RUSD_TEMPERATURE_TYPE_MAX], 8);
// POLL_MEMORY
NV_DECLARE_ALIGNED(RUSD_MEM_ROW_REMAP memRowRemap, 8);

38
src/common/sdk/nvidia/inc/class/cl2080_notification.h
View File

@@ -221,7 +221,8 @@ extern "C" {
#define NV2080_NOTIFIERS_OFA1 (180)
#define NV2080_NOTIFIERS_AUX_POWER_EVENT (181)
#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (182)
#define NV2080_NOTIFIERS_RESERVED_183 (183) // Unused
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define NV2080_NOTIFIERS_NVENC3 (183)
#define NV2080_NOTIFIERS_GSP_PERF_TRACE (184)
#define NV2080_NOTIFIERS_INBAND_RESPONSE (185)
#define NV2080_NOTIFIERS_RESERVED_186 (186) // Unused
@@ -233,7 +234,9 @@ extern "C" {
#define NV2080_NOTIFIERS_GPU_RECOVERY_ACTION (192)
#define NV2080_NOTIFIERS_POWER_SUSPEND (193)
#define NV2080_NOTIFIERS_POWER_RESUME (194)
#define NV2080_NOTIFIERS_MAXCOUNT (195)
#define NV2080_NOTIFIERS_CTXSW_UCODE_ERROR (195)
#define NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD (196)
#define NV2080_NOTIFIERS_MAXCOUNT (197)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))
@@ -247,9 +250,11 @@ extern "C" {
(((x) >= NV2080_NOTIFIERS_CE10) && ((x) <= NV2080_NOTIFIERS_CE19)))
// Indexed MSENC notifier reference
#define NV2080_NOTIFIERS_NVENC(x) (NV2080_NOTIFIERS_NVENC0 + (x))
#define NV2080_NOTIFIERS_NVENC_IDX(x) ((x) - NV2080_NOTIFIERS_NVENC0)
#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) (((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2))
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define NV2080_NOTIFIERS_NVENC(x) (((x) < 3) ? (NV2080_NOTIFIERS_NVENC0 + (x)) : (NV2080_NOTIFIERS_NVENC3 + (x) - 3))
#define NV2080_NOTIFIERS_NVENC_IDX(x) (((x) <= NV2080_NOTIFIERS_NVENC2) ? ((x) - NV2080_NOTIFIERS_NVENC0) : ((x) - NV2080_NOTIFIERS_NVENC3 + 3))
#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) ((((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2)) || \
(((x) == NV2080_NOTIFIERS_NVENC3)))
// Indexed NVDEC notifier reference
#define NV2080_NOTIFIERS_NVDEC(x) (NV2080_NOTIFIERS_NVDEC0 + (x))
#define NV2080_NOTIFIERS_NVDEC_IDX(x) ((x) - NV2080_NOTIFIERS_NVDEC0)
@@ -344,7 +349,8 @@ extern "C" {
#define NV2080_ENGINE_TYPE_COPY18 (0x0000003c)
#define NV2080_ENGINE_TYPE_COPY19 (0x0000003d)
#define NV2080_ENGINE_TYPE_OFA1 (0x0000003e)
#define NV2080_ENGINE_TYPE_RESERVED3f (0x0000003f)
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define NV2080_ENGINE_TYPE_NVENC3 (0x0000003f)
// See TBD documentation for how these defines work with existing ENGINE_TYPE_COPYN defines
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 (0x00000040)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY1 (0x00000041)
@@ -377,7 +383,8 @@ extern "C" {
//
#define NV2080_ENGINE_TYPE_COPY_SIZE 64
#define NV2080_ENGINE_TYPE_NVENC_SIZE 3
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define NV2080_ENGINE_TYPE_NVENC_SIZE 4
#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8
#define NV2080_ENGINE_TYPE_NVDEC_SIZE 8
#define NV2080_ENGINE_TYPE_GR_SIZE 8
@@ -394,9 +401,12 @@ extern "C" {
#define NV2080_ENGINE_TYPE_COPY_IDX(i) (((i) <= NV2080_ENGINE_TYPE_COPY9) ? \
((i) - NV2080_ENGINE_TYPE_COPY0) : ((i) - NV2080_ENGINE_TYPE_COPY10 + 10))
#define NV2080_ENGINE_TYPE_NVENC(i) (NV2080_ENGINE_TYPE_NVENC0+(i))
#define NV2080_ENGINE_TYPE_IS_NVENC(i) (((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) < NV2080_ENGINE_TYPE_NVENC(NV2080_ENGINE_TYPE_NVENC_SIZE)))
#define NV2080_ENGINE_TYPE_NVENC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVENC0)
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define NV2080_ENGINE_TYPE_NVENC(i) (((i) < 3) ? (NV2080_ENGINE_TYPE_NVENC0 + (i)) : (NV2080_ENGINE_TYPE_NVENC3 + (i) - 3))
#define NV2080_ENGINE_TYPE_IS_NVENC(i) ((((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) <= NV2080_ENGINE_TYPE_NVENC2)) || \
(((i) == NV2080_ENGINE_TYPE_NVENC3)))
#define NV2080_ENGINE_TYPE_NVENC_IDX(i) (((i) <= NV2080_ENGINE_TYPE_NVENC2) ? \
((i)-NV2080_ENGINE_TYPE_NVENC0) : ((i)-NV2080_ENGINE_TYPE_NVENC3 + 3))
#define NV2080_ENGINE_TYPE_NVDEC(i) (NV2080_ENGINE_TYPE_NVDEC0+(i))
#define NV2080_ENGINE_TYPE_IS_NVDEC(i) (((i) >= NV2080_ENGINE_TYPE_NVDEC0) && ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE)))
@@ -558,6 +568,14 @@ typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS {
NvU8 eventReason;
} NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS;
/*
* Workload type update event information. Workload type is enumerated as per the
* NV2080_CTRL_PERF_PERF_CF_CONTROLLER_DLCC_WORKLOAD_TYPE_ENUM
*/
typedef struct _NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE {
NvU8 workloadType;
} NV2080_NOTIFIERS_USE_GC6_REDUCED_THRESHOLD_UPDATE;
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON 23:16

10
src/common/sdk/nvidia/inc/class/cl90cdvideo.h
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@@ -78,6 +78,14 @@ typedef enum
NV_EVENT_BUFFER_VIDEO_CODEC_ID__LAST = NV_EVENT_BUFFER_VIDEO_CODEC_ID__AVD,
} NV_EVENT_BUFFER_VIDEO_ENGINE_CODEC_ID;
typedef enum
{
NV_EVENT_BUFFER_VIDEO_ENGINE_LOG_DATA_TYPE__GENERIC = 0, /* Generic opaque data */
NV_EVENT_BUFFER_VIDEO_ENGINE_LOG_DATA_TYPE__STR, /* Log data can be interpreted as string */
NV_EVENT_BUFFER_VIDEO_ENGINE_LOG_DATA_TYPE__BIN, /* Log data is binary data */
NV_EVENT_BUFFER_VIDEO_ENGINE_LOG_DATA_TYPE__NUM
} NV_EVENT_BUFFER_VIDEO_ENGINE_LOG_DATA_TYPE;
// V1 ------------------------------------------------------------------------
typedef struct
{
@@ -110,7 +118,7 @@ typedef struct
{
NvU8 engine_type;
NvU8 engine_id;
NvU16 codec_id;
NvU16 type;
NvU32 size;
} logData;
};

26
src/common/sdk/nvidia/inc/class/cl9171.h
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@@ -1,5 +1,6 @@
/*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -13,7 +14,7 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
@@ -73,6 +74,27 @@ typedef volatile struct _cl9171_tag0 {
#define NV9171_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x00690004-0x00690000+(i)*1024) /* R--4A */
#define NV9171_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 4 /* */
#define NV9171_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R--VF */
#define NV9171_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */
#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */
#define NV9171_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */

7
src/common/sdk/nvidia/inc/class/cl917a.h
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@@ -1,5 +1,6 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -8,12 +9,12 @@
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

7
src/common/sdk/nvidia/inc/class/cl917b.h
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -8,12 +9,12 @@
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

7
src/common/sdk/nvidia/inc/class/cl917dcrcnotif.h
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@@ -1,5 +1,6 @@
/*
* Copyright (c) 2003-2010, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -8,12 +9,12 @@
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

26
src/common/sdk/nvidia/inc/class/cl9271.h
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -13,7 +14,7 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
@@ -73,6 +74,27 @@ typedef volatile struct _cl9271_tag0 {
#define NV9271_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x00690004-0x00690000+(i)*1024) /* R--4A */
#define NV9271_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 4 /* */
#define NV9271_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R--VF */
#define NV9271_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */
#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */
#define NV9271_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */

26
src/common/sdk/nvidia/inc/class/cl9471.h
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -13,7 +14,7 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
@@ -73,6 +74,27 @@ typedef volatile struct _cl9471_tag0 {
#define NV9471_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x00690004-0x00690000+(i)*1024) /* R--4A */
#define NV9471_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 4 /* */
#define NV9471_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R--VF */
#define NV9471_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */
#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */
#define NV9471_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */

26
src/common/sdk/nvidia/inc/class/cl9571.h
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -13,7 +14,7 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
@@ -73,6 +74,27 @@ typedef volatile struct _cl9571_tag0 {
#define NV9571_SF_HDMI_INFO_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x00690004-0x00690000+(i)*1024) /* R--4A */
#define NV9571_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 4 /* */
#define NV9571_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R--VF */
#define NV9571_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */
#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */
#define NV9571_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */

68
src/common/sdk/nvidia/inc/class/clc371.h
View File

@@ -34,6 +34,74 @@ typedef volatile struct _clc371_tag0 {
NvU32 dispSfUserOffset[0x400];
} _NvC371DispSfUser, NvC371DispSfUserMap;
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x00690000-0x00690000+(i)*1024) /* RWX4A */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 4 /* */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x00690004-0x00690000+(i)*1024) /* R--4A */
#define NVC371_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 4 /* */
#define NVC371_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R--VF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x00690008-0x00690000+(i)*1024) /* RWX4A */
#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 4 /* */
#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x0069000C-0x00690000+(i)*1024) /* RWX4A */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 4 /* */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x00690010-0x00690000+(i)*1024) /* RWX4A */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 4 /* */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x00690014-0x00690000+(i)*1024) /* RWX4A */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 4 /* */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x00690018-0x00690000+(i)*1024) /* RWX4A */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 4 /* */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NVC371_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#ifdef __cplusplus
}; /* extern "C" */
#endif

7
src/common/sdk/nvidia/inc/class/clc37a.h
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -8,12 +9,12 @@
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

7
src/common/sdk/nvidia/inc/class/clc37b.h
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -8,12 +9,12 @@
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

7
src/common/sdk/nvidia/inc/class/clc37dcrcnotif.h
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2003-2016, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -8,12 +9,12 @@
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

8
src/common/sdk/nvidia/inc/class/clc573.h
View File

@@ -591,6 +591,14 @@ typedef volatile struct _clc573_tag0 {
#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */
#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#define NVC573_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */
#define NVC573_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */
#define NVC573_SOR_CLK_CAP__SIZE_1 8 /* */
#define NVC573_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */
#define NVC573_SOR_CLK_CAP_DP_MAX_INIT 0x00000051 /* RWI-V */
#define NVC573_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */
#define NVC573_SOR_CLK_CAP_TMDS_MAX_INIT 0x0000003C /* RWI-V */
#define NVC573_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */
#define NVC573_SOR_CLK_CAP_LVDS_MAX_INIT 0x00000000 /* RWI-V */
#ifdef __cplusplus
};

38
src/common/sdk/nvidia/inc/class/clc57a.h
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 1993-2020, NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -13,7 +14,7 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
@@ -43,6 +44,39 @@ typedef volatile struct _clc57a_tag0 {
#define NVC57A_FREE (0x00000008)
#define NVC57A_FREE_COUNT 5:0
#define NVC57A_UPDATE (0x00000200)
#define NVC57A_UPDATE_RELEASE_ELV 0:0
#define NVC57A_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVC57A_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVC57A_UPDATE_FLIP_LOCK_PIN 8:4
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVC57A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVC57A_SET_INTERLOCK_FLAGS (0x00000204)
#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0
#define NVC57A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)

3
src/common/sdk/nvidia/inc/class/clc57b.h
View File

@@ -51,6 +51,9 @@ extern "C" {
#define NVC57B_GET (0x00000004)
#define NVC57B_GET_PTR 9:0
#define NVC57B_UPDATE (0x00000200)
#define NVC57B_UPDATE_RELEASE_ELV 0:0
#define NVC57B_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVC57B_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVC57B_UPDATE_INTERLOCK_WITH_WINDOW 1:1
#define NVC57B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVC57B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)

106
src/common/sdk/nvidia/inc/class/clc673.h
View File

@@ -108,6 +108,107 @@ typedef volatile struct _clc673_tag0 {
#define NVC673_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */
#define NVC673_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB 0x4 /* RW-4R */
#define NVC673_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVC673_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */
#define NVC673_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */
#define NVC673_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */
#define NVC673_IHUB_COMMON_CAPA 0x10 /* RW-4R */
#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */
#define NVC673_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */
@@ -392,6 +493,11 @@ typedef volatile struct _clc673_tag0 {
#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */
#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVC673_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#define NVC673_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */
#define NVC673_SOR_CLK_CAP__SIZE_1 8 /* */
#define NVC673_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */
#define NVC673_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */
#define NVC673_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */
#ifdef __cplusplus
};

78
src/common/sdk/nvidia/inc/class/clc67a.h
View File

@@ -1,26 +1,25 @@
/*******************************************************************************
Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc67a__h_
#define _clc67a__h_
@@ -45,6 +44,39 @@ typedef volatile struct _clc67a_tag0 {
#define NVC67A_FREE (0x00000008)
#define NVC67A_FREE_COUNT 5:0
#define NVC67A_UPDATE (0x00000200)
#define NVC67A_UPDATE_RELEASE_ELV 0:0
#define NVC67A_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVC67A_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVC67A_UPDATE_FLIP_LOCK_PIN 8:4
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVC67A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVC67A_SET_INTERLOCK_FLAGS (0x00000204)
#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0
#define NVC67A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)

49
src/common/sdk/nvidia/inc/class/clc67b.h
View File

@@ -1,27 +1,25 @@
/*******************************************************************************
Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clC67b_h_
#define _clC67b_h_
@@ -53,6 +51,9 @@ extern "C" {
#define NVC67B_GET (0x00000004)
#define NVC67B_GET_PTR 9:0
#define NVC67B_UPDATE (0x00000200)
#define NVC67B_UPDATE_RELEASE_ELV 0:0
#define NVC67B_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVC67B_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVC67B_UPDATE_INTERLOCK_WITH_WINDOW 1:1
#define NVC67B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVC67B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)

46
src/common/sdk/nvidia/inc/class/clc67d.h
View File

@@ -1,27 +1,25 @@
/*******************************************************************************
Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clC67d_h_
#define _clC67d_h_

46
src/common/sdk/nvidia/inc/class/clc67e.h
View File

@@ -1,27 +1,25 @@
/*******************************************************************************
Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*******************************************************************************/
/*
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clC67e_h_
#define _clC67e_h_

30
src/common/sdk/nvidia/inc/class/clc761.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc761_h_
#define _clc761_h_
#define BLACKWELL_USERMODE_A (0xc761)
#endif /* _clc761_h_ */

35
src/common/sdk/nvidia/inc/class/clc771.h
View File

@@ -20,6 +20,7 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc771_h_
#define _clc771_h_
@@ -33,6 +34,11 @@ typedef volatile struct _clc771_tag0 {
NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */
} _NvC771DispSfUser, NvC771DispSfUserMap;
#define NVC771_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME 0x00000001 /* */
#define NVC771_SF_HDMI_INFO_IDX_VSI 0x00000004 /* */
#define NVC771_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC771_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */
#define NVC771_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
@@ -111,21 +117,40 @@ typedef volatile struct _clc771_tag0 {
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL(i,j) (0x000E0200-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_CTRL__SIZE_1 8 /* */
#define NVC771_SF_SHARED_GENERIC_CTRL__SIZE_2 6 /* */
#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE 4:4 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE_NO 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE_YES 0x00000001 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW 16:16 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_NO 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_YES 0x00000001 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_CTRL_LOC 9:8 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_VSYNC 0x00000001 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_LOADV 0x00000002 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_CTRL_NEW 12:12 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_NEW_INIT 0x00000000 /* R-I-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_NEW_DONE 0x00000000 /* R---V */
#define NVC771_SF_SHARED_GENERIC_CTRL_NEW_PENDING 0x00000001 /* R---V */
#define NVC771_SF_SHARED_GENERIC_CTRL_NEW_TRIGGER 0x00000001 /* -W--T */
#define NVC771_SF_SHARED_GENERIC_CTRL_STATUS 13:13 /* R-IVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_STATUS_DONE 0x00000001 /* R---V */
#define NVC771_SF_SHARED_GENERIC_CTRL_STATUS_WAIT 0x00000000 /* R---V */
#define NVC771_SF_SHARED_GENERIC_CTRL_STATUS_INIT 0x00000000 /* R-I-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW 16:16 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_NO 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_YES 0x00000001 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_CTRL_BUSY 20:20 /* R-IVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_BUSY_NO 0x00000000 /* R-I-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_BUSY_YES 0x00000001 /* R---V */
#define NVC771_SF_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE 28:28 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE_DISABLE 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_VSC_SDP_UPDATE_RFB_OVERRIDE_ENABLE 0x00000001 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE 31:31 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE_DISABLE 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_VSC_SDP_SU_COORDINATES_VALID_OVERRIDE_ENABLE 0x00000001 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER(i,j) (0x000E0204-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 8 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_2 6 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
@@ -229,4 +254,4 @@ typedef volatile struct _clc771_tag0 {
}; /* extern "C" */
#endif
#endif
#endif // _clc771_h_

642
src/common/sdk/nvidia/inc/class/clc773.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,6 +24,644 @@
#ifndef _clc773_h_
#define _clc773_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVC773_DISP_CAPABILITIES 0xC773
#endif
typedef volatile struct _clc773_tag0 {
NvU32 dispCapabilities[0x400];
} _NvC773DispCapabilities,NvC773DispCapabilities_Map ;
#define NVC773_SYS_CAP 0x0 /* RW-4R */
#define NVC773_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */
#define NVC773_SYS_CAP_HEAD0_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */
#define NVC773_SYS_CAP_HEAD1_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */
#define NVC773_SYS_CAP_HEAD2_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */
#define NVC773_SYS_CAP_HEAD3_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */
#define NVC773_SYS_CAP_HEAD4_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */
#define NVC773_SYS_CAP_HEAD5_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */
#define NVC773_SYS_CAP_HEAD6_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */
#define NVC773_SYS_CAP_HEAD7_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVC773_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NVC773_SYS_CAP_HEAD_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */
#define NVC773_SYS_CAP_SOR0_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */
#define NVC773_SYS_CAP_SOR1_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */
#define NVC773_SYS_CAP_SOR2_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */
#define NVC773_SYS_CAP_SOR3_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */
#define NVC773_SYS_CAP_SOR4_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */
#define NVC773_SYS_CAP_SOR5_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */
#define NVC773_SYS_CAP_SOR6_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */
#define NVC773_SYS_CAP_SOR7_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */
#define NVC773_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */
#define NVC773_SYS_CAP_SOR_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */
#define NVC773_SYS_CAP_DSI0_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */
#define NVC773_SYS_CAP_DSI1_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */
#define NVC773_SYS_CAP_DSI2_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */
#define NVC773_SYS_CAP_DSI3_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */
#define NVC773_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */
#define NVC773_SYS_CAP_DSI_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB 0x4 /* RW-4R */
#define NVC773_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW0_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW1_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW2_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW3_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW4_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW5_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW6_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW7_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW8_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW9_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW10_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW11_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW12_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW13_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW14_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW15_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW16_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW17_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW18_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW19_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW20_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW21_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW22_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW23_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW24_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW25_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW26_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW27_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW28_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW29_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW30_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW31_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVC773_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */
#define NVC773_SYS_CAPB_WINDOW_EXISTS_INIT 0x00000000 /* RWI-V */
#define NVC773_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */
#define NVC773_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA 0x10 /* RW-4R */
#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */
#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES_INIT 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_INIT 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_ROTATION_INIT 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_PLANAR_INIT 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_VGA_INIT 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_INIT 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MSCG_INIT 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_INIT 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_INIT 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_INIT 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */
#define NVC773_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */
#define NVC773_IHUB_COMMON_CAPC 0x18 /* RW-4R */
#define NVC773_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_INIT 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */
#define NVC773_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */
#define NVC773_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */
#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_INIT 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */
#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */
#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */
#define NVC773_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */
#define NVC773_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */
#define NVC773_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */
#define NVC773_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */
#define NVC773_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA__SIZE_1 8 /* */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT 24:24 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB__SIZE_1 8 /* */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_VGA 0:0 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_VGA_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ 9:6 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR 12:10 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD 14:14 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT 15:15 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC__SIZE_1 8 /* */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */
#define NVC773_POSTCOMP_HEAD_HDR_CAPD__SIZE_1 8 /* */
#define NVC773_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE__SIZE_1 8 /* */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE 3:0 /* RWIUF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE 13:8 /* RWIUF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_INIT 0x00000000 /* RWI-V */
#define NVC773_POSTCOMP_HEAD_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */
#define NVC773_POSTCOMP_HEAD_HDR_CAPF__SIZE_1 8 /* */
#define NVC773_POSTCOMP_HEAD_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */
#define NVC773_POSTCOMP_HEAD_HDR_CAPF_VFILTER_MAX_PIXELS_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */
#define NVC773_SOR_CAP__SIZE_1 8 /* */
#define NVC773_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */
#define NVC773_SOR_CAP_SINGLE_LVDS_18_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */
#define NVC773_SOR_CAP_SINGLE_LVDS_24_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */
#define NVC773_SOR_CAP_DUAL_LVDS_18_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */
#define NVC773_SOR_CAP_DUAL_LVDS_24_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */
#define NVC773_SOR_CAP_SINGLE_TMDS_A_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */
#define NVC773_SOR_CAP_SINGLE_TMDS_B_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */
#define NVC773_SOR_CAP_DUAL_TMDS_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */
#define NVC773_SOR_CAP_DISPLAY_OVER_PCIE_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_SDI 16:16 /* RWIVF */
#define NVC773_SOR_CAP_SDI_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_DP_A 24:24 /* RWIVF */
#define NVC773_SOR_CAP_DP_A_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_DP_B 25:25 /* RWIVF */
#define NVC773_SOR_CAP_DP_B_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */
#define NVC773_SOR_CAP_DP_INTERLACE_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */
#define NVC773_SOR_CAP_DP_8_LANES_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */
#define NVC773_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */
#define NVC773_SOR_CAP_HDMI_FRL_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */
#define NVC773_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ 9:6 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR 12:10 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD 14:14 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ 9:6 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR 12:10 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD 14:14 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#define NVC773_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */
#define NVC773_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */
#define NVC773_SOR_CLK_CAP__SIZE_1 8 /* */
#define NVC773_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */
#define NVC773_SOR_CLK_CAP_DP_MAX_INIT 0x00000051 /* RWI-V */
#define NVC773_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */
#define NVC773_SOR_CLK_CAP_TMDS_MAX_INIT 0x0000003C /* RWI-V */
#define NVC773_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */
#define NVC773_SOR_CLK_CAP_LVDS_MAX_INIT 0x00000000 /* RWI-V */
#ifdef __cplusplus
};
#endif /* extern C */
#endif //_clc773_h_

1345
src/common/sdk/nvidia/inc/class/clc77d.h
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41
src/common/sdk/nvidia/inc/class/clc870.h Normal file
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@@ -0,0 +1,41 @@
/*
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clc870.finn
//
#define NVC870_DISPLAY (0xc870U) /* finn: Evaluated from "NVC870_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NVC870_ALLOCATION_PARAMETERS_MESSAGE_ID (0xc870U)
typedef struct NVC870_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numDsis; // Number of DSIs in this chip/display
} NVC870_ALLOCATION_PARAMETERS;

380
src/common/sdk/nvidia/inc/class/clc871.h Normal file
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@@ -0,0 +1,380 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc871_h_
#define _clc871_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVC871_DISP_SF_USER (0x000C871)
typedef volatile struct _clc871_tag0 {
NvU32 dispSfUserOffset[0x400];
} _NvC871DispSfUser, NvC871DispSfUserMap;
#define NVC871_SF_HDMI_INFO_IDX_AVI_INFOFRAME 0x00000000 /* */
#define NVC871_SF_HDMI_INFO_IDX_GCP 0x00000001 /* */
#define NVC871_SF_HDMI_INFO_IDX_ACR 0x00000002 /* */
#define NVC871_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC871_SF_HDMI_INFO_CTRL__SIZE_1 8 /* */
#define NVC871_SF_HDMI_INFO_CTRL__SIZE_2 3 /* */
#define NVC871_SF_HDMI_INFO_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC871_SF_HDMI_INFO_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_INFO_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NVC871_SF_HDMI_INFO_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_INFO_CTRL_OTHER 4:4 /* RWIVF */
#define NVC871_SF_HDMI_INFO_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_INFO_CTRL_SINGLE 8:8 /* RWIVF */
#define NVC871_SF_HDMI_INFO_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_INFO_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NVC871_SF_HDMI_INFO_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_INFO_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_INFO_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NVC871_SF_HDMI_INFO_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */
#define NVC871_SF_HDMI_INFO_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NVC871_SF_HDMI_INFO_CTRL_HBLANK 12:12 /* RWIVF */
#define NVC871_SF_HDMI_INFO_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_CTRL_HBLANK_EN 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_INFO_CTRL_VIDEO_FMT 16:16 /* RWIVF */
#define NVC871_SF_HDMI_INFO_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */
#define NVC871_SF_HDMI_INFO_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_INFO_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */
#define NVC871_SF_HDMI_INFO_STATUS(i,j) (0x000E0004-0x000E0000+(i)*1024+(j)*64) /* R--4A */
#define NVC871_SF_HDMI_INFO_STATUS__SIZE_1 8 /* */
#define NVC871_SF_HDMI_INFO_STATUS__SIZE_2 3 /* */
#define NVC871_SF_HDMI_INFO_STATUS_SENT 0:0 /* R--VF */
#define NVC871_SF_HDMI_INFO_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NVC871_SF_HDMI_INFO_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NVC871_SF_HDMI_INFO_HEADER(i,j) (0x000E0008-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC871_SF_HDMI_INFO_HEADER__SIZE_1 8 /* */
#define NVC871_SF_HDMI_INFO_HEADER__SIZE_2 3 /* */
#define NVC871_SF_HDMI_INFO_HEADER_HB0 7:0 /* RWIVF */
#define NVC871_SF_HDMI_INFO_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_HEADER_HB1 15:8 /* RWIVF */
#define NVC871_SF_HDMI_INFO_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_HEADER_HB2 23:16 /* RWIVF */
#define NVC871_SF_HDMI_INFO_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW(i,j) (0x000E000C-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW__SIZE_1 8 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW__SIZE_2 3 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH(i,j) (0x000E0010-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH__SIZE_1 8 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH__SIZE_2 3 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW(i,j) (0x000E0014-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW__SIZE_1 8 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW__SIZE_2 3 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH(i,j) (0x000E0018-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH__SIZE_1 8 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH__SIZE_2 3 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW(i,j) (0x000E001C-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW__SIZE_1 8 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW__SIZE_2 3 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH(i,j) (0x000E0020-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH__SIZE_1 8 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH__SIZE_2 3 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW(i,j) (0x000E0024-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW__SIZE_1 8 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW__SIZE_2 3 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB21 7:0 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB22 15:8 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB23 23:16 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB24 31:24 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH(i,j) (0x000E0028-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH__SIZE_1 8 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH__SIZE_2 3 /* */
#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */
#define NVC871_SF_HDMI_INFO_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */
#define NVC871_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */
#define NVC871_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */
#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */
#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NVC871_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_GCP_CTRL(i) (0x000E0040-0x000E0000+(i)*1024) /* RW-4A */
#define NVC871_SF_HDMI_GCP_CTRL__SIZE_1 8 /* */
#define NVC871_SF_HDMI_GCP_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC871_SF_HDMI_GCP_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_GCP_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_GCP_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NVC871_SF_HDMI_GCP_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_GCP_CTRL_OTHER 4:4 /* RWIVF */
#define NVC871_SF_HDMI_GCP_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_GCP_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_GCP_CTRL_SINGLE 8:8 /* RWIVF */
#define NVC871_SF_HDMI_GCP_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_GCP_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_GCP_STATUS(i) (0x000E0044-0x000E0000+(i)*1024) /* R--4A */
#define NVC871_SF_HDMI_GCP_STATUS__SIZE_1 8 /* */
#define NVC871_SF_HDMI_GCP_STATUS_SENT 0:0 /* R-IVF */
#define NVC871_SF_HDMI_GCP_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_START_PP 6:4 /* R--VF */
#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_0 0x00000004 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_1 0x00000001 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_2 0x00000002 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_3 0x00000003 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_END_PP 10:8 /* R--VF */
#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_0 0x00000004 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_1 0x00000001 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_2 0x00000002 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_3 0x00000003 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_START_PP 14:12 /* R--VF */
#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_START_PP_0 0x00000004 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_START_PP_1 0x00000001 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_START_PP_2 0x00000002 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_START_PP_3 0x00000003 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_END_PP 18:16 /* R--VF */
#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_END_PP_0 0x00000004 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_END_PP_1 0x00000001 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_END_PP_2 0x00000002 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_VSYNC_END_PP_3 0x00000003 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_START_PP 22:20 /* R--VF */
#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_START_PP_0 0x00000004 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_START_PP_1 0x00000001 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_START_PP_2 0x00000002 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_START_PP_3 0x00000003 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_END_PP 26:24 /* R--VF */
#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_END_PP_0 0x00000004 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_END_PP_1 0x00000001 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_END_PP_2 0x00000002 /* R---V */
#define NVC871_SF_HDMI_GCP_STATUS_HSYNC_END_PP_3 0x00000003 /* R---V */
#define NVC871_SF_HDMI_GCP_SUBPACK(i) (0x000E004C-0x000E0000+(i)*1024) /* RW-4A */
#define NVC871_SF_HDMI_GCP_SUBPACK__SIZE_1 8 /* */
#define NVC871_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */
#define NVC871_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */
#define NVC871_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */
#define NVC871_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */
#define NVC871_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */
#define NVC871_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */
#define NVC871_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_HDMI_GCP_SUBPACK_SB1_CTRL 24:24 /* RWIVF */
#define NVC871_SF_HDMI_GCP_SUBPACK_SB1_CTRL_INIT 0x00000001 /* RWI-V */
#define NVC871_SF_HDMI_GCP_SUBPACK_SB1_CTRL_SW 0x00000000 /* RW--V */
#define NVC871_SF_HDMI_GCP_SUBPACK_SB1_CTRL_HW 0x00000001 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL(i,j) (0x000E0130-0x000E0000+(i)*1024+(j)*8) /* RW-4A */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL__SIZE_2 10 /* */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE 3:1 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ALWAYS 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ONCE 0x00000001 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ALWAYS 0x00000002 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ONCE 0x00000003 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_TRIGGER 0x00000004 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_LOC 5:4 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_LOC_VSYNC 0x00000001 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_LOC_LINE 0x00000002 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_LOC_LOADV 0x00000003 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_OFFSET 10:6 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_SIZE 18:14 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_SIZE_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_BUSY 22:22 /* R-IVF */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_BUSY_NO 0x00000000 /* R-I-V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_BUSY_YES 0x00000001 /* R---V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_SENT 23:23 /* R-IVF */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_SENT_NO 0x00000000 /* R-I-V */
#define NVC871_SF_GENERIC_INFOFRAME_CTRL_SENT_YES 0x00000001 /* R---V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG(i,j) (0x000E0134-0x000E0000+(i)*1024+(j)*8) /* RW-4A */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG__SIZE_1 8 /* */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG__SIZE_2 10 /* */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_FID 7:0 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_FID_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID 23:8 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED 24:24 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_NO 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_YES 0x00000001 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_CRC_OVERRIDE 28:28 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_CRC_OVERRIDE_NO 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_CRC_OVERRIDE_YES 0x00000001 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM 29:29 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_NO 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_YES 0x00000001 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_NEW 30:30 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_NEW_INIT 0x00000000 /* R-I-V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_NEW_DONE 0x00000000 /* R---V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_NEW_PENDING 0x00000001 /* R---V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_NEW_TRIGGER 0x00000001 /* -W--T */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL 31:31 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ACT 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ARM 0x00000001 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_DATA_CTRL(i) (0x000E03F0-0x000E0000+(i)*1024) /* RW-4A */
#define NVC871_SF_GENERIC_INFOFRAME_DATA_CTRL__SIZE_1 8 /* */
#define NVC871_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET 4:0 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_DATA(i) (0x000E03F4-0x000E0000+(i)*1024) /* RW-4A */
#define NVC871_SF_GENERIC_INFOFRAME_DATA__SIZE_1 8 /* */
#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE0 7:0 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE0_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE1 15:8 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE1_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE2 23:16 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE2_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE3 31:24 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_DATA_BYTE3_INIT 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL(i) (0x000E03F8-0x000E0000+(i)*1024) /* RW-4A */
#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL__SIZE_1 8 /* */
#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL_WIN_CHN_SEL 0:0 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL_WIN_CHN_SEL_PRIVATE 0x00000000 /* RWI-V */
#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL_WIN_CHN_SEL_PUBLIC 0x00000001 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY 1:1 /* RWIVF */
#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_HIGH 0x00000000 /* RW--V */
#define NVC871_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_LOW 0x00000001 /* RWI-V */
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clc871_h_

1336
src/common/sdk/nvidia/inc/class/clc87d.h Normal file
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4
src/common/sdk/nvidia/inc/class/clc97d.h
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@@ -890,6 +890,10 @@ extern "C" {
#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20
#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000)
#define NVC97D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001)
#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI(a) (0x000020C0 + (a)*0x00000800)
#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_HERTZ 3:0
#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX(a) (0x000020C4 + (a)*0x00000800)
#define NVC97D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HI_MAX_HERTZ 3:0
#define NVC97D_HEAD_SET_SURFACE_ADDRESS_HI_RG_REL_SEMAPHORE(a,b) (0x00002110 + (a)*0x00000800 + (b)*0x00000004)
#define NVC97D_HEAD_SET_SURFACE_ADDRESS_HI_RG_REL_SEMAPHORE_ADDRESS_HI 31:0
#define NVC97D_HEAD_SET_SURFACE_ADDRESS_LO_RG_REL_SEMAPHORE(a,b) (0x00002130 + (a)*0x00000800 + (b)*0x00000004)

41
src/common/sdk/nvidia/inc/class/clc97dswspare.h Normal file
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@@ -0,0 +1,41 @@
/*
* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc97d_sw_spare_h_
#define _clc97d_sw_spare_h_
/* This file is *not* auto-generated. */
//
// Quadro Sync is a mechanism used to synchronize scanout and flips between
// GPUs in different systems (e.g., to drive large video walls, such as in a
// planetarium). Special FPGA boards (e.g., P2060 or P2061) are added to the
// system to provide the reference frame lock signal. The VPLL_REF field below
// is set to "QSYNC" on the head which is selected to be driven by the external
// reference signal. As with any HEAD_SET_SW_SPARE method, changing the value
// of a field will trigger a supervisor interrupt sequence.
//
#define NVC97D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF 1:0
#define NVC97D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_NO_PREF (0x00000000)
#define NVC97D_HEAD_SET_SW_SPARE_A_CODE_VPLL_REF_QSYNC (0x00000001)
#endif // _clc97d_sw_spare_h_

74
src/common/sdk/nvidia/inc/class/clca6f.h Normal file
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@@ -0,0 +1,74 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb202_clca6f_h__
#define __gb202_clca6f_h__
typedef volatile struct Nvca6fControl_struct {
NvU32 Ignored00[0x23]; /* 0000-008b*/
NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
NvU32 Ignored01[0x5c];
} Nvca6fControl, BlackwellBControlGPFifo;
#define BLACKWELL_CHANNEL_GPFIFO_B (0x0000CA6F)
#define NVCA6F_SET_OBJECT (0x00000000)
#define NVCA6F_SEM_ADDR_LO (0x0000005c)
#define NVCA6F_SEM_ADDR_LO_OFFSET 31:2
#define NVCA6F_SEM_ADDR_HI (0x00000060)
#define NVCA6F_SEM_ADDR_HI_OFFSET 24:0
#define NVCA6F_SEM_PAYLOAD_LO (0x00000064)
#define NVCA6F_SEM_PAYLOAD_HI (0x00000068)
#define NVCA6F_SEM_EXECUTE (0x0000006c)
#define NVCA6F_SEM_EXECUTE_OPERATION 2:0
#define NVCA6F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
#define NVCA6F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
#define NVCA6F_SEM_EXECUTE_RELEASE_WFI 20:20
#define NVCA6F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
#define NVCA6F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
#define NVCA6F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
/* GPFIFO entry format */
#define NVCA6F_GP_ENTRY__SIZE 8
#define NVCA6F_GP_ENTRY0_FETCH 0:0
#define NVCA6F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
#define NVCA6F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
#define NVCA6F_GP_ENTRY0_GET 31:2
#define NVCA6F_GP_ENTRY0_OPERAND 31:0
#define NVCA6F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8
#define NVCA6F_GP_ENTRY1_GET_HI 7:0
#define NVCA6F_GP_ENTRY1_LEVEL 9:9
#define NVCA6F_GP_ENTRY1_LEVEL_MAIN 0x00000000
#define NVCA6F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
#define NVCA6F_GP_ENTRY1_LENGTH 30:10
#define NVCA6F_GP_ENTRY1_SYNC 31:31
#define NVCA6F_GP_ENTRY1_SYNC_PROCEED 0x00000000
#define NVCA6F_GP_ENTRY1_SYNC_WAIT 0x00000001
#define NVCA6F_GP_ENTRY1_OPCODE 7:0
#define NVCA6F_GP_ENTRY1_OPCODE_NOP 0x00000000
#define NVCA6F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
#define NVCA6F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
#define NVCA6F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
#define NVCA6F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004
#endif // __gb202_clca6f_h__

45
src/common/sdk/nvidia/inc/class/clca6fsw.h Normal file
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@@ -0,0 +1,45 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/* This file is *not* auto-generated. */
#ifndef _clca6f_sw_h_
#define _clca6f_sw_h_
#define NVCA6F_NOTIFIERS_RC (0)
#define NVCA6F_NOTIFIERS_REFCNT (1)
#define NVCA6F_NOTIFIERS_NONSTALL (2)
#define NVCA6F_NOTIFIERS_EVENTBUFFER (3)
#define NVCA6F_NOTIFIERS_IDLECHANNEL (4)
#define NVCA6F_NOTIFIERS_ENDCTX (5)
#define NVCA6F_NOTIFIERS_SW (6)
#define NVCA6F_NOTIFIERS_GR_DEBUG_INTR (7)
#define NVCA6F_NOTIFIERS_REPLAYABLE_FAULT (8)
#define NVCA6F_NOTIFIERS_KEY_ROTATION (9)
#define NVCA6F_NOTIFIERS_MAXCOUNT (10)
/* NvNotification[] fields and values */
#define NVCA6F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
#define NVCA6F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
#endif /* _clca6f_sw_h_ */

41
src/common/sdk/nvidia/inc/class/clca70.h Normal file
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@@ -0,0 +1,41 @@
/*
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/clca70.finn
//
#define NVCA70_DISPLAY (0xca70U) /* finn: Evaluated from "NVCA70_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NVCA70_ALLOCATION_PARAMETERS_MESSAGE_ID (0xca70U)
typedef struct NVCA70_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numDsis; // Number of DSIs in this chip/display
} NVCA70_ALLOCATION_PARAMETERS;

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src/common/sdk/nvidia/inc/class/clca71.h Normal file
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@@ -0,0 +1,186 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clca71_h_
#define _clca71_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCA71_DISP_SF_USER (0x000CA71)
typedef volatile struct _clca71_tag0 {
NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */
} _NvCA71DispSfUser, NvCA71DispSfUserMap;
#define NVCA71_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVCA71_SF_HDMI_INFO_CTRL__SIZE_1 8 /* */
#define NVCA71_SF_HDMI_INFO_CTRL__SIZE_2 3 /* */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NVCA71_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL(i,j) (0x000E0130-0x000E0000+(i)*1024+(j)*8) /* RW-4A */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL__SIZE_2 10 /* */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE 3:1 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ALWAYS 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_ONCE 0x00000001 /* RW--V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ALWAYS 0x00000002 /* RW--V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_ONCE 0x00000003 /* RW--V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_RUN_MODE_FID_TRIGGER 0x00000004 /* RW--V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_LOC 5:4 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_LOC_VSYNC 0x00000001 /* RW--V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_LOC_LINE 0x00000002 /* RW--V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_OFFSET 10:6 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_SIZE 18:14 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_SIZE_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_BUSY 22:22 /* R-IVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_BUSY_NO 0x00000000 /* R-I-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_BUSY_YES 0x00000001 /* R---V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_SENT 23:23 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_SENT_NO 0x00000000 /* R-I-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_SENT_YES 0x00000001 /* R---V */
#define NVCA71_SF_GENERIC_INFOFRAME_CTRL_SENT_CLEAR 0x00000001 /* -W--C */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG(i,j) (0x000E0134-0x000E0000+(i)*1024+(j)*8) /* RW-4A */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_1 8 /* */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG__SIZE_2 10 /* */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_FID 7:0 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_FID_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID 23:8 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED 24:24 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_NO 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_LINE_ID_REVERSED_YES 0x00000001 /* RW--V */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN 25:25 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_NO 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_AS_SDP_OVERRIDE_EN_YES 0x00000001 /* RW--V */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM 29:29 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_NO 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_HW_CHECKSUM_YES 0x00000001 /* RW--V */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_NEW 30:30 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_NEW_INIT 0x00000000 /* R-I-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_NEW_DONE 0x00000000 /* R---V */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_NEW_PENDING 0x00000001 /* R---T */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_NEW_TRIGGER 0x00000001 /* -W--T */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL 31:31 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ACT 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_CONFIG_MTD_STATE_CTRL_ARM 0x00000001 /* RW--V */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA_CTRL(i) (0x000E03F0-0x000E0000+(i)*1024) /* RW-4A */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA_CTRL__SIZE_1 8 /* */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET 4:0 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA(i) (0x000E03F4-0x000E0000+(i)*1024) /* RW-4A */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA__SIZE_1 8 /* */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE0 7:0 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE0_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE1 15:8 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE1_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE2 23:16 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE2_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE3 31:24 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_DATA_BYTE3_INIT 0x00000000 /* RWI-V */
#define NVCA71_SF_GENERIC_INFOFRAME_MISC_CTRL(i) (0x000E03F8-0x000E0000+(i)*1024) /* RW-4A */
#define NVCA71_SF_GENERIC_INFOFRAME_MISC_CTRL__SIZE_1 8 /* */
#define NVCA71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY 1:1 /* RWIVF */
#define NVCA71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_HIGH 0x00000000 /* RW--V */
#define NVCA71_SF_GENERIC_INFOFRAME_MISC_CTRL_AUDIO_PRIORITY_LOW 0x00000001 /* RWI-V */
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clca71_h_

915
src/common/sdk/nvidia/inc/class/clca73.h Normal file
View File

@@ -0,0 +1,915 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clca73_h_
#define _clca73_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCA73_DISP_CAPABILITIES 0xCA73
typedef volatile struct _clca73_tag0 {
NvU32 dispCapabilities[0x400];
} _NvCA73DispCapabilities,NvCA73DispCapabilities_Map ;
#define NVCA73_SYS_CAP 0x0 /* RW-4R */
#define NVCA73_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */
#define NVCA73_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */
#define NVCA73_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */
#define NVCA73_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */
#define NVCA73_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */
#define NVCA73_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */
#define NVCA73_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */
#define NVCA73_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */
#define NVCA73_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCA73_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NVCA73_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */
#define NVCA73_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */
#define NVCA73_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */
#define NVCA73_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */
#define NVCA73_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */
#define NVCA73_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */
#define NVCA73_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */
#define NVCA73_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */
#define NVCA73_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */
#define NVCA73_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */
#define NVCA73_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_RISCV0_EXISTS 16:16 /* RWIVF */
#define NVCA73_SYS_CAP_RISCV0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_RISCV0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_DSI0_EXISTS 20:20 /* RWIVF */
#define NVCA73_SYS_CAP_DSI0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_DSI0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_DSI1_EXISTS 21:21 /* RWIVF */
#define NVCA73_SYS_CAP_DSI1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_DSI1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_DSI2_EXISTS 22:22 /* RWIVF */
#define NVCA73_SYS_CAP_DSI2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_DSI2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_DSI3_EXISTS 23:23 /* RWIVF */
#define NVCA73_SYS_CAP_DSI3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_DSI3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAP_DSI_EXISTS(i) (20+(i)):(20+(i)) /* RWIVF */
#define NVCA73_SYS_CAP_DSI_EXISTS__SIZE_1 4 /* */
#define NVCA73_SYS_CAP_DSI_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAP_DSI_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB 0x4 /* RW-4R */
#define NVCA73_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCA73_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */
#define NVCA73_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC 0x20 /* RW-4R */
#define NVCA73_SYS_CAPC_TILE0_EXISTS 0:0 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE1_EXISTS 1:1 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE2_EXISTS 2:2 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE3_EXISTS 3:3 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE4_EXISTS 4:4 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE5_EXISTS 5:5 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE6_EXISTS 6:6 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE7_EXISTS 7:7 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCA73_SYS_CAPC_TILE_EXISTS__SIZE_1 8 /* */
#define NVCA73_SYS_CAPC_TILE_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE 8:8 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE 9:9 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE 10:10 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE 11:11 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE 12:12 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE 13:13 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE 14:14 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE 15:15 /* RWIVF */
#define NVCA73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE(i) (8+(i)):(8+(i)) /* RWIVF */
#define NVCA73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE__SIZE_1 8 /* */
#define NVCA73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPC_TILE_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPC_MERGER_TILE_BUFFER_SIZE 31:16 /* RWIUF */
#define NVCA73_SYS_CAPD 0x2c /* RW-4R */
#define NVCA73_SYS_CAPD_NUM_TELLTALE_REGIONS 4:0 /* RWIUF */
#define NVCA73_SYS_CAPD_NUM_FROZEN_FRAME_REGIONS 12:8 /* RWIUF */
#define NVCA73_SYS_CAPD_NUM_ROI 20:16 /* RWIUF */
#define NVCA73_SYS_CAPD_AE_SDP_EXISTS 30:30 /* RWIVF */
#define NVCA73_SYS_CAPD_AE_SDP_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPD_AE_SDP_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPD_AMSS_EXISTS 31:31 /* RWIVF */
#define NVCA73_SYS_CAPD_AMSS_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPD_AMSS_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE 0x34 /* RW-4R */
#define NVCA73_SYS_CAPE_VIRWIN0_EXISTS 0:0 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN1_EXISTS 1:1 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN2_EXISTS 2:2 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN3_EXISTS 3:3 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN4_EXISTS 4:4 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN5_EXISTS 5:5 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN6_EXISTS 6:6 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN7_EXISTS 7:7 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN8_EXISTS 8:8 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN8_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN8_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN9_EXISTS 9:9 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN9_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN9_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN10_EXISTS 10:10 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN10_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN10_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN11_EXISTS 11:11 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN11_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN11_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN12_EXISTS 12:12 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN12_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN12_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN13_EXISTS 13:13 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN13_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN13_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN14_EXISTS 14:14 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN14_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN14_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN15_EXISTS 15:15 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN15_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN15_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN16_EXISTS 16:16 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN16_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN16_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN17_EXISTS 17:17 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN17_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN17_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN18_EXISTS 18:18 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN18_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN18_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN19_EXISTS 19:19 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN19_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN19_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN20_EXISTS 20:20 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN20_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN20_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN21_EXISTS 21:21 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN21_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN21_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN22_EXISTS 22:22 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN22_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN22_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN23_EXISTS 23:23 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN23_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN23_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN24_EXISTS 24:24 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN24_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN24_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN25_EXISTS 25:25 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN25_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN25_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN26_EXISTS 26:26 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN26_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN26_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN27_EXISTS 27:27 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN27_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN27_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN28_EXISTS 28:28 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN28_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN28_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN29_EXISTS 29:29 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN29_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN29_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN30_EXISTS 30:30 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN30_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN30_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN31_EXISTS 31:31 /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN31_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN31_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCA73_SYS_CAPE_VIRWIN_EXISTS__SIZE_1 32 /* */
#define NVCA73_SYS_CAPE_VIRWIN_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_SYS_CAPE_VIRWIN_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_MISC_CAPA_NUM_VMS 17:13 /* RWIUF */
#define NVCA73_LINK_CAP 0x30 /* RW-4R */
#define NVCA73_LINK_CAP_PHYCTRL0_EXISTS 0:0 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL0_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL0_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL1_EXISTS 1:1 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL1_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL1_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL2_EXISTS 2:2 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL2_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL2_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL3_EXISTS 3:3 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL3_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL3_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL4_EXISTS 4:4 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL4_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL4_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL5_EXISTS 5:5 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL5_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL5_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL6_EXISTS 6:6 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL6_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL6_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL7_EXISTS 7:7 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL7_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL7_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL8_EXISTS 8:8 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL8_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL8_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL9_EXISTS 9:9 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL9_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL9_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL10_EXISTS 10:10 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL10_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL10_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL11_EXISTS 11:11 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL11_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL11_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL12_EXISTS 12:12 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL12_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL12_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL13_EXISTS 13:13 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL13_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL13_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL14_EXISTS 14:14 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL14_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL14_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL15_EXISTS 15:15 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL15_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL15_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL16_EXISTS 16:16 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL16_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL16_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL17_EXISTS 17:17 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL17_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL17_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL18_EXISTS 18:18 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL18_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL18_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL19_EXISTS 19:19 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL19_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL19_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL20_EXISTS 20:20 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL20_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL20_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL21_EXISTS 21:21 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL21_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL21_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL22_EXISTS 22:22 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL22_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL22_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL23_EXISTS 23:23 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL23_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL23_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL24_EXISTS 24:24 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL24_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL24_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL25_EXISTS 25:25 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL25_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL25_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL26_EXISTS 26:26 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL26_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL26_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL27_EXISTS 27:27 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL27_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL27_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL28_EXISTS 28:28 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL28_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL28_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL29_EXISTS 29:29 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL29_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL29_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL30_EXISTS 30:30 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL30_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL30_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL31_EXISTS 31:31 /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL31_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL31_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCA73_LINK_CAP_PHYCTRL_EXISTS__SIZE_1 32 /* */
#define NVCA73_LINK_CAP_PHYCTRL_EXISTS_NO 0x00000000 /* RW--V */
#define NVCA73_LINK_CAP_PHYCTRL_EXISTS_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA 0x10 /* RW-4R */
#define NVCA73_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */
#define NVCA73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS 26:26 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_FALSE 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_SUPPORT_MSCG_LPS_TRUE 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC 0x18 /* RW-4R */
#define NVCA73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */
#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */
#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION 13:13 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_FALSE 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPC_SUPPORT_MEMPOOL_YUV_COMPRESSION_TRUE 0x00000001 /* RWI-V */
#define NVCA73_IHUB_COMMON_CAPE 0x24 /* RW-4R */
#define NVCA73_IHUB_COMMON_CAPE_PHYWIN_BUFFER_SIZE 15:0 /* RWIUF */
#define NVCA73_IHUB_COMMON_CAPF 0x28 /* RW-4R */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE 0:0 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN0_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE 1:1 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN1_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE 2:2 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN2_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE 3:3 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN3_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE 4:4 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN4_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE 5:5 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN5_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE 6:6 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN6_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE 7:7 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN7_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE 8:8 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN8_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE 9:9 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN9_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE 10:10 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN10_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE 11:11 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN11_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE 12:12 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN12_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE 13:13 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN13_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE 14:14 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN14_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE 15:15 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN15_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE 16:16 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN16_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE 17:17 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN17_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE 18:18 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN18_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE 19:19 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN19_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE 20:20 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN20_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE 21:21 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN21_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE 22:22 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN22_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE 23:23 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN23_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE 24:24 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN24_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE 25:25 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN25_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE 26:26 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN26_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE 27:27 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN27_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE 28:28 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN28_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE 29:29 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN29_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE 30:30 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN30_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE 31:31 /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN31_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE(i) (0+(i)):(0+(i)) /* RWIVF */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE__SIZE_1 32 /* */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_NO 0x00000000 /* RW--V */
#define NVCA73_IHUB_COMMON_CAPF_PHYWIN_SUPPORT_MULTI_TILE_YES 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA(i) (0x680+(i)*32) /* RW-4A */
#define NVCA73_POSTCOMP_HDR_CAPA__SIZE_1 8 /* */
#define NVCA73_POSTCOMP_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_LTM_PRESENT 25:25 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPA_LTM_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPA_LTM_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPB(i) (0x684+(i)*32) /* RW-4A */
#define NVCA73_POSTCOMP_HDR_CAPB__SIZE_1 8 /* */
#define NVCA73_POSTCOMP_HDR_CAPB_VGA 0:0 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_SZ 12:1 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_LOGNR 15:13 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD 17:17 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_DIRECT 18:18 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPC(i) (0x688+(i)*32) /* RW-4A */
#define NVCA73_POSTCOMP_HDR_CAPC__SIZE_1 8 /* */
#define NVCA73_POSTCOMP_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPD(i) (0x68c+(i)*32) /* RW-4A */
#define NVCA73_POSTCOMP_HDR_CAPD__SIZE_1 8 /* */
#define NVCA73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPE(i) (0x690+(i)*32) /* RW-4A */
#define NVCA73_POSTCOMP_HDR_CAPE__SIZE_1 8 /* */
#define NVCA73_POSTCOMP_HDR_CAPE_DSC_MAXLINEWIDTH 15:0 /* RWIUF */
#define NVCA73_POSTCOMP_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT 18:18 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE 21:19 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_9x9x9 0x00000000 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_17x17x17 0x00000001 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_25x25x25 0x00000002 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_33x33x33 0x00000003 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_4 0x00000004 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_5 0x00000005 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_6 0x00000006 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_MAX_SIZE_RESERVED_7 0x00000007 /* RW--V */
#define NVCA73_POSTCOMP_HDR_CAPE_3DLUT_NUM_CURVES 23:22 /* RWIUF */
#define NVCA73_POSTCOMP_HDR_CAPF(i) (0x694+(i)*32) /* RW-4A */
#define NVCA73_POSTCOMP_HDR_CAPF__SIZE_1 8 /* */
#define NVCA73_POSTCOMP_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPF_LTM_MAX_PIXELS 31:16 /* RWIVF */
#define NVCA73_POSTCOMP_HDR_CAPG(i) (0x698+(i)*32) /* RW-4A */
#define NVCA73_POSTCOMP_HDR_CAPG__SIZE_1 8 /* */
#define NVCA73_POSTCOMP_HDR_CAPG_CMI_SZ 11:0 /* RWIUF */
#define NVCA73_POSTCOMP_HDR_CAPG_CMI_LOGNR 14:12 /* RWIUF */
#define NVCA73_POSTCOMP_HDR_CAPG_CMO_SZ 26:15 /* RWIUF */
#define NVCA73_POSTCOMP_HDR_CAPG_CMO_LOGNR 29:27 /* RWIUF */
#define NVCA73_SOR_CAP(i) (0x144+(i)*8) /* RW-4A */
#define NVCA73_SOR_CAP__SIZE_1 8 /* */
#define NVCA73_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */
#define NVCA73_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */
#define NVCA73_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */
#define NVCA73_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */
#define NVCA73_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_DP_DUAL_MODE 4:4 /* RWIVF */
#define NVCA73_SOR_CAP_DP_DUAL_MODE_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_DP_DUAL_MODE_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */
#define NVCA73_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */
#define NVCA73_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */
#define NVCA73_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */
#define NVCA73_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_DP_TUNNELING_OVER_USB4 15:15 /* RWIVF */
#define NVCA73_SOR_CAP_DP_TUNNELING_OVER_USB4_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_DP_TUNNELING_OVER_USB4_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_SDI 16:16 /* RWIVF */
#define NVCA73_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_DP_DUAL_MST 23:23 /* RWIVF */
#define NVCA73_SOR_CAP_DP_DUAL_MST_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_DP_DUAL_MST_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_DP_A 24:24 /* RWIVF */
#define NVCA73_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_DP_B 25:25 /* RWIVF */
#define NVCA73_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */
#define NVCA73_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */
#define NVCA73_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */
#define NVCA73_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_HDMI_FRL_YUV422 29:29 /* RWIVF */
#define NVCA73_SOR_CAP_HDMI_FRL_YUV422_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_HDMI_FRL_YUV422_TRUE 0x00000001 /* RW--V */
#define NVCA73_SOR_CAP_DP_128B132B 30:30 /* RWIVF */
#define NVCA73_SOR_CAP_DP_128B132B_FALSE 0x00000000 /* RW--V */
#define NVCA73_SOR_CAP_DP_128B132B_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x780+(i)*32) /* RW-4A */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x784+(i)*32) /* RW-4A */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x788+(i)*32) /* RW-4A */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT 13:13 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_FVLUT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x78c+(i)*32) /* RW-4A */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x790+(i)*32) /* RW-4A */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT 13:13 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_FVLUT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x794+(i)*32) /* RW-4A */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
#define NVCA73_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
#define NVCA73_SOR_CLK_CAP(i) (0x608+(i)*4) /* RW-4A */
#define NVCA73_SOR_CLK_CAP__SIZE_1 8 /* */
#define NVCA73_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */
#define NVCA73_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */
#define NVCA73_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */
#ifdef __cplusplus
};
#endif /* extern C */
#endif //_clca73_h_

216
src/common/sdk/nvidia/inc/class/clca7a.h Normal file
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@@ -0,0 +1,216 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clca7a__h_
#define _clca7a__h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCA7A_CURSOR_IMM_CHANNEL_PIO (0x0000CA7A)
typedef volatile struct _clca7a_tag0 {
NvV32 Reserved00[0x2];
NvV32 Free; // 0x00000008 - 0x0000000B
NvV32 Reserved01[0x7D];
NvV32 Update; // 0x00000200 - 0x00000203
NvV32 SetInterlockFlags; // 0x00000204 - 0x00000207
NvV32 SetCursorHotSpotPointOut[2]; // 0x00000208 - 0x0000020F
NvV32 SetWindowInterlockFlags; // 0x00000210 - 0x00000213
NvV32 Reserved02[0x3F7B];
} NVCA7ADispCursorImmControlPio;
#define NVCA7A_FREE (0x00000008)
#define NVCA7A_FREE_COUNT 5:0
#define NVCA7A_UPDATE (0x00000200)
#define NVCA7A_UPDATE_RELEASE_ELV 0:0
#define NVCA7A_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVCA7A_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN 8:4
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVCA7A_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVCA7A_UPDATE_FORCE_FULLSCREEN 12:12
#define NVCA7A_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
#define NVCA7A_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
#define NVCA7A_SET_INTERLOCK_FLAGS (0x00000204)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NVCA7A_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NVCA7A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004)
#define NVCA7A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0
#define NVCA7A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS (0x00000210)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
#define NVCA7A_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clca7a_h

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clca7b_h_
#define _clca7b_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCA7B_WINDOW_IMM_CHANNEL_DMA (0x0000CA7B)
// dma opcode instructions
#define NVCA7B_DMA
#define NVCA7B_DMA_OPCODE 31:29
#define NVCA7B_DMA_OPCODE_METHOD 0x00000000
#define NVCA7B_DMA_OPCODE_JUMP 0x00000001
#define NVCA7B_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NVCA7B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NVCA7B_DMA_METHOD_COUNT 27:18
#define NVCA7B_DMA_METHOD_OFFSET 15:2
#define NVCA7B_DMA_DATA 31:0
#define NVCA7B_DMA_DATA_NOP 0x00000000
#define NVCA7B_DMA_JUMP_OFFSET 15:2
#define NVCA7B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NVCA7B_PUT (0x00000000)
#define NVCA7B_PUT_PTR 13:0
#define NVCA7B_GET (0x00000004)
#define NVCA7B_GET_PTR 13:0
#define NVCA7B_UPDATE (0x00000200)
#define NVCA7B_UPDATE_RELEASE_ELV 0:0
#define NVCA7B_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVCA7B_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVCA7B_UPDATE_INTERLOCK_WITH_WINDOW 1:1
#define NVCA7B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVCA7B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVCA7B_UPDATE_FORCE_FULLSCREEN 4:4
#define NVCA7B_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
#define NVCA7B_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
#define NVCA7B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004)
#define NVCA7B_SET_POINT_OUT_X 15:0
#define NVCA7B_SET_POINT_OUT_Y 31:16
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clca7b_h

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src/common/sdk/nvidia/inc/class/clca7d.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clca7e_h_
#define _clca7e_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVCA7E_WINDOW_CHANNEL_DMA (0x0000CA7E)
// dma opcode instructions
#define NVCA7E_DMA
#define NVCA7E_DMA_OPCODE 31:29
#define NVCA7E_DMA_OPCODE_METHOD 0x00000000
#define NVCA7E_DMA_OPCODE_JUMP 0x00000001
#define NVCA7E_DMA_OPCODE_NONINC_METHOD 0x00000002
#define NVCA7E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
#define NVCA7E_DMA_METHOD_COUNT 27:18
#define NVCA7E_DMA_METHOD_OFFSET 15:2
#define NVCA7E_DMA_DATA 31:0
#define NVCA7E_DMA_DATA_NOP 0x00000000
#define NVCA7E_DMA_JUMP_OFFSET 15:2
#define NVCA7E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
// class methods
#define NVCA7E_PUT (0x00000000)
#define NVCA7E_PUT_PTR 13:0
#define NVCA7E_GET (0x00000004)
#define NVCA7E_GET_PTR 13:0
#define NVCA7E_UPDATE (0x00000200)
#define NVCA7E_UPDATE_RELEASE_ELV 0:0
#define NVCA7E_UPDATE_RELEASE_ELV_FALSE (0x00000000)
#define NVCA7E_UPDATE_RELEASE_ELV_TRUE (0x00000001)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN 8:4
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i))
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
#define NVCA7E_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
#define NVCA7E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12
#define NVCA7E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000)
#define NVCA7E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001)
#define NVCA7E_UPDATE_FORCE_FULLSCREEN 16:16
#define NVCA7E_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
#define NVCA7E_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
#define NVCA7E_SET_SEMAPHORE_ACQUIRE_HI (0x00000204)
#define NVCA7E_SET_SEMAPHORE_ACQUIRE_HI_VALUE 31:0
#define NVCA7E_GET_LINE (0x00000208)
#define NVCA7E_GET_LINE_LINE 15:0
#define NVCA7E_SET_SEMAPHORE_CONTROL (0x0000020C)
#define NVCA7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ 11:11
#define NVCA7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_FALSE (0x00000000)
#define NVCA7E_SET_SEMAPHORE_CONTROL_SKIP_ACQ_TRUE (0x00000001)
#define NVCA7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15
#define NVCA7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000)
#define NVCA7E_SET_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001)
#define NVCA7E_SET_SEMAPHORE_CONTROL_ACQ_MODE 13:12
#define NVCA7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000)
#define NVCA7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001)
#define NVCA7E_SET_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002)
#define NVCA7E_SET_SEMAPHORE_CONTROL_REL_MODE 14:14
#define NVCA7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE (0x00000000)
#define NVCA7E_SET_SEMAPHORE_CONTROL_REL_MODE_WRITE_AWAKEN (0x00000001)
#define NVCA7E_SET_SEMAPHORE_ACQUIRE (0x00000210)
#define NVCA7E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0
#define NVCA7E_SET_SEMAPHORE_RELEASE (0x00000214)
#define NVCA7E_SET_SEMAPHORE_RELEASE_VALUE 31:0
#define NVCA7E_SET_NOTIFIER_CONTROL (0x00000220)
#define NVCA7E_SET_NOTIFIER_CONTROL_MODE 0:0
#define NVCA7E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
#define NVCA7E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
#define NVCA7E_SET_SIZE (0x00000224)
#define NVCA7E_SET_SIZE_WIDTH 15:0
#define NVCA7E_SET_SIZE_HEIGHT 31:16
#define NVCA7E_SET_STORAGE (0x00000228)
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT 3:0
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
#define NVCA7E_SET_PARAMS (0x0000022C)
#define NVCA7E_SET_PARAMS_FORMAT 7:0
#define NVCA7E_SET_PARAMS_FORMAT_I8 (0x0000001E)
#define NVCA7E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F)
#define NVCA7E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
#define NVCA7E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
#define NVCA7E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E)
#define NVCA7E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
#define NVCA7E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6)
#define NVCA7E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
#define NVCA7E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9)
#define NVCA7E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
#define NVCA7E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
#define NVCA7E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
#define NVCA7E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
#define NVCA7E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
#define NVCA7E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028)
#define NVCA7E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029)
#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035)
#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036)
#define NVCA7E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038)
#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A)
#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B)
#define NVCA7E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055)
#define NVCA7E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056)
#define NVCA7E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058)
#define NVCA7E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075)
#define NVCA7E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076)
#define NVCA7E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078)
#define NVCA7E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18
#define NVCA7E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000)
#define NVCA7E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001)
#define NVCA7E_SET_PARAMS_SWAP_UV 19:19
#define NVCA7E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000)
#define NVCA7E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001)
#define NVCA7E_SET_PARAMS_FMT_ROUNDING_MODE 22:22
#define NVCA7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000)
#define NVCA7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001)
#define NVCA7E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004)
#define NVCA7E_SET_PLANAR_STORAGE_PITCH 12:0
#define NVCA7E_SET_SEMAPHORE_RELEASE_HI (0x0000023C)
#define NVCA7E_SET_SEMAPHORE_RELEASE_HI_VALUE 31:0
#define NVCA7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY (0x00000240)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_BEGUN_SEMAPHORE_ARRAY_ADDRESS_HI 31:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY (0x00000244)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ADDRESS_LO 31:4
#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET 3:2
#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE 0:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_BEGUN_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY (0x00000248)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_FINISH_SEMAPHORE_ARRAY_ADDRESS_HI 31:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY (0x0000024C)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ADDRESS_LO 31:4
#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET 3:2
#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_IOVA (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE 0:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_FINISH_SEMAPHORE_ARRAY_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004)
#define NVCA7E_SET_POINT_IN_X 15:0
#define NVCA7E_SET_POINT_IN_Y 31:16
#define NVCA7E_SET_SIZE_IN (0x00000298)
#define NVCA7E_SET_SIZE_IN_WIDTH 15:0
#define NVCA7E_SET_SIZE_IN_HEIGHT 31:16
#define NVCA7E_SET_SIZE_OUT (0x000002A4)
#define NVCA7E_SET_SIZE_OUT_WIDTH 15:0
#define NVCA7E_SET_SIZE_OUT_HEIGHT 31:16
#define NVCA7E_SET_CONTROL_INPUT_SCALER (0x000002A8)
#define NVCA7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS 2:0
#define NVCA7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001)
#define NVCA7E_SET_CONTROL_INPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004)
#define NVCA7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS 6:4
#define NVCA7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001)
#define NVCA7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_TAPS_TAPS_5 (0x00000004)
#define NVCA7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE 8:8
#define NVCA7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_CONTROL_INPUT_SCALER_VERTICAL_FORCE_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE 9:9
#define NVCA7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_CONTROL_INPUT_SCALER_HORIZONTAL_FORCE_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_INPUT_SCALER_COEFF_VALUE (0x000002AC)
#define NVCA7E_SET_INPUT_SCALER_COEFF_VALUE_DATA 9:0
#define NVCA7E_SET_INPUT_SCALER_COEFF_VALUE_INDEX 19:12
#define NVCA7E_SET_COMPOSITION_CONTROL (0x000002EC)
#define NVCA7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0
#define NVCA7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000)
#define NVCA7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001)
#define NVCA7E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002)
#define NVCA7E_SET_COMPOSITION_CONTROL_DEPTH 11:4
#define NVCA7E_SET_COMPOSITION_CONTROL_BYPASS 16:16
#define NVCA7E_SET_COMPOSITION_CONTROL_BYPASS_DISABLE (0x00000000)
#define NVCA7E_SET_COMPOSITION_CONTROL_BYPASS_ENABLE (0x00000001)
#define NVCA7E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0)
#define NVCA7E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0
#define NVCA7E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003)
#define NVCA7E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007)
#define NVCA7E_SET_KEY_ALPHA (0x000002F8)
#define NVCA7E_SET_KEY_ALPHA_MIN 15:0
#define NVCA7E_SET_KEY_ALPHA_MAX 31:16
#define NVCA7E_SET_KEY_RED_CR (0x000002FC)
#define NVCA7E_SET_KEY_RED_CR_MIN 15:0
#define NVCA7E_SET_KEY_RED_CR_MAX 31:16
#define NVCA7E_SET_KEY_GREEN_Y (0x00000300)
#define NVCA7E_SET_KEY_GREEN_Y_MIN 15:0
#define NVCA7E_SET_KEY_GREEN_Y_MAX 31:16
#define NVCA7E_SET_KEY_BLUE_CB (0x00000304)
#define NVCA7E_SET_KEY_BLUE_CB_MIN 15:0
#define NVCA7E_SET_KEY_BLUE_CB_MAX 31:16
#define NVCA7E_SET_PRESENT_CONTROL (0x00000308)
#define NVCA7E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0
#define NVCA7E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4
#define NVCA7E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
#define NVCA7E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
#define NVCA7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8
#define NVCA7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
#define NVCA7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE 13:12
#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000)
#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001)
#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002)
#define NVCA7E_SET_ACQ_SEMAPHORE_VALUE_HI (0x0000030C)
#define NVCA7E_SET_ACQ_SEMAPHORE_VALUE_HI_VALUE 31:0
#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL (0x00000330)
#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE 15:15
#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_32BIT (0x00000000)
#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_PAYLOAD_SIZE_PAYLOAD_64BIT (0x00000001)
#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE 13:12
#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_EQ (0x00000000)
#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_CGEQ (0x00000001)
#define NVCA7E_SET_ACQ_SEMAPHORE_CONTROL_ACQ_MODE_STRICT_GEQ (0x00000002)
#define NVCA7E_SET_ACQ_SEMAPHORE_VALUE (0x00000334)
#define NVCA7E_SET_ACQ_SEMAPHORE_VALUE_VALUE 31:0
#define NVCA7E_SET_SCAN_DIRECTION (0x0000033C)
#define NVCA7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION 0:0
#define NVCA7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_LEFT (0x00000000)
#define NVCA7E_SET_SCAN_DIRECTION_HORIZONTAL_DIRECTION_FROM_RIGHT (0x00000001)
#define NVCA7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION 1:1
#define NVCA7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_TOP (0x00000000)
#define NVCA7E_SET_SCAN_DIRECTION_VERTICAL_DIRECTION_FROM_BOTTOM (0x00000001)
#define NVCA7E_SET_SCAN_DIRECTION_COLUMN_ORDER 2:2
#define NVCA7E_SET_SCAN_DIRECTION_COLUMN_ORDER_FALSE (0x00000000)
#define NVCA7E_SET_SCAN_DIRECTION_COLUMN_ORDER_TRUE (0x00000001)
#define NVCA7E_SET_TIMESTAMP_ORIGIN_LO (0x00000340)
#define NVCA7E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0
#define NVCA7E_SET_TIMESTAMP_ORIGIN_HI (0x00000344)
#define NVCA7E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0
#define NVCA7E_SET_UPDATE_TIMESTAMP_LO (0x00000348)
#define NVCA7E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0
#define NVCA7E_SET_UPDATE_TIMESTAMP_HI (0x0000034C)
#define NVCA7E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0
#define NVCA7E_SET_INTERLOCK_FLAGS (0x00000370)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
#define NVCA7E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
#define NVCA7E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
#define NVCA7E_SET_CHROMA_VER (0x00000378)
#define NVCA7E_SET_CHROMA_VER_POSITION 1:0
#define NVCA7E_SET_CHROMA_VER_POSITION_TOP (0x00000000)
#define NVCA7E_SET_CHROMA_VER_POSITION_CENTER (0x00000001)
#define NVCA7E_SET_CHROMA_VER_POSITION_BOTTOM (0x00000002)
#define NVCA7E_SET_CHROMA_VER_USE_SWPOSITION 2:2
#define NVCA7E_SET_CHROMA_VER_USE_SWPOSITION_FALSE (0x00000000)
#define NVCA7E_SET_CHROMA_VER_USE_SWPOSITION_TRUE (0x00000001)
#define NVCA7E_SET_CHROMA_VER_WEIGHT_ODD 4:3
#define NVCA7E_SET_CHROMA_VER_WEIGHT_ODD_WT_0 (0x00000000)
#define NVCA7E_SET_CHROMA_VER_WEIGHT_ODD_WT_QUARTER (0x00000001)
#define NVCA7E_SET_CHROMA_VER_WEIGHT_ODD_WT_HALF (0x00000002)
#define NVCA7E_SET_CHROMA_VER_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003)
#define NVCA7E_SET_CHROMA_VER_WEIGHT_EVEN 6:5
#define NVCA7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_0 (0x00000000)
#define NVCA7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_QUARTER (0x00000001)
#define NVCA7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_HALF (0x00000002)
#define NVCA7E_SET_CHROMA_VER_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003)
#define NVCA7E_SET_CHROMA_VER_USE_SWWEIGHTS 7:7
#define NVCA7E_SET_CHROMA_VER_USE_SWWEIGHTS_FALSE (0x00000000)
#define NVCA7E_SET_CHROMA_VER_USE_SWWEIGHTS_TRUE (0x00000001)
#define NVCA7E_SET_CHROMA_HOR (0x0000037C)
#define NVCA7E_SET_CHROMA_HOR_REPLACE_ODD 0:0
#define NVCA7E_SET_CHROMA_HOR_REPLACE_ODD_DISABLE (0x00000000)
#define NVCA7E_SET_CHROMA_HOR_REPLACE_ODD_ENABLE (0x00000001)
#define NVCA7E_SET_CHROMA_HOR_REPLACE_EVEN 1:1
#define NVCA7E_SET_CHROMA_HOR_REPLACE_EVEN_DISABLE (0x00000000)
#define NVCA7E_SET_CHROMA_HOR_REPLACE_EVEN_ENABLE (0x00000001)
#define NVCA7E_SET_CHROMA_HOR_WEIGHT_ODD 3:2
#define NVCA7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_0 (0x00000000)
#define NVCA7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_QUARTER (0x00000001)
#define NVCA7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_HALF (0x00000002)
#define NVCA7E_SET_CHROMA_HOR_WEIGHT_ODD_WT_THREE_QUARTER (0x00000003)
#define NVCA7E_SET_CHROMA_HOR_WEIGHT_EVEN 5:4
#define NVCA7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_0 (0x00000000)
#define NVCA7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_QUARTER (0x00000001)
#define NVCA7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_HALF (0x00000002)
#define NVCA7E_SET_CHROMA_HOR_WEIGHT_EVEN_WT_THREE_QUARTER (0x00000003)
#define NVCA7E_SET_CHROMA_HOR_USE_SWWEIGHTS 6:6
#define NVCA7E_SET_CHROMA_HOR_USE_SWWEIGHTS_FALSE (0x00000000)
#define NVCA7E_SET_CHROMA_HOR_USE_SWWEIGHTS_TRUE (0x00000001)
#define NVCA7E_SET_EXT_PACKET_CONTROL (0x00000398)
#define NVCA7E_SET_EXT_PACKET_CONTROL_ENABLE 0:0
#define NVCA7E_SET_EXT_PACKET_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_EXT_PACKET_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_EXT_PACKET_CONTROL_LOCATION 4:4
#define NVCA7E_SET_EXT_PACKET_CONTROL_LOCATION_VSYNC (0x00000000)
#define NVCA7E_SET_EXT_PACKET_CONTROL_LOCATION_VBLANK (0x00000001)
#define NVCA7E_SET_EXT_PACKET_CONTROL_FREQUENCY 8:8
#define NVCA7E_SET_EXT_PACKET_CONTROL_FREQUENCY_EVERY_FRAME (0x00000000)
#define NVCA7E_SET_EXT_PACKET_CONTROL_FREQUENCY_ONCE (0x00000001)
#define NVCA7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE 12:12
#define NVCA7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_DISABLE (0x00000000)
#define NVCA7E_SET_EXT_PACKET_CONTROL_HEADER_OVERRIDE_ENABLE (0x00000001)
#define NVCA7E_SET_EXT_PACKET_CONTROL_SIZE 27:16
#define NVCA7E_SET_EXT_PACKET_DATA (0x0000039C)
#define NVCA7E_SET_EXT_PACKET_DATA_DB0 7:0
#define NVCA7E_SET_EXT_PACKET_DATA_DB1 15:8
#define NVCA7E_SET_EXT_PACKET_DATA_DB2 23:16
#define NVCA7E_SET_EXT_PACKET_DATA_DB3 31:24
#define NVCA7E_SET_WIN_INFOFRAME (0x000003A0)
#define NVCA7E_SET_WIN_INFOFRAME_FID 7:0
#define NVCA7E_SET_WIN_INFOFRAME_EN 16:16
#define NVCA7E_SET_WIN_INFOFRAME_EN_DISABLE (0x00000000)
#define NVCA7E_SET_WIN_INFOFRAME_EN_ENABLE (0x00000001)
#define NVCA7E_SET_FMT_COEFFICIENT_C00 (0x00000400)
#define NVCA7E_SET_FMT_COEFFICIENT_C00_VALUE 20:0
#define NVCA7E_SET_FMT_COEFFICIENT_C01 (0x00000404)
#define NVCA7E_SET_FMT_COEFFICIENT_C01_VALUE 20:0
#define NVCA7E_SET_FMT_COEFFICIENT_C02 (0x00000408)
#define NVCA7E_SET_FMT_COEFFICIENT_C02_VALUE 20:0
#define NVCA7E_SET_FMT_COEFFICIENT_C03 (0x0000040C)
#define NVCA7E_SET_FMT_COEFFICIENT_C03_VALUE 20:0
#define NVCA7E_SET_FMT_COEFFICIENT_C10 (0x00000410)
#define NVCA7E_SET_FMT_COEFFICIENT_C10_VALUE 20:0
#define NVCA7E_SET_FMT_COEFFICIENT_C11 (0x00000414)
#define NVCA7E_SET_FMT_COEFFICIENT_C11_VALUE 20:0
#define NVCA7E_SET_FMT_COEFFICIENT_C12 (0x00000418)
#define NVCA7E_SET_FMT_COEFFICIENT_C12_VALUE 20:0
#define NVCA7E_SET_FMT_COEFFICIENT_C13 (0x0000041C)
#define NVCA7E_SET_FMT_COEFFICIENT_C13_VALUE 20:0
#define NVCA7E_SET_FMT_COEFFICIENT_C20 (0x00000420)
#define NVCA7E_SET_FMT_COEFFICIENT_C20_VALUE 20:0
#define NVCA7E_SET_FMT_COEFFICIENT_C21 (0x00000424)
#define NVCA7E_SET_FMT_COEFFICIENT_C21_VALUE 20:0
#define NVCA7E_SET_FMT_COEFFICIENT_C22 (0x00000428)
#define NVCA7E_SET_FMT_COEFFICIENT_C22_VALUE 20:0
#define NVCA7E_SET_FMT_COEFFICIENT_C23 (0x0000042C)
#define NVCA7E_SET_FMT_COEFFICIENT_C23_VALUE 20:0
#define NVCA7E_SET_ILUT_CONTROL (0x00000440)
#define NVCA7E_SET_ILUT_CONTROL_INTERPOLATE 0:0
#define NVCA7E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCA7E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCA7E_SET_ILUT_CONTROL_MIRROR 1:1
#define NVCA7E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVCA7E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVCA7E_SET_ILUT_CONTROL_MODE 3:2
#define NVCA7E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000)
#define NVCA7E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001)
#define NVCA7E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002)
#define NVCA7E_SET_ILUT_CONTROL_SIZE 18:8
#define NVCA7E_SET_CSC00CONTROL (0x0000045C)
#define NVCA7E_SET_CSC00CONTROL_ENABLE 0:0
#define NVCA7E_SET_CSC00CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_CSC00CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_CSC00COEFFICIENT_C00 (0x00000460)
#define NVCA7E_SET_CSC00COEFFICIENT_C00_VALUE 20:0
#define NVCA7E_SET_CSC00COEFFICIENT_C01 (0x00000464)
#define NVCA7E_SET_CSC00COEFFICIENT_C01_VALUE 20:0
#define NVCA7E_SET_CSC00COEFFICIENT_C02 (0x00000468)
#define NVCA7E_SET_CSC00COEFFICIENT_C02_VALUE 20:0
#define NVCA7E_SET_CSC00COEFFICIENT_C03 (0x0000046C)
#define NVCA7E_SET_CSC00COEFFICIENT_C03_VALUE 20:0
#define NVCA7E_SET_CSC00COEFFICIENT_C10 (0x00000470)
#define NVCA7E_SET_CSC00COEFFICIENT_C10_VALUE 20:0
#define NVCA7E_SET_CSC00COEFFICIENT_C11 (0x00000474)
#define NVCA7E_SET_CSC00COEFFICIENT_C11_VALUE 20:0
#define NVCA7E_SET_CSC00COEFFICIENT_C12 (0x00000478)
#define NVCA7E_SET_CSC00COEFFICIENT_C12_VALUE 20:0
#define NVCA7E_SET_CSC00COEFFICIENT_C13 (0x0000047C)
#define NVCA7E_SET_CSC00COEFFICIENT_C13_VALUE 20:0
#define NVCA7E_SET_CSC00COEFFICIENT_C20 (0x00000480)
#define NVCA7E_SET_CSC00COEFFICIENT_C20_VALUE 20:0
#define NVCA7E_SET_CSC00COEFFICIENT_C21 (0x00000484)
#define NVCA7E_SET_CSC00COEFFICIENT_C21_VALUE 20:0
#define NVCA7E_SET_CSC00COEFFICIENT_C22 (0x00000488)
#define NVCA7E_SET_CSC00COEFFICIENT_C22_VALUE 20:0
#define NVCA7E_SET_CSC00COEFFICIENT_C23 (0x0000048C)
#define NVCA7E_SET_CSC00COEFFICIENT_C23_VALUE 20:0
#define NVCA7E_SET_CSC0LUT_FP_NORM_SCALE (0x00000490)
#define NVCA7E_SET_CSC0LUT_FP_NORM_SCALE_VALUE 31:0
#define NVCA7E_SET_CSC0LUT_CONTROL (0x000004A0)
#define NVCA7E_SET_CSC0LUT_CONTROL_INTERPOLATE 0:0
#define NVCA7E_SET_CSC0LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCA7E_SET_CSC0LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCA7E_SET_CSC0LUT_CONTROL_MIRROR 1:1
#define NVCA7E_SET_CSC0LUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVCA7E_SET_CSC0LUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVCA7E_SET_CSC0LUT_CONTROL_ENABLE 4:4
#define NVCA7E_SET_CSC0LUT_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_CSC0LUT_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_CSC0LUT_CONTROL_CURVE 6:5
#define NVCA7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000)
#define NVCA7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001)
#define NVCA7E_SET_CSC0LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002)
#define NVCA7E_SET_CSC01CONTROL (0x000004BC)
#define NVCA7E_SET_CSC01CONTROL_ENABLE 0:0
#define NVCA7E_SET_CSC01CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_CSC01CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_CSC01COEFFICIENT_C00 (0x000004C0)
#define NVCA7E_SET_CSC01COEFFICIENT_C00_VALUE 20:0
#define NVCA7E_SET_CSC01COEFFICIENT_C01 (0x000004C4)
#define NVCA7E_SET_CSC01COEFFICIENT_C01_VALUE 20:0
#define NVCA7E_SET_CSC01COEFFICIENT_C02 (0x000004C8)
#define NVCA7E_SET_CSC01COEFFICIENT_C02_VALUE 20:0
#define NVCA7E_SET_CSC01COEFFICIENT_C03 (0x000004CC)
#define NVCA7E_SET_CSC01COEFFICIENT_C03_VALUE 20:0
#define NVCA7E_SET_CSC01COEFFICIENT_C10 (0x000004D0)
#define NVCA7E_SET_CSC01COEFFICIENT_C10_VALUE 20:0
#define NVCA7E_SET_CSC01COEFFICIENT_C11 (0x000004D4)
#define NVCA7E_SET_CSC01COEFFICIENT_C11_VALUE 20:0
#define NVCA7E_SET_CSC01COEFFICIENT_C12 (0x000004D8)
#define NVCA7E_SET_CSC01COEFFICIENT_C12_VALUE 20:0
#define NVCA7E_SET_CSC01COEFFICIENT_C13 (0x000004DC)
#define NVCA7E_SET_CSC01COEFFICIENT_C13_VALUE 20:0
#define NVCA7E_SET_CSC01COEFFICIENT_C20 (0x000004E0)
#define NVCA7E_SET_CSC01COEFFICIENT_C20_VALUE 20:0
#define NVCA7E_SET_CSC01COEFFICIENT_C21 (0x000004E4)
#define NVCA7E_SET_CSC01COEFFICIENT_C21_VALUE 20:0
#define NVCA7E_SET_CSC01COEFFICIENT_C22 (0x000004E8)
#define NVCA7E_SET_CSC01COEFFICIENT_C22_VALUE 20:0
#define NVCA7E_SET_CSC01COEFFICIENT_C23 (0x000004EC)
#define NVCA7E_SET_CSC01COEFFICIENT_C23_VALUE 20:0
#define NVCA7E_SET_TMO_CONTROL (0x00000500)
#define NVCA7E_SET_TMO_CONTROL_INTERPOLATE 0:0
#define NVCA7E_SET_TMO_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCA7E_SET_TMO_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCA7E_SET_TMO_CONTROL_SAT_MODE 3:2
#define NVCA7E_SET_TMO_CONTROL_SIZE 18:8
#define NVCA7E_SET_TMO_LOW_INTENSITY_ZONE (0x00000508)
#define NVCA7E_SET_TMO_LOW_INTENSITY_ZONE_END 29:16
#define NVCA7E_SET_TMO_LOW_INTENSITY_VALUE (0x0000050C)
#define NVCA7E_SET_TMO_LOW_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVCA7E_SET_TMO_LOW_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVCA7E_SET_TMO_LOW_INTENSITY_VALUE_THRESHOLD 31:24
#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_ZONE (0x00000510)
#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_ZONE_START 13:0
#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_ZONE_END 29:16
#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_VALUE (0x00000514)
#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVCA7E_SET_TMO_MEDIUM_INTENSITY_VALUE_THRESHOLD 31:24
#define NVCA7E_SET_TMO_HIGH_INTENSITY_ZONE (0x00000518)
#define NVCA7E_SET_TMO_HIGH_INTENSITY_ZONE_START 13:0
#define NVCA7E_SET_TMO_HIGH_INTENSITY_VALUE (0x0000051C)
#define NVCA7E_SET_TMO_HIGH_INTENSITY_VALUE_LIN_WEIGHT 8:0
#define NVCA7E_SET_TMO_HIGH_INTENSITY_VALUE_NON_LIN_WEIGHT 20:12
#define NVCA7E_SET_TMO_HIGH_INTENSITY_VALUE_THRESHOLD 31:24
#define NVCA7E_SET_CSC10CONTROL (0x0000053C)
#define NVCA7E_SET_CSC10CONTROL_ENABLE 0:0
#define NVCA7E_SET_CSC10CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_CSC10CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_CSC10COEFFICIENT_C00 (0x00000540)
#define NVCA7E_SET_CSC10COEFFICIENT_C00_VALUE 20:0
#define NVCA7E_SET_CSC10COEFFICIENT_C01 (0x00000544)
#define NVCA7E_SET_CSC10COEFFICIENT_C01_VALUE 20:0
#define NVCA7E_SET_CSC10COEFFICIENT_C02 (0x00000548)
#define NVCA7E_SET_CSC10COEFFICIENT_C02_VALUE 20:0
#define NVCA7E_SET_CSC10COEFFICIENT_C03 (0x0000054C)
#define NVCA7E_SET_CSC10COEFFICIENT_C03_VALUE 20:0
#define NVCA7E_SET_CSC10COEFFICIENT_C10 (0x00000550)
#define NVCA7E_SET_CSC10COEFFICIENT_C10_VALUE 20:0
#define NVCA7E_SET_CSC10COEFFICIENT_C11 (0x00000554)
#define NVCA7E_SET_CSC10COEFFICIENT_C11_VALUE 20:0
#define NVCA7E_SET_CSC10COEFFICIENT_C12 (0x00000558)
#define NVCA7E_SET_CSC10COEFFICIENT_C12_VALUE 20:0
#define NVCA7E_SET_CSC10COEFFICIENT_C13 (0x0000055C)
#define NVCA7E_SET_CSC10COEFFICIENT_C13_VALUE 20:0
#define NVCA7E_SET_CSC10COEFFICIENT_C20 (0x00000560)
#define NVCA7E_SET_CSC10COEFFICIENT_C20_VALUE 20:0
#define NVCA7E_SET_CSC10COEFFICIENT_C21 (0x00000564)
#define NVCA7E_SET_CSC10COEFFICIENT_C21_VALUE 20:0
#define NVCA7E_SET_CSC10COEFFICIENT_C22 (0x00000568)
#define NVCA7E_SET_CSC10COEFFICIENT_C22_VALUE 20:0
#define NVCA7E_SET_CSC10COEFFICIENT_C23 (0x0000056C)
#define NVCA7E_SET_CSC10COEFFICIENT_C23_VALUE 20:0
#define NVCA7E_SET_CSC1LUT_FP_SCALE (0x00000570)
#define NVCA7E_SET_CSC1LUT_FP_SCALE_VALUE 15:0
#define NVCA7E_SET_CSC1LUT_CONTROL (0x00000580)
#define NVCA7E_SET_CSC1LUT_CONTROL_INTERPOLATE 0:0
#define NVCA7E_SET_CSC1LUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
#define NVCA7E_SET_CSC1LUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
#define NVCA7E_SET_CSC1LUT_CONTROL_MIRROR 1:1
#define NVCA7E_SET_CSC1LUT_CONTROL_MIRROR_DISABLE (0x00000000)
#define NVCA7E_SET_CSC1LUT_CONTROL_MIRROR_ENABLE (0x00000001)
#define NVCA7E_SET_CSC1LUT_CONTROL_ENABLE 4:4
#define NVCA7E_SET_CSC1LUT_CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_CSC1LUT_CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_CSC1LUT_CONTROL_CURVE 6:5
#define NVCA7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_PQ (0x00000000)
#define NVCA7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_HLG (0x00000001)
#define NVCA7E_SET_CSC1LUT_CONTROL_CURVE_CSCLUT_DIRECT (0x00000002)
#define NVCA7E_SET_CSC11CONTROL (0x0000059C)
#define NVCA7E_SET_CSC11CONTROL_ENABLE 0:0
#define NVCA7E_SET_CSC11CONTROL_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_CSC11CONTROL_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_CSC11CONTROL_LEVEL 7:2
#define NVCA7E_SET_CSC11COEFFICIENT_C00 (0x000005A0)
#define NVCA7E_SET_CSC11COEFFICIENT_C00_VALUE 20:0
#define NVCA7E_SET_CSC11COEFFICIENT_C01 (0x000005A4)
#define NVCA7E_SET_CSC11COEFFICIENT_C01_VALUE 20:0
#define NVCA7E_SET_CSC11COEFFICIENT_C02 (0x000005A8)
#define NVCA7E_SET_CSC11COEFFICIENT_C02_VALUE 20:0
#define NVCA7E_SET_CSC11COEFFICIENT_C03 (0x000005AC)
#define NVCA7E_SET_CSC11COEFFICIENT_C03_VALUE 20:0
#define NVCA7E_SET_CSC11COEFFICIENT_C10 (0x000005B0)
#define NVCA7E_SET_CSC11COEFFICIENT_C10_VALUE 20:0
#define NVCA7E_SET_CSC11COEFFICIENT_C11 (0x000005B4)
#define NVCA7E_SET_CSC11COEFFICIENT_C11_VALUE 20:0
#define NVCA7E_SET_CSC11COEFFICIENT_C12 (0x000005B8)
#define NVCA7E_SET_CSC11COEFFICIENT_C12_VALUE 20:0
#define NVCA7E_SET_CSC11COEFFICIENT_C13 (0x000005BC)
#define NVCA7E_SET_CSC11COEFFICIENT_C13_VALUE 20:0
#define NVCA7E_SET_CSC11COEFFICIENT_C20 (0x000005C0)
#define NVCA7E_SET_CSC11COEFFICIENT_C20_VALUE 20:0
#define NVCA7E_SET_CSC11COEFFICIENT_C21 (0x000005C4)
#define NVCA7E_SET_CSC11COEFFICIENT_C21_VALUE 20:0
#define NVCA7E_SET_CSC11COEFFICIENT_C22 (0x000005C8)
#define NVCA7E_SET_CSC11COEFFICIENT_C22_VALUE 20:0
#define NVCA7E_SET_CSC11COEFFICIENT_C23 (0x000005CC)
#define NVCA7E_SET_CSC11COEFFICIENT_C23_VALUE 20:0
#define NVCA7E_SET_CLAMP_RANGE (0x000005D0)
#define NVCA7E_SET_CLAMP_RANGE_LOW 15:0
#define NVCA7E_SET_CLAMP_RANGE_HIGH 31:16
#define NVCA7E_SW_RESERVED(b) (0x000005D4 + (b)*0x00000004)
#define NVCA7E_SW_RESERVED_VALUE 31:0
#define NVCA7E_SET_DIRTY_RECT_SIZE (0x000005E4)
#define NVCA7E_SET_DIRTY_RECT_SIZE_WIDTH 15:0
#define NVCA7E_SET_DIRTY_RECT_SIZE_HEIGHT 31:16
#define NVCA7E_SET_DIRTY_RECT_POSITION (0x000005E8)
#define NVCA7E_SET_DIRTY_RECT_POSITION_X 15:0
#define NVCA7E_SET_DIRTY_RECT_POSITION_Y 31:16
#define NVCA7E_SET_SUPERFRAME (0x000005EC)
#define NVCA7E_SET_SUPERFRAME_ENABLE 0:0
#define NVCA7E_SET_SUPERFRAME_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_SUPERFRAME_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_SUPERFRAME_MODE 2:1
#define NVCA7E_SET_SUPERFRAME_MODE_FIXED (0x00000000)
#define NVCA7E_SET_SUPERFRAME_MODE_DYNAMIC (0x00000001)
#define NVCA7E_SET_SUPERFRAME_MODE_SW (0x00000003)
#define NVCA7E_SET_SUPERFRAME_RATIO_IN 15:8
#define NVCA7E_SET_SUPERFRAME_RATIO_OUT 23:16
#define NVCA7E_SET_SUPERFRAME_START_COUNT 31:24
#define NVCA7E_SET_INFOFRAME_CTRL(b) (0x000005F0 + (b)*0x00000004)
#define NVCA7E_SET_INFOFRAME_CTRL_ENABLE 0:0
#define NVCA7E_SET_INFOFRAME_CTRL_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_INFOFRAME_CTRL_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_INFOFRAME_CTRL_LOCATION 5:4
#define NVCA7E_SET_INFOFRAME_CTRL_LOCATION_VBLANK (0x00000000)
#define NVCA7E_SET_INFOFRAME_CTRL_LOCATION_VSYNC (0x00000001)
#define NVCA7E_SET_INFOFRAME_CTRL_LOCATION_LINE (0x00000002)
#define NVCA7E_SET_INFOFRAME_CTRL_LINE_ID 30:16
#define NVCA7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED 31:31
#define NVCA7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_DISABLE (0x00000000)
#define NVCA7E_SET_INFOFRAME_CTRL_LINE_ID_REVERSED_ENABLE (0x00000001)
#define NVCA7E_SET_INFOFRAME_HEADER(b) (0x000005F8 + (b)*0x00000004)
#define NVCA7E_SET_INFOFRAME_HEADER_HB0 7:0
#define NVCA7E_SET_INFOFRAME_HEADER_HB1 15:8
#define NVCA7E_SET_INFOFRAME_HEADER_HB2 23:16
#define NVCA7E_SET_INFOFRAME_HEADER_HB3 31:24
#define NVCA7E_SET_INFOFRAME_DATA0(b) (0x00000600 + (b)*0x00000004)
#define NVCA7E_SET_INFOFRAME_DATA0_DB0 7:0
#define NVCA7E_SET_INFOFRAME_DATA0_DB1 15:8
#define NVCA7E_SET_INFOFRAME_DATA0_DB2 23:16
#define NVCA7E_SET_INFOFRAME_DATA0_DB3 31:24
#define NVCA7E_SET_INFOFRAME_DATA1(b) (0x00000608 + (b)*0x00000004)
#define NVCA7E_SET_INFOFRAME_DATA1_DB4 7:0
#define NVCA7E_SET_INFOFRAME_DATA1_DB5 15:8
#define NVCA7E_SET_INFOFRAME_DATA1_DB6 23:16
#define NVCA7E_SET_INFOFRAME_DATA1_DB7 31:24
#define NVCA7E_SET_INFOFRAME_DATA2(b) (0x00000610 + (b)*0x00000004)
#define NVCA7E_SET_INFOFRAME_DATA2_DB8 7:0
#define NVCA7E_SET_INFOFRAME_DATA2_DB9 15:8
#define NVCA7E_SET_INFOFRAME_DATA2_DB10 23:16
#define NVCA7E_SET_INFOFRAME_DATA2_DB11 31:24
#define NVCA7E_SET_INFOFRAME_DATA3(b) (0x00000618 + (b)*0x00000004)
#define NVCA7E_SET_INFOFRAME_DATA3_DB12 7:0
#define NVCA7E_SET_INFOFRAME_DATA3_DB13 15:8
#define NVCA7E_SET_INFOFRAME_DATA3_DB14 23:16
#define NVCA7E_SET_INFOFRAME_DATA3_DB15 31:24
#define NVCA7E_SET_INFOFRAME_DATA4(b) (0x00000620 + (b)*0x00000004)
#define NVCA7E_SET_INFOFRAME_DATA4_DB16 7:0
#define NVCA7E_SET_INFOFRAME_DATA4_DB17 15:8
#define NVCA7E_SET_INFOFRAME_DATA4_DB18 23:16
#define NVCA7E_SET_INFOFRAME_DATA4_DB19 31:24
#define NVCA7E_SET_INFOFRAME_DATA5(b) (0x00000628 + (b)*0x00000004)
#define NVCA7E_SET_INFOFRAME_DATA5_DB20 7:0
#define NVCA7E_SET_INFOFRAME_DATA5_DB21 15:8
#define NVCA7E_SET_INFOFRAME_DATA5_DB22 23:16
#define NVCA7E_SET_INFOFRAME_DATA5_DB23 31:24
#define NVCA7E_SET_INFOFRAME_DATA6(b) (0x00000630 + (b)*0x00000004)
#define NVCA7E_SET_INFOFRAME_DATA6_DB24 7:0
#define NVCA7E_SET_INFOFRAME_DATA6_DB25 15:8
#define NVCA7E_SET_INFOFRAME_DATA6_DB26 23:16
#define NVCA7E_SET_INFOFRAME_DATA6_DB27 31:24
#define NVCA7E_SET_INFOFRAME_DATA7(b) (0x00000638 + (b)*0x00000004)
#define NVCA7E_SET_INFOFRAME_DATA7_DB28 7:0
#define NVCA7E_SET_INFOFRAME_DATA7_DB29 15:8
#define NVCA7E_SET_INFOFRAME_DATA7_DB30 23:16
#define NVCA7E_SET_INFOFRAME_DATA7_DB31 31:24
#define NVCA7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE (0x00000640)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_SEMAPHORE_ADDRESS_HI 31:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE (0x00000644)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ADDRESS_LO 31:4
#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET 3:2
#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_IOVA (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE 0:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_SEMAPHORE_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE (0x00000648)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ACQ_SEMAPHORE_ADDRESS_HI 31:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE (0x0000064C)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ADDRESS_LO 31:4
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET 3:2
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_IOVA (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE 0:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ACQ_SEMAPHORE_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000650)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000654)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ISO(b) (0x00000658 + (b)*0x00000004)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ISO_ADDRESS_HI 31:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO(b) (0x00000670 + (b)*0x00000004)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ADDRESS_LO 31:4
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET 3:2
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_IOVA (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND 1:1
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE 0:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ILUT (0x00000688)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ILUT_ADDRESS_HI 31:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT (0x0000068C)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ADDRESS_LO 31:4
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET 3:2
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_IOVA (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE 0:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_ENABLE (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_TMO_LUT (0x00000690)
#define NVCA7E_SET_SURFACE_ADDRESS_HI_TMO_LUT_ADDRESS_HI 31:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT (0x00000694)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ADDRESS_LO 31:4
#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET 3:2
#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_IOVA (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_NVM (0x00000001)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI (0x00000002)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE 0:0
#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_DISABLE (0x00000000)
#define NVCA7E_SET_SURFACE_ADDRESS_LO_TMO_LUT_ENABLE_ENABLE (0x00000001)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _clca7e_h

44
src/common/sdk/nvidia/inc/class/clcab5.h Normal file
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@@ -0,0 +1,44 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcab5_h_
#define _clcab5_h_
#define BLACKWELL_DMA_COPY_B (0x0000CAB5)
#define NVCAB5_LAUNCH_DMA (0x00000300)
#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0
#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000)
#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001)
#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002)
#define NVCAB5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PREFETCH (0x00000003)
#define NVCAB5_REQ_ATTR (0x00000754)
#define NVCAB5_REQ_ATTR_PREFETCH_L2_CLASS 1:0
#define NVCAB5_REQ_ATTR_PREFETCH_L2_CLASS_EVICT_FIRST (0x00000000)
#define NVCAB5_REQ_ATTR_PREFETCH_L2_CLASS_EVICT_NORMAL (0x00000001)
#define NVCAB5_REQ_ATTR_PREFETCH_L2_CLASS_EVICT_LAST (0x00000002)
#define NVCAB5_REQ_ATTR_PREFETCH_L2_CLASS_EVICT_DEMOTE (0x00000003)
#endif /* _clcab5_h_ */

30
src/common/sdk/nvidia/inc/class/clce97.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clce97_h_
#define _clce97_h_
#define BLACKWELL_B 0xCE97
#endif /* _clce97_h_ */

30
src/common/sdk/nvidia/inc/class/clcec0.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcec0_h_
#define _clcec0_h_
#define BLACKWELL_COMPUTE_B 0xCEC0
#endif /* _clcec0_h_ */

30
src/common/sdk/nvidia/inc/class/clcfb0.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcfb0_h_
#define _clcfb0_h_
#define NVCFB0_VIDEO_DECODER (0x0000CFB0)
#endif /* _clcfb0_h_ */

30
src/common/sdk/nvidia/inc/class/clcfb7.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcfb7_h_
#define _clcfb7_h_
#define NVCFB7_VIDEO_ENCODER (0x0000CFB7)
#endif /* _clcfb7_h_ */

30
src/common/sdk/nvidia/inc/class/clcfd1.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcfd1_h_
#define _clcfd1_h_
#define NVCFD1_VIDEO_NVJPG (0x0000CFD1)
#endif /* _clcfd1_h_ */

30
src/common/sdk/nvidia/inc/class/clcffa.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clcffa_h_
#define _clcffa_h_
#define NVCFFA_VIDEO_OFA (0x0000CFFAU)
#endif /* _clcffa_h_ */

18
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -898,11 +898,11 @@ typedef struct NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS {
NvV32 timeout;
} NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS;
#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP (0x00000001U)
#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG (0x00000002U)
#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP (0x00000001U)
#define NV0000_CTRL_GPU_IMAGE_TYPE_GSP_LOG (0x00000002U)
#define NV0000_CTRL_GPU_IMAGE_TYPE_BINDATA_IMAGE (0x00000003U)
/*
* NV0000_CTRL_CMD_PUSH_GSP_UCODE
* NV0000_CTRL_CMD_PUSH_UCODE_IMAGE
*
* This command is used to push the GSP ucode into RM.
* This function is used only on VMware
@@ -915,15 +915,15 @@ typedef struct NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS {
* setup other than VMware host
*
*/
#define NV0000_CTRL_CMD_PUSH_GSP_UCODE (0x285) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_PUSH_UCODE_IMAGE (0x285) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS_MESSAGE_ID (0x85U)
#define NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS_MESSAGE_ID (0x85U)
typedef struct NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS {
typedef struct NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS {
NvU8 image;
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
NV_DECLARE_ALIGNED(NvP64 pData, 8);
} NV0000_CTRL_GPU_PUSH_GSP_UCODE_PARAMS;
} NV0000_CTRL_GPU_PUSH_UCODE_IMAGE_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_SET_NVLINK_BW_MODE

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h
View File

@@ -256,7 +256,7 @@ typedef struct NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS {
#define NV0000_CTRL_NVD_SIGNATURE_SIZE (4)
/* Maximum number of buffers */
#define NV0000_CTRL_NVD_MAX_BUFFERS (256)
#define NV0000_CTRL_NVD_MAX_BUFFERS (3840)
#define NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID (0x4U)

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
View File

@@ -2279,6 +2279,8 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
NvU32 cpuTdpmw;
} NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
typedef NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS NV0000_CTRL_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS;
/* Define the filter types */
#define CONTROLLER_FILTER_TYPE_EMWA 0U
#define CONTROLLER_FILTER_TYPE_MOVING_MAX 1U

37
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
View File

@@ -67,6 +67,12 @@
* vgpuId [OUT]
* This parameter returns the vgpu id allocated by RM for the device
*
* gpuInstanceId [OUT]
* This parameter returns the swizzId allocated by RM for the device.
*
* placementId [OUT]
* This parameter returns the placementId allocated by RM for the device.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_EVENT
@@ -85,6 +91,8 @@ typedef struct NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS {
NvU32 gpuPciBdf;
NvU32 vgpuTypeId;
NvU16 vgpuId;
NvU32 gpuInstanceId;
NvU32 placementId;
} NV0000_CTRL_VGPU_CREATE_DEVICE_PARAMS;
/*
@@ -184,4 +192,33 @@ typedef struct NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS {
NvU32 gpuId;
} NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_UPDATE_SYSFS_NODE
*
* This command will get/set the information of following sysfs node:
* gpuInstanceId
* placementId
*
* vgpuName [IN]
* This parameter provides the MDEV UUID or VF BDF depending on whether MDEV
* or vfio-pci-core framework is used.
*
* mode [IN]
* This parameter provides info about the type of operation this cmd will perform.
*
* sysfs_val [IN/OUT]
* This parameter will store the info of placementID/gpuInstanceId.
*
*/
#define NV0000_CTRL_CMD_GPU_UPDATE_SYSFS_NODE (0x206U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS {
NvU8 vgpuName[VM_UUID_SIZE];
NvU32 mode;
NvU32 sysfs_val;
} NV0000_CTRL_GPU_UPDATE_SYSFS_NODE_PARAMS;
/* _ctrl0000vgpu_h_ */

10
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -195,6 +195,16 @@ typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS {
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_10_0GBPS 0:0
#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_10_0GBPS_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_10_0GBPS_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_13_5GBPS 1:1
#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_13_5GBPS_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_13_5GBPS_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_20_0GBPS 2:2
#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_20_0GBPS_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS2_DP_UHBR_SUPPORTED_20_0GBPS_TRUE (0x00000001U)
/*

870
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -190,73 +190,7 @@ typedef struct NV0073_CTRL_DP_AUXCH_CTRL_PARAMS {
//have invalid argument
#define NV0073_CTRL_DP_AUXCH_REPLYTYPE_INVALID_ARGUMENT (0xffffffffU)
/*
* NV0073_CTRL_CMD_DP_AUXCH_SET_SEMA
*
* This command can be used to set the semaphore in order to gain control of
* the aux channel. This control is only used in HW verification.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the display for which the dfp
* caps should be returned. The display ID must a dfp display
* as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
* If more than one displayId bit is set or the displayId is not a dfp,
* this call will return NV_ERR_INVALID_ARGUMENT.
* owner
* This parameter is an input to this command.
* Here are the current defined fields:
* NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RM
* Write the aux channel semaphore for resource manager to own the
* the aux channel.
* NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_VBIOS
* Write the aux channel semaphore for vbios/efi to own the
* the aux channel. This value is used only for HW verification
* and should not be used in normal driver operation.
* NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_PMU
* Write the aux channel semaphore for pmu to own the
* the aux channel. This value is used only by pmu
* and should not be used in normal driver operation.
* NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_DPU
* Write the aux channel semaphore for dpu to own the
* the aux channel and should not be used in normal
* driver operation.
* NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_SEC2
* Write the aux channel semaphore for sec2 to own the
* the aux channel and should not be used in normal
* driver operation.
* NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RELEASE
* Write the aux channel semaphore for hardware to own the
* the aux channel. This value is used only for HW verification
* and should not be used in normal driver operation.
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_DP_AUXCH_SET_SEMA (0x731342U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS_MESSAGE_ID (0x42U)
typedef struct NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 owner;
} NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS;
#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER 2:0
#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RELEASE (0x00000000U)
#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_RM (0x00000001U)
#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_VBIOS (0x00000002U)
#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_PMU (0x00000003U)
#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_DPU (0x00000004U)
#define NV0073_CTRL_DP_AUXCH_SET_SEMA_OWNER_SEC2 (0x00000005U)
/*
* NV0073_CTRL_CMD_DP_CTRL
@@ -489,6 +423,9 @@ typedef struct NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS {
* If set to _ERR, the operation to Link Train repeater is failed.
* NV0073_CTRL_DP_ERR_ENABLE_FEC
* If set to _ERR, the operation to enable FEC is failed.
* NV0073_CTRL_DP_ERR_LINK_STATUS
* If set to _DISCONNECTED, link training failed and link is disconnected / unplugged.
*
* retryTimeMs
* This parameter is an output to this command. In case of
* NVOS_STATUS_ERROR_RETRY return status, this parameter returns the time
@@ -501,7 +438,7 @@ typedef struct NV0073_CTRL_DP_AUXCH_SET_SEMA_PARAMS {
* NVOS_STATUS_ERROR_RETRY
*/
#define NV0073_CTRL_CMD_DP_CTRL (0x731343U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP_CTRL (0x731343U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID (0x43U)
@@ -633,10 +570,13 @@ typedef struct NV0073_CTRL_DP_CTRL_PARAMS {
#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_2_LANE (0x00000002U)
#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_4_LANE (0x00000004U)
#define NV0073_CTRL_DP_ERR_EQ_DONE_LANE_8_LANE (0x00000008U)
#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER 30:30
#define NV0073_CTRL_DP_ERR_LINK_STATUS 29:29
#define NV0073_CTRL_DP_ERR_LINK_STATUS_CONNECTED (0x00000000U)
#define NV0073_CTRL_DP_ERR_LINK_STATUS_DISCONNECTED (0x00000001U)
#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER 30:30
#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER_NOERR (0x00000000U)
#define NV0073_CTRL_DP_ERR_INVALID_PARAMETER_ERR (0x00000001U)
#define NV0073_CTRL_DP_ERR_LINK_TRAINING 31:31
#define NV0073_CTRL_DP_ERR_LINK_TRAINING 31:31
#define NV0073_CTRL_DP_ERR_LINK_TRAINING_NOERR (0x00000000U)
#define NV0073_CTRL_DP_ERR_LINK_TRAINING_ERR (0x00000001U)
@@ -768,6 +708,8 @@ typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_GET_LANE_DATA_PARAMS;
typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_SET_LANE_DATA_PARAMS;
#define NV0073_CTRL_CSTM_BUFFER_SIZE 9U
/*
* NV0073_CTRL_DP_CSTM
*
@@ -782,7 +724,7 @@ typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_SET_LANE_DATA_PARAMS;
* field_31_0 contains bits 31:0
* field_63_32 contains bits 63:32
* field_95_64 contains bits 95:64
* field_127_95 contains bits 127:95
* field_127_96 contains bits 127:96
* field_159_128 contains bits 159:128
* field_191_160 contains bits 191:160
* field_223_192 contains bits 223:192
@@ -793,7 +735,7 @@ typedef struct NV0073_CTRL_DP_CSTM {
NvU32 field_31_0;
NvU32 field_63_32;
NvU32 field_95_64;
NvU32 field_127_95;
NvU32 field_127_96;
NvU32 field_159_128;
NvU32 field_191_160;
NvU32 field_223_192;
@@ -807,7 +749,7 @@ typedef struct NV0073_CTRL_DP_CSTM {
/*
* NV0073_CTRL_DP_TESTPATTERN
*
* This structure specifies the possible test patterns available in display port,
* This structure specifies the possible test patterns available in display port,
* and parameters for Square pattern.
*
*/
@@ -815,7 +757,6 @@ typedef struct NV0073_CTRL_DP_CSTM {
typedef struct NV0073_CTRL_DP_TESTPATTERN {
NvU32 testPattern;
} NV0073_CTRL_DP_TESTPATTERN;
#define NV0073_CTRL_DP_TESTPATTERN_DATA 4:0
#define NV0073_CTRL_DP_TESTPATTERN_DATA_NONE (0x00000000U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_D10_2 (0x00000001U)
@@ -830,6 +771,27 @@ typedef struct NV0073_CTRL_DP_TESTPATTERN {
#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING4 (0x0000000AU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT1 (0x0000000BU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_128B132B_TPS1 (0x0000000CU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_128B132B_TPS2 (0x0000000DU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_9 (0x0000000EU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_11 (0x0000000FU)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_15 (0x00000010U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_23 (0x00000011U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_31 (0x00000012U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_SQNUM (0x00000013U)
#define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM_264 (0x00000014U)
/*
* The following three flags specify the parameters for SQ Pattern tests.
* Only valid when testPattern is NV0073_CTRL_DP_TESTPATTERN_DATA_SQNUM
*/
#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_PRESHOOT 8:8
#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_PRESHOOT_DISABLED (0x00000000U)
#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_PRESHOOT_ENABLED (0x00000001U)
#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_DE_EMPHASIS 9:9
#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_DE_EMPHASIS_DISABLED (0x00000000U)
#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_DE_EMPHASIS_ENABLED (0x00000001U)
#define NV0073_CTRL_DP_TESTPATTERN_SQ_PATTERN_NUM 23:16
/*
@@ -938,9 +900,9 @@ typedef struct NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NV0073_CTRL_DP_TESTPATTERN testPattern;
NV0073_CTRL_DP_CSTM cstm;
} NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS;
#define NV0073_CTRL_CMD_DP_GET_TESTPATTERN (0x731348U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS_MESSAGE_ID" */
/*
@@ -1399,6 +1361,10 @@ typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS {
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_4_32GBPS (0x000001B0U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_6_75GBPS (0x000002A3U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_10_0GBPS (0x000003E8U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_13_5GBPS (0x00000546U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_20_0GBPS (0x000007D0U)
/*
* NV0073_CTRL_CMD_DP_GET_EDP_DATA
@@ -1716,6 +1682,8 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
* Specified the DP versions supported by the GPU
* UHBRSupportedByGpu
* Bitmask to specify the UHBR link rates supported by the GPU.
* minPClkForCompressed
* Pixel clock below which we should prefer non-DSC mode.
* bIsMultistreamSupported
* Returns NV_TRUE if MST is supported by the GPU else NV_FALSE
* bIsSCEnabled
@@ -1757,6 +1725,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
NvU32 maxLinkRate;
NvU32 dpVersionsSupported;
NvU32 UHBRSupportedByGpu;
NvU32 minPClkForCompressed;
NvBool bIsMultistreamSupported;
NvBool bIsSCEnabled;
NvBool bHasIncreasedWatermarkLimits;
@@ -1777,6 +1746,10 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_NO (0x00000000U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP2_0 2:2
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP2_0_NO (0x00000000U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP2_0_YES (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U)
@@ -1785,6 +1758,16 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR10_0 0:0
#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR10_0_NO (0x00000000U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR10_0_YES (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR13_5 1:1
#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR13_5_NO (0x00000000U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR13_5_YES (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR20_0 2:2
#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR20_0_NO (0x00000000U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_UHBR_SUPPORTED_UHBR20_0_YES (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U)
@@ -2717,6 +2700,417 @@ typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS {
NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues;
} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS;
/*
* NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL
*
* This command is used to trigger link training on DP2.x device with 128b132b channel encoding.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
*
* displayId
* This parameter specifies the ID of the display for which the dfp
* caps should be returned. The display ID must a dfp display.
* If more than one displayId bit is set or the displayId is not a dfp,
* this call will return NV_ERR_INVALID_ARGUMENT.
*
* cmd
* This parameter is an input to this command.
* Here are the current defined fields:
* 1.Ask RM to enter specific stage
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET
* _PRE_LT : Request RM to get ready for 128b/132b Link Training.
* _CHNL_EQ : Request RM to start Channel Equalization phase.
* _CDS : Request RM to start Clock Data Switch phase.
* _POST_LT : Request RM to clean up/sync up once 128b/132b LT is done.
*
* _SET_* only valid if _SETTING_TRUE
*
* 2.Ask RM to check the completion of specific stage
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_DONE
* _CHNL_EQ_INTERLANE_ALIGN
* _CDS
* _POLL_* only valid if _POLLING_TRUE
*
* _SETTING_TRUE and _POLLING_TRUE are mutual exclusive.
* RM will return NV_ERR_INVALID_ARGUMENT if both bit are set.
*
* 3.Downspread configuration
* NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD
* Specifies whether RM should be forced to enable or disable the DP
* Downspread setting. This can be used along with the Fake link
* training option so that we can configure the GPU to enable/disable
* spread when a real display is not connected.
*
* NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_NO (default behavior)
* RM will enable Downspread when the display supports it.
* NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_YES
* RM will enable/disable Downspread according to _SET_DOWNSPREAD field.
*
* NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD
* Specifies if RM should enable or disable downspread.
* Only valid when _FORCED_DOWNSPREAD is set to _YES
*
* NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_ENABLE
* RM will enable Downspread even if the display does not support it.
* NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_DISABLE
* RM will not enable Downspread even if the display does support it.
*
* 4.NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING
* This field specifies if fake link training is to be done. This will
* program enough of the hardware to avoid any hardware hangs and
* depending upon option chosen by the client, OR will be enabled for
* transmisssion.
*
* NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_NO
* No Fake LT will be performed
* NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION
* SOR will be not powered up during Fake LT
* NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON
* SOR will be powered up during Fake LT
*
* 5.NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG
*
* 6.NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING
* Specifies whether RM should skip HW training of the link.
* If this is the case then RM only updates its SW state without actually
* touching any HW registers. Clients should use this ONLY if it has determined -
* a. link is trained and not lost
* b. desired link config is same as current trained link config
* c. link is not in D3 (should be in D0)
*
* NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_NO
* RM doesn't skip HW LT as the current Link Config is not the same as the
* requested Link Config.
* NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_YES
* RM skips HW LT and only updates its SW state as client has determined that
* the current state of the link and the requested Link Config is the same.
*
* data
* This parameter is an input and output to this command.
* Here are the current defined fields:
* NV0073_CTRL_DP2X_DATA_LANE_COUNT
* Valid values: 0, 1, 2, 4
* NV0073_CTRL_DP2X_DATA_LINK_BW
* Valid values: all standard link rates defined in DP2.x and ILRs defined in eDP spec.
*
* NV0073_CTRL_DP2X_DATA_RESET_LINK_REASON
* Only valid when NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING and
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_PRE_LT are both set.
* Valid value:
* NV0073_CTRL_DP2X_DATA_RESET_REASON_START_LT:
* RM clears 0x102.
* NV0073_CTRL_DP2X_DATA_RESET_REASON_FALLBACK:
* RM clears 0x102 then clears 0x103-0x106.
* NV0073_CTRL_DP2X_DATA_RESET_REASON_CHANNEL_CODING:
* RM puts DPRX to D3 then clears 0x103-0x106.
*
* pollingInfo
* This parameter is an output to this command.
* Here are the current defined fields:
*
* NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL
* For Channel equalization, the polling interval is defined in DPCD 0x2216.
* RM report to DPLib when _SET_STAGE is set to _CHNL_EQ.
* Polling interval for Channel Equalization is defined as
* (128b132b_DP_TRAINING_AUX_RD_INTERVAL value + 1) * 128b132b_DP_TRAINING_AUX_RD_INTERVAL_UNIT.
* The maximum is 256 ms.
* (For CDS stage, the polling interval is fixed at 3ms.)
*
* NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL_UNIT
* Unit mapping for polling interval is
* 0 = 2ms
* 1 = 1ms
*
* NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL_UNIT_2MS
* NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL_UNIT_1MS
*
* NV0073_CTRL_DP2X_POLLING_INFO_RESULT
* _DONE: if the specified stage is done.
* _PENDING: if the specified stage is still pending.
*
* err
* This parameter provides info regarding the outcome of this calling control call.
* If zero, no errors were found.
* Otherwise, this parameter will specify the error detected.
* The valid parameter is broken down as follows:
* NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_DONE
* If set to _ERR, link training failed at channel equalization phase.
* NV0073_CTRL_DP2X_ERR_CDS_DONE
* If set to _ERR, link training failed at CDS phase.
* NV0073_CTRL_DP2X_ERR_TIMEOUT
* If set to _ERR, link training failed because of timeout.
* NV0073_CTRL_DP2X_ERR_LT_FAILED
* If set to _ERR, link training failed.
* NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER
* If set to _ERR, link configuration or displayID is invalid.
* NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT
* If set to _ERR, link training failed when setting lane count.
* NV0073_CTRL_DP2X_ERR_SET_LINK_BW
* If set to _ERR, link training failed when setting link rate.
* NV0073_CTRL_DP2X_ERR_ENABLE_FEC
* If set to _ERR, link training failed when enabling FEC.
* NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR
* If set to _ERR, link training failed when setting LTTPR.
* NV0073_CTRL_DP2X_ERR_PRE_LT
* If set to _ERR, link training failed before link training start.
* NV0073_CTRL_DP2X_ERR_LINK_STATUS
* If set to _DISCONNECTED, link training failed and link is disconnected / unplugged.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NVOS_STATUS_ERROR
*/
#define NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL (0x731383U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS_MESSAGE_ID (0x83U)
typedef struct NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 cmd;
NvU32 data;
NvU32 pollingInfo;
NvU32 err;
} NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS;
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING 0:0
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING_FALSE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING_TRUE (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET 3:1
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_RESET_LINK (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_PRE_LT (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CHNL_EQ (0x00000002U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CDS (0x00000003U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_POST_LT (0x00000004U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING 8:8
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING_FALSE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING_TRUE (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL 10:9
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_RESET_LINK (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_DONE (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_INTERLANE_ALIGN (0x00000002U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CDS (0x00000003U)
// Flags for link training.
#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD 16:16
#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_NO (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_YES (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD 17:17
#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_DISABLE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_ENABLE (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING 18:18
#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING 20:19
#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_NO (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U)
#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG 21:21
#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG_FALSE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG_TRUE (0x00000001U)
// Basic Data for Link training: Lane count and bandwidth.
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT 3:0
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_0 (0x00000000U)
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_1 (0x00000001U)
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_2 (0x00000002U)
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_4 (0x00000004U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW 7:4
#define NV0073_CTRL_DP2X_DATA_LINK_BW_1_62GBPS (0x00000001U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_16GBPS (0x00000002U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_43GBPS (0x00000003U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_70GBPS (0x00000004U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_3_24GBPS (0x00000005U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_4_32GBPS (0x00000006U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_5_40GBPS (0x00000007U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_6_75GBPS (0x00000008U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_8_10GBPS (0x00000009U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR10_0 (0x0000000AU)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR13_5 (0x0000000BU)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR20_0 (0x0000000CU)
// Flag for SET_RESET_LINK
#define NV0073_CTRL_DP2X_DATA_RESET_REASON 9:8
#define NV0073_CTRL_DP2X_DATA_RESET_REASON_START_LT (0x00000000U)
#define NV0073_CTRL_DP2X_DATA_RESET_REASON_FALLBACK (0x00000001U)
#define NV0073_CTRL_DP2X_DATA_RESET_REASON_CHANNEL_CODING (0x00000002U)
#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ 0:0
#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_DONE (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_FAILED (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_CDS 1:1
#define NV0073_CTRL_DP2X_ERR_CDS_DONE (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_CDS_FAILED (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_TIMEOUT 2:2
#define NV0073_CTRL_DP2X_ERR_TIMEOUT_NO (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_TIMEOUT_YES (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_LT_FAILED 3:3
#define NV0073_CTRL_DP2X_ERR_LT_FAILED_NO (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_LT_FAILED_YES (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER 4:4
#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT 5:5
#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW 6:6
#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC 7:7
#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR 8:8
#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_PRE_LT 9:9
#define NV0073_CTRL_DP2X_ERR_PRE_LT_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_PRE_LT_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_POST_LT 10:10
#define NV0073_CTRL_DP2X_ERR_POST_LT_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_POST_LT_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_RESET_LINK 11:11
#define NV0073_CTRL_DP2X_ERR_RESET_LINK_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_RESET_LINK_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_LINK_STATUS 12:12
#define NV0073_CTRL_DP2X_ERR_LINK_STATUS_CONNECTED (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_LINK_STATUS_DISCONNECTED (0x00000001U)
#define NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL 6:0
#define NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL_UNIT 7:7
#define NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL_UNIT_2MS (0x00000000U)
#define NV0073_CTRL_DP2X_POLLING_INFO_TRAINING_AUX_RD_INTERVAL_UNIT_1MS (0x00000001U)
#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT 31:31
#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT_PENDING (0x00000001U)
#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT_DONE (0x00000000U)
/*
* NV0073_CTRL_DP2X_LANE_DATA_PARAMS
*
* This structure provides DP2.x lane characteristics.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the display for which the dfp
* caps should be returned. The display ID must a dfp display.
* If more than one displayId bit is set or the displayId is not a dfp,
* this call will return NV_ERR_INVALID_ARGUMENT.
* numLanes
* Indicates number of lanes for which the data is valid.
* For SET it's an input. For GET it's an output.
*
* data
* This parameter can be an input or output based on the usage.
* For SET it's an input. For GET it's an output.
*
* Here are the current defined fields:
* NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL
* Possible Values:
* NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_0
* ...
* NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_15
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_DP2X_LANE_DATA_BUFFER_SIZE (0x20U) /* finn: Evaluated from "(4 * NV0073_CTRL_MAX_LANES)" */
typedef struct NV0073_CTRL_DP2X_LANE_DATA_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 numLanes;
NvU32 data[NV0073_CTRL_MAX_LANES];
} NV0073_CTRL_DP2X_LANE_DATA_PARAMS;
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL 3:0
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_0 (0x00000000U)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_1 (0x00000001U)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_2 (0x00000002U)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_3 (0x00000003U)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_4 (0x00000004U)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_5 (0x00000005U)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_6 (0x00000006U)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_7 (0x00000007U)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_8 (0x00000008U)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_9 (0x00000009U)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_10 (0x0000000AU)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_11 (0x0000000BU)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_12 (0x0000000CU)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_13 (0x0000000DU)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_14 (0x0000000EU)
#define NV0073_CTRL_DP2X_LANE_DATA_TXFFE_LEVEL_15 (0x0000000FU)
/*
* NV0073_CTRL_CMD_GET_DP2X_LANE_DATA
*
* This command is used to get the current TxFFE pre-defined level values for
* the current actively trained number of lanes.
*
* The command takes a NV0073_CTRL_DP2X_LANE_DATA_PARAMS structure as the
* argument with the appropriate subDeviceInstance and displayId filled.
* The arguments of this structure and the format of TxFFE Levels are described above.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*
* NOTE: This control call is only for testing purposes and should not be used
* in normal DP operations. TxFFE level for each lane will be set during
* Link training in normal DP operations
*
*/
#define NV0073_CTRL_CMD_DP2X_GET_LANE_DATA (0x731384U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP2X_GET_LANE_DATA_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP2X_GET_LANE_DATA_PARAMS_MESSAGE_ID (0x84U)
typedef NV0073_CTRL_DP2X_LANE_DATA_PARAMS NV0073_CTRL_DP2X_GET_LANE_DATA_PARAMS;
/*
* NV0073_CTRL_CMD_SET_DP2X_LANE_DATA
*
* This command is used to set the TxFFE pre-defined level for the specified number of lanes.
*
* The command takes a NV0073_CTRL_DP2X_LANE_DATA_PARAMS structure as the
* argument with the appropriate subDeviceInstance, displayId, number of
* lanes, TxFFE levels for each lanes filled in.
* The arguments of this structure and the format of TxFFE Levels are described above.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*
* NOTE: This control call is only for testing purposes and should not be used
* in normal DP operations. TxFFE level for each lane will be set during
* Link training in normal DP operations
*
*/
#define NV0073_CTRL_CMD_DP2X_SET_LANE_DATA (0x731385U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP2X_SET_LANE_DATA_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP2X_SET_LANE_DATA_PARAMS_MESSAGE_ID (0x85U)
typedef NV0073_CTRL_DP2X_LANE_DATA_PARAMS NV0073_CTRL_DP2X_SET_LANE_DATA_PARAMS;
/*
@@ -2779,4 +3173,332 @@ typedef struct NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL_PARAMS {
NvBool bVblControlCapable;
NvBool bVblStatus;
} NV0073_CTRL_CMD_DP_AUXCH_VBL_CTRL_PARAMS;
/*
* NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY
*
* This structure specifies the Pre-emphasis/Drive Current/preshoot/TxPu
* information for a DP device. These are the the current values that RM is
* using to map the levels for Pre-emphasis and Drive Current for Link Training.
* preEmphasis
* This field specifies the preemphasis values.
* driveCurrent
* This field specifies the driveCurrent values.
* preshoot
* This field specifies the preshoot values.
* TxPu
* This field specifies the pull-up current source drive values.
*/
#define NV0073_CTRL_DP2X_MAX_TXFFE_LEVELS 16
typedef struct NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY {
NvU32 preEmphasis;
NvU32 driveCurrent;
NvU32 preShoot;
NvU32 txPu;
} NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY;
/*
* NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA
*
* This command is used to override the Pre-emphasis/Drive Current/preshoot/TxPu
* data table in RM. This data is dependent on the target link rate.
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the digital display for which the
* data should be returned. The display ID must a digital display.
* If more than one displayId bit is set or the displayId is not a DP,
* this call will return NV_ERR_INVALID_ARGUMENT.
* linkRate
* The target link rate that the lane drive parameters will be used with,
* using 10M convention. Refer to NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW
* constants.
* This control call only supports DP1.x link rates. For DP2.X UHBR link rates,
* use NV0073_CTRL_DP2X_SET_LEVEL_INFO_TABLE_DATA
* dpData
* This parameter is of type NV0073_CTRL_DP_LEVEL_INFO_TABLE_DATA
* and specifies the Pre-emphasis/Drive Current/Preshoot/TxPu information
* for a DP device.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID (0x87U)
typedef struct NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 padlinkIndex;
NvU32 linkRate;
NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY dpData[NV0073_CTRL_MAX_DRIVECURRENT_LEVELS][NV0073_CTRL_MAX_PREEMPHASIS_LEVELS];
} NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA_PARAMS;
#define NV0073_CTRL_CMD_DP_SET_LEVEL_INFO_TABLE_DATA (0x731387U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_DP_GET_LEVEL_INFO_TABLE_DATA
*
* This command is used to fetch the Pre-emphasis/Drive Current/preshoot/TxPu
* data table in RM. This data is dependent on the target link rate.
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the digital display for which the
* data should be returned. The display ID must a digital display.
* If more than one displayId bit is set or the displayId is not a DP,
* this call will return NV_ERR_INVALID_ARGUMENT.
* linkRate
* The target link rate that the lane drive parameters will be used with,
* using 10M convention. Refer to NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW
* constants.
* This control call only supports DP1.x link rates. For DP2.X UHBR link rates,
* use NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA
* dpData
* This parameter is of type NV0073_CTRL_DP_LEVEL_INFO_TABLE_DATA
* and specifies the Pre-emphasis/Drive Current/Preshoot/TxPu information
* for a DP device.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV0073_CTRL_DP_GET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID (0x88U)
typedef struct NV0073_CTRL_DP_GET_LEVEL_INFO_TABLE_DATA_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 padlinkIndex;
NvU32 linkRate;
NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY dpData[NV0073_CTRL_MAX_DRIVECURRENT_LEVELS][NV0073_CTRL_MAX_PREEMPHASIS_LEVELS];
} NV0073_CTRL_DP_GET_LEVEL_INFO_TABLE_DATA_PARAMS;
#define NV0073_CTRL_CMD_DP_GET_LEVEL_INFO_TABLE_DATA (0x731388U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_DP2X_SET_LEVEL_INFO_TABLE_DATA
*
* This command is used to override the Pre-emphasis/Drive Current/preshoot/TxPu
* data table in RM. This data is dependent on the target link rate.
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the digital display for which the
* data should be returned. The display ID must a digital display.
* If more than one displayId bit is set or the displayId is not a DP,
* this call will return NV_ERR_INVALID_ARGUMENT.
* linkRate
* The target link rate that the lane drive parameters will be used with,
* using 10M convention. Refer to NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW
* constants.
* This control call only supports UHBR link rates. For DP1.x legacy link rates,
* use NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA
* dpData
* This parameter is of type NV0073_CTRL_DP_LEVEL_INFO_TABLE_DATA
* and specifies the Pre-emphasis/Drive Current/Preshoot/TxPu information
* for a DP device.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV0073_CTRL_DP2X_SET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV0073_CTRL_DP2X_SET_LEVEL_INFO_TABLE_DATA_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 padlinkIndex;
NvU32 linkRate;
NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY dpData[NV0073_CTRL_DP2X_MAX_TXFFE_LEVELS];
} NV0073_CTRL_DP2X_SET_LEVEL_INFO_TABLE_DATA_PARAMS;
#define NV0073_CTRL_CMD_DP2X_SET_LEVEL_INFO_TABLE_DATA (0x731389U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP2X_SET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA
*
* This command is used to fetch the Pre-emphasis/Drive Current/preshoot/TxPu
* data table in RM. This data is dependent on the target link rate.
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the digital display for which the
* data should be returned. The display ID must a digital display.
* If more than one displayId bit is set or the displayId is not a DP,
* this call will return NV_ERR_INVALID_ARGUMENT.
* linkRate
* The target link rate that the lane drive parameters will be used with,
* using 10M convention. Refer to NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW
* constants.
* This control call only supports UHBR link rates. For DP1.x legacy link rates,
* use NV0073_CTRL_DP_SET_LEVEL_INFO_TABLE_DATA
* dpData
* This parameter is of type NV0073_CTRL_DP_LEVEL_INFO_TABLE_DATA
* and specifies the Pre-emphasis/Drive Current/Preshoot/TxPu information
* for a DP device.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID (0x8AU)
typedef struct NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 padlinkIndex;
NvU32 linkRate;
NV0073_CTRL_DP_LEVEL_INFO_TABLE_ENTRY dpData[NV0073_CTRL_DP2X_MAX_TXFFE_LEVELS];
} NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS;
#define NV0073_CTRL_CMD_DP2X_GET_LEVEL_INFO_TABLE_DATA (0x73138aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_CMD_CALCULATE_DP_IMP
*
* This command is used to query if a certain mode is supported by the DP IMP
* calculation. The command is required for NVD5 and later GPUs.
*
* subDeviceInstance [in]
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId [in]
* This parameter specifies the ID of the DP display which owns
* the Main Link to be adjusted. The display ID must a DP display
* as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
* If more than one displayId bit is set or the displayId is not a DP,
* this call will return NV_ERR_INVALID_ARGUMENT.
* linkConfig [in]
* This parameter specifies the link configuration used to validate the mode.
* linkRate10M:
* The link rate that will be used to validate the IMP. Using 10M convention.
* Refer to NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW constants.
* laneCount:
* The lane count that will be used to validate the IMP.
* bEnhancedFraming:
* Specify if enhanced framing is enabled.
* bDp2xChannelCoding:
* Specify if it's using 8b/10b or 128b/132b channel coding.
* bMultiStreamTopology:
* Specify if it's on Multiple stream topology (the device direct connected is a branch).
* bFECEnabled:
* Specify if FEC is enabled.
* modesetInfo [in]
* This parameter specifies the target display mode to be validated.
* rasterWidth:
* The total width of the mode.
* rasterHeight:
* The total height of the mode.
* surfaceWidth:
* The active width of the mode.
* surfaceHeight:
* The active height of the mode.
* rasterBlankStartX / rasterBlankEndX:
* The pixel location of horizontal blank starts and ends.
* depth:
* Color depth represents the number of bits used to indicate the color of a single pixel.
* The value will be different when DSC is enabled.
* twoChannelAudioHz/eightChannelAudioHz:
* The audio sample rate for different channels used.
* pixelFrequencyKHz:
* The pixel clock used by the mode.
* colorFormat:
* RGB/YCbCr444/YCbCr422/YCbCr420.
* bDSCEnabled:
* Specify if DSC is enabled.
* watermark [out]
* This parameter reflects the results of the calculation/verification.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP (0x73138bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID" */
typedef struct NV0073_CTRL_DP_IMP_LINK_CONFIGURATION {
NvU32 linkRate10M;
NvU32 laneCount;
NvBool bEnhancedFraming;
NvBool bDp2xChannelCoding;
NvBool bMultiStreamTopology;
NvBool bFECEnabled;
} NV0073_CTRL_DP_IMP_LINK_CONFIGURATION;
typedef struct NV0073_CTRL_DP_IMP_DSC_PARAMETERS {
NvU32 sliceCount;
NvU32 sliceWidth;
NvU32 sliceHeight;
NvU32 dscVersionMajor;
NvU32 dscVersionMinor;
} NV0073_CTRL_DP_IMP_DSC_PARAMETERS;
typedef struct NV0073_CTRL_DP_IMP_MODESET_DATA {
NvU32 rasterWidth;
NvU32 rasterHeight;
NvU32 surfaceWidth;
NvU32 surfaceHeight;
NvU32 rasterBlankStartX;
NvU32 rasterBlankEndX;
NvU32 depth;
NvU32 twoChannelAudioHz;
NvU32 eightChannelAudioHz;
NvU32 pixelFrequencyKHz;
NvU32 bitsPerComponent;
NvU32 colorFormat;
NvBool bDSCEnabled;
} NV0073_CTRL_DP_IMP_MODESET_DATA;
typedef struct NV0073_CTRL_DP_IMP_WATERMARK {
NvU32 waterMark;
NvU32 tuSize;
NvU32 minHBlank;
NvU32 hBlankSym;
NvU32 vBlankSym;
NvU32 effectiveBpp;
NvBool bIsModePossible;
} NV0073_CTRL_DP_IMP_WATERMARK;
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID (0x8BU)
typedef struct NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 headIndex;
NV0073_CTRL_DP_IMP_LINK_CONFIGURATION linkConfig;
NV0073_CTRL_DP_IMP_MODESET_DATA modesetInfo;
NV0073_CTRL_DP_IMP_DSC_PARAMETERS dscInfo;
NV0073_CTRL_DP_IMP_WATERMARK watermark;
} NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS;
/* _ctrl0073dp_h_ */

6
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
View File

@@ -56,12 +56,6 @@ typedef NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_
typedef NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_ENABLE (0x730405U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_ENABLE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_ENABLE_PARAMS_MESSAGE_ID (0x5U)
typedef NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_ENABLE_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR (0x730406U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID (0x6U)

241
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -30,7 +30,6 @@
// Source file: ctrl/ctrl0073/ctrl0073system.finn
//
#include "nvlimits.h"
#include "ctrl/ctrl0073/ctrl0073base.h"
/* NV04_DISPLAY_COMMON system-level control commands and parameters */
@@ -1841,165 +1840,6 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS {
NvHandle hMemory;
} NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL
*
* The VBlank Semaphore Control API ("VBlank Sem Control") allows clients to
* register for a semaphore release to be performed on the specified memory.
*
* One or more clients may register a memory allocation + offset by describing a
* video memory object with _PARAMS::hMemory and an offset within that memory
* object (_PARAMS::memoryOffset). Until the hMemory + memoryOffset combination
* is disabled, during each vblank on the specified heads, RM will interpret the
* specified memory location as an
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA data structure. Each enabled
* head will inspect the corresponding
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD at
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA::head[head].
*
* _PARAMS::memoryOffset must be a multiple of 8, so that GPU semaphore releases
* and GSP can write to 8-byte fields within
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD with natural alignment.
*
* During vblank, the _CONTROL_DATA_ONE_HEAD::requestCounter field will be read,
* and the following pseudocode will be performed:
*
* swapInterval = DRF_VAL(data->flags)
* useMinimumGpuTime = DRV_VAL(data->flags)
*
* if (data->requestCounter == prevRequestCounter)
* return
*
* if (currentVblankCount < (prevVBlankCount + swapInterval))
* return
*
* if (useMinimumGpuTime && (data->minimumGpuTime < currentGpuTime))
* return
*
* data->vblankCount = currentVblankCount
* data->releaseGpuTime = currentGpuTime
* data->semaphore = data->requestCounter
*
* prevRequestCounter = data->requestCounter
* previousVblankCount = currentVblankCount
*
* I.e., if the client-described conditions are met, the RM will write
* _CONTROL_DATA_ONE_HEAD::semaphore to the client-requested 'requestCounter'
* along with several informational fields (vblankCount, releaseGpuTime).
*
* The intent is for clients to use semaphore releases to write:
*
* _CONTROL_DATA_ONE_HEAD::minimumGpuTime (if desired)
* _CONTROL_DATA_ONE_HEAD::swapInterval
* _CONTROL_DATA_ONE_HEAD::requestCounter
*
* and then perform a semaphore acquire on _CONTROL_DATA_ONE_HEAD::semaphore >=
* requestCounter (using the ACQ_GEQ semaphore operation). This will block any
* following methods in the client's channel (e.g., a blit) until the requested
* conditions are met. Note the ::requestCounter should be written last,
* because the change in value of ::requestCounter is what causes RM, during a
* vblank callback, to inspect the other fields.
*
* Additionally, clients should use the CPU (not semaphore releases in their
* channel) to write the field _CONTROL_DATA_ONE_HEAD::requestCounterAccel at
* the same time that they enqueue the semaphore release to write to
* _CONTROL_DATA_ONE_HEAD::requestCounter. ::requestCounterAccel will be used
* by resman to "accelerate" the vblank sem control by copying the value from
* ::requestCounterAccel to ::semaphore. This will be done when the vblank sem
* control is disabled, and when a client calls
* NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS. It is important for resman
* to have access to the value in ::requestCounterAccel, and not just
* ::requestCounter. The latter is only the last value released so far by the
* client's channel (further releases to ::requestCounter may still be inflight,
* perhaps blocked on pending semaphore acquires). The former should be the
* most recent value enqueued in the channel. This is also why it is important
* for clients to acquire with ACQ_GEQ (greater-than-or-equal-to), rather than
* just ACQUIRE.
*
* The same hMemory (with difference memoryOffsets) may be used by multiple
* VBlank Sem Controls.
*
* Lastly, the bUseHeadIndexMap field in the enable params is used to tell
* resman to honor the headIndexMap[] table in the enable params. Normally, the
* N-th bit in the enable params headMask corresponds to element N in the
* _CONTROL_DATA::head[] array. But, headIndexMap[] allows the N-th bit in
* headMask to be remapped to a different index in the head[] array. E.g.,
*
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA *pData = ...;
*
* FOR_EACH_INDEX_IN_MASK(32, head, pParams->headMask)
* {
* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD *pDataOneHead;
* NvU32 headIndex = pParams->bUseHeadIndexMap ?
* pParams->headIndexMap[head] : head;
* pDataOneHead = &pData->head[headIndex];
* ...
* }
* FOR_EACH_INDEX_IN_MASK_END;
*
* This remapping is important for nvkms' use of the RMAPI. To support
* 2head1or, nvkms may remap head indices between the headMask passed to RM and
* the array indices in _CONTROL_DATA::head[] as used by OpenGL.
*/
/* Fields within NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD::flags */
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_SWAP_INTERVAL 15:0
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_USE_MINIMUM_GPU_TIME 16:16
typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD {
NvU32 requestCounterAccel;
NvU32 requestCounter;
NvU32 flags;
NV_DECLARE_ALIGNED(NvU64 minimumGpuTime, 8);
NvU32 semaphore;
NV_DECLARE_ALIGNED(NvU64 vblankCount, 8);
NV_DECLARE_ALIGNED(NvU64 releaseGpuTime, 8);
} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD;
typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA {
NV_DECLARE_ALIGNED(NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD head[NV_MAX_HEADS], 8);
} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA;
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE (0x73014eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS_MESSAGE_ID (0x4EU)
typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS {
NvU32 subDeviceInstance;
NvU32 headMask;
NvU8 headIndexMap[NV_MAX_HEADS];
NvHandle hMemory;
NV_DECLARE_ALIGNED(NvU64 memoryOffset, 8);
NvBool bUseHeadIndexMap;
} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS;
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE (0x73014fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS_MESSAGE_ID (0x4FU)
typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS {
NvU32 subDeviceInstance;
NvHandle hMemory;
NV_DECLARE_ALIGNED(NvU64 memoryOffset, 8);
} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS;
/*
* Accelerate all VBlank Sem Controls on the specified heads.
*
* For all enabled vblank sem controls on the specified heads, immediate set
* their pending ::semaphore fields to the value in their ::requestCounterAccel
* field.
*/
#define NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS (0x730150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS_MESSAGE_ID (0x50U)
typedef struct NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS {
NvU32 subDeviceInstance;
NvU32 headMask;
} NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS;
/*
* Maps the memory allocated in Kernel RM into Physical RM using the
* memory descriptor information provided.
@@ -2037,8 +1877,8 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS {
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
* displayId
* DisplayId of the panel for which we are going to read loadv info
* head
* headId of the panel for which we are going to read loadv info
* Possible status values returned are:
* counterValue
* Counts number of frames that have been procesed or synchronized with display
@@ -2053,7 +1893,7 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS {
typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 head;
NvU32 counterValue;
} NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS;
@@ -2068,6 +1908,9 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_RISCV0CLK 0x0003
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_DISPCLK 0x0004
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_POSTRG_CLKS 0x0005
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_HUBCLK 0x0006
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_DISPCLK 0x0007
#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_POSTRG_CLKS 0x0008
// Parameter/characteristics of Display ALPM
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_INVALID 0x0000
@@ -2160,6 +2003,34 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_STATUS (0x0010)
/*!
* @brief Parameter/characteristics of hubclk, dispclk and Post-RG clock Gating
*
* Following are the Parameter/characteristics for of hubclk, dispclk and Post-RG
* Clock Gating
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_INVALID (0x0000)
/*!
* Property specifies if Clock Gating is supported
* or not. This property is applicable for hubclk, dispclk and Post-RG clk.
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_SUPPORT (0x0001)
/*!
* Property specifies if Clock Gating is enabled or not.
* This property is applicable for hubclk, dispclk and Post-RG clk.
* (This property allows Get and Set operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_ENABLED (0x0002)
/*!
* Property specifies the time(us) for which the specified clock was gated.
* This property is applicable for hubclk, dispclk and Post-RG clk
* (This property allows Get operation)
*/
#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_GATE_TIME_US (0x0003)
/*!
* @brief Structure to identify display low power feature
*
@@ -2234,6 +2105,16 @@ typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER {
* Commands returns SUCCESS only when it successfully retrieves value all
* parameter in the list.
*
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
*
* displayId
* DisplayId of the panel for which we are going to low power features data
* Possible status values returned are:
*
* listSize
* Number of valid entries in list.
*
@@ -2252,6 +2133,7 @@ typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER {
typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 listSize;
NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER list[NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE];
} NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS;
@@ -2285,6 +2167,7 @@ typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS {
typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 listSize;
NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER list[NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE];
} NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS;
@@ -2310,9 +2193,9 @@ typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR (0x730158U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR (0x730159U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS_MESSAGE_ID (0x58U)
#define NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS_MESSAGE_ID (0x59U)
typedef struct NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS {
NvU32 subDeviceInstance;
@@ -2320,6 +2203,34 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS {
NvBool bEnableDrr;
} NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO
*
* Fetches the Crash Lock Counter information from corresponding register.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
* head
* HeadId of the panel for which we are going to read crash lock counter info
* Possible status values returned are:
* counterValueV
* Counts number of vertical crashlock events that have occured with this display
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO (0x730160U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS_MESSAGE_ID (0x60U)
typedef struct NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS {
NvU32 subDeviceInstance;
NvU32 head;
NvU32 counterValueV;
} NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS;
/* _ctrl0073system_h_ */

116
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
View File

@@ -99,70 +99,74 @@ typedef struct NV0080_CTRL_GR_GET_CAPS_PARAMS {
typedef NVXXXX_CTRL_XXX_INFO NV0080_CTRL_GR_INFO;
/* valid graphics info index values */
#define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS (0x00000000)
#define NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 (0x00000001)
#define NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK (0x00000002)
#define NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT (0x00000003)
#define NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT (0x00000004)
#define NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE (0x00000005)
#define NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT (0x00000006)
#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT (0x00000007)
#define NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR (0x00000008)
#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT (0x00000009)
#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT (0x0000000A)
#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT (0x0000000B)
#define NV0080_CTRL_GR_INFO_INDEX_SM_VERSION (0x0000000C)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM (0x0000000D)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP (0x0000000E)
#define NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES (0x0000000F)
#define NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES (0x00000010)
#define NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY (0x00000011)
#define NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY (0x00000012)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM (0x00000013)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS (0x00000014)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS (0x00000015)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS (0x00000016)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC (0x00000017)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS (0x00000018)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS (0x00000019)
#define NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED (0x0000001A)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS (0x0000001B)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC (0x0000001C)
#define NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT (0x0000001D)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES (0x0000001E)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS (0x0000001F)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC (0x00000020)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS (0x00000021)
#define NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT (0x00000022)
#define NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT (0x00000023)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS (0x00000024)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS (0x00000025)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES (0x00000026)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC (0x00000027)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP (0x00000028)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC (0x00000029)
#define NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC (0x0000002A)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP (0x0000002B)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT (0x0000002C)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT (0x0000002D)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT (0x0000002E)
#define NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS (0x00000000)
#define NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 (0x00000001)
#define NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK (0x00000002)
#define NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT (0x00000003)
#define NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT (0x00000004)
#define NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE (0x00000005)
#define NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT (0x00000006)
#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT (0x00000007)
#define NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR (0x00000008)
#define NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT (0x00000009)
#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT (0x0000000A)
#define NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT (0x0000000B)
#define NV0080_CTRL_GR_INFO_INDEX_SM_VERSION (0x0000000C)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM (0x0000000D)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP (0x0000000E)
#define NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES (0x0000000F)
#define NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES (0x00000010)
#define NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY (0x00000011)
#define NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY (0x00000012)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM (0x00000013)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS (0x00000014)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS (0x00000015)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS (0x00000016)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC (0x00000017)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS (0x00000018)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS (0x00000019)
#define NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED (0x0000001A)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS (0x0000001B)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC (0x0000001C)
#define NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT (0x0000001D)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES (0x0000001E)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS (0x0000001F)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC (0x00000020)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS (0x00000021)
#define NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT (0x00000022)
#define NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT (0x00000023)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS (0x00000024)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS (0x00000025)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES (0x00000026)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC (0x00000027)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP (0x00000028)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC (0x00000029)
#define NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC (0x0000002A)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP (0x0000002B)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT (0x0000002C)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT (0x0000002D)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT (0x0000002E)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES (0x00000033)
#define NV0080_CTRL_GR_INFO_INDEX_DUMMY (0x00000033)
#define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000034)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES (0x00000035)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS (0x00000036)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG (0x00000037)
#define NV0080_CTRL_GR_INFO_INDEX_DUMMY (0x00000033)
#define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000034)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES (0x00000035)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS (0x00000036)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG (0x00000037)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET (0x00000038)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET (0x00000039)
/* When adding a new INDEX, please update MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
* reflects that.
*/
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000037)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x38) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000039)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x3a) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
/*
* NV0080_CTRL_CMD_GR_GET_INFO
@@ -180,7 +184,7 @@ typedef NVXXXX_CTRL_XXX_INFO NV0080_CTRL_GR_INFO;
* This buffer must be at least as big as grInfoListSize multiplied
* by the size of the NV0080_CTRL_GR_INFO structure.
*/
#define NV0080_CTRL_CMD_GR_GET_INFO (0x801104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_CMD_GR_GET_INFO (0x801104) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GR_INTERFACE_ID << 8) | NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x4U)

4
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -88,6 +88,8 @@ typedef struct NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS {
NvU16 height; /* out */
NvU16 depth; /* out */
NvU16 pitch; /* out */
NV_DECLARE_ALIGNED(NvU64 baseAddress, 8); /* out */
NV_DECLARE_ALIGNED(NvU64 size, 8); /* out */
} NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS;
/* _ctrl0080unix_h_ */

24
src/common/sdk/nvidia/inc/ctrl/ctrl0090.h
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@@ -128,3 +128,27 @@ typedef struct NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS {
#define NV0090_CTRL_CMD_PROGRAM_VIDMEM_PROMOTE (0x900107) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x7" */
#define NV0090_CTRL_CMD_INTERNAL_PROGRAM_VIDMEM_PROMOTE (0x900108) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0x8" */
/*
* NV0090_CTRL_SET_LG_SECTOR_PROMOTION
*
* This command toggles the type of LG sector promotion used by writing to NV_PTPC_PRI_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL and NV_PTPC_PRI_SM_L1TAG_CTRL2_SECTOR_PROMOTE_GLOBAL_EXT
*
* promoType[IN]
* This parameter specifies what kind of sector promotion to perform
*
*/
typedef enum NV0090_CTRL_SET_LG_SECTOR_PROMOTION_TYPE {
NV0090_CTRL_SET_LG_SECTOR_PROMOTION_NONE = 0,
NV0090_CTRL_SET_LG_SECTOR_PROMOTION_64B = 1,
NV0090_CTRL_SET_LG_SECTOR_PROMOTION_128B = 2,
} NV0090_CTRL_SET_LG_SECTOR_PROMOTION_TYPE;
#define NV0090_CTRL_SET_LG_SECTOR_PROMOTION_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV0090_CTRL_SET_LG_SECTOR_PROMOTION_PARAMS {
NV0090_CTRL_SET_LG_SECTOR_PROMOTION_TYPE promoType;
} NV0090_CTRL_SET_LG_SECTOR_PROMOTION_PARAMS;
#define NV0090_CTRL_CMD_SET_LG_SECTOR_PROMOTION (0x90010bU) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0xB" */
#define NV0090_CTRL_CMD_INTERNAL_SET_LG_SECTOR_PROMOTION (0x90010cU) /* finn: Evaluated from "(FINN_NV0090_KERNEL_GRAPHICS_CONTEXT_INTERFACE_ID << 8) | 0xC" */

30
src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -277,34 +277,6 @@ typedef struct NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS {
NvU16 numMemInfos;
} NV00F8_CTRL_GET_NUM_ATTACHED_MEM_PARAMS;
/*
* NV00F8_CTRL_CMD_GET_ATTACHED_MEM
*
* Queries attached physical memory info to the fabric object.
*
* offsetStart [IN]
* Offsets at which memory was attached.
*
* numMemInfos [IN]
* Number of memory infos to be filled.
*
* memInfos [IN/OUT]
* Attached memory infos.
* Use must populate a non-zero `hMemory` handle. This handle will be used by
* RM for duping physical memory.
*/
#define NV00F8_CTRL_CMD_GET_ATTACHED_MEM (0xf80106) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS_MESSAGE_ID" */
#define NV00F8_MAX_ATTACHED_MEM_INFOS 64
#define NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS {
NV_DECLARE_ALIGNED(NvU64 offsetStart, 8);
NvU16 numMemInfos;
NV_DECLARE_ALIGNED(NV00F8_CTRL_ATTACH_MEM_INFO memInfos[NV00F8_MAX_ATTACHED_MEM_INFOS], 8);
} NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS;
/*
* NV00F8_CTRL_CMD_GET_PAGE_LEVEL_INFO
*

10
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
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@@ -443,6 +443,13 @@ typedef struct NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS {
* This value indicates that UEFI is not running.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE
* This value indicates that UEFI is running.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT
* This field indicates the EFI running value. Legal values for
* this parameter include:
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE
* This value indicates that display is in vbios mode.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE
* This value indicates that display is in EFI mode.
*
* Possible status values returned are:
* NV_OK
@@ -468,6 +475,9 @@ typedef struct NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS {
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING 2:2
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE (0x00000000)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE (0x00000001)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT 3:3
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE (0x00000000)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE (0x00000001)

27
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -35,7 +35,7 @@
/*
* NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD
*
* Exports RM vidmem handles to a dma-buf fd.
* Exports RM vidmem and sysmem handles to a dma-buf fd.
*
* The objects in the 'handles' array are exported to the fd as range:
* [index, index + numObjects).
@@ -63,12 +63,25 @@
* This size includes the memory that will be exported in future export calls
* for this dma-buf.
*
* mappingType
* The type of mapping that must be used for this dma-buf.
* See NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_* for all possible values.
*
* With type DEFAULT, the driver shall decide the type based on platform coherency:
* C2C for coherent
* PCIe BAR1 for non-coherent
* Type FORCE_PCIE field is a workaround for platforms with Grace (PCIe Gen4/Gen5 RPs) paired with
* Gen6 parts like Blackwell GPUs and CX8 NICs, requiring a separate Gen6 PCIe link to maximize RDMA
* bandwidth. This type allows dma-buf to be mapped over this Gen6 PCIe link.
*
* This call shall return NV_ERR_NOT_SUPPORTED if FORCE_PCIE type is used on non-Grace platforms.
*
* handles
* An array of {handle, offset, size} that describes the dma-buf.
* The offsets and sizes must be OS page-size aligned.
*
* Limitations:
* 1. This call only supports vidmem objects for now.
* 1. This call supports vidmem and sysmem objects.
* 2. All memory handles should belong to the same GPU or the same GPU MIG instance.
*
* Possible status values returned are:
@@ -81,9 +94,12 @@
* NV_ERR_INVALID_OBJECT
* NV_ERR_INVALID_OBJECT_PARENT
*/
#define NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD (0x20803a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID << 8) | NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD (0x20803a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID << 8) | NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_DMABUF_MAX_HANDLES 128
#define NV2080_CTRL_DMABUF_MAX_HANDLES 128
#define NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT (0x00000000U)
#define NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE (0x00000001U)
typedef struct NV2080_CTRL_DMABUF_MEM_HANDLE_INFO {
NvHandle hMemory;
@@ -99,6 +115,7 @@ typedef struct NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS {
NvU32 numObjects;
NvU32 index;
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
NvU8 mappingType;
NV_DECLARE_ALIGNED(NV2080_CTRL_DMABUF_MEM_HANDLE_INFO handles[NV2080_CTRL_DMABUF_MAX_HANDLES], 8);
} NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS;

166
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
View File

@@ -389,6 +389,8 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/
#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7 (0x00000015U) /* GDDR7 */
/* valid RAM LOCATION types */
@@ -2669,6 +2671,9 @@ typedef struct NV2080_CTRL_CMD_FB_STATS_GET_PARAMS {
* @params [OUT] NvBool bStaticBar1Enabled:
* This field indicates the static BAR1 mode is enabled. All the following fields are valid
* only if static BAR1 mode is enabled.
* @params [OUT] NvU64 staticBar1StartOffset:
* Static BAR1 may start at nonzero BAR1 address.
* This field indicates the start offset of the static BAR1.
* @params [OUT] NvU64 staticBar1Size:
* This field indicates the size of the static BAR1.
*
@@ -2684,7 +2689,168 @@ typedef struct NV2080_CTRL_CMD_FB_STATS_GET_PARAMS {
typedef struct NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS {
NvBool bStaticBar1Enabled;
NV_DECLARE_ALIGNED(NvU64 staticBar1StartOffset, 8);
NV_DECLARE_ALIGNED(NvU64 staticBar1Size, 8);
} NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION
*
* This command returns the current DRAM encryption configuration
* setting for a GPU given its subdevice handle. The value returned
* is the current DRAM encryption setting for the GPU stored in non-volatile
* memory on the board.
*
* currentConfiguration
* The current DRAM encryption configuration setting.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION (0x20801355U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_DISABLED (0x00000000U)
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_ENABLED (0x00000001U)
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID (0x55U)
typedef struct NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS {
NvU32 currentConfiguration;
} NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS;
/*
* NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION
*
* This command changes the DRAM encryption configuration setting for
* a GPU given its subdevice handle. The value specified is stored
* in non-volatile memory on the board and will take effect with the
* next GPU reset.
*
* newConfiguration
* The new configuration setting to take effect with
* the next GPU reset.
*
* Possible status return values are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION (0x20801356U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_DISABLE (0x00000000U)
#define NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_ENABLE (0x00000001U)
#define NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID (0x56U)
typedef struct NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS {
NvU32 newConfiguration;
} NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_STATUS
*
* This control command is used by clients to get the FB availabilty status,
* i.e whether the GPU Memory is ready for use or not for MIG and non-MIG cases
*
* fbStatus[OUT]
* This parameter returns the various values of FB availability status.
* Valid values include:
* NV2080_CTRL_FB_STATUS_FAILED
* On Non Self hosted (Non NUMA) systems - this status is not expected since
* FB memory is available as part of GPU initialization itself.
* On Direct connected Self hosted systems - this status is not expected since
* FB memory is available as part of GPU initialization itself.
* On Nvswitch connected Self hosted systems - this status indicates that either
* the memory onlining has failed or fabric probe response has failed.
* GPU reset maybe required in such a case.
* NV2080_CTRL_FB_STATUS_READY
* On Non Self hosted systems - this status is always returned as memory is ready
* after GPU initialization is complete.
* On Self hosted systems - this status indicates that the FB memory has been onlined
* successfully and is available for client/user allocations.
* NV2080_CTRL_FB_STATUS_PENDING
* On Non Self hosted systems - this status is not expected
* On Direct connected Self hosted systems - this status is not expected since
* FB memory is available as part of GPU initialization itself.
* On Nvswitch connected Self hosted systems - This status indicates memory is yet to
* be onlined or is in progress since we are either still waiting for a fabric
* probe response or a fabric probe request hasn't been sent yet.
* NV2080_CTRL_FB_STATUS_NOT_APPLICABLE
* This status indicates that this is a system with no FB memory.
*
*
* @returns Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
* NV_ERR_NOT_READY
* NV_ERR_INVALID_LOCK_STATE
*/
#define NV2080_CTRL_CMD_FB_GET_STATUS (0x20801357U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID" */
// NUMA Memory Onlining Status
#define NV2080_CTRL_FB_STATUS_FAILED (0x00000000U)
#define NV2080_CTRL_FB_STATUS_READY (0x00000001U)
#define NV2080_CTRL_FB_STATUS_PENDING (0x00000002U)
#define NV2080_CTRL_FB_STATUS_NOT_APPLICABLE (0x00000003U)
#define NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID (0x57U)
typedef struct NV2080_CTRL_FB_GET_STATUS_PARAMS {
NvU32 fbStatus;
} NV2080_CTRL_FB_GET_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT
*
* This command returns whether or not DRAM encryption config object is supported via the InfoROM.
*
* isSupported [OUT]
* This parameter returns whether the DRAM Encryption inforom object is present in the inforom.
* The various values of isSupported is:
* 1. NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED
* 2. NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT (0x20801358U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED (0x00000000U)
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED (0x00000001U)
#define NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID (0x58U)
typedef struct NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS {
NvU32 isSupported;
} NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS;
/*
* NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS
*
* This command returns the current DRAM encryption status.
*
* currentStatus
* The current DRAM encryption status.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS (0x20801359U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED (0x00000000U)
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED (0x00000001U)
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID (0x59U)
typedef struct NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS {
NvU32 currentStatus;
} NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS;
/* _ctrl2080fb_h_ */

81
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -212,6 +212,10 @@ typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS {
* This index can be used to get max channel groups supported per engine/runlist.
* NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE
* This index can be used too get channel groups currently in use per engine/runlist.
* NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT
* This index can be used to query the maximum "lower" subcontext index
* allocated under NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER.
* Note: Includes subcontext ID 0, which will be allocated last in ASYNC allocation mode.
*
*/
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FIFO_INFO;
@@ -227,10 +231,11 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FIFO_INFO;
#define NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED (0x000000007)
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE (0x000000008)
#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE (0x000000009)
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT (0x00000000a)
/* set INDEX_MAX to greatest possible index value */
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT
#define NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT (12)
@@ -989,7 +994,7 @@ typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS {
* This field sets the runlist scheduling policy. It specifies the
* NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
*
* enableArr
* enableArr
* This field sets the Adaptive round robin scheduler
* is enabled/disabled.
*
@@ -1085,4 +1090,74 @@ typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS {
NvU32 minAvgFactorForARR;
} NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS;
// Max channels per group is limited by NV_RAMRL_ENTRY_TSG_LENGTH_MAX for the arch.
#define NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG 128
/*
* NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO
* hClient
* Input parameter
* This parameter specifies the client handle associated input channel/TSG
* hChannelOrTsg
* Input parameter.
* This parameter specifies the handle of input channel handle (or channel
* group)
* tsgId
* Output parameter.
* This field return the Unique of TSG object if user specified a channel group handle
* with hChannelOrTsg.
* numChannels
* Output parameter.
* This field return the number of channels under TSG if user specify a
* channel group handle or return 1 if user specify a channel handle.
* channelUniqueID
* Output parameter.
* This array field returns unique Channel ID for each channel.
* vasUniqueID
* Output parameter.
* This array field returns unique IDs of VA Space objects of channels under TSG or channel.
* veid
* Output parameter.
* This array field returns VEID for channels under TSG or channel.
*/
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO (0x20801123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID (0x23U)
typedef struct NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS {
NvHandle hClient;
NvHandle hChannelOrTsg;
NvU32 tsgId;
NvU32 numChannels;
NvU32 channelUniqueID[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
NvU32 vasUniqueID[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
NvU32 veid[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
} NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID
* This command is used query the CID (channel ID) in batch
* hClients
* Input parameter
* Array of Client handles
* hChannels
* Input parameter
* Array of Channel handles
* numChannels
* Indicates the number of input client, channel handle pairs.
* channelUniqueIDs
* Output parameter.
* This parameter returns an array of unique Channel IDs for each input pair.
* channel handles.
*/
#define NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID (0x20801124) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID (0x24U)
typedef struct NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS {
NvHandle hClients[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
NvHandle hChannels[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
NvU32 numChannels;
NvU32 channelUniqueIDs[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
} NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS;
/* _ctrl2080fifo_h_ */

209
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -42,7 +42,7 @@
#define NV_GRID_LICENSE_FEATURE_VAPPS_EDITION "GRID-Virtual-Apps,3.0"
#define NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0"
#define NV_GRID_LICENSE_FEATURE_GAMING_EDITION "GRID-vGaming,8.0"
#define NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION "NVIDIA-vComputeServer,9.0;Quadro-Virtual-DWS,5.0"
#define NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION "NVIDIA-vComputeServer,9.0"
#define NV_GRID_LICENSED_PRODUCT_VWS "NVIDIA RTX Virtual Workstation"
#define NV_GRID_LICENSED_PRODUCT_GAMING "NVIDIA Cloud Gaming"
@@ -81,7 +81,6 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE (0x00000025U)
#define NV2080_CTRL_GPU_INFO_INDEX_IBMNPU_RELAXED_ORDERING (0x00000026U)
#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED (0x00000027U)
#define NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED (0x00000028U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT (0x00000029U)
@@ -139,11 +138,6 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES (0x00000001U)
/* valid relaxed ordering values */
#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_DISABLED (0x00000000U)
#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_ENABLED (0x00000001U)
#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_UNSUPPORTED (0xFFFFFFFFU)
/* valid poison fuse capability values */
#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES (0x00000001U)
@@ -2523,6 +2517,26 @@ typedef struct NV2080_CTRL_GPU_PARTITION_SPAN {
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_GPU_PARTITION_SPAN;
/*
* NV2080_CTRL_EXEC_PARTITION_SPAN
*
* This struct represents the span of a compute partition, which represents the
* slices a given partition occupies (or may occupy) within a fixed range which
* is defined memory partition. A partition containing more resources will cover
* more GPU instance slices and therefore cover a larger span.
*
* lo
* - The starting unit of this span, inclusive
*
* hi
* - The ending unit of this span, inclusive
*
*/
typedef struct NV2080_CTRL_EXEC_PARTITION_SPAN {
NV_DECLARE_ALIGNED(NvU64 lo, 8);
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_EXEC_PARTITION_SPAN;
#define NV_GI_UUID_LEN 16U
/*
@@ -2607,6 +2621,18 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07 0x00000007U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 8U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE 7:5
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL 0x00000001U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF 0x00000002U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF 0x00000003U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER 0x00000004U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH 0x00000005U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_06 0x00000006U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_07 0x00000007U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE 0x00000000U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE 8U
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 40U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30
@@ -2896,10 +2922,13 @@ typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PA
typedef struct NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS {
NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
NvU32 runlistPriBase[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
NvU32 runlistId[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
} NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS;
#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL (0xFFFFFFFFU)
#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR (0xFFFFFFFBU)
#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_INVALID (0xFFFFFFFFU)
#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_ERROR (0xFFFFFFFBU)
/*
* NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID
@@ -3055,6 +3084,26 @@ typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS {
#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO (0x2080017cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX
*
* This command returns the first async ce index
*
* CE Index
* Output parameter.
* Returns the first async ce index
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID (0xe6U)
typedef struct NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS {
NvU32 firstAsyncCEIdx;
} NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS;
#define NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX (0x208001e6U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE
@@ -3069,7 +3118,7 @@ typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE (0x2080017eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE (0x2080017eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID (0x7EU)
@@ -4029,6 +4078,10 @@ typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE {
*
* This structure specifies resources in an execution partition
*
* partitionFlag[IN]
* - GPU instance profile flags for which to query compute profiles
* Ignored, if subdevice is subscribed to a GPU instance
*
* profileCount[OUT]
* - Total Number of profiles filled
*
@@ -4038,6 +4091,7 @@ typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE {
#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U)
typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
NvU32 partitionFlag;
NvU32 profileCount;
NV2080_CTRL_GPU_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE];
} NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS;
@@ -4057,10 +4111,25 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE 3:2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE 2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY 5:4
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE 2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY 7:6
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE 2
/*!
* NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS
@@ -4376,6 +4445,7 @@ typedef enum NV2080_CTRL_GPU_RECOVERY_ACTION {
NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET = 1,
NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT = 2,
NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P = 3,
NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET = 4,
} NV2080_CTRL_GPU_RECOVERY_ACTION;
#define NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID (0xB2U)
@@ -4400,5 +4470,120 @@ typedef struct NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS {
} NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS;
#define NV2080_CTRL_GPU_GET_FIPS_STATUS (0x208001e4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_GPU_GET_RAFTS_FS_MASK
*
* @brief Get floorsweeping mask for given skyline configuration.
*
* tpcCountMatrix [IN]
* TPC per GPC distribution for which user require floorsweeping mask.
*
* gfxGpcCount [IN]
* Number of GFX capable GPC required.
*
* gfxTpcCount [IN]
* Number of GFX capable TPC required.
*
* floorSweepConfig [OUT]
* MODS floorsweeping mask.
*
* bValid [OUT]
* If entries in floorSweepConfig are valid or not.
*
* @return NV_OK : on success
* @return NV_ERR_INVALID_PARAMETER : Parameters in pParams are incompatible with each other
* @return NV_ERR_NOT_SUPPORTED : Requested skyline not supported by current chip but can be supported by a chip
* with fewer defects
*/
typedef enum NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE {
NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID = 0,
NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC = 1,
NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC = 2,
} NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE;
typedef struct NV2080_RAFTS_FLOORSWEEP_INFO {
NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE unitType;
NvU32 parentId;
NvU32 mask;
} NV2080_RAFTS_FLOORSWEEP_INFO;
#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU 0x2
#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU 0xC
#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC (0x18) /* finn: Evaluated from "NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU * NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU" */
#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT (0x1a) /* finn: Evaluated from "NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC + 2" */
#define NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID (0xB3U)
typedef struct NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS {
NvU8 tpcCountMatrix[NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU][NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU];
NvBool bValid;
NV2080_RAFTS_FLOORSWEEP_INFO floorSweepConfig[NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT];
NvU8 gfxGpcCount;
NvU8 gfxTpcPerGpcCount;
NvU8 maxUgpuTpcDiff;
} NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS;
#define NV2080_CTRL_GPU_GET_RAFTS_FS_MASK (0x208001b3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS
*
* This structure specifies resources in an execution partition
*
* partitionFlag[IN]
* - If GPU instance profile flag for which to query specified
* compute profile
*
* computeSize[IN]
* - Size specifying compute profile whose info to query
*
* totalProfileCount[OUT]
* - Total Number of profiles possible to create in instance of specified GPU
* profile
*
* totalSpans[OUT]
* - List of spans which can possibly be occupied by partitions of the
* given type.
*
* totalSpansCount[OUT]
* - Number of entries filled in totalSpans
*
*/
#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILE_CAPACITY (0x208001e5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID (0xe5U)
typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS {
NvU32 partitionFlag;
NvU32 computeSize;
NvU32 totalProfileCount;
NV_DECLARE_ALIGNED(NV2080_CTRL_EXEC_PARTITION_SPAN totalSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8);
NvU32 totalSpansCount;
} NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK
*
* This command returns the TPC reconfig mask for a specific GPC
*
* gpc[IN]
* The GPC for which the TPC reconfig mask needs to be queried.
* The GPC should be specified as a logical index.
*
* tpcReconfigMask[OUT]
* Mask of reconfigurable TPCs in the specified GPC
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK (0x208001e7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID (0xe7U)
typedef struct NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS {
NvU32 gpc;
NvU32 tpcReconfigMask;
} NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS;
/* _ctrl2080gpu_h_ */

285
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -157,23 +157,23 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
* Valid GR info index values
* These indices are offset from supporting the 0080 version of this call
*/
#define NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS
#define NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894
#define NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK
#define NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS
#define NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894
#define NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK
/**
* This index is used to request the surface buffer alignment (in bytes)
* required by the associated subdevice. The return value is GPU
* implementation-dependent.
*/
#define NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT
#define NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT
#define NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE
#define NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT
#define NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT
#define NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE
/**
* This index is used to request the number of VPE units supported by the
* associated subdevice. The return value is GPU implementation-dependent.
* A return value of 0 indicates the GPU does not contain VPE units.
*/
#define NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT
/**
* This index is used to request the number of shader pipes supported by
* the associated subdevice. The return value is GPU
@@ -181,13 +181,13 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
* not contain dedicated shader units.
* For tesla: this value is the number of enabled TPCs
*/
#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT
/**
* This index is used to request the scaling factor for thread stack
* memory.
* A value of 0 indicates the GPU does not support this function.
*/
#define NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR
#define NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR
/**
* This index is used to request the number of sub units per
* shader pipes supported by the associated subdevice. The return
@@ -195,157 +195,167 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
* the GPU does not contain dedicated shader units.
* For tesla: this value is the number of enabled SMs (per TPC)
*/
#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT
/**
* This index is used to determine the SM version.
* A value of 0 indicates the GPU does not support this function.
* Otherwise one of NV2080_CTRL_GR_INFO_SM_VERSION_*.
*/
#define NV2080_CTRL_GR_INFO_INDEX_SM_VERSION NV0080_CTRL_GR_INFO_INDEX_SM_VERSION
#define NV2080_CTRL_GR_INFO_INDEX_SM_VERSION NV0080_CTRL_GR_INFO_INDEX_SM_VERSION
/**
* This index is used to determine the maximum number of warps
* (thread groups) per SM.
* A value of 0 indicates the GPU does not support this function.
*/
#define NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM
#define NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM
/**
* This index is used to determine the maximum number of threads
* in each warp (thread group).
* A value of 0 indicates the GPU does not support this function.
*/
#define NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP
#define NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES
#define NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES
#define NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY
#define NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY
#define NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS
#define NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS
#define NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP
#define NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES
#define NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES
#define NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY
#define NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY
#define NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS
#define NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS
/**
* This index is used to return the number of "Ray Tracing Cores"
* supported by the graphics pipeline
*/
#define NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP
#define NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
#define NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP
#define NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES
#define NV2080_CTRL_GR_INFO_INDEX_DUMMY NV0080_CTRL_GR_INFO_INDEX_DUMMY
#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
#define NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES
#define NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG
#define NV2080_CTRL_GR_INFO_INDEX_DUMMY NV0080_CTRL_GR_INFO_INDEX_DUMMY
#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
#define NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES
#define NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET
/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
* reflects that.
*/
#define NV2080_CTRL_GR_INFO_INDEX_MAX NV0080_CTRL_GR_INFO_INDEX_MAX
#define NV2080_CTRL_GR_INFO_MAX_SIZE NV0080_CTRL_GR_INFO_MAX_SIZE
#define NV2080_CTRL_GR_INFO_INDEX_MAX NV0080_CTRL_GR_INFO_INDEX_MAX
#define NV2080_CTRL_GR_INFO_MAX_SIZE NV0080_CTRL_GR_INFO_MAX_SIZE
/* valid SM version return values */
#define NV2080_CTRL_GR_INFO_SM_VERSION_NONE (0x00000000U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_05 (0x00000105U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_1 (0x00000110U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_2 (0x00000120U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_3 (0x00000130U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_4 (0x00000140U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_5 (0x00000150U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_2_0 (0x00000200U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_2_1 (0x00000210U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_2_2 (0x00000220U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_0 (0x00000300U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_1 (0x00000310U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_2 (0x00000320U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_3 (0x00000330U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_5 (0x00000350U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_6 (0x00000360U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_8 (0x00000380U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_9 (0x00000390U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_4_0 (0x00000400U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_0 (0x00000500U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_02 (0x00000502U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_03 (0x00000503U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_0 (0x00000600U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_01 (0x00000601U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_02 (0x00000602U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_0 (0x00000700U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_01 (0x00000701U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_02 (0x00000702U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_03 (0x00000703U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_05 (0x00000705U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_02 (0x00000802U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_06 (0x00000806U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_07 (0x00000807U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_08 (0x00000808U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_00 (0x00000A00U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01 (0x00000A01U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_NONE (0x00000000U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_05 (0x00000105U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_1 (0x00000110U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_2 (0x00000120U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_3 (0x00000130U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_4 (0x00000140U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_5 (0x00000150U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_2_0 (0x00000200U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_2_1 (0x00000210U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_2_2 (0x00000220U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_0 (0x00000300U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_1 (0x00000310U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_2 (0x00000320U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_3 (0x00000330U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_5 (0x00000350U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_6 (0x00000360U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_8 (0x00000380U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_9 (0x00000390U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_4_0 (0x00000400U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_0 (0x00000500U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_02 (0x00000502U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_03 (0x00000503U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_0 (0x00000600U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_01 (0x00000601U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_02 (0x00000602U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_0 (0x00000700U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_01 (0x00000701U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_02 (0x00000702U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_03 (0x00000703U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_05 (0x00000705U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_02 (0x00000802U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_06 (0x00000806U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_07 (0x00000807U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_08 (0x00000808U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_00 (0x00000A00U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01 (0x00000A01U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_04 (0x00000A04U)
/* compatibility SM versions to match the official names in the ISA (e.g., SM5.2) */
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_2 (NV2080_CTRL_GR_INFO_SM_VERSION_5_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_3 (NV2080_CTRL_GR_INFO_SM_VERSION_5_03)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_1 (NV2080_CTRL_GR_INFO_SM_VERSION_6_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_2 (NV2080_CTRL_GR_INFO_SM_VERSION_6_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_1 (NV2080_CTRL_GR_INFO_SM_VERSION_7_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_2 (NV2080_CTRL_GR_INFO_SM_VERSION_7_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_3 (NV2080_CTRL_GR_INFO_SM_VERSION_7_03)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_5 (NV2080_CTRL_GR_INFO_SM_VERSION_7_05)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_2 (NV2080_CTRL_GR_INFO_SM_VERSION_8_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_6 (NV2080_CTRL_GR_INFO_SM_VERSION_8_06)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_7 (NV2080_CTRL_GR_INFO_SM_VERSION_8_07)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_8 (NV2080_CTRL_GR_INFO_SM_VERSION_8_08)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9 (NV2080_CTRL_GR_INFO_SM_VERSION_8_09)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_0 (NV2080_CTRL_GR_INFO_SM_VERSION_10_00)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1 (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_2 (NV2080_CTRL_GR_INFO_SM_VERSION_5_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_3 (NV2080_CTRL_GR_INFO_SM_VERSION_5_03)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_1 (NV2080_CTRL_GR_INFO_SM_VERSION_6_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_2 (NV2080_CTRL_GR_INFO_SM_VERSION_6_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_1 (NV2080_CTRL_GR_INFO_SM_VERSION_7_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_2 (NV2080_CTRL_GR_INFO_SM_VERSION_7_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_3 (NV2080_CTRL_GR_INFO_SM_VERSION_7_03)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_5 (NV2080_CTRL_GR_INFO_SM_VERSION_7_05)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_2 (NV2080_CTRL_GR_INFO_SM_VERSION_8_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_6 (NV2080_CTRL_GR_INFO_SM_VERSION_8_06)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_7 (NV2080_CTRL_GR_INFO_SM_VERSION_8_07)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_8 (NV2080_CTRL_GR_INFO_SM_VERSION_8_08)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9 (NV2080_CTRL_GR_INFO_SM_VERSION_8_09)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_0 (NV2080_CTRL_GR_INFO_SM_VERSION_10_00)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1 (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_4 (NV2080_CTRL_GR_INFO_SM_VERSION_10_04)
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D 0:0
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D 1:1
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE 2:2
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M 3:3
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE 0x1U
/**
* NV2080_CTRL_CMD_GR_GET_INFO
@@ -367,7 +377,7 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
* disambiguate the target GR engine. When MIG is enabled, this
* is a mandatory parameter.
*/
#define NV2080_CTRL_CMD_GR_GET_INFO (0x20801201U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GR_GET_INFO (0x20801201U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
@@ -1909,26 +1919,29 @@ typedef struct NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS {
} NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS;
/*
* NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION
* NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK
*
* This command grabs information on GFX capable GPC's and TPC's for a specifc GR engine
* This command returns the TPC reconfig mask for a specific GPC
*
* promoType[IN]
* This parameter specifies what kind of sector promotion to perform
* gpc[IN]
* The GPC for which the TPC reconfig mask needs to be queried.
* The GPC should be specified as a logical index.
*
* tpcReconfigMask[OUT]
* Mask of reconfigurable TPCs in the specified GPC
*
* grRouteInfo[IN]
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_SET_LG_SECTOR_PROMOTION (0x2080123bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK (0x2080123bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_TYPE {
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_NONE = 0,
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_64B = 1,
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_128B = 2,
} NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_TYPE;
#define NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID (0x3bU)
#define NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS_MESSAGE_ID (0x3BU)
typedef struct NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS {
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_TYPE promoType;
} NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS;
typedef struct NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS {
NvU32 gpc;
NvU32 tpcReconfigMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
} NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS;
/* _ctrl2080gr_h_ */

55
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h
View File

@@ -131,8 +131,63 @@ typedef struct NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT {
typedef struct NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS {
NvU32 gfid;
NV_DECLARE_ALIGNED(NvU64 managedSize, 8);
NV_DECLARE_ALIGNED(NvU64 largestFreeChunkSize, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT current, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT peak, 8);
} NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS;
/*
* NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS
*
* This command reports the current partition's VGPU-GSP plugin's heap usage statistics.
*
* managedSize
* The total size in bytes of the underlying heap. Note that not all memory
* will be allocatable, due to fragmentation and memory allocator/tracking
* overhead.
* allocatedSize
* Allocated memory size, in bytes. This value does not include overhead used
* by the underlying allocator for padding/metadata.
* allocationCount
* The number of active allocations. This count reflects the current number of
* memory blocks that have been allocated but not yet freed.
* peakAllocatedSize
* The highest recorded allocated memory size, in bytes. This value represents the
* maximum amount of memory that has been allocated at any point in time. When a new
* highest allocated size is recorded, the peakAllocatedSize is updated.
* peakAllocationCount
* The number of active allocations corresponding to the highest recorded peakAllocatedSize.
*/
#define NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS (0x20803603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 allocatedSize, 8);
NV_DECLARE_ALIGNED(NvU64 peakAllocatedSize, 8);
NV_DECLARE_ALIGNED(NvU64 managedSize, 8);
NvU32 allocationCount;
NvU32 peakAllocationCount;
NV_DECLARE_ALIGNED(NvU64 largestFreeChunkSize, 8);
} NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS;
#define NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS (0x20803604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX 64
typedef struct NV2080_CTRL_GSP_LIBOS_POOL_STATS {
NvU32 allocations;
NvU32 peakAllocations;
NV_DECLARE_ALIGNED(NvU64 objectSize, 8);
} NV2080_CTRL_GSP_LIBOS_POOL_STATS;
#define NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_LIBOS_POOL_STATS poolStats[NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX], 8);
NV_DECLARE_ALIGNED(NvU64 totalHeapSize, 8);
NvU8 poolCount;
} NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS;
// _ctrl2080gsp_h_

626
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -79,6 +79,7 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS {
NvU32 embeddedDisplayPortMask;
NvBool bExternalMuxSupported;
NvBool bInternalMuxSupported;
NvU32 numDispChannels;
} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS;
@@ -2195,7 +2196,6 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS {
NvBool bIsC2CLinkUp;
NvBool bIsDeviceMultiFunction;
NvBool bGcxPmuCfgSpaceRestore;
NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8);
} NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS;
/*!
@@ -2227,33 +2227,6 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS {
NvU32 programPciePeerMask;
} NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID
*
* Given a mask of link ids, find the first with a valid peerId.
*
* linkMask[IN]
* Mask of linkIds to check.
*
* peerId[OUT]
* The peerId for the lowest-index link with a valid peerId, if any.
* If none found, NV2080_CTRLINTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER (return value will still be NV_OK).
*
* Possible status values returned are:
* NV_OK
*
*/
#define NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID (0x20800a89) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER 0xffffffff
#define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS {
NvU32 linkMask;
NvU32 peerId;
} NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS
*
@@ -2806,7 +2779,7 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS {
#define NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID (0xBFU)
typedef struct NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS {
NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters;
NV_DECLARE_ALIGNED(NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters, 8);
} NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS;
/*!
@@ -2952,6 +2925,7 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS {
* Handle to SYSMEM memlist object
* [in] bEnteringGcoffState
* Value of PDB_PROP_GPU_GCOFF_STATE_ENTERING
* [in] sysmemAddrOfSuspendResumeData
*
* Possible status values returned are:
* NV_OK
@@ -2967,6 +2941,7 @@ typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
NvHandle hClient;
NvHandle hSysMem;
NvBool bEnteringGcoffState;
NV_DECLARE_ALIGNED(NvU64 sysmemAddrOfSuspendResumeData, 8);
} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS;
/*!
@@ -3822,6 +3797,23 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS
} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID
*
* This command is an internal command sent from Kernel RM to Physical RM
* to update the logical Uproc Id for the configuration.
*
* logicalUprocId [OUT]
*/
#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID (0x20800aef) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID (0xEFU)
typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS {
NvU8 logicalUprocId;
} NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP
@@ -4021,6 +4013,7 @@ typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS {
* @brief Set mask of data to be polled on physical for RUSD
*
* @param[in] polledDataMask Bitmask of data requested, defined in cl00de
* @param[in] pollFrequencyMs Requested polling interval, in ms
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
@@ -4029,6 +4022,7 @@ typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS {
NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8);
NvU32 pollFrequencyMs;
} NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */
@@ -4128,8 +4122,17 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS {
* This command is used to perform recovery actions after the fabric has been
* idled due to a fatal nvlink error.
* This command accepts no parameters.
*
* bSuccessful
* NV_TRUE if recovery was successful, NV_FALSE otherwise
*/
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY (0x20800aea) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xEA" */
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY (0x20800aea) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID (0xEAU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS {
NvBool bSuccessful;
} NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP
@@ -4686,4 +4689,567 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS {
} NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER (0x20800a50U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID
*
* Log an XID message to OOB.
*
* xid [in]
* The XID number of the message.
*
* message [in]
* The text message, including the NULL terminator.
*
* len [in]
* The length, in bytes, of the text message, excluding the NULL terminator.
*
* Possible status return values are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID (0x20800a56U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID" */
#define NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE (81U)
#define NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID (0x56U)
typedef struct NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS {
NvU32 xid;
NvU8 message[NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE];
NvU32 len;
} NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS;
#define NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM 0x1U
#define NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER 0x2U
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING
*
* Performs all the necessary actions required to remove NVLink mapping (sysmem or peer or both)
*
* [In] mapTypeMask
* Remove NVLink mapping for the given map types (sysmem or peer or both)
* [In] peerMask
* Mask of Peer IDs which needs to be removed on NVLink
* Only parsed if mapTypeMask accounts peer
* [In] bL2Entry
* Is the peer removal happening because links are entering L2 low power state?
* Only parsed if mapTypeMask accounts peer
*/
#define NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID (0x5FU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS {
NvU32 mapTypeMask;
NvU32 peerMask;
NvBool bL2Entry;
} NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING (0x20800a5fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE
*
* Performs all the necessary actions required to save/restore HSHUB state during NVLink L2 entry/exit
*
* [In] bSave
* Whether this is a save/restore operation
* [In] linkMask
* Mask of links for which HSHUB config registers need to be saved/restored
*/
#define NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID (0x62U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS {
NvBool bSave;
NvU32 linkMask;
} NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE (0x20800a62U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET (0x00000000)
#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE (0x00000001)
#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE (0x00000002)
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY
*
* Performs all the necessary actions required to save/restore bufferready state during NVLink L2 entry/exit
*
* [In] flags
* Whether to set, save or restore bufferready
* [In] bSysmem
* Whether to perform the operation for sysmem links or peer links
* [In] peerLinkMask
* Mask of peer links for which bufferready state need to be set/saved/restored
*/
#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID (0x64U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS {
NvU32 flags;
NvBool bSysmem;
NvU32 peerLinkMask;
} NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY (0x20800a64U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG
*
* Performs all the necessary actions required to update the current Nvlink configuration
*
* [out] bNvlinkSysmemEnabled
* Whether sysmem nvlink support was enabled
*/
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID (0x78U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS {
NvBool bNvlinkSysmemEnabled;
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG (0x20800a78U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK
*
* Synchronizes the peerLinkMask between CPU-RM and GSP-RM
*
* [In] gpuInst
* Gpu instance
* [In] peerLinkMask
* Mask of links to the given peer GPU
*/
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID (0x7DU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS {
NvU32 gpuInst;
NvU32 peerLinkMask;
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK (0x20800a7dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION
*
* Updates the remote connection information for a link
*
* [In] linkId
* Id of the link to be used
* [In] bConnected
* Boolean that tracks whether the link is connected
* [In] remoteDeviceType
* Tracks whether the remote device is switch/gpu/ibmnpu/tegra
* [In] remoteLinkNumber
* Tracks the link number for the connected remote device
*/
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID (0x82U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS {
NV_DECLARE_ALIGNED(NvU64 remoteDeviceType, 8);
NV_DECLARE_ALIGNED(NvU64 remoteChipSid, 8);
NvU32 linkId;
NvU32 laneRxdetStatusMask;
NvU32 remoteLinkNumber;
NvU32 remotePciDeviceId;
NvU32 remoteDomain;
NvU8 remoteBus;
NvU8 remoteDevice;
NvU8 remoteFunction;
NvBool bConnected;
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION (0x20800a82U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY
*
* Enable links post topology via GSP
*
* [In] linkMask
* Mask of links to enable
* [Out] initializedLinks
* Mask of links that were initialized
*/
#define NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID (0x83U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS {
NvU32 linkMask;
NvU32 initializedLinks;
} NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY (0x20800a83U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI
*
* [In] linkMask
* Mask of enabled links to train
* [In] bSync
* The input sync boolean
*/
#define NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x84U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS {
NvU32 linkMask;
NvBool bSync;
} NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI (0x20800a84U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE 64
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET
*
* Get link mask post Rx detection
*
* [Out] postRxDetLinkMask
* Mask of links discovered
* [Out] laneRxdetStatusMask
* RXDET per-lane status mask
*/
#define NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID (0x85U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS {
NV_DECLARE_ALIGNED(NvU64 postRxDetLinkMask, 8);
NvU32 laneRxdetStatusMask[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET (0x20800a85U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI
*
* [In] linkMask
* Mask of enabled links to train
* [In] bSync
* The input sync boolean
*/
#define NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x86U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS {
NvU32 linkMask;
NvBool bSync;
} NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI (0x20800a86U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES {
NvBool bValid;
NvU8 linkId;
NvU32 ioctrlId;
NvU8 pllMasterLinkId;
NvU8 pllSlaveLinkId;
NvU32 ipVerDlPl;
} NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES;
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO
*
* [Out] ioctrlMask
* Mask of IOCTRLs discovered from PTOP device info table
* [Out] ioctrlNumEntries
* Number of IOCTRL entries in the PTOP device info table
* [Out] ioctrlSize
* Maximum number of entries in the PTOP device info table
* [Out] discoveredLinks
* Mask of links discovered from all the IOCTRLs
* [Out] ipVerNvlink
* IP revision of the NVLink HW
* [Out] linkInfo
* Per link information
*/
#define NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID (0x87U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS {
NvU32 ioctrlMask;
NvU8 ioctrlNumEntries;
NvU32 ioctrlSize;
NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8);
NvU32 ipVerNvlink;
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES linkInfo[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO (0x20800a87U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_NVLINK_MAX_LINKS_PER_IOCTRL_SW 6U
typedef struct NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES {
NvU32 ipVerIoctrl;
NvU32 ipVerMinion;
} NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES;
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO
*
* [In] ioctrlIdx
* IOCTRL index
* [Out] PublicId
* PublicId of the IOCTRL discovered
* [Out] localDiscoveredLinks
* Mask of discovered links local to the IOCTRL
* [Out] localGlobalLinkOffset
* Global link offsets for the locally discovered links
* [Out] ioctrlDiscoverySize
* IOCTRL table size
* [Out] numDevices
* Number of devices discovered from the IOCTRL
* [Out] deviceIpRevisions
* IP revisions for the devices discovered in the IOCTRL
*/
#define NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x8EU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS {
NvU32 ioctrlIdx;
NvU32 PublicId;
NvU32 localDiscoveredLinks;
NvU32 localGlobalLinkOffset;
NvU32 ioctrlDiscoverySize;
NvU8 numDevices;
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES ipRevisions;
} NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO (0x20800a8eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED
*
* Program NVLink Speed from OS/VBIOS
*
* [In] bPlatformLinerateDefined
* Whether line rate is defined in the platform
* [In] platformLineRate
* Platform defined line rate
* [Out] nvlinkLinkSpeed
* The line rate that was programmed for the links
*/
#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID (0x8FU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS {
NvBool bPlatformLinerateDefined;
NvU32 platformLineRate;
NvU32 nvlinkLinkSpeed;
} NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED (0x20800a8fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED
*
* [In] linkMask
* Mask of links whose state will be checked
* [In] bActiveOnly
* The input boolean to check for Link Active state
* [Out] bIsLinkActive
* Boolean array to track if the link is trained
*/
#define NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID (0x90U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS {
NvU32 linkMask;
NvBool bActiveOnly;
NvBool bIsLinkActive[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED (0x20800a90U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_ASSERT (0x00000000)
#define NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_DEASSERT (0x00000001)
#define NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_TOGGLE (0x00000002)
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS
*
* [In] linkMask
* Mask of links which need to be reset
* [In] flags
* Whether to assert, de-assert or toggle the Nvlink reset
*/
#define NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID (0x91U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS {
NvU32 linkMask;
NvU32 flags;
} NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS (0x20800a91U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS
*
* [In] linkMask
* Mask of links for which DL interrrupts need to be disabled
*/
#define NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID (0x92U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS {
NvU32 linkMask;
} NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS (0x20800a92U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID" */
/*
* Structure to store the GET_LINK_AND_CLOCK__INFO params
*
* [Out] bLinkConnectedToSystem
* Boolean indicating sysmem connection of a link
* [Out] bLinkConnectedToPeer
* Boolean indicating peer connection of a link
* [Out] bLinkReset
* Whether the link is in reset
* [Out] subLinkWidth
* Number of lanes per sublink
* [Out] linkState
* Mode of the link
* [Out] txSublinkState
* Tx sublink state
* [Out] rxSublinkState
* Rx sublink state
* [Out] bLaneReversal
* Boolean indicating if a link's lanes are reversed
* [Out] nvlinkLinkClockKHz
* Link clock value in KHz
* [Out] nvlinkLineRateMbps
* Link line rate in Mbps
* [Out] nvlinkLinkClockMhz
* Link clock in MHz
* [Out] nvlinkLinkDataRateKiBps
* Link Data rate in KiBps
* [Out] nvlinkRefClkType
* Current Nvlink refclk source
* [Out] nvlinkReqLinkClockMhz
* Requested link clock value
* [Out] nvlinkMinL1Threshold
* Requested link Min L1 Threshold
* [Out] nvlinkMaxL1Threshold
* Requested link Max L1 Threshold
* [Out] nvlinkL1ThresholdUnits
* Requested link L1 Threshold Units
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES {
NvBool bLinkConnectedToSystem;
NvBool bLinkConnectedToPeer;
NvBool bLinkReset;
NvU8 subLinkWidth;
NvU32 linkState;
NvU32 txSublinkState;
NvU32 rxSublinkState;
NvBool bLaneReversal;
NvU32 nvlinkLinkClockKHz;
NvU32 nvlinkLineRateMbps;
NvU32 nvlinkLinkClockMhz;
NvU32 nvlinkLinkDataRateKiBps;
NvU8 nvlinkRefClkType;
NvU32 nvlinkReqLinkClockMhz;
NvU32 nvlinkMinL1Threshold;
NvU32 nvlinkMaxL1Threshold;
NvU32 nvlinkL1ThresholdUnits;
} NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES;
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO
*
* [In] linkMask
* Mask of enabled links to loop over
* [Out] nvlinkRefClkSpeedKHz
* Ref clock value n KHz
* [Out] linkInfo
* Per link information
*/
#define NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID (0x93U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NvU32 nvlinkRefClkSpeedKHz;
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO (0x20800a93U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM
*
* Updates the HSHUB sysmem config resgister state to reflect sysmem NVLinks
*
* [In] sysmemLinkMask
* Mask of discovered sysmem NVLinks
*/
#define NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID (0x94U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS {
NvU32 sysmemLinkMask;
} NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM (0x20800a94U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS
*
* Process NVLink forced configurations which includes setting of HSHUB and memory system
*
* [In] bLegacyForcedConfig
* Tracks whether the forced config is legacy forced config or chiplib config
* [Out] bOverrideComputePeerMode
* Whether compute peer mode was enabled
* [In] phase
* Only applicable when bLegacyForcedConfig is true
* Tracks the set of registers to program from the NVLink table
* [In] linkConnection
* Array of chiplib configurations
*/
#define NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID (0x95U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS {
NvBool bLegacyForcedConfig;
NvBool bOverrideComputePeerMode;
NvU32 phase;
NvU32 linkConnection[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS (0x20800a95U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS
*
* Sync the NVLink lane shutdown properties with GSP-RM
*
* [In] bLaneShutdownOnUnload
* Whether nvlink shutdown should be triggered on driver unload
*/
#define NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID (0x96U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS {
NvBool bLaneShutdownOnUnload;
} NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS (0x20800a96U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS
*
* Enable ATS functionality related to NVLink sysmem if hardware support is available
*
* [In] notUsed
*/
#define NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID (0x97U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS {
NvU32 notUsed;
} NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS (0x20800a97U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK
*
* Get the mask of Nvlink links connected to system
*
* [Out] sysmemLinkMask
* Mask of Nvlink links connected to system
*/
#define NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID (0xABU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
NvU32 sysmemLinkMask;
} NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20800aabU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */
/* ctrl2080internal_h */

12
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h
View File

@@ -81,6 +81,8 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 (0x00000190)
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100 (0x000001A0)
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200 (0x000001B0)
/* valid ARCHITECTURE_T23X implementation values */
@@ -132,6 +134,16 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 (0x00000002)
/* valid ARCHITECTURE_GB20x implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 (0x00000003)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB204 (0x00000004)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 (0x00000005)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 (0x00000006)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 (0x00000007)
/* Valid Chip sub revisions */
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)

726
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -50,9 +50,13 @@
* This field specifies the lowest supported NCI version for this subdevice.
* highestNciVersion
* This field specifies the highest supported NCI version for this subdevice.
* discoveredLinkMask
* discoveredLinkMask // deprecated use discovered links
* This field provides a bitfield mask of NVLink links discovered on this subdevice.
* enabledLinkMask
* enabledLinkMask // deprecated use enabled Links
* This field provides a bitfield mask of NVLink links enabled on this subdevice.
* discoveredLinks
* This field provides a bitfield mask of NVLink links discovered on this subdevice.
* enabledLinks
* This field provides a bitfield mask of NVLink links enabled on this subdevice.
*
*/
@@ -68,6 +72,9 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
NvU32 discoveredLinkMask;
NvU32 enabledLinkMask;
NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8);
NV_DECLARE_ALIGNED(NvU64 enabledLinks, 8);
} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS;
/* extract cap bit setting from tbl */
@@ -175,6 +182,8 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
* See NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_* for possible values
* deviceUUID
* This field specifies the device UUID of the device. Useful for identifying the device (or version)
* fabricRecoveryStatusMask
* This field contains flags which advertise the current GPU-centric health status of the NVLINKs
*/
typedef struct NV2080_CTRL_NVLINK_DEVICE_INFO {
// ID Flags
@@ -192,21 +201,31 @@ typedef struct NV2080_CTRL_NVLINK_DEVICE_INFO {
// Device UUID
NvU8 deviceUUID[16];
// GPU-centric fabric health
NvU32 fabricRecoveryStatusMask;
} NV2080_CTRL_NVLINK_DEVICE_INFO;
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS 31:0
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE (0x00000000U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU (0x00000001U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU (0x00000002U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH (0x00000003U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA (0x00000004U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE (0x000000FFU)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE (0x00000000U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU (0x00000001U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU (0x00000002U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH (0x00000003U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA (0x00000004U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE (0x000000FFU)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID (0xFFFFFFFFU)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID (0xFFFFFFFFU)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED 0:0
#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_FALSE (0x00000000U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_TRUE (0x00000001U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY 1:1
#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_INACTIVE (0x00000000U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_ACTIVE (0x00000001U)
/*
* NV2080_CTRL_NVLINK_NVLINK_LINK_STATUS_INFO
@@ -409,6 +428,7 @@ typedef enum NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT {
} NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT;
#define NV2080_CTRL_NVLINK_MAX_LINKS 32
#define NV2080_CTRL_NVLINK_MAX_ARR_SIZE 64
// NVLink REFCLK types
#define NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID (0x00U)
@@ -420,7 +440,7 @@ typedef enum NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT {
typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS {
NvU32 enabledLinkMask;
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_STATUS_INFO linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_STATUS_INFO linkInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS;
/*
@@ -691,7 +711,7 @@ typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO {
typedef struct NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS {
NvU32 linkMask;
NV2080_CTRL_NVLINK_ERR_INFO linkErrInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
NV2080_CTRL_NVLINK_ERR_INFO linkErrInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
NvU32 ioctrlMask;
NV2080_CTRL_NVLINK_COMMON_ERR_INFO commonErrInfo[NV2080_CTRL_NVLINK_MAX_IOCTRLS];
NvU8 ErrInfoFlags;
@@ -799,7 +819,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES {
typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS {
NvU32 counterMask;
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
} NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_COUNTERS (0x20803004U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID" */
@@ -1008,7 +1028,7 @@ typedef struct NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES {
typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES counter[NV2080_CTRL_NVLINK_MAX_LINKS][NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES counter[NV2080_CTRL_NVLINK_MAX_ARR_SIZE][NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ], 8);
} NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2 (0x20803050U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID)" */
@@ -1138,7 +1158,7 @@ typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG {
typedef struct NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG errCfg[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG errCfg[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
} NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT (0x20803081U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID" */
@@ -1189,7 +1209,7 @@ typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO {
typedef struct NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO errInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO errInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT (0x20803082U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID" */
@@ -1209,7 +1229,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS {
typedef struct NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS {
NvU32 linkMask;
NvU32 numRecoveries[NV2080_CTRL_NVLINK_MAX_LINKS];
NvU32 numRecoveries[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS;
/*
@@ -1891,7 +1911,7 @@ typedef struct NV2080_CTRL_NVLINK_LINK_ECC_ERROR {
typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS {
NvU32 linkMask;
NV2080_CTRL_NVLINK_LINK_ECC_ERROR errorLink[NV2080_CTRL_NVLINK_MAX_LINKS];
NV2080_CTRL_NVLINK_LINK_ECC_ERROR errorLink[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS;
@@ -1960,7 +1980,7 @@ typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES {
typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS {
NvU16 counterMask;
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS (0x20803015U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID" */
@@ -2028,93 +2048,10 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS {
NvU32 counterValues[NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS];
} NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */
#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */
#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM 0x1U
#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER 0x2U
/*
* NV2080_CTRL_CMD_NVLINK_REMOVE_NVLINK_MAPPING
*
* Performs all the necessary actions required to remove NVLink mapping (sysmem or peer or both)
*
* [In] mapTypeMask
* Remove NVLink mapping for the given map types (sysmem or peer or both)
* [In] peerMask
* Mask of Peer IDs which needs to be removed on NVLink
* Only parsed if mapTypeMask accounts peer
* [In] bL2Entry
* Is the peer removal happening because links are entering L2 low power state?
* Only parsed if mapTypeMask accounts peer
*/
#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID (0x1fU)
typedef struct NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS {
NvU32 mapTypeMask;
NvU32 peerMask;
NvBool bL2Entry;
} NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_REMOVE_NVLINK_MAPPING (0x2080301fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_SAVE_RESTORE_HSHUB_STATE
*
* Performs all the necessary actions required to save/restore HSHUB state during NVLink L2 entry/exit
*
* [In] bSave
* Whether this is a save/restore operation
* [In] linkMask
* Mask of links for which HSHUB config registers need to be saved/restored
*/
#define NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS {
NvBool bSave;
NvU32 linkMask;
} NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SAVE_RESTORE_HSHUB_STATE (0x20803020U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET (0x00000000)
#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE (0x00000001)
#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE (0x00000002)
/*
* NV2080_CTRL_CMD_NVLINK_PROGRAM_BUFFERREADY
*
* Performs all the necessary actions required to save/restore bufferready state during NVLink L2 entry/exit
*
* [In] flags
* Whether to set, save or restore bufferready
* [In] bSysmem
* Whether to perform the operation for sysmem links or peer links
* [In] peerLinkMask
* Mask of peer links for which bufferready state need to be set/saved/restored
*/
#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS {
NvU32 flags;
NvBool bSysmem;
NvU32 peerLinkMask;
} NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PROGRAM_BUFFERREADY (0x20803021U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_UPDATE_CURRENT_CONFIG
*
* Performs all the necessary actions required to update the current Nvlink configuration
*
* [out] bNvlinkSysmemEnabled
* Whether sysmem nvlink support was enabled
*/
#define NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID (0x22U)
typedef struct NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS {
NvBool bNvlinkSysmemEnabled;
} NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_UPDATE_CURRENT_CONFIG (0x20803022U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID" */
//
// Set the near end loopback mode using the following
@@ -2149,93 +2086,6 @@ typedef struct NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE (0x20803023U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_UPDATE_PEER_LINK_MASK
*
* Synchronizes the peerLinkMask between CPU-RM and GSP-RM
*
* [In] gpuInst
* Gpu instance
* [In] peerLinkMask
* Mask of links to the given peer GPU
*/
#define NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID (0x24U)
typedef struct NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS {
NvU32 gpuInst;
NvU32 peerLinkMask;
} NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_UPDATE_PEER_LINK_MASK (0x20803024U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_UPDATE_LINK_CONNECTION
*
* Updates the remote connection information for a link
*
* [In] linkId
* Id of the link to be used
* [In] bConnected
* Boolean that tracks whether the link is connected
* [In] remoteDeviceType
* Tracks whether the remote device is switch/gpu/ibmnpu/tegra
* [In] remoteLinkNumber
* Tracks the link number for the connected remote device
*/
#define NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID (0x25U)
typedef struct NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS {
NV_DECLARE_ALIGNED(NvU64 remoteDeviceType, 8);
NV_DECLARE_ALIGNED(NvU64 remoteChipSid, 8);
NvU32 linkId;
NvU32 laneRxdetStatusMask;
NvU32 remoteLinkNumber;
NvU32 remotePciDeviceId;
NvU32 remoteDomain;
NvU8 remoteBus;
NvU8 remoteDevice;
NvU8 remoteFunction;
NvBool bConnected;
} NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_UPDATE_LINK_CONNECTION (0x20803025U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS_POST_TOPOLOGY
*
* Enable links post topology via GSP
*
* [In] linkMask
* Mask of links to enable
* [Out] initializedLinks
* Mask of links that were initialized
*/
#define NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID (0x26U)
typedef struct NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS {
NvU32 linkMask;
NvU32 initializedLinks;
} NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS_POST_TOPOLOGY (0x20803026U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI
*
* [In] linkMask
* Mask of enabled links to train
* [In] bSync
* The input sync boolean
*/
#define NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x27U)
typedef struct NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS {
NvU32 linkMask;
NvBool bSync;
} NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI (0x20803027U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
//
// Read Refresh counter - the pass/fail occurrences
//
@@ -2290,366 +2140,6 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS (0x20803029U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET
*
* Get link mask post Rx detection
*
* [Out] postRxDetLinkMask
* Mask of links discovered
* [Out] laneRxdetStatusMask
* RXDET per-lane status mask
*/
#define NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID (0x2aU)
typedef struct NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS {
NvU32 postRxDetLinkMask;
NvU32 laneRxdetStatusMask[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET (0x2080302aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI
*
* [In] linkMask
* Mask of enabled links to train
* [In] bSync
* The input sync boolean
*/
#define NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x2bU)
typedef struct NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS {
NvU32 linkMask;
NvBool bSync;
} NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI (0x2080302bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES {
NvBool bValid;
NvU8 linkId;
NvU32 ioctrlId;
NvU8 pllMasterLinkId;
NvU8 pllSlaveLinkId;
NvU32 ipVerDlPl;
} NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES;
/*
* NV2080_CTRL_CMD_NVLINK_GET_NVLINK_DEVICE_INFO
*
* [Out] ioctrlMask
* Mask of IOCTRLs discovered from PTOP device info table
* [Out] ioctrlNumEntries
* Number of IOCTRL entries in the PTOP device info table
* [Out] ioctrlSize
* Maximum number of entries in the PTOP device info table
* [Out] discoveredLinks
* Mask of links discovered from all the IOCTRLs
* [Out] ipVerNvlink
* IP revision of the NVLink HW
* [Out] linkInfo
* Per link information
*/
#define NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID (0x2cU)
typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS {
NvU32 ioctrlMask;
NvU8 ioctrlNumEntries;
NvU32 ioctrlSize;
NvU32 discoveredLinks;
NvU32 ipVerNvlink;
NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_DEVICE_INFO (0x2080302cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_MAX_LINKS_PER_IOCTRL_SW 6U
typedef struct NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES {
NvU32 ipVerIoctrl;
NvU32 ipVerMinion;
} NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES;
/*
* NV2080_CTRL_CMD_NVLINK_GET_IOCTRL_DEVICE_INFO
*
* [In] ioctrlIdx
* IOCTRL index
* [Out] PublicId
* PublicId of the IOCTRL discovered
* [Out] localDiscoveredLinks
* Mask of discovered links local to the IOCTRL
* [Out] localGlobalLinkOffset
* Global link offsets for the locally discovered links
* [Out] ioctrlDiscoverySize
* IOCTRL table size
* [Out] numDevices
* Number of devices discovered from the IOCTRL
* [Out] deviceIpRevisions
* IP revisions for the devices discovered in the IOCTRL
*/
#define NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x2dU)
typedef struct NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS {
NvU32 ioctrlIdx;
NvU32 PublicId;
NvU32 localDiscoveredLinks;
NvU32 localGlobalLinkOffset;
NvU32 ioctrlDiscoverySize;
NvU8 numDevices;
NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES ipRevisions;
} NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_IOCTRL_DEVICE_INFO (0x2080302dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_PROGRAM_LINK_SPEED
*
* Program NVLink Speed from OS/VBIOS
*
* [In] bPlatformLinerateDefined
* Whether line rate is defined in the platform
* [In] platformLineRate
* Platform defined line rate
* [Out] nvlinkLinkSpeed
* The line rate that was programmed for the links
*/
#define NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID (0x2eU)
typedef struct NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS {
NvBool bPlatformLinerateDefined;
NvU32 platformLineRate;
NvU32 nvlinkLinkSpeed;
} NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PROGRAM_LINK_SPEED (0x2080302eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED
*
* [In] linkMask
* Mask of links whose state will be checked
* [In] bActiveOnly
* The input boolean to check for Link Active state
* [Out] bIsLinkActive
* Boolean array to track if the link is trained
*/
#define NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID (0x2fU)
typedef struct NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS {
NvU32 linkMask;
NvBool bActiveOnly;
NvBool bIsLinkActive[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED (0x2080302fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_RESET_FLAGS_ASSERT (0x00000000)
#define NV2080_CTRL_NVLINK_RESET_FLAGS_DEASSERT (0x00000001)
#define NV2080_CTRL_NVLINK_RESET_FLAGS_TOGGLE (0x00000002)
/*
* NV2080_CTRL_CMD_NVLINK_RESET_LINKS
*
* [In] linkMask
* Mask of links which need to be reset
* [In] flags
* Whether to assert, de-assert or toggle the Nvlink reset
*/
#define NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID (0x30U)
typedef struct NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS {
NvU32 linkMask;
NvU32 flags;
} NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_RESET_LINKS (0x20803030U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_DISABLE_DL_INTERRUPTS
*
* [In] linkMask
* Mask of links for which DL interrrupts need to be disabled
*/
#define NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID (0x31U)
typedef struct NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS {
NvU32 linkMask;
} NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_DISABLE_DL_INTERRUPTS (0x20803031U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID" */
/*
* Structure to store the GET_LINK_AND_CLOCK__INFO params
*
* [Out] bLinkConnectedToSystem
* Boolean indicating sysmem connection of a link
* [Out] bLinkConnectedToPeer
* Boolean indicating peer connection of a link
* [Out] bLinkReset
* Whether the link is in reset
* [Out] subLinkWidth
* Number of lanes per sublink
* [Out] linkState
* Mode of the link
* [Out] txSublinkState
* Tx sublink state
* [Out] rxSublinkState
* Rx sublink state
* [Out] bLaneReversal
* Boolean indicating if a link's lanes are reversed
* [Out] nvlinkLinkClockKHz
* Link clock value in KHz
* [Out] nvlinkLineRateMbps
* Link line rate in Mbps
* [Out] nvlinkLinkClockMhz
* Link clock in MHz
* [Out] nvlinkLinkDataRateKiBps
* Link Data rate in KiBps
* [Out] nvlinkRefClkType
* Current Nvlink refclk source
* [Out] nvlinkReqLinkClockMhz
* Requested link clock value
* [Out] nvlinkMinL1Threshold
* Requested link Min L1 Threshold
* [Out] nvlinkMaxL1Threshold
* Requested link Max L1 Threshold
* [Out] nvlinkL1ThresholdUnits
* Requested link L1 Threshold Units
*/
typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES {
NvBool bLinkConnectedToSystem;
NvBool bLinkConnectedToPeer;
NvBool bLinkReset;
NvU8 subLinkWidth;
NvU32 linkState;
NvU32 txSublinkState;
NvU32 rxSublinkState;
NvBool bLaneReversal;
NvU32 nvlinkLinkClockKHz;
NvU32 nvlinkLineRateMbps;
NvU32 nvlinkLinkClockMhz;
NvU32 nvlinkLinkDataRateKiBps;
NvU8 nvlinkRefClkType;
NvU32 nvlinkReqLinkClockMhz;
NvU32 nvlinkMinL1Threshold;
NvU32 nvlinkMaxL1Threshold;
NvU32 nvlinkL1ThresholdUnits;
} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES;
/*
* NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO
*
* [In] linkMask
* Mask of enabled links to loop over
* [Out] nvlinkRefClkSpeedKHz
* Ref clock value n KHz
* [Out] linkInfo
* Per link information
*/
#define NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID (0x32U)
typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS {
NvU32 linkMask;
NvU32 nvlinkRefClkSpeedKHz;
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO (0x20803032U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_SETUP_NVLINK_SYSMEM
*
* Updates the HSHUB sysmem config resgister state to reflect sysmem NVLinks
*
* [In] sysmemLinkMask
* Mask of discovered sysmem NVLinks
*/
#define NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID (0x33U)
typedef struct NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS {
NvU32 sysmemLinkMask;
} NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SETUP_NVLINK_SYSMEM (0x20803033U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_PROCESS_FORCED_CONFIGS
*
* Process NVLink forced configurations which includes setting of HSHUB and memory system
*
* [In] bLegacyForcedConfig
* Tracks whether the forced config is legacy forced config or chiplib config
* [Out] bOverrideComputePeerMode
* Whether compute peer mode was enabled
* [In] phase
* Only applicable when bLegacyForcedConfig is true
* Tracks the set of registers to program from the NVLink table
* [In] linkConnection
* Array of chiplib configurations
*/
#define NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID (0x34U)
typedef struct NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS {
NvBool bLegacyForcedConfig;
NvBool bOverrideComputePeerMode;
NvU32 phase;
NvU32 linkConnection[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PROCESS_FORCED_CONFIGS (0x20803034U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS
*
* Sync the NVLink lane shutdown properties with GSP-RM
*
* [In] bLaneShutdownOnUnload
* Whether nvlink shutdown should be triggered on driver unload
*/
#define NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID (0x35U)
typedef struct NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS {
NvBool bLaneShutdownOnUnload;
} NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS (0x20803035U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_ENABLE_SYSMEM_NVLINK_ATS
*
* Enable ATS functionality related to NVLink sysmem if hardware support is available
*
* [In] notUsed
*/
#define NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID (0x36U)
typedef struct NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS {
NvU32 notUsed;
} NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_ENABLE_SYSMEM_NVLINK_ATS (0x20803036U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK
*
* Get the mask of Nvlink links connected to system
*
* [Out] sysmemLinkMask
* Mask of Nvlink links connected to system
*/
#define NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID (0x37U)
typedef struct NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
NvU32 sysmemLinkMask;
} NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20803037U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR
*
@@ -2707,12 +2197,12 @@ typedef struct NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS {
#define NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID (0x39U)
typedef struct NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS {
NvU32 discoveredLinks;
NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8);
NvU32 connectedLinksMask;
NvU32 bridgeSensableLinks;
NV_DECLARE_ALIGNED(NvU64 bridgeSensableLinks, 8);
NvU32 bridgedLinks;
NvU32 initDisabledLinksMask;
NvU32 vbiosDisabledLinkMask;
NV_DECLARE_ALIGNED(NvU64 vbiosDisabledLinkMask, 8);
NvU32 initializedLinks;
NvBool bEnableTrainingAtLoad;
NvBool bEnableSafeModeAtLoad;
@@ -3340,7 +2830,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS {
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 plane_ind;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
@@ -3362,7 +2851,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS {
NvBool sw;
NvBool dm_ig;
NvBool p;
NvBool tun_ovr;
NvBool s;
NvBool e;
NvU8 modulation;
@@ -3546,7 +3034,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS {
NvU8 critical_inactive_time;
NvU8 critical_active_time;
NvBool cc;
NvU16 queue_depth_th;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR (0x2080307dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID" */
@@ -3745,6 +3232,127 @@ typedef struct NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS {
NvU8 rbmMode;
} NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO
*
* localDeviceInfo
* NVLINK-relevant information about the device
*/
#define NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO (0x20803088U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x88U)
typedef struct NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO localDeviceInfo, 8);
} NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR
*
* This command is used to inject NVL5 ERROR_INJECT_V2 commands
*
* [out]
* Error Types to be injected
*
* Possible status values returned are:
* NV_OK
* If the Error is injected successfully
* NV_ERR_NOT_SUPPORTED
* If NVLINK is not supported on the chip
* NV_ERR_INVALID_ARGUMENT
* If the link is not enabled on the GPU
* NV_ERR_INVALID_STATE
* If the link is in an invalid state
*/
#define NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR (0x20803089U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY {
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL = 0,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL = 1,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL = 2,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION = 3,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT = 4,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL = 5,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE = 6,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL = 7,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL = 8,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR = 9,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL = 10,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL = 11,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL = 12,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL = 13,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL = 14,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL = 15,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL = 16,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL = 17,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL = 18,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL = 19,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL = 20,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = 21,
} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY;
#define NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS {
NvU32 linkMask;
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY severity;
} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY
*
* Signal to GSP that lazy error recovery can proceed.
*/
#define NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY (0x2080308aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x8A" */
/*
* NV2080_CTRL_CMD_SET_NVLINK_CONFIGURE_L1_TOGGLE
*
* This command configures the nvlink L1 toggle pattern
*
* Commands returns SUCCESS only when it successfully sets value of all
* parameter in the list.
*
* Possible status return values are:
* NV_OK
*
* Reference:
*
*/
#define NV2080_CTRL_CMD_NVLINK_CONFIGURE_L1_TOGGLE (0x2080308eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE {
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED = 0,
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE = 1,
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED = 2,
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED = 3,
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE = 4,
} NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE;
typedef struct NV2080_CTRL_NVLINK_L1_FORCE_CONFIG {
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE mode;
NvU8 toggleActiveTime;
NvU8 toggleInactiveTime;
NvBool bTrigger;
} NV2080_CTRL_NVLINK_L1_FORCE_CONFIG;
#define NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID (0x8EU)
typedef struct NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS {
NvU32 linkMask;
NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config;
} NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_L1_TOGGLE (0x2080308fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID (0x8FU)
typedef struct NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS {
NvU32 linkMask;
NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS;
/* _ctrl2080nvlink_h_ */

20
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -471,6 +471,12 @@ typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE {
* the sample was taken. If no process is active then NULL will be returned.
*/
char subProcessName[NV_SUBPROC_NAME_MAX_LENGTH];
/*!
* PID struct pointer of the process that was active on the engine when the
* the sample was taken. If no process is active then NULL pointer
* will be returned
*/
NV_DECLARE_ALIGNED(NvU64 pOsPidInfo, 8);
} NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE;
/*!
@@ -484,27 +490,27 @@ typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE {
/*!
* FB bandwidth utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb;
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb, 8);
/*!
* GR utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr;
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr, 8);
/*!
* NV ENCODER utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc;
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc, 8);
/*!
* NV DECODER utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec;
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec, 8);
/*!
* NV JPEG utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvjpg;
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvjpg, 8);
/*!
* NV OFA utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvofa;
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvofa, 8);
} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE;
/*!

18
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
View File

@@ -458,4 +458,22 @@ typedef struct NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS {
NvBool bFlrDisabled;
} NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE
*
* This command will set heterogenous mode in GSP RM
*
* bHeterogeneousMode
* Mode of heterogeneous
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE (0x2080400e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
NvBool bHeterogeneousMode;
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS;
/* _ctrl2080vgpumgrinternal_h_ */

24
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffifo.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -64,28 +64,6 @@ typedef struct NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS {
NvBool exists;
} NV208F_CTRL_FIFO_CHECK_ENGINE_CONTEXT_PARAMS;
/*
* NV208F_CTRL_CMD_FIFO_ENABLE_VIRTUAL_CONTEXT
*
* This command enables virtual context for a given channel (for all engines).
* This API is intended for testing virtual context. For debug only.
*
* hChannel
* The handle to the channel.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_DEVICE
* NV_ERR_INVALID_CHANNEL
*/
#define NV208F_CTRL_CMD_FIFO_ENABLE_VIRTUAL_CONTEXT (0x208f0402) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FIFO_INTERFACE_ID << 8) | NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS {
NvHandle hChannel;
} NV208F_CTRL_FIFO_ENABLE_VIRTUAL_CONTEXT_PARAMS;
/*
* NV208F_CTRL_CMD_FIFO_GET_CHANNEL_STATE
*

35
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2010-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -135,4 +135,37 @@ typedef struct NV208F_CTRL_GR_ECC_SET_TRANSIENT_CLEARING_POLICY_PARAMS {
NvU32 policy;
} NV208F_CTRL_GR_ECC_SET_TRANSIENT_CLEARING_POLICY_PARAMS;
/*
* NV208F_CTRL_CMD_GR_INJECT_CTXSW_UCODE_ERROR
*
* Control command to inject a CTXSW ucode error
*
* Parameters:
*
* errorType
* Warning, Partial GR Reset, Full GR Reset, or GPU Reset
*
* errorMethod
* Main, Firmware, or Sideband error
*
* bInjectGpccs
* TRUE - inject into GPCCS
* FALSE - inject into FECS
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV208F_CTRL_CMD_GR_INJECT_CTXSW_UCODE_ERROR (0x208f1206) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID << 8) | NV208F_CTRL_GR_INJECT_CTXSW_UCODE_ERROR_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_GR_INJECT_CTXSW_UCODE_ERROR_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV208F_CTRL_GR_INJECT_CTXSW_UCODE_ERROR_PARAMS {
NvU32 errorType;
NvU32 errorMethod;
NvBool bInjectGpccs;
} NV208F_CTRL_GR_INJECT_CTXSW_UCODE_ERROR_PARAMS;
/* _ctrl208fgr_h_ */

10
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fucodecoverage.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -38,6 +38,9 @@
#define NV208F_UCODE_COVERAGE_GSP_TASK_RM 3
#define NV208F_UCODE_COVERAGE_GSP_TASK_VGPU 4
/* Coverage Type */
#define NV208F_SANITIZER_COVERAGE_TYPE 0
#define NV208F_BULLSEYE_COVERAGE_TYPE 1
/*
* NV208F_CTRL_UCODE_COVERAGE_STATE_PARAMS
@@ -51,6 +54,7 @@ typedef struct NV208F_CTRL_UCODE_COVERAGE_STATE_PARAMS {
NvU32 gfid;
NvBool bEnabled;
NvBool bClear;
NvU32 covType;
} NV208F_CTRL_UCODE_COVERAGE_STATE_PARAMS;
/*
@@ -63,6 +67,7 @@ typedef struct NV208F_CTRL_UCODE_COVERAGE_STATE_PARAMS {
* (applies to ucode=NV208F_UCODE_COVERAGE_GSP_TASK_VGPU only)
* bEnabled whether the ucode's SanitizerCoverage run-time data gathering
* is enabled (NV_TRUE) or not (NV_FALSE)
* covType determines if using SanitizerCoverage or BullseyeCoverage
*
* Possible status values returned are
* NV_OK
@@ -85,6 +90,7 @@ typedef NV208F_CTRL_UCODE_COVERAGE_STATE_PARAMS NV208F_CTRL_UCODE_COVERAGE_GET_S
* (applies to ucode=NV208F_UCODE_COVERAGE_GSP_TASK_VGPU only)
* bEnabled whether to enable (NV_TRUE) or disable (NV_FALSE) coverage for the given ucode
* bClear whether to clear coverage prior to enabling enabling coverage collection
* covType determines if using SanitizerCoverage or BullseyeCoverage
*
* Possible status values returned are
* NV_OK
@@ -117,6 +123,7 @@ typedef NV208F_CTRL_UCODE_COVERAGE_STATE_PARAMS NV208F_CTRL_UCODE_COVERAGE_SET_S
* gfid specifies which partition to send the command to
* (applies to ucode=NV208F_UCODE_FUZZER_GSP_TASK_VGPU only)
* offset offset of internal buffer to copy from
* covType determines if using SanitizerCoverage or BullseyeCoverage
*
* Possible status values returned are
* NV_OK
@@ -132,6 +139,7 @@ typedef struct NV208F_CTRL_UCODE_COVERAGE_GET_DATA_PARAMS {
NvU32 ucode;
NvU32 gfid;
NvU32 offset;
NvU32 covType;
} NV208F_CTRL_UCODE_COVERAGE_GET_DATA_PARAMS;
/* _ctrl208fucodecoverage_h_ */

4
src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1167,7 +1167,7 @@ typedef struct NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS {
NvU32 vInterlacedBlankStart;
NvU32 vTotal;
NvU32 refreshX10K;
NvU32 pixelClockHz;
NV_DECLARE_ALIGNED(NvU64 pixelClockHz, 8);
NvBool bOptimized;
} NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS;

143
src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070event.h
View File

@@ -1,143 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl5070/ctrl5070event.finn
//
#include "ctrl/ctrl5070/ctrl5070base.h"
/* NV50_DISPLAY event-related control commands and parameters */
/*
* NV5070_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* This command sets event notification state for the NV50_DISPLAY object.
* This command requires that an instance of NV01_EVENT has been previously
* bound to the NV50_DISPLAY object.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the NV50_DISPLAY
* parent device to which the operation should be directed. This parameter
* must specify a value between zero and the total number of subdevices
* within the parent device. This parameter should be set to zero for
* default behavior.
* hEvent
* This parameter specifies the handle of the NV01_EVENT instance
* to be bound to the given subDeviceInstance.
* event
* This parameter specifies the type of event to which the specified
* action is to be applied. This parameter must specify a valid
* NOTIFIERS value of display class.
* action
* This parameter specifies the desired event notification action.
* Valid notification actions include:
* NV5070_CTRL_SET_EVENT_NOTIFICATION_DISABLE
* This action disables event notification for the specified
* event for the associated subdevice object.
* NV5070_CTRL_SET_EVENT_NOTIFICATION_SINGLE
* This action enables single-shot event notification for the
* specified event for the associated subdevice object.
* NV5070_CTRL_SET_EVENT_NOTIFICATION_REPEAT
* This action enables repeated event notification for the specified
* event for the associated system controller object.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV5070_CTRL_CMD_EVENT_SET_NOTIFICATION (0x50700901) /* finn: Evaluated from "(FINN_NV50_DISPLAY_EVENT_INTERFACE_ID << 8) | NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
NvU32 subDeviceInstance;
NvHandle hEvent;
NvU32 event;
NvU32 action;
} NV5070_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000)
#define NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001)
#define NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
/*
* NV5070_CTRL_CMD_EVENT_SET_TRIGGER
*
* This command triggers a software event for the NV50_DISPLAY object.
* This command accepts no parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV5070_CTRL_CMD_EVENT_SET_TRIGGER (0x50700902) /* finn: Evaluated from "(FINN_NV50_DISPLAY_EVENT_INTERFACE_ID << 8) | 0x2" */
/*
* NV5070_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY
*
* hMemory
* This parameter specifies the handle of the memory object
* that identifies the memory address translation for this
* subdevice instance's notification(s). The beginning of the
* translation points to an array of notification data structures.
* The size of the translation must be at least large enough to hold the
* maximum number of notification data structures.
* Legal argument values must be instances of the following classes:
* NV01_NULL
* NV04_MEMORY
* When hMemory specifies the NV01_NULL_OBJECT value then any existing
* memory translation connection is cleared. There must not be any
* pending notifications when this command is issued.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV5070_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x50700903) /* finn: Evaluated from "(FINN_NV50_DISPLAY_EVENT_INTERFACE_ID << 8) | NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS {
NvU32 subDeviceInstance;
NvHandle hMemory;
} NV5070_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS;
#define NV5070_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0
#define NV5070_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1
#define NV5070_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2
/* _ctrl5070event_h_ */

73
src/common/sdk/nvidia/inc/ctrl/ctrl83de/ctrl83dedebug.h
View File

@@ -1157,5 +1157,78 @@ typedef struct NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS {
NvBool bDropDeferredRc;
} NV83DE_CTRL_DEBUG_SET_DROP_DEFERRED_RC_PARAMS;
/*
* NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG
*
* This command sets the MMU GCC DEBUG mode. This is Blackwell-onwards feature.
* If the query is made on an incorrect platform (for example, pre-Blackwell)
* the call will return with an NV_ERR_NOT_SUPPORTED error.
*
* action
* The possible action values are:
* - NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_ENABLE
* This enables the MMU GCC debug mode if possible. If however, any another
* client has already disabled the mode (via NV83DE call) then this
* operation returns NV_ERR_STATE_IN_USE.
*
* - NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_DISABLE
* This disables the MMU GCC debug mode if possible. If however, any another
* client has already enabled the mode (via NV83DE call) then this
* operation returns NV_ERR_STATE_IN_USE.
*
* - NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_GCC_DEBUG_REQUESTS
* This operation releases all the client's outstanding requests to enable
* or disable the MMU debug mode.
*
* Possible return values:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_CLIENT
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG (0x83de032a) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID" */
#define NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID (0x2AU)
typedef struct NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS {
NvU32 action;
} NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS;
#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_ENABLE (0x00000001)
#define NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_GCC_DEBUG_DISABLE (0x00000002)
#define NV83DE_CTRL_CMD_DEBUG_RELEASE_MMU_GCC_DEBUG_REQUESTS (0x00000003)
/*
* NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG
*
* This command gets the value of currently configured MMU GCC DEBUG mode.
* This is Blackwell-onwards feature. If the query is made on an incorrect
* platform (for example, pre-Blackwell) the call will return with an
* NV_ERR_NOT_SUPPORTED error.
*
* value
* This parameter returns the configured value.
*
* Possible return values:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_CLIENT
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG (0x83de032b) /* finn: Evaluated from "(FINN_GT200_DEBUGGER_DEBUG_INTERFACE_ID << 8) | NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID" */
#define NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_MESSAGE_ID (0x2BU)
typedef struct NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS {
NvU32 value;
} NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS;
#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_ENABLED (0x00000001)
#define NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_GCC_DEBUG_DISABLED (0x00000002)
/* _ctrl83dedebug_h_ */

24
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
View File

@@ -124,8 +124,10 @@ typedef struct NVA081_CTRL_VGPU_INFO {
// used only by NVML
NvU32 gpuInstanceProfileId;
NvU32 placementSize;
NvU32 placementCount;
NvU32 placementIds[NVA081_MAX_VGPU_PER_PGPU];
NvU32 homogeneousPlacementCount;
NvU32 homogeneousPlacementIds[NVA081_MAX_VGPU_PER_PGPU];
NvU32 heterogeneousPlacementCount;
NvU32 heterogeneousPlacementIds[NVA081_MAX_VGPU_PER_PGPU];
} NVA081_CTRL_VGPU_INFO;
/*
@@ -730,10 +732,11 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS {
} NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO
* NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PLACEMENT_INFO
*
* This command is used to get a placement Id from RM for timesliced
* heterogeneous vGPUs.
* heterogeneous or homogeneous vGPUs. The physical GPU shall be used
* in either heterogeneous or homogeneous mode at a time.
*
* isHeterogeneousEnabled [OUT]
* This param specific whether timesliced heterogeneous vGPU is enabled
@@ -746,6 +749,9 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS {
* vgpuTypeId [IN]
* This param specifies the Type ID for VGPU profile
*
* vgpuDevName [IN]
* This param specifies the VF BDF of the virtual GPU.
*
* guestFbLength [OUT]
* This param specifies the FB size assigned to the VM.
*
@@ -765,19 +771,20 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS {
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*/
#define NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO (0xa081011b) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PLACEMENT_INFO (0xa081011b) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_UPDATE_PLACEMENT_INFO_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS_MESSAGE_ID (0x1bU)
#define NVA081_CTRL_VGPU_CONFIG_UPDATE_PLACEMENT_INFO_PARAMS_MESSAGE_ID (0x1bU)
typedef struct NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS {
typedef struct NVA081_CTRL_VGPU_CONFIG_UPDATE_PLACEMENT_INFO_PARAMS {
NvBool isHeterogeneousEnabled;
NvU16 placementId;
NvU32 vgpuTypeId;
NvU8 vgpuDevName[VM_UUID_SIZE];
NV_DECLARE_ALIGNED(NvU64 guestFbLength, 8);
NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8);
NV_DECLARE_ALIGNED(NvU64 gspHeapOffset, 8);
NV_DECLARE_ALIGNED(NvU64 guestBar1PFOffset, 8);
} NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS;
} NVA081_CTRL_VGPU_CONFIG_UPDATE_PLACEMENT_INFO_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS
@@ -846,6 +853,7 @@ typedef struct NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS {
#define NVA081_CTRL_VGPU_CAPABILITY_HETEROGENEOUS_TIMESLICE_SIZES 6
#define NVA081_CTRL_VGPU_CAPABILITY_HETEROGENEOUS_TIMESLICE_PROFILES 7
#define NVA081_CTRL_VGPU_CAPABILITY_FRACTIONAL_MULTI_VGPU 8
#define NVA081_CTRL_VGPU_CAPABILITY_HOMOGENEOUS_PLACEMENT_ID 9
/*
* NVA081_CTRL_CMD_VGPU_SET_CAPABILITY

28
src/common/sdk/nvidia/inc/ctrl/ctrla084.h
View File

@@ -356,4 +356,32 @@ typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK_PARAMS {
NvBool bDeviceProfilingEnabled;
} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_BOOTLOAD_VGPU_TASK_PARAMS;
/*
* NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_PLACEMENT_ID
*
* This command will set the placementId and reserve system channel Ids
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_CLIENT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_NOT_SUPPORTED
*
* Parameters:
* numChannels -> Used only when SRIOV is enabled.
* placementId -> Used to provide placement Id of vGPU device with heterogeneous timesliced vGPUs.
* Also Ada onwards for Homogeneous GPUs as well.
* Otherwise set to NVA081_PLACEMENT_ID_INVALID.
*/
#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_PLACEMENT_ID (0xa084010e) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_PLACEMENT_ID_PARAMS_MESSAGE_ID" */
#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_PLACEMENT_ID_PARAMS_MESSAGE_ID (0xEU)
typedef struct NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_PLACEMENT_ID_PARAMS {
NvU32 numChannels;
NvU16 placementId;
} NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_SET_PLACEMENT_ID_PARAMS;
/* _ctrla084_h_ */

8
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -129,11 +129,17 @@ typedef struct NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS {
* [in] Is Admin profiling permitted
*/
NvBool bAdminProfilingPermitted;
/*!
* [in] Is Device profiling permitted
*/
NvBool bDevProfilingPermitted;
/*!
* [in] Is Context profiling permitted
*/
NvBool bCtxProfilingPermitted;
/*!
* [in] Is Video memory profiling permitted
*/

23
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h
View File

@@ -682,5 +682,28 @@ typedef struct NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS {
} NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS;
/*!
* NVB0CC_CTRL_CMD_RESERVE_CCU_PROF
*
* Reserves CCU Prof resource for use by the calling client.
* This CCU prof resource will be accessible only if this reservation is
* taken.
*
* This reservation can be released with @ref NVB0CC_CTRL_CMD_RELEASE_CCU_PROF.
*
*/
#define NVB0CC_CTRL_CMD_RESERVE_CCU_PROF (0xb0cc0119) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS_MESSAGE_ID (0x19U)
typedef struct NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS {
/*!
* [in] Enable ctxsw for CCU prof.
*/
NvBool ctxsw;
} NVB0CC_CTRL_RESERVE_CCUPROF_PARAMS;
#define NVB0CC_CTRL_CMD_RELEASE_CCU_PROF (0xb0cc011a) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | 0x1a" */
/* _ctrlb0ccprofiler_h_ */

11
src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370event.h
View File

@@ -31,16 +31,15 @@
//
#include "ctrl/ctrlc370/ctrlc370base.h"
/* C370 is partially derived from 5070 */
#include "ctrl/ctrl5070/ctrl5070event.h"
/* C370 is partially derived from 0073 */
#include "ctrl/ctrl0073/ctrl0073event.h"
/* valid action values */
#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE
#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE
#define NVC370_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT
/* _ctrlc370event_h_ */

52
src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370or.h
View File

@@ -37,5 +37,57 @@
#include "ctrl/ctrl5070/ctrl5070or.h"
//
// NVC370_CTRL_CMD_SET_SOR_FLUSH_MODE
//
// This command is used enable/disable flush mode on all the heads attached to the SOR
// [in] subDeviceInstance
// This parameter specifies the subdevice instance within the
// NV04_DISPLAY_COMMON parent device to which the operation should be
// directed. This parameter must specify a value between zero and the
// total number of subdevices within the parent device. This parameter
// should be set to zero for default behavior.
// [in] sorNumber
// All heads connected to this SOR will be programmed
// [in] headIndex
// Phase 1 flush exit programs SF_DP_LINKCTL for each head separately
// [in] attachFailedHeadMask
// Head mask for the heads where add stream failed
// [in] phase
// Flush has 2 Phases (Broad overview):
// - For Entry
// - Phase 1: Set core to debug, disable AUDIO and HDCP and engage flush
// - Phase 2: Disable SOR and SF
// - For Exit
// - Phase 1: Program SF for each stream
// - Phase 2: Exit flush, enable AUDIO and HDCP and disengage flush
// This design allows interleaving add/delete MST information in-between them
// [in] bEnable
// Whether to enable/disable flush
// Possible return values:
// NV_OK
// NV_ERR_NOT_SUPPORTED
//
#define NVC370_CTRL_CMD_SET_SOR_FLUSH_MODE (0xc3700401U) /* finn: Evaluated from "(FINN_NVC370_DISPLAY_OR_INTERFACE_ID << 8) | NVC370_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID" */
#define NVC370_CTRL_SET_SOR_FLUSH_MODE_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVC370_CTRL_SET_SOR_FLUSH_MODE_PARAMS {
NvU32 subDeviceInstance;
NvU32 sorNumber;
NvU32 headIndex;
NvU32 attachFailedHeadMask;
NvU8 phase;
NvBool bEnable;
} NVC370_CTRL_SET_SOR_FLUSH_MODE_PARAMS;
/* _ctrlc370or_h_ */
#define NVC370_CTRL_SET_SOR_FLUSH_RUN 1:0
#define NVC370_CTRL_SET_SOR_FLUSH_RUN_PHASE_INVALID (0x00000000U)
#define NVC370_CTRL_SET_SOR_FLUSH_RUN_PHASE1 (0x00000001U)
#define NVC370_CTRL_SET_SOR_FLUSH_RUN_PHASE2 (0x00000002U)

3
src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h
View File

@@ -361,8 +361,7 @@
* This output is returned for each head and suggests to the clients
* if the mode will be possible or not on that head when OSLD is enabled.
* The output is only valid if bGetOSLDOutput is set in the head input.
* Note that with OSLD output, RM will also return the legacy output
* values.
* Note that bIsOSLDPossible is only valid if bIsPossible is true.
*
* minImpVPState
* minImpVPState returns the minimum v-pstate at which the mode is possible

61
src/common/sdk/nvidia/inc/ctrl/ctrlca6f.h Normal file
View File

@@ -0,0 +1,61 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlca6f.finn
//
#include "nvcfg_sdk.h"
/* BLACKWELL_CHANNEL_GPFIFO_B control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
#define NVCA6F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xC36F, NVCA6F_CTRL_##cat, idx)
/* BLACKWELL_CHANNEL_GPFIFO_B command categories (6bits) */
#define NVCA6F_CTRL_RESERVED (0x00)
#define NVCA6F_CTRL_GPFIFO (0x01)
#define NVCA6F_CTRL_EVENT (0x02)
/*
* NVCA6F_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned is: NV_OK
*/
#define NVCA6F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL)

4
src/common/sdk/nvidia/inc/g_finn_rm_api.h
View File

@@ -473,8 +473,6 @@ typedef FINN_RM_API FINN_NV50_CHANNEL_GPFIFO_GPFIFO;
typedef FINN_RM_API FINN_NV50_DISPLAY_RESERVED;
#define FINN_NV50_DISPLAY_CHNCTL_INTERFACE_ID (0x507001U)
typedef FINN_RM_API FINN_NV50_DISPLAY_CHNCTL;
#define FINN_NV50_DISPLAY_EVENT_INTERFACE_ID (0x507009U)
typedef FINN_RM_API FINN_NV50_DISPLAY_EVENT;
#define FINN_NV50_DISPLAY_OR_INTERFACE_ID (0x507004U)
typedef FINN_RM_API FINN_NV50_DISPLAY_OR;
#define FINN_NV50_DISPLAY_RG_INTERFACE_ID (0x507002U)
@@ -719,6 +717,8 @@ typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER;
typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_BLACKWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc96f00U)
typedef FINN_RM_API FINN_BLACKWELL_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_BLACKWELL_CHANNEL_GPFIFO_B_RESERVED_INTERFACE_ID (0xca6f00U)
typedef FINN_RM_API FINN_BLACKWELL_CHANNEL_GPFIFO_B_RESERVED;
#define FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED_INTERFACE_ID (0xcb3300U)
typedef FINN_RM_API FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED;

4
src/common/sdk/nvidia/inc/nvdump.h
View File

@@ -71,11 +71,11 @@ typedef enum
NVDUMP_COMPONENT_ENG_CLK,
NVDUMP_COMPONENT_ENG_SEC2,
NVDUMP_COMPONENT_ENG_NVLINK,
NVDUMP_COMPONENT_ENG_BSP,
NVDUMP_COMPONENT_ENG_NVDEC,
NVDUMP_COMPONENT_ENG_DPU,
NVDUMP_COMPONENT_ENG_FBFLCN,
NVDUMP_COMPONENT_ENG_HDA,
NVDUMP_COMPONENT_ENG_MSENC,
NVDUMP_COMPONENT_ENG_NVENC,
NVDUMP_COMPONENT_ENG_GSP,
NVDUMP_COMPONENT_ENG_INFOROM,
NVDUMP_COMPONENT_ENG_GCX,

26
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -134,6 +134,8 @@
#define ROBUST_CHANNEL_OFA1_ERROR (139)
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)
#define ROBUST_CHANNEL_FAST_PATH_ERROR (141)
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define ROBUST_CHANNEL_NVENC3_ERROR (142)
#define GPU_INIT_ERROR (143)
#define NVLINK_SAW_ERROR (144)
#define NVLINK_RLW_ERROR (145)
@@ -146,7 +148,8 @@
#define RESERVED7_ERROR (152)
#define RESERVED8_ERROR (153)
#define GPU_RECOVERY_ACTION_CHANGED (154)
#define ROBUST_CHANNEL_LAST_ERROR (154)
#define NVLINK_SW_DEFINED_ERROR (155)
#define ROBUST_CHANNEL_LAST_ERROR (157)
// Indexed CE reference
@@ -214,22 +217,27 @@
(x - ROBUST_CHANNEL_NVDEC5_ERROR + 5))))
// Indexed NVENC reference
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define ROBUST_CHANNEL_NVENC_ERROR(x) \
((x == 0) ? (ROBUST_CHANNEL_NVENC0_ERROR) : \
((x == 1) ? (ROBUST_CHANNEL_NVENC1_ERROR) : \
(ROBUST_CHANNEL_NVENC2_ERROR)))
((x == 2) ? (ROBUST_CHANNEL_NVENC2_ERROR) : \
(ROBUST_CHANNEL_NVENC3_ERROR))))
#define ROBUST_CHANNEL_IS_NVENC_ERROR(x) \
((x == ROBUST_CHANNEL_NVENC0_ERROR) || \
(x == ROBUST_CHANNEL_NVENC1_ERROR) || \
(x == ROBUST_CHANNEL_NVENC2_ERROR))
(x == ROBUST_CHANNEL_NVENC2_ERROR) || \
(x == ROBUST_CHANNEL_NVENC3_ERROR))
#define ROBUST_CHANNEL_NVENC_ERROR_IDX(x) \
(((x == ROBUST_CHANNEL_NVENC0_ERROR)) ? \
(x - ROBUST_CHANNEL_NVENC0_ERROR) : \
(((x == ROBUST_CHANNEL_NVENC1_ERROR)) ? \
(x - ROBUST_CHANNEL_NVENC1_ERROR + 1) : \
(x - ROBUST_CHANNEL_NVENC2_ERROR + 2)))
#define ROBUST_CHANNEL_NVENC_ERROR_IDX(x) \
((x == ROBUST_CHANNEL_NVENC0_ERROR) ? \
(x - ROBUST_CHANNEL_NVENC0_ERROR) : \
((x == ROBUST_CHANNEL_NVENC1_ERROR) ? \
(x - ROBUST_CHANNEL_NVENC1_ERROR + 1) : \
((x == ROBUST_CHANNEL_NVENC2_ERROR) ? \
(x - ROBUST_CHANNEL_NVENC2_ERROR + 2) : \
(x - ROBUST_CHANNEL_NVENC3_ERROR + 3))))
// Indexed NVJPG reference
#define ROBUST_CHANNEL_NVJPG_ERROR(x) \

48
src/common/sdk/nvidia/inc/nvmisc.h
View File

@@ -33,38 +33,18 @@ extern "C" {
#include "nvtypes.h"
#if !defined(NVIDIA_UNDEF_LEGACY_BIT_MACROS)
//
// Miscellaneous macros useful for bit field manipulations
//
// STUPID HACK FOR CL 19434692. Will revert when fix CL is delivered bfm -> chips_a.
#ifndef BIT
#define BIT(b) (1U<<(b))
#endif
#ifndef BIT32
#define BIT32(b) ((NvU32)1U<<(b))
#endif
#ifndef BIT64
#define BIT64(b) ((NvU64)1U<<(b))
#endif
#endif
//
// It is recommended to use the following bit macros to avoid macro name
// collisions with other src code bases.
//
// Miscellaneous macros useful for bit field manipulations.
#ifndef NVBIT
#define NVBIT(b) (1U<<(b))
#define NVBIT(b) (1U<<(b))
#endif
#ifndef NVBIT_TYPE
#define NVBIT_TYPE(b, t) (((t)1U)<<(b))
#define NVBIT_TYPE(b, t) (((t)1U)<<(b))
#endif
#ifndef NVBIT32
#define NVBIT32(b) NVBIT_TYPE(b, NvU32)
#define NVBIT32(b) NVBIT_TYPE(b, NvU32)
#endif
#ifndef NVBIT64
#define NVBIT64(b) NVBIT_TYPE(b, NvU64)
#define NVBIT64(b) NVBIT_TYPE(b, NvU64)
#endif
//Concatenate 2 32bit values to a 64bit value
@@ -72,7 +52,7 @@ extern "C" {
// Helper macro's for 32 bit bitmasks
#define NV_BITMASK32_ELEMENT_SIZE (sizeof(NvU32) << 3)
#define NV_BITMASK32_IDX(chId) (((chId) & ~(0x1F)) >> 5)
#define NV_BITMASK32_IDX(chId) (((chId) & ~(0x1F)) >> 5)
#define NV_BITMASK32_OFFSET(chId) ((chId) & (0x1F))
#define NV_BITMASK32_SET(pChannelMask, chId) \
(pChannelMask)[NV_BITMASK32_IDX(chId)] |= NVBIT(NV_BITMASK32_OFFSET(chId))
@@ -990,6 +970,22 @@ static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address)
// Get the number of elements the specified fixed-size array
#define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0])))
#if !defined(NVIDIA_UNDEF_LEGACY_BIT_MACROS)
//
// Deprecated macros whose definition can be removed once the code base no longer references them.
// Use the NVBIT* macros instead of these macros.
//
#ifndef BIT
#define BIT(b) (1U<<(b))
#endif
#ifndef BIT32
#define BIT32(b) ((NvU32)1U<<(b))
#endif
#ifndef BIT64
#define BIT64(b) ((NvU64)1U<<(b))
#endif
#endif
#ifdef __cplusplus
}
#endif //__cplusplus

43
src/common/sdk/nvidia/inc/nvos.h
View File

@@ -1200,7 +1200,7 @@ typedef struct
#define NVOS32_ATTR2_SMMU_ON_GPU_ENABLE 0x00000002
// Used for allocating the memory from scanout carveout.
#define NVOS32_ATTR2_USE_SCANOUT_CARVEOUT 10:10
#define NVOS32_ATTR2_USE_SCANOUT_CARVEOUT 10:10
#define NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_FALSE 0x00000000
#define NVOS32_ATTR2_USE_SCANOUT_CARVEOUT_TRUE 0x00000001
@@ -2121,16 +2121,10 @@ typedef struct
#define NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE (0x00000000)
#define NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE (0x00000001)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP 19:16
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_DEFAULT (0x00000000)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_1 (0x00000001)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_2 (0x00000002)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_4 (0x00000003)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_8 (0x00000004)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_16 (0x00000005)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_32 (0x00000006)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_64 (0x00000007)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_128 (0x00000008)
#define NVOS46_FLAGS_DISABLE_ENCRYPTION 16:16
#define NVOS46_FLAGS_DISABLE_ENCRYPTION_FALSE (0x00000000)
#define NVOS46_FLAGS_DISABLE_ENCRYPTION_TRUE (0x00000001)
#define NVOS46_FLAGS_P2P 27:20
#define NVOS46_FLAGS_P2P_ENABLE 21:20
@@ -2149,6 +2143,15 @@ typedef struct
#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC 29:29
#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE (0x00000000)
#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE (0x00000001)
//
// Force pte kind to compresssed for this and future mappings of the memory object
// Only affects mappings using NVOS46_FLAGS_PAGE_KIND_VIRTUAL
// Only has effect when physical allocation is compressed
//
#define NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP 30:30
#define NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_FALSE (0x00000000)
#define NVOS46_FLAGS_ENABLE_FORCE_COMPRESSED_MAP_TRUE (0x00000001)
//
// This flag must be used with caution. Improper use can leave stale entries in the TLB,
// and allow access to memory no longer owned by the RM client or cause page faults.
@@ -2308,8 +2311,8 @@ typedef struct
NvU8 bForcePowerStateFail;
NvU32 errorStatus; // [OUT] To tell client if there is bubble up errors
NvU32 fastBootPowerState;
NvU8 reserved;
NvU8 reserved2;
NvU8 bGC8Transition;
NvU8 bGC8InputRailCutOff; // [OUT] To tell client if input rail was cut off in GC8
} NVPOWERSTATE_PARAMETERS, *PNVPOWERSTATE_PARAMETERS;
/***************************************************************************\
@@ -2817,6 +2820,9 @@ typedef struct
* SPECIFIED
* Force the VEID specified in the subctxId parameter.
* This flag is intended for verif. i.e testing VEID reuse etc.
* PREFER_LOWER
* Identical behavior to ASYNC, except lower VEIDs are preferred on VOLTA+ chips
*
*
* subctxId
* As input, it is used to specify the subcontext ID, when the _SPECIFIED flag is set.
@@ -2835,6 +2841,17 @@ typedef struct
#define NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SYNC (0x00000000)
#define NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC (0x00000001)
#define NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SPECIFIED (0x00000002)
#define NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER (0x00000003)
/*
* The high bit of NV_CTXSHARE_ALLOCATION_PARAMETERS.subctxId is used to indicate success or failure allocating
* a subcontext ID below an architecture specific value, which can be queried with
* NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT. Remaining bits are currently reserved for the subcontext ID.
*/
#define NV_CTXSHARE_ALLOCATION_SUBCTXID_SUBCTXID 30:0
#define NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION 31:31
#define NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_SUCCESS (0x00000001)
#define NV_CTXSHARE_ALLOCATION_SUBCTXID_ASYNC_PREFER_LOWER_ALLOCATION_FAIL (0x00000000)
/**
* @brief RmTimeoutControl parameters

4
src/common/sdk/nvidia/inc/nvstatuscodes.h
View File

@@ -155,6 +155,10 @@ NV_STATUS_CODE(NV_ERR_KEY_ROTATION_IN_PROGRESS, 0x0000007D, "Operation no
NV_STATUS_CODE(NV_ERR_TEST_ONLY_CODE_NOT_ENABLED, 0x0000007E, "Test-only code path not enabled")
NV_STATUS_CODE(NV_ERR_SECURE_BOOT_FAILED, 0x0000007F, "GFW secure boot failed")
NV_STATUS_CODE(NV_ERR_INSUFFICIENT_ZBC_ENTRY, 0x00000080, "No more ZBC entry for the client")
NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_NOT_READY, 0x00000081, "Nvlink Fabric Status or Fabric Probe is not yet complete, caller needs to retry")
NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_FAILURE, 0x00000082, "Nvlink Fabric Probe failed")
NV_STATUS_CODE(NV_ERR_GPU_MEMORY_ONLINING_FAILURE, 0x00000083, "GPU Memory Onlining failed")
NV_STATUS_CODE(NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE, 0x00000084, "Reduction Manager is not available")
// Warnings:
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")