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This commit is contained in:
Bernhard Stoeckner
2025-01-27 19:36:56 +01:00
parent 9d0b0414a5
commit 54d69484da
1166 changed files with 318863 additions and 182687 deletions
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6
src/nvidia/inc/kernel/core/bin_data.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -100,11 +100,11 @@ const BINDATA_STORAGE * bindataArchiveGetStorage(const BINDATA_ARCHIVE *pBinArch
// do_stuff(datablock, size);
// }
//
void* bindataGetNextUnreferencedStorage(const BINDATA_STORAGE **iter, NvU32 *pDataSize);
void* bindataGetNextUnreferencedStorage(NvU32 *pIdx, NvU32 *pDataSize);
//
// Marks a given BINDATA_STORAGE as destroyed, making all subsequent attempts
// to access it fail and return NULL/0
//
void bindataDestroyStorage(BINDATA_STORAGE *storage);
void bindataDestroyStorage(NvU32 idx);
#endif // _BINDATA_H

4
src/nvidia/inc/kernel/core/locks.h
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@@ -165,13 +165,15 @@ NvBool rmGpuLockIsHidden(OBJGPU *);
NV_STATUS rmGpuLockSetOwner(OS_THREAD_HANDLE);
void rmGpuLockGetTimes(NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *);
NV_STATUS rmGpuGroupLockAcquire(NvU32, GPU_LOCK_GRP_ID, NvU32, NvU32, GPU_MASK *);
NV_STATUS rmGpuGroupLockRelease(GPU_MASK, NvU32);
void rmGpuGroupLockRelease(GPU_MASK, NvU32);
NvBool rmGpuGroupLockIsOwner(NvU32, GPU_LOCK_GRP_ID, GPU_MASK*);
NvBool rmDeviceGpuLockIsOwner(NvU32);
NV_STATUS rmDeviceGpuLockSetOwner(OBJGPU *, OS_THREAD_HANDLE);
NV_STATUS rmDeviceGpuLocksAcquire(OBJGPU *, NvU32, NvU32);
NvU32 rmDeviceGpuLocksRelease(OBJGPU *, NvU32, OBJGPU *);
NvU32 rmDeviceGpuLocksReleaseAndThreadStateFreeDeferredIntHandlerOptimized(OBJGPU *, NvU32, OBJGPU *);
NV_STATUS rmIntrMaskLockAlloc(NvU32 gpuInst);
void rmIntrMaskLockFree(NvU32 gpuInst);

4
src/nvidia/inc/kernel/core/printf.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2001-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -247,6 +247,8 @@ void nvDbgDumpBufferBytes(void *pBuffer, NvU32 length);
void nvErrorLog(void *pVoid, NvU32 num, const char *pFormat, va_list arglist);
void nvErrorLog_va(void * pGpu, NvU32 num, const char * pFormat, ...);
void nvErrorLog2(void *pVoid, NvU32 num, NvBool oobLogging, const char *pFormat, va_list arglist);
void nvErrorLog2_va(void * pGpu, NvU32 num, NvBool oobLogging, const char * pFormat, ...);
#ifdef __cplusplus
}

2
src/nvidia/inc/kernel/core/thread_state.h
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@@ -199,6 +199,8 @@ NvU32 threadStateGetSetupFlags(void);
void threadStateInitISRLockless(THREAD_STATE_NODE *, OBJGPU*, NvU32);
void threadStateFreeISRLockless(THREAD_STATE_NODE *, OBJGPU*, NvU32);
void threadStateInitISRAndDeferredIntHandler(THREAD_STATE_NODE *, OBJGPU*, NvU32);
void threadStateOnlyProcessWorkISRAndDeferredIntHandler(THREAD_STATE_NODE *, OBJGPU*, NvU32);
void threadStateOnlyFreeISRAndDeferredIntHandler(THREAD_STATE_NODE *, OBJGPU*, NvU32);
void threadStateFreeISRAndDeferredIntHandler(THREAD_STATE_NODE *, OBJGPU*, NvU32);
void threadStateInit(THREAD_STATE_NODE *pThreadNode, NvU32 flags);
void threadStateFree(THREAD_STATE_NODE *pThreadNode, NvU32 flags);

3
src/nvidia/inc/kernel/diagnostics/code_coverage_mgr.h Normal file
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@@ -0,0 +1,3 @@
#include "g_code_coverage_mgr_nvoc.h"

96
src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_keystore.h
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@@ -1,96 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef CONF_COMPUTE_KEYSTORE_H
#define CONF_COMPUTE_KEYSTORE_H
#include "nvtypes.h"
#include "nvstatus.h"
#include "cc_drv.h"
#include "kernel/gpu/fifo/kernel_channel.h"
// Named values for ccKeyStoreDeposit()'s slotNumber parameter.
#define KEYSTORE_SLOT_GSP 0
#define KEYSTORE_SLOT_SEC2 1
// LCE index can range from 0 to 7 inclusive.
#define KEYSTORE_SLOT_LCE_UMD(index) (2 + (index) * 3)
#define KEYSTORE_SLOT_LCE_KMD(index) (3 + (index) * 3)
#define KEYSTORE_SLOT_LCE_MGPU(index) (4 + (index) * 3)
/*!
* @brief Initialize the keystore.
*
* @param[in] pGpu Pointer to GPU object.
*
* @return NV_ERR_INVALID_STATE if system is not in Confidential Compute mode.
*/
NV_STATUS
ccKeyStoreInit (OBJGPU *pGpu);
/*!
* @brief Deposits a KMB into a keystore slot.
*
* @param[in] slotNumber Slot number into which the KMB will be deposited.
* @param[in] keyMaterialBundle Pair of key / IV / IV mask tuples. IV will be set to 0 by function.
*
* @return NV_ERR_INVALID_INDEX if slotNumber is illegal, NV_OK otherwise.
*/
NV_STATUS
ccKeyStoreDeposit
(
NvU32 slotNumber,
CC_KMB keyMaterialBundle
);
/*!
* @brief Retrieves a KMB based on the channel. The keystore uses channel
information such as engine type and the associated privilege mode
to determine which KMB to fetch.
* The IV's channel counter for the given direction is pre-incremented.
*
* @param[in] pKernelChannel
* @param[in] rotateOperation Either:
ROTATE_IV_ENCRYPT
ROTATE_IV_DECRYPT
ROTATE_IV_ALL_VALID
* @param[out] keyMaterialBundle The KMB for the given channel.
*
* @return NV_ERR_INSUFFICIENT_RESOURCES if channel counter overflow would occur.
NV_ERR_GENERIC for other errors.
* NV_OK otherwise.
*/
NV_STATUS
ccKeyStoreRetrieveViaChannel
(
KernelChannel *pKernelChannel,
ROTATE_IV_TYPE rotateOperation,
PCC_KMB keyMaterialBundle
);
/*!
* @brief Clears the contents of the keystore.
*/
void
cckeyStoreClear (void);
#endif // CONF_COMPUTE_KEYSTORE_H

129
src/nvidia/inc/kernel/gpu/error_cont.h
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@@ -76,11 +76,11 @@ typedef enum _NV_ERROR_CONT_ERR_ID
*/
typedef struct _NV_ERROR_CONT_SMC_DIS_EN_SETTING
{
NvU32 rcErrorCode;
NvBool bGpuResetReqd;
NvBool bGpuDrainAndResetReqd;
NvBool bPrintSmcPartitionInfo;
NvU32 nv2080Notifier;
NvU32 rcErrorCode;
NvBool bGpuResetReqd;
NvBool bGpuDrainAndResetReqd;
NvBool bPrintSmcPartitionInfo;
NvU32 nv2080Notifier;
} NV_ERROR_CONT_SMC_DIS_EN_SETTING;
/*!
@@ -88,9 +88,9 @@ typedef struct _NV_ERROR_CONT_SMC_DIS_EN_SETTING
*/
typedef struct _NV_ERROR_CONT_STATE_TABLE
{
NV_ERROR_CONT_ERR_ID errorCode;
NV_ERROR_CONT_SMC_DIS_EN_SETTING smcDisEnSetting[2]; // 0: SMC memory partitioning disabled,
// 1: SMC memory partitioning enabled
NV_ERROR_CONT_ERR_ID errorCode;
NV_ERROR_CONT_SMC_DIS_EN_SETTING smcDisEnSetting[2]; // 0: SMC memory partitioning disabled,
// 1: SMC memory partitioning enabled
} NV_ERROR_CONT_STATE_TABLE;
/*!
@@ -117,8 +117,8 @@ typedef struct _NV_ERROR_CONT_LOCATION_DRAM
*/
typedef struct _NV_ERROR_CONT_LOCATION_ENG_ID
{
RM_ENGINE_TYPE rmEngineId;
Device *pDevice;
RM_ENGINE_TYPE rmEngineId;
Device *pDevice;
} NV_ERROR_CONT_LOCATION_ENG_ID;
/*!
@@ -126,11 +126,11 @@ typedef struct _NV_ERROR_CONT_LOCATION_ENG_ID
*/
typedef enum _NV_ERROR_CONT_LOCATION_TYPE
{
NV_ERROR_CONT_LOCATION_TYPE_NONE = 0, // No location information available
NV_ERROR_CONT_LOCATION_TYPE_DRAM = 1, // DRAM location
NV_ERROR_CONT_LOCATION_TYPE_LTC = 2, // LTC location
NV_ERROR_CONT_LOCATION_TYPE_ENGINE = 3, // Engine location
NV_ERROR_CONT_LOCATION_TYPE_VF = 4 // VF location
NV_ERROR_CONT_LOCATION_TYPE_NONE = 0, // No location information available
NV_ERROR_CONT_LOCATION_TYPE_DRAM = 1, // DRAM location
NV_ERROR_CONT_LOCATION_TYPE_LTC = 2, // LTC location
NV_ERROR_CONT_LOCATION_TYPE_ENGINE = 3, // Engine location
NV_ERROR_CONT_LOCATION_TYPE_VF = 4 // VF location
} NV_ERROR_CONT_LOCATION_TYPE;
/*!
@@ -138,10 +138,10 @@ typedef enum _NV_ERROR_CONT_LOCATION_TYPE
*/
typedef union _NV_ERROR_CONT_LOCATION_INFO
{
NV_ERROR_CONT_LOCATION_DRAM dramLoc; // DRAM location
NV_ERROR_CONT_LOCATION_LTC ltcLoc; // LTC location
NV_ERROR_CONT_LOCATION_ENG_ID engineLoc; // Engine location
NvU32 vfGfid; // VF location
NV_ERROR_CONT_LOCATION_DRAM dramLoc; // DRAM location
NV_ERROR_CONT_LOCATION_LTC ltcLoc; // LTC location
NV_ERROR_CONT_LOCATION_ENG_ID engineLoc; // Engine location
NvU32 vfGfid; // VF location
} NV_ERROR_CONT_LOCATION_INFO;
typedef struct _NV_ERROR_CONT_LOCATION
@@ -152,14 +152,15 @@ typedef struct _NV_ERROR_CONT_LOCATION
/* ------------------------ Macros ------------------------------------------ */
#define ROBUST_CHANNEL_CONTAINED_ERROR_STR "Contained"
#define ROBUST_CHANNEL_UNCONTAINED_ERROR_STR "Uncontained"
#define NO_XID NV_U32_MAX
#define NO_NV2080_NOTIFIER NV2080_NOTIFIERS_MAXCOUNT
#define NV_ERR_CONT_LOCATION_STRING_SIZE_MAX 64
#define ROBUST_CHANNEL_CONTAINED_ERROR_STR "Contained"
#define ROBUST_CHANNEL_UNCONTAINED_ERROR_STR "Uncontained"
#define NO_XID NV_U32_MAX
#define NO_NV2080_NOTIFIER NV2080_NOTIFIERS_MAXCOUNT
#define NV_ERR_CONT_LOCATION_STRING_SIZE_MAX 64
/*!
* Error Containment error types string
* Error Containment error types string.
* The order of this list must match the NV_ERROR_CONT_ERR_ID enums.
*/
#define NV_ERROR_CONT_ERR_ID_STRING_PUBLIC {"FB DED", \
"DED CBC", \
@@ -185,82 +186,4 @@ typedef struct _NV_ERROR_CONT_LOCATION
"NVJPG", \
"OFA"}
/*!
* Error Containment state table showing policy settings for each error id
*
* Where:
* RC_Recovery_Type:
* Type of RC recovery handling in response to a given error. Possible values:
*
* - NO_RC : No RC Recovery performed. Subsequent 2nd interrupt by engine
* consuming poison will determine the RC Recovery type.
* - RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE : RC Recovery compute channels of only the processes whose
* channels were loaded on halted TSG when _E10_SM_POISON or
* _E12A_CE_POISON_IN_USER_CHANNEL occurs.
* - RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION : RC Recovery compute channels of only specific MIG partition
* as that error can be attributed to a specific MIG partition.
* - RC_ALL_CHANNELS_IN_VF : RC Recovery compute channels of only specific GFID
* as that error can be attributed to a VF.
* - RC_ALL_USER_CHANNELS : RC Recovery ALL user channels on a GPU.
* - RC_ALL_COMPUTE_CHANNELS : RC Recovery ALL compute channels on a GPU that saw this interrupt.
* (If MIG is enabled, then RC Recovery compute channels in all MIG partitions)
* - CE_TSG_RESET : Reset the halted CE Engine. Impacts the CE channels loaded on the TSG when the CE Halted.
* This is used in NV_ERROR_CONT_ERR_ID_E12A_CE_POISON_IN_USER_CHANNEL &
* NV_ERROR_CONT_ERR_ID_E12B_CE_POISON_IN_KERNEL_CHANNEL along with additional
* Compute Channels RC policy (either RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE or
* RC_ALL_COMPUTE_CHANNELS).
*/
#define NV_ERROR_CONT_STATE_TABLE_SETTINGS \
{ \
/* errorCode , rcErrorCode , bGpuResetReqd, bGpuDrainAndResetReqd, bPrintSmcPartitionInfo, nv2080Notifier , Dynamic Page Blacklisting , RC_Recovery_Type */ \
{ NV_ERROR_CONT_ERR_ID_E01_FB_ECC_DED , {{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , Yes(PMA but not subheap) , NO_RC */ }, \
{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , Yes(PMA but not subheap) , NO_RC */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E02_FB_ECC_DED_IN_CBC_STORE , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , Yes(PMA but not subheap) , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_TRUE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , Yes(PMA but not subheap) , RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E05_LTC_ECC_DSTG , {{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , No , NO_RC */ }, \
{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , No , NO_RC */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E06_LTC_UNSUPPORTED_CLIENT_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_TRUE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E07_LTC_ECC_TSTG , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E08_LTC_ECC_RSTG , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_TRUE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E09_FBHUB_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E10_SM_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E12A_CE_POISON_IN_USER_CHANNEL , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE + CE_TSG_RESET */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE + CE_TSG_RESET */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E12B_CE_POISON_IN_KERNEL_CHANNEL , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS + CE_TSG_RESET */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS + CE_TSG_RESET */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E13_MMU_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , NO_RC */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , NO_RC */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E16_GCC_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E17_CTXSW_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E20_XALEP_EGRESS_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E21A_XALEP_INGRESS_CONTAINED_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_CHANNELS_IN_VF */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_CHANNELS_IN_VF */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E21B_XALEP_INGRESS_UNCONTAINED_POISON, {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E22_PMU_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E23_SEC2_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E24_GSP_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_USER_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_USER_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E25_FBFALCON_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E26_NVDEC_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E27_NVJPG_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E28_OFA_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}} \
}
/* ------------------------ Function Prototypes ----------------------------- */
#endif // _ERROR_CONT_H_

2
src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h
View File

@@ -247,7 +247,7 @@ NV_STATUS gsyncSetInterlaceMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU3
NV_STATUS gsyncRefSwapBarrier_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvBool *);
NV_STATUS gsyncGetWatchdog_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetWatchdog_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
NV_STATUS gsyncGetRevision_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCCAPSPARAMS *);
NV_STATUS gsyncGetRevision_P2060 (OBJGPU *, OBJGSYNC *, GSYNCCAPSPARAMS *);
NV_STATUS gsyncOptimizeTimingParameters_P2060(OBJGPU *, GSYNCTIMINGPARAMS *);
NV_STATUS gsyncGetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);

2
src/nvidia/inc/kernel/gpu/external_device/dev_p2061.h
View File

@@ -35,7 +35,7 @@
#define NV_P2061_STATUS6_INT_PORT_DIRECTION_OUTPUT 1 /* RWXVF */
// Used in FW 3.00 and above
#define NV_P2061_CONTROL5 0x33 /* RW-1R */
#define NV_P2061_CONTROL5 0x15 /* RW-1R */
#define NV_P2061_CONTROL5_RASTER_SYNC_DECODE_MODE 1:0 /* RWXVF */
#define NV_P2061_CONTROL5_RASTER_SYNC_DECODE_MODE_VSYNC_SHORT_PULSE 0 /* RWXVF */
#define NV_P2061_CONTROL5_RASTER_SYNC_DECODE_MODE_VSYNC_SINGLE_PULSE 1 /* RWXVF */

3
src/nvidia/inc/kernel/gpu/gpu_child_list.h
View File

@@ -306,6 +306,9 @@
#if RMCFG_MODULE_KERNEL_CCU && GPU_CHILD_MODULE(KERNEL_CCU)
GPU_CHILD_SINGLE_INST( KernelCcu, GPU_GET_KERNEL_CCU, 1, NV_FALSE, pKernelCcu )
#endif
#if RMCFG_MODULE_KERNEL_GSPLITE && GPU_CHILD_MODULE(KERNEL_GSPLITE)
GPU_CHILD_MULTI_INST( KernelGsplite, GPU_GET_KERNEL_GSPLITE, GPU_MAX_GSPLITES, NV_FALSE, pKernelGsplite )
#endif
// Undefine the entry macros to simplify call sites
#undef GPU_CHILD

6
src/nvidia/inc/kernel/gpu/gpu_engine_type.h
View File

@@ -71,7 +71,8 @@ typedef enum
RM_ENGINE_TYPE_NVENC0 = (0x00000025),
RM_ENGINE_TYPE_NVENC1 = (0x00000026),
RM_ENGINE_TYPE_NVENC2 = (0x00000027),
RM_ENGINE_TYPE_RESERVED28 = (0x00000028),
// Bug 4175886 - Use this new value for all chips once GB20X is released
RM_ENGINE_TYPE_NVENC3 = (0x00000028),
RM_ENGINE_TYPE_VP = (0x00000029),
RM_ENGINE_TYPE_ME = (0x0000002a),
RM_ENGINE_TYPE_PPP = (0x0000002b),
@@ -129,7 +130,8 @@ typedef enum
#define RM_ENGINE_TYPE_NVJPG RM_ENGINE_TYPE_NVJPEG0
#define RM_ENGINE_TYPE_COPY_SIZE 20
#define RM_ENGINE_TYPE_NVENC_SIZE 3
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define RM_ENGINE_TYPE_NVENC_SIZE 4
#define RM_ENGINE_TYPE_NVJPEG_SIZE 8
#define RM_ENGINE_TYPE_NVDEC_SIZE 8
#define RM_ENGINE_TYPE_OFA_SIZE 2

1
src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h
View File

@@ -44,6 +44,7 @@ void gpuFabricProbeStopPhysical(GPU_FABRIC_PROBE_INFO_PHYSICAL *pGpuFabricProbeI
NvU32 gfId);
void gpuFabricProbeSuspend(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
void gpuFabricProbeInvalidate(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
NV_STATUS gpuFabricProbeResume(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
NV_STATUS gpuFabricProbeGetGpuFabricHandle(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pHandle);

2
src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h
View File

@@ -41,6 +41,8 @@ typedef struct GpuSharedDataMap {
NvU64 lastPolledDataMask;
NvU32 processId;
NvU32 pollingRegistryOverride;
NvU32 pollingFrequencyMs;
NvBool bPollFrequencyOverridden;
TMR_EVENT *pRusdRefreshTmrEvent;

33
src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -68,7 +68,15 @@
//
#define GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE ((48 << 10) * 2048) // Support 2048 channels
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (565 << 20) // Default for all VGPU configs
#if RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
#define BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA (12u)
#define BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA (70u)
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT \
((581u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA)) << 20)
#else
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (581 << 20)
#endif // RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
@@ -76,10 +84,25 @@
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB (64u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB (256u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB (86u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB (278u)
#if RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
// Size increased for compatibility reasons with ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE
// and ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE in init_partition.h
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB \
(88u + (BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA))
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB \
(280u + (BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA))
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB (565u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB \
(581u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA))
#else
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB (88u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB (280u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB (581u)
#endif // RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB (1040u)
#endif // GSP_FW_HEAP_H

7
src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,10 +24,10 @@
#ifndef GSP_INIT_ARGS_H
#define GSP_INIT_ARGS_H
#include "core/core.h"
#include "nvtypes.h"
typedef struct {
RmPhysAddr sharedMemPhysAddr;
NvU64 sharedMemPhysAddr;
NvU32 pageTableEntryCount;
NvLength cmdQueueOffset;
NvLength statQueueOffset;
@@ -47,6 +47,7 @@ typedef struct
MESSAGE_QUEUE_INIT_ARGUMENTS messageQueueInitArguments;
GSP_SR_INIT_ARGUMENTS srInitArguments;
NvU32 gpuInstance;
NvBool bDmemStack;
struct
{

12
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
View File

@@ -68,6 +68,12 @@ typedef struct
NvU32 ecidExtended;
} EcidManufacturingInfo;
typedef struct
{
NvU64 nonWprHeapOffset;
NvU64 frtsOffset;
} FW_WPR_LAYOUT_OFFSET;
// Fetched from GSP-RM into CPU-RM
typedef struct GspStaticConfigInfo_t
{
@@ -103,8 +109,10 @@ typedef struct GspStaticConfigInfo_t
NvBool bIsTesla;
NvBool bIsMobile;
NvBool bIsGc6Rtd3Allowed;
NvBool bIsGc8Rtd3Allowed;
NvBool bIsGcOffRtd3Allowed;
NvBool bIsGcoffLegacyAllowed;
NvBool bIsMigSupported;
/* "Total Board Power" refers to power requirement of GPU,
* while in GC6 state. Majority of this power will be used
@@ -154,6 +162,8 @@ typedef struct GspStaticConfigInfo_t
NvBool bIsEfiInit;
EcidManufacturingInfo ecidInfo[MAX_GROUP_COUNT];
FW_WPR_LAYOUT_OFFSET fwWprLayoutOffset;
} GspStaticConfigInfo;
// Pushed from CPU-RM to GSP-RM
@@ -182,6 +192,7 @@ typedef struct GspSystemInfo
NvBool bFlrSupported;
NvBool b64bBar0Supported;
NvBool bMnocAvailable;
NvU32 chipsetL1ssEnable;
NvBool bUpstreamL0sUnsupported;
NvBool bUpstreamL1Unsupported;
NvBool bUpstreamL1PorSupported;
@@ -204,6 +215,7 @@ typedef struct GspSystemInfo
NvBool bFeatureStretchVblankCapable;
NvBool bEnableDynamicGranularityPageArrays;
NvBool bClockBoostSupported;
NvBool bRouteDispIntrsToCPU;
} GspSystemInfo;

26
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
View File

@@ -78,7 +78,8 @@
#define MC_ENGINE_IDX_NVENC 38
#define MC_ENGINE_IDX_NVENC1 39
#define MC_ENGINE_IDX_NVENC2 40
#define MC_ENGINE_IDX_RESERVED41 41
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define MC_ENGINE_IDX_NVENC3 41
#define MC_ENGINE_IDX_C2C 42
#define MC_ENGINE_IDX_LTC 43
#define MC_ENGINE_IDX_FBHUB 44
@@ -152,12 +153,19 @@
#define MC_ENGINE_IDX_PXUC 168
#define MC_ENGINE_IDX_SYSLTC 169
#define MC_ENGINE_IDX_LRCC 170
#define MC_ENGINE_IDX_RESERVED171 171
#define MC_ENGINE_IDX_RESERVED172 172
#define MC_ENGINE_IDX_RESERVED173 173
#define MC_ENGINE_IDX_RESERVED174 174
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define MC_ENGINE_IDX_GSPLITE 171
#define MC_ENGINE_IDX_GSPLITE0 MC_ENGINE_IDX_GSPLITE
#define MC_ENGINE_IDX_GSPLITE1 172
#define MC_ENGINE_IDX_GSPLITE2 173
#define MC_ENGINE_IDX_GSPLITE3 174
#define MC_ENGINE_IDX_GSPLITE_MAX MC_ENGINE_IDX_GSPLITE3
#define MC_ENGINE_IDX_DPAUX 175
#define MC_ENGINE_IDX_DISP_LOW 176
// This must be kept as the max bit if we need to add more engines
#define MC_ENGINE_IDX_MAX 175
#define MC_ENGINE_IDX_MAX 177
// Index GR reference
#define MC_ENGINE_IDX_GRn(x) (MC_ENGINE_IDX_GR0 + (x))
@@ -184,6 +192,12 @@
// Index OFA reference
#define MC_ENGINE_IDX_OFA(x) (MC_ENGINE_IDX_OFA0 + (x))
//
// Bug 4175886 - Remove check once GB20X is released
// Index GSPLITE reference
//
#define MC_ENGINE_IDX_GSPLITEn(x) (MC_ENGINE_IDX_GSPLITE + (x))
MAKE_BITVECTOR(MC_ENGINE_BITVECTOR, MC_ENGINE_IDX_MAX);
typedef MC_ENGINE_BITVECTOR *PMC_ENGINE_BITVECTOR;

2
src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h
View File

@@ -51,6 +51,8 @@
#include "class/clc9b5.h" // BLACKWELL_DMA_COPY_A
#include "class/clcab5.h" // BLACKWELL_DMA_COPY_B
#include "gpu/conf_compute/ccsl.h"
#include "nvctassert.h"

14
src/nvidia/inc/kernel/gpuvideo/video_event.h
View File

@@ -94,8 +94,7 @@ typedef enum
} VIDEO_ENGINE_EVENT_ID;
/*!
* Defines types of the log data of video events if VIDEO_ENGINE_EVENT__LOG_DATA_MAGIC present
* as first DWORD of log data.
* Defines types of the log data of video events
*/
typedef enum
{
@@ -143,19 +142,10 @@ typedef struct
{
NvU8 engine_type;
NvU8 engine_id;
NvU16 codec_id;
NvU16 type; /* VIDEO_ENGINE_EVENT_LOG_DATA_TYPE */
NvU32 size; /* size of data being logged in NvU32 */
} VIDEO_ENGINE_EVENT__LOG_DATA;
#define VIDEO_ENGINE_EVENT__LOG_DATA_MAGIC RM_VIDEO_TRACE_EVENT_MAGIC_HI
typedef struct
{
NvU32 magic;
VIDEO_ENGINE_EVENT_LOG_DATA_TYPE type;
NvU32 data[];
} VIDEO_ENGINE_EVENT__LOG_DATA_HDR;
/*!
* Defines the struct for a full trace record contains various event structs.
*/

2
src/nvidia/inc/kernel/mem_mgr/p2p.h
View File

@@ -28,7 +28,7 @@
NV_STATUS RmP2PGetPages (NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, OBJGPU **, void *, void (*)(void *), void *);
NV_STATUS RmP2PGetPagesWithoutCallbackRegistration (NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, OBJGPU **, void *);
NV_STATUS RmP2PGetPagesPersistent (NvU64, NvU64, void **, NvU64 *, NvU32 *, void *, void *, void **);
NV_STATUS RmP2PGetPagesPersistent (NvU64, NvU64, void **, NvU64 *, NvU32 *, NvBool, void *, void *, void **);
NV_STATUS RmP2PRegisterCallback (NvU64, NvU64, NvU64, void *, void (*)(void *), void *);
NV_STATUS RmP2PPutPages (NvU64, NvU32, NvU64, void *);
NV_STATUS RmP2PGetGpuByAddress (NvU64, NvU64, OBJGPU **);

2
src/nvidia/inc/kernel/rmapi/control.h
View File

@@ -332,6 +332,8 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *pParamCopy, RmCtrlParams *pRmC
//
#define RMCTRL_FLAGS_NO_API_LOCK 0x000400000
#define RMCTRL_FLAGS_PERSISTENT_CACHEABLE 0x000800000
//
// 'ACCESS_RIGHTS' Attribute
// ------------------------

2
src/nvidia/inc/kernel/rmapi/rmapi.h
View File

@@ -317,9 +317,11 @@ NV_STATUS rmapiControlCacheSet(NvHandle hClient, NvHandle hObject, NvU32 cmd,
void* params, NvU32 paramsSize);
NV_STATUS rmapiControlCacheSetGpuAttrForObject(NvHandle hClient, NvHandle hObject, OBJGPU *pGpu);
void rmapiControlCacheFreeAllCacheForGpu(NvU32 gpuInst);
void rmapiControlCacheFreeNonPersistentCacheForGpu(NvU32 gpuInst);
void rmapiControlCacheSetMode(NvU32 mode);
NvU32 rmapiControlCacheGetMode(void);
void rmapiControlCacheFree(void);
NV_STATUS rmapiControlCacheFreeForControl(NvU32 gpuInstance, NvU32 cmd);
void rmapiControlCacheFreeClientEntry(NvHandle hClient);
void rmapiControlCacheFreeObjectEntry(NvHandle hClient, NvHandle hObject);

54
src/nvidia/inc/kernel/rmapi/rmapi_cache_handlers.h Normal file
View File

@@ -0,0 +1,54 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _RMAPI_CACHE_HANDLERS_H_
#define _RMAPI_CACHE_HANDLERS_H_
#include "nvtypes.h"
#include "nvstatus.h"
#include "ctrl/ctrl0073/ctrl0073system.h"
typedef NV_STATUS (*RmapiCacheGetByInputHandler)(void *cachedEntry, void* pParams, NvBool bSet);
//
// Rm Cmd Cache Handler structure definitions and function declarations.
//
typedef struct DispSystemGetSupportedCacheEntry
{
NvBool valid;
NvU32 displayMask;
NvU32 displayMaskDDC;
} DispSystemGetSupportedCacheEntry;
NV_STATUS _dispSystemGetSupportedCacheHandler(void *cachedEntry, void* pParams, NvBool bSet);
typedef struct DispSystemGetInternalDisplaysCacheEntry
{
NvBool valid;
NvU32 internalDisplaysMask;
NvU32 availableInternalDisplaysMask;
} DispSystemGetInternalDisplaysCacheEntry;
NV_STATUS _dispSystemGetInternalDisplaysCacheHandler(void *cachedEntry, void* pParams, NvBool bSet);
#endif

456
src/nvidia/inc/kernel/vgpu/rm_plugin_shared_code.h
View File

@@ -833,6 +833,27 @@ return_t deserialize_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06(NV83DE_CTRL_DE
return SUCCESS_T;
}
static
return_t deserialize_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07(NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07 *src = (void*)(buffer);
NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS *dest = pParams;
if (src && dest) {
#ifdef COPY_INPUT_PARAMETERS
dest->action = src->action;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t deserialize_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *pParams,
NvU8 *buffer,
@@ -1101,6 +1122,85 @@ return_t deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04(NV20
return SUCCESS_T;
}
static
return_t deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09 *src = (void*)(buffer);
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *dest = pParams;
if (src && dest) {
#ifdef COPY_OUTPUT_PARAMETERS
NvU32 i;
dest->enabledLinkMask = src->enabledLinkMask;
FOR_EACH_INDEX_IN_MASK(32, i, src->enabledLinkMask)
{
NV2080_CTRL_NVLINK_DEVICE_INFO *deviceInfo_d = NULL;
NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09 *deviceInfo_s = NULL;
if (i >= NV2080_CTRL_NVLINK_MAX_LINKS_v23_04)
break;
dest->linkInfo[i].capsTbl = src->linkInfo[i].capsTbl;
dest->linkInfo[i].phyType = src->linkInfo[i].phyType;
dest->linkInfo[i].subLinkWidth = src->linkInfo[i].subLinkWidth;
dest->linkInfo[i].linkState = src->linkInfo[i].linkState;
dest->linkInfo[i].rxSublinkStatus = src->linkInfo[i].rxSublinkStatus;
dest->linkInfo[i].txSublinkStatus = src->linkInfo[i].txSublinkStatus;
dest->linkInfo[i].nvlinkVersion = src->linkInfo[i].nvlinkVersion;
dest->linkInfo[i].nciVersion = src->linkInfo[i].nciVersion;
dest->linkInfo[i].phyVersion = src->linkInfo[i].phyVersion;
dest->linkInfo[i].nvlinkLinkClockKHz = src->linkInfo[i].nvlinkLinkClockKHz;
dest->linkInfo[i].nvlinkLineRateMbps = src->linkInfo[i].nvlinkLineRateMbps;
dest->linkInfo[i].connected = src->linkInfo[i].connected;
dest->linkInfo[i].remoteDeviceLinkNumber = src->linkInfo[i].remoteDeviceLinkNumber;
dest->linkInfo[i].localDeviceLinkNumber = src->linkInfo[i].localDeviceLinkNumber;
deviceInfo_d = &dest->linkInfo[i].remoteDeviceInfo;
deviceInfo_s = &src->linkInfo[i].remoteDeviceInfo;
deviceInfo_d->deviceIdFlags = deviceInfo_s->deviceIdFlags;
deviceInfo_d->domain = deviceInfo_s->domain;
deviceInfo_d->bus = deviceInfo_s->bus;
deviceInfo_d->device = deviceInfo_s->device;
deviceInfo_d->function = deviceInfo_s->function;
deviceInfo_d->pciDeviceId = deviceInfo_s->pciDeviceId;
deviceInfo_d->deviceType = deviceInfo_s->deviceType;
portMemCopy(deviceInfo_d->deviceUUID,
sizeof(deviceInfo_d->deviceUUID),
deviceInfo_s->deviceUUID,
sizeof(deviceInfo_s->deviceUUID));
deviceInfo_d->fabricRecoveryStatusMask = deviceInfo_s->fabricRecoveryStatusMask;
deviceInfo_d = &dest->linkInfo[i].localDeviceInfo;
deviceInfo_s = &src->linkInfo[i].localDeviceInfo;
deviceInfo_d->deviceIdFlags = deviceInfo_s->deviceIdFlags;
deviceInfo_d->domain = deviceInfo_s->domain;
deviceInfo_d->bus = deviceInfo_s->bus;
deviceInfo_d->device = deviceInfo_s->device;
deviceInfo_d->function = deviceInfo_s->function;
deviceInfo_d->pciDeviceId = deviceInfo_s->pciDeviceId;
deviceInfo_d->deviceType = deviceInfo_s->deviceType;
portMemCopy(deviceInfo_d->deviceUUID,
sizeof(deviceInfo_d->deviceUUID),
deviceInfo_s->deviceUUID,
sizeof(deviceInfo_s->deviceUUID));
deviceInfo_d->fabricRecoveryStatusMask = deviceInfo_s->fabricRecoveryStatusMask;
}
FOR_EACH_INDEX_IN_MASK_END;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t deserialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *pParams,
NvU8 *buffer,
@@ -2556,6 +2656,7 @@ return_t deserialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_B
#ifdef COPY_INPUT_PARAMETERS
NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 *src = (void*)(buffer);
NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *dest = pParams;
if (src && dest)
{
dest->connectionType = src->connectionType;
@@ -2574,6 +2675,35 @@ return_t deserialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_B
return SUCCESS_T;
}
return_t deserialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08(NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
#ifdef COPY_INPUT_PARAMETERS
NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08 *src = (void*)(buffer);
NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *dest = pParams;
if (src && dest)
{
dest->connectionType = src->connectionType;
dest->peerId = src->peerId;
dest->bEgmPeer = src->bEgmPeer;
dest->bSpaAccessOnly = src->bSpaAccessOnly;
dest->bUseUuid = src->bUseUuid;
dest->remoteGpuId = src->remoteGpuId;
portMemCopy(dest->remoteGpuUuid,
VM_UUID_SIZE_v21_02,
src->remoteGpuUuid,
VM_UUID_SIZE_v21_02);
}
else
return FAILURE_T;
#endif
return SUCCESS_T;
}
return_t deserialize_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
@@ -2745,6 +2875,26 @@ return_t deserialize_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_SET_HS
return SUCCESS_T;
}
#ifndef UMED_BUILD
return_t deserialize_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07(NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07 *src = (void*)(buffer);
NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS *dest = pParams;
if (src && dest) {
dest->value = src->value;
}
else
return FAILURE_T;
return SUCCESS_T;
}
#endif
#ifndef UMED_BUILD
return_t deserialize_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04(NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *pParams,
NvU8 *buffer,
@@ -3522,6 +3672,26 @@ return_t serialize_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06(NV83DE_CTRL_DEBU
return SUCCESS_T;
}
static
return_t serialize_NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07(NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS *src = pParams;
NV83DE_CTRL_DEBUG_SET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07 *dest = (void*)(buffer);
if (src && dest) {
#ifdef COPY_INPUT_PARAMETERS
dest->action = src->action;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t serialize_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *pParams,
NvU8 *buffer,
@@ -3790,6 +3960,86 @@ return_t serialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04(NV2080
return SUCCESS_T;
}
static
return_t serialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *src = pParams;
NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v28_09 *dest = (void*)(buffer);
if (src && dest) {
#ifdef COPY_OUTPUT_PARAMETERS
NvU32 i;
dest->enabledLinkMask = src->enabledLinkMask;
FOR_EACH_INDEX_IN_MASK(32, i, src->enabledLinkMask)
{
NV2080_CTRL_NVLINK_DEVICE_INFO *deviceInfo_s = NULL;
NV2080_CTRL_NVLINK_DEVICE_INFO_v28_09 *deviceInfo_d = NULL;
if (i >= NV2080_CTRL_NVLINK_MAX_LINKS_v23_04)
break;
dest->linkInfo[i].capsTbl = src->linkInfo[i].capsTbl;
dest->linkInfo[i].phyType = src->linkInfo[i].phyType;
dest->linkInfo[i].subLinkWidth = src->linkInfo[i].subLinkWidth;
dest->linkInfo[i].linkState = src->linkInfo[i].linkState;
dest->linkInfo[i].rxSublinkStatus = src->linkInfo[i].rxSublinkStatus;
dest->linkInfo[i].txSublinkStatus = src->linkInfo[i].txSublinkStatus;
dest->linkInfo[i].nvlinkVersion = src->linkInfo[i].nvlinkVersion;
dest->linkInfo[i].nciVersion = src->linkInfo[i].nciVersion;
dest->linkInfo[i].phyVersion = src->linkInfo[i].phyVersion;
dest->linkInfo[i].nvlinkLinkClockKHz = src->linkInfo[i].nvlinkLinkClockKHz;
dest->linkInfo[i].nvlinkLineRateMbps = src->linkInfo[i].nvlinkLineRateMbps;
dest->linkInfo[i].connected = src->linkInfo[i].connected;
dest->linkInfo[i].remoteDeviceLinkNumber = src->linkInfo[i].remoteDeviceLinkNumber;
dest->linkInfo[i].localDeviceLinkNumber = src->linkInfo[i].localDeviceLinkNumber;
deviceInfo_d = &dest->linkInfo[i].localDeviceInfo;
deviceInfo_s = &src->linkInfo[i].localDeviceInfo;
deviceInfo_d->deviceIdFlags = deviceInfo_s->deviceIdFlags;
deviceInfo_d->domain = deviceInfo_s->domain;
deviceInfo_d->bus = deviceInfo_s->bus;
deviceInfo_d->device = deviceInfo_s->device;
deviceInfo_d->function = deviceInfo_s->function;
deviceInfo_d->pciDeviceId = deviceInfo_s->pciDeviceId;
deviceInfo_d->deviceType = deviceInfo_s->deviceType;
portMemCopy(deviceInfo_d->deviceUUID,
sizeof(deviceInfo_d->deviceUUID),
deviceInfo_s->deviceUUID,
sizeof(deviceInfo_s->deviceUUID));
deviceInfo_d->fabricRecoveryStatusMask = deviceInfo_s->fabricRecoveryStatusMask;
deviceInfo_d = &dest->linkInfo[i].remoteDeviceInfo;
deviceInfo_s = &src->linkInfo[i].remoteDeviceInfo;
deviceInfo_d->deviceIdFlags = deviceInfo_s->deviceIdFlags;
deviceInfo_d->domain = deviceInfo_s->domain;
deviceInfo_d->bus = deviceInfo_s->bus;
deviceInfo_d->device = deviceInfo_s->device;
deviceInfo_d->function = deviceInfo_s->function;
deviceInfo_d->pciDeviceId = deviceInfo_s->pciDeviceId;
deviceInfo_d->deviceType = deviceInfo_s->deviceType;
portMemCopy(deviceInfo_d->deviceUUID,
sizeof(deviceInfo_d->deviceUUID),
deviceInfo_s->deviceUUID,
sizeof(deviceInfo_s->deviceUUID));
deviceInfo_d->fabricRecoveryStatusMask = deviceInfo_s->fabricRecoveryStatusMask;
}
FOR_EACH_INDEX_IN_MASK_END;
#endif
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t serialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *pParams,
NvU8 *buffer,
@@ -5259,6 +5509,37 @@ return_t serialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_BUS
}
#endif
#ifdef BUILD_COMMON_RPCS
return_t serialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08(NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
#ifdef COPY_INPUT_PARAMETERS
NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v29_08 *dest = (void*)(buffer);
NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *src = pParams;
if (src && dest)
{
dest->connectionType = src->connectionType;
dest->peerId = src->peerId;
dest->bEgmPeer = src->bEgmPeer;
dest->bSpaAccessOnly = src->bSpaAccessOnly;
dest->bUseUuid = src->bUseUuid;
dest->remoteGpuId = src->remoteGpuId;
portMemCopy(dest->remoteGpuUuid,
VM_UUID_SIZE_v21_02,
src->remoteGpuUuid,
VM_UUID_SIZE_v21_02);
}
else
return FAILURE_T;
#endif
return SUCCESS_T;
}
#endif
#ifdef BUILD_COMMON_RPCS
return_t serialize_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams,
NvU8 *buffer,
@@ -5430,6 +5711,25 @@ return_t serialize_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_SET_HS_C
return SUCCESS_T;
}
#ifndef UMED_BUILD
return_t serialize_NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07(NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS *src = pParams;
NV83DE_CTRL_DEBUG_GET_MODE_MMU_GCC_DEBUG_PARAMS_v29_07 *dest = (void*)(buffer);
if (src && dest) {
dest->value = src->value;
}
else
return FAILURE_T;
return SUCCESS_T;
}
#endif
#ifndef UMED_BUILD
return_t serialize_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04(NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *pParams,
NvU8 *buffer,
@@ -5578,6 +5878,146 @@ return_t deserialize_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v27_00(NV2080_CTRL_FB_GET
}
#endif // defined(BUILD_COMMON_RPCS)
#if defined(BUILD_COMMON_RPCS) && !defined(UMED_BUILD)
static
return_t serialize_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03(NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS *src = pParams;
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03 *dest = (void*)(buffer);
if (src && dest)
{
dest->allocatedSize = src->allocatedSize;
dest->peakAllocatedSize = src->peakAllocatedSize;
dest->managedSize = src->managedSize;
dest->allocationCount = src->allocationCount;
dest->peakAllocationCount = src->peakAllocationCount;
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t deserialize_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03(NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_03 *src = (void*)(buffer);
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS *dest = pParams;
if (src && dest)
{
dest->allocatedSize = src->allocatedSize;
dest->peakAllocatedSize = src->peakAllocatedSize;
dest->managedSize = src->managedSize;
dest->allocationCount = src->allocationCount;
dest->peakAllocationCount = src->peakAllocationCount;
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t serialize_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06(NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS *src = pParams;
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06 *dest = (void*)(buffer);
if (src && dest)
{
dest->allocatedSize = src->allocatedSize;
dest->peakAllocatedSize = src->peakAllocatedSize;
dest->managedSize = src->managedSize;
dest->allocationCount = src->allocationCount;
dest->peakAllocationCount = src->peakAllocationCount;
dest->largestFreeChunkSize = src->largestFreeChunkSize;
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t deserialize_NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06(NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_v28_06 *src = (void*)(buffer);
NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS *dest = pParams;
if (src && dest)
{
dest->allocatedSize = src->allocatedSize;
dest->peakAllocatedSize = src->peakAllocatedSize;
dest->managedSize = src->managedSize;
dest->allocationCount = src->allocationCount;
dest->peakAllocationCount = src->peakAllocationCount;
dest->largestFreeChunkSize = src->largestFreeChunkSize;
}
else
return FAILURE_T;
return SUCCESS_T;
}
return_t serialize_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02(NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS *src = pParams;
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02 *dest = (void*)(buffer);
NvU8 i;
if (src && dest && (src->poolCount <= NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX_v29_02))
{
dest->poolCount = src->poolCount;
dest->totalHeapSize= src->totalHeapSize;
for (i = 0; i < dest->poolCount; ++i)
{
portMemCopy(&dest->poolStats[i], sizeof(dest->poolStats[i]), &src->poolStats[i], sizeof(src->poolStats[i]));
}
}
else
return FAILURE_T;
return SUCCESS_T;
}
static
return_t deserialize_NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02(NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS *pParams,
NvU8 *buffer,
NvU32 bufferSize,
NvU32 *offset)
{
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_v29_02 *src = (void*)(buffer);
NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS *dest = pParams;
NvU8 i;
if (src && dest && (src->poolCount <= NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX_v29_02))
{
dest->poolCount = src->poolCount;
dest->totalHeapSize= src->totalHeapSize;
for (i = 0; i < dest->poolCount; ++i)
{
portMemCopy(&dest->poolStats[i], sizeof(dest->poolStats[i]), &src->poolStats[i], sizeof(src->poolStats[i]));
}
}
else
return FAILURE_T;
return SUCCESS_T;
}
#endif
#ifdef BUILD_COMMON_RPCS
static NV_STATUS static_data_copy(OBJRPCSTRUCTURECOPY *pObjRpcStructureCopy,
@@ -5952,7 +6392,7 @@ static NV_STATUS static_data_copy(OBJRPCSTRUCTURECOPY *pObjRpcStructureCopy,
if (status != NVOS_STATUS_SUCCESS) {
return status;
}
if (getIpVersion() < 0x26010000) {
goto end;
}
@@ -5967,6 +6407,20 @@ static NV_STATUS static_data_copy(OBJRPCSTRUCTURECOPY *pObjRpcStructureCopy,
return status;
}
if (getIpVersion() < 0x29050000) {
goto end;
}
NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset)
status = serialize_deserialize(NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS)(pObjRpcStructureCopy,
&pVSI->ccuSampleInfo,
buffer,
bufferSize,
offset);
if (status != NVOS_STATUS_SUCCESS) {
return status;
}
end:
return status;
}

1
src/nvidia/inc/kernel/vgpu/rpc.h
View File

@@ -73,6 +73,7 @@ typedef struct ContextDma ContextDma;
{ \
root_alloc_params.processID = pClient->ProcID; \
NV_ASSERT(root_alloc_params.processID == osGetCurrentProcess()); \
root_alloc_params.pOsPidInfo = (NvP64)(pClient->pOsPidInfo); \
} \
} \
else \

10
src/nvidia/inc/kernel/vgpu/rpc_global_enums.h
View File

@@ -222,7 +222,15 @@ enum {
X(RM, UPDATE_GPM_GUEST_BUFFER_INFO, 212)
X(RM, CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE, 213)
X(RM, CTRL_SET_ZBC_STENCIL_CLEAR, 214)
X(RM, NUM_FUNCTIONS, 215)
X(RM, CTRL_SUBDEVICE_GET_VGPU_HEAP_STATS, 215)
X(RM, CTRL_SUBDEVICE_GET_LIBOS_HEAP_STATS, 216)
X(RM, CTRL_DBG_SET_MODE_MMU_GCC_DEBUG, 217)
X(RM, CTRL_DBG_GET_MODE_MMU_GCC_DEBUG, 218)
X(RM, CTRL_RESERVE_HES, 219)
X(RM, CTRL_RELEASE_HES, 220)
X(RM, CTRL_RESERVE_CCU_PROF, 221)
X(RM, CTRL_RELEASE_CCU_PROF, 222)
X(RM, NUM_FUNCTIONS, 223)
#ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H
};
# undef X

7
src/nvidia/inc/kernel/vgpu/sdk-structures.h
View File

@@ -131,6 +131,7 @@ typedef struct vmiopd_SM_info {
#define NV0080_CTRL_GR_INFO_MAX_SIZE_24_02 (0x00000036)
#define NV0080_CTRL_GR_INFO_MAX_SIZE_24_03 (0x00000037)
#define NV0080_CTRL_GR_INFO_MAX_SIZE_24_07 (0x00000038)
#define NV0080_CTRL_GR_INFO_MAX_SIZE_29_00 (0x0000003A)
#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04 8
#define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1B_05 256
#define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03 240
@@ -217,6 +218,8 @@ typedef struct VGPU_BSP_CAPS
#define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1A_0F (0x00000033)
#define NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09 (0x00000034)
#define NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX_v29_02 (64)
//Maximum GMMU_FMT_LEVELS
#define GMMU_FMT_MAX_LEVELS_v05_00 5
#define GMMU_FMT_MAX_LEVELS_v1A_12 6
@@ -352,6 +355,7 @@ typedef struct _VGPU_STATIC_PROPERTIES
NvU32 channelCount;
NvBool bPblObjNotPresent; //Valid only in case of GA100 SRIOV Heavy
NvU64 vmmuSegmentSize;
NvU32 firstAsyncCEIdx;
} VGPU_STATIC_PROPERTIES;
struct _vgpu_static_info
@@ -434,6 +438,7 @@ struct _vgpu_static_info
NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS busGetPcieReqAtomicsCaps;
NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS masterGetVfErrCntIntMsk;
GPU_EXEC_SYSPIPE_INFO execSyspipeInfo;
NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS ccuSampleInfo;
};
typedef struct _vgpu_static_info VGPU_STATIC_INFO, VGPU_STATIC_INFO2;
@@ -455,7 +460,7 @@ ct_assert(NV2080_CTRL_FB_FS_INFO_MAX_QUERIES == NV2080_CTRL_FB_FS_INFO_MAX_QUERI
ct_assert(NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE == NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D);
ct_assert(NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES == NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D);
ct_assert(NV2080_CTRL_GRMGR_MAX_SMC_IDS == NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D);
ct_assert((NV0080_CTRL_GR_INFO_INDEX_MAX + 1) == NV0080_CTRL_GR_INFO_MAX_SIZE_24_07);
ct_assert((NV0080_CTRL_GR_INFO_INDEX_MAX + 1) == NV0080_CTRL_GR_INFO_MAX_SIZE_29_00);
ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_ENGINES == NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04);
ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_SM == NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03);
ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_GPC == NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03);

4
src/nvidia/inc/kernel/vgpu/vgpu_events.h
View File

@@ -156,9 +156,6 @@ struct _object_vgpu
VGPU_MEM_INFO debugBuff;
NvBool bGspPlugin;
NvBool bIsBar2Physical;
// Start offset of FB to use in Physical BAR2 mode
NvU64 allocFbOffsetBar2Physical;
// Message sequence counter
NvU32 sequence_base;
@@ -236,6 +233,7 @@ typedef struct vgpu_sysmem_pfn_bitmap_node {
NvU64 nodeEndPfn;
NvU64 sizeInBytes;
NvU32 index;
NvBool bAddedToBitmap;
ListNode listNode; // For intrusive lists
} VGPU_SYSMEM_PFN_BITMAP_NODE, * VGPU_SYSMEM_PFN_BITMAP_NODE_P;

13
src/nvidia/inc/kernel/vgpu/vgpu_version.h
View File

@@ -25,13 +25,13 @@
#define __vgpu_vgpu_version_h__
/* VGX interface version */
#define NV_RPC_VERSION_NUMBER_MAJOR 31:24 /* R---D */
#define NV_RPC_VERSION_NUMBER_MINOR 23:16 /* R---D */
#define NV_RPC_VERSION_NUMBER_MAJOR 31:24 /* R---D */
#define NV_RPC_VERSION_NUMBER_MINOR 23:16 /* R---D */
#define RPC_VERSION_FROM_VGX_VERSION(major, minor) (DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \
DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor))
#define VGX_MAJOR_VERSION_NUMBER 0x28
#define VGX_MINOR_VERSION_NUMBER 0x08
#define VGX_MAJOR_VERSION_NUMBER 0x29
#define VGX_MINOR_VERSION_NUMBER 0x09
#define VGX_MAJOR_VERSION_NUMBER_VGPU_12_0 0x1A
#define VGX_MINOR_VERSION_NUMBER_VGPU_12_0 0x18
@@ -53,7 +53,8 @@
* 2. This is the first break in migration compatibility after a release.
*/
#define NV_VGPU_GRIDSW_INTERNAL_TO_EXTERNAL_VERSION_MAPPING \
{{0x28, 0x00}, {0x28, 0x08}, {0x17, 0x01}}, \
{{0x29, 0x00}, {0x29, 0x09}, {0x18, 0x01}}, \
{{0x28, 0x00}, {0x28, 0x09}, {0x17, 0x01}}, \
{{0x27, 0x00}, {0x27, 0x06}, {0x16, 0x01}}, \
{{0x26, 0x00}, {0x26, 0x05}, {0x15, 0x01}}, \
{{0x25, 0x00}, {0x25, 0x1B}, {0x14, 0x01}}, \
@@ -104,7 +105,7 @@
/* WARNING: Should be updated with each vGPU release, if there is a break in
* migration compatibility during the development of that release. */
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x17
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x18
#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1
/* WARNING: Should be updated with each vGPU release, if minimum supported

87
src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h
View File

@@ -50,44 +50,61 @@ typedef struct
VM_ID guestVmId;
} SET_GUEST_ID_PARAMS;
/* This structure stores per vGPU instance supported placement information */
typedef struct
{
/* For Heterogeneous vGPU mode only */
NvU16 heterogeneousSupportedPlacementId;
NvU16 heterogeneousSupportedChidOffset;
/* For Homogeneous vGPU placement mode only */
NvU16 homogeneousSupportedPlacementId;
NvU16 homogeneousSupportedChidOffset;
} VGPU_INSTANCE_SUPPORTED_PLACEMENT_INFO;
/* This structure stores per vGPU type's placement information */
typedef struct
{
NvU32 placementSize;
NvU32 channelCount;
VGPU_INSTANCE_SUPPORTED_PLACEMENT_INFO vgpuInstanceSupportedPlacementInfo[MAX_VGPU_DEVICES_PER_PGPU];
NvU16 heterogeneousPlacementCount;
NvU16 homogeneousPlacementCount;
} VGPU_TYPE_SUPPORTED_PLACEMENT_INFO;
/* This structure represents the vGPU type's attributes */
typedef struct
{
NvU32 vgpuTypeId;
NvU8 vgpuName[VGPU_STRING_BUFFER_SIZE];
NvU8 vgpuClass[VGPU_STRING_BUFFER_SIZE];
NvU8 license[NV_GRID_LICENSE_INFO_MAX_LENGTH];
NvU8 licensedProductName[NV_GRID_LICENSE_INFO_MAX_LENGTH];
NvU32 placementSize;
NvU16 supportedPlacementIds[MAX_VGPU_DEVICES_PER_PGPU];
NvU32 supportedChidOffsets[MAX_VGPU_DEVICES_PER_PGPU];
NvU32 channelCount;
NvU32 placementCount;
NvU32 maxInstance;
NvU32 numHeads;
NvU32 maxResolutionX;
NvU32 maxResolutionY;
NvU32 maxPixels;
NvU32 frlConfig;
NvU32 cudaEnabled;
NvU32 eccSupported;
NvU32 gpuInstanceSize;
NvU32 multiVgpuSupported;
NvU64 vdevId NV_ALIGN_BYTES(8);
NvU64 pdevId NV_ALIGN_BYTES(8);
NvU64 profileSize NV_ALIGN_BYTES(8);
NvU64 fbLength NV_ALIGN_BYTES(8);
NvU64 gspHeapSize NV_ALIGN_BYTES(8);
NvU64 fbReservation NV_ALIGN_BYTES(8);
NvU64 mappableVideoSize NV_ALIGN_BYTES(8);
NvU32 encoderCapacity;
NvU64 bar1Length NV_ALIGN_BYTES(8);
NvU32 frlEnable;
NvU32 gpuDirectSupported;
NvU32 nvlinkP2PSupported;
NvU32 multiVgpuExclusive;
NvU8 vgpuExtraParams[VGPU_CONFIG_PARAMS_MAX_LENGTH];
NvU8 vgpuSignature[VGPU_SIGNATURE_SIZE];
NvU32 vgpuTypeId;
NvU8 vgpuName[VGPU_STRING_BUFFER_SIZE];
NvU8 vgpuClass[VGPU_STRING_BUFFER_SIZE];
NvU8 license[NV_GRID_LICENSE_INFO_MAX_LENGTH];
NvU8 licensedProductName[NV_GRID_LICENSE_INFO_MAX_LENGTH];
VGPU_TYPE_SUPPORTED_PLACEMENT_INFO vgpuTypeSupportedPlacementInfo;
NvU32 maxInstance;
NvU32 numHeads;
NvU32 maxResolutionX;
NvU32 maxResolutionY;
NvU32 maxPixels;
NvU32 frlConfig;
NvU32 cudaEnabled;
NvU32 eccSupported;
NvU32 gpuInstanceSize;
NvU32 multiVgpuSupported;
NvU64 vdevId NV_ALIGN_BYTES(8);
NvU64 pdevId NV_ALIGN_BYTES(8);
NvU64 profileSize NV_ALIGN_BYTES(8);
NvU64 fbLength NV_ALIGN_BYTES(8);
NvU64 gspHeapSize NV_ALIGN_BYTES(8);
NvU64 fbReservation NV_ALIGN_BYTES(8);
NvU64 mappableVideoSize NV_ALIGN_BYTES(8);
NvU32 encoderCapacity;
NvU64 bar1Length NV_ALIGN_BYTES(8);
NvU32 frlEnable;
NvU32 gpuDirectSupported;
NvU32 nvlinkP2PSupported;
NvU32 multiVgpuExclusive;
NvU8 vgpuExtraParams[VGPU_CONFIG_PARAMS_MAX_LENGTH];
NvU8 vgpuSignature[VGPU_SIGNATURE_SIZE];
} VGPU_TYPE;
MAKE_LIST(VGPU_TYPE_LIST, VGPU_TYPE);