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This commit is contained in:
Andy Ritger
2022-11-10 08:39:33 -08:00
parent 7c345b838b
commit 758b4ee818
1323 changed files with 262135 additions and 60754 deletions
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54
src/common/nvswitch/kernel/inc/common_nvswitch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -152,6 +152,17 @@ static NV_INLINE void nvswitch_clear_flags(NvU32 *val, NvU32 flags)
nvswitch_inforom_bbx_add_sxid(_d, _sxid, 0, 0, 0); \
} while(0)
#define NVSWITCH_PRINT_SXID_NO_BBX(_d, _sxid, _fmt, ...) \
do \
{ \
NVSWITCH_ASSERT(nvswitch_translate_hw_error(_sxid) != NVSWITCH_NVLINK_HW_GENERIC); \
nvswitch_os_print(NVSWITCH_DBG_LEVEL_ERROR, \
"nvidia-%s: SXid (PCI:" NVLINK_PCI_DEV_FMT "): %05d, " _fmt, \
(_d)->name, NVLINK_PCI_DEV_FMT_ARGS(&(_d)->nvlink_device->pciInfo), _sxid, \
##__VA_ARGS__); \
nvswitch_lib_smbpbi_log_sxid(_d, _sxid, _fmt, ##__VA_ARGS__); \
} while(0)
#define NVSWITCH_DEV_CMD_DISPATCH_WITH_PRIVATE_DATA(cmd, function, type, private)\
case cmd: \
{ \
@@ -189,18 +200,9 @@ static NV_INLINE void nvswitch_clear_flags(NvU32 *val, NvU32 flags)
#define NVSWITCH_MODS_CMDS_SUPPORTED NV_FALSE
#if defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS)
#define NVSWITCH_TEST_CMDS_SUPPORTED NV_TRUE
#else
#define NVSWITCH_TEST_CMDS_SUPPORTED NV_FALSE
#endif
#define NVSWITCH_DEV_CMD_DISPATCH_MODS(cmd, function, type) \
NVSWITCH_DEV_CMD_DISPATCH_HELPER(cmd, NVSWITCH_MODS_CMDS_SUPPORTED, function, type)
#define NVSWITCH_DEV_CMD_DISPATCH_TEST(cmd, function, type) \
NVSWITCH_DEV_CMD_DISPATCH_HELPER(cmd, NVSWITCH_TEST_CMDS_SUPPORTED, function, type)
#define NVSWITCH_MAX_NUM_LINKS 100
#if NVSWITCH_MAX_NUM_LINKS <= 100
#define NVSWITCH_LINK_INSTANCE_LEN 2
@@ -251,9 +253,13 @@ typedef struct
NvU32 select_uphy_tables;
NvU32 link_training_mode;
NvU32 i2c_access_control;
NvU32 force_kernel_i2c;
NvU32 link_recal_settings;
NvU32 crc_bit_error_rate_short;
NvU32 crc_bit_error_rate_long;
NvU32 lp_threshold;
NvU32 minion_intr;
NvU32 surpress_link_errors_for_gpu_reset;
} NVSWITCH_REGKEY_TYPE;
//
@@ -261,14 +267,28 @@ typedef struct
//
typedef struct NVSWITCH_TASK
{
struct NVSWITCH_TASK *prev;
struct NVSWITCH_TASK *next;
void (*task_fn)(nvswitch_device *);
void (*task_fn_vdptr)(nvswitch_device *, void *);
void (*task_fn_devptr)(nvswitch_device *);
void *task_args;
NvU64 period_nsec;
NvU64 last_run_nsec;
NvU32 flags;
} NVSWITCH_TASK_TYPE;
#define NVSWITCH_TASK_TYPE_FLAGS_ALWAYS_RUN 0x1 // Run even the if not initialized
#define NVSWITCH_TASK_TYPE_FLAGS_RUN_EVEN_IF_DEVICE_NOT_INITIALIZED 0x1 // Run even the if not initialized
#define NVSWITCH_TASK_TYPE_FLAGS_RUN_ONCE 0x2 // Only run the task once. Memory for task struct and args will be freed by dispatcher after running.
#define NVSWITCH_TASK_TYPE_FLAGS_VOID_PTR_ARGS 0x4 // Function accepts args as void * args.
//
// Wrapper struct for deffered SXID errors
//
typedef struct
{
NvU32 nvlipt_instance;
NvU32 link;
} NVSWITCH_DEFERRED_ERROR_REPORTING_ARGS;
//
// PLL
@@ -487,6 +507,7 @@ typedef struct NVSWITCH_TIMEOUT
#define NVSWITCH_INTERVAL_50USEC_IN_NS 50000LL
#define NVSWITCH_INTERVAL_1MSEC_IN_NS 1000000LL
#define NVSWITCH_INTERVAL_5MSEC_IN_NS 5000000LL
#define NVSWITCH_INTERVAL_750MSEC_IN_NS 750000000LL
#define NVSWITCH_INTERVAL_1SEC_IN_NS 1000000000LL
#define NVSWITCH_INTERVAL_4SEC_IN_NS 4000000000LL
@@ -516,8 +537,12 @@ void nvswitch_reg_write_32(nvswitch_device *device, NvU32 offset, NvU32 data);
NvU64 nvswitch_read_64bit_counter(nvswitch_device *device, NvU32 lo_offset, NvU32 hi_offset);
void nvswitch_timeout_create(NvU64 timeout_ns, NVSWITCH_TIMEOUT *time);
NvBool nvswitch_timeout_check(NVSWITCH_TIMEOUT *time);
void nvswitch_task_create(nvswitch_device *device,
void (*task_fn)(nvswitch_device *device), NvU64 period_nsec, NvU32 flags);
NvlStatus nvswitch_task_create(nvswitch_device *device,
void (*task_fn)(nvswitch_device *device),
NvU64 period_nsec, NvU32 flags);
NvlStatus nvswitch_task_create_args(nvswitch_device* device, void *fn_args,
void (*task_fn)(nvswitch_device* device, void *fn_args),
NvU64 period_nsec, NvU32 flags);
void nvswitch_tasks_destroy(nvswitch_device *device);
void nvswitch_free_chipdevice(nvswitch_device *device);
@@ -535,6 +560,7 @@ void nvswitch_reset_persistent_link_hw_state(nvswitch_device *device, NvU32
void nvswitch_store_topology_information(nvswitch_device *device, nvlink_link *link);
NvlStatus nvswitch_launch_ALI(nvswitch_device *device);
NvlStatus nvswitch_launch_ALI_link_training(nvswitch_device *device, nvlink_link *link, NvBool bSync);
NvlStatus nvswitch_inband_read_data(nvswitch_device *device, NvU8 *dest, NvU32 linkId, NvU32 *dataSize);
void nvswitch_filter_messages(nvswitch_device *device, NvU32 linkId);
NvlStatus nvswitch_set_training_mode(nvswitch_device *device);

36
src/common/nvswitch/kernel/inc/haldef_nvswitch.h
View File

@@ -94,6 +94,8 @@
_op(NvlStatus, nvswitch_ctrl_set_latency_bins, (nvswitch_device *device, NVSWITCH_SET_LATENCY_BINS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_ingress_reqlinkid, (nvswitch_device *device, NVSWITCH_GET_INGRESS_REQLINKID_PARAMS *params), _arch) \
_op(NvU32, nvswitch_i2c_get_port_info, (nvswitch_device *device, NvU32 port), _arch) \
_op(NvlStatus, nvswitch_ctrl_register_read, (nvswitch_device *device, NVSWITCH_REGISTER_READ *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_register_write, (nvswitch_device *device, NVSWITCH_REGISTER_WRITE *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_i2c_indexed, (nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams), _arch) \
_op(NvlStatus, nvswitch_ctrl_therm_read_temperature, (nvswitch_device *device, NVSWITCH_CTRL_GET_TEMPERATURE_PARAMS *info), _arch) \
_op(NvlStatus, nvswitch_ctrl_therm_get_temperature_limit, (nvswitch_device *device, NVSWITCH_CTRL_GET_TEMPERATURE_LIMIT_PARAMS *info), _arch) \
@@ -122,7 +124,9 @@
_op(NvBool, nvswitch_is_smbpbi_supported, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_post_init_device_setup, (nvswitch_device *device), _arch) \
_op(void, nvswitch_post_init_blacklist_device_setup, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_setup_link_system_registers, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_setup_system_registers, (nvswitch_device *device), _arch) \
_op(void, nvswitch_setup_link_system_registers, (nvswitch_device *device, nvlink_link *link), _arch) \
_op(void, nvswitch_load_link_disable_settings, (nvswitch_device *device, nvlink_link *link), _arch) \
_op(NvlStatus, nvswitch_read_vbios_link_entries, (nvswitch_device *device, NvU32 tblPtr,NvU32 expected_link_entriesCount,NVLINK_CONFIG_DATA_LINKENTRY *link_entries, NvU32 *identified_link_entriesCount), _arch) \
_op(NvlStatus, nvswitch_vbios_read_structure, (nvswitch_device *device, void *structure, NvU32 offset, NvU32 *ppacked_size, const char *format), _arch) \
_op(NvlStatus, nvswitch_get_nvlink_ecc_errors, (nvswitch_device *device, NVSWITCH_GET_NVLINK_ECC_ERRORS_PARAMS *p), _arch) \
@@ -137,19 +141,25 @@
_op(void, nvswitch_load_uuid, (nvswitch_device *device), _arch) \
_op(void, nvswitch_i2c_set_hw_speed_mode, (nvswitch_device *device, NvU32 port, NvU32 speedMode), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_bios_info, (nvswitch_device *device, NVSWITCH_GET_BIOS_INFO_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_inforom_version, (nvswitch_device *device, NVSWITCH_GET_INFOROM_VERSION_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_read_oob_blacklist_state, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_write_fabric_state, (nvswitch_device *device), _arch) \
_op(void, nvswitch_initialize_oms_state, (nvswitch_device *device, INFOROM_OMS_STATE *pOmsState), _arch) \
_op(NvlStatus, nvswitch_oms_inforom_flush, (nvswitch_device *device), _arch) \
_op(void, nvswitch_inforom_ecc_get_total_errors, (nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, NvU64 *corCount, NvU64 *uncCount), _arch) \
_op(NvlStatus, nvswitch_bbx_setup_prologue, (nvswitch_device *device, void *pInforomBbxState), _arch) \
_op(NvlStatus, nvswitch_bbx_setup_epilogue, (nvswitch_device *device, void *pInforomBbxState), _arch) \
_op(NvlStatus, nvswitch_bbx_add_data_time, (nvswitch_device *device, void *pInforomBbxState, void *pInforomBbxData), _arch) \
_op(NvlStatus, nvswitch_bbx_add_sxid, (nvswitch_device *device, void *pInforomBbxState, void *pInforomBbxData), _arch) \
_op(NvlStatus, nvswitch_bbx_add_temperature, (nvswitch_device *device, void *pInforomBbxState, void *pInforomBbxData), _arch) \
_op(void, nvswitch_bbx_set_initial_temperature, (nvswitch_device *device, void *pInforomBbxState, void *pInforomBbxData), _arch) \
_op(NvlStatus, nvswitch_inforom_bbx_get_sxid, (nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_bbx_add_sxid, (nvswitch_device *device, NvU32 exceptionType, NvU32 data0, NvU32 data1, NvU32 data2), _arch) \
_op(NvlStatus, nvswitch_bbx_unload, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_bbx_load, (nvswitch_device *device, NvU64 time_ns, NvU8 osType, NvU32 osVersion), _arch) \
_op(NvlStatus, nvswitch_bbx_get_sxid, (nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS * params), _arch) \
_op(NvlStatus, nvswitch_smbpbi_alloc, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_smbpbi_post_init_hal, (nvswitch_device *device), _arch) \
_op(void, nvswitch_smbpbi_destroy_hal, (nvswitch_device *device), _arch) \
_op(void, nvswitch_smbpbi_send_unload, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_smbpbi_dem_load, (nvswitch_device *device), _arch) \
_op(void, nvswitch_smbpbi_dem_flush, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_smbpbi_get_dem_num_messages, (nvswitch_device *device, NvU8 *pMsgCount), _arch) \
_op(void, nvswitch_smbpbi_log_message, (nvswitch_device *device, NvU32 num, NvU32 msglen, NvU8 *osErrorString), _arch) \
_op(NvlStatus, nvswitch_smbpbi_send_init_data, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_set_minion_initialized, (nvswitch_device *device, NvU32 idx_minion, NvBool initialized), _arch) \
_op(NvBool, nvswitch_is_minion_initialized, (nvswitch_device *device, NvU32 idx_minion), _arch) \
_op(NvlStatus, nvswitch_get_link_public_id, (nvswitch_device *device, NvU32 linkId, NvU32 *publicId), _arch) \
@@ -206,13 +216,19 @@
_op(void, nvswitch_apply_recal_settings, (nvswitch_device *device, nvlink_link *), _arch) \
_op(NvlStatus, nvswitch_service_nvldl_fatal_link, (nvswitch_device *device, NvU32 nvliptInstance, NvU32 link), _arch) \
_op(NvlStatus, nvswitch_service_minion_link, (nvswitch_device *device, NvU32 link_id), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_sw_info, (nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p), _arch)
_op(NvlStatus, nvswitch_ctrl_get_sw_info, (nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_err_info, (nvswitch_device *device, NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS *ret), _arch) \
_op(NvlStatus, nvswitch_ctrl_clear_counters, (nvswitch_device *device, NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS *ret), _arch)
#define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \
_op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_launch_ALI_link_training, (nvswitch_device *device, nvlink_link *link), _arch) \
_op(NvlStatus, nvswitch_launch_ALI_link_training, (nvswitch_device *device, nvlink_link *link, NvBool bSync), _arch) \
_op(NvlStatus, nvswitch_ctrl_inband_send_data, (nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_inband_read_data, (nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p), _arch) \
_op(void, nvswitch_send_inband_nack, (nvswitch_device *device, NvU32 *msghdr, NvU32 linkId), _arch) \
_op(NvU32, nvswitch_get_max_persistent_message_count, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_ctrl_set_mc_rid_table, (nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_mc_rid_table, (nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_set_residency_bins, (nvswitch_device *device, NVSWITCH_SET_RESIDENCY_BINS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_residency_bins, (nvswitch_device *device, NVSWITCH_GET_RESIDENCY_BINS *p), _arch) \
_op(NvlStatus, nvswitch_ctrl_get_rb_stall_busy, (nvswitch_device *device, NVSWITCH_GET_RB_STALL_BUSY *p), _arch) \

17
src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h
View File

@@ -46,6 +46,20 @@
(destName)[2] = (srcName)[2]; \
}
//
// OS type defines.
//
#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_TYPE_OTHER 0x0
#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_TYPE_WIN9X 0x1
#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_TYPE_WIN2K 0x2
#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_TYPE_WIN 0x4
#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_TYPE_UNIX 0x5
#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_MAJOR 7:0
#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_MINOR 15:8
#define INFOROM_BBX_OBJ_V1_00_SYSTEM_OS_BUILD 31:16
struct INFOROM_OBJECT_CACHE_ENTRY
{
INFOROM_OBJECT_HEADER_V1_00 header;
@@ -110,6 +124,7 @@ NvlStatus nvswitch_inforom_load_object(nvswitch_device* device,
const char *pObjectFormat, NvU8 *pPackedObject, void *pObject);
void nvswitch_inforom_read_static_data(nvswitch_device *device,
struct inforom *pInforom, RM_SOE_SMBPBI_INFOROM_DATA *pData);
void nvswitch_inforom_string_copy(inforom_U008 *pSrc, NvU8 *pDst, NvU32 size);
// InfoROM RO APIs
NvlStatus nvswitch_inforom_read_only_objects_load(nvswitch_device *device);
@@ -151,8 +166,6 @@ void nvswitch_inforom_bbx_unload(nvswitch_device * device);
NvlStatus nvswitch_inforom_bbx_add_sxid(nvswitch_device *device,
NvU32 exceptionType, NvU32 data0,
NvU32 data1, NvU32 data2);
void nvswitch_bbx_collect_current_time(nvswitch_device *device,
void *pBbxState);
NvlStatus nvswitch_inforom_bbx_get_sxid(nvswitch_device *device,
NVSWITCH_GET_SXIDS_PARAMS *params);

12
src/common/nvswitch/kernel/inc/io_nvswitch.h
View File

@@ -125,7 +125,6 @@ typedef struct engine_descriptor
_op(PTIMER) \
_op(CPR) \
_op(TILEOUT) \
_op(TILEOUT_PERFMON) \
#define NVSWITCH_LIST_ALL_ENGINES(_op) \
_op(XVE) \
@@ -150,11 +149,6 @@ typedef struct engine_descriptor
_op(NPORT_PERFMON) \
\
_op(NVLW_PERFMON) \
_op(RX_PERFMON) \
_op(TX_PERFMON) \
\
_op(NXBAR_PERFMON) \
_op(TILE_PERFMON) \
#define ENGINE_ID_LIST(_eng) \
NVSWITCH_ENGINE_ID_##_eng,
@@ -360,12 +354,6 @@ typedef struct
NvBool bIsRepeaterMode;
// Check if BUFFER_COMPLETE is seen
volatile NvBool isBufferComplete;
// Check if BUFFER_FAIL is seen
volatile NvBool isBufferFail;
// Minion Inband Data structure
nvswitch_inband_receive_data inbandData;

56
src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h
View File

@@ -108,56 +108,36 @@ nvswitch_oms_inforom_flush_lr10
struct nvswitch_device *device
);
NvlStatus
nvswitch_bbx_setup_prologue_lr10
(
nvswitch_device *device,
void *pInforomBbxState
);
NvlStatus
nvswitch_bbx_setup_epilogue_lr10
(
nvswitch_device *device,
void *pInforomBbxState
);
NvlStatus
nvswitch_bbx_add_data_time_lr10
(
nvswitch_device *device,
void *pInforomBbxState,
void *pInforomBbxData
);
NvlStatus
nvswitch_bbx_add_sxid_lr10
(
nvswitch_device *device,
void *pInforomBbxState,
void *pInforomBbxData
NvU32 exceptionType,
NvU32 data0,
NvU32 data1,
NvU32 data2
);
NvlStatus
nvswitch_bbx_add_temperature_lr10
nvswitch_bbx_unload_lr10
(
nvswitch_device *device,
void *pInforomBbxState,
void *pInforomBbxData
);
void
nvswitch_bbx_set_initial_temperature_lr10
(
nvswitch_device *device,
void *pInforomBbxState,
void *pInforomBbxData
nvswitch_device *device
);
NvlStatus
nvswitch_inforom_bbx_get_sxid_lr10
nvswitch_bbx_load_lr10
(
nvswitch_device *device,
NVSWITCH_GET_SXIDS_PARAMS *params
NvU64 time_ns,
NvU8 osType,
NvU32 osVersion
);
NvlStatus
nvswitch_bbx_get_sxid_lr10
(
nvswitch_device *device,
NVSWITCH_GET_SXIDS_PARAMS * params
);
#endif //_INFOROM_LR10_H_

16
src/common/nvswitch/kernel/inc/lr10/lr10.h
View File

@@ -470,11 +470,6 @@ typedef struct
_op(NPORT_PERFMON, _MULTICAST_BCAST) \
\
_op(NVLW_PERFMON, _BCAST) \
_op(RX_PERFMON, _MULTICAST_BCAST) \
_op(TX_PERFMON, _MULTICAST_BCAST) \
\
_op(NXBAR_PERFMON, _BCAST) \
_op(TILE_PERFMON, _MULTICAST_BCAST) \
typedef struct
{
@@ -648,11 +643,20 @@ NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_lr10(nvswitch_device *device, NVS
NvlStatus nvswitch_service_nvldl_fatal_link_lr10(nvswitch_device *device, NvU32 nvliptInstance, NvU32 link);
NvlStatus nvswitch_ctrl_inband_send_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p);
NvlStatus nvswitch_ctrl_inband_read_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p);
NvlStatus nvswitch_launch_ALI_link_training_lr10(nvswitch_device *device, nvlink_link *link);
void nvswitch_send_inband_nack_lr10(nvswitch_device *device, NvU32 *msghdr, NvU32 linkId);
NvU32 nvswitch_get_max_persistent_message_count_lr10(nvswitch_device *device);
NvlStatus nvswitch_launch_ALI_link_training_lr10(nvswitch_device *device, nvlink_link *link, NvBool bSync);
NvlStatus nvswitch_service_minion_link_lr10(nvswitch_device *device, NvU32 nvliptInstance);
void nvswitch_apply_recal_settings_lr10(nvswitch_device *device, nvlink_link *link);
NvlStatus nvswitch_ctrl_get_sw_info_lr10(nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p);
void nvswitch_setup_link_system_registers_lr10(nvswitch_device *device, nvlink_link *link);
void nvswitch_load_link_disable_settings_lr10(nvswitch_device *device, nvlink_link *link);
NvBool nvswitch_is_smbpbi_supported_lr10(nvswitch_device *device);
NvlStatus nvswitch_ctrl_set_mc_rid_table_lr10(nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p);
NvlStatus nvswitch_ctrl_get_mc_rid_table_lr10(nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p);
NvlStatus nvswitch_launch_ALI_lr10(nvswitch_device *device);
NvlStatus nvswitch_ctrl_get_bios_info_lr10(nvswitch_device *device, NVSWITCH_GET_BIOS_INFO_PARAMS *p);
#endif //_LR10_H_

59
src/common/nvswitch/kernel/inc/lr10/smbpbi_lr10.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,6 +24,24 @@
#ifndef _SMBPBI_LR10_H_
#define _SMBPBI_LR10_H_
NvlStatus
nvswitch_smbpbi_alloc_lr10
(
nvswitch_device *device
);
NvlStatus
nvswitch_smbpbi_post_init_hal_lr10
(
nvswitch_device *device
);
void
nvswitch_smbpbi_destroy_hal_lr10
(
nvswitch_device *device
);
NvlStatus
nvswitch_smbpbi_get_dem_num_messages_lr10
(
@@ -31,4 +49,43 @@ nvswitch_smbpbi_get_dem_num_messages_lr10
NvU8 *pMsgCount
);
NvlStatus
nvswitch_inforom_dem_load_lr10
(
nvswitch_device *device
);
NvlStatus
nvswitch_smbpbi_dem_load_lr10
(
nvswitch_device *device
);
void
nvswitch_smbpbi_send_unload_lr10
(
nvswitch_device *device
);
void
nvswitch_smbpbi_dem_flush_lr10
(
nvswitch_device *device
);
void
nvswitch_smbpbi_log_message_lr10
(
nvswitch_device *device,
NvU32 num,
NvU32 msglen,
NvU8 *osErrorString
);
NvlStatus
nvswitch_smbpbi_send_init_data_lr10
(
nvswitch_device *device
);
#endif //_SMBPBI_LR10_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _CLOCK_LS10_H_
#define _CLOCK_LS10_H_
NvlStatus
nvswitch_init_pll_config_ls10
(
nvswitch_device *device
);
NvlStatus
nvswitch_init_pll_ls10
(
nvswitch_device *device
);
void
nvswitch_init_clock_gating_ls10
(
nvswitch_device *device
);
#endif //_CLOCK_LS10_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _GFW_LS10_H_
#define _GFW_LS10_H_
#include "nvswitch/ls10/dev_nvlsaw_ip.h"
#include "nvswitch/ls10/dev_therm.h"
#include "nvswitch/ls10/dev_fsp_pri.h"
//
// Transcribed from GFW ucode r5 v1 scratch definition for LS10
//
#define NV_NVLSAW_SW_SCRATCH(_index) (NV_NVLSAW_SW_SCRATCH_0 + (_index)*4)
#define NV_NVLSAW_SW_BIOS_VERSION NV_NVLSAW_SW_SCRATCH(6)
#define NV_NVLSAW_SW_OEM_BIOS_VERSION NV_NVLSAW_SW_SCRATCH(7)
//-----------------------------------------------------------------------------
#define NV_GFW_GLOBAL_BOOT_PARTITION_PROGRESS NV_THERM_I2CS_SCRATCH
#define NV_GFW_GLOBAL_BOOT_PARTITION_PROGRESS_VALUE 7:0
#define NV_GFW_GLOBAL_BOOT_PARTITION_PROGRESS_VALUE_SUCCESS 0x000000FF
#define NV_NVLSAW_SW_OEM_BIOS_VERSION_BOARD_ID 31:16
#endif //_GFW_LS10_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _INFOROM_LS10_H_
#define _INFOROM_LS10_H_
NvlStatus nvswitch_inforom_nvl_log_error_event_ls10
(
nvswitch_device *device,
void *pNvlGeneric,
void *pNvlErrorEvent,
NvBool *bDirty
);
NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_ls10
(
nvswitch_device *device,
void *pNvlGeneric,
void *pData,
NvU8 linkId,
NvU8 nvliptInstance,
NvU8 localLinkIdx,
void *pNvlErrorCounts,
NvBool *bDirty
);
void
nvswitch_initialize_oms_state_ls10
(
nvswitch_device *device,
INFOROM_OMS_STATE *pOmsState
);
NvBool
nvswitch_oms_get_device_disable_ls10
(
INFOROM_OMS_STATE *pOmsState
);
void
nvswitch_oms_set_device_disable_ls10
(
INFOROM_OMS_STATE *pOmsState,
NvBool bForceDeviceDisable
);
NvlStatus
nvswitch_oms_inforom_flush_ls10
(
struct nvswitch_device *device
);
void
nvswitch_inforom_ecc_get_total_errors_ls10
(
nvswitch_device *device,
INFOROM_ECC_OBJECT *pEccGeneric,
NvU64 *pCorrectedTotal,
NvU64 *pUncorrectedTotal
);
NvlStatus
nvswitch_bbx_add_sxid_ls10
(
nvswitch_device *device,
NvU32 exceptionType,
NvU32 data0,
NvU32 data1,
NvU32 data2
);
NvlStatus
nvswitch_bbx_unload_ls10
(
nvswitch_device *device
);
NvlStatus
nvswitch_bbx_load_ls10
(
nvswitch_device *device,
NvU64 time_ns,
NvU8 osType,
NvU32 osVersion
);
NvlStatus
nvswitch_bbx_get_sxid_ls10
(
nvswitch_device *device,
NVSWITCH_GET_SXIDS_PARAMS * params
);
#endif //_INFOROM_LS10_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _LS10_H_
#define _LS10_H_
#include "export_nvswitch.h"
#include "common_nvswitch.h"
#include "ctrl_dev_nvswitch.h"
#include "nvswitch/ls10/dev_master.h"
#define NVSWITCH_NUM_LINKS_LS10 64
#define NVSWITCH_NUM_LANES_LS10 2
#define NVSWITCH_LINKS_PER_MINION_LS10 4
#define NVSWITCH_LINKS_PER_NVLIPT_LS10 4
#define NVSWITCH_LINKS_PER_NVLW_LS10 4
#define NVSWITCH_LINKS_PER_NPG_LS10 4
#define NVSWITCH_NPORT_PER_NPG_LS10 NVSWITCH_LINKS_PER_NPG_LS10
#define NUM_PTOP_ENGINE_LS10 1
#define NUM_FUSE_ENGINE_LS10 1
#define NUM_GIN_ENGINE_LS10 1
#define NUM_JTAG_ENGINE_LS10 1
#define NUM_PMGR_ENGINE_LS10 1
#define NUM_SAW_ENGINE_LS10 1
#define NUM_ROM_ENGINE_LS10 1
#define NUM_EXTDEV_ENGINE_LS10 1
#define NUM_PTIMER_ENGINE_LS10 1
#define NUM_SOE_ENGINE_LS10 1
#define NUM_SMR_ENGINE_LS10 2
#define NUM_SE_ENGINE_LS10 1
#define NUM_THERM_ENGINE_LS10 1
#define NUM_XAL_ENGINE_LS10 1
#define NUM_XAL_FUNC_ENGINE_LS10 1
#define NUM_XTL_CONFIG_ENGINE_LS10 1
#define NUM_XPL_ENGINE_LS10 1
#define NUM_XTL_ENGINE_LS10 1
#define NUM_SYSCTRL_ENGINE_LS10 1
#define NUM_UXL_ENGINE_LS10 1
#define NUM_GPU_PTOP_ENGINE_LS10 1
#define NUM_PMC_ENGINE_LS10 1
#define NUM_PBUS_ENGINE_LS10 1
#define NUM_ROM2_ENGINE_LS10 1
#define NUM_GPIO_ENGINE_LS10 1
#define NUM_FSP_ENGINE_LS10 1
#define NUM_CLKS_SYS_ENGINE_LS10 1
#define NUM_CLKS_SYSB_ENGINE_LS10 1
#define NUM_CLKS_P0_ENGINE_LS10 4
#define NUM_CLKS_P0_BCAST_ENGINE_LS10 1
#define NUM_SAW_PM_ENGINE_LS10 1
#define NUM_PCIE_PM_ENGINE_LS10 1
#define NUM_PRT_PRI_HUB_ENGINE_LS10 16
#define NUM_PRT_PRI_RS_CTRL_ENGINE_LS10 16
#define NUM_PRT_PRI_HUB_BCAST_ENGINE_LS10 1
#define NUM_PRT_PRI_RS_CTRL_BCAST_ENGINE_LS10 1
#define NUM_SYS_PRI_HUB_ENGINE_LS10 1
#define NUM_SYS_PRI_RS_CTRL_ENGINE_LS10 1
#define NUM_SYSB_PRI_HUB_ENGINE_LS10 1
#define NUM_SYSB_PRI_RS_CTRL_ENGINE_LS10 1
#define NUM_PRI_MASTER_RS_ENGINE_LS10 1
#define NUM_NPG_ENGINE_LS10 16
#define NUM_NPG_PERFMON_ENGINE_LS10 NUM_NPG_ENGINE_LS10
#define NUM_NPORT_ENGINE_LS10 (NUM_NPG_ENGINE_LS10 * NVSWITCH_NPORT_PER_NPG_LS10)
#define NUM_NPORT_MULTICAST_ENGINE_LS10 NUM_NPG_ENGINE_LS10
#define NUM_NPORT_PERFMON_ENGINE_LS10 NUM_NPORT_ENGINE_LS10
#define NUM_NPORT_PERFMON_MULTICAST_ENGINE_LS10 NUM_NPG_ENGINE_LS10
#define NUM_NPG_BCAST_ENGINE_LS10 1
#define NUM_NPG_PERFMON_BCAST_ENGINE_LS10 NUM_NPG_BCAST_ENGINE_LS10
#define NUM_NPORT_BCAST_ENGINE_LS10 NVSWITCH_NPORT_PER_NPG_LS10
#define NUM_NPORT_MULTICAST_BCAST_ENGINE_LS10 NUM_NPG_BCAST_ENGINE_LS10
#define NUM_NPORT_PERFMON_BCAST_ENGINE_LS10 NUM_NPORT_BCAST_ENGINE_LS10
#define NUM_NPORT_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NPG_BCAST_ENGINE_LS10
#define NUM_NVLW_ENGINE_LS10 16
#define NUM_NVLIPT_ENGINE_LS10 NUM_NVLW_ENGINE_LS10
#define NUM_MINION_ENGINE_LS10 NUM_NVLW_ENGINE_LS10
#define NUM_PLL_ENGINE_LS10 NUM_NVLW_ENGINE_LS10
#define NUM_CPR_ENGINE_LS10 NUM_NVLW_ENGINE_LS10
#define NUM_NVLW_PERFMON_ENGINE_LS10 NUM_NVLW_ENGINE_LS10
#define NUM_NVLIPT_SYS_PERFMON_ENGINE_LS10 NUM_NVLW_ENGINE_LS10
#define NUM_NVLDL_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10
#define NUM_NVLTLC_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10
#define NUM_NVLIPT_LNK_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10
#define NUM_SYS_PERFMON_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10
#define NUM_TX_PERFMON_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10
#define NUM_RX_PERFMON_MULTICAST_ENGINE_LS10 NUM_NVLW_ENGINE_LS10
#define NUM_NVLDL_ENGINE_LS10 (NUM_NVLW_ENGINE_LS10 * NVSWITCH_LINKS_PER_NVLIPT_LS10)
#define NUM_NVLTLC_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10
#define NUM_NVLIPT_LNK_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10
#define NUM_SYS_PERFMON_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10
#define NUM_TX_PERFMON_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10
#define NUM_RX_PERFMON_ENGINE_LS10 NUM_NVLDL_ENGINE_LS10
#define NUM_NVLW_BCAST_ENGINE_LS10 1
#define NUM_NVLIPT_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10
#define NUM_MINION_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10
#define NUM_PLL_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10
#define NUM_CPR_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10
#define NUM_NVLW_PERFMON_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10
#define NUM_NVLIPT_SYS_PERFMON_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10
#define NUM_NVLDL_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10
#define NUM_NVLTLC_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10
#define NUM_NVLIPT_LNK_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10
#define NUM_SYS_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10
#define NUM_TX_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10
#define NUM_RX_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NVLW_BCAST_ENGINE_LS10
#define NUM_NVLDL_BCAST_ENGINE_LS10 NVSWITCH_LINKS_PER_NVLIPT_LS10
#define NUM_NVLTLC_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10
#define NUM_NVLIPT_LNK_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10
#define NUM_SYS_PERFMON_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10
#define NUM_TX_PERFMON_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10
#define NUM_RX_PERFMON_BCAST_ENGINE_LS10 NUM_NVLDL_BCAST_ENGINE_LS10
#define NUM_NXBAR_ENGINE_LS10 3
#define NUM_NXBAR_PERFMON_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10
#define NUM_TILE_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10
#define NUM_TILE_PERFMON_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10
#define NUM_TILE_ENGINE_LS10 (12 * NUM_NXBAR_ENGINE_LS10)
#define NUM_TILE_PERFMON_ENGINE_LS10 NUM_TILE_ENGINE_LS10
#define NUM_TILEOUT_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10
#define NUM_TILEOUT_PERFMON_MULTICAST_ENGINE_LS10 NUM_NXBAR_ENGINE_LS10
#define NUM_TILEOUT_ENGINE_LS10 NUM_TILE_ENGINE_LS10
#define NUM_TILEOUT_PERFMON_ENGINE_LS10 NUM_TILE_ENGINE_LS10
#define NUM_NXBAR_BCAST_ENGINE_LS10 1
#define NUM_NXBAR_PERFMON_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10
#define NUM_TILE_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10
#define NUM_TILE_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10
#define NUM_TILE_BCAST_ENGINE_LS10 12
#define NUM_TILE_PERFMON_BCAST_ENGINE_LS10 NUM_TILE_BCAST_ENGINE_LS10
#define NUM_TILEOUT_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10
#define NUM_TILEOUT_PERFMON_MULTICAST_BCAST_ENGINE_LS10 NUM_NXBAR_BCAST_ENGINE_LS10
#define NUM_TILEOUT_BCAST_ENGINE_LS10 NUM_TILE_BCAST_ENGINE_LS10
#define NUM_TILEOUT_PERFMON_BCAST_ENGINE_LS10 NUM_TILE_BCAST_ENGINE_LS10
#define NUM_MAX_MCFLA_SLOTS_LS10 128
#define NPORT_TO_LINK_LS10(_device, _npg, _nport) \
( \
NVSWITCH_ASSERT((_npg < NUM_NPG_ENGINE_LS10)) \
, \
NVSWITCH_ASSERT((_nport < NVSWITCH_NPORT_PER_NPG_LS10)) \
, \
((_npg) * NVSWITCH_NPORT_PER_NPG_LS10 + (_nport)) \
)
#define NVSWITCH_NUM_LINKS_PER_NVLIPT_LS10 (NVSWITCH_NUM_LINKS_LS10/NUM_NVLIPT_ENGINE_LS10)
#define NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(_physlinknum) \
((_physlinknum)%NVSWITCH_NUM_LINKS_PER_NVLIPT_LS10)
#define NVSWITCH_NVLIPT_GET_LOCAL_LINK_MASK64_LS10(_nvlipt_idx) \
(NVBIT64(NVSWITCH_LINKS_PER_NVLIPT_LS10) - 1) << (_nvlipt_idx * NVSWITCH_LINKS_PER_NVLIPT_LS10);
#define DMA_ADDR_WIDTH_LS10 64
//
// Helpful IO wrappers
//
#define NVSWITCH_NPORT_WR32_LS10(_d, _engidx, _dev, _reg, _data) \
NVSWITCH_ENG_WR32(_d, NPORT, , _engidx, _dev, _reg, _data)
#define NVSWITCH_NPORT_RD32_LS10(_d, _engidx, _dev, _reg) \
NVSWITCH_ENG_RD32(_d, NPORT, , _engidx, _dev, _reg)
#define NVSWITCH_MINION_WR32_LS10(_d, _engidx, _dev, _reg, _data) \
NVSWITCH_ENG_WR32(_d, MINION, , _engidx, _dev, _reg, _data)
#define NVSWITCH_MINION_RD32_LS10(_d, _engidx, _dev, _reg) \
NVSWITCH_ENG_RD32(_d, MINION, , _engidx, _dev, _reg)
#define NVSWITCH_MINION_WR32_BCAST_LS10(_d, _dev, _reg, _data) \
NVSWITCH_ENG_WR32(_d, MINION, _BCAST, 0, _dev, _reg, _data)
#define NVSWITCH_NPG_WR32_LS10(_d, _engidx, _dev, _reg, _data) \
NVSWITCH_ENG_WR32(_d, NPG, , _engidx, _dev, _reg, _data)
#define NVSWITCH_NPG_RD32_LS10(_d, _engidx, _dev, _reg) \
NVSWITCH_ENG_RD32(_d, NPG, , _engidx, _dev, _reg)
//
// Per-chip device information
//
#define DISCOVERY_TYPE_UNDEFINED 0
#define DISCOVERY_TYPE_DISCOVERY 1
#define DISCOVERY_TYPE_UNICAST 2
#define DISCOVERY_TYPE_BROADCAST 3
typedef struct
{
NvBool valid;
NvU32 initialized;
NvU32 version;
NvU32 disc_type;
union
{
struct
{
NvU32 cluster;
NvU32 cluster_id;
NvU32 discovery; // Used for top level only
} top;
struct
{
NvU32 uc_addr;
} uc;
struct
{
NvU32 bc_addr;
NvU32 mc_addr[3];
} bc;
} info;
} ENGINE_DISCOVERY_TYPE_LS10;
#define NVSWITCH_DECLARE_ENGINE_UC_LS10(_engine) \
ENGINE_DISCOVERY_TYPE_LS10 eng##_engine[NUM_##_engine##_ENGINE_LS10];
#define NVSWITCH_DECLARE_ENGINE_LS10(_engine) \
ENGINE_DISCOVERY_TYPE_LS10 eng##_engine[NUM_##_engine##_ENGINE_LS10]; \
ENGINE_DISCOVERY_TYPE_LS10 eng##_engine##_BCAST[NUM_##_engine##_BCAST_ENGINE_LS10];
#define NVSWITCH_LIST_LS10_ENGINE_UC(_op) \
_op(PTOP) \
_op(FUSE) \
_op(GIN) \
_op(JTAG) \
_op(PMGR) \
_op(SAW) \
_op(ROM) \
_op(EXTDEV) \
_op(PTIMER) \
_op(SOE) \
_op(SMR) \
_op(SE) \
_op(THERM) \
_op(XAL) \
_op(XAL_FUNC) \
_op(XTL_CONFIG) \
_op(XPL) \
_op(XTL) \
_op(UXL) \
_op(GPU_PTOP) \
_op(PMC) \
_op(PBUS) \
_op(ROM2) \
_op(GPIO) \
_op(FSP) \
_op(CLKS_SYS) \
_op(CLKS_SYSB) \
_op(CLKS_P0) \
_op(CLKS_P0_BCAST) \
_op(SAW_PM) \
_op(PCIE_PM) \
_op(SYS_PRI_HUB) \
_op(SYS_PRI_RS_CTRL) \
_op(SYSB_PRI_HUB) \
_op(SYSB_PRI_RS_CTRL) \
_op(PRI_MASTER_RS) \
#define NVSWITCH_LIST_PRI_HUB_LS10_ENGINE(_op) \
_op(PRT_PRI_HUB) \
_op(PRT_PRI_RS_CTRL) \
_op(PRT_PRI_HUB_BCAST) \
_op(PRT_PRI_RS_CTRL_BCAST) \
#define NVSWITCH_LIST_NPG_LS10_ENGINE(_op) \
_op(NPG) \
_op(NPG_PERFMON) \
_op(NPORT) \
_op(NPORT_MULTICAST) \
_op(NPORT_PERFMON) \
_op(NPORT_PERFMON_MULTICAST)
#define NVSWITCH_LIST_NVLW_LS10_ENGINE(_op) \
_op(NVLW) \
_op(NVLIPT) \
_op(MINION) \
_op(CPR) \
_op(NVLW_PERFMON) \
_op(NVLIPT_SYS_PERFMON) \
_op(NVLDL_MULTICAST) \
_op(NVLTLC_MULTICAST) \
_op(NVLIPT_LNK_MULTICAST) \
_op(SYS_PERFMON_MULTICAST) \
_op(TX_PERFMON_MULTICAST) \
_op(RX_PERFMON_MULTICAST) \
_op(NVLDL) \
_op(NVLTLC) \
_op(NVLIPT_LNK) \
_op(SYS_PERFMON) \
_op(TX_PERFMON) \
_op(RX_PERFMON)
#define NVSWITCH_LIST_NXBAR_LS10_ENGINE(_op) \
_op(NXBAR) \
_op(NXBAR_PERFMON) \
_op(TILE_MULTICAST) \
_op(TILE_PERFMON_MULTICAST) \
_op(TILE) \
_op(TILE_PERFMON) \
_op(TILEOUT_MULTICAST) \
_op(TILEOUT_PERFMON_MULTICAST) \
_op(TILEOUT) \
_op(TILEOUT_PERFMON)
#define NVSWITCH_LIST_LS10_ENGINE(_op) \
NVSWITCH_LIST_NPG_LS10_ENGINE(_op) \
NVSWITCH_LIST_NVLW_LS10_ENGINE(_op) \
NVSWITCH_LIST_NXBAR_LS10_ENGINE(_op)
//
// The chip-specific engine list is used to generate the code to collect
// discovered unit information and coalesce it into the data structures used by
// the common IO library (see io_nvswitch.h).
//
// The PTOP discovery table presents the information on wrappers and sub-units
// in a hierarchical manner. The top level discovery contains information
// about top level UNICAST units and IP wrappers like NPG, NVLW, and NXBAR.
// Individual units within an IP wrapper are described in discovery sub-tables.
// Each IP wrapper may have MULTICAST descriptors to allow addressing sub-units
// within a wrapper and a cluster of IP wrappers will also have a BCAST
// discovery tables, which have MULTICAST descriptors within them.
// In order to collect all the useful unit information into a single container,
// we need to pick where to find each piece within the parsed discovery table.
// Top level IP wrappers like NPG have a BCAST range to broadcast reads/writes,
// but IP sub-units like NPORT have a MULTICAST range within the BCAST IP
// wrapper to broadcast to all the sub-units in all the IP wrappers.
// So in the lists below top level IP wrappers (NPG, NVLW, and NXBAR) point
// to the _BCAST IP wrapper, but sub-unit point to the _MULTICAST range inside
// the BCAST unit (_MULTICAST_BCAST).
//
// All IP-based (0-based register manuals) engines need to be listed here to
// generate chip-specific handlers as well as in the global common list of all
// engines that have ever existed on *ANY* architecture(s) in order for them
// use common IO wrappers.
//
#define NVSWITCH_LIST_LS10_ENGINES(_op) \
_op(GIN, ) \
_op(XAL, ) \
_op(XPL, ) \
_op(XTL, ) \
_op(SAW, ) \
_op(SOE, ) \
_op(SMR, ) \
\
_op(PRT_PRI_HUB, _BCAST) \
_op(PRT_PRI_RS_CTRL, _BCAST) \
_op(SYS_PRI_HUB, ) \
_op(SYS_PRI_RS_CTRL, ) \
_op(SYSB_PRI_HUB, ) \
_op(SYSB_PRI_RS_CTRL, ) \
_op(PRI_MASTER_RS, ) \
_op(PTIMER, ) \
_op(CLKS_SYS, ) \
_op(CLKS_SYSB, ) \
_op(CLKS_P0, _BCAST) \
\
_op(NPG, _BCAST) \
_op(NPORT, _MULTICAST_BCAST) \
\
_op(NVLW, _BCAST) \
_op(MINION, _BCAST) \
_op(NVLIPT, _BCAST) \
_op(CPR, _BCAST) \
_op(NVLIPT_LNK, _MULTICAST_BCAST) \
_op(NVLTLC, _MULTICAST_BCAST) \
_op(NVLDL, _MULTICAST_BCAST) \
\
_op(NXBAR, _BCAST) \
_op(TILE, _MULTICAST_BCAST) \
_op(TILEOUT, _MULTICAST_BCAST) \
\
_op(NPG_PERFMON, _BCAST) \
_op(NPORT_PERFMON, _MULTICAST_BCAST) \
\
_op(NVLW_PERFMON, _BCAST) \
//
// These field #defines describe which physical fabric address bits are
// relevant to the specific remap table address check/remap operation.
//
#define NV_INGRESS_REMAP_ADDR_PHYS_LS10 51:39 /* LR10: 46:36 */
#define NV_INGRESS_REMAP_ADR_OFFSET_PHYS_LS10 38:21 /* LR10: 35:20 */
#define NV_INGRESS_REMAP_ADR_BASE_PHYS_LS10 38:21 /* LR10: 35:20 */
#define NV_INGRESS_REMAP_ADR_LIMIT_PHYS_LS10 38:21 /* LR10: 35:20 */
//
// Multicast REMAP table is not indexed through the same _RAM_SEL mechanism as
// other REMAP tables, but we want to be able to use the same set of APIs for
// all the REMAP tables, so define a special RAM_SEL value for MCREMAP that
// does not conflict with the existing definitions.
//
#define NV_INGRESS_REQRSPMAPADDR_RAM_SEL_SELECT_MULTICAST_REMAPRAM (DRF_MASK(NV_INGRESS_REQRSPMAPADDR_RAM_ADDRESS) + 1)
//
// NPORT Portstat information
//
//
// LS10 supports CREQ0(0), DNGRD(1), ATR(2), ATSD(3), PROBE(4), RSP0(5), CREQ1(6), and RSP1(7) VCs.
// But DNGRD(1), ATR(2), ATSD(3), and PROBE(4) will be never used.
//
#define NVSWITCH_NUM_VCS_LS10 8
typedef struct
{
NvU32 count;
NvU32 low;
NvU32 medium;
NvU32 high;
NvU32 panic;
}
NVSWITCH_LATENCY_BINS_LS10;
typedef struct
{
NvU32 count;
NvU64 start_time_nsec;
NvU64 last_read_time_nsec;
NVSWITCH_LATENCY_BINS_LS10 accum_latency[NVSWITCH_NUM_LINKS_LS10];
}
NVSWITCH_LATENCY_VC_LS10;
typedef struct
{
NvU32 sample_interval_msec;
NvU64 last_visited_time_nsec;
NVSWITCH_LATENCY_VC_LS10 latency[NVSWITCH_NUM_VCS_LS10];
} NVSWITCH_LATENCY_STATS_LS10;
#define NV_NPORT_PORTSTAT_LS10(_block, _reg, _vc, _hi_lo) (NV_NPORT_PORTSTAT ## _block ## _reg ## _0 ## _hi_lo + \
_vc * (NV_NPORT_PORTSTAT ## _block ## _reg ## _1 ## _hi_lo - NV_NPORT_PORTSTAT ## _block ## _reg ## _0 ## _hi_lo))
#define NVSWITCH_NPORT_PORTSTAT_RD32_LS10(_d, _engidx, _block, _reg, _hi_lo, _vc) \
( \
NVSWITCH_ASSERT(NVSWITCH_IS_LINK_ENG_VALID_LS10(_d, NPORT, _engidx)) \
, \
NVSWITCH_PRINT(_d, MMIO, \
"%s: MEM_RD NPORT_PORTSTAT[%d]: %s,%s,_%s,%s (%06x+%04x)\n", \
__FUNCTION__, \
_engidx, \
#_block, #_reg, #_vc, #_hi_lo, \
NVSWITCH_GET_ENG(_d, NPORT, , _engidx), \
NV_NPORT_PORTSTAT_LS10(_block, _reg, _vc, _hi_lo)) \
, \
nvswitch_reg_read_32(_d, \
NVSWITCH_GET_ENG(_d, NPORT, , _engidx) + \
NV_NPORT_PORTSTAT_LS10(_block, _reg, _vc, _hi_lo)) \
); \
((void)(_d))
#define NVSWITCH_PORTSTAT_BCAST_WR32_LS10(_d, _block, _reg, _idx, _data) \
{ \
NVSWITCH_PRINT(_d, MMIO, \
"%s: BCAST_WR NPORT_PORTSTAT: %s,%s (%06x+%04x) 0x%08x\n", \
__FUNCTION__, \
#_block, #_reg, \
NVSWITCH_GET_ENG(_d, NPORT, _BCAST, 0), \
NV_NPORT_PORTSTAT_LS10(_block, _reg, _idx, ), _data); \
NVSWITCH_OFF_WR32(_d, \
NVSWITCH_GET_ENG(_d, NPORT, _BCAST, 0) + \
NV_NPORT_PORTSTAT_LS10(_block, _reg, _idx, ), _data); \
}
#define NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS (10 * NVSWITCH_INTERVAL_1SEC_IN_NS)
#define NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS (10 * NVSWITCH_INTERVAL_1MSEC_IN_NS)
// Struct used for passing around error masks in error handling functions
typedef struct
{
NvU32 dl;
NvU32 tlcRx0;
NvU32 tlcRx0Injected;
NvU32 tlcRx1;
NvU32 tlcRx1Injected;
NvU32 liptLnk;
NvU32 liptLnkInjected;
} NVLINK_LINK_ERROR_INFO_ERR_MASKS, *PNVLINK_LINK_ERROR_INFO_ERR_MASKS;
typedef struct
{
NvBool bLinkErrorsCallBackEnabled;
NvBool bLinkStateCallBackEnabled;
NVLINK_LINK_ERROR_INFO_ERR_MASKS fatalIntrMask;
NVLINK_LINK_ERROR_INFO_ERR_MASKS nonFatalIntrMask;
} NVLINK_LINK_ERROR_REPORTING;
typedef struct
{
struct
{
NVSWITCH_ENGINE_DESCRIPTOR_TYPE common[NVSWITCH_ENGINE_ID_SIZE];
} io;
NVSWITCH_LIST_LS10_ENGINE_UC(NVSWITCH_DECLARE_ENGINE_UC_LS10)
NVSWITCH_LIST_PRI_HUB_LS10_ENGINE(NVSWITCH_DECLARE_ENGINE_UC_LS10)
NVSWITCH_LIST_LS10_ENGINE(NVSWITCH_DECLARE_ENGINE_LS10)
// Interrupts
NvU32 intr_minion_dest;
// VBIOS configuration Data
NVSWITCH_BIOS_NVLINK_CONFIG bios_config;
// GPIO
const NVSWITCH_GPIO_INFO *gpio_pin;
NvU32 gpio_pin_size;
// Latency statistics
NVSWITCH_LATENCY_STATS_LS10 *latency_stats;
// External TDIODE info
NVSWITCH_TDIODE_INFO_TYPE tdiode;
//
// Book-keep interrupt masks to restore them after reset.
// Note: There is no need to book-keep interrupt masks for NVLink units like
// DL, MINION, TLC etc. because NVLink init routines would setup them.
//
struct
{
NVSWITCH_INTERRUPT_MASK route;
NVSWITCH_INTERRUPT_MASK ingress[2];
NVSWITCH_INTERRUPT_MASK egress[2];
NVSWITCH_INTERRUPT_MASK tstate;
NVSWITCH_INTERRUPT_MASK sourcetrack;
NVSWITCH_INTERRUPT_MASK mc_tstate;
NVSWITCH_INTERRUPT_MASK red_tstate;
NVSWITCH_INTERRUPT_MASK tile;
NVSWITCH_INTERRUPT_MASK tileout;
} intr_mask;
// Ganged Link table
NvU64 *ganged_link_table;
//NVSWITCH Minion core
NvU32 minionEngArch;
NvBool riscvManifestBoot;
// Nvlink error reporting management
NVLINK_LINK_ERROR_REPORTING deferredLinkErrors[NVSWITCH_NUM_LINKS_LS10];
} ls10_device;
//
// Helpful IO wrappers
//
#define NVSWITCH_GET_CHIP_DEVICE_LS10(_device) \
( \
((_device)->chip_id == NV_PMC_BOOT_42_CHIP_ID_LS10) ? \
((ls10_device *) _device->chip_device) : \
NULL \
)
#define NVSWITCH_ENG_VALID_LS10(_d, _eng, _engidx) \
( \
((_engidx < NUM_##_eng##_ENGINE_LS10) && \
(NVSWITCH_GET_CHIP_DEVICE_LS10(_d)->eng##_eng[_engidx].valid)) ? \
NV_TRUE : NV_FALSE \
)
#define NVSWITCH_ENG_WR32_LS10(_d, _eng, _bcast, _engidx, _dev, _reg, _data) \
NVSWITCH_ENG_WR32(_d, _eng, _bcast, _engidx, _dev, _reg, _data)
#define NVSWITCH_ENG_RD32_LS10(_d, _eng, _engidx, _dev, _reg) \
NVSWITCH_ENG_RD32(_d, _eng, , _engidx, _dev, _reg)
#define NVSWITCH_BCAST_WR32_LS10(_d, _eng, _dev, _reg, _data) \
NVSWITCH_ENG_WR32(_d, _eng, _BCAST, 0, _dev, _reg, _data)
#define NVSWITCH_BCAST_RD32_LS10(_d, _eng, _dev, _reg) \
NVSWITCH_ENG_RD32(_d, _eng, _BCAST, 0, _dev, _reg)
#define NVSWITCH_SOE_WR32_LS10(_d, _instance, _dev, _reg, _data) \
NVSWITCH_ENG_WR32(_d, SOE, , _instance, _dev, _reg, _data)
#define NVSWITCH_SOE_RD32_LS10(_d, _instance, _dev, _reg) \
NVSWITCH_ENG_RD32(_d, SOE, , _instance, _dev, _reg)
#define NVSWITCH_NPORT_BCAST_WR32_LS10(_d, _dev, _reg, _data) \
NVSWITCH_ENG_WR32(_d, NPORT, _BCAST, 0, _dev, _reg, _data)
#define NVSWITCH_SAW_WR32_LS10(_d, _dev, _reg, _data) \
NVSWITCH_ENG_WR32(_d, SAW, , 0, _dev, _reg, _data)
#define NVSWITCH_SAW_RD32_LS10(_d, _dev, _reg) \
NVSWITCH_ENG_RD32(_d, SAW, , 0, _dev, _reg)
#define NVSWITCH_NPORT_MC_BCAST_WR32_LS10(_d, _dev, _reg, _data) \
NVSWITCH_BCAST_WR32_LS10(_d, NPORT, _dev, _reg, _data)
//
// Tile Column consists of 12 Tile blocks and 11 (really 12) Tileout blocks.
//
#define NUM_NXBAR_TILES_PER_TC_LS10 12
#define NUM_NXBAR_TILEOUTS_PER_TC_LS10 12
#define TILE_INDEX_LS10(_device, _nxbar, _tile) \
( \
NVSWITCH_ASSERT((_nxbar < NUM_NXBAR_ENGINE_LS10)) \
, \
NVSWITCH_ASSERT((_tile < NUM_NXBAR_TILES_PER_TC_LS10)) \
, \
((_nxbar) * NUM_NXBAR_TILES_PER_TC_LS10 + (_tile)) \
)
#define NVSWITCH_TILE_RD32(_d, _engidx, _dev, _reg) \
NVSWITCH_ENG_RD32(_d, TILE, , _engidx, _dev, _reg)
#define NVSWITCH_TILE_WR32(_d, _engidx, _dev, _reg, _data) \
NVSWITCH_ENG_WR32(_d, TILE, , _engidx, _dev, _reg, _data)
#define NVSWITCH_TILEOUT_RD32(_d, _engidx, _dev, _reg) \
NVSWITCH_ENG_RD32(_d, TILEOUT, , _engidx, _dev, _reg)
#define NVSWITCH_TILEOUT_WR32(_d, _engidx, _dev, _reg, _data) \
NVSWITCH_ENG_WR32(_d, TILEOUT, , _engidx, _dev, _reg, _data)
//
// Per link register access routines
// LINK_* MMIO wrappers are used to reference per-link engine instances
//
#define NVSWITCH_IS_LINK_ENG_VALID_LS10(_d, _eng, _linknum) \
NVSWITCH_IS_LINK_ENG_VALID(_d, _linknum, _eng)
#define NVSWITCH_LINK_OFFSET_LS10(_d, _physlinknum, _eng, _dev, _reg) \
NVSWITCH_LINK_OFFSET(_d, _physlinknum, _eng, _dev, _reg)
#define NVSWITCH_LINK_WR32_LS10(_d, _physlinknum, _eng, _dev, _reg, _data) \
NVSWITCH_LINK_WR32(_d, _physlinknum, _eng, _dev, _reg, _data)
#define NVSWITCH_LINK_RD32_LS10(_d, _physlinknum, _eng, _dev, _reg) \
NVSWITCH_LINK_RD32(_d, _physlinknum, _eng, _dev, _reg)
#define NVSWITCH_LINK_WR32_IDX_LS10(_d, _physlinknum, _eng, _dev, _reg, _idx, _data) \
NVSWITCH_LINK_WR32_IDX(_d, _physlinknum, _eng, _dev, _reg, _idx, _data)
#define NVSWITCH_LINK_RD32_IDX_LS10(_d, _physlinknum, _eng, _dev, _reg, _idx) \
NVSWITCH_LINK_RD32_IDX(_d, _physlinknum, _eng, _dev, _reg, _idx)
#define NVSWITCH_MINION_LINK_WR32_LS10(_d, _physlinknum, _dev, _reg, _data) \
NVSWITCH_LINK_WR32(_d, _physlinknum, MINION, _dev, _reg, _data)
#define NVSWITCH_MINION_LINK_RD32_LS10(_d, _physlinknum, _dev, _reg) \
NVSWITCH_LINK_RD32(_d, _physlinknum, MINION, _dev, _reg)
//
// MINION
//
typedef const struct
{
NvU32 osCodeOffset;
NvU32 osCodeSize;
NvU32 osDataOffset;
NvU32 osDataSize;
NvU32 numApps;
NvU32 appCodeStart;
NvU32 appDataStart;
NvU32 codeOffset;
NvU32 codeSize;
NvU32 dataOffset;
NvU32 dataSize;
} FALCON_UCODE_HDR_INFO_LS10, *PFALCON_UCODE_HDR_INFO_LS10;
typedef const struct
{
//
// Version 1
// Version 2
// Vesrion 3 = for Partition boot
// Vesrion 4 = for eb riscv boot
//
NvU32 version; // structure version
NvU32 bootloaderOffset;
NvU32 bootloaderSize;
NvU32 bootloaderParamOffset;
NvU32 bootloaderParamSize;
NvU32 riscvElfOffset;
NvU32 riscvElfSize;
NvU32 appVersion; // Changelist number associated with the image
//
// Manifest contains information about Monitor and it is
// input to BR
//
NvU32 manifestOffset;
NvU32 manifestSize;
//
// Monitor Data offset within RISCV image and size
//
NvU32 monitorDataOffset;
NvU32 monitorDataSize;
//
// Monitor Code offset withtin RISCV image and size
//
NvU32 monitorCodeOffset;
NvU32 monitorCodeSize;
NvU32 bIsMonitorEnabled;
//
// Swbrom Code offset within RISCV image and size
//
NvU32 swbromCodeOffset;
NvU32 swbromCodeSize;
//
// Swbrom Data offset within RISCV image and size
//
NvU32 swbromDataOffset;
NvU32 swbromDataSize;
} RISCV_UCODE_HDR_INFO_LS10, *PRISCV_UCODE_HDR_INFO_LS10;
//
// HAL functions shared by LR10 and used by LS10
//
#define nvswitch_is_link_valid_ls10 nvswitch_is_link_valid_lr10
#define nvswitch_is_link_in_use_ls10 nvswitch_is_link_in_use_lr10
#define nvswitch_initialize_device_state_ls10 nvswitch_initialize_device_state_lr10
#define nvswitch_deassert_link_reset_ls10 nvswitch_deassert_link_reset_lr10
#define nvswitch_determine_platform_ls10 nvswitch_determine_platform_lr10
#define nvswitch_get_swap_clk_default_ls10 nvswitch_get_swap_clk_default_lr10
#define nvswitch_post_init_device_setup_ls10 nvswitch_post_init_device_setup_lr10
#define nvswitch_set_training_error_info_ls10 nvswitch_set_training_error_info_lr10
#define nvswitch_init_scratch_ls10 nvswitch_init_scratch_lr10
#define nvswitch_hw_counter_shutdown_ls10 nvswitch_hw_counter_shutdown_lr10
#define nvswitch_hw_counter_read_counter_ls10 nvswitch_hw_counter_read_counter_lr10
#define nvswitch_ecc_writeback_task_ls10 nvswitch_ecc_writeback_task_lr10
#define nvswitch_ctrl_get_routing_id_ls10 nvswitch_ctrl_get_routing_id_lr10
#define nvswitch_ctrl_set_routing_id_valid_ls10 nvswitch_ctrl_set_routing_id_valid_lr10
#define nvswitch_ctrl_set_routing_id_ls10 nvswitch_ctrl_set_routing_id_lr10
#define nvswitch_ctrl_set_routing_lan_ls10 nvswitch_ctrl_set_routing_lan_lr10
#define nvswitch_ctrl_get_routing_lan_ls10 nvswitch_ctrl_get_routing_lan_lr10
#define nvswitch_ctrl_set_routing_lan_valid_ls10 nvswitch_ctrl_set_routing_lan_valid_lr10
#define nvswitch_ctrl_set_ingress_request_table_ls10 nvswitch_ctrl_set_ingress_request_table_lr10
#define nvswitch_ctrl_get_ingress_request_table_ls10 nvswitch_ctrl_get_ingress_request_table_lr10
#define nvswitch_ctrl_set_ingress_request_valid_ls10 nvswitch_ctrl_set_ingress_request_valid_lr10
#define nvswitch_ctrl_get_ingress_response_table_ls10 nvswitch_ctrl_get_ingress_response_table_lr10
#define nvswitch_ctrl_set_ingress_response_table_ls10 nvswitch_ctrl_set_ingress_response_table_lr10
#define nvswitch_ctrl_get_info_ls10 nvswitch_ctrl_get_info_lr10
#define nvswitch_ctrl_set_switch_port_config_ls10 nvswitch_ctrl_set_switch_port_config_lr10
#define nvswitch_ctrl_get_fom_values_ls10 nvswitch_ctrl_get_fom_values_lr10
#define nvswitch_ctrl_get_throughput_counters_ls10 nvswitch_ctrl_get_throughput_counters_lr10
#define nvswitch_save_nvlink_seed_data_from_minion_to_inforom_ls10 nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10
#define nvswitch_store_seed_data_from_inforom_to_corelib_ls10 nvswitch_store_seed_data_from_inforom_to_corelib_lr10
#define nvswitch_corelib_clear_link_state_ls10 nvswitch_corelib_clear_link_state_lr10
#define nvswitch_read_oob_blacklist_state_ls10 nvswitch_read_oob_blacklist_state_lr10
#define nvswitch_corelib_add_link_ls10 nvswitch_corelib_add_link_lr10
#define nvswitch_corelib_remove_link_ls10 nvswitch_corelib_remove_link_lr10
#define nvswitch_corelib_set_tl_link_mode_ls10 nvswitch_corelib_set_tl_link_mode_lr10
#define nvswitch_corelib_set_rx_mode_ls10 nvswitch_corelib_set_rx_mode_lr10
#define nvswitch_corelib_set_rx_detect_ls10 nvswitch_corelib_set_rx_detect_lr10
#define nvswitch_corelib_write_discovery_token_ls10 nvswitch_corelib_write_discovery_token_lr10
#define nvswitch_corelib_read_discovery_token_ls10 nvswitch_corelib_read_discovery_token_lr10
#define nvswitch_inforom_nvl_get_minion_data_ls10 nvswitch_inforom_nvl_get_minion_data_lr10
#define nvswitch_inforom_nvl_set_minion_data_ls10 nvswitch_inforom_nvl_set_minion_data_lr10
#define nvswitch_inforom_nvl_get_max_correctable_error_rate_ls10 nvswitch_inforom_nvl_get_max_correctable_error_rate_lr10
#define nvswitch_inforom_nvl_get_errors_ls10 nvswitch_inforom_nvl_get_errors_lr10
#define nvswitch_inforom_ecc_log_error_event_ls10 nvswitch_inforom_ecc_log_error_event_lr10
#define nvswitch_inforom_ecc_get_errors_ls10 nvswitch_inforom_ecc_get_errors_lr10
#define nvswitch_inforom_bbx_get_sxid_ls10 nvswitch_inforom_bbx_get_sxid_lr10
#define nvswitch_vbios_read_structure_ls10 nvswitch_vbios_read_structure_lr10
#define nvswitch_setup_system_registers_ls10 nvswitch_setup_system_registers_lr10
#define nvswitch_minion_get_initoptimize_status_ls10 nvswitch_minion_get_initoptimize_status_lr10
#define nvswitch_poll_sublink_state_ls10 nvswitch_poll_sublink_state_lr10
#define nvswitch_setup_link_loopback_mode_ls10 nvswitch_setup_link_loopback_mode_lr10
#define nvswitch_link_lane_reversed_ls10 nvswitch_link_lane_reversed_lr10
#define nvswitch_request_tl_link_state_ls10 nvswitch_request_tl_link_state_lr10
#define nvswitch_i2c_get_port_info_ls10 nvswitch_i2c_get_port_info_lr10
#define nvswitch_i2c_set_hw_speed_mode_ls10 nvswitch_i2c_set_hw_speed_mode_lr10
#define nvswitch_ctrl_get_err_info_ls10 nvswitch_ctrl_get_err_info_lr10
NvlStatus nvswitch_ctrl_get_err_info_lr10(nvswitch_device *device, NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS *ret);
NvBool nvswitch_is_link_valid_lr10(nvswitch_device *device, NvU32 link_id);
NvBool nvswitch_is_link_in_use_lr10(nvswitch_device *device, NvU32 link_id);
NvlStatus nvswitch_initialize_device_state_lr10(nvswitch_device *device);
NvlStatus nvswitch_deassert_link_reset_lr10(nvswitch_device *device, nvlink_link *link);
void nvswitch_determine_platform_lr10(nvswitch_device *device);
NvU32 nvswitch_get_swap_clk_default_lr10(nvswitch_device *device);
NvlStatus nvswitch_post_init_device_setup_lr10(nvswitch_device *device);
NvlStatus nvswitch_set_training_error_info_lr10(nvswitch_device *device, NVSWITCH_SET_TRAINING_ERROR_INFO_PARAMS *pLinkTrainingErrorInfoParams);
void nvswitch_init_scratch_lr10(nvswitch_device *device);
void nvswitch_hw_counter_shutdown_lr10(nvswitch_device *device);
NvU64 nvswitch_hw_counter_read_counter_lr10(nvswitch_device *device);
void nvswitch_ecc_writeback_task_lr10(nvswitch_device *device);
NvlStatus nvswitch_ctrl_get_routing_id_lr10(nvswitch_device *device, NVSWITCH_GET_ROUTING_ID_PARAMS *params);
NvlStatus nvswitch_ctrl_set_routing_id_valid_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_ID_VALID *p);
NvlStatus nvswitch_ctrl_set_routing_id_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_ID *p);
NvlStatus nvswitch_ctrl_set_routing_lan_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_LAN *p);
NvlStatus nvswitch_ctrl_get_routing_lan_lr10(nvswitch_device *device, NVSWITCH_GET_ROUTING_LAN_PARAMS *params);
NvlStatus nvswitch_ctrl_set_routing_lan_valid_lr10(nvswitch_device *device, NVSWITCH_SET_ROUTING_LAN_VALID *p);
NvlStatus nvswitch_ctrl_set_ingress_request_table_lr10(nvswitch_device *device, NVSWITCH_SET_INGRESS_REQUEST_TABLE *p);
NvlStatus nvswitch_ctrl_get_ingress_request_table_lr10(nvswitch_device *device, NVSWITCH_GET_INGRESS_REQUEST_TABLE_PARAMS *params);
NvlStatus nvswitch_ctrl_set_ingress_request_valid_lr10(nvswitch_device *device, NVSWITCH_SET_INGRESS_REQUEST_VALID *p);
NvlStatus nvswitch_ctrl_get_ingress_response_table_lr10(nvswitch_device *device, NVSWITCH_GET_INGRESS_RESPONSE_TABLE_PARAMS *params);
NvlStatus nvswitch_ctrl_set_ingress_response_table_lr10(nvswitch_device *device, NVSWITCH_SET_INGRESS_RESPONSE_TABLE *p);
NvlStatus nvswitch_ctrl_get_nvlink_status_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_STATUS_PARAMS *ret);
NvlStatus nvswitch_ctrl_get_nvlink_status_ls10(nvswitch_device *device, NVSWITCH_GET_NVLINK_STATUS_PARAMS *ret);
NvlStatus nvswitch_ctrl_get_info_lr10(nvswitch_device *device, NVSWITCH_GET_INFO *p);
NvlStatus nvswitch_ctrl_set_switch_port_config_lr10(nvswitch_device *device, NVSWITCH_SET_SWITCH_PORT_CONFIG *p);
NvlStatus nvswitch_ctrl_get_fom_values_lr10(nvswitch_device *device, NVSWITCH_GET_FOM_VALUES_PARAMS *p);
NvlStatus nvswitch_ctrl_get_throughput_counters_lr10(nvswitch_device *device, NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS *p);
void nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10(nvswitch_device *device, NvU32 linkId);
void nvswitch_store_seed_data_from_inforom_to_corelib_lr10(nvswitch_device *device);
NvlStatus nvswitch_read_oob_blacklist_state_lr10(nvswitch_device *device);
NvlStatus nvswitch_corelib_add_link_lr10(nvlink_link *link);
NvlStatus nvswitch_corelib_remove_link_lr10(nvlink_link *link);
NvlStatus nvswitch_corelib_get_dl_link_mode_lr10(nvlink_link *link, NvU64 *mode);
NvlStatus nvswitch_corelib_set_tl_link_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags);
NvlStatus nvswitch_corelib_get_tx_mode_lr10(nvlink_link *link, NvU64 *mode, NvU32 *subMode);
NvlStatus nvswitch_corelib_set_rx_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags);
NvlStatus nvswitch_corelib_get_rx_mode_lr10(nvlink_link *link, NvU64 *mode, NvU32 *subMode);
NvlStatus nvswitch_corelib_set_rx_detect_lr10(nvlink_link *link, NvU32 flags);
NvlStatus nvswitch_corelib_write_discovery_token_lr10(nvlink_link *link, NvU64 token);
NvlStatus nvswitch_corelib_read_discovery_token_lr10(nvlink_link *link, NvU64 *token);
NvlStatus nvswitch_corelib_set_dl_link_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags);
NvlStatus nvswitch_corelib_set_tx_mode_lr10(nvlink_link *link, NvU64 mode, NvU32 flags);
NvlStatus nvswitch_corelib_get_tl_link_mode_lr10(nvlink_link *link, NvU64 *mode);
void nvswitch_init_buffer_ready_lr10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady);
NvlStatus nvswitch_inforom_nvl_get_minion_data_lr10(nvswitch_device *device, void *pNvlGeneric, NvU8 linkId, NvU32 *seedData);
NvlStatus nvswitch_inforom_nvl_set_minion_data_lr10(nvswitch_device *device, void *pNvlGeneric, NvU8 linkId, NvU32 *seedData, NvU32 size, NvBool *bDirty);
NvlStatus nvswitch_inforom_nvl_get_max_correctable_error_rate_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params);
NvlStatus nvswitch_inforom_nvl_get_errors_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params);
NvlStatus nvswitch_inforom_ecc_log_error_event_lr10(nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, INFOROM_NVS_ECC_ERROR_EVENT *err_event);
NvlStatus nvswitch_inforom_ecc_get_errors_lr10(nvswitch_device *device, NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS *params);
NvlStatus nvswitch_inforom_bbx_get_sxid_lr10(nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS *params);
void nvswitch_init_dlpl_interrupts_lr10(nvlink_link *link);
NvlStatus nvswitch_vbios_read_structure_lr10(nvswitch_device *device, void *structure, NvU32 offset, NvU32 *ppacked_size, const char *format);
NvlStatus nvswitch_setup_system_registers_lr10(nvswitch_device *device);
NvlStatus nvswitch_minion_get_initoptimize_status_lr10(nvswitch_device *device, NvU32 linkId);
NvlStatus nvswitch_poll_sublink_state_lr10(nvswitch_device *device, nvlink_link *link);
void nvswitch_setup_link_loopback_mode_lr10(nvswitch_device *device, NvU32 linkNumber);
NvBool nvswitch_link_lane_reversed_lr10(nvswitch_device *device, NvU32 linkId);
void nvswitch_store_topology_information_lr10(nvswitch_device *device, nvlink_link *link);
NvlStatus nvswitch_request_tl_link_state_lr10(nvlink_link *link, NvU32 tlLinkState, NvBool bSync);
NvlStatus nvswitch_wait_for_tl_request_ready_lr10(nvlink_link *link);
NvlStatus nvswitch_parse_bios_image_lr10(nvswitch_device *device);
NvU32 nvswitch_i2c_get_port_info_lr10(nvswitch_device *device, NvU32 port);
void nvswitch_i2c_set_hw_speed_mode_lr10(nvswitch_device *device, NvU32 port, NvU32 speedMode);
NvlStatus nvswitch_ctrl_i2c_indexed_lr10(nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams);
void nvswitch_corelib_clear_link_state_lr10(nvlink_link *link);
//
// Internal function declarations
//
NvlStatus nvswitch_corelib_set_dl_link_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags);
NvlStatus nvswitch_corelib_set_tx_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags);
void nvswitch_init_lpwr_regs_ls10(nvlink_link *link);
NvlStatus nvswitch_minion_service_falcon_interrupts_ls10(nvswitch_device *device, NvU32 instance);
NvlStatus nvswitch_device_discovery_ls10(nvswitch_device *device, NvU32 discovery_offset);
void nvswitch_filter_discovery_ls10(nvswitch_device *device);
NvlStatus nvswitch_process_discovery_ls10(nvswitch_device *device);
void nvswitch_lib_enable_interrupts_ls10(nvswitch_device *device);
void nvswitch_lib_disable_interrupts_ls10(nvswitch_device *device);
NvlStatus nvswitch_lib_service_interrupts_ls10(nvswitch_device *device);
NvlStatus nvswitch_lib_check_interrupts_ls10(nvswitch_device *device);
void nvswitch_initialize_interrupt_tree_ls10(nvswitch_device *device);
void nvswitch_corelib_training_complete_ls10(nvlink_link *link);
NvlStatus nvswitch_init_nport_ls10(nvswitch_device *device);
NvlStatus nvswitch_corelib_get_rx_detect_ls10(nvlink_link *link);
void nvswitch_reset_persistent_link_hw_state_ls10(nvswitch_device *device, NvU32 linkNumber);
NvlStatus nvswitch_minion_get_rxdet_status_ls10(nvswitch_device *device, NvU32 linkId);
NvlStatus nvswitch_minion_restore_seed_data_ls10(nvswitch_device *device, NvU32 linkId, NvU32 *seedData);
NvlStatus nvswitch_minion_set_sim_mode_ls10(nvswitch_device *device, nvlink_link *link);
NvlStatus nvswitch_minion_set_smf_settings_ls10(nvswitch_device *device, nvlink_link *link);
NvlStatus nvswitch_minion_select_uphy_tables_ls10(nvswitch_device *device, nvlink_link *link);
NvlStatus nvswitch_set_training_mode_ls10(nvswitch_device *device);
NvlStatus nvswitch_corelib_get_tl_link_mode_ls10(nvlink_link *link, NvU64 *mode);
NvU32 nvswitch_get_sublink_width_ls10(nvswitch_device *device,NvU32 linkNumber);
NvlStatus nvswitch_parse_bios_image_ls10(nvswitch_device *device);
NvBool nvswitch_is_link_in_reset_ls10(nvswitch_device *device, nvlink_link *link);
void nvswitch_corelib_get_uphy_load_ls10(nvlink_link *link, NvBool *bUnlocked);
NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_ls10(nvswitch_device *device, NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS *params);
void nvswitch_init_buffer_ready_ls10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady);
void nvswitch_apply_recal_settings_ls10(nvswitch_device *device, nvlink_link *link);
NvlStatus nvswitch_corelib_get_dl_link_mode_ls10(nvlink_link *link, NvU64 *mode);
NvlStatus nvswitch_corelib_get_tx_mode_ls10(nvlink_link *link, NvU64 *mode, NvU32 *subMode);
NvlStatus nvswitch_corelib_get_rx_mode_ls10(nvlink_link *link, NvU64 *mode, NvU32 *subMode);
NvlStatus nvswitch_ctrl_get_sw_info_ls10(nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p);
NvlStatus nvswitch_launch_ALI_link_training_ls10(nvswitch_device *device, nvlink_link *link, NvBool bSync);
NvlStatus nvswitch_service_nvldl_fatal_link_ls10(nvswitch_device *device, NvU32 nvliptInstance, NvU32 link);
NvlStatus nvswitch_ctrl_inband_send_data_ls10(nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p);
NvlStatus nvswitch_ctrl_inband_read_data_ls10(nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p);
void nvswitch_send_inband_nack_ls10(nvswitch_device *device, NvU32 *msghdr, NvU32 linkId);
NvU32 nvswitch_get_max_persistent_message_count_ls10(nvswitch_device *device);
NvlStatus nvswitch_service_minion_link_ls10(nvswitch_device *device, NvU32 nvliptInstance);
void nvswitch_apply_recal_settings_ls10(nvswitch_device *device, nvlink_link *link);
void nvswitch_store_topology_information_ls10(nvswitch_device *device, nvlink_link *link);
NvlStatus nvswitch_ctrl_i2c_indexed_ls10(nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams);
NvBool nvswitch_i2c_is_device_access_allowed_ls10(nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead);
NvlStatus nvswitch_minion_get_ali_debug_registers_ls10(nvswitch_device *device, nvlink_link *link, NVSWITCH_MINION_ALI_DEBUG_REGISTERS *params);
void nvswitch_setup_link_system_registers_ls10(nvswitch_device *device, nvlink_link *link);
void nvswitch_load_link_disable_settings_ls10(nvswitch_device *device, nvlink_link *link);
void nvswitch_execute_unilateral_link_shutdown_ls10(nvlink_link *link);
void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link);
NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 link_mask);
void nvswitch_service_minion_all_links_ls10(nvswitch_device *device);
//
// SU generated functions
//
NvlStatus nvswitch_nvs_top_prod_ls10(nvswitch_device *device);
NvlStatus nvswitch_apply_prod_nvlw_ls10(nvswitch_device *device);
NvlStatus nvswitch_apply_prod_nxbar_ls10(nvswitch_device *device);
NvlStatus nvswitch_launch_ALI_ls10(nvswitch_device *device);
NvlStatus nvswitch_ctrl_set_mc_rid_table_ls10(nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p);
NvlStatus nvswitch_ctrl_get_mc_rid_table_ls10(nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p);
void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link);
NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 link_mask);
void nvswitch_service_minion_all_links_ls10(nvswitch_device *device);
NvBool nvswitch_is_inforom_supported_ls10(nvswitch_device *device);
#endif //_LS10_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _MINION_LS10_H_
#define _MINION_LS10_H_
#include "ls10.h"
#include "nvlink_inband_drv_header.h"
#define FALCON_IMEM_BLK_SIZE_BYTES_LS10 256
#define FALCON_CODE_HDR_OS_CODE_OFFSET_LS10 0
#define FALCON_CODE_HDR_OS_CODE_SIZE_LS10 1
#define FALCON_CODE_HDR_OS_DATA_OFFSET_LS10 2
#define FALCON_CODE_HDR_OS_DATA_SIZE_LS10 3
#define FALCON_CODE_HDR_NUM_APPS_LS10 4
#define FALCON_CODE_HDR_APP_CODE_START_LS10 5
#define FALCON_CODE_HDR_APP_DATA_START_LS10 ( FALCON_CODE_HDR_APP_CODE_START_LS10 + (FALCON_CODE_HDR_NUM_APPS_LS10 * 2))
#define FALCON_CODE_HDR_CODE_OFFSET_LS10 0
#define FALCON_CODE_HDR_CODE_SIZE_LS10 1
#define FALCON_CODE_HDR_DATA_OFFSET_LS10 0
#define FALCON_CODE_HDR_DATA_SIZE_LS10 1
#define NV_MINION_NVLINK_DL_STAT_ARGS_LANEID 15:12
#define NV_MINION_NVLINK_DL_STAT_ARGS_ADDRS 11:0
//
// Inband data structure
//
typedef struct inband_send_data
{
// Inband buffer at sender Minion
NvU8 *sendBuffer;
// Number of bytes of data to be sent
NvU32 bufferSize;
// Header
nvlink_inband_drv_hdr_t hdr;
} nvswitch_inband_send_data;
//
// Internal function declarations
//
NvlStatus nvswitch_minion_get_dl_status_ls10(nvswitch_device *device, NvU32 linkId, NvU32 statusIdx, NvU32 statusArgs, NvU32 *statusData);
NvlStatus nvswitch_set_minion_initialized_ls10(nvswitch_device *device, NvU32 idx_minion, NvBool initialized);
NvBool nvswitch_is_minion_initialized_ls10(nvswitch_device *device, NvU32 idx_minion);
NvlStatus nvswitch_init_minion_ls10(nvswitch_device *device);
NvlStatus nvswitch_minion_send_command_ls10(nvswitch_device *device, NvU32 linkNumber, NvU32 command, NvU32 scratch0);
NvlStatus nvswitch_minion_riscv_get_physical_address_ls10(nvswitch_device *device,NvU32 idx_minion, NvU32 target, NvLength offset, NvU64 *pRiscvPa);
NvlStatus nvswitch_minion_set_sim_mode_ls10(nvswitch_device *device, nvlink_link *link);
NvlStatus nvswitch_minion_set_smf_settings_ls10(nvswitch_device *device, nvlink_link *link);
NvlStatus nvswitch_minion_select_uphy_tables_ls10(nvswitch_device *device, nvlink_link *link);
NvBool nvswitch_minion_is_riscv_active_ls10(nvswitch_device *device, NvU32 idx_minion);
NvlStatus nvswitch_minion_clear_dl_error_counters_ls10(nvswitch_device *device, NvU32 linkId);
NvlStatus nvswitch_minion_send_inband_data_ls10(nvswitch_device *device, NvU32 linkId, nvswitch_inband_send_data *inBandData);
void nvswitch_minion_receive_inband_data_ls10(nvswitch_device *device, NvU32 linkId);
NvlStatus nvswitch_minion_log_ali_debug_registers_ls10(nvswitch_device *device, nvlink_link *link);
#endif //_MINION_LS10_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _MINION_NVLINK_DEFINES_PUBLIC_H_
#define _MINION_NVLINK_DEFINES_PUBLIC_H_
// SUBCODES for DLCMD FAULT (uses DLCMDFAULR code) - dlCmdFault() - NVLINK_LINK_INT
typedef enum _MINION_STATUS
{
MINION_OK = 0,
MINION_ALARM_BUSY = 80,
} MINION_STATUS;
#endif // _MINION_NVLINK_DEFINES_PUBLIC_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _MULTICAST_LS10_H_
#define _MULTICAST_LS10_H_
#define NVSWITCH_MC_TCP_LIST_SIZE_LS10 NVSWITCH_NUM_LINKS_LS10 / 2
#define NVSWITCH_MC_MAX_SPRAY_LS10 16
#define NVSWITCH_MC_NUM_COLUMNS_LS10 6
#define NVSWITCH_MC_NUM_COLUMN_PAIRS_LS10 NVSWITCH_MC_NUM_COLUMNS_LS10 / 2
#define NVSWITCH_MC_PORTS_PER_COLUMN_LS10 11
#define NVSWITCH_MC_MIN_PORTS_PER_GROUP_LS10 1
#define PRIMARY_REPLICA_NONE 0
#define PRIMARY_REPLICA_EVEN 1
#define PRIMARY_REPLICA_ODD 2
#define NVSWITCH_MC_INVALID 0xFF
#define NVSWITCH_MC_NULL_PORT_LS10 0xF
//
// Debug and trace print toggles
// To enable tracing, define NVSWITCH_MC_TRACE
//
#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS)
#define NVSWITCH_MC_DEBUG 1
#endif
typedef struct {
NvU32 column;
NvU32 port_offset;
} NVSWITCH_COLUMN_PORT_OFFSET_LS10;
typedef struct {
NvU8 tcp; // Tile column pair
NvU8 tcpEPort; // Port index within even column
NvU8 tcpEVCHop; // VC selection
NvU8 tcpOPort; // Port index within odd column
NvU8 tcpOVCHop; // VC selection
NvU8 roundSize; // This is no longer part of the hardware structure. We retain it here
// because it is useful in various loops
NvU8 primaryReplica;// This field is not in hardware. This code uses it to
// track which port should be primary, so that it can make a pass over
// the assembled tcp directive list and adjust portFlag and
// continueRound as needed to indicate primary replica
// valid values are:
// PRIMARY_REPLICA_NONE (0b00): no primary replica in tcp
// PRIMARY_REPLICA_EVEN (0b01): even (0) port is primary replica
// PRIMARY_REPLICA_ODD (0b10): odd (1) port is primary replica
NvBool tcpEAltPath :1;// Alternative to select from odd column
NvBool tcpOAltPath :1;// Alternative to select from even column
NvBool lastRound :1;// last TCP directive of the last round in this multicast string
// could be multiple strings in case of spray
NvBool continueRound:1;// dual meaning:
// 1) if lastRound = 1 and continueRound = 1, primary replica is in
// this TCP directive and portFlag = 0/1 selects even/odd port
// 2) if lastRound = 0 there are more TCP directives for this round.
NvBool portFlag :1;// triple meaning:
// 1) if lastRound = 1 and continueRound = 1, primary replica is in
// this TCP directive and portFlag = 0/1 selects even/odd port
// 2) If the previous TCP directive was not used to select the even/odd
// port of its predecessor, and if portFlag of the previous TCP
// directive = 1, portFlag of this TCP directive = 0/1 selects
// the even/odd port of its predecessor
// 3) if the previous TCP directive's portFlag = 0, and if it was not
// used to select the even or odd port of its predecessor, this TCP
// directive's portFlag == 1, this TCP directive contains the
// primary replica, and the next TCP directive's portFlag = 0/1
// selects the even/odd port of this TCP directive
} NVSWITCH_TCP_DIRECTIVE_LS10;
typedef struct {
NvU8 index;
NvBool use_extended_table;
NvU8 mcpl_size;
NvU8 num_spray_groups;
NvU8 ext_ptr;
NvBool no_dyn_rsp;
NvBool ext_ptr_valid;
NvBool valid;
NVSWITCH_TCP_DIRECTIVE_LS10 directives[NVSWITCH_MC_TCP_LIST_SIZE_LS10];
NvU8 spray_group_ptrs[NVSWITCH_MC_MAX_SPRAY_LS10];
} NVSWITCH_MC_RID_ENTRY_LS10;
NvlStatus nvswitch_mc_build_mcp_list_ls10(nvswitch_device *device, NvU32 *port_list,
NvU32 *ports_per_spray_string,
NvU32 *pri_replica_offsets, NvBool *replica_valid_array,
NvU8 *vchop_array,
NVSWITCH_MC_RID_ENTRY_LS10 *table_entry,
NvU32 *entries_used);
NvlStatus nvswitch_mc_unwind_directives_ls10(nvswitch_device *device,
NVSWITCH_TCP_DIRECTIVE_LS10* directives,
NvU32 *ports, NvU8 *vc_hop,
NvU32 *ports_per_spray_group, NvU32 *replica_offset,
NvBool *replica_valid);
NvlStatus nvswitch_mc_invalidate_mc_rid_entry_ls10(nvswitch_device *device, NvU32 port, NvU32 index,
NvBool use_extended_table, NvBool zero);
NvlStatus nvswitch_mc_program_mc_rid_entry_ls10(nvswitch_device *device, NvU32 port,
NVSWITCH_MC_RID_ENTRY_LS10 *table_entry,
NvU32 directive_list_size);
NvlStatus nvswitch_mc_read_mc_rid_entry_ls10(nvswitch_device *device, NvU32 port,
NVSWITCH_MC_RID_ENTRY_LS10 *table_entry);
#endif //_MULTICAST_LS10_H_

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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _PMGR_LS10_H_
#define _PMGR_LS10_H_
#include "ls10.h"
void
nvswitch_init_pmgr_ls10
(
nvswitch_device *device
);
void
nvswitch_init_pmgr_devices_ls10
(
nvswitch_device *device
);
NvU32
nvswitch_read_physical_id_ls10
(
nvswitch_device *device
);
NvlStatus
nvswitch_get_rom_info_ls10
(
nvswitch_device *device,
NVSWITCH_EEPROM_TYPE *eeprom
);
void
nvswitch_i2c_set_hw_speed_mode_ls10
(
nvswitch_device *device,
NvU32 port,
NvU32 speedMode
);
NvBool
nvswitch_is_i2c_supported_ls10
(
nvswitch_device *device
);
#endif //_PMGR_LS10_H_

91
src/common/nvswitch/kernel/inc/ls10/smbpbi_ls10.h Normal file
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@@ -0,0 +1,91 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _SMBPBI_LS10_H_
#define _SMBPBI_LS10_H_
NvlStatus
nvswitch_smbpbi_alloc_ls10
(
nvswitch_device *device
);
NvlStatus
nvswitch_smbpbi_post_init_hal_ls10
(
nvswitch_device *device
);
void
nvswitch_smbpbi_destroy_hal_ls10
(
nvswitch_device *device
);
NvlStatus
nvswitch_smbpbi_get_dem_num_messages_ls10
(
nvswitch_device *device,
NvU8 *pMsgCount
);
NvlStatus
nvswitch_inforom_dem_load_ls10
(
nvswitch_device *device
);
NvlStatus
nvswitch_smbpbi_dem_load_ls10
(
nvswitch_device *device
);
void
nvswitch_smbpbi_send_unload_ls10
(
nvswitch_device *device
);
void
nvswitch_smbpbi_dem_flush_ls10
(
nvswitch_device *device
);
void
nvswitch_smbpbi_log_message_ls10
(
nvswitch_device *device,
NvU32 num,
NvU32 msglen,
NvU8 *osErrorString
);
NvlStatus
nvswitch_smbpbi_send_init_data_ls10
(
nvswitch_device *device
);
#endif //_SMBPBI_LS10_H_

46
src/common/nvswitch/kernel/inc/ls10/soe_ls10.h Normal file
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@@ -0,0 +1,46 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _SOE_LS10_H_
#define _SOE_LS10_H_
#include "ls10.h"
//
// Functions shared with LR10
//
#include "rmflcncmdif_nvswitch.h"
NvlStatus nvswitch_init_soe_ls10(nvswitch_device *device);
NvlStatus nvswitch_unload_soe_ls10(nvswitch_device *device);
NvlStatus nvswitch_soe_register_event_callbacks_ls10(nvswitch_device *device);
void nvswitch_cci_soe_callback_ls10(nvswitch_device *device, RM_FLCN_MSG *pGenMsg,
void *pParams, NvU32 seqDesc, NV_STATUS status);
NvlStatus nvswitch_set_nport_tprod_state_ls10(nvswitch_device *device, NvU32 nport);
void nvswitch_soe_unregister_events_ls10(nvswitch_device *device);
NvlStatus nvswitch_soe_register_event_callbacks_ls10(nvswitch_device *device);
NvlStatus nvswitch_soe_restore_nport_state_ls10(nvswitch_device *device, NvU32 nport);
NvlStatus nvswitch_soe_issue_nport_reset_ls10(nvswitch_device *device, NvU32 nport);
#endif //_SOE_LS10_H_

77
src/common/nvswitch/kernel/inc/ls10/sugen_ls10.h Normal file
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@@ -0,0 +1,77 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _SUGEN_LS10_H_
#define _SUGEN_LS10_H_
#include "common_nvswitch.h"
#include "ls10/ls10.h"
#include "nvswitch/ls10/dev_nvs_top.h"
#include "nvswitch/ls10/dev_pri_masterstation_ip.h"
#include "nvswitch/ls10/dev_pri_ringstation_sys_ip.h"
#include "nvswitch/ls10/dev_pri_ringstation_sysb_ip.h"
#include "nvswitch/ls10/dev_pri_ringstation_prt_ip.h"
#include "nvswitch/ls10/dev_pri_hub_sys_ip.h"
#include "nvswitch/ls10/dev_pri_hub_sysb_ip.h"
#include "nvswitch/ls10/dev_pri_hub_prt_ip.h"
#include "nvswitch/ls10/dev_nvlsaw_ip.h"
#include "nvswitch/ls10/dev_ctrl_ip.h"
#include "nvswitch/ls10/dev_timer_ip.h"
#include "nvswitch/ls10/dev_trim.h"
#include "nvswitch/ls10/dev_nv_xal_ep.h"
#include "nvswitch/ls10/dev_nv_xpl.h"
#include "nvswitch/ls10/dev_xtl_ep_pri.h"
#include "nvswitch/ls10/dev_soe_ip.h"
#include "nvswitch/ls10/dev_se_pri.h"
#include "nvswitch/ls10/dev_perf.h"
#include "nvswitch/ls10/dev_pmgr.h"
#include "nvswitch/ls10/dev_therm.h"
// NVLW
#include "nvswitch/ls10/dev_nvlw_ip.h"
#include "nvswitch/ls10/dev_cpr_ip.h"
#include "nvswitch/ls10/dev_nvlipt_ip.h"
#include "nvswitch/ls10/dev_nvlipt_lnk_ip.h"
#include "nvswitch/ls10/dev_nvltlc_ip.h"
#include "nvswitch/ls10/dev_nvldl_ip.h"
#include "nvswitch/ls10/dev_minion_ip.h"
// NPG/NPORT
#include "nvswitch/ls10/dev_npg_ip.h"
#include "nvswitch/ls10/dev_npgperf_ip.h"
#include "nvswitch/ls10/dev_nport_ip.h"
#include "nvswitch/ls10/dev_route_ip.h"
#include "nvswitch/ls10/dev_tstate_ip.h"
#include "nvswitch/ls10/dev_egress_ip.h"
#include "nvswitch/ls10/dev_ingress_ip.h"
#include "nvswitch/ls10/dev_sourcetrack_ip.h"
#include "nvswitch/ls10/dev_multicasttstate_ip.h"
#include "nvswitch/ls10/dev_reductiontstate_ip.h"
// NXBAR
#include "nvswitch/ls10/dev_nxbar_tile_ip.h"
#include "nvswitch/ls10/dev_nxbar_tileout_ip.h"
#endif //_SUGEN_LS10_H_

53
src/common/nvswitch/kernel/inc/ls10/therm_ls10.h Normal file
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@@ -0,0 +1,53 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _THERM_LS10_H_
#define _THERM_LS10_H_
NvlStatus
nvswitch_init_thermal_ls10
(
nvswitch_device *device
);
NvlStatus
nvswitch_ctrl_therm_read_temperature_ls10
(
nvswitch_device *device,
NVSWITCH_CTRL_GET_TEMPERATURE_PARAMS *info
);
NvlStatus
nvswitch_ctrl_therm_get_temperature_limit_ls10
(
nvswitch_device *device,
NVSWITCH_CTRL_GET_TEMPERATURE_LIMIT_PARAMS *info
);
void
nvswitch_monitor_thermal_alert_ls10
(
nvswitch_device *device
);
#endif //_THERM_LS10_H_

8
src/common/nvswitch/kernel/inc/pmgr_nvswitch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -301,6 +301,12 @@ struct NVSWITCH_OBJI2C
// I2C device allow list
NVSWITCH_I2C_DEVICE_DESCRIPTOR_TYPE *i2c_allow_list;
NvU32 i2c_allow_list_size;
// For I2C via SOE support
NvBool soeI2CSupported;
NvBool kernelI2CSupported;
void *pCpuAddr;
NvU64 dmaHandle;
};
//

49
src/common/nvswitch/kernel/inc/regkey_nvswitch.h
View File

@@ -323,6 +323,8 @@
#define NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_40G 0x0F
#define NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_50G 0x10
#define NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_53_12500G 0x11
#define NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_100_00000G 0x12
#define NV_SWITCH_REGKEY_SPEED_CONTROL_SPEED_106_25000G 0x13
/*
* Enable/Disable periodic flush to inforom. Default is disabled.
@@ -516,13 +518,23 @@
#define NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL_ENABLE 0x1
#define NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL_DISABLE 0x0
/*
* NV_SWITCH_REGKEY_FORCE_KERNEL_I2C - Used to force Kernel I2C path
*
* Private: Debug use only
*/
#define NV_SWITCH_REGKEY_FORCE_KERNEL_I2C "ForceKernelI2c"
#define NV_SWITCH_REGKEY_FORCE_KERNEL_I2C_DEFAULT 0x0
#define NV_SWITCH_REGKEY_FORCE_KERNEL_I2C_ENABLE 0x1
#define NV_SWITCH_REGKEY_FORCE_KERNEL_I2C_DISABLE 0x0
/*
* NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT - Configure the CRC bit error rate for the short interrupt
*
* Public: Available in release drivers
*/
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT "CRCBitErrorRateShort"
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_OFF 0x0
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT 0x0
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN 2:0
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP 3:3
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN 6:4
@@ -534,7 +546,7 @@
* Public: Available in release drivers
*/
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG "CRCBitErrorRateLong"
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_OFF 0x000
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_DEFAULT 0x000
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_BUG_3365481_CASE_1 0x803
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_BUG_3365481_CASE_2 0x703
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_BUG_3365481_CASE_5 0x34D
@@ -544,4 +556,37 @@
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_TIMESCALE_MAN 6:4
#define NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_LONG_TIMESCALE_EXP 12:8
/*
* NV_SWITCH_REGKEY_SET_LP_THRESHOLD - Sets the LP Threshold Value
*
* Private: Debug use only
*/
#define NV_SWITCH_REGKEY_SET_LP_THRESHOLD "LPThreshold"
#define NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT 0x0
/*
* NV_SWITCH_REGKEY_MINION_INTERRUPTS - Enable/disable MINION interrupts
*
* Used for bug #3572329. To be removed once fmodel conflict is resolved.
*
* Public: Available in release drivers
*/
#define NV_SWITCH_REGKEY_MINION_INTERRUPTS "MINIONIntr"
#define NV_SWITCH_REGKEY_MINION_INTERRUPTS_DEFAULT 0x0
#define NV_SWITCH_REGKEY_MINION_INTERRUPTS_ENABLE 0x1
#define NV_SWITCH_REGKEY_MINION_INTERRUPTS_DISABLE 0x2
/*
* NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET - surpresses error prints/notifs
*
* When set, Heartbeat timeout, Short Error Rate and Fault Up interrupts won't be
* logged
*
* Public: Available in release drivers
*/
#define NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET "SurpressLinkErrorsForGpuReset"
#define NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET_DISABLE 0x0
#define NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET_ENABLE 0x1
#endif //_REGKEY_NVSWITCH_H_

4
src/common/nvswitch/kernel/inc/smbpbi_nvswitch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -45,6 +45,7 @@ struct smbpbi
{
SOE_SMBPBI_SHARED_SURFACE *sharedSurface;
NvU64 dmaHandle;
NvU32 logMessageNesting;
};
NvlStatus nvswitch_smbpbi_init(nvswitch_device *);
@@ -55,6 +56,5 @@ NvlStatus nvswitch_smbpbi_set_link_error_info(nvswitch_device *,
void nvswitch_smbpbi_unload(nvswitch_device *);
void nvswitch_smbpbi_destroy(nvswitch_device *);
NvlStatus nvswitch_smbpbi_refresh_ecc_counts(nvswitch_device *);
void nvswitch_smbpbi_log_message(nvswitch_device *device, NvU32 num, NvU32 msglen, NvU8 *osErrorString);
#endif //_SMBPBI_NVSWITCH_H_

3046
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
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File diff suppressed because it is too large Load Diff

3046
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
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File diff suppressed because it is too large Load Diff

6
src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,6 +28,7 @@
#include "nvstatus.h"
#include "flcnifcmn.h"
#include "flcn/haldefs_flcnable_nvswitch.h"
#include "common_nvswitch.h"
struct SOE;
@@ -112,6 +113,9 @@ typedef struct {
NvlStatus (*setPcieLinkSpeed)(
struct nvswitch_device *device,
NvU32 linkSpeed);
NvlStatus (*i2cAccess)(
struct nvswitch_device *device,
NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams);
} soe_hal;
// HAL functions

4
src/common/nvswitch/kernel/inc/soe/soe_nvswitch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,6 +27,7 @@
#include "nvlink_errors.h"
#include "nvtypes.h"
#include "nvstatus.h"
#include "common_nvswitch.h"
typedef struct SOE SOE, *PSOE;
struct FLCNABLE;
@@ -55,5 +56,6 @@ NvlStatus soeGetPexEomStatus_HAL (struct nvswitch_device *device, NvU8 mo
NvlStatus soeGetUphyDlnCfgSpace_HAL (struct nvswitch_device *device, NvU32 regAddress, NvU32 laneSelectMask, NvU16 *pRegValue);
NvlStatus soeForceThermalSlowdown_HAL (struct nvswitch_device *device, NvBool slowdown, NvU32 periodUs);
NvlStatus soeSetPcieLinkSpeed_HAL (struct nvswitch_device *device, NvU32 linkSpeed);
NvlStatus soeI2CAccess_HAL (struct nvswitch_device *device, NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams);
#endif //_SOE_NVSWITCH_H_

2
src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a