520.61.05

src/common/displayport/inc/dp_connector.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -260,6 +260,9 @@ namespace DisplayPort
         virtual bool isMSAOverMSTCapable() = 0;
         virtual bool isFakedMuxDevice() = 0;
 
+        virtual bool setPanelReplayConfig(panelReplayConfig prcfg) = 0;
+        virtual bool isPanelReplaySupported() = 0;
+
     protected:
             virtual ~Device() {}
 

src/common/displayport/inc/dp_connectorimpl.h

@@ -315,14 +315,6 @@ namespace DisplayPort
         //
         bool        bDscMstCapBug3143315;
 
-        //
-        // Enable DSC Pass through support in driver based on regkey.
-        //
-        bool        bDscMstEnablePassThrough;
-
-        // Reduce number of 2H1OR LTs which fixes bug 3534707
-        bool        bDscOptimizeLTBug3534707;
-
         //
         // Synaptics branch device doesn't support Virtual Peer Devices so DSC
         // capability of downstream device should be decided based on device's own

src/common/displayport/inc/dp_deviceimpl.h

@@ -173,6 +173,8 @@ namespace DisplayPort
         bool bIsFakedMuxDevice;
         bool bIsPreviouslyFakedMuxDevice;
         bool bisMarkedForDeletion;
+        bool bIgnoreMsaCap;
+        bool bIgnoreMsaCapCached;
 
         //
         // Device doing the DSC decompression for this device. This could be device itself
@@ -194,6 +196,7 @@ namespace DisplayPort
 
         TriState bSdpExtCapable;
         bool bMSAOverMSTCapable;
+        bool bDscPassThroughColorFormatWar;
 
         DeviceImpl(DPCDHAL * hal, ConnectorImpl * connector, DeviceImpl * parent);
         ~DeviceImpl();
@@ -349,15 +352,9 @@ namespace DisplayPort
             return true;
         }
 
-        bool getIgnoreMSACap()
-        {
-            return hal->getMsaTimingparIgnored();
-        }
+        bool getIgnoreMSACap();
 
-        AuxRetry::status setIgnoreMSAEnable(bool msaTimingParamIgnoreEn)
-        {
-            return hal->setIgnoreMSATimingParamters(msaTimingParamIgnoreEn);
-        }
+        AuxRetry::status setIgnoreMSAEnable(bool msaTimingParamIgnoreEn);
 
         bool isVirtualPeerDevice()
         {

src/common/displayport/inc/dp_edid.h

@@ -308,7 +308,9 @@ namespace DisplayPort
 
     static const NvU8 ddcAddrList[] = {EDID_DDC_ADR0, EDID_DDC_ADR1, EDID_DDC_ADR2};
     const NvU8 ddcAddrListSize = sizeof(ddcAddrList)/sizeof(NvU8);
-    const NvU8 EDID_READ_MAX_RETRY_COUNT = 6;
+
+    // HDMI 1.4 Section 8.5: HDMI Sink can have up to 100ms to get EDID ready.
+    const NvU8 EDID_READ_RETRY_TIMEOUT_MS = 100;
     const NvU8 EDID_MAX_AUX_RETRIES = 10;
     const NvU8 EDID_AUX_WAIT_TIME = 1;
     NvU8 getEDIDBlockChecksum(const Buffer &);

src/common/displayport/inc/dp_groupimpl.h

@@ -68,8 +68,6 @@ namespace DisplayPort
             Watermark         watermarks;           // Cached watermark calculations
         } timeslot;
 
-        bool            bIsCurrentModesetGroup;     // Group that is getting attached 
-
         GroupImpl(ConnectorImpl * parent, bool isFirmwareGroup = false)
             : parent(parent),
               streamValidationDone(true),
@@ -82,7 +80,6 @@ namespace DisplayPort
               dscModeActive(DSC_MODE_NONE),
               singleHeadMultiStreamID(DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY),
               singleHeadMultiStreamMode(DP_SINGLE_HEAD_MULTI_STREAM_MODE_NONE),
-              bIsCurrentModesetGroup(false),
               headAttached(false)
         {
             timeslot.count = 0;

src/common/displayport/inc/dp_linkconfig.h

@@ -145,6 +145,7 @@ namespace DisplayPort
         EDP_3_24GHZ = 324000000,
         EDP_4_32GHZ = 432000000,
         HBR2        = 540000000,
+        EDP_6_75GHZ = 675000000,
         HBR3        = 810000000
     };
 

src/common/displayport/inc/dp_messages.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a

src/common/displayport/inc/dp_regkeydatabase.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -65,12 +65,6 @@
 //
 #define NV_DP_DSC_MST_CAP_BUG_3143315                  "DP_DSC_MST_CAP_BUG_3143315"
 
-// Enable DSC Pass through support in MST mode.
-#define NV_DP_DSC_MST_ENABLE_PASS_THROUGH              "DP_DSC_MST_ENABLE_PASS_THROUGH"
-
-// Regkey to reduce number of 2H1OR LTs which fixes bug 3534707
-#define NV_DP_DSC_OPTIMIZE_LT_BUG_3534707              "DP_DSC_OPTIMIZE_LT_BUG_3534707"
-
 #define NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING   "NO_REPLY_TIMER_FOR_BUSY_WAITING"
 
 #define NV_DP_REGKEY_DPCD_PROBING_FOR_BUSY_WAITING     "DP_DPCD_PROBING_FOR_BUSY_WAITING"
@@ -106,8 +100,6 @@ struct DP_REGKEY_DATABASE
     bool  bOptLinkKeptAliveSst;
     bool  bBypassEDPRevCheck;
     bool  bDscMstCapBug3143315;
-    bool  bDscMstEnablePassThrough;
-    bool  bDscOptimizeLTBug3534707;
     bool  bNoReplyTimerForBusyWaiting;
     bool  bDpcdProbingForBusyWaiting;
 };

src/common/displayport/src/dp_connectorimpl.cpp

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -188,8 +188,6 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
     this->bDisableSSC                   = dpRegkeyDatabase.bSscDisabled;
     this->bEnableFastLT                 = dpRegkeyDatabase.bFastLinkTrainingEnabled;
     this->bDscMstCapBug3143315          = dpRegkeyDatabase.bDscMstCapBug3143315;
-    this->bDscMstEnablePassThrough      = dpRegkeyDatabase.bDscMstEnablePassThrough;
-    this->bDscOptimizeLTBug3534707      = dpRegkeyDatabase.bDscOptimizeLTBug3534707;
 }
 
 void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -633,27 +631,56 @@ create:
         newDev->queryGUID2();
     }
 
-    // Read panel DSC support only if GPU supports DSC
-    bool bGpuDscSupported;
-    main->getDscCaps(&bGpuDscSupported);
-    if (bGpuDscSupported)
+    if (!linkAwaitingTransition)
     {
-        if (newDev->getDSCSupport())
-        {
-            // Read and parse DSC caps only if panel supports DSC
-            newDev->readAndParseDSCCaps();
+        //
+        // When link is awaiting SST<->MST transition, DSC caps read from downstream
+        // DSC branch device might be wrong. DSC Caps exposed by DSC MST branch depends
+        // on the current link state. If it is in SST mode ie MST_EN (0x111[bit 0]) is 0 and
+        // panel connected behind it supports DSC, then branch will expose the DSC caps
+        // of the panel connected down stream rather than it's own. This is because source
+        // will have no other way to read the caps of the downstream panel. In fact when
+        // MST_EN = 0 and UP_REQ_EN (0x111 [bit 1]) = 1 source can read the caps of the
+        // downstream panel using REMOTE_DPCD_READ but branch device's behavior depends
+        // only on MST_EN bit. Similarly in SST, if the panel connected downstream to branch
+        // does not support DSC, DSC MST branch will expose it's own DSC caps.
+        // During boot since VBIOS drives display in SST mode and when driver takes over,
+        // linkAwaitingTransition will be true. DpLib does link assessment and topology
+        // discovery by setting UP_REQ_EN to true while still keeping MST_EN to false.
+        // This is to ensure we detach the head and active modeset groups that are in SST mode
+        // before switching the link to MST mode. When processNewDevice is called at this
+        // point to create new devices we should not read DSC caps due to above mentioned reason.
+        // As long as linkIsAwaitingTransition is true, Dplib will not report new Devices to
+        // to client since isPendingNewDevice() will be false even though DPlib discovered
+        // new devices. After Dplib completes topology discovery, DD initiates notifyDetachBegin/End
+        // to remove active groups from the link and notifyDetachEnd calls assessLink
+        // where we toggle the link state. Only after this we should read DSC caps in this case.
+        // Following this assesslink calls fireEvents() which will report
+        // the new devies to clients and client will have the correct DSC caps.
+        // 
+        bool bGpuDscSupported;
 
-            // Read and Parse Branch Specific DSC Caps
-            if (!newDev->isVideoSink() && !newDev->isAudioSink())
+        // Check GPU DSC Support
+        main->getDscCaps(&bGpuDscSupported);
+        if (bGpuDscSupported)
+        {
+            if (newDev->getDSCSupport())
             {
-                newDev->readAndParseBranchSpecificDSCCaps();
-            }
-        }
+                // Read and parse DSC caps only if panel supports DSC
+                newDev->readAndParseDSCCaps();
 
-        if (!processedEdid.WARFlags.bIgnoreDscCap)
-        {
-            // Check if DSC is possible for the device and if so, set DSC Decompression device.
-            newDev->setDscDecompressionDevice(this->bDscCapBasedOnParent);
+                // Read and Parse Branch Specific DSC Caps
+                if (!newDev->isVideoSink() && !newDev->isAudioSink())
+                {
+                    newDev->readAndParseBranchSpecificDSCCaps();
+                }
+            }
+
+            if (!processedEdid.WARFlags.bIgnoreDscCap)
+            {
+                // Check if DSC is possible for the device and if so, set DSC Decompression device.
+                newDev->setDscDecompressionDevice(this->bDscCapBasedOnParent);
+            }
         }
     }
 
@@ -675,6 +702,8 @@ create:
         newDev->bMSAOverMSTCapable = false;
     }
 
+    newDev->applyOUIOverrides();
+
     fireEvents();
 }
 
@@ -1194,6 +1223,40 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
                     DP_LOG(("Current version is 1.1"));
                 }
 
+                if ((dev->devDoingDscDecompression == dev) && dev->parent)
+                {
+                    if (dev->parent->bDscPassThroughColorFormatWar)
+                    {
+                        //
+                        // Bug 3692417
+                        // Color format should only depend on device doing DSC decompression when DSC is enabled according to DP Spec. 
+                        // But when Synaptics VMM5320 is the parent of the device doing DSC decompression, if a certain color 
+                        // format is not supported by Synaptics Virtual Peer Device decoder(parent), even though it is pass through mode
+                        // and panel supports the color format, panel cannot light up. Once Synaptics fixes this issue, we will modify 
+                        // the WAR to be applied only before the firmware version that fixes it.
+                        //
+                        if ((modesetParams.colorFormat == dpColorFormat_RGB      && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bRgb) ||
+                            (modesetParams.colorFormat == dpColorFormat_YCbCr444 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCr444) || 
+                            (modesetParams.colorFormat == dpColorFormat_YCbCr422 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCrSimple422))
+                        {
+                            if (pDscParams->forceDsc == DSC_FORCE_ENABLE)
+                            {
+                                // If DSC is force enabled then return failure here
+                                compoundQueryResult = false;
+                                pDscParams->bEnableDsc = false;
+                                return false;
+                            }
+                            else
+                            {
+                                // We should check if mode is possible without DSC.
+                                pDscParams->bEnableDsc = false;
+                                lc.enableFEC(false);
+                                goto nonDscDpIMP;
+                            }
+                        }
+                    }
+                }
+
                 availableBandwidthBitsPerSecond = lc.minRate * 8 * lc.lanes;
 
                 warData.dpData.linkRateHz = lc.peakRate;
@@ -2550,7 +2613,6 @@ bool ConnectorImpl::notifyAttachBegin(Group *                target,       // Gr
     }
 
     GroupImpl* targetImpl = (GroupImpl*)target;
-    targetImpl->bIsCurrentModesetGroup = true;
 
     if (bEnableDsc)
     {
@@ -2667,7 +2729,6 @@ bool ConnectorImpl::notifyAttachBegin(Group *                target,       // Gr
     NV_DPTRACE_INFO(NOTIFY_ATTACH_BEGIN_STATUS, bLinkTrainingStatus);
 
     bFromResumeToNAB = false;
-    targetImpl->bIsCurrentModesetGroup = false;
     return bLinkTrainingStatus;
 }
 
@@ -3283,6 +3344,7 @@ bool ConnectorImpl::trainSingleHeadMultipleSSTLinkNotAlive(GroupImpl *pGroupAtta
 void ConnectorImpl::assessLink(LinkTrainingType trainType)
 {
     this->bSkipLt = false;  // Assesslink should never skip LT, so let's reset it in case it was set.
+    bool bLinkStateToggle = false;
 
     if (bSkipAssessLinkForPCon)
     {
@@ -3409,6 +3471,7 @@ void ConnectorImpl::assessLink(LinkTrainingType trainType)
             linkState = hal->getSupportsMultistream() ?
                 DP_TRANSPORT_MODE_MULTI_STREAM : DP_TRANSPORT_MODE_SINGLE_STREAM;
             linkAwaitingTransition = false;
+            bLinkStateToggle = true;
         }
         else
         {
@@ -3517,6 +3580,30 @@ done:
     {
         disableFlush();
     }
+
+    if (bLinkStateToggle)
+    {
+        DP_LOG(("DP> Link state toggled, reading DSC caps now"));
+        // Read panel DSC support only if GPU supports DSC
+        bool bGpuDscSupported;
+        main->getDscCaps(&bGpuDscSupported);
+        if (bGpuDscSupported)
+        {
+            for (Device * i = enumDevices(0); i; i=enumDevices(i))
+            {
+                DeviceImpl * dev = (DeviceImpl *)i;
+                if(dev->getDSCSupport())
+                {
+                    // Read and parse DSC caps only if panel and GPU supports DSC
+                    dev->readAndParseDSCCaps();
+                }
+                if (!(dev->processedEdid.WARFlags.bIgnoreDscCap))
+                {
+                    dev->setDscDecompressionDevice(this->bDscCapBasedOnParent);
+                }
+            }
+        }
+    }
 }
 
 bool ConnectorImpl::handleCPIRQ()
@@ -3902,36 +3989,21 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
     GroupImpl * groupAttached = 0;
     for (ListElement * e = activeGroups.begin(); e != activeGroups.end(); e = e->next)
     {
-        DP_ASSERT(bIsUefiSystem);
+        DP_ASSERT(bIsUefiSystem || linkUseMultistream() || (!groupAttached && "Multiple attached heads"));
         groupAttached = (GroupImpl * )e;
 
-        if (bDscOptimizeLTBug3534707)
+        if ((groupAttached->dscModeRequest == DSC_DUAL) && (groupAttached->dscModeActive != DSC_DUAL))
         {
-            if ((groupAttached->dscModeRequest == DSC_DUAL) && (groupAttached->dscModeActive != DSC_DUAL))
-            {
-                //
-                // If current modeset group requires 2Head1OR and
-                //  - group is not active yet (first modeset on the group)
-                //  - group is active but not in 2Head1OR mode (last modeset on the group did not require 2Head1OR)
-                // then re-train the link
-                // This is because for 2Head1OR mode, we need to set some LT parametes for slave SOR after
-                // successful LT on primary SOR without which 2Head1OR modeset will lead to HW hang.
-                //
-                bTwoHeadOneOrLinkRetrain = true;
-                break;
-            }
-        }
-        else
-        {
-            if (groupAttached->lastModesetInfo.mode == DSC_DUAL && groupAttached->bIsCurrentModesetGroup)
-            {
-                //
-                // If current modeset group requires 2Head1OR mode, we should retrain link.
-                //   For SST, there will be only one group per connector.
-                //   For MST, we need to re-run LT in case the current modeset group requires DSC_DUAL.
-                bTwoHeadOneOrLinkRetrain = true;
-                break;
-            }
+            //
+            // If current modeset group requires 2Head1OR and 
+            //  - group is not active yet (first modeset on the group)
+            //  - group is active but not in 2Head1OR mode (last modeset on the group did not require 2Head1OR)
+            // then re-train the link
+            // This is because for 2Head1OR mode, we need to set some LT parametes for slave SOR after 
+            // successful LT on primary SOR without which 2Head1OR modeset will lead to HW hang.
+            //
+            bTwoHeadOneOrLinkRetrain = true;
+            break;
         }
     }
 
@@ -4018,9 +4090,9 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
             //
             // Check if we are already trained to the desired link config?
             // Make sure requested FEC state matches with the current FEC state of link.
-            // If 2Head1OR mode is requested, retrain if group is not active or
-            // last modeset on active group was not in 2Head1OR mode.
-            // bTwoHeadOneOrLinkRetrain tracks this requirement.
+            // If 2Head1OR mode is requested, retrain if group is not active or 
+            // last modeset on active group was not in 2Head1OR mode. 
+            // bTwoHeadOneOrLinkRetrain tracks this requirement. 
             //
 
             //
@@ -4033,8 +4105,7 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
             if ((activeLinkConfig == lowestSelected) &&
                 (!isLinkInD3()) &&
                 (!isLinkLost()) &&
-                ((!bDscOptimizeLTBug3534707 && !this->bFECEnable) ||
-                 (bDscOptimizeLTBug3534707  && (this->bFECEnable == activeLinkConfig.bEnableFEC))) &&
+                (this->bFECEnable == activeLinkConfig.bEnableFEC) &&
                 !bTwoHeadOneOrLinkRetrain)
             {
                 if (bSkipRedundantLt || main->isInternalPanelDynamicMuxCapable())
@@ -4151,8 +4222,8 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
         //
         // Make sure link is physically active and healthy, otherwise re-train.
         // Make sure requested FEC state matches with the current FEC state of link.
-        // If 2Head1OR mode is requested, retrain if group is not active or last modeset on active group
-        // was not in 2Head1OR mode. bTwoHeadOneOrLinkRetrain tracks this requirement.
+        // If 2Head1OR mode is requested, retrain if group is not active or last modeset on active group 
+        // was not in 2Head1OR mode. bTwoHeadOneOrLinkRetrain tracks this requirement. 
         //
         bRetrainToEnsureLinkStatus = (isLinkActive() && isLinkInD3()) ||
                                      isLinkLost() ||
@@ -6143,6 +6214,13 @@ void ConnectorImpl::notifyShortPulse()
             }
         }
 
+        // If DPCD access is not available, skip trying to restore link configuration.
+        hal->updateDPCDOffline();
+        if (hal->isDpcdOffline())
+        {
+            return;
+        }
+
         DP_LOG(("DP> Link not alive, Try to restore link configuration"));
 
         if (trainSingleHeadMultipleSSTLinkNotAlive(getActiveGroupForSST()))

src/common/displayport/src/dp_deviceimpl.cpp

@@ -91,7 +91,10 @@ DeviceImpl::DeviceImpl(DPCDHAL * hal, ConnectorImpl * connector, DeviceImpl * pa
       bIsFakedMuxDevice(false),
       bIsPreviouslyFakedMuxDevice(false),
       bisMarkedForDeletion(false),
-      bSdpExtCapable(Indeterminate)
+      bIgnoreMsaCap(false),
+      bIgnoreMsaCapCached(false),
+      bSdpExtCapable(Indeterminate),
+      bDscPassThroughColorFormatWar(false)
 {
     bandwidth.enum_path.dataValid = false;
     shadow.plugged = false;
@@ -921,6 +924,7 @@ void DeviceImpl::applyOUIOverrides()
                     (buffer[8] == 0x31 || buffer[8] == 0x20))
                 {
                     this->bSdpExtCapable = False;
+                    this->bDscPassThroughColorFormatWar = true;
 
                     //
                     // Check firmware version
@@ -1026,7 +1030,7 @@ bool DeviceImpl::getSDPExtnForColorimetrySupported()
                                                 _YES, byte) ? True : False;
         }
     }
-    this->applyOUIOverrides();
+
     if (parentDevice && (this->bSdpExtCapable == True))
     {
         //
@@ -1458,11 +1462,6 @@ NvBool DeviceImpl::getDSCSupport()
         {
             dscCaps.bDSCSupported = true;
         }
-
-        if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH_SUPPORT, _YES, byte))
-        {
-            dscCaps.bDSCPassThroughSupported = true;
-        }
     }
 
     else
@@ -1572,6 +1571,11 @@ bool DeviceImpl::parseDscCaps(const NvU8 *buffer, NvU32 bufferSize)
         return false;
     }
 
+    if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH_SUPPORT, _YES, buffer[0x0]))
+    {
+        dscCaps.bDSCPassThroughSupported = true;
+    }
+
     dscCaps.versionMajor = DRF_VAL(_DPCD14, _DSC_ALGORITHM_REVISION, _MAJOR, buffer[0x1]);
     dscCaps.versionMinor = DRF_VAL(_DPCD14, _DSC_ALGORITHM_REVISION, _MINOR, buffer[0x1]);
 
@@ -1758,6 +1762,21 @@ bool DeviceImpl::readAndParseDSCCaps()
     return parseDscCaps(&rawDscCaps[0], sizeof(rawDscCaps));
 }
 
+bool DeviceImpl::readAndParseBranchSpecificDSCCaps()
+{
+    unsigned sizeCompleted = 0;
+    unsigned nakReason = NakUndefined;
+    NvU8 rawBranchSpecificDscCaps[3];
+
+    if(AuxBus::success != this->getDpcdData(NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0,
+        &rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps), &sizeCompleted, &nakReason))
+    {
+        return false;
+    }
+
+    return parseBranchSpecificDscCaps(&rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps));
+}
+
 void DeviceImpl::queryGUID2()
 {
     unsigned sizeCompleted  = 0;
@@ -1779,21 +1798,6 @@ void DeviceImpl::queryGUID2()
     }
 }
 
-bool DeviceImpl::readAndParseBranchSpecificDSCCaps()
-{
-    unsigned sizeCompleted = 0;
-    unsigned nakReason = NakUndefined;
-    NvU8 rawBranchSpecificDscCaps[3];
-
-    if(AuxBus::success != this->getDpcdData(NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0,
-        &rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps), &sizeCompleted, &nakReason))
-    {
-        return false;
-    }
-
-    return parseBranchSpecificDscCaps(&rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps));
-}
-
 bool DeviceImpl::getDscEnable(bool *pEnable)
 {
     AuxBus::status  status = AuxBus::success;
@@ -1928,7 +1932,8 @@ bool DeviceImpl::setDscEnable(bool enable)
     unsigned nakReason   = NakUndefined;
     bool bCurrDscEnable  = false;
     bool bDscPassThrough = false;
-    bool bDscPassThroughUpdated = true;
+    AuxBus::status dscEnableStatus      = AuxBus::success;
+    AuxBus::status dscPassThroughStatus = AuxBus::success;
     Address::StringBuffer buffer;
     DP_USED(buffer);
 
@@ -1938,7 +1943,7 @@ bool DeviceImpl::setDscEnable(bool enable)
         return false;
     }
 
-    if ((this->devDoingDscDecompression == this) && !this->isLogical() && this->parent != NULL && this->connector->bDscMstEnablePassThrough)
+    if ((this->devDoingDscDecompression == this) && !this->isLogical() && this->parent != NULL)
     {
         //
         // If the device has a parent, that means the sink is on a MST link and
@@ -1948,20 +1953,18 @@ bool DeviceImpl::setDscEnable(bool enable)
         //
         bDscPassThrough = true;
     }
-    else
+
+    //
+    // Get Current DSC Enable State
+    // Ideally we don't need to check the current state but Synaptics DSC device,
+    // which was used for inital DSC code developement did not follow spec and so
+    // we have added this code. Overwriting the same value should not have any 
+    // impact as per the spec. Will remove this check once all DSC devices follow spec.
+    //
+    if (!getDscEnable(&bCurrDscEnable))
     {
-        //
-        // Get Current DSC Enable State
-        // Ideally we don't need to check the current state but Synaptics DSC device,
-        // which was used for inital DSC code developement did not follow spec and so
-        // we have added this code. Overwriting the same value should not have any 
-        // impact as per the spec. Will remove this check once all DSC devices follow spec.
-        //
-        if (!getDscEnable(&bCurrDscEnable))
-        {
-            DP_LOG(("DP-DEV> Not able to get DSC Enable State!"));
-            return false;
-        }
+        DP_LOG(("DP-DEV> Not able to get DSC Enable State!"));
+        return false;
     }
 
     if(enable)
@@ -1970,7 +1973,7 @@ bool DeviceImpl::setDscEnable(bool enable)
         {
             dscPassthroughByte = FLD_SET_DRF(_DPCD20, _DSC_PASS_THROUGH, _ENABLE, _YES, dscPassthroughByte);
             DP_LOG(("DP-DEV> Enabling DSC Pass through on branch device - %s",
-                    this->parent->getTopologyAddress().toString(buffer)));          
+                    this->parent->getTopologyAddress().toString(buffer)));
         }
 
         if (!bCurrDscEnable)
@@ -1983,7 +1986,6 @@ bool DeviceImpl::setDscEnable(bool enable)
         {
             DP_LOG(("DP-DEV> DSC decompression is already enabled on device - %s", 
                     this->devDoingDscDecompression->getTopologyAddress().toString(buffer)));
-            return true;
         }
     }
     else
@@ -2005,22 +2007,40 @@ bool DeviceImpl::setDscEnable(bool enable)
         {
             DP_LOG(("DP-DEV> DSC decompression is already disabled on device - %s", 
                     this->devDoingDscDecompression->getTopologyAddress().toString(buffer)));
-            return true;
         }
     }
 
     if (bDscPassThrough)
     {
-        if(this->parent->setDpcdData(NV_DPCD20_DSC_PASS_THROUGH,
-            &dscPassthroughByte, sizeof dscPassthroughByte, &size, &nakReason))
+        dscPassThroughStatus = this->parent->setDpcdData(NV_DPCD20_DSC_PASS_THROUGH, 
+                                   &dscPassthroughByte, sizeof dscPassthroughByte, &size, &nakReason);
+        if (dscPassThroughStatus != AuxBus::success)
         {
-            DP_LOG(("DP-DEV> Setting DSC Passthrough state on parent branch failed"));
-            bDscPassThroughUpdated = false;
+            DP_LOG(("DP-DEV> Setting DSC Passthrough on parent branch %s failed", 
+                    this->parent->getTopologyAddress().toString(buffer)));
         }
     }
 
-    return (!this->devDoingDscDecompression->setDpcdData(NV_DPCD14_DSC_ENABLE,
-        &dscEnableByte, sizeof dscEnableByte, &size, &nakReason)) && bDscPassThroughUpdated;
+    if (enable != bCurrDscEnable)
+    {
+        dscEnableStatus = this->devDoingDscDecompression->setDpcdData(NV_DPCD14_DSC_ENABLE,
+                              &dscEnableByte, sizeof dscEnableByte, &size, &nakReason);
+        if (dscEnableStatus != AuxBus::success)
+        {
+            DP_LOG(("DP-DEV> Setting DSC Enable on sink %s failed", 
+                    this->devDoingDscDecompression->getTopologyAddress().toString(buffer)));
+ 
+        }
+    }
+
+    if ((dscPassThroughStatus != AuxBus::success) || (dscEnableStatus != AuxBus::success))
+    {
+        return false;
+    }
+    else
+    {
+        return true;
+    }
 }
 
 unsigned DeviceImpl::getDscVersionMajor()
@@ -2236,6 +2256,124 @@ bool DeviceImpl::getPCONCaps(PCONCaps *pPCONCaps)
     return true;
 }
 
+bool DeviceImpl::getIgnoreMSACap()
+{
+    NvU8 byte = 0;
+    unsigned size = 0;
+    unsigned nakReason = NakUndefined;
+    AuxBus::status status;
+
+    if (bIgnoreMsaCapCached)
+    {
+        return bIgnoreMsaCap;
+    }
+
+    if (this->isMultistream())
+    {
+        status = this->getDpcdData(NV_DPCD_DOWN_STREAM_PORT,
+                                   &byte, sizeof byte, &size, &nakReason);
+        if (status == AuxBus::success)
+        {
+            if(FLD_TEST_DRF(_DPCD, _DOWN_STREAM_PORT, _MSA_TIMING_PAR_IGNORED, _YES, byte))
+            {
+                if (this->parent && this->parent->isVirtualPeerDevice())
+                {
+                    byte = 0;
+                    size = 0;
+                    nakReason = NakUndefined;
+
+                    status = this->parent->getDpcdData(NV_DPCD_DOWN_STREAM_PORT,
+                                                       &byte, sizeof byte, &size, &nakReason);
+                    if (status == AuxBus::success)
+                    {
+                        if(FLD_TEST_DRF(_DPCD, _DOWN_STREAM_PORT, _MSA_TIMING_PAR_IGNORED, _YES, byte))
+                        {
+                            bIgnoreMsaCap = true;
+                        }
+                        else
+                        {
+                            bIgnoreMsaCap = false;
+                        }
+                        bIgnoreMsaCapCached = true;
+                    }
+                    else
+                    {
+                        DP_LOG(("DP-DEV> Aux Read from DPCD offset 0x7 failed!"));
+                        return false;
+                    }
+                }
+                else
+                {
+                    bIgnoreMsaCap = true;
+                    bIgnoreMsaCapCached = true;
+                }
+            }
+            else
+            {
+                bIgnoreMsaCap = false;
+                bIgnoreMsaCapCached = true;
+            }
+        }
+        else
+        {
+            DP_LOG(("DP-DEV> Aux Read from DPCD offset 0x7 failed!"));
+            return false;
+        }
+    }
+    else
+    {
+        bIgnoreMsaCap = hal->getMsaTimingparIgnored();
+        bIgnoreMsaCapCached = true;
+    }
+
+    return bIgnoreMsaCap;
+}
+
+AuxRetry::status  DeviceImpl::setIgnoreMSAEnable(bool msaTimingParamIgnoreEn)
+{
+    NvU8 byte = 0;
+    unsigned size = 0;
+    unsigned nakReason = NakUndefined;
+    AuxBus::status status;
+
+    if (this->isMultistream())
+    {
+        status = this->getDpcdData(NV_DPCD_DOWNSPREAD_CTRL,
+                                   &byte, sizeof byte, &size, &nakReason);
+        if (status == AuxBus::success)
+        {
+            if (msaTimingParamIgnoreEn)
+            {
+                byte = FLD_SET_DRF(_DPCD, _DOWNSPREAD_CTRL, _MSA_TIMING_PAR_IGNORED, _TRUE, byte);
+            }
+            else
+            {
+                byte = FLD_SET_DRF(_DPCD, _DOWNSPREAD_CTRL, _MSA_TIMING_PAR_IGNORED, _FALSE, byte);
+            }
+
+            status = this->setDpcdData(NV_DPCD_DOWNSPREAD_CTRL,
+                                       &byte, sizeof byte, &size, &nakReason);
+            if (status == AuxBus::success)
+            {
+                return AuxRetry::ack;
+            }
+            else
+            {
+                DP_LOG(("DP-DEV> Aux Write to DPCD offset 0x107 failed!"));
+                return AuxRetry::nack;
+            }
+        }
+        else
+        {
+            DP_LOG(("DP-DEV> Aux Read from DPCD offset 0x7 failed!"));
+            return AuxRetry::nack;
+        }
+    }
+    else
+    {
+        return hal->setIgnoreMSATimingParamters(msaTimingParamIgnoreEn);
+    }
+}
 
 void
 DeviceHDCPDetection::start()

src/common/displayport/src/dp_evoadapter.cpp

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -94,8 +94,6 @@ const struct
     {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST,          &dpRegkeyDatabase.bOptLinkKeptAliveSst,            DP_REG_VAL_BOOL},
     {NV_DP_REGKEY_FORCE_EDP_ILR,                    &dpRegkeyDatabase.bBypassEDPRevCheck,              DP_REG_VAL_BOOL},
     {NV_DP_DSC_MST_CAP_BUG_3143315,                 &dpRegkeyDatabase.bDscMstCapBug3143315,            DP_REG_VAL_BOOL},
-    {NV_DP_DSC_MST_ENABLE_PASS_THROUGH,             &dpRegkeyDatabase.bDscMstEnablePassThrough,        DP_REG_VAL_BOOL},
-    {NV_DP_DSC_OPTIMIZE_LT_BUG_3534707,             &dpRegkeyDatabase.bDscOptimizeLTBug3534707,        DP_REG_VAL_BOOL},
     {NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING,  &dpRegkeyDatabase.bNoReplyTimerForBusyWaiting,     DP_REG_VAL_BOOL},
     {NV_DP_REGKEY_DPCD_PROBING_FOR_BUSY_WAITING,    &dpRegkeyDatabase.bDpcdProbingForBusyWaiting,      DP_REG_VAL_BOOL}
 };
@@ -1048,6 +1046,7 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
             case EDP_3_24GHZ:
             case EDP_4_32GHZ:
             case HBR2:
+            case EDP_6_75GHZ:
             case HBR3:
                 linkBw = linkrate / DP_LINK_BW_FREQ_MULTI_MBPS;
                 dpCtrlData = FLD_SET_DRF_NUM(0073_CTRL, _DP_DATA, _SET_LINK_BW,
@@ -1797,6 +1796,7 @@ bool EvoMainLink::configureLinkRateTable
                 case linkBW_3_24Gbps:
                 case linkBW_4_32Gbps:
                 case linkBW_5_40Gbps:
+                case linkBW_6_75Gbps:
                 case linkBW_8_10Gbps:
                     pLinkRates->import(params.linkBwTbl[i]);
                     break;

src/common/displayport/src/dp_groupimpl.cpp

@@ -177,12 +177,59 @@ void GroupImpl::remove(Device * dev)
 
 void GroupImpl::destroy()
 {
+    ConnectorImpl* parent = NULL;
     for (Device * i = enumDevices(0); i; i = enumDevices(i))
         remove(i);
 
     // Cancel any queue the auth callback.
     cancelHdcpCallbacks();
 
+    parent = this->parent;
+
+    if (parent)
+    {
+        if (!parent->activeGroups.isEmpty())
+        {
+            for (ListElement * i = parent->activeGroups.begin(); i != parent->activeGroups.end(); i = i->next)
+            {
+                GroupImpl * group = (GroupImpl *)i;
+                if (group == this)
+                {
+                    parent->activeGroups.remove(this);
+                    DP_LOG(("DP-GRP> Deleted group 0x%x from active group!", this));
+                    break;
+                }
+            }
+        }
+
+
+        if (!parent->inactiveGroups.isEmpty())
+        {
+            for (ListElement * i = parent->inactiveGroups.begin(); i != parent->inactiveGroups.end(); i = i->next)
+            {
+                GroupImpl * group = (GroupImpl *)i;
+                if (group == this)
+                {
+                    parent->inactiveGroups.remove(this);
+                    DP_LOG(("DP-GRP> Deleted group 0x%x from inactive group!", this));
+                    break;
+                }
+            }
+        }
+
+        if (parent->intransitionGroups.contains(this))
+        {
+            parent->intransitionGroups.remove(this);
+            DP_LOG(("DP-GRP> Deleted group 0x%x from intransition group!", this));
+        }
+
+        if (parent->addStreamMSTIntransitionGroups.contains(this))
+        {
+            parent->addStreamMSTIntransitionGroups.remove(this);
+            DP_LOG(("DP-GRP> Deleted group 0x%x from addStreamMSTIntransitionGroups group!", this));
+        }
+    }
+
     delete this;
 }
 

src/common/displayport/src/dp_messages.cpp

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a

src/common/displayport/src/dp_sst_edid.cpp

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2010-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -240,10 +240,13 @@ bool DisplayPort::EdidReadSST(Edid & edid, AuxBus * auxBus, Timer* timer,
     Edid previousEdid;
     Buffer *buffer;
     bool status;
-
+    bool firstTrial = true;
+    NvU64 startTime, elapsedTime;
     for (unsigned i = 0; i < ddcAddrListSize; i++)
     {
-        for (unsigned j = 0; j < EDID_READ_MAX_RETRY_COUNT; j++)
+        startTime = timer->getTimeUs();
+        elapsedTime = 0;
+        do
         {
             //
             // Client asks to use RM control code to fetch EDID.
@@ -312,9 +315,10 @@ bool DisplayPort::EdidReadSST(Edid & edid, AuxBus * auxBus, Timer* timer,
                 }
                 else
                 {
-                    if (j == 0) // first failure?
+                    if (firstTrial) // first failure?
                     {
                         previousEdid.swap(edid);
+                        firstTrial = false;
                     }
                     else
                     {
@@ -327,7 +331,9 @@ bool DisplayPort::EdidReadSST(Edid & edid, AuxBus * auxBus, Timer* timer,
                     }
                 }
             }
-        }
+            elapsedTime = timer->getTimeUs() - startTime;
+            timer->sleep(1);
+        } while (elapsedTime < (EDID_READ_RETRY_TIMEOUT_MS * 1000));
     }
 
     DP_LOG(("EDID> Failed to ping sst DDC addresses"));

src/common/inc/displayport/displayport.h

@@ -104,6 +104,7 @@ typedef enum
     linkBW_3_24Gbps                = 0x0C,
     linkBW_4_32Gbps                = 0x10,
     linkBW_5_40Gbps                = 0x14,
+    linkBW_6_75Gbps                = 0x19,
     linkBW_8_10Gbps                = 0x1E,
     linkBW_Supported
 } DP_LINK_BANDWIDTH;
@@ -118,6 +119,7 @@ typedef enum
     linkSpeedId_2_43Gbps                = 0x05,
     linkSpeedId_3_24Gbps                = 0x06,
     linkSpeedId_4_32Gbps                = 0x07,
+    linkSpeedId_6_75Gbps                = 0x08,
     linkSpeedId_Supported
 } DP_LINK_SPEED_INDEX;
 
@@ -535,7 +537,8 @@ typedef struct PanelReplayConfig
 #define IS_INTERMEDIATE_LINKBW(val) (((NvU32)(val)==linkBW_2_16Gbps) || \
                                      ((NvU32)(val)==linkBW_2_43Gbps) || \
                                      ((NvU32)(val)==linkBW_3_24Gbps) || \
-                                     ((NvU32)(val)==linkBW_4_32Gbps))
+                                     ((NvU32)(val)==linkBW_4_32Gbps) || \
+                                     ((NvU32)(val)==linkBW_6_75Gbps))
 
 #define IS_VALID_LINKBW(val) (IS_STANDARD_LINKBW(val) || \
                               IS_INTERMEDIATE_LINKBW(val))

src/common/inc/displayport/dpcd.h

@@ -1364,12 +1364,10 @@ number of Downstream ports will be limited to 32.
 #define NV_DPCD_SINK_STATUS_ESI_RECEIVE_PORT_1_STATUS_IN_SYNC_YES       (0x00000001) /* R-XUV */
 
 // 0x00002010-0x0002025: RESERVED. Read all 0s
-
 #define NV_DPCD_OVERDRIVE_STATUS                                        (0x00002026) /* R-XUR */
 #define NV_DPCD_OVERDRIVE_STATUS_OVERDRIVE_ENGINE_STATUS                        0:0  /* R-XUF */
 #define NV_DPCD_OVERDRIVE_STATUS_OVERDRIVE_ENGINE_STATUS_NOT_ACTIVE     (0x00000000) /* R-XUV */
 #define NV_DPCD_OVERDRIVE_STATUS_OVERDRIVE_ENGINE_STATUS_ACTIVE         (0x00000001) /* R-XUV */
-
 // 0x00002027-0x00067FF: RESERVED. Read all 0s
 
 #define NV_DPCD_HDCP_BKSV_OFFSET                                 (0x00068000) /* R-XUR */

src/common/inc/displayport/dpcd20.h

@@ -47,7 +47,7 @@
 #define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO                    (0x00000000)
 #define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES                   (0x00000001)
 
-/// BRANCH SPECIFIC DSC CAPS
+// BRANCH SPECIFIC DSC CAPS
 #define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0                            (0x000000A0)
 #define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE                              7:0
 
@@ -55,5 +55,4 @@
 #define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1_VALUE                              7:0
 
 #define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH                            (0x000000A2)
-#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE                              7:0
-
+#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE                              7:0

src/common/inc/nvBldVer.h

@@ -36,26 +36,26 @@
 // and then checked back in. You cannot make changes to these sections without
 // corresponding changes to the buildmeister script
 #ifndef NV_BUILD_BRANCH
-    #define NV_BUILD_BRANCH             r515_00
+    #define NV_BUILD_BRANCH             r521_82
 #endif
 #ifndef NV_PUBLIC_BRANCH
-    #define NV_PUBLIC_BRANCH             r515_00
+    #define NV_PUBLIC_BRANCH             r521_82
 #endif
 
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
-#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r515/r515_00-409"
-#define NV_BUILD_CHANGELIST_NUM         (31799928)
+#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r520/r521_82-338"
+#define NV_BUILD_CHANGELIST_NUM         (31864828)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "rel/gpu_drv/r515/r515_00-409"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31799928)
+#define NV_BUILD_NAME                   "rel/gpu_drv/r520/r521_82-338"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31864828)
 
 #else     /* Windows builds */
-#define NV_BUILD_BRANCH_VERSION         "r515_00-323"
-#define NV_BUILD_CHANGELIST_NUM         (31799928)
+#define NV_BUILD_BRANCH_VERSION         "r521_82-4"
+#define NV_BUILD_CHANGELIST_NUM         (31858738)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "517.40"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31799928)
-#define NV_BUILD_BRANCH_BASE_VERSION    R515
+#define NV_BUILD_NAME                   "522.06"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31858738)
+#define NV_BUILD_BRANCH_BASE_VERSION    R520
 #endif
 // End buildmeister python edited section
 

src/common/inc/nvUnixVersion.h

@@ -4,7 +4,7 @@
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
     (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
 
-#define NV_VERSION_STRING               "515.76"
+#define NV_VERSION_STRING               "520.61.05"
 
 #else
 

src/common/inc/swref/published/ampere/ga100/dev_falcon_v4.h

@@ -28,15 +28,11 @@
 #define NV_PFALCON_FALCON_IRQSCLR_HALT_SET                                                             0x00000001     /* -W--V */
 #define NV_PFALCON_FALCON_IRQSCLR_SWGEN0                                                               6:6            /* -WXVF */
 #define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET                                                           0x00000001     /* -W--V */
-#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1                                                               7:7            /* -WXVF */
-#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET                                                           0x00000001     /* -W--V */
 #define NV_PFALCON_FALCON_IRQSTAT                                                                      0x00000008     /* R--4R */
 #define NV_PFALCON_FALCON_IRQSTAT_HALT                                                                 4:4            /* R-IVF */
 #define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE                                                            0x00000001     /* R---V */
 #define NV_PFALCON_FALCON_IRQSTAT_SWGEN0                                                               6:6            /* R-IVF */
 #define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE                                                          0x00000001     /* R---V */
-#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1                                                               7:7            /* R-IVF */
-#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE                                                          0x00000001     /* R---V */
 #define NV_PFALCON_FALCON_IRQMSET                                                                      0x00000010     /* -W-4R */
 #define NV_PFALCON_FALCON_IRQMCLR                                                                      0x00000014     /* -W-4R */
 #define NV_PFALCON_FALCON_IRQMASK                                                                      0x00000018     /* R--4R */

src/common/inc/swref/published/ampere/ga102/dev_falcon_v4.h

@@ -28,15 +28,11 @@
 #define NV_PFALCON_FALCON_IRQSCLR_HALT_SET                                                             0x00000001     /* -W--V */
 #define NV_PFALCON_FALCON_IRQSCLR_SWGEN0                                                               6:6            /* -WXVF */
 #define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET                                                           0x00000001     /* -W--V */
-#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1                                                               7:7            /* -WXVF */
-#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET                                                           0x00000001     /* -W--V */
 #define NV_PFALCON_FALCON_IRQSTAT                                                                      0x00000008     /* R--4R */
 #define NV_PFALCON_FALCON_IRQSTAT_HALT                                                                 4:4            /* R-IVF */
 #define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE                                                            0x00000001     /* R---V */
 #define NV_PFALCON_FALCON_IRQSTAT_SWGEN0                                                               6:6            /* R-IVF */
 #define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE                                                          0x00000001     /* R---V */
-#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1                                                               7:7            /* R-IVF */
-#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE                                                          0x00000001     /* R---V */
 #define NV_PFALCON_FALCON_INTR_RETRIGGER(i)                                                            (0x000003e8+(i)*4) /* -W-4A */
 #define NV_PFALCON_FALCON_INTR_RETRIGGER__SIZE_1                                                       2              /*       */
 #define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER                                                       0:0            /* -W-VF */

src/common/inc/swref/published/disp/v04_00/dev_disp.h

@@ -29,6 +29,10 @@
 #define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_NOT_PENDING                                0x00000000 /* R---V */
 #define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_PENDING                                    0x00000001 /* R---V */
 #define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_RESET                                      0x00000001 /* -W--V */
+#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING(i)                                       (0x00611C00+(i)*4) /* R--4A */
+#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_LAST_DATA                                               1:1 /* R-IVF */
+#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_LAST_DATA_NOT_PENDING                            0x00000000 /* R-I-V */
+#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_LAST_DATA_PENDING                                0x00000001 /* R---V */
 #define NV_PDISP_FE_RM_INTR_DISPATCH                                                          0x00611EC0 /* R--4R */
 #define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING(i)                                      (0+(i)):(0+(i)) /* R--VF */
 #define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_NOT_PENDING                                  0x00000000 /* R---V */

src/common/inc/swref/published/hopper/gh100/dev_ce.h

@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __gh100_dev_ce_h__
+#define __gh100_dev_ce_h__
+#define NV_CE_PCE2LCE_CONFIG__SIZE_1          16
+#define NV_CE_GRCE_CONFIG_SHARED              30:30 /* RWIVF */
+#define NV_CE_GRCE_CONFIG_SHARED_LCE          3:0 /* RWIVF */
+#define NV_CE_GRCE_CONFIG_SHARED_LCE_NONE     0xf /* RW--V */
+#endif // __gh100_dev_ce_h__

src/common/inc/swref/published/hopper/gh100/dev_falcon_v4.h

@@ -0,0 +1,100 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_falcon_v4_h__
+#define __gh100_dev_falcon_v4_h__
+
+#define NV_PFALCON_FALCON_MAILBOX0                                                                     0x00000040     /* RW-4R */
+#define NV_PFALCON_FALCON_MAILBOX0_DATA                                                                31:0           /* RWIVF */
+#define NV_PFALCON_FALCON_MAILBOX0_DATA_INIT                                                           0x00000000     /* RWI-V */
+#define NV_PFALCON_FALCON_MAILBOX1                                                                     0x00000044     /* RW-4R */
+#define NV_PFALCON_FALCON_MAILBOX1_DATA                                                                31:0           /* RWIVF */
+#define NV_PFALCON_FALCON_MAILBOX1_DATA_INIT                                                           0x00000000     /* RWI-V */
+
+#define NV_PFALCON_FALCON_OS                                                                           0x00000080     /* RW-4R */
+#define NV_PFALCON_FALCON_OS__DEVICE_MAP                                                               0x00000013 /*       */
+#define NV_PFALCON_FALCON_OS_VERSION                                                                   31:0           /* RWIVF */
+#define NV_PFALCON_FALCON_OS_VERSION_INIT                                                              0x00000000     /* RWI-V */
+
+#define NV_PFALCON_FALCON_HWCFG2                                                                       0x000000f4     /* R--4R */
+#define NV_PFALCON_FALCON_HWCFG2_SHA                                                                   0:0            /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_SHA_ENABLE                                                            0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_SHA_DISABLE                                                           0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_BMEM                                                                  1:1            /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_BMEM_ENABLE                                                           0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_BMEM_DISABLE                                                          0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_PKCBOOT                                                               2:2            /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_PKCBOOT_ENABLE                                                        0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_PKCBOOT_DISABLE                                                       0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_DBGMODE                                                               3:3            /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_DBGMODE_ENABLE                                                        0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_DBGMODE_DISABLE                                                       0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_KMEM                                                                  4:4            /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_KMEM_ENABLE                                                           0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_KMEM_DISABLE                                                          0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_HSCODE_REVOCATION                                                     5:5            /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE                                              0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE                                             0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_STRAP_FUN                                                             6:6            /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_STRAP_FUN_ENABLE                                                      0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_STRAP_FUN_DISABLE                                                     0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_VHR                                                                   7:7            /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_VHR_ENABLE                                                            0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_VHR_DISABLE                                                           0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_HS                                                                    8:8            /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_HS_ENABLE                                                             0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_HS_DISABLE                                                            0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_SECUREBUS                                                             9:9            /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_SECUREBUS_ENABLE                                                      0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_SECUREBUS_DISABLE                                                     0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_RISCV                                                                 10:10          /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_RISCV_ENABLE                                                          0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_RISCV_DISABLE                                                         0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE                                                     11:11          /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE                                                0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE                                               0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING                                                         12:12          /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING_PENDING                                                 0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING_DONE                                                    0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN                                                13:13          /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK                                           0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK                                         0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_BOOT_FROM_HS                                                          14:14          /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_BOOT_FROM_HS_TRUE                                                     0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_BOOT_FROM_HS_FALSE                                                    0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_ADPAIR                                                       15:15          /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_ADPAIR_ENABLE                                                0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_ADPAIR_DISABLE                                               0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_SCP                                                                   16:16          /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_SCP_ENABLE                                                            0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_SCP_DISABLE                                                           0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_GDMA                                                                  17:17          /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_GDMA_ENABLE                                                           0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_GDMA_DISABLE                                                          0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_SE_LITE                                                               18:18          /* R--VF */
+#define NV_PFALCON_FALCON_HWCFG2_SE_LITE_ENABLE                                                        0x00000001     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_SE_LITE_DISABLE                                                       0x00000000     /* R---V */
+#define NV_PFALCON_FALCON_HWCFG2_PRGN_RSVD_FUSE                                                        31:24          /* R-IVF */
+#define NV_PFALCON_FALCON_HWCFG2_PRGN_RSVD_FUSE_DEFAULT                                                0x00000000     /* R-I-V */
+
+#endif // __gh100_dev_falcon_v4_h__

src/common/inc/swref/published/hopper/gh100/dev_fault.h

@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_fault_h__
+#define __gh100_dev_fault_h__
+
+#define NV_PFAULT_MMU_ENG_ID_GRAPHICS           384 /*       */
+
+#endif // __gh100_dev_fault_h__

src/common/inc/swref/published/hopper/gh100/dev_fb.h

@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+ 
+#ifndef __gh100_dev_fb_h
+#define __gh100_dev_fb_h_
+#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT                       8 /*       */
+#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO           0x00100A34 /* RW-4R */
+#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR             31:0 /* RWIVF */
+#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI           0x00100A38 /* RW-4R */
+#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR             31:0 /* RWIVF */
+#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK  0x000FFFFF /* ----V */
+#endif // __gh100_dev_fb_h__

src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h

@@ -0,0 +1,78 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_fsp_addendum_h__
+#define __gh100_dev_fsp_addendum_h__
+
+//
+// RM uses channel 0 for FSP EMEM on GH100.
+//
+#define FSP_EMEM_CHANNEL_RM             0x0
+
+//
+// PMU/SOE use channel 4 for FSP EMEM on GH100.
+//
+#define FSP_EMEM_CHANNEL_PMU_SOE        0x4
+#define FSP_EMEM_CHANNEL_MAX            0x8
+
+// EMEM channel 0 (RM) is allocated 1K bytes.
+#define FSP_EMEM_CHANNEL_RM_SIZE        1024
+
+// EMEM channel 4 (PMU/SOE) is allocated 1K bytes.
+#define FSP_EMEM_CHANNEL_PMU_SOE_SIZE   1024
+#define FSP_EMEM_CHANNEL_PMU_SOE_OFFSET 4096
+
+//
+// MCTP (Management Component Transport Protocol) overlayed on NVDM (NVIDIA Data
+// Model) is the mechanism used between FSP management partition and CPU-RM.
+//
+
+#define MCTP_HEADER_RSVD             7:4
+#define MCTP_HEADER_VERSION          3:0
+
+#define MCTP_HEADER_DEID            15:8
+
+#define MCTP_HEADER_SEID            23:16
+
+#define MCTP_HEADER_SOM             31:31
+#define MCTP_HEADER_EOM             30:30
+#define MCTP_HEADER_SEQ             29:28
+#define MCTP_HEADER_TO              27:27
+#define MCTP_HEADER_TAG             26:24
+
+#define MCTP_MSG_HEADER_IC           7:7
+#define MCTP_MSG_HEADER_TYPE         6:0
+#define MCTP_MSG_HEADER_VENDOR_ID    23:8
+#define MCTP_MSG_HEADER_NVDM_TYPE    31:24
+
+#define MCTP_MSG_HEADER_TYPE_VENDOR_PCI 0x7e
+#define MCTP_MSG_HEADER_VENDOR_ID_NV    0x10de
+
+#define NVDM_TYPE_HULK                  0x11
+#define NVDM_TYPE_FIRMWARE_UPDATE       0x12
+#define NVDM_TYPE_COT                   0x14
+#define NVDM_TYPE_FSP_RESPONSE          0x15
+#define NVDM_TYPE_INFOROM               0x17
+#define NVDM_TYPE_SMBPBI                0x18
+
+#endif // __gh100_dev_fsp_addendum_h__

src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h

@@ -0,0 +1,68 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __gh100_dev_fsp_pri_h__
+#define __gh100_dev_fsp_pri_h__
+
+#define NV_PFSP_EMEMC(i)                                                                                 (0x008F2ac0+(i)*8) /* RW-4A */
+#define NV_PFSP_EMEMC__SIZE_1                                                                            8              /*       */
+#define NV_PFSP_EMEMC_OFFS                                                                               7:2            /* RWIVF */
+#define NV_PFSP_EMEMC_OFFS_INIT                                                                          0x00000000     /* RWI-V */
+#define NV_PFSP_EMEMC_BLK                                                                                15:8           /* RWIVF */
+#define NV_PFSP_EMEMC_BLK_INIT                                                                           0x00000000     /* RWI-V */
+#define NV_PFSP_EMEMC_AINCW                                                                              24:24          /* RWIVF */
+#define NV_PFSP_EMEMC_AINCW_INIT                                                                         0x00000000     /* RWI-V */
+#define NV_PFSP_EMEMC_AINCW_TRUE                                                                         0x00000001     /* RW--V */
+#define NV_PFSP_EMEMC_AINCW_FALSE                                                                        0x00000000     /* RW--V */
+#define NV_PFSP_EMEMC_AINCR                                                                              25:25          /* RWIVF */
+#define NV_PFSP_EMEMC_AINCR_INIT                                                                         0x00000000     /* RWI-V */
+#define NV_PFSP_EMEMC_AINCR_TRUE                                                                         0x00000001     /* RW--V */
+#define NV_PFSP_EMEMC_AINCR_FALSE                                                                        0x00000000     /* RW--V */
+#define NV_PFSP_EMEMD(i)                                                                                 (0x008F2ac4+(i)*8) /* RW-4A */
+#define NV_PFSP_EMEMD__SIZE_1                                                                            8              /*       */
+#define NV_PFSP_EMEMD_DATA                                                                               31:0           /* RWXVF */
+
+#define NV_PFSP_MSGQ_HEAD(i)                                                                             (0x008F2c80+(i)*8) /* RW-4A */
+#define NV_PFSP_MSGQ_HEAD__SIZE_1                                                                        8              /*       */
+#define NV_PFSP_MSGQ_HEAD_VAL                                                                            31:0           /* RWIUF */
+#define NV_PFSP_MSGQ_HEAD_VAL_INIT                                                                       0x00000000     /* RWI-V */
+#define NV_PFSP_MSGQ_TAIL(i)                                                                             (0x008F2c84+(i)*8) /* RW-4A */
+#define NV_PFSP_MSGQ_TAIL__SIZE_1                                                                        8              /*       */
+#define NV_PFSP_MSGQ_TAIL_VAL                                                                            31:0           /* RWIUF */
+#define NV_PFSP_MSGQ_TAIL_VAL_INIT                                                                       0x00000000     /* RWI-V */
+
+#define NV_PFSP_QUEUE_HEAD(i)                                                                            (0x008F2c00+(i)*8) /* RW-4A */
+#define NV_PFSP_QUEUE_HEAD__SIZE_1                                                                       8              /*       */
+#define NV_PFSP_QUEUE_HEAD_ADDRESS                                                                       31:0           /* RWIVF */
+#define NV_PFSP_QUEUE_HEAD_ADDRESS_INIT                                                                  0x00000000     /* RWI-V */
+#define NV_PFSP_QUEUE_TAIL(i)                                                                            (0x008F2c04+(i)*8) /* RW-4A */
+#define NV_PFSP_QUEUE_TAIL__SIZE_1                                                                       8              /*       */
+#define NV_PFSP_QUEUE_TAIL_ADDRESS                                                                       31:0           /* RWIVF */
+#define NV_PFSP_QUEUE_TAIL_ADDRESS_INIT                                                                  0x00000000     /* RWI-V */
+
+#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(i)                                                         (0x008f0320+(i)*4) /* RW-4A */
+#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1                                                    4              /*       */
+#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP                                                0x00000016 /*       */
+#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL                                                        31:0           /* RWIVF */
+#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT                                                   0x00000000     /* RWI-V */
+
+#endif // __gh100_dev_fsp_pri_h__

src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h

@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_gc6_island_h__
+#define __gh100_dev_gc6_island_h__
+
+#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0                           0x00118df4 /* RW-4R */
+#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE                           0:0 /* RWEVF */
+#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE_DONE               0x00000000 /* R-E-V */
+#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE_TRIGGER            0x00000001 /* -W--T */
+#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_NSEC                            31:5 /* RWEUF */
+#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_NSEC_ZERO                 0x00000000 /* RWE-V */
+#define NV_PGC6_SCI_SYS_TIMER_OFFSET_1                           0x00118df8 /* RW-4R */
+#define NV_PGC6_SCI_SYS_TIMER_OFFSET_1_NSEC                            28:0 /* RWEUF */
+#define NV_PGC6_SCI_SYS_TIMER_OFFSET_1_NSEC_ZERO                 0x00000000 /* RWE-V */
+
+#endif // __gh100_dev_gc6_island_h__

src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h

@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_gc6_island_addendum_h__
+#define __gh100_dev_gc6_island_addendum_h__
+
+#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K                        0x100
+
+#endif // __gh100_dev_gc6_island_addendum_h__

src/common/inc/swref/published/hopper/gh100/dev_gsp.h

@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __gh100_dev_gsp_h__
+#define __gh100_dev_gsp_h__
+#define NV_PGSP_FALCON_ENGINE                                                                            0x1103c0     /* RW-4R */
+#define NV_PGSP_FALCON_ENGINE_RESET                                                                      0:0            /* RWEVF */
+#define NV_PGSP_FALCON_ENGINE_RESET_DEASSERT                                                             0              /*       */
+#define NV_PGSP_FALCON_ENGINE_RESET_ASSERT                                                               1              /*       */
+#define NV_PGSP_FALCON_ENGINE_RESET_STATUS                                                               10:8           /* R-EVF */
+#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_ASSERTED                                                      0x00000000     /* R-E-V */
+#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_DEASSERTED                                                    0x00000002     /* R---V */
+#define NV_PGSP_MAILBOX(i)                                                                               (0x110804+(i)*4) /* RW-4A */
+#endif // __gh100_dev_gsp_h__

src/common/inc/swref/published/hopper/gh100/dev_mmu.h

@@ -0,0 +1,194 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_mmu_h__
+#define __gh100_dev_mmu_h__
+
+
+#define NV_MMU_PTE                                                      /* ----G */
+#define NV_MMU_PTE_APERTURE                           (1*32+2):(1*32+1) /* RWXVF */
+#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY                     0x00000000 /* RW--V */
+#define NV_MMU_PTE_APERTURE_PEER_MEMORY                      0x00000001 /* RW--V */
+#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY           0x00000002 /* RW--V */
+#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY       0x00000003 /* RW--V */
+#define NV_MMU_PTE_KIND                              (1*32+7):(1*32+4) /* RWXVF */
+#define NV_MMU_PTE_KIND_INVALID                       0x07 /* R---V */
+#define NV_MMU_PTE_KIND_PITCH                         0x00 /* R---V */
+#define NV_MMU_PTE_KIND_GENERIC_MEMORY                                                  0x6 /* R---V */
+#define NV_MMU_PTE_KIND_Z16                                                             0x1 /* R---V */
+#define NV_MMU_PTE_KIND_S8                                                              0x2 /* R---V */
+#define NV_MMU_PTE_KIND_S8Z24                                                           0x3 /* R---V */
+#define NV_MMU_PTE_KIND_ZF32_X24S8                                                      0x4 /* R---V */
+#define NV_MMU_PTE_KIND_Z24S8                                                           0x5 /* R---V */
+#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE                                     0x8 /* R---V */
+#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC                         0x9 /* R---V */
+#define NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC                                     0xA /* R---V */
+#define NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC                                    0xB /* R---V */
+#define NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC                                  0xC /* R---V */
+#define NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC                             0xD /* R---V */
+#define NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC                                  0xE /* R---V */
+#define NV_MMU_PTE_KIND_SMSKED_MESSAGE                                                  0xF /* R---V */
+
+#define NV_MMU_VER3_PDE                                                      /* ----G */
+#define NV_MMU_VER3_PDE_IS_PTE                                           0:0 /* RWXVF */
+#define NV_MMU_VER3_PDE_IS_PTE_TRUE                                      0x1 /* RW--V */
+#define NV_MMU_VER3_PDE_IS_PTE_FALSE                                     0x0 /* RW--V */
+#define NV_MMU_VER3_PDE_VALID                                            0:0 /* RWXVF */
+#define NV_MMU_VER3_PDE_VALID_TRUE                                       0x1 /* RW--V */
+#define NV_MMU_VER3_PDE_VALID_FALSE                                      0x0 /* RW--V */
+#define NV_MMU_VER3_PDE_APERTURE                                         2:1 /* RWXVF */
+#define NV_MMU_VER3_PDE_APERTURE_INVALID                          0x00000000 /* RW--V */
+#define NV_MMU_VER3_PDE_APERTURE_VIDEO_MEMORY                     0x00000001 /* RW--V */
+#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_COHERENT_MEMORY           0x00000002 /* RW--V */
+#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY       0x00000003 /* RW--V */
+#define NV_MMU_VER3_PDE_PCF                                                                        5:3 /* RWXVF */
+#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED               0x00000000 /* RW--V */
+#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED                                        0x00000000 /* RW--V */
+#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_ALLOWED                                             0x00000000 /* RW--V */
+#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED              0x00000001 /* RW--V */
+#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED                                      0x00000001 /* RW--V */
+#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_ALLOWED                                              0x00000001 /* RW--V */
+#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED       0x00000002 /* RW--V */
+#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED                                    0x00000002 /* RW--V */
+#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_NOT_ALLOWED                                         0x00000002 /* RW--V */
+#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED      0x00000003 /* RW--V */
+#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED                                  0x00000003 /* RW--V */
+#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_NOT_ALLOWED                                          0x00000003 /* RW--V */
+#define NV_MMU_VER3_PDE_ADDRESS                                             51:12 /* RWXVF */
+#define NV_MMU_VER3_PDE_ADDRESS_SHIFT                                  0x0000000c /*       */
+#define NV_MMU_VER3_PDE__SIZE                                              8
+
+#define NV_MMU_VER3_DUAL_PDE                                                      /* ----G */
+#define NV_MMU_VER3_DUAL_PDE_IS_PTE                                           0:0 /* RWXVF */
+#define NV_MMU_VER3_DUAL_PDE_IS_PTE_TRUE                                      0x1 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_IS_PTE_FALSE                                     0x0 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_VALID                                            0:0 /* RWXVF */
+#define NV_MMU_VER3_DUAL_PDE_VALID_TRUE                                       0x1 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_VALID_FALSE                                      0x0 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG                                     2:1 /* RWXVF */
+#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_INVALID                      0x00000000 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY                 0x00000001 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY       0x00000002 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY   0x00000003 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG                                                                        5:3 /* RWXVF */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED               0x00000000 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED                                        0x00000000 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_ALLOWED                                             0x00000000 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED              0x00000001 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED                                      0x00000001 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_ALLOWED                                              0x00000001 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED       0x00000002 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED                                    0x00000002 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_NOT_ALLOWED                                         0x00000002 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED      0x00000003 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED                                  0x00000003 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_NOT_ALLOWED                                          0x00000003 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG                                     51:8 /* RWXVF */
+#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL                                 66:65 /* RWXVF */
+#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_INVALID                    0x00000000 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY               0x00000001 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY     0x00000002 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL                                                                      69:67 /* RWXVF */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED               0x00000000 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED                                        0x00000000 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_ALLOWED                                             0x00000000 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED              0x00000001 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED                                      0x00000001 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_ALLOWED                                              0x00000001 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED       0x00000002 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED                                    0x00000002 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_NOT_ALLOWED                                         0x00000002 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED      0x00000003 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED                                  0x00000003 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_NOT_ALLOWED                                          0x00000003 /* RW--V */
+#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SMALL                                 115:76 /* RWXVF */
+#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SHIFT                             0x0000000c /*       */
+#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /*       */
+#define NV_MMU_VER3_DUAL_PDE__SIZE                                             16
+
+#define NV_MMU_VER3_PTE                                                      /* ----G */
+#define NV_MMU_VER3_PTE_VALID                                            0:0 /* RWXVF */
+#define NV_MMU_VER3_PTE_VALID_TRUE                                       0x1 /* RW--V */
+#define NV_MMU_VER3_PTE_VALID_FALSE                                      0x0 /* RW--V */
+#define NV_MMU_VER3_PTE_APERTURE                                         2:1 /* RWXVF */
+#define NV_MMU_VER3_PTE_APERTURE_VIDEO_MEMORY                     0x00000000 /* RW--V */
+#define NV_MMU_VER3_PTE_APERTURE_PEER_MEMORY                      0x00000001 /* RW--V */
+#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_COHERENT_MEMORY           0x00000002 /* RW--V */
+#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY       0x00000003 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF                                                                        7:3 /* RWXVF */
+#define NV_MMU_VER3_PTE_PCF_INVALID                                                         0x00000000 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_SPARSE                                                          0x00000001 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_MAPPING_NOWHERE                                                 0x00000002 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_NO_VALID_4KB_PAGE                                               0x00000003 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACE                                    0x00000000 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACE                                  0x00000001 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACE                                  0x00000002 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACE                                0x00000003 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACE                                    0x00000004 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACE                                   0x00000005 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACE                                  0x00000006 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACE                                0x00000007 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACE                                 0x00000008 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACE                               0x00000009 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACE                               0x0000000A /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACE                             0x0000000B /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACE                                 0x0000000C /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACE                               0x0000000D /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACE                               0x0000000E /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACE                             0x0000000F /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACD                                    0x00000010 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACD                                  0x00000011 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACD                                  0x00000012 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACD                                0x00000013 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACD                                    0x00000014 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACD                                  0x00000015 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACD                                  0x00000016 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACD                                0x00000017 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACD                                 0x00000018 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACD                               0x00000019 /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACD                               0x0000001A /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACD                             0x0000001B /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACD                                 0x0000001C /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACD                               0x0000001D /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACD                               0x0000001E /* RW--V */
+#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD                             0x0000001F /* RW--V */
+#define NV_MMU_VER3_PTE_KIND                                           11:8 /* RWXVF */
+#define NV_MMU_VER3_PTE_ADDRESS                                         51:12 /* RWXVF */
+#define NV_MMU_VER3_PTE_ADDRESS_SYS                                     51:12 /* RWXVF */
+#define NV_MMU_VER3_PTE_ADDRESS_PEER                                    51:12 /* RWXVF */
+#define NV_MMU_VER3_PTE_ADDRESS_VID                                     39:12 /* RWXVF */
+#define NV_MMU_VER3_PTE_PEER_ID                63:(64-3) /* RWXVF */
+#define NV_MMU_VER3_PTE_PEER_ID_0                                 0x00000000 /* RW--V */
+#define NV_MMU_VER3_PTE_PEER_ID_1                                 0x00000001 /* RW--V */
+#define NV_MMU_VER3_PTE_PEER_ID_2                                 0x00000002 /* RW--V */
+#define NV_MMU_VER3_PTE_PEER_ID_3                                 0x00000003 /* RW--V */
+#define NV_MMU_VER3_PTE_PEER_ID_4                                 0x00000004 /* RW--V */
+#define NV_MMU_VER3_PTE_PEER_ID_5                                 0x00000005 /* RW--V */
+#define NV_MMU_VER3_PTE_PEER_ID_6                                 0x00000006 /* RW--V */
+#define NV_MMU_VER3_PTE_PEER_ID_7                                 0x00000007 /* RW--V */
+#define NV_MMU_VER3_PTE_ADDRESS_SHIFT                             0x0000000c /*       */
+#define NV_MMU_VER3_PTE__SIZE                                              8
+
+
+#endif // __gh100_dev_mmu_h__

src/common/inc/swref/published/hopper/gh100/dev_nv_xal_addendum.h

@@ -0,0 +1,31 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_nv_xal_addendum_h__
+#define __gh100_dev_nv_xal_addendum_h__
+
+#define NV_XAL_EP_MEMOP_TOKEN_SIZE               31
+#define NV_XAL_EP_MEMOP_TOKEN_MAX_ISSUED         4
+#define NV_XAL_EP_MEMOP_MAX_OUTSTANDING          140
+
+#endif // __gh100_dev_nv_xal_addendum_h__

src/common/inc/swref/published/hopper/gh100/dev_pmc.h

@@ -0,0 +1,27 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_pmc_h__
+#define __gh100_dev_pmc_h__
+#define NV_PMC_BOOT_0                                    0x00000000 /* R--4R */
+#endif // __gh100_dev_pmc_h__

src/common/inc/swref/published/hopper/gh100/dev_ram.h

@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_ram_h__
+#define __gh100_dev_ram_h__
+#define NV_PRAMIN                             0x007FFFFF:0x00700000 /* RW--M */
+#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_LO      (31+0*32):(8+0*32) /* RWXUF */
+#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI_HW   (19+1*32):(0+1*32) /* RWXUF */
+#endif // __gh100_dev_ram_h__

src/common/inc/swref/published/hopper/gh100/dev_riscv_pri.h

@@ -0,0 +1,72 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __gh100_dev_riscv_pri_h__
+#define __gh100_dev_riscv_pri_h__
+
+#define NV_PRISCV_RISCV_BCR_DMACFG                                                                     0x0000066c     /* RW-4R */
+#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET                                                              1:0            /* RWIVF */
+#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET_LOCAL_FB                                                     0x00000000     /* RWI-V */
+#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET_COHERENT_SYSMEM                                              0x00000001     /* RW--V */
+#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET_NONCOHERENT_SYSMEM                                           0x00000002     /* RW--V */
+#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET_IO                                                           0x00000003     /* RW--V */
+#define NV_PRISCV_RISCV_BCR_DMACFG_POINTER_WALKING                                                     28:28          /* RWIVF */
+#define NV_PRISCV_RISCV_BCR_DMACFG_POINTER_WALKING_FALSE                                               0x00000000     /* RWI-V */
+#define NV_PRISCV_RISCV_BCR_DMACFG_POINTER_WALKING_TRUE                                                0x00000001     /* RW--V */
+#define NV_PRISCV_RISCV_BCR_DMACFG_LOCK                                                                31:31          /* RWIVF */
+#define NV_PRISCV_RISCV_BCR_DMACFG_LOCK_UNLOCKED                                                       0x00000000     /* RWI-V */
+#define NV_PRISCV_RISCV_BCR_DMACFG_LOCK_LOCKED                                                         0x00000001     /* RW--V */
+
+#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_LO                                                        0x00000670     /* RW-4R */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_LO_VAL                                                    31:0           /* RWIVF */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_LO_VAL_INIT                                               0x00000000     /* RWI-V */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_HI                                                        0x00000674     /* RW-4R */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_HI_VAL                                                    11:0           /* RWIVF */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_HI_VAL_INIT                                               0x00000000     /* RWI-V */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_LO                                                         0x00000678     /* RW-4R */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_LO_VAL                                                     31:0           /* RWIVF */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_LO_VAL_INIT                                                0x00000000     /* RWI-V */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_HI                                                         0x0000067c     /* RW-4R */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_HI_VAL                                                     11:0           /* RWIVF */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_HI_VAL_INIT                                                0x00000000     /* RWI-V */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_LO                                                         0x00000680     /* RW-4R */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_LO_VAL                                                     31:0           /* RWIVF */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_LO_VAL_INIT                                                0x00000000     /* RWI-V */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_HI                                                         0x00000684     /* RW-4R */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_HI_VAL                                                     11:0           /* RWIVF */
+#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_HI_VAL_INIT                                                0x00000000     /* RWI-V */
+
+#define NV_PRISCV_RISCV_CPUCTL                                                                         0x00000388     /* RW-4R */
+#define NV_PRISCV_RISCV_CPUCTL_STARTCPU                                                                0:0            /* -WIVF */
+#define NV_PRISCV_RISCV_CPUCTL_STARTCPU_FALSE                                                          0x00000000     /* -WI-V */
+#define NV_PRISCV_RISCV_CPUCTL_STARTCPU_TRUE                                                           0x00000001     /* -W--V */
+#define NV_PRISCV_RISCV_CPUCTL_HALTED                                                                  4:4            /* R-IVF */
+#define NV_PRISCV_RISCV_CPUCTL_HALTED_INIT                                                             0x00000001     /* R-I-V */
+#define NV_PRISCV_RISCV_CPUCTL_HALTED_TRUE                                                             0x00000001     /* R---V */
+#define NV_PRISCV_RISCV_CPUCTL_HALTED_FALSE                                                            0x00000000     /* R---V */
+#define NV_PRISCV_RISCV_CPUCTL_STOPPED                                                                 5:5            /* R-IVF */
+#define NV_PRISCV_RISCV_CPUCTL_STOPPED_INIT                                                            0x00000000     /* R-I-V */
+#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT                                                             7:7            /* R-IVF */
+#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT_INACTIVE                                                    0x00000000     /* R-I-V */
+#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE                                                      0x00000001     /* R---V */
+
+#endif // __gh100_dev_riscv_pri_h__

src/common/inc/swref/published/hopper/gh100/dev_therm.h

@@ -0,0 +1,30 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __gh100_dev_therm_h__
+#define __gh100_dev_therm_h__
+
+#define NV_THERM_I2CS_SCRATCH                                                  0x000200bc /* RW-4R */
+#define NV_THERM_I2CS_SCRATCH_DATA                                                   31:0 /* RWIVF */
+#define NV_THERM_I2CS_SCRATCH_DATA_INIT                                        0x00000000 /* RWI-V */
+
+#endif // __gh100_dev_therm_h__

src/common/inc/swref/published/hopper/gh100/dev_therm_addendum.h

@@ -0,0 +1,31 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __gh100_dev_therm_addendum_h__
+#define __gh100_dev_therm_addendum_h__
+
+#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE                                   NV_THERM_I2CS_SCRATCH
+#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS                                             31:0
+#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS                               0x000000FF
+#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_FAILED                                0x00000000
+
+#endif // __gh100_dev_therm_addendum_h__

src/common/inc/swref/published/hopper/gh100/dev_timer.h

@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_timer_h__
+#define __gh100_dev_timer_h__
+
+#define NV_PTIMER_TIME_PRIV_LEVEL_MASK                                            0x00009430 /* RW-4R */
+#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                           4:4 /*       */
+#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE             0x00000001
+#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE            0x00000000
+#define NV_PTIMER_TIME_0_NSEC                                                           31:5 /* R-XUF */
+
+#endif // __gh100_dev_timer_h__

src/common/inc/swref/published/hopper/gh100/dev_vm.h

@@ -0,0 +1,50 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_vm_h__
+#define __gh100_dev_vm_h__
+#define NV_VIRTUAL_FUNCTION_PRIV                       0x0002FFFF:0x00000000 /* RW--D */
+#define NV_VIRTUAL_FUNCTION                            0x0003FFFF:0x00030000 /* RW--D */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE                                    0x00000F10   /* R--4R */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_TOKEN                   (31-1):0   /* R-IUF */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED                           0x00000F14   /* R--4R */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_TOKEN         (31-1):0   /* R-IUF */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_STATUS                                   31:31   /* R-IUF */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_STATUS_BUSY                         0x00000001   /* R---V */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE                                   0x00000F18   /* R--4R */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_TOKEN                  (31-1):0   /* R-IUF */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED                         0x00000F1C   /* R--4R */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_TOKEN        (31-1):0   /* R-IUF */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_STATUS                                  31:31   /* R-IUF */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_STATUS_BUSY                        0x00000001   /* R---V */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR                                                0x00000F70   /* RW-4R */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE                                                  9:9   /* RWIUF */
+#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE_PHYSICAL                                  0x00000000   /* RWI-V */
+#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(i)                                                (i) /*       */
+#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1                                                   16 /*       */
+#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1                                            16  /*       */
+#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1                                          16 /*       */
+#define NV_VIRTUAL_FUNCTION_PRIV_TIMER(i)               (0x2300+(i)*4) /* RW-4A */
+#define NV_VIRTUAL_FUNCTION_PRIV_TIMER__SIZE_1                      2  /*        */
+
+#endif // __gh100_dev_vm_h__

src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h

@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_vm_addendum_h__
+#define __gh100_dev_vm_addendum_h__
+
+//
+// Compile time asserts in the source code files will ensure that
+// these don't end up exceeding the range of the top level registers.
+//
+
+// Subtrees at CPU_INTR top level for UVM owned interrupts
+#define NV_CPU_INTR_UVM_SUBTREE_START NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(1)
+#define NV_CPU_INTR_UVM_SUBTREE_LAST  NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(1)
+
+#define NV_CPU_INTR_UVM_SHARED_SUBTREE_START NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(2)
+#define NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(2)
+
+//
+// Subtrees at CPU_INTR top level for all stall interrupts from host-driven
+// engines
+//
+#define NV_CPU_INTR_STALL_SUBTREE_START NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(3)
+#define NV_CPU_INTR_STALL_SUBTREE_LAST_SWRL NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(4)
+#define NV_CPU_INTR_STALL_SUBTREE_LAST  NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(5)
+
+//
+// CPU doorbell can be anything on GH100+! Define them the same as
+// pre-GH100 for compatibility
+//
+#define NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT                           0x00000081
+
+#endif // __gh100_dev_vm_addendum_h__

src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h

@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_xtl_ep_pcfg_gpu_h__
+#define __gh100_dev_xtl_ep_pcfg_gpu_h__
+#define NV_EP_PCFG_GPU_ID                                                                                      0x00000000           /* R--4R */
+#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS                                                                     0x00000004           /* RW-4R */
+#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE                                                        0:0                  /* RWIVF */
+#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE_ENABLE                                                 0x00000001           /* RW--V */
+#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE                                                               0x00000008           /* R--4R */
+#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_PGM_INTERFACE                                                 15:8                 /* R-IVF */
+#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_SUB_CLASSCODE                                                 23:16                /* R-IVF */
+#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE                                                31:24                /* R-IVF */
+#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE_3D                                             0x00000003           /* R-I-V */
+#define NV_EP_PCFG_GPU_SUBSYSTEM_ID                                                                            0x0000002C           /* R--4R */
+#define NV_EP_PCFG_GPU_MSI_64_HEADER                                                                           0x00000048           /* RW-4R */
+#define NV_EP_PCFG_GPU_MSI_64_HEADER_MSI_ENABLE                                                                16:16                /* RWIVF */
+#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES                                                                     0x00000064           /* R--4R */
+#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED                                        5:5                  /* R-IVF */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS                                                                   0x00000068           /* RW-4R */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING                                           4:4                  /* RWIVF */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT                                      0x00000001           /* RWI-V */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE                                         8:8                  /* RWIVF */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT                                    0x00000001           /* RWI-V */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP                                                   11:11                /* RWIVF */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED                                               16:16                /* RWIVF */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED                                          17:17                /* RWIVF */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED                                              18:18                /* RWIVF */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED                                           19:19                /* RWIVF */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2                                                                 0x00000088           /* RW-4R */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE                                      6:6                  /* RWIVF */
+#define NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE_DEFAULT                              0x00000000           /* RWI-V */
+#define NV_EP_PCFG_GPU_LINK_CAPABILITIES                                                                       0x0000006C           /* R--4R */
+#define NV_EP_PCFG_GPU_LINK_CONTROL_STATUS                                                                     0x00000070           /* RW-4R */
+#define NV_EP_PCFG_GPU_LINK_CONTROL_STATUS_CURRENT_LINK_SPEED                                                  19:16                /* R-EVF */
+#define NV_EP_PCFG_GPU_MSIX_CAP_HEADER                                                                         0x000000B0           /* RW-4R */
+#define NV_EP_PCFG_GPU_MSIX_CAP_HEADER_ENABLE                                                                  31:31                /* RWIVF */
+#define NV_EP_PCFG_GPU_MSIX_CAP_HEADER_ENABLE_ENABLED                                                          0x00000001           /* RW--V */
+#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS                                                              0x000001BC           /* RW-4R */
+#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_DL_PROTOCOL_ERROR                                            4:4                  /* RWCVF */
+#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_RCVD                                            12:12                /* RWCVF */
+#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT                                           14:14                /* RWCVF */
+#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION                                        16:16                /* RWCVF */
+#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP                                                18:18                /* RWCVF */
+#define NV_EP_PCFG_GPU_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR                                    20:20                /* RWCVF */
+#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS                                                                0x000001C8           /* RW-4R */
+#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR                                                 0:0                  /* RWCVF */
+#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_BAD_TLP                                                        6:6                  /* RWCVF */
+#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_BAD_DLLP                                                       7:7                  /* RWCVF */
+#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER                                            8:8                  /* RWCVF */
+#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT                                           12:12                /* RWCVF */
+#define NV_EP_PCFG_GPU_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR                                       13:13                /* RWCVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC                                                                          0x000002B4           /* R--4R */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FUSE_POD                                                           0:0                  /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FUSE_SCPM                                                          1:1                  /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FSP_SCPM                                                           2:2                  /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_SEC2_SCPM                                                          3:3                  /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_FSP_DCLS                                                           4:4                  /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_SEC2_DCLS                                                          5:5                  /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_GSP_DCLS                                                           6:6                  /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_PMU_DCLS                                                           7:7                  /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_SEQ_TOO_BIG                                                        8:8                  /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_PRE_IFF_CRC                                                        9:9                  /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_POST_IFF_CRC                                                       10:10                /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ECC                                                                11:11                /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_CMD                                                                12:12                /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_PRI                                                                13:13                /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_WDG                                                                14:14                /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_BOOTFSM                                                            15:15                /* R-CVF */
+#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS                                                                  22:16                /* R-CVF */
+#endif // __gh100_dev_xtl_ep_pcfg_gpu_h__

src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pri.h

@@ -0,0 +1,27 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __gh100_dev_xtl_ep_pri_h__
+#define __gh100_dev_xtl_ep_pri_h__
+#define NV_EP_PCFGM                                                              0x92FFF:0x92000        /* RW--D */
+#endif // __gh100_dev_xtl_ep_pri_h__

src/common/inc/swref/published/hopper/gh100/hwproject.h

@@ -0,0 +1,23 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS              52

src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h

@@ -0,0 +1,51 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __gh100_pri_nv_xal_ep_h__
+#define __gh100_pri_nv_xal_ep_h__
+#define NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT                                         0x000010
+#define NV_XAL_EP_BAR0_WINDOW_BASE                                                   21:0
+#define NV_XAL_EP_BAR0_WINDOW                                                  0x0010fd40
+#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY                                        0x0010f810
+#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_TOKEN                                        30:0
+#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED                              0x0010f814
+#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_TOKEN                              30:0
+#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS                            31:31
+#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS_BUSY                         0x1
+#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED                           0x0010f80c
+#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_TOKEN                           30:0
+#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS                         31:31
+#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS_BUSY                      0x1
+#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS                                     0x0010f808
+#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_TOKEN                                     30:0
+#define NV_XAL_EP_INTR_0                                                       0x0010f100
+#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT                                               5:5
+#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT_PENDING                                       0x1
+#define NV_XAL_EP_INTR_0_PRI_FECSERR                                                  1:1
+#define NV_XAL_EP_INTR_0_PRI_FECSERR_PENDING                                          0x1
+#define NV_XAL_EP_INTR_0_PRI_REQ_TIMEOUT                                              2:2
+#define NV_XAL_EP_INTR_0_PRI_REQ_TIMEOUT_PENDING                                      0x1
+#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT                                              3:3
+#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT_PENDING                                      0x1
+#define NV_XAL_EP_SCPM_PRI_DUMMY_DATA_PATTERN_INIT                             0xbadf0200
+#endif // __gh100_pri_nv_xal_ep_h__
+

src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep_p2p.h

@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __gh100_pri_nv_xal_ep_p2p_h__
+#define __gh100_pri_nv_xal_ep_p2p_h__
+#define NV_XAL_EP_P2P                   0x00827fff:0x00826000
+#define NV_XAL_EP_P2P_WMBOX_ADDR_ADDR   22:1
+#define NV_XAL_EP_P2P_WREQMB_L(i)                                     (0x00826200+(i)*64) /* R--4A */
+#define NV_XAL_EP_P2P_WREQMB_L__SIZE_1                                                  8 /*       */
+#define NV_XAL_EP_P2P_WREQMB_L__PRIV_LEVEL_MASK                                0x00826900 /*       */
+#define NV_XAL_EP_P2P_WREQMB_L_PAGE_ADDR                                             21:0 /* R-IUF */
+#define NV_XAL_EP_P2P_WREQMB_L_PAGE_ADDR_INIT                                    0x000000 /* R-I-V */
+#define NV_XAL_EP_P2P_WREQMB_H(i)                                     (0x00826204+(i)*64) /* R--4A */
+#define NV_XAL_EP_P2P_WREQMB_H__SIZE_1                                                  8 /*       */
+#define NV_XAL_EP_P2P_WREQMB_H__PRIV_LEVEL_MASK                                0x00826900 /*       */
+#define NV_XAL_EP_P2P_WREQMB_H_REQ_ATTR                                              31:0 /* R-IUF */
+#define NV_XAL_EP_P2P_WREQMB_H_REQ_ATTR_INIT                                   0x00000000 /* R-I-V */
+#endif // __gh100_pri_nv_xal_ep_p2p_h__

src/common/inc/swref/published/nv_arch.h

@@ -24,6 +24,8 @@
 #ifndef NV_ARCH_PUBLISHED_H
 #define NV_ARCH_PUBLISHED_H
 
+#include "nvcfg_sdk.h"
+
 // high byte indicates GPU-SERIES, as defined in Gpus.pm.
 #define NVGPU_ARCHITECTURE_SERIES               31:24
 #define NVGPU_ARCHITECTURE_SERIES_CLASSIC        0x00
@@ -44,6 +46,9 @@
 #define GPU_ARCHITECTURE_VOLTA2          GPU_ARCHITECTURE(_CLASSIC, 0x0150)
 #define GPU_ARCHITECTURE_TURING          GPU_ARCHITECTURE(_CLASSIC, 0x0160)
 #define GPU_ARCHITECTURE_AMPERE          GPU_ARCHITECTURE(_CLASSIC, 0x0170)
+#define GPU_ARCHITECTURE_HOPPER          GPU_ARCHITECTURE(_CLASSIC, 0x0180)
+
+#define GPU_ARCHITECTURE_ADA             GPU_ARCHITECTURE(_CLASSIC, 0x0190)
 
 #define GPU_ARCHITECTURE_T12X            GPU_ARCHITECTURE(_TEGRA,   0x0040)
 #define GPU_ARCHITECTURE_T13X            GPU_ARCHITECTURE(_TEGRA,   0x0013)
@@ -89,6 +94,15 @@
 #define GPU_IMPLEMENTATION_GA107         0x07
 #define GPU_IMPLEMENTATION_GA102F        0x0F
 
+#define GPU_IMPLEMENTATION_GH100         0x00
+
+
+#define GPU_IMPLEMENTATION_AD102         0x02
+
+#define GPU_IMPLEMENTATION_AD103         0x03
+
+#define GPU_IMPLEMENTATION_AD104         0x04
+
 #define GPU_IMPLEMENTATION_T124          0x00
 #define GPU_IMPLEMENTATION_T132          0x00
 #define GPU_IMPLEMENTATION_T210          0x00

src/common/inc/swref/published/nv_ref.h

@@ -127,6 +127,8 @@
 #define NV_PMC_BOOT_0_ARCHITECTURE_TU100                 0x00000016 /* R---V */
 #define NV_PMC_BOOT_0_ARCHITECTURE_TU110                 0x00000016 /* R---V */
 #define NV_PMC_BOOT_0_ARCHITECTURE_GA100                 0x00000017 /* R---V */
+#define NV_PMC_BOOT_0_ARCHITECTURE_GH100                 0x00000018 /* R---V */
+#define NV_PMC_BOOT_0_ARCHITECTURE_AD100                 0x00000019 /* R---V */
 
 #define NV_PMC_BOOT_1                                    0x00000004 /* R--4R */
 #define NV_PMC_BOOT_1_VGPU8                                     8:8 /* R--VF */

src/common/inc/swref/published/turing/tu102/dev_falcon_v4.h

@@ -28,15 +28,11 @@
 #define NV_PFALCON_FALCON_IRQSCLR_HALT_SET                                                             0x00000001     /* -W--V */
 #define NV_PFALCON_FALCON_IRQSCLR_SWGEN0                                                               6:6            /* -WXVF */
 #define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET                                                           0x00000001     /* -W--V */
-#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1                                                               7:7            /* -WXVF */
-#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET                                                           0x00000001     /* -W--V */
 #define NV_PFALCON_FALCON_IRQSTAT                                                                      0x00000008     /* R--4R */
 #define NV_PFALCON_FALCON_IRQSTAT_HALT                                                                 4:4            /* R-XVF */
 #define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE                                                            0x00000001     /* R---V */
 #define NV_PFALCON_FALCON_IRQSTAT_SWGEN0                                                               6:6            /* R-XVF */
 #define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE                                                          0x00000001     /* R---V */
-#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1                                                               7:7            /* R-XVF */
-#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE                                                          0x00000001     /* R---V */
 #define NV_PFALCON_FALCON_IRQMSET                                                                      0x00000010     /* -W-4R */
 #define NV_PFALCON_FALCON_IRQMCLR                                                                      0x00000014     /* -W-4R */
 #define NV_PFALCON_FALCON_IRQMASK                                                                      0x00000018     /* R--4R */

src/common/modeset/hdmipacket/nvhdmipkt.c

@@ -25,6 +25,7 @@
  * Purpose:   Provide initialization functions for HDMI library
  */
 
+#include <stddef.h>
 #include "nvlimits.h"
 #include "nvhdmipkt_common.h"
 #include "nvhdmipkt_class.h"
@@ -46,6 +47,7 @@
 #include "class/clc57d.h"
 #include "class/clc670.h"
 #include "class/clc67d.h"
+#include "class/clc770.h"
 
 // Class hierarchy structure
 typedef struct tagNVHDMIPKT_CLASS_HIERARCHY
@@ -167,6 +169,16 @@ static const NVHDMIPKT_CLASS_HIERARCHY hierarchy[] =
         NVC670_DISPLAY,                   // displayClass
         NVC67D_CORE_CHANNEL_DMA           // coreDmaClass
     },
+    {// Index 8==NVHDMIPKT_C771_CLASS
+        NVHDMIPKT_C771_CLASS,             // classId
+        NVHDMIPKT_C671_CLASS,             // parentClassId
+        NV_FALSE,                         // isRootClass
+        initializeHdmiPktInterfaceC771,   // initInterface
+        hdmiConstructorC771,              // constructor
+        hdmiDestructorC771,               // destructor
+        NVC770_DISPLAY,                   // displayClass
+        NVC67D_CORE_CHANNEL_DMA           // coreDmaClass
+    },
 };
 
 #if defined(DSC_CALLBACK_MODIFIED)
@@ -234,6 +246,11 @@ NvHdmiPkt_PacketWrite(NvHdmiPkt_Handle  libHandle,
         return NVHDMIPKT_LIBRARY_INIT_FAIL;
     }
 
+    if ((pPacket == NULL) || (packetLen == 0))
+    {
+        return NVHDMIPKT_INVALID_ARG;
+    }
+
     return pClass->hdmiPacketWrite(pClass,
                                    subDevice,
                                    displayId,

src/common/modeset/hdmipacket/nvhdmipkt.h

@@ -70,6 +70,12 @@ typedef enum _NVHDMIPKT_TYPE
     NVHDMIPKT_TYPE_VENDOR_SPECIFIC_INFOFRAME  = 4,  // VSI
     NVHDMIPKT_TYPE_AUDIO_INFOFRAME            = 5,  // Audio InfoFrame
     NVHDMIPKT_TYPE_EXTENDED_METADATA_PACKET   = 6,  // Extended Metadata Packet (HDMI 2.1)
+    NVHDMIPKT_TYPE_SHARED_GENERIC1            = 7,  // ADA+ Specifc shared generic infoframe 1~6
+    NVHDMIPKT_TYPE_SHARED_GENERIC2            = 8,
+    NVHDMIPKT_TYPE_SHARED_GENERIC3            = 9,
+    NVHDMIPKT_TYPE_SHARED_GENERIC4            = 10,
+    NVHDMIPKT_TYPE_SHARED_GENERIC5            = 11,
+    NVHDMIPKT_TYPE_SHARED_GENERIC6            = 12,
     NVHDMIPKT_INVALID_PKT_TYPE                = 13
 } NVHDMIPKT_TYPE;
 
@@ -99,6 +105,11 @@ typedef enum _NVHDMIPKT_TYPE
 #define NV_HDMI_PKT_TRANSMIT_CTRL_VIDEO_FMT_SW_CTRL     0x00000000
 #define NV_HDMI_PKT_TRANSMIT_CTRL_VIDEO_FMT_HW_CTRL     0x00000001
 
+#define NV_HDMI_PKT_TRANSMIT_CTRL_LOC                   7:6
+#define NV_HDMI_PKT_TRANSMIT_CTRL_LOC_VBLANK            0x00000000
+#define NV_HDMI_PKT_TRANSMIT_CTRL_LOC_VSYNC             0x00000001
+#define NV_HDMI_PKT_TRANSMIT_CTRL_LOC_LOADV             0x00000002
+
 // NVHDMIPKT_TC: HDMI Packet Transmit Control
 // NOTE: Client should use these defines below for transmit control, and avoid using the ones
 //       above. Use only if client knows and wants fine control. And in that case the value
@@ -132,6 +143,29 @@ typedef enum _NVHDMIPKT_TC
     NVHDMIPKT_TRANSMIT_CONTROL_VIDEO_FMT_HW_CTRL           =
     (DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _VIDEO_FMT, _HW_CTRL)),
 
+    NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME_LOC_LOADV=
+    (NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME   |
+     DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _LOADV)),
+
+    NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME_LOC_LOADV=
+    (NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME  |
+     DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _LOADV)),
+
+    NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME_LOC_VSYNC=
+    (NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME   |
+     DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VSYNC)),
+
+    NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME_LOC_VSYNC=
+    (NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME  |
+     DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VSYNC)),
+
+    NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME_LOC_VBLANK=
+    (NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME   |
+     DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VBLANK)),
+
+    NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME_LOC_VBLANK=
+    (NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME  |
+     DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VBLANK)),
 } NVHDMIPKT_TC;
 
 // RM client handles. Used when client chooses that hdmi library make RM calls.

src/common/modeset/hdmipacket/nvhdmipkt_0073.c

@@ -109,6 +109,12 @@ hdmiPacketWrite0073(NVHDMIPKT_CLASS*   pThis,
                     NvU8 const *const  pPacket)
 {
     NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS;
+
+    if (packetLen > NV0073_CTRL_SET_OD_MAX_PACKET_SIZE)
+    {
+        return NVHDMIPKT_INVALID_ARG;
+    }
+
     NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS params = {0};
 
     NVMISC_MEMSET(&params, 0, sizeof(params));

src/common/modeset/hdmipacket/nvhdmipkt_9171.c

@@ -282,12 +282,9 @@ hdmiWriteVendorPacket9171(NVHDMIPKT_CLASS*   pThis,
                           NvU32*             pBaseReg,
                           NvU32              head,
                           NvU32              packetLen,
-                          NvU8 const *const  pPacketIn)
+                          NvU8 const *const  pPacket)
 {
     NvU32 data = 0;
-    NvU8  pPacket[31] = {0};
-
-    NVMISC_MEMCPY(pPacket, pPacketIn, packetLen);
 
     data = REG_RD32(pBaseReg, NV9171_SF_HDMI_VSI_HEADER(head));
     data = FLD_SET_DRF_NUM(9171, _SF_HDMI_VSI_HEADER, _HB0,         pPacket[0],  data);
@@ -515,6 +512,41 @@ checkPacketStatus_exit:
     return result;
 }
 
+static NVHDMIPKT_RESULT
+validateInputPacketLength(NvU32               pktType9171,
+                          NvU32               packetLen, 
+                          NvU8 const *const   pPacketIn)
+{
+    NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS;
+    HDMI_PACKET_TYPE infoframeType = pPacketIn[0];
+
+    // Lower bound check. Since actual infoframe size varies depending on the infoframe packet being sent, 
+    // check all supported infoframe types and their expected sizes. This is not a strict == check becuase they may/may not need
+    // additional checksum byte (library clients take care of adding checksum byte if needed)
+    if (((infoframeType == hdmi_pktType_GeneralControl)                 && (packetLen < 6))                                             ||
+        ((infoframeType == hdmi_pktType_GamutMetadata)                  && (packetLen < sizeof(NVT_GAMUT_METADATA)))                    ||
+        ((infoframeType == hdmi_pktType_ExtendedMetadata)               && (packetLen < sizeof(NVT_EXTENDED_METADATA_PACKET_INFOFRAME)))||
+        ((infoframeType == hdmi_pktType_VendorSpecInfoFrame)            && (packetLen < 8))                                             ||
+        ((infoframeType == hdmi_pktType_AviInfoFrame)                   && (packetLen < sizeof(NVT_VIDEO_INFOFRAME)))                   ||
+        ((infoframeType == hdmi_pktType_SrcProdDescInfoFrame)           && (packetLen < sizeof(NVT_SPD_INFOFRAME)))                     ||
+        ((infoframeType == hdmi_pktType_DynamicRangeMasteringInfoFrame) && (packetLen < sizeof(NVT_HDR_INFOFRAME))))
+        //  Unused: hdmi_pktType_AudioClkRegeneration
+        //  Unused: hdmi_pktType_MpegSrcInfoFrame
+    {
+        result = NVHDMIPKT_INVALID_ARG;
+    }
+
+    // Upper bound check. Check against number of bytes possible on the hw infoframe unit
+    if (((pktType9171 == NV9171_SF_HDMI_INFO_IDX_AVI_INFOFRAME)     && (packetLen > 17)) || // 3 bytes header + 14 bytes data
+        ((pktType9171 == NV9171_SF_HDMI_INFO_IDX_GENERIC_INFOFRAME) && (packetLen > 31)) || // 3 bytes header + 28 bytes data
+        ((pktType9171 == NV9171_SF_HDMI_INFO_IDX_VSI)               && (packetLen > 31)))   // 3 bytes header + 28 bytes data
+    {
+        result = NVHDMIPKT_INVALID_ARG;
+    }
+
+    return result;
+}
+
 /*
  * hdmiPacketWrite9171
  */
@@ -526,7 +558,7 @@ hdmiPacketWrite9171(NVHDMIPKT_CLASS*   pThis,
                     NVHDMIPKT_TYPE     packetType,
                     NVHDMIPKT_TC       transmitControl, 
                     NvU32              packetLen, 
-                    NvU8 const *const  pPacket)
+                    NvU8 const *const  pPacketIn)
 {
     NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS;
     NvU32* pBaseReg    = (NvU32*)pThis->memMap[subDevice].pMemBase;
@@ -534,13 +566,26 @@ hdmiPacketWrite9171(NVHDMIPKT_CLASS*   pThis,
     NvU32  tc          = pThis->translateTransmitControl(pThis, transmitControl);
     NV0073_CTRL_SPECIFIC_CTRL_HDMI_PARAMS params = {0};
 
-    if (pBaseReg == 0 || head >= NV9171_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 ||
-        packetLen == 0 || pPacket == 0 || pktType9171 == NVHDMIPKT_9171_INVALID_PKT_TYPE)
+    // packetIn can be of varying size. Use a fixed max size buffer for programing hw units to prevent out of bounds access
+    NvU8   pPacket[31] = {0};
+
+    if (pBaseReg == 0  || head >= NV9171_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 ||
+        packetLen == 0 || pPacketIn == 0 || pktType9171 == NVHDMIPKT_9171_INVALID_PKT_TYPE)
     {
         result = NVHDMIPKT_INVALID_ARG;
         goto hdmiPacketWrite9171_exit;
     }
 
+    if ((result = validateInputPacketLength(pktType9171, packetLen, pPacketIn)) != NVHDMIPKT_SUCCESS)
+    {
+        NvHdmiPkt_Print(pThis, "ERROR - input packet length incorrect");
+        NvHdmiPkt_Assert(0);
+        goto hdmiPacketWrite9171_exit;
+    }
+
+    // input packet looks ok to use, copy over the bytes
+    NVMISC_MEMCPY(pPacket, pPacketIn, packetLen);
+
     // acquire mutex
     pThis->callback.acquireMutex(pThis->cbHandle);
 

src/common/modeset/hdmipacket/nvhdmipkt_C771.c

@@ -0,0 +1,306 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * File:      nvhdmipkt_C771.c
+ *
+ * Purpose:   Provides packet write functions for HDMI library  for ADA+ chips
+ */
+
+#include "nvhdmipkt_common.h"
+#include "nvhdmipkt_class.h"
+
+#include "nvhdmipkt_internal.h"
+
+#include "class/clc771.h"
+
+extern NVHDMIPKT_RESULT hdmiPacketWrite9171(NVHDMIPKT_CLASS*   pThis,
+                                            NvU32              subDevice,
+                                            NvU32              displayId,
+                                            NvU32              head,
+                                            NVHDMIPKT_TYPE     packetType,
+                                            NVHDMIPKT_TC       transmitControl,
+                                            NvU32              packetLen,
+                                            NvU8 const *const  pPacket);
+
+extern NVHDMIPKT_RESULT hdmiPacketCtrl9171(NVHDMIPKT_CLASS*  pThis,
+                                            NvU32             subDevice,
+                                            NvU32             displayId,
+                                            NvU32             head,
+                                            NVHDMIPKT_TYPE    packetType,
+                                            NVHDMIPKT_TC      transmitControl);
+
+static NvU32
+translateTransmitControlC771(NVHDMIPKT_CLASS*  pThis,
+                             NVHDMIPKT_TC      transmitControl)
+{
+    NvU32 tc = 0;
+
+    if (FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _ENABLE, _EN, transmitControl))
+    {
+        tc = FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _ENABLE, _YES, tc);
+    }
+
+    if (FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _SINGLE, _EN, transmitControl))
+    {
+        tc = FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _SINGLE, _YES, tc);
+    }
+
+    if (FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _CHKSUM_HW, _EN, transmitControl))
+    {
+        tc = FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _CHECKSUM_HW, _YES, tc);
+    }
+
+    if (FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VBLANK, transmitControl))
+    {
+        tc = FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _LOC, _VBLANK, tc);
+    }
+    else if (FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _VSYNC, transmitControl))
+    {
+        tc = FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _LOC, _VSYNC, tc);
+    }
+    else if (FLD_TEST_DRF(_HDMI_PKT, _TRANSMIT_CTRL, _LOC, _LOADV, transmitControl))
+    {
+        tc = FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _LOC, _LOADV, tc);
+    }
+
+    return tc;
+}
+
+static NVHDMIPKT_RESULT
+hdmiWritePacketCtrlC771(NVHDMIPKT_CLASS*  pThis,
+                        NvU32*            pBaseReg,
+                        NvU32             head,
+                        NvU32             pktTypeC771,
+                        NvU32             transmitControl,
+                        NvBool            bDisable)
+{
+    NvU32 regOffset = 0;
+    NvU32 hdmiCtrl  = 0;
+    NvU32 sharedGenericIdx = pktTypeC771;
+
+    // This function only handles shared generic infoframe ctrl.
+    if (pBaseReg == 0 || head >= NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 || 
+        sharedGenericIdx >= NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_2)
+    {
+        return NVHDMIPKT_INVALID_ARG;
+    }
+
+    regOffset = NVC771_SF_SHARED_GENERIC_CTRL(head, sharedGenericIdx);
+    hdmiCtrl = REG_RD32(pBaseReg, regOffset);
+    hdmiCtrl = (bDisable == NV_TRUE) ?
+                (FLD_SET_DRF(C771, _SF_SHARED_GENERIC_CTRL, _ENABLE, _NO, hdmiCtrl)) :
+                (transmitControl);
+    REG_WR32(pBaseReg, regOffset, hdmiCtrl);
+
+    return NVHDMIPKT_SUCCESS;
+}
+
+static NVHDMIPKT_RESULT
+hdmiPacketCtrlC771(NVHDMIPKT_CLASS*  pThis,
+                   NvU32             subDevice,
+                   NvU32             displayId,
+                   NvU32             head,
+                   NVHDMIPKT_TYPE    packetType,
+                   NVHDMIPKT_TC      transmitControl)
+{
+    NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS;
+    NvU32* pBaseReg    = (NvU32*)pThis->memMap[subDevice].pMemBase;
+
+    if (pBaseReg == 0 || head >= NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1
+        || packetType >= NVHDMIPKT_INVALID_PKT_TYPE)
+    {
+        return NVHDMIPKT_INVALID_ARG;
+    }
+
+    NvU32 tc = 0;
+    switch (packetType)
+    {
+        case NVHDMIPKT_TYPE_SHARED_GENERIC1:
+        case NVHDMIPKT_TYPE_SHARED_GENERIC2:
+        case NVHDMIPKT_TYPE_SHARED_GENERIC3:
+        case NVHDMIPKT_TYPE_SHARED_GENERIC4:
+        case NVHDMIPKT_TYPE_SHARED_GENERIC5:
+        case NVHDMIPKT_TYPE_SHARED_GENERIC6:
+            tc = translateTransmitControlC771(pThis, transmitControl);
+            result = hdmiWritePacketCtrlC771(pThis, pBaseReg, head, packetType - NVHDMIPKT_TYPE_SHARED_GENERIC1, tc, NV_FALSE);
+            break;
+        default:
+            result = hdmiPacketCtrl9171(pThis, subDevice, displayId, head, packetType, transmitControl);
+            break;
+    }
+    return result;
+}
+
+static NVHDMIPKT_RESULT
+hdmiWriteSharedGenericPacketC771(NVHDMIPKT_CLASS*   pThis,
+                                 NvU32              subDevice,
+                                 NvU32              displayId,
+                                 NvU32              head,
+                                 NvU32              pktTypeC771,
+                                 NVHDMIPKT_TC       transmitControl,
+                                 NvU32              packetLen,
+                                 NvU8 const *const  pPacketIn)
+{
+    NvU32 sharedGenericIdx = pktTypeC771;
+    NvU32 data = 0;
+    NvU32* pBaseReg = (NvU32*)pThis->memMap[subDevice].pMemBase;
+    NvU32  tc          = translateTransmitControlC771(pThis, transmitControl);
+    NvU8 pPacket[36] = {0};
+
+    if (pBaseReg == 0  || head >= NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 ||
+        packetLen == 0 || (packetLen > 36) || pPacketIn == 0 || sharedGenericIdx >= NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_2)
+    {
+        return NVHDMIPKT_INVALID_ARG;
+    }
+
+    // In case client doesn't guarantee input pkt length to be 9 DWORDs, create a local buffer to avoid out of bound access of input
+    NVMISC_MEMCPY(pPacket, pPacketIn, packetLen);
+
+    // Disable this packet type.
+    hdmiWritePacketCtrlC771(pThis, pBaseReg, head, sharedGenericIdx, tc, NV_TRUE);
+
+    data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER(head, sharedGenericIdx));
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_HEADER, _HB0,         pPacket[0],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_HEADER, _HB1,         pPacket[1],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_HEADER, _HB2,         pPacket[2],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_HEADER, _HB3,         pPacket[3],  data);
+    REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER(head, sharedGenericIdx), data);
+
+    data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0(head, sharedGenericIdx));
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK0, _DB0,   pPacket[4],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK0, _DB1,   pPacket[5],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK0, _DB2,   pPacket[6],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK0, _DB3,   pPacket[7],  data);
+    REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0(head, sharedGenericIdx), data);
+
+    data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1(head, sharedGenericIdx));
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK1, _DB4,   pPacket[8],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK1, _DB5,   pPacket[9],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK1, _DB6,   pPacket[10],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK1, _DB7,   pPacket[11],  data);
+    REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1(head, sharedGenericIdx), data);
+
+    data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2(head, sharedGenericIdx));
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK2, _DB8,   pPacket[12],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK2, _DB9,   pPacket[13],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK2, _DB10,   pPacket[14],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK2, _DB11,   pPacket[15],  data);
+    REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2(head, sharedGenericIdx), data);
+
+    data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3(head, sharedGenericIdx));
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK3, _DB12,   pPacket[16],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK3, _DB13,   pPacket[17],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK3, _DB14,   pPacket[18],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK3, _DB15,   pPacket[19],  data);
+    REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3(head, sharedGenericIdx), data);
+
+    data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4(head, sharedGenericIdx));
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK4, _DB16,   pPacket[20],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK4, _DB17,   pPacket[21],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK4, _DB18,   pPacket[22],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK4, _DB19,   pPacket[23],  data);
+    REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4(head, sharedGenericIdx), data);
+
+    data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5(head, sharedGenericIdx));
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK5, _DB20,   pPacket[24],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK5, _DB21,   pPacket[25],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK5, _DB22,   pPacket[26],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK5, _DB23,   pPacket[27],  data);
+    REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5(head, sharedGenericIdx), data);
+
+    data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6(head, sharedGenericIdx));
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK6, _DB24,   pPacket[28],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK6, _DB25,   pPacket[29],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK6, _DB26,   pPacket[30],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK6, _DB27,   pPacket[31],  data);
+    REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6(head, sharedGenericIdx), data);
+
+    data = REG_RD32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7(head, sharedGenericIdx));
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK7, _DB28,   pPacket[32],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK7, _DB29,   pPacket[33],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK7, _DB30,   pPacket[34],  data);
+    data = FLD_SET_DRF_NUM(C771, _SF_SHARED_GENERIC_INFOFRAME_SUBPACK7, _DB31,   pPacket[35],  data);
+    REG_WR32(pBaseReg, NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7(head, sharedGenericIdx), data);
+
+    // Enable this infoframe.
+    hdmiWritePacketCtrlC771(pThis, pBaseReg, head, sharedGenericIdx, tc, NV_FALSE);
+
+    return NVHDMIPKT_SUCCESS;
+}
+
+static NVHDMIPKT_RESULT
+hdmiPacketWriteC771(NVHDMIPKT_CLASS*   pThis,
+                    NvU32              subDevice,
+                    NvU32              displayId,
+                    NvU32              head,
+                    NVHDMIPKT_TYPE     packetType,
+                    NVHDMIPKT_TC       transmitControl, 
+                    NvU32              packetLen, 
+                    NvU8 const *const  pPacketIn)
+{
+    NVHDMIPKT_RESULT result = NVHDMIPKT_SUCCESS;
+
+    if (head >= NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 ||
+        packetLen == 0                                            || 
+        pPacketIn == 0                                            ||
+        packetType >= NVHDMIPKT_INVALID_PKT_TYPE)
+    {
+        return NVHDMIPKT_INVALID_ARG;
+    }
+
+    if (packetType >= NVHDMIPKT_TYPE_SHARED_GENERIC1 && packetType <= NVHDMIPKT_TYPE_SHARED_GENERIC6)
+    {
+        result = hdmiWriteSharedGenericPacketC771(pThis, subDevice, displayId, head, packetType - NVHDMIPKT_TYPE_SHARED_GENERIC1, transmitControl, packetLen, pPacketIn);
+    }
+    else
+    {
+        result = hdmiPacketWrite9171(pThis, subDevice, displayId, head, packetType, transmitControl, packetLen, pPacketIn);
+    }
+
+    return result;
+}
+
+// non-HW - class utility/maintenance functions
+NvBool
+hdmiConstructorC771(NVHDMIPKT_CLASS* pThis)
+{
+    NvBool result = NV_TRUE;
+
+    return result;
+}
+
+void
+hdmiDestructorC771(NVHDMIPKT_CLASS* pThis)
+{
+    return;
+}
+
+void
+initializeHdmiPktInterfaceC771(NVHDMIPKT_CLASS* pClass)
+{
+    // Update SF_USER data
+    pClass->dispSfUserClassId = NVC771_DISP_SF_USER;
+    pClass->dispSfUserSize    = sizeof(NvC771DispSfUserMap);
+
+    pClass->hdmiPacketCtrl    = hdmiPacketCtrlC771;
+    pClass->hdmiPacketWrite   = hdmiPacketWriteC771;
+}

src/common/modeset/hdmipacket/nvhdmipkt_class.h

@@ -47,6 +47,7 @@ typedef enum
     NVHDMIPKT_C371_CLASS = 5, // GV100
     NVHDMIPKT_C571_CLASS = 6, // TU102
     NVHDMIPKT_C671_CLASS = 7, // GA102, T234D
+    NVHDMIPKT_C771_CLASS = 8, // AD10X
     NVHDMIPKT_INVALID_CLASS   // Not to be used by client, and always the last entry here.
 } NVHDMIPKT_CLASS_ID;
 

src/common/modeset/hdmipacket/nvhdmipkt_internal.h

@@ -41,6 +41,7 @@ extern void initializeHdmiPktInterface9471(NVHDMIPKT_CLASS*);
 extern void initializeHdmiPktInterface9571(NVHDMIPKT_CLASS*);
 extern void initializeHdmiPktInterfaceC371(NVHDMIPKT_CLASS*);
 extern void initializeHdmiPktInterfaceC671(NVHDMIPKT_CLASS*);
+extern void initializeHdmiPktInterfaceC771(NVHDMIPKT_CLASS*);
 
 extern NvBool hdmiConstructor0073(NVHDMIPKT_CLASS*);
 extern void   hdmiDestructor0073 (NVHDMIPKT_CLASS*);
@@ -56,5 +57,7 @@ extern NvBool hdmiConstructorC371(NVHDMIPKT_CLASS*);
 extern void   hdmiDestructorC371 (NVHDMIPKT_CLASS*);
 extern NvBool hdmiConstructorC671(NVHDMIPKT_CLASS*);
 extern void   hdmiDestructorC671 (NVHDMIPKT_CLASS*);
+extern NvBool hdmiConstructorC771(NVHDMIPKT_CLASS*);
+extern void   hdmiDestructorC771 (NVHDMIPKT_CLASS*);
 
 #endif //_NVHDMIPKT_INTERNAL_H_

src/common/modeset/timing/nvt_cvt.c

@@ -1,6 +1,6 @@
 //*****************************************************************************
 //
-//  SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+//  SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 //  SPDX-License-Identifier: MIT
 //
 //  Permission is hereby granted, free of charge, to any person obtaining a
@@ -38,19 +38,19 @@ CONS_SEGMENT(PAGE_CONS)
 
 const NvU32 NVT_MAX_NVU32= (NvU32)(-1);
 
-const NvU32 NVT_CVT_CELL_GRAN=8;              
-const NvU32 NVT_CVT_MIN_VSYNCBP=11;     // in 550us (!!) [1000000:550 = 20000:11]
-const NvU32 NVT_CVT_V_PORCH=3;          // in pixels
-const NvU32 NVT_CVT_C_PRIME=30;         // value of (C' * 10)
-const NvU32 NVT_CVT_M_PRIME_D_20=15;    // value of (M' / 100)
-const NvU32 NVT_CVT_CLOCK_STEP=25;      // Pclk step, in 10kHz
-const NvU32 NVT_CVT_H_SYNC_PER=8;       // HSYNC percentage (8%)
+const NvU32 NVT_CVT_CELL_GRAN        = 8;  // Character cell width. 
+const NvU32 NVT_CVT_MIN_VSYNCBP      = 11; // in 550us (!!) [1000000:550 = 20000:11]
+const NvU32 NVT_CVT_V_PORCH          = 3;  // in pixels
+const NvU32 NVT_CVT_C_PRIME          = 30; // value of (C' * 10)
+const NvU32 NVT_CVT_M_PRIME_D_20     = 15; // value of (M' / 100)
+const NvU32 NVT_CVT_CLOCK_STEP       = 25; // Pclk step, in 10kHz
+const NvU32 NVT_CVT_H_SYNC_PER       = 8;  // HSYNC percentage (8%)
 
-const NvU32 NVT_CVT_RB_HBLANK_CELLS=20; // 160 fixed hblank for RB
-const NvU32 NVT_CVT_RB_HFPORCH_CELLS=6; // 48 fixed hfporch for RB
-const NvU32 NVT_CVT_RB_HSYNCW_CELLS=4;  // 32 fixed hsyncwidth for RB
-const NvU32 NVT_CVT_RB_MIN_VBLANK=23;   // 460 lines (or 460 us?) [1000000:460 = 50000:23]
-const NvU32 NVT_CVT_MIN_V_BPORCH=6;
+const NvU32 NVT_CVT_RB_HBLANK_CELLS  = 20; // 160 fixed hblank for RB
+const NvU32 NVT_CVT_RB_HFPORCH_CELLS = 6;  // 48 fixed hfporch for RB
+const NvU32 NVT_CVT_RB_HSYNCW_CELLS  = 4;  // 32 fixed hsyncwidth for RB
+const NvU32 NVT_CVT_RB_MIN_VBLANK    = 23; // 460 lines (or 460 us?) [1000000:460 = 50000:23]
+const NvU32 NVT_CVT_MIN_V_BPORCH     = 6;  // Minimum vertical back porch.
 
 
 // VESA CVT spec ver1.2:
@@ -60,13 +60,12 @@ const NvU32 NVT_CVT_MIN_V_BPORCH=6;
 #define NVT_CVT_RB2_H_BLANK_PIXELS         80
 #define NVT_CVT_RB2_H_SYNC_PIXELS          32
 #define NVT_CVT_RB2_MIN_VBLANK_MICROSEC    460
-#define NVT_CVT_RB2_V_FPORCH_MIN           1
-#define NVT_CVT_RB2_V_BPORCH               6
+#define NVT_CVT_RB2_MIN_V_FPORCH           1
+#define NVT_CVT_RB2_MIN_V_BPORCH           6
 // Page 16 : Table 3-2 : Vertical Sync Duration
 #define NVT_CVT_RB2_V_SYNC_WIDTH           8    
 // Page 22: RB_MIN_VBI = RB_V_FPORCH + V_SYNC_RND + MIN_V_BPORCH
-#define NVT_CVT_RB2_MIN_VBI  NVT_CVT_RB2_V_SYNC_WIDTH + NVT_CVT_RB2_V_FPORCH_MIN + NVT_CVT_RB2_V_BPORCH
-
+#define NVT_CVT_RB2_MIN_VBI  NVT_CVT_RB2_V_SYNC_WIDTH + NVT_CVT_RB2_MIN_V_FPORCH + NVT_CVT_RB2_MIN_V_BPORCH
 // Page 15 : The Horizontal Sync Pulse duration will in all cases be 32 pixel clocks in duration, with the position
 // set so that the trailing edge of the Horizontal Sync Pulse is located in the center of the Horizontal
 // Blanking period.This implies that for a fixed blank of 80 pixel clocks, the Horizontal Back Porch is
@@ -74,6 +73,21 @@ const NvU32 NVT_CVT_MIN_V_BPORCH=6;
 #define NVT_CVT_RB2_H_FPORCH               8
 #define NVT_CVT_RB2_H_BPORCH               40
 
+// VESA CVT spec ver2.0:
+//
+// Page 15 : Table 3-2 Constants
+#define NVT_CVT_RB3_CLOCK_STEP_KHZ        1000
+#define NVT_CVT_RB3_H_BLANK_PIXELS        NVT_CVT_RB2_H_BLANK_PIXELS
+#define NVT_CVT_RB3_H_SYNC_PIXELS         NVT_CVT_RB2_H_SYNC_PIXELS
+#define NVT_CVT_RB3_H_FPORCH              NVT_CVT_RB2_H_FPORCH
+#define NVT_CVT_RB3_MIN_VBLANK_MICROSEC   NVT_CVT_RB2_MIN_VBLANK_MICROSEC
+#define NVT_CVT_RB3_V_FIELD_RATE_PPM_ADJ  350
+#define NVT_CVT_RB3_V_SYNC_WIDTH          NVT_CVT_RB2_V_SYNC_WIDTH
+#define NVT_CVT_RB3_MIN_V_FPORCH          NVT_CVT_RB2_MIN_V_FPORCH
+#define NVT_CVT_RB3_MIN_V_BPROCH          NVT_CVT_RB2_MIN_V_BPORCH
+
+#define NVT_CVT_RB3_MIN_VBI               NVT_CVT_RB2_MIN_VBI
+
 CODE_SEGMENT(PAGE_DD_CODE)
 static NvU16 getCVTVSync(NvU32 XRes, NvU32 YRes)
 {
@@ -136,10 +150,12 @@ NVT_STATUS NvTiming_CalcCVT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT
     
     NVMISC_MEMSET(pT, 0, sizeof(NVT_TIMING));
 
-    pT->etc.status = NVT_STATUS_CVT;  
+    pT->etc.status = NVT_STATUS_CVT;
+
+    // H_PIXELS_RND = ROUNDDOWN(H_PIXELS / CELL_GRAN_RND,0) * CELL_GRAN_RND
     if ((width % NVT_CVT_CELL_GRAN)!=0)
     {
-        width = (width + NVT_CVT_CELL_GRAN / 2) / NVT_CVT_CELL_GRAN * NVT_CVT_CELL_GRAN;
+        width = (width / NVT_CVT_CELL_GRAN) * NVT_CVT_CELL_GRAN;
         NVT_SET_TIMING_STATUS_MISMATCH(pT->etc.status, NVT_STATUS_TIMING_MISMATCH_ALIGNMENT);
     }
 
@@ -245,11 +261,12 @@ NVT_STATUS NvTiming_CalcCVT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag,
         return NVT_STATUS_ERR;//NVT_STATUS_ERR_BACKOFF | NVT_STATUS_ERR_OUTOFRANGE;
 
     NVMISC_MEMSET(pT, 0, sizeof(NVT_TIMING));
-
     pT->etc.status = NVT_STATUS_CVT_RB;   
+    
+    // H_PIXELS_RND = ROUNDDOWN(H_PIXELS / CELL_GRAN_RND,0) * CELL_GRAN_RND
     if ((width % NVT_CVT_CELL_GRAN)!=0)
     {
-        width = (width + NVT_CVT_CELL_GRAN / 2) / NVT_CVT_CELL_GRAN * NVT_CVT_CELL_GRAN;
+        width = (width / NVT_CVT_CELL_GRAN) * NVT_CVT_CELL_GRAN;
         NVT_SET_TIMING_STATUS_MISMATCH(pT->etc.status, NVT_STATUS_TIMING_MISMATCH_ALIGNMENT);
     }
 
@@ -371,7 +388,7 @@ NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is10
     // 15. Find Actual Field Rate(Hz) :
     // ACT_FIELD_RATE = 1000 * ACT_H_FREQ / TOTAL_V_LINES
     // 16. Find actual Vertical Refresh Rate(Hz) :
-    // ACT_FRAME_RATE = IF(INT_RQD ? = "y", ACT_FIELD_RATE / 2, ACT_FI
+    // ACT_FRAME_RATE = IF(INT_RQD ? = "y", ACT_FIELD_RATE / 2, ACT_FIELD_RATE
 
     // fill in the essential timing info for output
     pT->HVisible    = (NvU16)width;
@@ -381,7 +398,7 @@ NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is10
     pT->VVisible    = (NvU16)height;
     pT->VTotal      = (NvU16)total_v_lines;
     pT->VSyncWidth  = NVT_CVT_RB2_V_SYNC_WIDTH;
-    pT->VFrontPorch = (NvU16)(act_vbi_lines - NVT_CVT_RB2_V_SYNC_WIDTH - NVT_CVT_RB2_V_BPORCH);
+    pT->VFrontPorch = (NvU16)(act_vbi_lines - NVT_CVT_RB2_V_SYNC_WIDTH - NVT_CVT_RB2_MIN_V_BPORCH);
     pT->pclk        = (act_pixel_freq_khz + 5) / 10; //convert to 10Khz
     pT->HSyncPol    = NVT_H_SYNC_POSITIVE;
     pT->VSyncPol    = NVT_V_SYNC_NEGATIVE;
@@ -391,7 +408,7 @@ NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is10
     // fill in the extra timing info
     pT->etc.flag   = 0;
     pT->etc.rr     = (NvU16)rr;
-    pT->etc.rrx1k  = axb_div_c((NvU32)pT->pclk, (NvU32)10000 * (NvU32)1000, (NvU32)pT->HTotal*(NvU32)pT->VTotal);
+    pT->etc.rrx1k  = (NvU32)axb_div_c_64((NvU64)pT->pclk, (NvU64)10000 * (NvU64)1000, (NvU64)pT->HTotal*(NvU64)pT->VTotal);
     pT->etc.aspect = 0;
     pT->etc.rep    = 0x1;
     NVT_SNPRINTF((char *)pT->etc.name, 40, "CVT-RB2:%dx%dx%dHz", width, height, rr);
@@ -400,27 +417,206 @@ NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is10
     return NVT_STATUS_SUCCESS;
 }
 
+
+// CVT-RB3 timing calculation
+// This is intended to work in conjunction with VESA Adaptive-Sync operation (or other similar VRR methodology)
+CODE_SEGMENT(PAGE_DD_CODE)
+NVT_STATUS NvTiming_CalcCVT_RB3(NvU32 width, NvU32 height, NvU32 rr, NvU32 deltaHBlank, NvU32 vBlankMicroSec, NvBool isEarlyVSync, NVT_TIMING *pT)
+{
+    NvU32 vbi, act_v_blank_time, act_v_blank_lines, v_back_porch, total_v_lines, total_pixels, adj_rr_x1M, act_pixel_freq_khz;
+    NvU64 act_pixel_freq_hz = 0xFFFFFFFFFFFFFFFFULL;    
+
+    // parameter check 
+    if (pT == NULL)
+        return NVT_STATUS_ERR;
+
+    if (width == 0 || height == 0 || rr == 0)
+        return NVT_STATUS_ERR;
+
+    // Check for valid input parameter   
+    if ( (height % 8 != 0) || (deltaHBlank % 8 != 0) || deltaHBlank > 120 || vBlankMicroSec > 245)
+        return NVT_STATUS_INVALID_PARAMETER;
+
+    NVMISC_MEMSET(pT, 0, sizeof(NVT_TIMING));
+    pT->etc.status = NVT_STATUS_CVT_RB_3;
+
+    // 1 Calculate the required field refresh rate (Hz):
+    // V_FIELD_RATE_RQD = I_IP_FREQ_RQD * (1 + C_V_FIELD_RATE_PPM_ADJ / 1000000)
+
+    // Parameters mapping:
+    // - V_FIELD_RATE_RQD == "adj_rr_x1M"
+    // - I_IP_FREQ_RQD == "rr"
+    // - C_V_FIELD_RATE_PPM_ADJ == "NVT_CVT_RB3_V_FIELD_RATE_PPM_ADJ"
+    adj_rr_x1M = rr * (1000000 + NVT_CVT_RB3_V_FIELD_RATE_PPM_ADJ);
+
+    // 2 Round the desired number of horizontal pixels down to the nearest character cell boundary:
+    // TOTAL_ACTIVE_PIXELS = ROUNDDOWN(I_H_PIXELS / C_CELL_GRAN_RND, 0) * C_CELL_GRAN_RND
+
+    // Parameters mapping:
+    // - TOTAL_ACTIVE_PIXELS and I_H_PIXELS == "width"
+    // - C_CELL_GRAN_RND == "NVT_CVT_CELL_GRAN"
+    if ((width % NVT_CVT_CELL_GRAN) != 0)
+    {
+        // ROUNDDOWN
+        width = (width / NVT_CVT_CELL_GRAN) * NVT_CVT_CELL_GRAN;
+        NVT_SET_TIMING_STATUS_MISMATCH(pT->etc.status, NVT_STATUS_TIMING_MISMATCH_ALIGNMENT);
+    }
+
+    // 3 Round the number of vertical lines down to the nearest integer:    
+    // V_LINES_RND = ROUNDDOWN(I_V_LINES, 0)
+
+    // Parameters mapping:
+    // - V_LINES_RND == "height"
+
+    // 4 Calculate the estimated Horizontal Period (kHz):
+    // H_PERIOD_EST = ((1000000 / (V_FIELD_RATE_RQD)) - C_RB_MIN_V_BLANK) / V_LINES_RND
+    
+    // Parameters mapping:
+    // - H_PERIOD_EST     == "h_period_est"
+    // - C_RB_MIN_V_BLANK == "NVT_CVT_RB3_MIN_VBLANK_MICROSEC"
+    // h_period_est = ((1000000000000 / adj_rr_x1M) - NVT_CVT_RB3_MIN_VBLANK_MICROSEC) / height
+    
+    // 5 Calculate the total VBlank time:
+    // ACT_V_BLANK_TIME = IF(I_VBLANK < C_RB_MIN_V_BLANK, C_RB_MIN_V_BLANK, I_VBLANK)
+    
+    // Parameters mapping:
+    // - ACT_V_BLANK_TIME == "act_v_blank_time"
+    // - I_VBLANK         == "vBlankMicroSec"
+    act_v_blank_time = MAX(vBlankMicroSec + 460, NVT_CVT_RB3_MIN_VBLANK_MICROSEC);
+
+    // 6 Calculate the number of idealized lines in the VBlank interval:
+    // VBI_LINES = ROUNDUP(ACT_V_BLANK_TIME / H_PERIOD_EST, 0)
+    
+    // Parameters mapping:
+    // - VBI_LINES == vbi"
+    // below formula are combining step 4, 5, 6 togerther. i.e. both numerator and denominator multiple by height and addj_rr_x1M.    
+    vbi = (NvU32)(((NvU64)height * (NvU64)act_v_blank_time * (NvU64)adj_rr_x1M) / ((NvU64)1000000000000 - (NvU64)act_v_blank_time * (NvU64)adj_rr_x1M));
+    // ROUNDUP
+    if (((NvU64)height * (NvU64)act_v_blank_time * (NvU64)adj_rr_x1M) % ((NvU64)1000000000000 - (NvU64)act_v_blank_time * (NvU64)adj_rr_x1M) !=0)
+        vbi += 1;
+
+    // 7 Determine whether idealized VBlank is sufficient and calculate the actual number of lines in the VBlank period:
+    // RB_MIN_VBI = C_RB_V_FPORCH + C_V_SYNC_RND + C_MIN_V_BPORCH
+    // V_BLANK = IF(VBI_LINES < RB_MIN_VBI, RB_MIN_VBI, VBI_LINES)
+
+    // Paameters mapping:
+    // - C_RB_V_FPORCH  == 1
+    // - C_V_SYNC_RND   == 8
+    // - C_MIN_V_BPORCH == 6
+    // - V_BLANK        == "act_v_blank_lines"
+    // NVT_CVT_RB3_MIN_VBI ==  1 + 8 + 6 = 15
+    act_v_blank_lines = MAX(vbi, NVT_CVT_RB3_MIN_VBI);
+
+    // 8 Calculate the total number of vertical lines:
+    // TOTAL_V_LINES = V_BLANK + V_LINES_RND
+    total_v_lines = act_v_blank_lines + height;
+
+    // 9 Calculate the vertical back porch:
+    // V_BACK_PORCH = IF(AND(I_RED_BLANK_VER=3, I_EARLY_VSYNC_RQD?="Y"), ROUNDDOWN(VBI_LINES / 2, 0), C_MIN_V_BPORCH)
+    
+    // Paameters mapping:
+    // - V_BACK_PORCH      == "v_back_porch"
+    // - I_RED_BLANK_VER   == "3" this is for RB3 function so the value is 3 
+    // - I_EARLY_VSYNC_RQD == "isEarlyVSync"
+    // - C_MIN_V_BPORCH    == 6
+    if (isEarlyVSync)
+        v_back_porch = vbi / 2;
+        // v_back_porch = act_v_blank_lines /2 ;
+    else 
+        v_back_porch = NVT_CVT_RB3_MIN_V_BPROCH;
+
+    // 10 Calculate the vertical front porch: 
+    // V_FRONT_PORCH = V_BLANK – V_BACK_PORCH – C_V_SYNC_RND
+    // we directly use this to assign as pT->VFrontPorch value in NVT_TIMING 
+
+    // 11 Calculate the total number of pixels per line:
+    // TOTAL_PIXELS = TOTAL_ACTIVE_PIXELS + C_RB_H_BLANK + IF(I_RED_BLANK_VER=3, I_ADDITIONAL_HBLANK, 0)
+
+    // Parameters mapping:
+    // - C_RB_H_BLANK        == 80 
+    // - I_ADDITIONAL_HBLANK == deltaHBlank scopes are defined in the TypeX in displayId2.1 
+    // 80 <= HBlank <=200 is a valid scope 
+    total_pixels  = width + deltaHBlank + 80;
+
+    // 12 Calculate the horizontal back porch:
+    // H_BACK_PORCH = C_RB_H_BLANK + IF(I_RED_BLANK_VER=3, I_ADDITIONAL_HBLANK, 0) – C_H_FRONT_PORCH – C_RB_H_SYNC
+    // NVT_TIMING did not need to store H_BACK_PORCH
+    
+    // sanity check just in case of bad edid where the timing value could exceed the limit of NVT_TIMING structure which unfortunately is defined in NvU16
+    if (total_pixels > (NvU16)-1 || total_v_lines > (NvU16)-1)
+        return NVT_STATUS_INVALID_PARAMETER;
+    
+    // 13 Calculate the pixel clock frequency to the nearest C_CLOCK_STEP (MHz):
+    // ACT_PIXEL_FREQ = C_CLOCK_STEP * ROUNDUP((V_FIELD_RATE_RQD * TOTAL_V_LINES * TOTAL_PIXELS / 1000000 * 1) / C_CLOCK_STEP, 0))
+    
+    // Parameters mapping:
+    // - ACT_PIXEL_FREQ == "act_pixel_freq_hz"
+    // - C_CLOCK_STEP   == "NVT_CVT_RB3_CLOCK_STEP_KHZ" == 1000
+    act_pixel_freq_hz = ((NvU64)adj_rr_x1M * (NvU64)total_v_lines * (NvU64)total_pixels / (NvU64)1000000);
+
+    // Here we need to divide extra 1000 because adj_rr_x1M extends to Million, i.e 1Mhz / 1000 = 1kHz
+    act_pixel_freq_khz = (NvU32)(act_pixel_freq_hz / NVT_CVT_RB3_CLOCK_STEP_KHZ);
+
+    // kHz ROUNDUP
+    if ((act_pixel_freq_hz  % 1000) != 0)       
+        act_pixel_freq_khz += 1;
+
+    pT->HVisible     = (NvU16)width;
+    pT->HTotal       = (NvU16)total_pixels;
+    pT->HFrontPorch  = NVT_CVT_RB3_H_FPORCH; 
+    pT->HSyncWidth   = NVT_CVT_RB3_H_SYNC_PIXELS;
+    pT->VVisible     = (NvU16)height;
+    pT->VTotal       = (NvU16)total_v_lines;
+    pT->VSyncWidth   = NVT_CVT_RB3_V_SYNC_WIDTH;
+    pT->VFrontPorch  = (NvU16)(act_v_blank_lines - NVT_CVT_RB2_V_SYNC_WIDTH - v_back_porch);
+    pT->pclk         = ((NvU32)act_pixel_freq_khz + 5) / 10; //convert to 10Khz
+    pT->HSyncPol     = NVT_H_SYNC_POSITIVE;
+    pT->VSyncPol     = NVT_V_SYNC_NEGATIVE;
+    pT->HBorder      = pT->VBorder = 0;  // not supported
+    pT->interlaced   = 0;                // not supported yet
+
+    // fill in the extra timing info
+    pT->etc.flag     = 0;
+    pT->etc.rr       = (NvU16)rr;
+    pT->etc.rrx1k    = (NvU32)axb_div_c_64((NvU64)pT->pclk, (NvU64)10000 * (NvU64)1000, (NvU64)pT->HTotal*(NvU64)pT->VTotal);
+    pT->etc.aspect   = 0;
+    pT->etc.rep      = 0x1;
+    NVT_SNPRINTF((char *)pT->etc.name, 40, "CVT-RB3:%dx%dx%dHz", width, height, rr);
+    pT->etc.name[39] = '\0';
+
+    return NVT_STATUS_SUCCESS;
+}
+
 CODE_SEGMENT(PAGE_DD_CODE)
 NvBool NvTiming_IsTimingCVTRB(const NVT_TIMING *pTiming)
 {
     // Check from the Timing Type
     NvU32 reducedType = 0;
+    NvU32 hblank      = 0;
     reducedType = NVT_GET_TIMING_STATUS_TYPE(pTiming->etc.status);
 
-    if (reducedType == NVT_TYPE_CVT_RB || reducedType == NVT_TYPE_CVT_RB_2)
+    if (reducedType == NVT_TYPE_CVT_RB || reducedType == NVT_TYPE_CVT_RB_2 || reducedType == NVT_TYPE_CVT_RB_3)
     {
         return NV_TRUE;
     }
 
+    hblank = pTiming->HTotal - pTiming->HVisible;
+
     // Manually Check for RB 1 and 2
     // RB1 - HBlank = 160, and HSync = 32, HFrontPorch = 48, HBackPorch = 80
-    if (((pTiming->HTotal - pTiming->HVisible) == 160) && (pTiming->HSyncWidth == 32) && (pTiming->HFrontPorch == 48))
+    if ((hblank == 160) && (pTiming->HSyncWidth == 32) && (pTiming->HFrontPorch == 48))
     {
         return NV_TRUE;
     }
 
     // RB2 - HBlank = 80, HSync = 32, HFrontPorch = 8, HBackPorch = 40
-    if (((pTiming->HTotal - pTiming->HVisible) == 80) && (pTiming->HSyncWidth == 32) && (pTiming->HFrontPorch == 8))
+    if ((hblank == 80) && (pTiming->HSyncWidth == 32) && (pTiming->HFrontPorch == 8))
+    {
+        return NV_TRUE;
+    }
+
+    // RB3 - HBlank is any integer multiple of 8 [80-200], HSync = 32, HFrontPorch = 8
+    if (((hblank > 80) && (hblank <= 200) && (hblank % 8 == 0)) && (pTiming->HSyncWidth == 32) && (pTiming->HFrontPorch == 8))
     {
         return NV_TRUE;
     }

src/common/modeset/timing/nvt_dsc_pps.c

@@ -283,6 +283,114 @@ static const NvU8 maxqp444_12b[15][61]={
        ,{23,23,22,22,21,21,21,21,20,20,19,19,19,19,18,18,18,17,17,17,16,16,16,16,15,15,14,14,14,14,14,13,13,12,12,12,12,12,11,11,10,10,10,10,10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4}
 };
 
+static const NvU8 minqp422_8b[15][21] = {
+        {0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{3 ,3 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{3 ,3 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0}
+       ,{3 ,3 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0}
+       ,{3 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,0 ,0}
+       ,{3 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1}
+       ,{3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1}
+       ,{5 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1}
+       ,{5 ,5 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,1 ,1}
+       ,{5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1}
+       ,{8 ,8 ,7 ,7 ,7 ,7 ,7 ,7 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,2}
+       ,{12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3}
+};
+
+static const NvU8 maxqp422_8b[15][21] = {
+        {4 ,4 ,3 ,3 ,2 ,2 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{4 ,4 ,4 ,4 ,4 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{5 ,5 ,5 ,5 ,5 ,4 ,3 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0}
+       ,{6 ,6 ,6 ,6 ,6 ,5 ,4 ,3 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0}
+       ,{7 ,7 ,7 ,7 ,7 ,6 ,5 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1}
+       ,{7 ,7 ,7 ,7 ,7 ,6 ,5 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1}
+       ,{7 ,7 ,7 ,7 ,7 ,6 ,5 ,4 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1}
+       ,{8 ,8 ,8 ,8 ,8 ,7 ,6 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,1 ,1}
+       ,{9 ,9 ,9 ,8 ,8 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2}
+       ,{10,10,9 ,9 ,9 ,8 ,7 ,6 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2}
+       ,{10,10,10,9 ,9 ,8 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,2}
+       ,{11,11,10,10,9 ,9 ,8 ,7 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2}
+       ,{11,11,11,10,9 ,9 ,8 ,8 ,7 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2}
+       ,{12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,3}
+       ,{13,13,12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4}
+};
+
+static const NvU8 minqp422_10b[15][29] = {
+        {0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{4 ,4 ,4 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{5 ,5 ,5 ,4 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{6 ,6 ,6 ,6 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{6 ,6 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0}
+       ,{6 ,6 ,6 ,6 ,6 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,3 ,2 ,1 ,1 ,0 ,0 ,0 ,0 ,0}
+       ,{6 ,6 ,6 ,6 ,6 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0}
+       ,{7 ,7 ,7 ,7 ,7 ,6 ,6 ,6 ,6 ,6 ,6 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1}
+       ,{7 ,7 ,7 ,7 ,7 ,6 ,6 ,6 ,6 ,6 ,6 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1}
+       ,{8 ,8 ,7 ,7 ,7 ,7 ,7 ,7 ,7 ,7 ,7 ,7 ,6 ,6 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,1}
+       ,{9 ,9 ,9 ,8 ,8 ,8 ,8 ,8 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,5 ,5 ,5 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1}
+       ,{9 ,9 ,9 ,9 ,8 ,8 ,8 ,8 ,8 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,6 ,6 ,6 ,5 ,5 ,4 ,3 ,3 ,2 ,2 ,1 ,1 ,1}
+       ,{9 ,9 ,9 ,9 ,9 ,9 ,9 ,9 ,9 ,9 ,9 ,8 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,3 ,3 ,3 ,2 ,2 ,1 ,1}
+       ,{12,12,11,11,11,11,11,11,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,1}
+       ,{16,16,15,15,14,14,13,13,12,12,11,11,10,10,9 ,9 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,3}
+};
+
+static const NvU8 maxqp422_10b[15][29] = {
+        {8 ,8 ,7 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{8 ,8 ,8 ,6 ,6 ,5 ,4 ,4 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{9 ,9 ,9 ,8 ,7 ,6 ,5 ,4 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0}
+       ,{10,10,10,10,9 ,8 ,7 ,6 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1}
+       ,{11,11,11,11,10,9 ,8 ,6 ,5 ,5 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1}
+       ,{11,11,11,11,11,10,9 ,8 ,7 ,6 ,6 ,5 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,3 ,2 ,2 ,1 ,1 ,1 ,1 ,1}
+       ,{11,11,11,11,11,10,9 ,8 ,7 ,7 ,7 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1}
+       ,{12,12,12,12,12,11,10,9 ,8 ,8 ,8 ,7 ,7 ,7 ,7 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,2 ,2 ,2}
+       ,{13,13,13,12,12,11,10,10,9 ,9 ,9 ,8 ,8 ,7 ,7 ,7 ,6 ,5 ,5 ,5 ,5 ,4 ,3 ,3 ,2 ,2 ,2 ,2 ,2}
+       ,{14,14,13,13,13,12,11,10,9 ,9 ,9 ,9 ,8 ,8 ,8 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,2 ,2}
+       ,{14,14,14,13,13,12,11,11,10,10,10,9 ,9 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,6 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2}
+       ,{15,15,14,14,13,13,12,11,11,11,10,10,9 ,9 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,2}
+       ,{15,15,15,14,13,13,12,12,11,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2}
+       ,{16,16,15,15,14,14,13,13,12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,2}
+       ,{17,17,16,16,15,15,14,14,13,13,12,12,11,11,10,10,9 ,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,4}
+};
+
+static const NvU8 minqp422_12b[15][37] = {
+        {0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{4 ,4 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{9 ,9 ,9 ,8 ,7 ,6 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,2 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{10,10,10,10,8 ,8 ,8 ,7 ,6 ,6 ,6 ,6 ,6 ,5 ,4 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{11,11,11,11,10,9 ,9 ,8 ,7 ,7 ,7 ,7 ,6 ,6 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{11,11,11,11,11,10,10,9 ,9 ,8 ,8 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,3 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{11,11,11,11,11,10,10,10,9 ,9 ,9 ,9 ,8 ,7 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,0 ,0 ,0 ,0}
+       ,{11,11,11,11,11,11,10,10,10,10,10,9 ,8 ,8 ,8 ,7 ,6 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,0 ,0 ,0}
+       ,{11,11,11,11,11,11,11,11,11,11,11,10,9 ,8 ,8 ,8 ,7 ,6 ,6 ,6 ,6 ,5 ,4 ,4 ,3 ,3 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,1 ,0 ,0 ,0}
+       ,{11,11,11,11,11,11,11,11,11,11,11,11,9 ,9 ,9 ,8 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,3 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,0 ,0}
+       ,{13,13,13,13,13,12,12,12,12,12,12,11,11,10,10,10,9 ,9 ,8 ,8 ,8 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1 ,1}
+       ,{13,13,13,13,13,13,13,13,13,13,12,12,11,11,10,10,10,9 ,9 ,8 ,8 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1}
+       ,{13,13,13,13,13,13,13,13,13,13,13,12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,6 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1}
+       ,{16,16,15,15,15,15,15,15,15,15,14,14,13,13,12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2}
+       ,{20,20,19,19,18,18,17,17,16,16,15,15,14,14,13,13,12,12,12,11,11,10,10,9 ,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,4 ,4}
+};
+
+static const NvU8 maxqp422_12b[15][37] = {
+        {12,12,11,9 ,6 ,6 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{12,12,12,10,9 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{13,13,13,12,10,9 ,8 ,7 ,6 ,6 ,6 ,6 ,6 ,6 ,5 ,5 ,4 ,3 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{14,14,14,14,12,11,10,9 ,8 ,8 ,8 ,8 ,8 ,7 ,6 ,5 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,2 ,2 ,2 ,1 ,1 ,0 ,0 ,0 ,0 ,0 ,0}
+       ,{15,15,15,15,14,13,12,10,9 ,9 ,9 ,9 ,8 ,8 ,7 ,6 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,0 ,0 ,0}
+       ,{15,15,15,15,15,14,13,12,11,10,10,9 ,8 ,8 ,7 ,7 ,7 ,6 ,6 ,6 ,6 ,5 ,4 ,4 ,3 ,3 ,3 ,2 ,2 ,2 ,2 ,1 ,1 ,1 ,1 ,1 ,1}
+       ,{15,15,15,15,15,14,13,12,11,11,11,11,10,9 ,9 ,9 ,8 ,8 ,7 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1 ,1 ,1}
+       ,{16,16,16,16,16,15,14,13,12,12,12,11,10,10,10,9 ,8 ,8 ,8 ,7 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,5 ,5 ,3 ,3 ,3 ,2 ,2 ,1 ,1 ,1}
+       ,{17,17,17,16,16,15,14,14,13,13,13,12,11,10,10,10,9 ,8 ,8 ,8 ,8 ,7 ,6 ,6 ,5 ,5 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,1 ,1 ,1}
+       ,{18,18,17,17,17,16,15,14,13,13,13,13,11,11,11,10,9 ,9 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,1 ,1}
+       ,{18,18,18,17,17,16,15,15,14,14,14,13,13,12,12,12,11,11,10,10,10,8 ,8 ,7 ,7 ,7 ,6 ,6 ,6 ,5 ,4 ,4 ,3 ,3 ,2 ,2 ,2}
+       ,{19,19,18,18,17,17,16,15,15,15,14,14,13,13,12,12,12,11,11,10,10,9 ,8 ,8 ,7 ,7 ,6 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2}
+       ,{19,19,19,18,17,17,16,16,15,15,15,14,14,13,13,12,12,11,11,10,10,9 ,8 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,4 ,4 ,3 ,3 ,2 ,2}
+       ,{20,20,19,19,18,18,17,17,16,16,15,15,14,14,13,13,12,12,11,11,10,10,9 ,9 ,8 ,8 ,7 ,7 ,6 ,6 ,5 ,5 ,5 ,4 ,4 ,3 ,3}
+       ,{21,21,20,20,19,19,18,18,17,17,16,16,15,15,14,14,13,13,13,12,12,11,11,10,10,10,9 ,9 ,8 ,8 ,7 ,7 ,7 ,6 ,6 ,5 ,5}
+};
+
 static const NvU32 rcBufThresh[] = { 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, 7744, 7872, 8000, 8064 };
 
 /* ------------------------ Static Variables ------------------------------- */
@@ -369,7 +477,7 @@ DSC_PpsCalcExtraBits
     DSC_OUTPUT_PARAMS *out
 )
 {
-    NvU32 numSsps = 3;
+    NvU32 numSsps = out->native_422 ? 4 : 3;
     NvU32 sliceBits;
     NvU32 extra_bits;
     NvU32 bitsPerComponent = out->bits_per_component;
@@ -418,6 +526,7 @@ DSC_PpsCalcRcInitValue
 )
 {
     NvU32 bitsPerPixel = out->bits_per_pixel;
+    NvU32 xmit_delay;
     out->rc_model_size = 8192;
 
     if (out->native_422)
@@ -427,7 +536,7 @@ DSC_PpsCalcRcInitValue
             out->initial_offset = 2048;
         else if (bitsPerPixel >= 14 * BPP_UNIT)
             out->initial_offset = 5632 - ((bitsPerPixel - 14 * BPP_UNIT) * 1792 + BPP_UNIT / 2) / BPP_UNIT;
-        else if (bitsPerPixel >= 12 * BPP_UNIT)
+        else
             out->initial_offset = 5632;
     }
     else
@@ -450,12 +559,52 @@ DSC_PpsCalcRcInitValue
     }
     RANGE_CHECK("initial_scale_value", out->initial_scale_value, 0, 63);
 
-    out->initial_xmit_delay = (4096*BPP_UNIT + bitsPerPixel / 2) / bitsPerPixel;
-    //RANGE_CHECK("initial_xmit_delay", out->initial_xmit_delay, 0, 1023);
+    xmit_delay = (4096*BPP_UNIT + bitsPerPixel/2) / bitsPerPixel;
+
+    if (out->native_420 || out->native_422)
+    {
+	    NvU32 slicew = (out->native_420 || out->native_422) ? out->slice_width / 2 : out->slice_width;
+	    NvU32 padding_pixels = ((slicew % 3) ? (3 - (slicew % 3)) : 0) * (xmit_delay / slicew);
+	    if (3 * bitsPerPixel >= ((xmit_delay + 2) / 3) * (out->native_422 ? 4 : 3) * BPP_UNIT &&
+			    (((xmit_delay + padding_pixels) % 3) == 1))
+        {
+		    xmit_delay++;
+	    }
+    }
+    out->initial_xmit_delay = xmit_delay;
+    RANGE_CHECK("initial_xmit_delay", out->initial_xmit_delay, 0, 1023);
 
     return NVT_STATUS_SUCCESS;
 }
 
+static NvU32 DSC_PpsCalcComputeOffset(DSC_OUTPUT_PARAMS *out, NvU32 grpcnt)
+{
+	NvU32 offset = 0;
+	NvU32 groupsPerLine = out->groups_per_line;
+	NvU32 grpcnt_id = (out->initial_xmit_delay + PIXELS_PER_GROUP - 1) / PIXELS_PER_GROUP;
+
+	if(grpcnt <= grpcnt_id)
+		offset = (grpcnt * PIXELS_PER_GROUP * out->bits_per_pixel + BPP_UNIT - 1) / BPP_UNIT;
+	else
+		offset = (grpcnt_id * PIXELS_PER_GROUP * out->bits_per_pixel + BPP_UNIT - 1) / BPP_UNIT - (((grpcnt-grpcnt_id) * out->slice_bpg_offset)>>OFFSET_FRACTIONAL_BITS);
+
+	if(grpcnt <= groupsPerLine)
+		offset += grpcnt * out->first_line_bpg_offset;
+	else
+		offset += groupsPerLine * out->first_line_bpg_offset - (((grpcnt - groupsPerLine) * out->nfl_bpg_offset)>>OFFSET_FRACTIONAL_BITS);
+
+	if(out->native_420)
+	{
+		if(grpcnt <= groupsPerLine)
+			offset -= (grpcnt * out->nsl_bpg_offset) >> OFFSET_FRACTIONAL_BITS;
+		else if(grpcnt <= 2*groupsPerLine)
+			offset += (grpcnt - groupsPerLine) * out->second_line_bpg_offset - ((groupsPerLine * out->nsl_bpg_offset)>>OFFSET_FRACTIONAL_BITS);
+		else
+			offset += (grpcnt - groupsPerLine) * out->second_line_bpg_offset - (((grpcnt - groupsPerLine) * out->nsl_bpg_offset)>>OFFSET_FRACTIONAL_BITS);
+	}
+	return(offset);
+}
+
 /*
  * @brief Calculate bpg value except slice_bpg_offset
  *
@@ -477,6 +626,7 @@ NvU32 DSC_PpsCalcBpg
     NvU32 bitsPerPixel;
     NvU32 rbsMin;
     NvU32 hrdDelay;
+    NvU32 groups_total;
 
     if (out->native_422)
         uncompressedBpgRate = PIXELS_PER_GROUP * out->bits_per_component * 4;
@@ -515,9 +665,35 @@ NvU32 DSC_PpsCalcBpg
     out->second_line_offset_adj = out->native_420 ? 512 : 0;
 
     bitsPerPixel = out->bits_per_pixel;
-    rbsMin = out->rc_model_size - out->initial_offset
+    groups_total = out->groups_per_line * out->slice_height;
+    out->slice_bpg_offset = (((out->rc_model_size - out->initial_offset + out->num_extra_mux_bits) << OFFSET_FRACTIONAL_BITS)
+                + groups_total - 1) / groups_total;
+    RANGE_CHECK("slice_bpg_offset", out->slice_bpg_offset, 0, 65535);
+
+    if((PIXELS_PER_GROUP * bitsPerPixel << OFFSET_FRACTIONAL_BITS) - (out->slice_bpg_offset + out->nfl_bpg_offset) * BPP_UNIT
+            < (1+5*PIXELS_PER_GROUP)*BPP_UNIT <<OFFSET_FRACTIONAL_BITS )
+    {
+        return NVT_STATUS_ERR;
+    }
+
+    if (((out->dsc_version_major > 1) || (out->dsc_version_major == 1 && out->dsc_version_minor >= 2)) &&
+        (out->native_420 || out->native_422))
+    {
+        // OPTIMIZED computation of rbsMin:
+        // Compute max by sampling offset at points of inflection
+        // *MODEL NOTE* MN_RBS_MIN
+        NvU32 maxOffset;
+        maxOffset = DSC_PpsCalcComputeOffset(out, (out->initial_xmit_delay+PIXELS_PER_GROUP-1)/PIXELS_PER_GROUP );  // After initial delay
+        maxOffset = MAX(maxOffset, DSC_PpsCalcComputeOffset(out, out->groups_per_line));   // After first line
+        maxOffset = MAX(maxOffset, DSC_PpsCalcComputeOffset(out, 2*out->groups_per_line));
+        rbsMin = out->rc_model_size - out->initial_offset + maxOffset;
+    }
+    else
+    { // DSC 1.1 method
+        rbsMin = out->rc_model_size - out->initial_offset
             + (out->initial_xmit_delay * bitsPerPixel + BPP_UNIT - 1) / BPP_UNIT
             + out->groups_per_line * out->first_line_bpg_offset;
+    }
     hrdDelay = (rbsMin * BPP_UNIT + bitsPerPixel - 1) / bitsPerPixel;
     out->initial_dec_delay = hrdDelay - out->initial_xmit_delay;
     RANGE_CHECK("initial_dec_delay", out->initial_dec_delay, 0, 65535);
@@ -526,7 +702,7 @@ NvU32 DSC_PpsCalcBpg
 }
 
 /*
- * @brief Calculate slice_bpg_offset, final_offset and scale_increment_interval,
+ * @brief Calculate final_offset and scale_increment_interval,
  *        scale_decrement_interval
  *
  * @param[in/out]   out   DSC output parameter
@@ -541,22 +717,9 @@ DSC_PpsCalcScaleInterval
 )
 {
     NvU32 final_scale;
-    NvU32 groups_total;
-    NvU32 bitsPerPixel = out->bits_per_pixel;
 
-    groups_total = out->groups_per_line * out->slice_height;
-    out->slice_bpg_offset = (((out->rc_model_size - out->initial_offset + out->num_extra_mux_bits) << OFFSET_FRACTIONAL_BITS)
-                + groups_total - 1) / groups_total;
-    RANGE_CHECK("slice_bpg_offset", out->slice_bpg_offset, 0, 65535);
-
-    if ((PIXELS_PER_GROUP * bitsPerPixel << OFFSET_FRACTIONAL_BITS) - (out->slice_bpg_offset + out->nfl_bpg_offset) * BPP_UNIT
-        < (1 + 5 * PIXELS_PER_GROUP) * BPP_UNIT << OFFSET_FRACTIONAL_BITS)
-    {
-        DSC_Print("The bits/pixel allocation for non-first lines is too low (<5.33bpp).");
-        DSC_Print("Consider decreasing FIRST_LINE_BPG_OFFSET.");
-    }
-
-    out->final_offset = out->rc_model_size - (out->initial_xmit_delay * bitsPerPixel + 8)/BPP_UNIT + out->num_extra_mux_bits;
+    out->final_offset = (out->rc_model_size - (out->initial_xmit_delay * out->bits_per_pixel + 8) /
+                         BPP_UNIT + out->num_extra_mux_bits);
     RANGE_CHECK("final_offset", out->final_offset, 0, out->rc_model_size-1); //try increase initial_xmit_delay
 
     final_scale = 8 * out->rc_model_size / (out->rc_model_size - out->final_offset);
@@ -571,7 +734,8 @@ DSC_PpsCalcScaleInterval
         //   for that configuration.
         //
         out->scale_increment_interval = (out->final_offset << OFFSET_FRACTIONAL_BITS) /
-                                        ((final_scale - 9) * (out->nfl_bpg_offset + out->slice_bpg_offset + out->nsl_bpg_offset));
+                                        ((final_scale - 9) * (out->nfl_bpg_offset +
+                                        out->slice_bpg_offset + out->nsl_bpg_offset));
         RANGE_CHECK("scale_increment_interval", out->scale_increment_interval, 0, 65535);
     }
     else
@@ -607,6 +771,9 @@ DSC_PpsCalcRcParam
     NvU32 bpcm8 = out->bits_per_component - 8;
     NvU32 yuv_modifier = out->convert_rgb == 0 && out->dsc_version_minor == 1;
     NvU32 qp_bpc_modifier = bpcm8 * 2 - yuv_modifier;
+    const int ofs_und6[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 };
+    const int ofs_und7[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
+    const int ofs_und10[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
 
     out->flatness_min_qp = 3 + qp_bpc_modifier;
     out->flatness_max_qp = 12 + qp_bpc_modifier;
@@ -620,102 +787,167 @@ DSC_PpsCalcRcParam
     for (i = 0; i < NUM_BUF_RANGES - 1; i++)
         out->rc_buf_thresh[i] = rcBufThresh[i] & (0xFF << 6);
 
-    //if (out->native_420)
-    //    idx = bitsPerPixel/BPP_UNIT - 8;
-    //else if(out->native_422)
-    //    idx = bitsPerPixel/BPP_UNIT - 12;
-    //else
-    idx = (2 * (bitsPerPixel - 6 * BPP_UNIT) ) / BPP_UNIT;
-
-    if (bpcm8 == 0)
+    if (out->native_422)
     {
-        for (i = 0; i < NUM_BUF_RANGES; i++)
+        idx = bitsPerPixel/BPP_UNIT - 12;
+        if (bpcm8 == 0)
         {
-            const NvU32 min = minqp444_8b[i][idx];
-            const NvU32 max = maxqp444_8b[i][idx];
-
-            out->range_min_qp[i] = MAX(0, min - yuv_modifier);
-            out->range_max_qp[i] = MAX(0, max - yuv_modifier);
+            for (i = 0; i < NUM_BUF_RANGES; ++i)
+            {
+                out->range_min_qp[i] = minqp422_8b[i][idx];
+                out->range_max_qp[i] = maxqp422_8b[i][idx];
+            }
         }
-    }
-    else if (bpcm8 == 2)
-    {
-        for (i = 0; i < NUM_BUF_RANGES; i++)
+        else if (bpcm8 == 2)
         {
-            const NvU32 min = minqp444_10b[i][idx];
-            const NvU32 max = maxqp444_10b[i][idx];
+            for (i=0; i < NUM_BUF_RANGES; i++)
+            {
+                out->range_min_qp[i] = minqp422_10b[i][idx];
+                out->range_max_qp[i] = maxqp422_10b[i][idx];
+            }
+        }
+        else
+        {
+            for (i=0; i<NUM_BUF_RANGES; i++)
+            {
+                out->range_min_qp[i] = minqp422_12b[i][idx];
+                out->range_max_qp[i] = maxqp422_12b[i][idx];
+            }
+        }
 
-            out->range_min_qp[i] = MAX(0, min - yuv_modifier);
-            out->range_max_qp[i] = MAX(0, max - yuv_modifier);
+        for (i = 0; i < NUM_BUF_RANGES; ++i)
+        {
+            if (bitsPerPixel <= 12*BPP_UNIT)
+            {
+                out->range_bpg_offset[i] = ofs_und6[i];
+            }
+            else if (bitsPerPixel <= 14*BPP_UNIT)
+            {
+                out->range_bpg_offset[i] = ofs_und6[i] + ((bitsPerPixel - 12*BPP_UNIT) *
+                                           (ofs_und7[i] - ofs_und6[i]) + BPP_UNIT) / (2*BPP_UNIT);
+            }
+            else if (bitsPerPixel <= 16*BPP_UNIT)
+            {
+                out->range_bpg_offset[i] = ofs_und7[i];
+            }
+            else if (bitsPerPixel <= 20*BPP_UNIT)
+            {
+                out->range_bpg_offset[i] = ofs_und7[i] + ((bitsPerPixel - 16*BPP_UNIT) *
+                                           (ofs_und10[i] - ofs_und7[i]) + 2*BPP_UNIT) / (4*BPP_UNIT);
+            }
+            else
+            {
+                out->range_bpg_offset[i] = ofs_und10[i];
+            }
         }
     }
     else
     {
-        for (i = 0; i < NUM_BUF_RANGES; i++)
-        {
-            const NvU32 min = minqp444_12b[i][idx];
-            const NvU32 max = maxqp444_12b[i][idx];
+        idx = (2 * (bitsPerPixel - 6 * BPP_UNIT) ) / BPP_UNIT;
 
-            out->range_min_qp[i] = MAX(0, min - yuv_modifier);
-            out->range_max_qp[i] = MAX(0, max - yuv_modifier);
+        if (bpcm8 == 0)
+        {
+            for (i = 0; i < NUM_BUF_RANGES; i++)
+            {
+                const NvU32 min = minqp444_8b[i][idx];
+                const NvU32 max = maxqp444_8b[i][idx];
+
+                out->range_min_qp[i] = MAX(0, min - yuv_modifier);
+                out->range_max_qp[i] = MAX(0, max - yuv_modifier);
+            }
         }
-    }
-
-    for (i = 0; i < NUM_BUF_RANGES; ++i)
-    {
-        //if (out->native_420)
-        //{
-        //  NvU32 ofs_und4[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 };
-        //  NvU32 ofs_und5[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
-        //  NvU32 ofs_und6[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
-        //  NvU32 ofs_und8[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
-        //  out->range_min_qp[i] = minqp_420[bpcm8 / 2][i][idx];
-        //  out->range_max_qp[i] = maxqp_420[bpcm8 / 2][i][idx];
-        //  if (bitsPerPixel <= 8*BPP_UNIT)
-        //      out->range_bpg_offset[i] = ofs_und4[i];
-        //  else if (bitsPerPixel <= 10*BPP_UNIT)
-        //      out->range_bpg_offset[i] = ofs_und4[i] + (NvU32)(0.5 * (bitsPerPixel - 8.0) * (ofs_und5[i] - ofs_und4[i]) + 0.5);
-        //  else if (bitsPerPixel <= 12*BPP_UNIT)
-        //      out->range_bpg_offset[i] = ofs_und5[i] + (NvU32)(0.5 * (bitsPerPixel - 10.0) * (ofs_und6[i] - ofs_und5[i]) + 0.5);
-        //  else if (bitsPerPixel <= 16*BPP_UNIT)
-        //      out->range_bpg_offset[i] = ofs_und6[i] + (NvU32)(0.25 * (bitsPerPixel - 12.0) * (ofs_und8[i] - ofs_und6[i]) + 0.5);
-        //  else
-        //      out->range_bpg_offset[i] = ofs_und8[i];
-        //}
-        //else if (out->native_422)
-        //{
-        //  NvU32 ofs_und6[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 };
-        //  NvU32 ofs_und7[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
-        //  NvU32 ofs_und10[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
-        //  out->range_min_qp[i] = minqp_422[bpcm8 / 2][i][idx];
-        //  out->range_max_qp[i] = maxqp_422[bpcm8 / 2][i][idx];
-        //  if (bitsPerPixel <= 12*BPP_UNIT)
-        //      out->range_bpg_offset[i] = ofs_und6[i];
-        //  else if(bitsPerPixel <= 14*BPP_UNIT)
-        //      out->range_bpg_offset[i] = ofs_und6[i] + (NvU32)((bitsPerPixel - 12.0) * (ofs_und7[i] - ofs_und6[i]) / 2.0 + 0.5);
-        //  else if(bitsPerPixel <= 16*BPP_UNIT)
-        //      out->range_bpg_offset[i] = ofs_und7[i];
-        //  else if(bitsPerPixel <= 20*BPP_UNIT)
-        //      out->range_bpg_offset[i] = ofs_und7[i] + (NvU32)((bitsPerPixel - 16.0) * (ofs_und10[i] - ofs_und7[i]) / 4.0 + 0.5);
-        //  else
-        //      out->range_bpg_offset[i] = ofs_und10[i];
-        //}
-        //else
+        else if (bpcm8 == 2)
         {
-            const NvU32 ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 };
-            const NvU32 ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
-            const NvU32 ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
-            const NvU32 ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
-            if (bitsPerPixel <= 6 * BPP_UNIT)
-                out->range_bpg_offset[i] = ofs_und6[i];
-            else if (bitsPerPixel <= 8 * BPP_UNIT)
-                out->range_bpg_offset[i] = ofs_und6[i] + ((bitsPerPixel - 6 * BPP_UNIT) * (ofs_und8[i] - ofs_und6[i]) + BPP_UNIT) / (2 * BPP_UNIT);
-            else if (bitsPerPixel <= 12 * BPP_UNIT)
-                out->range_bpg_offset[i] = ofs_und8[i];
-            else if (bitsPerPixel <= 15 * BPP_UNIT)
-                out->range_bpg_offset[i] = ofs_und12[i] + ((bitsPerPixel - 12 * BPP_UNIT) * (ofs_und15[i] - ofs_und12[i]) + 3 * BPP_UNIT / 2) / (3 * BPP_UNIT);
-            else
-                out->range_bpg_offset[i] = ofs_und15[i];
+            for (i = 0; i < NUM_BUF_RANGES; i++)
+            {
+                const NvU32 min = minqp444_10b[i][idx];
+                const NvU32 max = maxqp444_10b[i][idx];
+
+                out->range_min_qp[i] = MAX(0, min - yuv_modifier);
+                out->range_max_qp[i] = MAX(0, max - yuv_modifier);
+            }
+        }
+        else
+        {
+            for (i = 0; i < NUM_BUF_RANGES; i++)
+            {
+                const NvU32 min = minqp444_12b[i][idx];
+                const NvU32 max = maxqp444_12b[i][idx];
+
+                out->range_min_qp[i] = MAX(0, min - yuv_modifier);
+                out->range_max_qp[i] = MAX(0, max - yuv_modifier);
+            }
+        }
+
+        for (i = 0; i < NUM_BUF_RANGES; ++i)
+        {
+            //if (out->native_420)
+            //{
+            //  NvU32 ofs_und4[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 };
+            //  NvU32 ofs_und5[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
+            //  NvU32 ofs_und6[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
+            //  NvU32 ofs_und8[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
+            //  out->range_min_qp[i] = minqp_420[bpcm8 / 2][i][idx];
+            //  out->range_max_qp[i] = maxqp_420[bpcm8 / 2][i][idx];
+            //  if (bitsPerPixel <= 8*BPP_UNIT)
+            //      out->range_bpg_offset[i] = ofs_und4[i];
+            //  else if (bitsPerPixel <= 10*BPP_UNIT)
+            //      out->range_bpg_offset[i] = ofs_und4[i] + (NvU32)(0.5 * (bitsPerPixel - 8.0) * (ofs_und5[i] - ofs_und4[i]) + 0.5);
+            //  else if (bitsPerPixel <= 12*BPP_UNIT)
+            //      out->range_bpg_offset[i] = ofs_und5[i] + (NvU32)(0.5 * (bitsPerPixel - 10.0) * (ofs_und6[i] - ofs_und5[i]) + 0.5);
+            //  else if (bitsPerPixel <= 16*BPP_UNIT)
+            //      out->range_bpg_offset[i] = ofs_und6[i] + (NvU32)(0.25 * (bitsPerPixel - 12.0) * (ofs_und8[i] - ofs_und6[i]) + 0.5);
+            //  else
+            //      out->range_bpg_offset[i] = ofs_und8[i];
+            //}
+            //else if (out->native_422)
+            //{
+            //  NvU32 ofs_und6[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 };
+            //  NvU32 ofs_und7[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
+            //  NvU32 ofs_und10[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
+            //  out->range_min_qp[i] = minqp_422[bpcm8 / 2][i][idx];
+            //  out->range_max_qp[i] = maxqp_422[bpcm8 / 2][i][idx];
+            //  if (bitsPerPixel <= 12*BPP_UNIT)
+            //      out->range_bpg_offset[i] = ofs_und6[i];
+            //  else if(bitsPerPixel <= 14*BPP_UNIT)
+            //      out->range_bpg_offset[i] = ofs_und6[i] + (NvU32)((bitsPerPixel - 12.0) * (ofs_und7[i] - ofs_und6[i]) / 2.0 + 0.5);
+            //  else if(bitsPerPixel <= 16*BPP_UNIT)
+            //      out->range_bpg_offset[i] = ofs_und7[i];
+            //  else if(bitsPerPixel <= 20*BPP_UNIT)
+            //      out->range_bpg_offset[i] = ofs_und7[i] + (NvU32)((bitsPerPixel - 16.0) * (ofs_und10[i] - ofs_und7[i]) / 4.0 + 0.5);
+            //  else
+            //      out->range_bpg_offset[i] = ofs_und10[i];
+            //}
+            //else
+            {
+                const NvU32 ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 };
+                const NvU32 ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
+                const NvU32 ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
+                const NvU32 ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
+
+                if (bitsPerPixel <= 6 * BPP_UNIT)
+                {
+                    out->range_bpg_offset[i] = ofs_und6[i];
+                }
+                else if (bitsPerPixel <= 8 * BPP_UNIT)
+                {
+                    out->range_bpg_offset[i] = ofs_und6[i] + ((bitsPerPixel - 6 * BPP_UNIT) *
+                                               (ofs_und8[i] - ofs_und6[i]) + BPP_UNIT) / (2 * BPP_UNIT);
+                }
+                else if (bitsPerPixel <= 12 * BPP_UNIT)
+                {
+                    out->range_bpg_offset[i] = ofs_und8[i];
+                }
+                else if (bitsPerPixel <= 15 * BPP_UNIT)
+                {
+                    out->range_bpg_offset[i] = ofs_und12[i] + ((bitsPerPixel - 12 * BPP_UNIT) *
+                                               (ofs_und15[i] - ofs_und12[i]) + 3 * BPP_UNIT / 2) / (3 * BPP_UNIT);
+                }
+                else
+                {
+                    out->range_bpg_offset[i] = ofs_und15[i];
+                }
+            }
         }
     }
     return NVT_STATUS_SUCCESS;
@@ -1155,6 +1387,11 @@ DSC_PpsCalcSliceParams
 
         out->slice_width = (out->pic_width + out->slice_num - 1) / out->slice_num;
 
+        if (out->native_420 || out->native_422)
+        {
+            out->slice_width = (out->slice_width+1)/2 * 2 ;
+        }
+
         if (out->slice_width > max_slice_width)
         {
             DSC_Print("Slice width corresponding to the requested slice count is not supported\n");
@@ -1934,13 +2171,7 @@ DSC_GeneratePPS
     if (*pBitsPerPixelX16 != 0)
     {
         *pBitsPerPixelX16 = DSC_AlignDownForBppPrecision(*pBitsPerPixelX16, pDscInfo->sinkCaps.bitsPerPixelPrecision);
-
-        // The calculation of in->bits_per_pixel here in PPSlib, which is the maximum bpp that is allowed by available bandwidth, 
-        // which is applicable to DP alone and not to HDMI FRL. 
-        // Before calling PPS lib to generate PPS data, HDMI library has done calculation according to HDMI2.1 spec 
-        // to determine if FRL rate is sufficient for the requested bpp. So restricting the condition to DP alone.
-        if ((pWARData && (pWARData->connectorType == DSC_DP)) &&
-            (*pBitsPerPixelX16 > in->bits_per_pixel))
+        if (*pBitsPerPixelX16 > in->bits_per_pixel)
         {
             DSC_Print("ERROR - Invalid bits per pixel value specified.");
             ret = NVT_STATUS_INVALID_PARAMETER;
@@ -2009,6 +2240,36 @@ DSC_GeneratePPS
     in->slice_count_mask = pDscInfo->sinkCaps.sliceCountSupportedMask;
     in->peak_throughput_mode0 = pDscInfo->sinkCaps.peakThroughputMode0;
     in->peak_throughput_mode1 = pDscInfo->sinkCaps.peakThroughputMode1;
+    
+    if (in->native_422)
+    {
+        if (in->dsc_version_minor == 1)
+        {
+            DSC_Print("Error! DSC1.1 can't support native422!\n");
+            ret = NVT_STATUS_INVALID_PARAMETER;
+            goto done;
+        }
+        //the bpp in native 422 mode is doubled.
+        if((((NvS32)(in->bits_per_pixel)) < (NvS32)(2*6*BPP_UNIT)) ||
+           (((NvS32)(in->bits_per_pixel)) > (NvS32)(2*32*BPP_UNIT-1)))
+        {
+            DSC_Print("bits_per_pixelx16 (=%u) needs to be between %u and %u",
+                      in->bits_per_pixel, 2*6*BPP_UNIT, 2*32*BPP_UNIT-1);
+            ret = NVT_STATUS_INVALID_PARAMETER;
+            goto done;
+        }
+    }
+    else
+    {
+        if ((((NvS32)(in->bits_per_pixel)) < (NvS32)(8*BPP_UNIT)) ||
+            (((NvS32)(in->bits_per_pixel)) > (NvS32)(32*BPP_UNIT)))
+        {
+            DSC_Print("bits_per_pixelx16 (=%u) needs to be between %u and %u",
+                      in->bits_per_pixel, 8*BPP_UNIT, 32*BPP_UNIT);
+            ret = NVT_STATUS_INVALID_PARAMETER;
+            goto done;
+        }
+    }
 
     ret = DSC_PpsDataGen(in, pps);
 

src/common/modeset/timing/nvt_edidext_861.c

@@ -2871,6 +2871,7 @@ void parseEdidHdmiForumVSDB(VSDB_DATA *pVsdb, NVT_HDMI_FORUM_INFO *pHdmiInfo)
             pHdmiInfo->cnmvrr               = pHdmiForum->CNMVRR;
             pHdmiInfo->cinemaVrr            = pHdmiForum->CinemaVRR;
             pHdmiInfo->m_delta              = pHdmiForum->M_delta;
+            pHdmiInfo->fapa_end_extended    = pHdmiForum->FAPA_End_Extended;
             
             // sixth byte
             if (!remainingSize--)

src/common/modeset/timing/nvtiming.h

@@ -304,6 +304,7 @@ typedef enum NVT_TIMING_TYPE
     NVT_TYPE_DISPLAYID_8,                             // DisplayID 2.0 enumerated timing - Type VIII
     NVT_TYPE_DISPLAYID_9,                             // DisplayID 2.0 formula-based timing - Type IX
     NVT_TYPE_DISPLAYID_10,                            // DisplayID 2.0 formula-based timing - Type X
+    NVT_TYPE_CVT_RB_3,                                // CVT timing with reduced blanking V3
 }NVT_TIMING_TYPE;
 //
 // 5. the timing sequence number like the TV format and EIA861B predefined timing format
@@ -357,6 +358,7 @@ typedef enum NVT_TV_FORMAT
 #define NVT_STATUS_CVT                       NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT, 0)        // CVT timing with regular blanking
 #define NVT_STATUS_CVT_RB                    NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB,  0)    // CVT_RB timing
 #define NVT_STATUS_CVT_RB_2                  NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB_2,  0)  // CVT_RB timing V2
+#define NVT_STATUS_CVT_RB_3                  NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB_3,  0)  // CVT_RB timing V3
 #define NVT_STATUS_CUST                      NVT_DEF_TIMING_STATUS(NVT_TYPE_CUST,    0)    // Customized timing
 #define NVT_STATUS_EDID_DTD                  NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_DTD, 0)
 #define NVT_STATUS_EDID_STD                  NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_STD, 0)
@@ -2081,6 +2083,7 @@ typedef struct tagNVT_HDMI_LLC_INFO
 typedef struct tagNVT_HDMI_FORUM_INFO
 {
     NvU8 max_TMDS_char_rate;
+
     NvU8 threeD_Osd_Disparity       :  1;
     NvU8 dual_view                  :  1;
     NvU8 independent_View           :  1;
@@ -2089,29 +2092,40 @@ typedef struct tagNVT_HDMI_FORUM_INFO
     NvU8 cable_status               :  1;
     NvU8 rr_capable                 :  1;
     NvU8 scdc_present               :  1;
+
     NvU8 dc_30bit_420               :  1;
     NvU8 dc_36bit_420               :  1;
     NvU8 dc_48bit_420               :  1;
     NvU8 uhd_vic                    :  1;
     NvU8 max_FRL_Rate               :  4;
+
     NvU8 fapa_start_location        :  1;
     NvU8 allm                       :  1;
     NvU8 fva                        :  1;
     NvU8 cnmvrr                     :  1;
     NvU8 cinemaVrr                  :  1;
     NvU8 m_delta                    :  1;
-    NvU8 vrr_min                    :  6;
+    NvU8 fapa_end_extended          :  1;
+    NvU8 rsvd                       :  1;
+
+    NvU16 vrr_min                   :  6;
     NvU16 vrr_max                   : 10;
+
+    NvU16 dsc_MaxSlices             :  6;    
+    NvU16 dsc_MaxPclkPerSliceMHz    : 10;
+
     NvU8 dsc_10bpc                  :  1;
     NvU8 dsc_12bpc                  :  1;
     NvU8 dsc_16bpc                  :  1;
     NvU8 dsc_All_bpp                :  1;
+    NvU8 dsc_Max_FRL_Rate           :  4;
+
     NvU8 dsc_Native_420             :  1;
     NvU8 dsc_1p2                    :  1;
-    NvU8 dsc_MaxSlices              :  6;
-    NvU16 dsc_MaxPclkPerSliceMHz    : 10;
-    NvU8 dsc_Max_FRL_Rate           :  4;
+    NvU8 rsvd_2                     :  6;
+
     NvU8 dsc_totalChunkKBytes       :  7; // = 1 + EDID reported DSC_TotalChunkKBytes
+    NvU8 rsvd_3                     :  1;
 
 } NVT_HDMI_FORUM_INFO;
 
@@ -2785,10 +2799,6 @@ typedef struct tagNVT_SPD_INFOFRAME_PAYLOAD
     NvU8 productBytes[16];
 
     NvU8 sourceInformation;
-    
-    // Since HDMI Library doesn't clear the rest of the bytes and checksum is calculated for all the 32 bytes : Temporary WAR
-    NvU8 paddingBytes[3];
-
 
 } NVT_SPD_INFOFRAME_PAYLOAD;
 
@@ -3720,7 +3730,9 @@ typedef struct tagNVT_HDMI_FORUM_VSDB_PAYLOAD
     NvU8    CNMVRR                  : 1;
     NvU8    CinemaVRR               : 1;
     NvU8    M_delta                 : 1;
-    NvU8    Rsvd_2                  : 2;
+    NvU8    Rsvd_2                  : 1;
+    NvU8    FAPA_End_Extended       : 1;
+
     // sixth byte
     NvU8    VRR_min                 : 6;
     NvU8    VRR_max_high            : 2;
@@ -5253,6 +5265,7 @@ NVT_STATUS NvTiming_CalcDMT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag,
 NVT_STATUS NvTiming_CalcCVT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT);
 NVT_STATUS NvTiming_CalcCVT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT);
 NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is1000div1001, NVT_TIMING *pT);
+NVT_STATUS NvTiming_CalcCVT_RB3(NvU32 width, NvU32 height, NvU32 rr, NvU32 deltaHBlank, NvU32 vBlankMicroSec, NvBool isEarlyVSync, NVT_TIMING *pT);
 NvBool NvTiming_IsTimingCVTRB(const NVT_TIMING *pTiming);
 
 // CEA/EIA/Psf timing

src/common/nvlink/interface/nvlink.h

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2014-2022 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 //
 //     nvlink.h
@@ -72,6 +71,7 @@ extern "C" {
 #define NVLINK_TRANSITION_OFF_TIMEOUT        1
 #define NVLINK_TRANSITION_SAFE_TIMEOUT       300
 #define NVLINK_TRANSITION_HS_TIMEOUT         8000
+#define NVLINK_TRANSITION_ACTIVE_PENDING     2000
 #define NVLINK_TRANSITION_POST_HS_TIMEOUT    70
 
 // Link training seed values
@@ -109,9 +109,17 @@ struct nvlink_device
     NvU64  type;
     NvBool initialized;
 
+    // Training type: ALI or Non-ALI
+    NvBool enableALI;
+
     // fabric node id
     NvU16  nodeId;
 
+    // per Ioctrl data
+    NvU32 numIoctrls;
+    NvU32 numLinksPerIoctrl;
+    NvU32 numActiveLinksPerIoctrl;
+
     // Client private information
     void *pDevInfo;
 };
@@ -249,6 +257,7 @@ struct nvlink_link_handlers
     NV_API_CALL NvlStatus (*read_discovery_token)       (struct nvlink_link *link, NvU64 *token);
     NV_API_CALL void      (*training_complete)          (struct nvlink_link *link);
     NV_API_CALL void      (*get_uphy_load)              (struct nvlink_link *link, NvBool* bUnlocked);
+    NV_API_CALL NvlStatus (*ali_training)               (struct nvlink_link *link);
 };
 
 //
@@ -318,11 +327,15 @@ typedef struct nvlink_inband_data      nvlink_inband_data;
 #define NVLINK_LINKSTATE_DISABLE_HEARTBEAT              0x18   // Disables the heartbeat errors
 #define NVLINK_LINKSTATE_CONTAIN                        0x19   // TL is in contain mode
 #define NVLINK_LINKSTATE_INITTL                         0x1A   // INITTL
+#define NVLINK_LINKSTATE_INITPHASE5                     0x1B   // INITPHASE5
+#define NVLINK_LINKSTATE_ALI                            0x1C   // ALI
+#define NVLINK_LINKSTATE_ACTIVE_PENDING                 0x1D   // Intermediate state for a link going to active
 #define NVLINK_LINKSTATE_INVALID                        0xFF   // Invalid state
 
 // NVLINK TX SUBLINK states
 #define NVLINK_SUBLINK_STATE_TX_HS                      0x0   // TX High Speed
 #define NVLINK_SUBLINK_STATE_TX_SINGLE_LANE             0x4   // TX Single Lane (1/8th or 1/4th) Mode (Deprecated)
+#define NVLINK_SUBLINK_STATE_TX_LOW_POWER               0x4   // TX Single Lane Mode / L1
 #define NVLINK_SUBLINK_STATE_TX_TRAIN                   0x5   // TX training
 #define NVLINK_SUBLINK_STATE_TX_SAFE                    0x6   // TX Safe Mode
 #define NVLINK_SUBLINK_STATE_TX_OFF                     0x7   // TX OFF
@@ -336,6 +349,7 @@ typedef struct nvlink_inband_data      nvlink_inband_data;
 // NVLINK RX SUBLINK states
 #define NVLINK_SUBLINK_STATE_RX_HS                      0x0   // RX High Speed
 #define NVLINK_SUBLINK_STATE_RX_SINGLE_LANE             0x4   // RX Single Lane (1/8th or 1/4th) Mode (Deprecated)
+#define NVLINK_SUBLINK_STATE_RX_LOW_POWER               0x4   // RX Single Lane Mode / L1
 #define NVLINK_SUBLINK_STATE_RX_TRAIN                   0x5   // RX training
 #define NVLINK_SUBLINK_STATE_RX_SAFE                    0x6   // RX Safe Mode
 #define NVLINK_SUBLINK_STATE_RX_OFF                     0x7   // RX OFF
@@ -426,6 +440,15 @@ NvlStatus nvlink_lib_set_link_master(nvlink_link *link);
  */
 NvlStatus nvlink_lib_get_link_master(nvlink_link *link, nvlink_link **master);
 
+/*
+ * Set the training state for the given link as non-ALI or ALI
+ */
+NvlStatus nvlink_lib_is_link_using_ALI(nvlink_link *link, NvBool *usingALI);
+
+/*
+ * Set the training state for the given link as non-ALI or ALI
+ */
+NvlStatus nvlink_lib_link_set_training_mode(nvlink_link *link, NvBool enableALI);
 /************************************************************************************************/
 /*************************** NVLink topology discovery functions ********************************/
 /************************************************************************************************/
@@ -508,6 +531,7 @@ void nvlink_lib_restore_training_seeds(nvlink_link * link,
 NvlStatus nvlink_lib_check_training_complete(nvlink_link **links,
                                              NvU32 linkCount);
 
+
 /************************************************************************************************/
 /********************************** NVLink shutdown functions ***********************************/
 /************************************************************************************************/
@@ -542,21 +566,26 @@ NvlStatus nvlink_lib_reset_links(nvlink_link **links,
                                  NvU32         numLinks,
                                  NvU32         flags);
 
+/*
+ * Floorsweep the necessary links and set buffer ready on the active links
+ */
+NvlStatus nvlink_lib_powerdown_floorswept_links_to_off(nvlink_device *pDevice);
+
 
 /*
  * Nvlink core library structure iterators
  */
 
-#define FOR_EACH_DEVICE_REGISTERED(dev, head, node)                \
+#define FOR_EACH_DEVICE_REGISTERED(dev, head, node)  \
         nvListForEachEntry(dev, &head.node, node)
 
-#define FOR_EACH_LINK_REGISTERED(link, dev, node)                  \
+#define FOR_EACH_LINK_REGISTERED(link, dev, node)    \
         nvListForEachEntry(link, &dev->link_list, node)
 
 #define FOR_EACH_LINK_REGISTERED_SAFE(link, next, dev, node)       \
         nvListForEachEntry_safe(link, next, &dev->link_list, node)
 
-#define FOR_EACH_CONNECTION(conn, head, node)                      \
+#define FOR_EACH_CONNECTION(conn, head, node)        \
         nvListForEachEntry(conn, &head.node, node)
 
 #ifdef __cplusplus

src/common/nvlink/interface/nvlink_common.h

@@ -69,6 +69,7 @@ struct nvlink_detailed_device_info
     NvU64       deviceType;
     NvU8       *devUuid;
     NvBool      bInitialized;
+    NvBool      bEnableALI;
     void       *dev_info;     // Endpoint driver device info opaque
                               // to core lib. Passed from end point
                               // driver to core

src/common/nvlink/interface/nvlink_lib_ctrl.h

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2016-2022 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #ifndef _NVLINK_LIB_CTRL_H_
 #define _NVLINK_LIB_CTRL_H_
@@ -30,7 +29,7 @@
 /* List of supported capability type */
 #define NVLINK_CAP_FABRIC_MANAGEMENT 0
 
-/*
+/* 
  * Max supported capabilities count
  *
  */
@@ -62,7 +61,7 @@
 
 /*
  * Total number of nvlink endpoints core library can have
- *  This is mapped to NVLINK_MAX_SYSTEM_LINK_NUM in drivers/nvlink/interface/nvlink.h
+ *  This is mapped to NVLINK_MAX_SYSTEM_LINK_NUM in drivers/nvlink/interface/nvlink.h 
  */
 #define NVLINK_MAX_NVLINK_ENDPOINTS 624
 
@@ -90,7 +89,7 @@ typedef struct
 typedef struct
 {
     NvU16               nodeId;
-    NvU32               linkIndex;
+    NvU16               linkIndex;
     nvlink_pci_dev_info pciInfo;
 } nvlink_endpoint;
 
@@ -110,13 +109,15 @@ typedef struct
     NvU16               numLinks;
     NvU32               devType;
     NV_DECLARE_ALIGNED(NvU64 enabledLinkMask, 8);
+    NvBool              bEnableAli;
+    /* See struct definition modification guidelines at the top of this file */
 } nvlink_detailed_dev_info;
 
 /* detailed information about a remote nvlink connection endpoint */
 typedef struct
 {
     NvU16               nodeId;
-    NvU32               linkIndex;
+    NvU16               linkIndex;
     nvlink_pci_dev_info pciInfo;
     NvU8                devUuid[NVLINK_UUID_LEN];
     NvU32               devType;
@@ -188,9 +189,9 @@ typedef enum
 /* link and sublink state of an nvlink endpoint */
 typedef struct
 {
-    NvU32 linkMode;
-    NvU32 txSubLinkMode;
-    NvU32 rxSubLinkMode;
+    NvU8 linkMode;
+    NvU8 txSubLinkMode;
+    NvU8 rxSubLinkMode;
 } nvlink_link_state;
 
 /*
@@ -353,7 +354,7 @@ typedef struct
  */
 typedef struct
 {
-    NvU32  linkIndex;
+    NvU16  linkIndex;
     NvBool initStatus;
 } nvlink_link_init_status;
 
@@ -502,7 +503,7 @@ typedef struct
  */
 typedef struct
 {
-    NvU32 linkIndex;
+    NvU16 linkIndex;
     NV_DECLARE_ALIGNED(NvU64 tokenValue, 8);
 } nvlink_token_info;
 
@@ -586,6 +587,7 @@ typedef enum
     nvlink_train_conn_to_off,
     nvlink_train_conn_active_to_swcfg,
     nvlink_train_conn_swcfg_to_off,
+    /* See enum modification guidelines at the top of this file */
 } nvlink_conn_train_type;
 
 typedef struct
@@ -1075,7 +1077,7 @@ typedef struct
 } nvlink_initphase5;
 
 /*
- * CTRL_NVLINK_GET_DEVICE_LINKS_STATE
+ * CTRL_NVLINK_GET_DEVICE_LINK_STATES
  *
  * Returns the link state of all enabled links on a given device.
  *
@@ -1109,6 +1111,11 @@ typedef struct
     NvU32                  endStatesCount;
 } nvlink_get_device_link_states;
 
+/* 
+ * Note: Verify that new parameter structs for IOCTLs satisfy 
+ *       sizing restrictions for all OSs they could be used in.
+ */ 
+
 #define CTRL_NVLINK_CHECK_VERSION                            0x01
 #define CTRL_NVLINK_SET_NODE_ID                              0x02
 #define CTRL_NVLINK_SET_TX_COMMON_MODE                       0x03

src/common/nvlink/interface/nvlink_lock.h

@@ -1,25 +1,21 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2020 NVidia Corporation
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 
 #ifndef _NVLINK_LOCK_H_

src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"
@@ -392,7 +391,9 @@ nvlink_core_check_intranode_conn_state
             if ((nvlink_core_check_link_state(conn->end0, NVLINK_LINKSTATE_HS)) &&
                 (nvlink_core_check_link_state(conn->end1, NVLINK_LINKSTATE_HS)))
             {
-                if (!((nvlink_core_check_tx_sublink_state(conn->end0,
+                // In NVLINK4.0, corelib doesn't control sublink state transitions
+                if (conn->end0->version < NVLINK_DEVICE_VERSION_40 &&
+                    !((nvlink_core_check_tx_sublink_state(conn->end0,
                                                          NVLINK_SUBLINK_STATE_TX_HS)) &&
                       (nvlink_core_check_tx_sublink_state(conn->end1,
                                                          NVLINK_SUBLINK_STATE_TX_HS)) &&
@@ -455,6 +456,16 @@ nvlink_core_check_intranode_conn_state
 
             return NVL_ERR_GENERIC;
         }
+        case NVLINK_LINKSTATE_ACTIVE_PENDING:
+        {
+            // Check if both ends of connection are already in ACTIVE_PENDING
+            if ((nvlink_core_check_link_state(conn->end0, NVLINK_LINKSTATE_ACTIVE_PENDING)) &&
+                (nvlink_core_check_link_state(conn->end1, NVLINK_LINKSTATE_ACTIVE_PENDING)))
+            {
+                return NVL_SUCCESS;
+            }
+            break;
+        }
     }
 
     return NVL_SUCCESS;

src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"
@@ -85,6 +84,15 @@ nvlink_core_discover_and_get_remote_end
                     pLinks[linkCount++] = link;
                 }
             }
+
+            if (pLinks[0]->version >= NVLINK_DEVICE_VERSION_40)
+            {
+                if (!pLinks[0]->dev->enableALI)
+                {
+                    nvlink_core_init_links_from_off_to_swcfg_non_ALI(pLinks, linkCount, flags);
+                }
+            }
+            else
             {
                 nvlink_core_init_links_from_off_to_swcfg(pLinks, linkCount, flags);
             }
@@ -216,11 +224,12 @@ _nvlink_core_discover_topology(void)
                         isTokenFound = NV_TRUE;
 
                         //
-                        // If R4 tokens were used for NVLink3.0+, then mark initnegotiate
-                        // passed, since ALT training won't get kicked off without it.
+                        // If a token is found mark bInitnegotiateConfigGood as
+                        // True since we can only finish off discovery if
+                        // INITNEGOTIATE has finished in order to get topology info from
+                        // MINION
                         //
-                        if ((end0->version >= NVLINK_DEVICE_VERSION_30) &&
-                            ((end0->localSid == 0) || (end0->remoteSid == 0)))
+                        if ((end0->version >= NVLINK_DEVICE_VERSION_30))
                         {
                             end0->bInitnegotiateConfigGood = NV_TRUE;
                             end1->bInitnegotiateConfigGood = NV_TRUE;

src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2021 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"
@@ -255,6 +254,294 @@ nvlink_core_init_links_from_off_to_swcfg
     nvlink_core_initnegotiate(pLinks, numLinks, flags);
 }
 
+/**
+ * Initialize all the endpoints from OFF to SWCFG state
+ * Used for NvLink 4.0+
+ *
+ * @param[in]  links    Array of link endpoints to initialize
+ * @param[in]  numLinks Number of links in the array
+ * @param[in]  flags    Flags to determine whether init is sync/async
+ */
+void
+nvlink_core_init_links_from_off_to_swcfg_non_ALI
+(
+    nvlink_link **pLinks,
+    NvU32         numLinks,
+    NvU32         flags
+)
+{
+    NvlStatus  status = NVL_SUCCESS;
+    NvU64      linkMode;
+    NvU32      i;
+
+    // Sanity check the links array
+    nvlink_assert(pLinks != NULL);
+
+    // Return early if there are no links to initialize
+    if (numLinks == 0)
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+            "%s: No links to initialize\n",
+            __FUNCTION__));
+        return;
+    }
+
+    // Step 1: Perform INITPHASE1 on all endpoints
+    nvlink_core_initphase1(pLinks, numLinks, flags);
+
+    // Get state on all links. This ensures NVLINK_LINKSTATE_INITPHASE1 completes
+    if (flags == NVLINK_STATE_CHANGE_ASYNC)
+    {
+        for (i = 0; i < numLinks; i++)
+        {
+            status = pLinks[i]->link_handlers->get_dl_link_mode(pLinks[i], &linkMode);
+            if ((status != NVL_SUCCESS) ||
+                (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT))
+            {
+                NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+                    "%s: Link %s:%s is in bad state\n",
+                    __FUNCTION__, pLinks[i]->dev->deviceName, pLinks[i]->linkName));
+            }
+        }
+    }
+    
+    // Step 2 RECEIVER DETECT :Perform receiver detect on all the endpoints
+    nvlink_core_set_rx_detect(pLinks, numLinks, flags);
+
+    // Get state on all links. This ensures receiver detect command completes
+    if (flags == NVLINK_STATE_CHANGE_ASYNC)
+    {
+        for (i = 0; i < numLinks; i++)
+        {
+            // In NVLink3.0 and 3.1, RXDET must be called serially - done above (Bug 2546220)
+            if (!((pLinks[i]->version == NVLINK_DEVICE_VERSION_30) ||
+                  (pLinks[i]->version == NVLINK_DEVICE_VERSION_31)))
+            {
+                // If receiver detect has passed for the link, move to next link
+                if (pLinks[i]->bRxDetected)
+                    continue;
+
+                status = pLinks[i]->link_handlers->get_dl_link_mode(pLinks[i], &linkMode);
+                if ((status != NVL_SUCCESS) ||
+                    (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT))
+                {
+                    NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+                        "%s: Link %s:%s is in bad state\n",
+                        __FUNCTION__, pLinks[i]->dev->deviceName, pLinks[i]->linkName));
+                }
+            }
+        }
+    }
+
+    // Step 2.1 RECEIVER DETECT :Poll for output of receiver detect on all the endpoints
+    nvlink_core_get_rx_detect(pLinks, numLinks, flags);
+
+
+    /***************** Receiver Detect is completed at this point ****************/
+    /***************** Proceed with the link initialization steps ****************/
+
+    // Step 3: Enable Common mode on all Tx's
+    nvlink_core_enable_common_mode(pLinks, numLinks, flags);
+
+    // Get state on all links. This ensures NVLINK_SUBLINK_STATE_TX_COMMON_MODE completes
+    if (flags == NVLINK_STATE_CHANGE_ASYNC)
+    {
+        for (i = 0; i < numLinks; i++)
+        {
+            // If receiver detect failed for the link, move to next link
+            if (!pLinks[i]->bRxDetected || pLinks[i]->bTxCommonModeFail)
+                continue;
+
+            status = pLinks[i]->link_handlers->get_dl_link_mode(pLinks[i], &linkMode);
+            if ((status != NVL_SUCCESS) ||
+                (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT))
+            {
+                NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+                    "%s: Link %s:%s is in bad state\n",
+                    __FUNCTION__, pLinks[i]->dev->deviceName, pLinks[i]->linkName));
+            }
+        }
+    }
+
+    // Step 4: call INITPHASE5
+    nvlink_core_initphase5(pLinks, numLinks, flags);
+
+    // Get state on all links. This ensures NVLINK_SUBLINK_STATE_TX_DATA_READY completes
+    if (flags == NVLINK_STATE_CHANGE_ASYNC)
+    {
+        for (i = 0; i < numLinks; i++)
+        {
+            // If receiver detect failed for the link, move to next link
+            if (!pLinks[i]->bRxDetected || pLinks[i]->bTxCommonModeFail || pLinks[i]->bInitphase5Fails)
+                continue;
+
+            status = pLinks[i]->link_handlers->get_dl_link_mode(pLinks[i], &linkMode);
+            if ((status != NVL_SUCCESS) ||
+                (linkMode == NVLINK_LINKSTATE_FAIL) || (linkMode == NVLINK_LINKSTATE_FAULT))
+            {
+                NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+                    "%s: Link %s:%s is in bad state\n",
+                    __FUNCTION__, pLinks[i]->dev->deviceName, pLinks[i]->linkName));
+            }
+        }
+    }
+
+    // Step 5: Put the links in SAFE mode
+    for (i = 0; i < numLinks; i++)
+    {
+        // If receiver detect failed for the link, move to next link
+        if (!pLinks[i]->bRxDetected || pLinks[i]->bTxCommonModeFail || pLinks[i]->bInitphase5Fails)
+            continue;
+
+        linkMode = 0;
+        if (pLinks[i]->link_handlers->get_dl_link_mode(pLinks[i], &linkMode))
+        {
+            NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+                "%s: Unable to get link mode for %s:%s",
+                __FUNCTION__, pLinks[i]->dev->deviceName, pLinks[i]->linkName));
+        }
+
+        if ((linkMode != NVLINK_LINKSTATE_SAFE) && (linkMode != NVLINK_LINKSTATE_HS))
+        {
+            // Check if the link has reached failed state
+            if (pLinks[i]->state == NVLINK_LINKSTATE_FAIL)
+            {
+                NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO,
+                    "%s:%s marked as failed.\n",
+                    pLinks[i]->dev->deviceName, pLinks[i]->linkName));
+                continue;
+            }
+
+            //
+            // Check if number of attempts to put the link into
+            // safe state has already exceeded the maximum number
+            // of retries. If yes, mark the link as failed
+            //
+            // On NVLink3.0, we don't support retraining in the driver.
+            // However MODS test 252 (on NVL3+ specifically)  will train 
+            // HS->OFF->HS many times. This check causes RM to stop
+            // training after NVLINK_MAX_NUM_SAFE_RETRIES times
+            //
+            if ((pLinks[i]->safe_retries > NVLINK_MAX_NUM_SAFE_RETRIES) &&
+                (pLinks[i]->version < NVLINK_DEVICE_VERSION_30))
+            {
+                NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO,
+                    "Max safe mode retries reached for %s:%s. Marking it as failed.\n",
+
+                pLinks[i]->dev->deviceName, pLinks[i]->linkName));
+                pLinks[i]->state = NVLINK_LINKSTATE_FAIL;
+                continue;
+            }
+
+            // Put the link in safe state and increment the retry count
+            pLinks[i]->link_handlers->set_dl_link_mode(pLinks[i], NVLINK_LINKSTATE_SAFE, flags);
+            pLinks[i]->safe_retries++;
+        }
+    }
+
+    // Poll for links to enter SAFE mode
+    for (i = 0; i < numLinks; i++)
+    {
+        status = nvlink_core_wait_for_link_init(pLinks[i]);
+        if (status == NVL_SUCCESS)
+        {
+            pLinks[i]->powerStateTransitionStatus = nvlink_power_state_in_L0;
+        }
+    }
+
+    // Send INITNEGOTIATE to all the links
+    nvlink_core_initnegotiate(pLinks, numLinks, flags);
+}
+
+/**
+ * Kick-off INITPHASE5 on the given array of links
+ *
+ * @param[in]  links     Array of nvlink_link pointers
+ * @param[in]  numLinks  Number of links in the array
+ * @param[in]  flags     Flags - Async/Sync
+ *
+ * return NvlStatus
+ */
+NvlStatus
+nvlink_core_initphase5
+(
+    nvlink_link **links,
+    NvU32         numLinks,
+    NvU32         flags
+)
+{
+    NvU32 i;
+
+    // Sanity check the links array
+    nvlink_assert(links != NULL);
+
+    // Return early if link array is empty
+    if (numLinks == 0)
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO,
+            "%s: Link array is empty\n",
+            __FUNCTION__));
+        return NVL_SUCCESS;
+    }
+
+    for (i = 0; i < numLinks; i++)
+    {
+        NvlStatus status     = NVL_SUCCESS;
+        NvU64     dlLinkMode = 0;
+
+        // INITPHASE5 is supported only for NVLINK version >= 4.0
+        if (links[i]->version < NVLINK_DEVICE_VERSION_40)
+            continue;
+
+        // If receiver detect failed for the link, move to next link
+        if (!links[i]->bRxDetected || links[i]->bTxCommonModeFail)
+            continue;
+
+        if (links[i]->link_handlers->get_dl_link_mode(links[i], &dlLinkMode))
+        {
+            NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+                "%s: Unable to get link mode for %s:%s",
+                __FUNCTION__, links[i]->dev->deviceName, links[i]->linkName));
+        }
+
+        // Check if the link has reached failed state
+        if (links[i]->state == NVLINK_LINKSTATE_FAIL)
+        {
+            NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO,
+                "%s: %s:%s marked as failed.\n",
+                __FUNCTION__, links[i]->dev->deviceName, links[i]->linkName));
+            continue;
+        }
+
+        // Skip this step if link is in HS/SAFE
+        if (dlLinkMode == NVLINK_LINKSTATE_HS ||
+            dlLinkMode == NVLINK_LINKSTATE_SAFE)
+        {
+            continue;
+        }
+
+        status = links[i]->link_handlers->set_dl_link_mode(links[i],
+                                                  NVLINK_LINKSTATE_INITPHASE5,
+                                                  flags);
+
+        // Although it fails we need to continue with the next link
+        if (status != NVL_SUCCESS)
+        {
+            NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+                "%s: Initphase5 failed on Device:Link %s:%s\n",
+                __FUNCTION__, links[i]->dev->deviceName, links[i]->linkName));
+            links[i]->bInitphase5Fails = NV_TRUE;
+        }
+    }
+
+    //
+    // We could have links which are faulty and cannot be initialized. But proceeding
+    // the initialization sequence allows us to use other non-faulty links. Therefore
+    // return success always.
+    //
+    return NVL_SUCCESS;
+}
+
 /**
  * Kick-off INITPHASE1 on the given array of links
  *
@@ -295,11 +582,16 @@ nvlink_core_initphase1
         NvU32     txSubMode  = 0;
         NvU64     rxMode     = 0;
         NvU32     rxSubMode  = 0;
+        NvBool    bPhyUnlocked  = NV_FALSE;
 
         // INITPHASE1 is supported only for NVLINK version >= 3.0
         if (links[i]->version < NVLINK_DEVICE_VERSION_30)
             continue;
 
+        if (links[i]->version >= NVLINK_DEVICE_VERSION_40)
+            links[i]->link_handlers->get_uphy_load(links[i], &bPhyUnlocked);
+
+        if (!bPhyUnlocked)
         {
             if (links[i]->link_handlers->get_tl_link_mode(links[i], &tlLinkMode))
             {
@@ -343,6 +635,7 @@ nvlink_core_initphase1
         //
         if ((tlLinkMode == NVLINK_LINKSTATE_SLEEP) ||
             (dlLinkMode == NVLINK_LINKSTATE_RESET) ||
+            (bPhyUnlocked)                         ||
             ((txMode    == NVLINK_SUBLINK_STATE_TX_OFF) &&
              (rxMode    == NVLINK_SUBLINK_STATE_RX_OFF)))
         {

src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2017-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2017-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvVer.h"
@@ -443,6 +442,8 @@ nvlink_core_copy_device_info
     devInfo->numLinks         = nvListCount(&tmpDev->link_list);
     devInfo->devType          = _nvlink_core_map_device_type(tmpDev->type);
     devInfo->enabledLinkMask  = _nvlink_core_get_enabled_link_mask(tmpDev);
+    devInfo->bEnableAli       = tmpDev->enableALI;
+
     // copy device uuid information if available
     if (tmpDev->uuid != NULL)
     {

src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"
@@ -68,7 +67,36 @@ nvlink_core_check_link_state
             }
             break;
         }
+        case NVLINK_LINKSTATE_ALI:
+        {
+            status = link->link_handlers->get_tl_link_mode(link, &crntTlLinkMode);
+            if (status != NVL_SUCCESS)
+            {
+                NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+                    "%s: Unable to get TL link mode for %s:%s\n",
+                    __FUNCTION__, link->dev->deviceName, link->linkName));
+                return NV_FALSE;
+            }
+
+            status = link->link_handlers->get_dl_link_mode(link, &crntDlLinkMode);
+            if (status != NVL_SUCCESS)
+            {
+                NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+                    "%s: Unable to get DL link mode for %s:%s\n",
+                    __FUNCTION__, link->dev->deviceName, link->linkName));
+                return NV_FALSE;
+            }
+
+            if (crntTlLinkMode == NVLINK_LINKSTATE_HS &&
+                (crntDlLinkMode == NVLINK_LINKSTATE_HS ||
+                 crntDlLinkMode == NVLINK_LINKSTATE_SLEEP))
+            {
+                return NV_TRUE;
+            }
+            break;
+        }
         case NVLINK_LINKSTATE_SLEEP:
+        case NVLINK_LINKSTATE_ACTIVE_PENDING:
         {
             status = link->link_handlers->get_tl_link_mode(link, &crntTlLinkMode);
             if (status != NVL_SUCCESS)
@@ -85,7 +113,6 @@ nvlink_core_check_link_state
             }
             break;
         }
-
     }
 
     // return false for default case or the states are not matching

src/common/nvlink/kernel/nvlink/core/nvlink_logger.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"

src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"
@@ -431,7 +430,7 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off
                 
             // to track Failure
             conns[i]->end0->inSWCFG = NV_FALSE;        
-	}
+	    }
         else
         {
             conns[i]->end0->inSWCFG = NV_TRUE;
@@ -449,14 +448,14 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off
 
             // to track Failure
             conns[i]->end1->inSWCFG = NV_FALSE; 
-	}
+	    }
         else
         {
             conns[i]->end1->inSWCFG = NV_TRUE;
         }
 
         // Change each sublink state to SAFE
-	if(conns[i]->end0->inSWCFG == NV_TRUE)
+	    if(conns[i]->end0->inSWCFG == NV_TRUE)
         {
             conns[i]->end0->link_handlers->set_tx_mode(conns[i]->end0,
                                                        NVLINK_SUBLINK_STATE_TX_SAFE,
@@ -843,3 +842,148 @@ _nvlink_core_clear_link_state
     link->tx_sublink_state = NVLINK_SUBLINK_STATE_TX_OFF;
     link->rx_sublink_state = NVLINK_SUBLINK_STATE_RX_OFF;
 }
+
+static NvBool
+_nvlink_core_check_if_conn_in_array
+(
+    nvlink_intranode_conn **connArray,
+    NvU32                  connArrayLength,
+    nvlink_intranode_conn *conn
+)
+{
+    NvU32 i;
+
+    for (i = 0; i < connArrayLength; ++i)
+    {
+        if (conn == connArray[i])
+        {
+            return NV_TRUE;
+        }
+    }
+    return NV_FALSE;
+}
+
+NvlStatus
+nvlink_core_powerdown_floorswept_conns_to_off
+(
+    nvlink_link           **links,
+    NvU32                   linkCount,
+    NvU32                   numIoctrls,
+    NvU32                   numLinksPerIoctrl,
+    NvU32                   numActiveLinksPerIoctrl
+)
+{
+    NvU32 i,j;
+    nvlink_intranode_conn **connsToShutdown;
+    nvlink_intranode_conn **visitedConns;
+    nvlink_intranode_conn *conn;
+    NvU32 connCount;
+    NvU32 numConnsToShutdown;
+
+    if (linkCount == 0 || numIoctrls == 0 || numLinksPerIoctrl == 0 ||
+        numActiveLinksPerIoctrl == 0)
+    {
+        return NVL_BAD_ARGS;
+    }
+
+    connsToShutdown = (nvlink_intranode_conn **)nvlink_malloc(
+                            sizeof(nvlink_intranode_conn *) * NVLINK_MAX_SYSTEM_LINK_NUM);
+
+    if (connsToShutdown == NULL)
+    {
+        return NVL_NO_MEM;
+    }
+
+    visitedConns = (nvlink_intranode_conn **)nvlink_malloc(
+                            sizeof(nvlink_intranode_conn *) * NVLINK_MAX_SYSTEM_LINK_NUM);
+
+    if (visitedConns == NULL)
+    {
+        return NVL_NO_MEM;
+    }
+
+
+    //
+    // For each IOCTRL find the total # of connections and shutdown
+    // any connections over the number of active links per IOCTRL
+    //
+    for (i=0; i<numIoctrls; i++)
+    {
+        connCount = 0;
+        numConnsToShutdown = 0;
+        for (j = 0; j < linkCount; j++)
+        {
+            //
+            // If the link is associated with the current IOCTRL
+            // then retrieve its connection. If there is no
+            // active connection associated with the link then continue
+            // If the connection is not active, shutdown the links but don't
+            // increment connCount as this is not an active connection to be used for P2P
+            // If the number of connections found so far is greater
+            // then the number of active links allowed, mark the connection
+            // as being needed to shutdown. Increment the total connection count
+            //
+            if (links[j]->linkNumber >= numLinksPerIoctrl*i &&
+                links[j]->linkNumber < numLinksPerIoctrl*(i+1))
+            {
+                nvlink_core_get_intranode_conn(links[j], &(conn));
+                if (conn == NULL ||
+                    _nvlink_core_check_if_conn_in_array(visitedConns, connCount, conn) ||
+                    (conn->end0 == NULL || conn->end1 == NULL))
+                {
+                    continue;
+                }
+                else if(nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_OFF) ==
+                            NVL_SUCCESS)
+                {
+                    continue;
+                }
+                else if ((nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_HS) != NVL_SUCCESS  &&
+                          nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_SAFE) != NVL_SUCCESS) &&
+                        (!_nvlink_core_check_if_conn_in_array(connsToShutdown, numConnsToShutdown, conn)))
+                {
+                    // If link is not in SAFE or HS and not currently in our connsToShutdown array then add it
+                    connsToShutdown[numConnsToShutdown++] = conn;
+                }
+                else
+                {
+                    visitedConns[connCount++] = conn;
+                    if (connCount > numActiveLinksPerIoctrl &&
+                        !_nvlink_core_check_if_conn_in_array(connsToShutdown, numConnsToShutdown, conn))
+                    {
+                        connsToShutdown[numConnsToShutdown++] = conn;
+                    }
+                }
+
+                //
+                // If the #of conns found == #of links per IOCTRl then
+                // bail early since we know none of the other links can be
+                // part of this IOCTRL
+                //
+                if (connCount == numLinksPerIoctrl)
+                {
+                    connCount = 0;
+                    break;
+                }
+            }
+        }
+
+        //
+        // If the number of shutdown is non-zero then shutdown the connections
+        // and remove the connection from the corelib since all endpoints
+        // will query the corelib for topology and this connection should no longer
+        // be reported
+        //
+        if (numConnsToShutdown != 0)
+        {
+            nvlink_core_powerdown_intranode_conns_from_active_to_off(connsToShutdown, numConnsToShutdown, 0);
+
+            for (j = 0; j < numConnsToShutdown; ++j)
+            {
+                nvlink_core_remove_intranode_conn(connsToShutdown[j]);
+            }
+        }
+    }
+
+    return NVL_SUCCESS;
+}

src/common/nvlink/kernel/nvlink/core/nvlink_training.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"
@@ -31,6 +30,31 @@ static void _nvlink_core_set_sublink_pre_hs_settings(nvlink_link *, NvU32);
 static void _nvlink_core_set_link_pre_active_settings(nvlink_link *, NvU32);
 static void _nvlink_core_set_link_post_active_settings(nvlink_link *, NvU32);
 
+NvlStatus
+nvlink_core_train_check_link_ready_ALI
+(
+    nvlink_link **links,
+    NvU32 linkCount
+)
+{
+    NvU32 i = 0;
+    NvlStatus status = NVL_SUCCESS;
+
+    for (i = 0; i < linkCount; i++)
+    {
+        if (!nvlink_core_check_link_state(links[i], NVLINK_LINKSTATE_ALI))
+        {
+            // If link is not in active, update status to be error and continue
+            status = NVL_ERR_GENERIC;
+            continue;
+        }
+
+        links[i]->link_handlers->training_complete(links[i]);
+    }
+
+    return status;
+}
+
 /**
  * Link training
  *   Train the internode connection link from SWCFG to ACTIVE
@@ -671,6 +695,157 @@ nvlink_core_train_intranode_conns_from_from_L2_to_active
     return status;
 }
 
+/**
+ * Train intranode connections associated with a list of links to HS
+ * using non-ALI sequence
+ *
+ * @param[in]  conns      Array of connections to train
+ * @param[in]  connCount  Number of connections in the array
+ * @param[in]  flags      Flags to track if training is sync/async
+ *
+ * return NVL_SUCCESS if the connections train successfully
+ */
+NvlStatus
+nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI
+(
+    nvlink_intranode_conn **conns,
+    NvU32                   connCount,
+    NvU32                   flags
+)
+{
+    NvlStatus status     = NVL_SUCCESS;
+    NvlStatus pollStatus = NVL_SUCCESS;
+    NvU32     i;
+
+    if ((conns == NULL) || (connCount == 0))
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+            "%s: No connections to train to ACTIVE\n",
+            __FUNCTION__));
+
+        return NVL_ERR_GENERIC;
+    }
+
+    // Trigger INITOPTIMIZE on both ends of the connection
+    for (i = 0; i < connCount; i++)
+    {
+        conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0,
+                                                        NVLINK_LINKSTATE_INITOPTIMIZE,
+                                                        flags);
+
+        // On loopback, only send INITOPTIMIZE to one side.
+        if (conns[i]->end0 != conns[i]->end1)
+        {
+            conns[i]->end1->link_handlers->set_dl_link_mode(conns[i]->end1,
+                                                            NVLINK_LINKSTATE_INITOPTIMIZE,
+                                                            flags);
+        }
+    }
+
+    // Trigger POST_INITOPTIMIZE (Checks INITOPTIMIZE was successful) on both ends of the connection
+    for (i = 0; i < connCount; i++)
+    {
+        conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0,
+                                                        NVLINK_LINKSTATE_POST_INITOPTIMIZE,
+                                                        flags);
+
+        // On loopback, only send POST_INITOPTIMIZE to one side.
+        if (conns[i]->end0 != conns[i]->end1)
+        {
+            conns[i]->end1->link_handlers->set_dl_link_mode(conns[i]->end1,
+                                                            NVLINK_LINKSTATE_POST_INITOPTIMIZE,
+                                                            flags);
+        }
+    }
+
+    // Set link modes to ACTIVE
+    for (i = 0; i < connCount; i++)
+    {
+        // Some settings required before moving to ACTIVE
+        _nvlink_core_set_link_pre_active_settings(conns[i]->end0, flags);
+        _nvlink_core_set_link_pre_active_settings(conns[i]->end1, flags);
+
+        conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0,
+                                                        NVLINK_LINKSTATE_HS,
+                                                        flags);
+
+        // If not in loopback send the dl link mode
+        if (conns[i]->end0 != conns[i]->end1)
+        {
+
+            conns[i]->end1->link_handlers->set_dl_link_mode(conns[i]->end1,
+                                                        NVLINK_LINKSTATE_HS,
+                                                        flags);
+        }
+
+    }
+
+    // Verify link mode HS on the endpoints
+    for (i = 0; i < connCount; i++)
+    {
+
+        pollStatus = nvlink_core_poll_link_state(conns[i]->end0,
+                                                NVLINK_LINKSTATE_HS,
+                                                NVLINK_TRANSITION_HS_TIMEOUT);
+        if (pollStatus != NVL_SUCCESS)
+        {
+            status = pollStatus;
+        }
+
+        pollStatus = nvlink_core_poll_link_state(conns[i]->end1,
+                                                NVLINK_LINKSTATE_HS,
+                                                NVLINK_TRANSITION_HS_TIMEOUT);
+        if (pollStatus != NVL_SUCCESS)
+        {
+            status = pollStatus;
+        }
+
+        conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0,
+                                                        NVLINK_LINKSTATE_INITTL,
+                                                        flags);
+
+        // On loopback, only send once
+        if (conns[i]->end0 != conns[i]->end1)
+        {
+            conns[i]->end1->link_handlers->set_dl_link_mode(conns[i]->end1,
+                                                        NVLINK_LINKSTATE_INITTL,
+                                                        flags);
+        }
+
+        conns[i]->end0->link_handlers->training_complete(conns[i]->end0);
+
+        // On loopback, only send once
+        if (conns[i]->end0 != conns[i]->end1)
+        {
+            conns[i]->end1->link_handlers->training_complete(conns[i]->end1);
+        }
+
+        conns[i]->end0->link_handlers->set_tx_mode(conns[i]->end0,
+                                                   NVLINK_SUBLINK_STATE_TX_POST_HS,
+                                                   flags);
+        // On loopback, only send once
+        if (conns[i]->end0 != conns[i]->end1)
+        {
+            conns[i]->end1->link_handlers->set_tx_mode(conns[i]->end1,
+                                                       NVLINK_SUBLINK_STATE_TX_POST_HS,
+                                                       flags);
+        }
+
+        conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0,
+                                                        NVLINK_LINKSTATE_TRAFFIC_SETUP,
+                                                        flags);
+        // On loopback, only send once
+        if (conns[i]->end0 != conns[i]->end1)
+        {
+            conns[i]->end1->link_handlers->set_dl_link_mode(conns[i]->end1,
+                                                            NVLINK_LINKSTATE_TRAFFIC_SETUP,
+                                                            flags);
+        }
+    }
+
+    return status;
+}
+
 /**
  * Train intranode connections associated with a list of links to HS
  * using ALT sequence

src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2017-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2017-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvVer.h"
@@ -708,6 +707,12 @@ nvlink_lib_ctrl_all_links
             // default initialize status to NVL_SUCCESS
             iocReq->status = NVL_SUCCESS;
 
+            if (links[0]->dev->enableALI)
+            {
+                status = NVL_SUCCESS;
+                goto nvlink_lib_ctrl_all_links_end;
+            }
+
             iocReq->status = nvlink_core_initphase1(links, numLinks,
                                                     NVLINK_STATE_CHANGE_SYNC);
             break;
@@ -727,6 +732,16 @@ nvlink_lib_ctrl_all_links
             // default initialize status to NVL_SUCCESS
             iocReq->status = NVL_SUCCESS;
 
+            //
+            // If the current nvlink device does not support the command
+            // skip using the command and return success for FM to continue on.
+            //
+            if (links[0]->version >= NVLINK_DEVICE_VERSION_40)
+            {
+                status = NVL_SUCCESS;
+                goto nvlink_lib_ctrl_all_links_end;
+            }
+
             iocReq->status = nvlink_core_rx_init_term(links, numLinks,
                                                       NVLINK_STATE_CHANGE_ASYNC);
             break;
@@ -746,6 +761,12 @@ nvlink_lib_ctrl_all_links
             // default initialize status to NVL_SUCCESS
             iocReq->status = NVL_SUCCESS;
 
+            if (links[0]->dev->enableALI)
+            {
+                status = NVL_SUCCESS;
+                goto nvlink_lib_ctrl_all_links_end;
+            }
+
             iocReq->status = nvlink_core_set_rx_detect(links, numLinks,
                                                       NVLINK_STATE_CHANGE_ASYNC);
             break;
@@ -765,6 +786,12 @@ nvlink_lib_ctrl_all_links
             // default initialize status to NVL_SUCCESS
             iocReq->status = NVL_SUCCESS;
 
+            if (links[0]->dev->enableALI)
+            {
+                status = NVL_SUCCESS;
+                goto nvlink_lib_ctrl_all_links_end;
+            }
+
             iocReq->status = nvlink_core_get_rx_detect(links, numLinks,
                                                       NVLINK_STATE_CHANGE_ASYNC);
             break;
@@ -784,6 +811,12 @@ nvlink_lib_ctrl_all_links
             // default initialize status to NVL_SUCCESS
             iocReq->status = NVL_SUCCESS;
 
+            if (links[0]->dev->enableALI)
+            {
+                status = NVL_SUCCESS;
+                goto nvlink_lib_ctrl_all_links_end;
+            }
+
             if (iocReq->commMode)
             {
                 iocReq->status = nvlink_core_enable_common_mode(links, numLinks,
@@ -816,6 +849,16 @@ nvlink_lib_ctrl_all_links
             // default initialize status to NVL_SUCCESS
             iocReq->status = NVL_SUCCESS;
 
+            //
+            // If the current nvlink device does not support the command
+            // skip using the command and return success for FM to continue on.
+            //
+            if (links[0]->version >= NVLINK_DEVICE_VERSION_40)
+            {
+                iocReq->status = NVL_SUCCESS;
+                goto nvlink_lib_ctrl_all_links_end;
+            }
+
             iocReq->status = nvlink_core_calibrate_links(links, numLinks,
                                                       NVLINK_STATE_CHANGE_SYNC);
             break;
@@ -834,6 +877,16 @@ nvlink_lib_ctrl_all_links
             // default initialize status to NVL_SUCCESS
             iocReq->status = NVL_SUCCESS;
 
+            //
+            // If the current nvlink device does not support the command
+            // skip using the command and return success for FM to continue on.
+            //
+            if (links[0]->version >= NVLINK_DEVICE_VERSION_40)
+            {
+                status = NVL_SUCCESS;
+                goto nvlink_lib_ctrl_all_links_end;
+            }
+
             iocReq->status = nvlink_core_enable_data(links, numLinks,
                                                       NVLINK_STATE_CHANGE_SYNC);
             break;
@@ -871,10 +924,17 @@ nvlink_lib_ctrl_all_links
             // default initialize status to NVL_SUCCESS
             iocReq->status = NVL_SUCCESS;
 
+            if (links[0]->dev->enableALI)
+            {
+                status = NVL_SUCCESS;
+                goto nvlink_lib_ctrl_all_links_end;
+            }
+
             iocReq->status = nvlink_core_initnegotiate(links, numLinks,
                                                       NVLINK_STATE_CHANGE_ASYNC);
             break;
         }
+
         case CTRL_NVLINK_INITPHASE5:
         {
             nvlink_initphase5 *iocReq;
@@ -889,6 +949,18 @@ nvlink_lib_ctrl_all_links
             // default initialize status to NVL_SUCCESS
             iocReq->status = NVL_SUCCESS;
 
+            //
+            // If the current nvlink device does not support the command
+            // skip using the command and return success for FM to continue on.
+            //
+            if (links[0]->version < NVLINK_DEVICE_VERSION_40 ||
+                links[0]->dev->enableALI)
+            {
+                status = NVL_SUCCESS;
+                goto nvlink_lib_ctrl_all_links_end;
+            }
+            iocReq->status = nvlink_core_initphase5(links, numLinks,
+                                                      NVLINK_STATE_CHANGE_ASYNC);
             break;
         }
 
@@ -2043,6 +2115,16 @@ nvlink_lib_ctrl_train_intranode_conn
     {
         case nvlink_train_conn_off_to_swcfg:
         {
+            if (srcLink->version >= NVLINK_DEVICE_VERSION_40)
+            {
+                // non-ALI training for NVLink4.0+
+                if (!srcLink->dev->enableALI)
+                {
+                    nvlink_core_init_links_from_off_to_swcfg_non_ALI(
+                                            initLinks, count, NVLINK_STATE_CHANGE_SYNC);
+                }
+            }
+            else
             {
                 // ALT training for NVLink3.0+
                 nvlink_core_init_links_from_off_to_swcfg(
@@ -2052,8 +2134,16 @@ nvlink_lib_ctrl_train_intranode_conn
         }
         case nvlink_train_conn_swcfg_to_active:
         {
-            if (srcLink->version >= NVLINK_DEVICE_VERSION_30)
-
+            if (srcLink->version >= NVLINK_DEVICE_VERSION_40)
+            {
+                // non-ALI training for NVLink4.0+
+                if (!srcLink->dev->enableALI)
+                {
+                    status = nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI(
+                                                     &conn, 1, NVLINK_STATE_CHANGE_SYNC);
+                }
+            } 
+            else if (srcLink->version >= NVLINK_DEVICE_VERSION_30)
             {
                 // ALT training for NVLink3.0+
                 status = nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT(
@@ -2333,6 +2423,16 @@ nvlink_lib_ctrl_train_intranode_conns_parallel
     {
         case nvlink_train_conn_off_to_swcfg:
         {
+            if (srcLink->version >= NVLINK_DEVICE_VERSION_40)
+            {
+                // non-ALI training for NVLink4.0+
+                if (!srcLink->dev->enableALI)
+                {
+                    nvlink_core_init_links_from_off_to_swcfg_non_ALI(
+                                            initLinks, count, NVLINK_STATE_CHANGE_SYNC);
+                }
+            }
+            else
             {
                 // ALT training for NVLink3.0+
                 nvlink_core_init_links_from_off_to_swcfg(
@@ -2342,6 +2442,16 @@ nvlink_lib_ctrl_train_intranode_conns_parallel
         }
         case nvlink_train_conn_swcfg_to_active:
         {
+            if (srcLink->version >= NVLINK_DEVICE_VERSION_40)
+            {
+                // non-ALI training for NVLink4.0+
+                if (!srcLink->dev->enableALI)
+                {
+                    status = nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI(
+                                                        conns, numConns, NVLINK_STATE_CHANGE_SYNC);
+                }
+            }
+            else
             {
                 // ALT training for NVLink3.0+
                 status = nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT(
@@ -3418,8 +3528,6 @@ nvlink_lib_ctrl_get_device_link_states
 {
     nvlink_link  *endpoint  = NULL;
     nvlink_device *dev      = NULL;
-	nvlink_device *devIter    = NULL;
-    nvlink_link   *remoteLink = NULL;
     NvlStatus     status    = NVL_SUCCESS;
     NvU32         numLinks  = 0;
     NvU32         i         = 0;
@@ -3463,14 +3571,12 @@ nvlink_lib_ctrl_get_device_link_states
     // Top-level lock is now acquired. Proceed to traversing the list
     // of devices and list of links to lock all links
     //
-    FOR_EACH_DEVICE_REGISTERED(devIter, nvlinkLibCtx.nv_devicelist_head, node)
+    FOR_EACH_LINK_REGISTERED(endpoint, dev, node)
     {
-        FOR_EACH_LINK_REGISTERED(endpoint, devIter, node)
-    {
-            if (numLinks >= NVLINK_MAX_SYSTEM_LINK_NUM)
+        if (numLinks >= NVLINK_MAX_NVLINK_ENDPOINTS)
         {
             NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
-                    "%s: numLinks >= NVLINK_MAX_SYSTEM_LINK_NUM",
+                "%s: numLinks >= NVLINK_MAX_NVLINK_ENDPOINTS",
                 __FUNCTION__));
 
             nvlink_assert(0);
@@ -3483,7 +3589,6 @@ nvlink_lib_ctrl_get_device_link_states
         links[numLinks] = endpoint;
         numLinks++;
     }
-	}
 
     // Acquire the per-link locks
     status = nvlink_lib_link_locks_acquire(links, numLinks);
@@ -3519,31 +3624,6 @@ nvlink_lib_ctrl_get_device_link_states
             "%s: link 0x%x -- rxDet status 0x%x, linkMode 0x%x,\n",
             __FUNCTION__, i, links[i]->bRxDetected, params->endStates[i].linkMode));
 
-        //
-        // If the link succeeds rxDet then go through and find its peer link. What is important
-        // is not actually finding the link, but making sure the corelib goes through the discovery
-        // process and has endpoints cache the remote information in the corelib such that
-        // FM or endpoints can query the corelib for the topology of the system.
-        //
-        if (links[i]->bRxDetected)
-        {
-            remoteLink = NULL;
-            nvlink_core_discover_and_get_remote_end(links[i], &remoteLink, 0);
-
-            if (remoteLink == NULL)
-            {
-                NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
-                    "%s: link 0x%x: couldn't find link pair\n",
-                    __FUNCTION__, i));
-                continue;
-            }
-
-        // If the link is in active, issue postActive settings
-        if (params->endStates[i].linkMode == nvlink_link_mode_active)
-        {
-            links[i]->link_handlers->training_complete(links[i]);
-        }
-    }
     }
 
     params->endStatesCount = numLinks;

src/common/nvlink/kernel/nvlink/interface/nvlink_kern_discovery_entry.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"

src/common/nvlink/kernel/nvlink/interface/nvlink_kern_initialize_entry.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"
@@ -108,6 +107,16 @@ nvlink_lib_reinit_link_from_off_to_swcfg
     // Release the top level-lock
     //
     nvlink_lib_top_lock_release();
+
+    if (conn->end0->version >= NVLINK_DEVICE_VERSION_40 ||
+        conn->end1->version >= NVLINK_DEVICE_VERSION_40)
+    {
+        if (!conn->end0->dev->enableALI)
+        {
+            nvlink_core_init_links_from_off_to_swcfg_non_ALI(links, 2, flags);
+        }
+    } 
+    else
     {
         nvlink_core_init_links_from_off_to_swcfg(links, 2, flags);
     }

src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"
@@ -320,4 +319,135 @@ nvlink_lib_get_link_master
     return status;
 }
 
+/**
+ * Set whether the link is using ALI for training.
+ * 
+ * @param[in]  link       NVLink Link pointer
+ * @param[in]  enableALI  Boolean for whether the link is using
+ *                        ALI to train the link
+ *
+ * return NvlSuccess if setting the variable was successful.
+ */
+NvlStatus
+nvlink_lib_link_set_training_mode
+(
+    nvlink_link  *link,
+    NvBool        enableALI
+)
+{
+    NvlStatus status = NVL_SUCCESS;
+    if (link == NULL)
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+            "%s: Bad link pointer specified.\n",
+            __FUNCTION__));
+        return NVL_ERR_GENERIC;
+    }
+
+    // Acquire the top-level lock
+    status = nvlink_lib_top_lock_acquire();
+    if (status != NVL_SUCCESS)
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+            "%s: Failed to acquire top-level lock\n",
+            __FUNCTION__));
+
+        return status;
+    }
+
+
+    // Acquire the per-link lock
+    status = nvlink_lib_link_locks_acquire(&link, 1);
+    if (status != NVL_SUCCESS)
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+            "%s: Failed to acquire per-link locks\n",
+            __FUNCTION__));
+
+        // Release the top-level lock
+        nvlink_lib_top_lock_release();
+
+        return status;
+    }
+
+    //
+    // All the required per-link locks are successfully acquired
+    // The connection list traversal is also complete now
+    // Release the top level-lock
+    //
+    nvlink_lib_top_lock_release();
+
+    // TODO: Add Setter for per-link enableALI state variable
+
+    // Release the per-link lock
+    nvlink_lib_link_locks_release(&link, 1);
+
+    return status;
+}
+
+/**
+ * Get whether the link is using ALI for training.
+ *
+ * @param[in]  link     NVLink Link pointer
+ * @param[out] usingAli Boolean on whether ALI training is being used
+ *
+ * return NVL_SUCCESS if getting the variable is successful
+ */
+NvlStatus
+nvlink_lib_is_link_using_ALI
+(
+    nvlink_link  *link,
+    NvBool       *usingALI
+)
+{
+    NvlStatus status = NVL_SUCCESS;
+    usingALI         = NV_FALSE;
+    
+    if (link == NULL)
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+            "%s: Bad link pointer specified.\n",
+            __FUNCTION__));
+        return NVL_ERR_GENERIC;
+    }
+
+    // Acquire the top-level lock
+    status = nvlink_lib_top_lock_acquire();
+    if (status != NVL_SUCCESS)
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+            "%s: Failed to acquire top-level lock\n",
+            __FUNCTION__));
+
+        return status;
+    }
+
+    // Acquire the per-link lock
+    status = nvlink_lib_link_locks_acquire(&link, 1);
+    if (status != NVL_SUCCESS)
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+            "%s: Failed to acquire per-link locks\n",
+            __FUNCTION__));
+
+        // Release the top-level lock
+        nvlink_lib_top_lock_release();
+
+        return status;
+    }
+
+    //
+    // All the required per-link locks are successfully acquired
+    // The connection list traversal is also complete now
+    // Release the top level-lock
+    //
+    nvlink_lib_top_lock_release();
+
+    // TODO: Add Getter for per-link enableALI state variable
+
+    // Release the per-link lock
+    nvlink_lib_link_locks_release(&link, 1);
+
+    return status;
+}
 

src/common/nvlink/kernel/nvlink/interface/nvlink_kern_registration_entry.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+    The above copyright notice and this permission notice shall be
+    included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"

src/common/nvlink/kernel/nvlink/interface/nvlink_kern_shutdown_entry.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"
@@ -304,10 +303,10 @@ nvlink_lib_powerdown_links_from_active_to_off
     nvlink_intranode_conn **conns    = NULL;
     nvlink_intranode_conn  *conn     = NULL;
     NvU32                   numConns = 0;
-    NvU32                   i;
+    NvU32                   i,j;
     NvU32                   lockLinkCount = 0;
     nvlink_link           **lockLinks = NULL;
-
+    NvBool                  bIsAlreadyPresent = NV_FALSE;
 
     if ((links == NULL) || (numLinks == 0))
     {
@@ -424,8 +423,51 @@ nvlink_lib_powerdown_links_from_active_to_off
             continue;
         }
 
-        conns[numConns] = conn;
-        numConns++;
+        //
+        // If device is using ALI based link training, it is possible
+        // for links to be still transitioning to active when a request to shutdown
+        // is made. Ensure that all connections transiton successfully to HS or fault
+        // before continuining to shutdown
+        //
+        if(links[0]->dev->enableALI)
+        {
+
+            status = nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_ACTIVE_PENDING);
+
+            if (status == NVL_SUCCESS)
+            {
+                status = nvlink_core_poll_link_state(conn->end0,
+                                             NVLINK_LINKSTATE_HS,
+                                             NVLINK_TRANSITION_ACTIVE_PENDING);
+
+                if (status != NVL_SUCCESS &&
+                    nvlink_core_check_intranode_conn_state(conn, NVLINK_LINKSTATE_FAULT) != NVL_SUCCESS)
+                {
+                    NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+                        "%s: Connection between %s: %s and %s: %s is not ready for shutdown (link state is no in HS or FAULT). Soldiering on...\n",
+                        __FUNCTION__, conn->end0->dev->deviceName, conn->end0->linkName,
+                        conn->end1->dev->deviceName, conn->end1->linkName));
+                }
+            }
+        }
+
+        bIsAlreadyPresent = NV_FALSE;
+        // Check if the the connection is already included in the list
+        for (j = 0; j < numConns; j++)
+        {
+            if (conns[j] == conn)
+            {
+                bIsAlreadyPresent = NV_TRUE;
+                break;
+            }
+        }
+
+        // If this is a new connection, add it to the list
+        if (!bIsAlreadyPresent)
+        {
+            conns[numConns] = conn;
+            numConns++;
+        }
     }
 
     //
@@ -775,3 +817,109 @@ nvlink_lib_reset_links_end:
 
     return status;
 }
+
+
+NvlStatus
+nvlink_lib_powerdown_floorswept_links_to_off
+(
+    nvlink_device *dev
+)
+{
+    NvlStatus                status    = NVL_SUCCESS;
+    nvlink_link             *link      = NULL;
+    nvlink_link            **lockLinks = NULL;
+    NvU32                    lockLinkCount = 0;
+
+    if (dev == NULL)
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+            "%s: Bad device pointer specified.\n",
+            __FUNCTION__));
+
+        return NVL_ERR_GENERIC;
+    }
+
+    lockLinks = (nvlink_link **)nvlink_malloc(
+                            sizeof(nvlink_link *) * NVLINK_MAX_SYSTEM_LINK_NUM);
+    if (lockLinks == NULL)
+    {
+        return NVL_NO_MEM;
+    }
+
+    // Acquire the top-level lock
+    status = nvlink_lib_top_lock_acquire();
+    if (status != NVL_SUCCESS)
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+            "%s: Failed to acquire top-level lock\n",
+            __FUNCTION__));
+        goto nvlink_core_powerdown_floorswept_conns_to_off_end;
+    }
+
+    //
+    // If the device has less than or equal links in the IP then
+    // can be active, then skip floorsweeping
+    //
+    if (dev->numActiveLinksPerIoctrl >= dev->numLinksPerIoctrl)
+    {
+        nvlink_lib_top_lock_release();
+        goto nvlink_core_powerdown_floorswept_conns_to_off_end;
+    }
+
+    //
+    // Top-level lock is now acquired. Proceed to traversing the device
+    // and link lists and connection lists
+    //
+
+    // Get the array of link endpoints whose lock needs to be acquired
+    FOR_EACH_LINK_REGISTERED(link, dev, node)
+    {
+        if(link == NULL)
+        {
+            continue;
+        }
+
+        lockLinks[lockLinkCount] = link;
+        lockLinkCount++;
+    }
+
+    // Acquire the per-link locks for all links captured
+    status = nvlink_lib_link_locks_acquire(lockLinks, lockLinkCount);
+    if (status != NVL_SUCCESS)
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+            "%s: Failed to acquire per-link locks\n",
+            __FUNCTION__));
+
+        // Release the top-level lock
+        nvlink_lib_top_lock_release();
+
+        goto nvlink_core_powerdown_floorswept_conns_to_off_end;
+    }
+
+    //
+    // All the required per-link locks are successfully acquired
+    // The connection list traversal is also complete now
+    // Release the top level-lock
+    //
+    nvlink_lib_top_lock_release();
+
+    status = nvlink_core_powerdown_floorswept_conns_to_off(lockLinks, lockLinkCount, dev->numIoctrls,
+                        dev->numLinksPerIoctrl, dev->numActiveLinksPerIoctrl);
+
+    if (status == NVL_BAD_ARGS)
+    {
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_INFO,
+            "%s: Bad args passed in for floorsweeping. Chip might not support the feature\n",
+            __FUNCTION__));
+    }
+
+nvlink_core_powerdown_floorswept_conns_to_off_end:
+    if (lockLinks != NULL)
+    {
+        nvlink_free((void *)lockLinks);
+    }
+
+    return status;
+}
+

src/common/nvlink/kernel/nvlink/interface/nvlink_kern_training_entry.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"
@@ -116,6 +115,24 @@ nvlink_lib_check_training_complete
 
     nvlink_lib_top_lock_release();
 
+    // Only run the check if ALI is enabled
+    if(links[0]->dev->enableALI)
+    {
+        //
+        // This will be the returned back to the caller, the core function
+        // will return early with an error status if a link is not Active
+        //
+        status = nvlink_core_train_check_link_ready_ALI(lockLinks, lockLinkCount);
+    }
+    else
+    {
+        // If ALI is not enabled, return error
+        NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
+            "%s: ALI is not enabled! Cannot check training status, please use non-ALI or ALT training to get links to active\n",
+            __FUNCTION__));
+        status = NVL_ERR_GENERIC;
+    }
+
     // Release the per-link locks
     nvlink_lib_link_locks_release(lockLinks, lockLinkCount);
 nvlink_lib_check_training_complete_end:
@@ -297,7 +314,18 @@ nvlink_lib_train_links_from_swcfg_to_active
 
     if (connCount > 0)
     {
-        if ((conn->end0->version >= NVLINK_DEVICE_VERSION_30) ||
+        if ((conn->end0->version >= NVLINK_DEVICE_VERSION_40) ||
+            (conn->end1->version >= NVLINK_DEVICE_VERSION_40))
+        {
+            if (!conn->end0->dev->enableALI)
+            {
+                status = nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI(conns,
+                                                                                connCount,
+                                                                                flags);
+            }
+        }
+        // For NVLink3+, use ALT sequence
+        else if ((conn->end0->version >= NVLINK_DEVICE_VERSION_30) ||
             (conn->end1->version >= NVLINK_DEVICE_VERSION_30))
         {
             status = nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT(conns,
@@ -685,9 +713,23 @@ nvlink_lib_retrain_link_from_swcfg_to_active
 
         return status;
     }
-    if ((conn->end0->version >= NVLINK_DEVICE_VERSION_30) ||
+    
+    if ((conn->end0->version >= NVLINK_DEVICE_VERSION_40) ||
+        (conn->end1->version >= NVLINK_DEVICE_VERSION_40))
+    {
+        if (!conn->end0->bInitnegotiateConfigGood ||
+            !conn->end1->bInitnegotiateConfigGood)
+        {
+            status = NVL_ERR_GENERIC;
+        }
+        else if (!conn->end0->dev->enableALI)
+        {
+            // ALI training for NVLink4.0+
+            status = nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI(conns, 0x1, flags);
+        }
+    }
+    else if ((conn->end0->version >= NVLINK_DEVICE_VERSION_30) ||
         (conn->end1->version >= NVLINK_DEVICE_VERSION_30))
-
     {
         if (!conn->end0->bInitnegotiateConfigGood ||
             !conn->end1->bInitnegotiateConfigGood)

src/common/nvlink/kernel/nvlink/nvlink_ctx.h

@@ -1,25 +1,25 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2014-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2014-2017 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
+
 
 #ifndef _NVLINK_CTX_H_
 #define _NVLINK_CTX_H_

src/common/nvlink/kernel/nvlink/nvlink_helper.h

@@ -1,30 +1,28 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2017-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2017-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #ifndef _NVLINK_HELPER_H_
 #define _NVLINK_HELPER_H_
 
-
 //
 // fabric node id will be used as MSB 16 bits of the link token value to 
 // generate a unique token for discovering connections
@@ -67,6 +65,11 @@ void nvlink_core_copy_device_info(nvlink_device *tmpDev, nvlink_detailed_dev_inf
 /****************************** NVLink initialization functions *********************************/
 /************************************************************************************************/
 
+/**
+ * Kick-off INITPHASE5 on the given array of links
+ */
+NvlStatus nvlink_core_initphase5(nvlink_link **links, NvU32 numLinks, NvU32 flags);
+
 /**
  * Kick-off INITPHASE1 on the given array of links
  */
@@ -124,12 +127,18 @@ void nvlink_core_init_links_from_off_to_swcfg(nvlink_link **pLinks,
                                               NvU32         numLinks,
                                               NvU32         flags);
 
+/*
+ * Initialize all the endpoints from OFF to SWCFG state for Non-ALI sequence
+ * Used for nvlink 4.0+
+ */
+void nvlink_core_init_links_from_off_to_swcfg_non_ALI(nvlink_link **pLinks,
+                                                     NvU32         numLinks,
+                                                     NvU32         flags);
 /**
  * Send INITNEGOTIATE command on the given array of links
  */
 NvlStatus nvlink_core_initnegotiate(nvlink_link **links, NvU32 numLinks, NvU32 flags);
 
-
 /************************************************************************************************/
 /*************************** NVLink topology discovery functions ********************************/
 /************************************************************************************************/
@@ -195,6 +204,7 @@ NvlStatus nvlink_core_train_intranode_conns_from_swcfg_to_active_ALT(nvlink_intr
                                                                      NvU32                   flags);
 
 
+
 /**
  * Train a single intranode connection associated with a list of links to HS using legacy
  * pre-Ampere sequence
@@ -203,6 +213,21 @@ NvlStatus nvlink_core_train_intranode_conns_from_swcfg_to_active_legacy(nvlink_i
                                                                         NvU32                   connCount,
                                                                         NvU32                   flags);
 
+/**
+ * Train intranode connections associated with a list of links to HS using non-ALI sequence
+ * for nvlink 4.0+
+ */
+NvlStatus nvlink_core_train_intranode_conns_from_swcfg_to_active_non_ALI(nvlink_intranode_conn **conns,
+                                                                        NvU32                   connCount,
+                                                                        NvU32                   flags);
+
+/**
+ * Check to make sure that links are in active and ready for ALI training for nvlink 4.0+
+ */
+NvlStatus nvlink_core_train_check_link_ready_ALI(nvlink_link **links,
+                                                 NvU32         linkCount);
+
+
 /************************************************************************************************/
 /********************************** NVLink shutdown functions ***********************************/
 /************************************************************************************************/
@@ -239,6 +264,15 @@ NvlStatus nvlink_core_reset_intranode_conns(nvlink_intranode_conn **conns,
                                             NvU32                   connCount,
                                             NvU32                   flags);
 
+/**
+ * Check to make sure that links are in active and ready for ALI training for nvlink 4.0+
+ */
+NvlStatus nvlink_core_powerdown_floorswept_conns_to_off(nvlink_link **links,
+                                       NvU32          numLinks,
+                                       NvU32          numIoctrls,
+                                       NvU32          numLinksPerIoctrl,
+                                       NvU32          numActiveLinksPerIoctrl);
+
 
 /************************************************************************************************/
 /**************************** NVLink connection management functions ****************************/

src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c

@@ -1,25 +1,24 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2019-2020 NVidia Corporation
+
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+
+    The above copyright notice and this permission notice shall be
+    included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvlink_export.h"

src/common/nvlink/kernel/nvlink/nvlink_lock.c

@@ -1,25 +1,21 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
+/*******************************************************************************
+    Copyright (c) 2020 NVidia Corporation
+    Permission is hereby granted, free of charge, to any person obtaining a copy
+    of this software and associated documentation files (the "Software"), to
+    deal in the Software without restriction, including without limitation the
+    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+    sell copies of the Software, and to permit persons to whom the Software is
+    furnished to do so, subject to the following conditions:
+        The above copyright notice and this permission notice shall be
+        included in all copies or substantial portions of the Software.
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+*******************************************************************************/
 
 #include "nvlink.h"
 #include "nvtypes.h"

src/common/nvswitch/common/inc/soe/soebif.h

@@ -57,16 +57,6 @@ enum
      * Get UPHY EOM(Eye Opening Measurement) status.
      */
     RM_SOE_BIF_CMD_GET_EOM_STATUS,
-
-    /*!
-     * Signal Lane Margining
-     */
-    RM_SOE_BIF_CMD_SIGNAL_LANE_MARGINING,
-
-    /*!
-     * Handle Margining interrupt
-     */
-    RM_SOE_BIF_CMD_SERVICE_MARGINING_INTERRUPTS,
 };
 
 /*!
@@ -99,12 +89,6 @@ typedef struct
     NvU32 laneSelectMask;
 } RM_SOE_BIF_CMD_UPHY_DLN_CFG_SPACE;
 
-typedef struct
-{
-    NvU8 cmdType;
-    NvU8 laneNum;
-} RM_SOE_BIF_CMD_LANE_MARGINING;
-
 #define RM_SOE_BIF_LINK_SPEED_INVALID      (0x00)
 #define RM_SOE_BIF_LINK_SPEED_GEN1PCIE     (0x01)
 #define RM_SOE_BIF_LINK_SPEED_GEN2PCIE     (0x02)
@@ -141,7 +125,7 @@ typedef union
     RM_SOE_BIF_CMD_UPHY_DLN_CFG_SPACE cfgctl;
     RM_SOE_BIF_CMD_PCIE_LINK_SPEED speedctl;
     RM_SOE_BIF_CMD_EOM_STATUS eomStatus;
-    RM_SOE_BIF_CMD_LANE_MARGINING laneMargining;
 } RM_SOE_BIF_CMD;
 
 #endif  // _SOEBIF_H_
+

src/common/nvswitch/common/inc/soe/soeifsoe.h

@@ -42,6 +42,22 @@ enum
     RM_SOE_INIT_MSG_ID_SOE_INIT = 0,
 };
 
+/*
+ * CMDQ and MSGQ lengths used in INIT-MSG on LS10
+ *
+ * These values are hard-coded in soe-riscv.
+ * They need to be same in SOE and driver and
+ * are protected by compile time checks in SOE.
+ *
+ */
+#define SOE_CMD_QUEUE_LENGTH    (0x80ul)
+#define SOE_MSG_QUEUE_LENGTH    (0x80ul)
+
+/*!
+ * Define SOE CMDQ and MSGQ EMEM offsets
+ */
+#define SOE_EMEM_CHANNEL_CMDQ_OFFSET 0x1000080
+#define SOE_EMEM_CHANNEL_MSGQ_OFFSET 0x1000000
 
 /*!
  * Defines the logical queue IDs that must be used when submitting commands

src/common/nvswitch/interface/ctrl_dev_nvswitch.h

@@ -85,10 +85,11 @@ typedef enum nvswitch_get_info_index
     NVSWITCH_GET_INFO_INDEX_ENABLED_PORTS_MASK_63_32,
     NVSWITCH_GET_INFO_INDEX_NUM_VCS,
     NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_TABLE_SIZE,
-    NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_EXTA_TABLE_SIZE,
-    NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_EXTB_TABLE_SIZE,
     NVSWITCH_GET_INFO_INDEX_ROUTING_ID_TABLE_SIZE,
     NVSWITCH_GET_INFO_INDEX_ROUTING_LAN_TABLE_SIZE,
+    NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_EXTA_TABLE_SIZE,
+    NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_EXTB_TABLE_SIZE,
+    NVSWITCH_GET_INFO_INDEX_REMAP_POLICY_MULTICAST_TABLE_SIZE,
 
     NVSWITCH_GET_INFO_INDEX_FREQ_KHZ = 0x200,
     NVSWITCH_GET_INFO_INDEX_VCOFREQ_KHZ,
@@ -105,6 +106,9 @@ typedef enum nvswitch_get_info_index
 #define NVSWITCH_GET_INFO_INDEX_ARCH_LR10     0x02
 #define NVSWITCH_GET_INFO_INDEX_IMPL_LR10     0x01
 
+#define NVSWITCH_GET_INFO_INDEX_ARCH_LS10     0x03
+#define NVSWITCH_GET_INFO_INDEX_IMPL_LS10     0x01
+
 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_UNKNOWN    0x00
 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_RTLSIM     0x01
 #define NVSWITCH_GET_INFO_INDEX_PLATFORM_FMODEL     0x02
@@ -352,7 +356,8 @@ typedef enum nvswitch_table_select_remap
     NVSWITCH_TABLE_SELECT_REMAP_PRIMARY = 0,
     NVSWITCH_TABLE_SELECT_REMAP_EXTA,
     NVSWITCH_TABLE_SELECT_REMAP_EXTB,
-    NVSWITCH_TABLE_SELECT_REMAP_MULTICAST
+    NVSWITCH_TABLE_SELECT_REMAP_MULTICAST,
+    NVSWITCH_TABLE_SELECT_REMAP_MAX
 } NVSWITCH_TABLE_SELECT_REMAP;
 
 typedef struct nvswitch_set_remap_policy
@@ -826,6 +831,29 @@ typedef enum nvswitch_err_type
     NVSWITCH_ERR_HW_NPORT_INGRESS_RIDTAB_ECC_LIMIT_ERR                 = 11022,
     NVSWITCH_ERR_HW_NPORT_INGRESS_RLANTAB_ECC_LIMIT_ERR                = 11023,
     NVSWITCH_ERR_HW_NPORT_INGRESS_ADDRTYPEERR                          = 11024,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_INDEX_ERR               = 11025,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_INDEX_ERR               = 11026,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_INDEX_ERR                 = 11027,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_DBE_ERR             = 11028,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_DBE_ERR             = 11029,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ECC_DBE_ERR               = 11030,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_REQCONTEXTMISMATCHERR   = 11031,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_REQCONTEXTMISMATCHERR   = 11032,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_REQCONTEXTMISMATCHERR     = 11033,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ACLFAIL                 = 11034,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ACLFAIL                 = 11035,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ACLFAIL                   = 11036,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ADDRBOUNDSERR           = 11037,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ADDRBOUNDSERR           = 11038,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ADDRBOUNDSERR             = 11039,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ECC_LIMIT_ERR           = 11040,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ECC_LIMIT_ERR           = 11041,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ECC_LIMIT_ERR             = 11042,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_MCCMDTOUCADDRERR                     = 11043,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_READMCREFLECTMEMERR                  = 11044,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTAREMAPTAB_ADDRTYPEERR             = 11045,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_EXTBREMAPTAB_ADDRTYPEERR             = 11046,
+    NVSWITCH_ERR_HW_NPORT_INGRESS_MCREMAPTAB_ADDRTYPEERR               = 11047,
     NVSWITCH_ERR_HW_NPORT_INGRESS_LAST, /* NOTE: Must be last */
 
     /* NPORT: Egress errors */
@@ -863,9 +891,24 @@ typedef enum nvswitch_err_type
     NVSWITCH_ERR_HW_NPORT_EGRESS_NCISOC_CREDIT_PARITY_ERR              = 12031,
     NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_FLITTYPE_MISMATCH_ERR           = 12032,
     NVSWITCH_ERR_HW_NPORT_EGRESS_CREDIT_TIME_OUT_ERR                   = 12033,
-    NVSWITCH_ERR_HW_NPORT_EGRESS_TIMESTAMP_LOG                         = 12034,
-    NVSWITCH_ERR_HW_NPORT_EGRESS_MISC_LOG                              = 12035,
-    NVSWITCH_ERR_HW_NPORT_EGRESS_HEADER_LOG                            = 12036,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_INVALIDVCSET_ERR                      = 12034,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_SIDEBAND_PD_PARITY_ERR          = 12035,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_LIMIT_ERR     = 12036,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_ECC_DBE_ERR       = 12037,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_LIMIT_ERR          = 12038,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSPCTRLSTORE_ECC_DBE_ERR            = 12039,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_LIMIT_ERR             = 12040,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_RBCTRLSTORE_ECC_DBE_ERR               = 12041,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDSGT_ECC_LIMIT_ERR                = 12042,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDSGT_ECC_DBE_ERR                  = 12043,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDBUF_ECC_LIMIT_ERR                = 12044,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_MCREDBUF_ECC_DBE_ERR                  = 12045,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_LIMIT_ERR           = 12046,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_RAM_HDR_ECC_DBE_ERR             = 12047,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_HDR_PARITY_ERR        = 12048,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_NXBAR_REDUCTION_FLITTYPE_MISMATCH_ERR = 12049,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_MCRSP_CNT_ERR                         = 12050,
+    NVSWITCH_ERR_HW_NPORT_EGRESS_RBRSP_CNT_ERR                         = 12051,
     NVSWITCH_ERR_HW_NPORT_EGRESS_LAST, /* NOTE: Must be last */
 
     /* NPORT: Fstate errors */
@@ -917,7 +960,7 @@ typedef enum nvswitch_err_type
     NVSWITCH_ERR_HW_NPORT_ROUTE_NVS_ECC_LIMIT_ERR                      = 15011,
     NVSWITCH_ERR_HW_NPORT_ROUTE_NVS_ECC_DBE_ERR                        = 15012,
     NVSWITCH_ERR_HW_NPORT_ROUTE_CDTPARERR                              = 15013,
-    NVSWITCH_ERR_HW_NPORT_ROUTE_LAST, /* NOTE: Must be last */
+    NVSWITCH_ERR_HW_NPORT_ROUTE_LAST = 15021, /* NOTE: Must be last */
 
     /* NPORT: Nport errors */
     NVSWITCH_ERR_HW_NPORT                                              = 16000,
@@ -1153,6 +1196,9 @@ typedef enum nvswitch_err_type
     NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN0_TD_CRUMBSTORE_ECC_DBE_ERR    = 24005,
     NVSWITCH_ERR_HW_NPORT_SOURCETRACK_CREQ_TCEN1_CRUMBSTORE_ECC_DBE_ERR       = 24006,
     NVSWITCH_ERR_HW_NPORT_SOURCETRACK_SOURCETRACK_TIME_OUT_ERR                = 24007,
+    NVSWITCH_ERR_HW_NPORT_SOURCETRACK_DUP_CREQ_TCEN0_TAG_ERR                  = 24008,
+    NVSWITCH_ERR_HW_NPORT_SOURCETRACK_INVALID_TCEN0_RSP_ERR                   = 24009,
+    NVSWITCH_ERR_HW_NPORT_SOURCETRACK_INVALID_TCEN1_RSP_ERR                   = 24010,
     NVSWITCH_ERR_HW_NPORT_SOURCETRACK_LAST, /* NOTE: Must be last */
 
     /* NVLIPT_LNK errors */
@@ -1300,6 +1346,8 @@ typedef struct nvswitch_set_latency_bins
  *      Set true, if the port is AC coupled.
  *   enableVC1 [IN]
  *      Set true, if VC1 should be enabled for the port.
+ *   trunkSrcMask [IN]
+ *      Mask of source trunk ports.
  */
 
 typedef enum nvswitch_connection_type
@@ -1328,6 +1376,7 @@ typedef struct nvswitch_set_switch_port_config
     NvU32  count;
     NvBool acCoupled;
     NvBool enableVC1;
+    NvU64  trunkSrcMask;
 
 } NVSWITCH_SET_SWITCH_PORT_CONFIG;
 
@@ -1652,6 +1701,7 @@ typedef struct
 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_2_2          (0x00000004)
 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_3_0          (0x00000005)
 #define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_3_1          (0x00000006)
+#define NVSWITCH_NVLINK_CAPS_NVLINK_VERSION_4_0          (0x00000007)
 
 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_INVALID         (0x00000000)
 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_1_0             (0x00000001)
@@ -1659,6 +1709,7 @@ typedef struct
 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_2_2             (0x00000004)
 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_3_0             (0x00000005)
 #define NVSWITCH_NVLINK_CAPS_NCI_VERSION_3_1             (0x00000006)
+#define NVSWITCH_NVLINK_CAPS_NCI_VERSION_4_0             (0x00000007)
 
 
 /*
@@ -1769,6 +1820,9 @@ typedef struct
     // LR10+ only
     NvU32   laneRxdetStatusMask;
 
+    // LS10+ only
+    NvBool  bIsRepeaterMode;
+
     NVSWITCH_NVLINK_DEVICE_INFO remoteDeviceInfo;
     NVSWITCH_NVLINK_DEVICE_INFO localDeviceInfo;
 } NVSWITCH_NVLINK_LINK_STATUS_INFO;
@@ -1926,6 +1980,24 @@ typedef struct
 #define NVSWITCH_THERM_CHANNEL_LR10_TDIODE_OFFSET      0x03
 #define NVSWITCH_NUM_CHANNELS_LR10                        4
 
+/*
+ * Laguna Seca thermal channels
+ */
+#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_MAX         0x00
+#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_OFFSET_MAX  0x01
+#define NVSWITCH_THERM_CHANNEL_LS10_TDIODE             0x02
+#define NVSWITCH_THERM_CHANNEL_LS10_TDIODE_OFFSET      0x03
+#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_0           0x04
+#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_1           0x05
+#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_2           0x06
+#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_3           0x07
+#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_4           0x08
+#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_5           0x09
+#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_6           0x0A
+#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_7           0x0B
+#define NVSWITCH_THERM_CHANNEL_LS10_TSENSE_8           0x0C
+#define NVSWITCH_NUM_CHANNELS_LS10                       13
+
 /*
  * CTRL_NVSWITCH_GET_THROUGHPUT_COUNTERS
  *
@@ -2094,7 +2166,8 @@ typedef struct nvswitch_set_training_error_info
 #define NVSWITCH_DEVICE_EVENT_NONFATAL        1
 #define NVSWITCH_DEVICE_EVENT_PORT_UP         2
 #define NVSWITCH_DEVICE_EVENT_PORT_DOWN       3
-#define NVSWITCH_DEVICE_EVENT_COUNT           4
+#define NVSWITCH_DEVICE_EVENT_INBAND_DATA     4
+#define NVSWITCH_DEVICE_EVENT_COUNT           5
 #define NVSWITCH_REGISTER_EVENTS_MAX_EVENT_IDS (500)
 
 /*
@@ -2784,6 +2857,140 @@ typedef struct nvswitch_get_rd_stall_busy
     NVSWITCH_STALL_BUSY vc1;
 } NVSWITCH_GET_RB_STALL_BUSY;
 
+/*
+ * CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR
+ *
+ * Control for querying multicast ID error vector
+ *
+ * Parameters:
+ *  [in] link
+ *    Link number on which the error vector is requested
+ *
+ *  [out] error_vector[]
+ *      Bit vector of multicast IDs that are in error.
+ */
+
+#define NVSWITCH_MC_ID_ERROR_VECTOR_COUNT   128
+
+typedef struct nvswitch_get_multicast_id_error_vector
+{
+    NvU32 link;
+    NvU32 error_vector[NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / sizeof(NvU32)];
+} NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR;
+
+/*
+ * CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR
+ *
+ * Control for clearing multicast ID error vector
+ *
+ * Parameters:
+ *  [in] link
+ *    Link number on which the error vector clear is requested
+ *
+ *  [in] error_vector[]
+ *      Bit vector of multicast IDs to clear error.
+ */
+
+typedef struct nvswitch_clear_multicast_id_error_vector
+{
+    NvU32 link;
+    NvU32 error_vector[NVSWITCH_MC_ID_ERROR_VECTOR_COUNT / sizeof(NvU32)];
+} NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR;
+
+#define NVSWITCH_INBAND_DATA_SIZE 4096
+
+/*
+ * CTRL_NVSWITCH_INBAND_SEND_DATA
+ * 
+ * Control call used for sending data over inband.
+ *
+ * Parameters:
+ *
+ *    dataSize[IN]
+ *      Valid data in the buffer
+ *
+ *    linkId[IN]
+ *      Link number on which the data needs to be sent
+ *
+ *    buffer[IN]
+ *      Data which needs to be sent on the other side
+ *
+ *    dataSent [OUT]
+ *      Bytes of data which were sent to the other side
+ */
+typedef struct nvswitch_inband_send_data_params
+{
+    /* input parameters */
+    NvU32 dataSize;
+    NvU32 linkId;
+    NvU8  buffer[NVSWITCH_INBAND_DATA_SIZE];
+
+    /* output parameters */
+    NvU32 dataSent;
+} NVSWITCH_INBAND_SEND_DATA_PARAMS;
+
+/*
+ * CTRL_NVSWITCH_INBAND_READ_DATA
+ * 
+ * Control call used for reading data received over inband
+ *
+ * Parameters:
+ *
+ *    linkId[IN]
+ *      Link number on which the data needs to be read.
+ *
+ *    dataSize[OUT]
+ *      Valid data in the buffer
+ *
+ *    buffer[OUT]
+ *      Data which needs to be read from the other side
+ */
+typedef struct nvswitch_inband_read_data_params
+{
+    /* input parameters */
+    NvU32 linkId;
+
+    /* output parameters */
+    NvU32 dataSize;
+    NvU8  buffer[NVSWITCH_INBAND_DATA_SIZE];
+} NVSWITCH_INBAND_READ_DATA_PARAMS;
+
+/*
+ * CTRL_NVSWITCH_INBAND_FLUSH_DATA
+ * 
+ * Flushing all the pending data for the corresponding link.
+ * Messages would be stored in a queue. If flush is send all the
+ * pending messages which are there for that linkId will be deleted.
+ *
+ * Parameters:
+ *
+ *    linkMask[IN]
+ *      Mask of Links on which the data needs to be flushed.
+ */
+typedef struct nvswitch_inband_flush_data_params
+{
+    /* input parameters */
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+
+    /* output parameters */
+} NVSWITCH_INBAND_FLUSH_DATA_PARAMS;
+
+/*
+ * CTRL_NVSWITCH_INBAND_PENDING_DATA_STATS
+ * 
+ * Control call to check which links have pending data
+ *
+ * Parameters:
+ *
+ *    linkMask[OUT]
+ *      Mask of the links which has data on it.
+ */
+typedef struct nvswitch_inband_pending_data_stats_params
+{
+    /* output parameters */
+    NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
+} NVSWITCH_INBAND_PENDING_DATA_STATS_PARAMS;
+
 #define NVSWITCH_GET_SW_INFO_COUNT_MAX 32
 
 typedef enum nvswitch_get_sw_info_index
@@ -3106,6 +3313,12 @@ typedef struct
 #define CTRL_NVSWITCH_RESERVED_3                            0x3A
 #define CTRL_NVSWITCH_RESERVED_4                            0x3B
 #define CTRL_NVSWITCH_RESERVED_5                            0x3C
+#define CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR         0x3D
+#define CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR       0x3E
+#define CTRL_NVSWITCH_INBAND_SEND_DATA                      0x43
+#define CTRL_NVSWITCH_INBAND_READ_DATA                      0x44
+#define CTRL_NVSWITCH_INBAND_FLUSH_DATA                     0x45
+#define CTRL_NVSWITCH_INBAND_PENDING_DATA_STATS             0x46
 #define CTRL_NVSWITCH_GET_SW_INFO                           0x47
 #define CTRL_NVSWITCH_RESERVED_6                            0x48
 #define CTRL_NVSWITCH_RESERVED_7                            0x49

src/common/nvswitch/kernel/flcn/flcnqueue_nvswitch.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2018-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -1405,29 +1405,14 @@ _flcnQueueCmdPostNonBlocking_IMPL
     }
 
     // Falcon must be in a ready state before commands may be submitted.
-    if (!pFlcn->bOSReady)
+    status = soeWaitForInitAck_HAL(device,  (PSOE)pFlcn->pFlcnable);
+    if (status != NV_OK)
     {
-        if (pFlcn->engineTag != ENG_TAG_SOE) {
-            NVSWITCH_PRINT(device, ERROR,
-                "%s: FLCN not ready for command processing\n",
-                __FUNCTION__);
-            return NV_ERR_INVALID_STATE;
-        }
-        else
-        {
-            SOE *pSoe = (PSOE)pFlcn->pFlcnable;
-
-            status = soeWaitForInitAck(device, pSoe);
-
-            if (status != NV_OK || !pFlcn->bOSReady)
-            {
-                NVSWITCH_PRINT(device, ERROR,
-                    "%s: SOE not ready for command processing\n",
-                    __FUNCTION__);
-                NVSWITCH_ASSERT(0);
-                return status;
-            }
-        }
+        NVSWITCH_PRINT(device, ERROR,
+            "%s: SOE not ready for command processing\n",
+            __FUNCTION__);
+        NVSWITCH_ASSERT(0);
+        return status;
     }
 
     // Sanity check the command input.

src/common/nvswitch/kernel/inc/common_nvswitch.h

@@ -389,6 +389,9 @@ struct nvswitch_device
 
     // List of client events
     NVListRec                            client_events_list;
+
+    // To be removed once newer vbios is on TOT.
+    NvBool  bIsNvlinkVbiosTableVersion2;
 };
 
 #define NVSWITCH_IS_DEVICE_VALID(device) \
@@ -485,6 +488,7 @@ typedef struct NVSWITCH_TIMEOUT
 #define NVSWITCH_INTERVAL_1MSEC_IN_NS     1000000LL
 #define NVSWITCH_INTERVAL_5MSEC_IN_NS     5000000LL
 #define NVSWITCH_INTERVAL_1SEC_IN_NS      1000000000LL
+#define NVSWITCH_INTERVAL_4SEC_IN_NS      4000000000LL
 
 #define NVSWITCH_HEARTBEAT_INTERVAL_NS    NVSWITCH_INTERVAL_1SEC_IN_NS
 
@@ -505,6 +509,7 @@ do                                                              \
 #define NVSWITCH_SET_CAP(tbl,cap,field) ((tbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)]) |= (0?cap##field))
 
 NvBool nvswitch_is_lr10_device_id(NvU32 device_id);
+NvBool nvswitch_is_ls10_device_id(NvU32 device_id);
 
 NvU32 nvswitch_reg_read_32(nvswitch_device *device, NvU32 offset);
 void nvswitch_reg_write_32(nvswitch_device *device, NvU32 offset, NvU32 data);
@@ -529,6 +534,10 @@ void      nvswitch_setup_link_loopback_mode(nvswitch_device *device, NvU32 linkN
 void      nvswitch_reset_persistent_link_hw_state(nvswitch_device *device, NvU32 linkNumber);
 void      nvswitch_store_topology_information(nvswitch_device *device, nvlink_link *link);
 
+NvlStatus nvswitch_launch_ALI(nvswitch_device *device);
+NvlStatus nvswitch_launch_ALI_link_training(nvswitch_device *device, nvlink_link *link, NvBool bSync);
+NvlStatus nvswitch_inband_read_data(nvswitch_device *device, NvU8 *dest, NvU32 linkId, NvU32 *dataSize);
+void      nvswitch_filter_messages(nvswitch_device *device, NvU32 linkId);
 NvlStatus nvswitch_set_training_mode(nvswitch_device *device);
 NvBool    nvswitch_is_link_in_reset(nvswitch_device *device, nvlink_link *link);
 void      nvswitch_apply_recal_settings(nvswitch_device *device, nvlink_link *link);

src/common/nvswitch/kernel/inc/error_nvswitch.h

@@ -61,9 +61,27 @@ typedef struct
     NvU32 data[4];              // record of interrupt specific data
 } NVSWITCH_INTERRUPT_LOG_TYPE;
 
+#define NVSWITCH_RAW_ERROR_LOG_DATA_SIZE    16
+
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_TIME     BIT(0)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_MISC     BIT(1)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR      BIT(2)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_TIME   BIT(3)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_MISC   BIT(4)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR    BIT(5)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_TIME    BIT(6)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MISC    BIT(7)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_HDR     BIT(8)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_TIME BIT(9)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_MISC BIT(10)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_EGRESS_MC_HDR  BIT(11)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_MC_TIME        BIT(12)
+#define NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_RED_TIME       BIT(13)
+
 typedef struct
 {
-    NvU32 data[16];
+    NvU32 flags;
+    NvU32 data[NVSWITCH_RAW_ERROR_LOG_DATA_SIZE];
 } NVSWITCH_RAW_ERROR_LOG_TYPE;
 
 #define NVSWITCH_ERROR_NEXT_LOCAL_NUMBER(log) (log->error_total)

src/common/nvswitch/kernel/inc/flcn/haldefs_flcn_nvswitch.h

@@ -97,6 +97,7 @@ void flcnQueueSetupHal(struct FLCN *pFlcn);
 void flcnRtosSetupHal(struct FLCN *pFlcn);
 void flcnQueueRdSetupHal(struct FLCN *pFlcn);
 
+void flcnSetupHal_LS10(struct FLCN *pFlcn);
 void flcnSetupHal_LR10(struct FLCN *pFlcn);
 
 void flcnSetupHal_v03_00(struct FLCN *pFlcn);

src/common/nvswitch/kernel/inc/haldef_nvswitch.h

@@ -79,6 +79,8 @@
     _op(NvlStatus, nvswitch_ctrl_get_ingress_response_table, (nvswitch_device *device, NVSWITCH_GET_INGRESS_RESPONSE_TABLE_PARAMS *params), _arch)  \
     _op(NvlStatus, nvswitch_ctrl_set_ingress_response_table, (nvswitch_device *device, NVSWITCH_SET_INGRESS_RESPONSE_TABLE *p), _arch)  \
     _op(NvlStatus, nvswitch_ctrl_set_ganged_link_table,      (nvswitch_device *device, NVSWITCH_SET_GANGED_LINK_TABLE *p), _arch)  \
+    _op(void,      nvswitch_init_npg_multicast,     (nvswitch_device *device), _arch)  \
+    _op(void,      nvswitch_init_warm_reset,        (nvswitch_device *device), _arch)  \
     _op(NvlStatus, nvswitch_ctrl_set_remap_policy,  (nvswitch_device *device, NVSWITCH_SET_REMAP_POLICY *p), _arch)  \
     _op(NvlStatus, nvswitch_ctrl_get_remap_policy,  (nvswitch_device *device, NVSWITCH_GET_REMAP_POLICY_PARAMS *params), _arch)  \
     _op(NvlStatus, nvswitch_ctrl_set_remap_policy_valid, (nvswitch_device *device, NVSWITCH_SET_REMAP_POLICY_VALID *p), _arch)  \
@@ -114,15 +116,15 @@
     _op(NvlStatus, nvswitch_ctrl_get_fom_values,    (nvswitch_device *device, NVSWITCH_GET_FOM_VALUES_PARAMS *p), _arch)  \
     _op(NvlStatus, nvswitch_deassert_link_reset,    (nvswitch_device *device, nvlink_link *link), _arch)  \
     _op(NvBool,    nvswitch_is_soe_supported,       (nvswitch_device *device), _arch)  \
-    _op(NvlStatus, nvswitch_soe_set_ucode_core,     (nvswitch_device *device, NvBool bFalcon), _arch)  \
     _op(NvlStatus, nvswitch_init_soe, (nvswitch_device *device), _arch)  \
     _op(NvBool,    nvswitch_is_inforom_supported,   (nvswitch_device *device), _arch)  \
     _op(NvBool,    nvswitch_is_spi_supported,       (nvswitch_device *device), _arch)  \
     _op(NvBool,    nvswitch_is_smbpbi_supported,   (nvswitch_device *device), _arch)  \
-    _op(NvlStatus, nvswitch_soe_prepare_for_reset, (nvswitch_device *device), _arch)  \
     _op(NvlStatus, nvswitch_post_init_device_setup, (nvswitch_device *device), _arch)  \
     _op(void,      nvswitch_post_init_blacklist_device_setup, (nvswitch_device *device), _arch)  \
     _op(NvlStatus, nvswitch_setup_link_system_registers, (nvswitch_device *device), _arch)  \
+    _op(NvlStatus, nvswitch_read_vbios_link_entries, (nvswitch_device *device, NvU32 tblPtr,NvU32 expected_link_entriesCount,NVLINK_CONFIG_DATA_LINKENTRY *link_entries, NvU32 *identified_link_entriesCount), _arch)  \
+    _op(NvlStatus, nvswitch_vbios_read_structure, (nvswitch_device *device, void *structure, NvU32 offset, NvU32 *ppacked_size, const char *format), _arch)  \
     _op(NvlStatus, nvswitch_get_nvlink_ecc_errors,  (nvswitch_device *device, NVSWITCH_GET_NVLINK_ECC_ERRORS_PARAMS *p), _arch)  \
     _op(NvlStatus, nvswitch_inforom_ecc_log_error_event, (nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, INFOROM_NVS_ECC_ERROR_EVENT *error_event), _arch)  \
     _op(void,      nvswitch_oms_set_device_disable, (INFOROM_OMS_STATE *pOmsState, NvBool bForceDeviceDisable), _arch)  \
@@ -184,7 +186,6 @@
     _op(NvlStatus, nvswitch_init_nxbar,      (nvswitch_device *device), _arch)  \
     _op(NvlStatus, nvswitch_clear_nport_rams,       (nvswitch_device *device), _arch)  \
     _op(NvlStatus, nvswitch_pri_ring_init,          (nvswitch_device *device), _arch)  \
-    _op(NvlStatus, nvswitch_get_soe_ucode_binaries, (nvswitch_device *device, const NvU32 **soe_ucode_data, const NvU32 **soe_ucode_header), _arch)  \
     _op(NvlStatus, nvswitch_get_remap_table_selector,   (nvswitch_device *device, NVSWITCH_TABLE_SELECT_REMAP table_selector, NvU32 *remap_ram_sel), _arch)  \
     _op(NvU32,     nvswitch_get_ingress_ram_size,   (nvswitch_device *device, NvU32 ingress_ram_selector), _arch)  \
     _op(NvlStatus, nvswitch_minion_get_dl_status,   (nvswitch_device *device, NvU32 linkId, NvU32 statusIdx, NvU32 statusArgs, NvU32 *statusData), _arch)  \
@@ -202,14 +203,22 @@
     _op(NvBool,    nvswitch_is_link_in_reset, (nvswitch_device *device, nvlink_link *link), _arch) \
     _op(void,      nvswitch_init_buffer_ready, (nvswitch_device *device, nvlink_link * link, NvBool bNportBufferReady), _arch) \
     _op(NvlStatus, nvswitch_ctrl_get_nvlink_lp_counters, (nvswitch_device *device, NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS *p), _arch) \
-    _op(NvlStatus, nvswitch_ctrl_set_residency_bins, (nvswitch_device *device, NVSWITCH_SET_RESIDENCY_BINS *p), _arch) \
-    _op(NvlStatus, nvswitch_ctrl_get_residency_bins, (nvswitch_device *device, NVSWITCH_GET_RESIDENCY_BINS *p), _arch) \
     _op(void,      nvswitch_apply_recal_settings, (nvswitch_device *device, nvlink_link *), _arch) \
     _op(NvlStatus, nvswitch_service_nvldl_fatal_link, (nvswitch_device *device, NvU32 nvliptInstance, NvU32 link), _arch) \
-    _op(NvlStatus, nvswitch_ctrl_get_rb_stall_busy, (nvswitch_device *device, NVSWITCH_GET_RB_STALL_BUSY *p), _arch) \
     _op(NvlStatus, nvswitch_service_minion_link, (nvswitch_device *device, NvU32 link_id), _arch) \
     _op(NvlStatus, nvswitch_ctrl_get_sw_info,  (nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p), _arch)
 
+#define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \
+    _op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \
+    _op(NvlStatus, nvswitch_launch_ALI_link_training, (nvswitch_device *device, nvlink_link *link, NvBool bSync), _arch) \
+    _op(NvlStatus, nvswitch_ctrl_inband_send_data, (nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p), _arch) \
+    _op(NvlStatus, nvswitch_ctrl_inband_read_data, (nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p), _arch) \
+    _op(NvlStatus, nvswitch_ctrl_set_residency_bins, (nvswitch_device *device, NVSWITCH_SET_RESIDENCY_BINS *p), _arch) \
+    _op(NvlStatus, nvswitch_ctrl_get_residency_bins, (nvswitch_device *device, NVSWITCH_GET_RESIDENCY_BINS *p), _arch) \
+    _op(NvlStatus, nvswitch_ctrl_get_rb_stall_busy, (nvswitch_device *device, NVSWITCH_GET_RB_STALL_BUSY *p), _arch) \
+    _op(NvlStatus, nvswitch_ctrl_get_multicast_id_error_vector, (nvswitch_device *device, NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR *p), _arch) \
+    _op(NvlStatus, nvswitch_ctrl_clear_multicast_id_error_vector, (nvswitch_device *device, NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR *p), _arch) \
+
 //
 // Declare HAL function pointer table
 //
@@ -226,6 +235,7 @@
 typedef struct nvswitch_hal_functions
 {
     NVSWITCH_HAL_FUNCTION_LIST(DECLARE_HAL_FUNCTIONS, HAL)
+    NVSWITCH_HAL_FUNCTION_LIST_LS10(DECLARE_HAL_FUNCTIONS, HAL)
 
 } nvswitch_hal;
 
@@ -243,6 +253,9 @@ typedef struct nvswitch_hal_functions
 #define NVSWITCH_INIT_HAL(device, arch)                             \
     NVSWITCH_HAL_FUNCTION_LIST(CREATE_HAL_FUNCTIONS, arch)          \
 
+#define NVSWITCH_INIT_HAL_LS10(device, arch)                         \
+    NVSWITCH_HAL_FUNCTION_LIST_LS10(CREATE_HAL_FUNCTIONS, arch)      \
+
 //
 // Declare HAL function dispatch functions
 //
@@ -255,8 +268,10 @@ typedef struct nvswitch_hal_functions
     _return _function _params;
 
 NVSWITCH_HAL_FUNCTION_LIST(DECLARE_HAL_DISPATCHERS, unused_argument)
+NVSWITCH_HAL_FUNCTION_LIST_LS10(DECLARE_HAL_DISPATCHERS, unused_argument)
 
 // HAL functions
 void nvswitch_setup_hal_lr10(nvswitch_device *device);
+void nvswitch_setup_hal_ls10(nvswitch_device *device);
 
 #endif //_HALDEF_NVSWITCH_H_

src/common/nvswitch/kernel/inc/io_nvswitch.h

@@ -24,6 +24,9 @@
 #ifndef _IO_NVSWITCH_H_
 #define _IO_NVSWITCH_H_
 
+#include "nv_list.h"
+#include "ctrl_dev_nvswitch.h"
+
 // NVSWITCH_REG_* MMIO wrappers are to be used for absolute symbolic BAR0 offset
 // register  references like SMC, CLOCK, BUS, and PRIV_MASTER.
 //
@@ -92,11 +95,7 @@ typedef struct engine_descriptor
 // NVSWITCH_REG_RD/WR IO wrappers.
 //
 
-#define NVSWITCH_LIST_ALL_ENGINES(_op)      \
-    _op(XVE)                                \
-    _op(SAW)                                \
-    _op(SOE)                                \
-    _op(SMR)                                \
+#define NVSWITCH_LIST_LS10_ONLY_ENGINES(_op)     \
     _op(GIN)                                \
     _op(XAL)                                \
     _op(XAL_FUNC)                           \
@@ -124,6 +123,15 @@ typedef struct engine_descriptor
     _op(SYSB_PRI_RS_CTRL)                   \
     _op(PRI_MASTER_RS)                      \
     _op(PTIMER)                             \
+    _op(CPR)                                \
+    _op(TILEOUT)                            \
+    _op(TILEOUT_PERFMON)                    \
+
+#define NVSWITCH_LIST_ALL_ENGINES(_op)      \
+    _op(XVE)                                \
+    _op(SAW)                                \
+    _op(SOE)                                \
+    _op(SMR)                                \
                                             \
     _op(NPG)                                \
     _op(NPORT)                              \
@@ -134,11 +142,9 @@ typedef struct engine_descriptor
     _op(NVLIPT_LNK)                         \
     _op(NVLTLC)                             \
     _op(NVLDL)                              \
-    _op(CPR)                                \
                                             \
     _op(NXBAR)                              \
     _op(TILE)                               \
-    _op(TILEOUT)                            \
                                             \
     _op(NPG_PERFMON)                        \
     _op(NPORT_PERFMON)                      \
@@ -149,7 +155,6 @@ typedef struct engine_descriptor
                                             \
     _op(NXBAR_PERFMON)                      \
     _op(TILE_PERFMON)                       \
-    _op(TILEOUT_PERFMON)                    \
 
 #define ENGINE_ID_LIST(_eng)                \
     NVSWITCH_ENGINE_ID_##_eng,
@@ -164,6 +169,7 @@ typedef struct engine_descriptor
 typedef enum nvswitch_engine_id
 {
     NVSWITCH_LIST_ALL_ENGINES(ENGINE_ID_LIST)
+    NVSWITCH_LIST_LS10_ONLY_ENGINES(ENGINE_ID_LIST)
     NVSWITCH_ENGINE_ID_SIZE,
 } NVSWITCH_ENGINE_ID;
 
@@ -312,30 +318,30 @@ typedef enum nvswitch_engine_id
 
 #define NVSWITCH_MAX_SEED_BUFFER_SIZE         NVSWITCH_MAX_SEED_NUM + 1
 
-#define NVSWITCH_MAX_INBAND_BUFFER_SIZE       256*8
-#define NVSWITCH_MAX_INBAND_BITS_SENT_AT_ONCE 32
-#define NVSWITCH_MAX_INBAND_BUFFER_ENTRIES    NVSWITCH_MAX_INBAND_BUFFER_SIZE/NVSWITCH_MAX_INBAND_BITS_SENT_AT_ONCE
-
 //
-// Inband data structure
+// Storing list entries for sending to FM 
 //
-struct nvswitch_inband_data
+typedef struct
 {
-    // Inband bufer at sender Minion
-    NvU32  sendBuffer[NVSWITCH_MAX_INBAND_BUFFER_ENTRIES];
+    NVListRec entry;
+    NvU8      data[NVSWITCH_INBAND_DATA_SIZE];
+    NvU32     dataSize;
+} nvswitch_inband_data_list;
 
-    // Inband buffer at receiver Minion
-    NvU32  receiveBuffer[NVSWITCH_MAX_INBAND_BUFFER_ENTRIES];
+typedef struct
+{
+    // Temp entry being received
+    nvswitch_inband_data_list *message;
 
-    // Is the current Minion a sender or receiver of Inband Data?
-    NvBool bIsSenderMinion;
+    //
+    // Persistent messages are stored even if the listener (e.g. FM) is
+    // not present.
+    //
+    NVListRec persistent_list;
 
-    // Bool to say fail or not
-    NvBool bTransferFail;
-
-    // # of transmisions done - count
-    // NvU32 txCount;
-};
+    // Stores messages if and only if the listener is present.
+    NVListRec nonpersistent_list;
+} nvswitch_inband_receive_data;
 
 typedef struct
 {
@@ -347,14 +353,21 @@ typedef struct
     NvBool egress_packet_latched;
 
     NvBool nea;    // Near end analog
-    NvBool ned;    // Near end digital
+    NvBool nedr;   // Near end digital
+    NvBool nedw;
 
     NvU32  lane_rxdet_status_mask;
 
     NvBool bIsRepeaterMode;
 
+    // Check if BUFFER_COMPLETE is seen
+    volatile NvBool isBufferComplete;
+
+    // Check if BUFFER_FAIL is seen
+    volatile NvBool isBufferFail;
+
     // Minion Inband Data structure
-    struct nvswitch_inband_data inBandData;
+    nvswitch_inband_receive_data inbandData;
 
 } NVSWITCH_LINK_TYPE;
 

src/common/nvswitch/kernel/inc/lr10/lr10.h

@@ -352,7 +352,7 @@ typedef NVSWITCH_LINK_TYPE  NVSWITCH_LINK_TYPE_LR10;
 //
 
 //
-// LR10 supports CREQ0(0), DNGRD(1), ATR(2), ATSD(3), PROBE(4), RSP0(5), CREQ1(6), and RSP1(7) VCs. 
+// LR10 supports CREQ0(0), DNGRD(1), ATR(2), ATSD(3), PROBE(4), RSP0(5), CREQ1(6), and RSP1(7) VCs.
 // But DNGRD(1), ATR(2), ATSD(3), and PROBE(4) will be never used as PowerPC ATS support is not a POR for LR10 HW.
 //
 #define NVSWITCH_NUM_VCS_LR10    8
@@ -436,7 +436,7 @@ typedef struct
 // In order to collect all the useful unit information into a single container,
 // we need to pick where to find each piece within the parsed discovery table.
 // Top level IP wrappers like NPG have a BCAST range to broadcast reads/writes,
-// but IP sub-units like NPORT have a MULTICAST range within the BCAST IP 
+// but IP sub-units like NPORT have a MULTICAST range within the BCAST IP
 // wrapper to broadcast to all the sub-units in all the IP wrappers.
 // So in the lists below top level IP wrappers (NPG, NVLW, and NXBAR) point
 // to the _BCAST IP wrapper, but sub-unit point to the _MULTICAST range inside
@@ -627,11 +627,11 @@ NvlStatus nvswitch_get_link_public_id_lr10(nvswitch_device *device, NvU32 linkId
 NvlStatus nvswitch_get_link_local_idx_lr10(nvswitch_device *device, NvU32 linkId, NvU32 *localLinkIdx);
 NvlStatus nvswitch_set_training_error_info_lr10(nvswitch_device *device,
                                                 NVSWITCH_SET_TRAINING_ERROR_INFO_PARAMS *pLinkTrainingErrorInfoParams);
+NvlStatus nvswitch_read_vbios_link_entries_lr10(nvswitch_device *device, NvU32 tblPtr,NvU32 entriesCount,NVLINK_CONFIG_DATA_LINKENTRY *link_entries, NvU32 *identified_entriesCount);
 NvlStatus nvswitch_ctrl_get_fatal_error_scope_lr10(nvswitch_device *device, NVSWITCH_GET_FATAL_ERROR_SCOPE_PARAMS *pParams);
 void      nvswitch_init_scratch_lr10(nvswitch_device *device);
 void      nvswitch_init_dlpl_interrupts_lr10(nvlink_link *link);
 NvlStatus nvswitch_init_nport_lr10(nvswitch_device *device);
-NvlStatus nvswitch_get_soe_ucode_binaries_lr10(nvswitch_device *device, const NvU32 **soe_ucode_data, const NvU32 **soe_ucode_header);
 NvlStatus nvswitch_poll_sublink_state_lr10(nvswitch_device *device, nvlink_link *link);
 void      nvswitch_setup_link_loopback_mode_lr10(nvswitch_device *device, NvU32 linkNumber);
 void nvswitch_reset_persistent_link_hw_state_lr10(nvswitch_device *device, NvU32 linkNumber);
@@ -646,8 +646,13 @@ void nvswitch_corelib_get_uphy_load_lr10(nvlink_link *link, NvBool *bUnlocked);
 void      nvswitch_init_buffer_ready_lr10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady);
 NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_LP_COUNTERS_PARAMS *params);
 NvlStatus nvswitch_service_nvldl_fatal_link_lr10(nvswitch_device *device, NvU32 nvliptInstance, NvU32 link);
+NvlStatus nvswitch_ctrl_inband_send_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_SEND_DATA_PARAMS *p);
+NvlStatus nvswitch_ctrl_inband_read_data_lr10(nvswitch_device *device, NVSWITCH_INBAND_READ_DATA_PARAMS *p);
+NvlStatus nvswitch_launch_ALI_link_training_lr10(nvswitch_device *device, nvlink_link *link, NvBool bSync);
 NvlStatus nvswitch_service_minion_link_lr10(nvswitch_device *device, NvU32 nvliptInstance);
 void      nvswitch_apply_recal_settings_lr10(nvswitch_device *device, nvlink_link *link);
 NvlStatus nvswitch_ctrl_get_sw_info_lr10(nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p);
 
+NvlStatus nvswitch_launch_ALI_lr10(nvswitch_device *device);
+
 #endif //_LR10_H_

src/common/nvswitch/kernel/inc/lr10/minion_lr10.h

@@ -92,4 +92,5 @@ NvU32     nvswitch_minion_get_data_rate_KiBps_lr10(nvswitch_device *device, NvU3
 NvlStatus nvswitch_set_minion_initialized_lr10(nvswitch_device *device, NvU32 idx_minion, NvBool initialized);
 NvBool    nvswitch_is_minion_initialized_lr10(nvswitch_device *device, NvU32 idx_minion);
 NvlStatus nvswitch_minion_clear_dl_error_counters_lr10(nvswitch_device *device, NvU32 linkId);
+
 #endif //_MINION_LR10_H_

src/common/nvswitch/kernel/inc/lr10/soe_lr10.h

@@ -58,10 +58,8 @@ typedef const struct
 // Internal function declarations
 //
 NvlStatus nvswitch_init_soe_lr10(nvswitch_device *device);
-NvlStatus nvswitch_soe_prepare_for_reset_lr10(nvswitch_device *device);
 void nvswitch_soe_unregister_events_lr10(nvswitch_device *device);
 void nvswitch_therm_soe_callback_lr10(nvswitch_device *device, union RM_FLCN_MSG *pMsg,
          void *pParams, NvU32 seqDesc, NV_STATUS status);
-NvlStatus nvswitch_soe_set_ucode_core_lr10(nvswitch_device *device, NvBool bFalcon);
 NvlStatus nvswitch_soe_register_event_callbacks_lr10(nvswitch_device *device);
 #endif //_SOE_LR10_H_

src/common/nvswitch/kernel/inc/regkey_nvswitch.h

@@ -229,15 +229,6 @@
 #define NV_SWITCH_REGKEY_SOE_DISABLE_NO         0x0
 #define NV_SWITCH_REGKEY_SOE_DISABLE_YES        0x1
 
-/*
- * NV_SWITCH_REGKEY_SOE_BOOT_CORE - Selects SOE core
- *
- * Public: Available in release drivers
- */
-#define NV_SWITCH_REGKEY_SOE_BOOT_CORE          "SoeBootCore"
-#define NV_SWITCH_REGKEY_SOE_BOOT_CORE_FALCON   0x0
-#define NV_SWITCH_REGKEY_SOE_BOOT_CORE_DEFAULT  0x2
-
 /*
  * NV_SWITCH_REGKEY_ENABLE_PM
  *
@@ -409,11 +400,18 @@
  *
  * When the regkey is set to FALCON, the Nvswitch driver will run MINION on Falcon core.
  *
+ * If set to RISCV, the MINION will run on RISCV core in Non-Manifest Mode.
+ * If set to RISCV_MANIFEST, the MINION will run on RISCV core in Manifest Mode.
+ *
+ * In the default option, RISCV_BCR_CTRL register will be used to get the default core.
+ *
  * Private: Debug use only
  */
 #define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET                "MinionSetUcodeTarget"
 #define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET_DEFAULT        0x0
 #define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET_FALCON         0x1
+#define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET_RISCV          0x2
+#define NV_SWITCH_REGKEY_MINION_SET_UCODE_TARGET_RISCV_MANIFEST 0x3
 
 /*
  * NV_SWITCH_REGKEY_MINION_SET_SIMMODE - Selects simmode settings to send to MINION
@@ -500,13 +498,14 @@
 /*
  * NV_SWITCH_REGKEY_LINK_TRAINING_SELECT - Select the Link training to be done
  *
- * This regkey will
+ * For LS10, links can be trained via non-ALI or ALI training. This regkey will
  * allow for overriding System Defaults and can force either training method
  * when desired.
  */
-
 #define NV_SWITCH_REGKEY_LINK_TRAINING_SELECT           "LinkTrainingMode"
 #define NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_DEFAULT   0x0
+#define NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_NON_ALI   0x1
+#define NV_SWITCH_REGKEY_LINK_TRAINING_SELECT_ALI       0x2
 /*
  * NV_SWITCH_REGKEY_I2C_ACCESS_CONTROL - Enable access to all I2C Ports/Devices
  *

src/common/nvswitch/kernel/inc/rom_nvswitch.h

@@ -547,6 +547,9 @@ nvswitch_read_rom_tables
 #define NVLINK_CONFIG_DATA_HEADER_20_SIZE   8
 #define NVLINK_CONFIG_DATA_HEADER_20_FMT    "6b1w"
 
+#define NVLINK_CONFIG_DATA_HEADER_VER_30    0x3
+#define NVLINK_CONFIG_DATA_HEADER_30_SIZE   8
+
 typedef struct _PCI_DATA_STRUCT
 {
     bios_U032       sig;                    //  00h: Signature, the string "PCIR" or NVIDIA's alternate "NPDS"
@@ -747,7 +750,9 @@ typedef struct _nvlink_Config_Data_Header_20
 #define NV_NVLINK_VBIOS_PARAM6_TXTRAIN_MINIMUM_TRAIN_TIME_EXPONENT           7:4
 
 #define NVLINK_CONFIG_DATA_BASEENTRY_FMT "1b"
-#define NVLINK_CONFIG_DATA_LINKENTRY_FMT "7b"
+#define NVLINK_CONFIG_DATA_LINKENTRY_FMT_20 "7b"
+#define NVLINK_CONFIG_DATA_LINKENTRY_FMT_30 "10b"
+
 // Version 2.0 Link Entry and Base Entry
 typedef struct _nvlink_config_data_baseentry_20
 {
@@ -764,9 +769,11 @@ typedef struct _nvlink_config_data_linkentry_20
      NvU8  nvLinkparam4;
      NvU8  nvLinkparam5;
      NvU8  nvLinkparam6;
+     NvU8  nvLinkparam7;
+     NvU8  nvLinkparam8;
+     NvU8  nvLinkparam9;
 } NVLINK_CONFIG_DATA_LINKENTRY;
 
-
 // Union of different VBIOS configuration table formats
 typedef union __nvlink_Config_Data_Header
 {
@@ -788,7 +795,22 @@ typedef struct _nvlink_vbios_config_data_linkentry_20
      bios_U008  nvLinkparam4;
      bios_U008  nvLinkparam5;
      bios_U008  nvLinkparam6;
-} NVLINK_VBIOS_CONFIG_DATA_LINKENTRY, *PNVLINK_VBIOS_CONFIG_DATA_LINKENTRY;
+} NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20, *PNVLINK_VBIOS_CONFIG_DATA_LINKENTRY_20;
+
+typedef struct _nvlink_vbios_config_data_linkentry_30
+{
+    // VBIOS configuration Data
+     bios_U008  nvLinkparam0;
+     bios_U008  nvLinkparam1;
+     bios_U008  nvLinkparam2;
+     bios_U008  nvLinkparam3;
+     bios_U008  nvLinkparam4;
+     bios_U008  nvLinkparam5;
+     bios_U008  nvLinkparam6;
+     bios_U008  nvLinkparam7;
+     bios_U008  nvLinkparam8;
+     bios_U008  nvLinkparam9;
+} NVLINK_VBIOS_CONFIG_DATA_LINKENTRY_30, *PNVLINK_VBIOS_CONFIG_DATA_LINKENTRY_30;
 
 //
 // NVSwitch driver structures

src/common/nvswitch/kernel/inc/soe/haldefs_soe_nvswitch.h

@@ -116,5 +116,6 @@ typedef struct {
 
 // HAL functions
 void soeSetupHal_LR10(struct SOE *pSoe);
+void soeSetupHal_LS10(struct SOE *pSoe);
 
 #endif //_HALDEFS_SOE_NVSWITCH_H_