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This commit is contained in:
Andy Ritger
2022-10-10 14:59:24 -07:00
parent fe0728787f
commit 90eb10774f
758 changed files with 88383 additions and 26493 deletions
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63
src/common/sdk/nvidia/inc/class/cl0000.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,63 +21,32 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0000_h_
#define _cl0000_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0000.finn
//
#include "nvtypes.h"
#include "nvlimits.h"
#include "cl0000_notification.h"
/* object NV01_NULL_OBJECT */
#define NV01_NULL_OBJECT (0x00000000)
#define NV01_NULL_OBJECT (0x00000000)
/* obsolete alises */
#define NV1_NULL_OBJECT NV01_NULL_OBJECT
#define NV1_NULL_OBJECT NV01_NULL_OBJECT
/*event values*/
#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0)
#define NV0000_NOTIFIERS_EVENT_NONE_PENDING (1)
#define NV0000_NOTIFIERS_VM_START (2)
#define NV0000_NOTIFIERS_GPU_BIND_EVENT (3)
#define NV0000_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (4)
#define NV0000_NOTIFIERS_MAXCOUNT (5)
/*Status definitions for NV0000_NOTIFIERS_DISPLAY_CHANGE event*/
#define NV0000_NOTIFIERS_STATUS_ACPI_DISPLAY_DEVICE_CYCLE (0)
//---------------------------------------------------------------------------
#define NV01_ROOT (0x00000000)
/* NvNotification[] fields and values */
#define NV000_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
#define NV01_ROOT (0x00000000)
/* NvAlloc parameteters */
typedef struct {
#define NV0000_ALLOC_PARAMETERS_MESSAGE_ID (0x0000U)
typedef struct NV0000_ALLOC_PARAMETERS {
NvHandle hClient; /* CORERM-2934: hClient must remain the first member until all allocations use these params */
NvU32 processID;
char processName[NV_PROC_NAME_MAX_LENGTH];
} NV0000_ALLOC_PARAMETERS;
/* pio method data structure */
typedef volatile struct _cl0000_tag0 {
NvV32 Reserved00[0x7c0];
} Nv000Typedef, Nv01Root;
/* obsolete aliases */
#define NV000_TYPEDEF Nv01Root
#define Nv1Root Nv01Root
#define nv1Root Nv01Root
#define nv01Root Nv01Root
/*event values*/
#define NV0000_NOTIFIERS_ENABLE_CPU_UTIL_CTRL (1)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0000_h_ */

68
src/common/sdk/nvidia/inc/class/cl0000_notification.h Normal file
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@@ -0,0 +1,68 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0000_notification_h_
#define _cl0000_notification_h_
#ifdef __cplusplus
extern "C" {
#endif
/*event values*/
#define NV0000_NOTIFIERS_DISPLAY_CHANGE (0)
#define NV0000_NOTIFIERS_EVENT_NONE_PENDING (1)
#define NV0000_NOTIFIERS_VM_START (2)
#define NV0000_NOTIFIERS_GPU_BIND_EVENT (3)
#define NV0000_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (4)
#define NV0000_NOTIFIERS_MAXCOUNT (5)
/*Status definitions for NV0000_NOTIFIERS_DISPLAY_CHANGE event*/
#define NV0000_NOTIFIERS_STATUS_ACPI_DISPLAY_DEVICE_CYCLE (0)
//---------------------------------------------------------------------------
/* NvNotification[] fields and values */
#define NV000_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0000_tag0 {
NvV32 Reserved00[0x7c0];
} Nv000Typedef, Nv01Root;
/* obsolete aliases */
#define NV000_TYPEDEF Nv01Root
#define Nv1Root Nv01Root
#define nv1Root Nv01Root
#define nv01Root Nv01Root
/*event values*/
#define NV0000_NOTIFIERS_ENABLE_CPU_UTIL_CTRL (1)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0000_notification_h_ */

43
src/common/sdk/nvidia/inc/class/cl0005.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,39 +21,32 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0005_h_
#define _cl0005_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0005.finn
//
#define NV01_EVENT (0x00000005)
/* NvNotification[] fields and values */
#define NV003_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0005_tag0 {
NvV32 Reserved00[0x7c0];
} Nv005Typedef, Nv01Event;
#define NV005_TYPEDEF Nv01Event
/* obsolete stuff */
#define NV1_TIMER (0x00000004)
#define Nv1Event Nv01Event
#define nv1Event Nv01Event
#define nv01Event Nv01Event
#include "cl0005_notification.h"
#define NV01_EVENT (0x00000005)
/* NvRmAlloc() parameters */
typedef struct {
#define NV0005_ALLOC_PARAMETERS_MESSAGE_ID (0x0005U)
typedef struct NV0005_ALLOC_PARAMETERS {
NvHandle hParentClient;
NvHandle hSrcResource;
NvV32 hClass;
NvV32 notifyIndex;
NvP64 data NV_ALIGN_BYTES(8);
NV_DECLARE_ALIGNED(NvP64 data, 8);
} NV0005_ALLOC_PARAMETERS;
/* NV0005_ALLOC_PARAMETERS's notifyIndex field is overloaded to contain the
* notifyIndex value itself, plus flags, and optionally a subdevice field if
* flags contains NV01_EVENT_SUBDEVICE_SPECIFIC. Note that NV01_EVENT_*
@@ -63,9 +56,3 @@ typedef struct {
#define NV0005_NOTIFY_INDEX_INDEX 15:0
#define NV0005_NOTIFY_INDEX_SUBDEVICE 23:16
#define NV0005_NOTIFY_INDEX_FLAGS 31:24
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0005_h_ */

51
src/common/sdk/nvidia/inc/class/cl0005_notification.h Normal file
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@@ -0,0 +1,51 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0005_notification_h_
#define _cl0005_notification_h_
#ifdef __cplusplus
extern "C" {
#endif
/* NvNotification[] fields and values */
#define NV003_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0005_tag0 {
NvV32 Reserved00[0x7c0];
} Nv005Typedef, Nv01Event;
#define NV005_TYPEDEF Nv01Event
/* obsolete stuff */
#define NV1_TIMER (0x00000004)
#define Nv1Event Nv01Event
#define nv1Event Nv01Event
#define nv01Event Nv01Event
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0005_notification_h_ */

33
src/common/sdk/nvidia/inc/class/cl000f.h
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@@ -21,25 +21,26 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl000f_h_
#define _cl000f_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl000f.finn
//
#define FABRIC_MANAGER_SESSION (0x0000000F)
#define FABRIC_MANAGER_SESSION (0x0000000F)
#define NV000F_NOTIFIERS_FABRIC_EVENT (0)
#define NV000F_NOTIFIERS_FABRIC_EVENT (0)
#define NV000F_FLAGS_CHANNEL_RECOVERY 0:0
#define NV000F_FLAGS_CHANNEL_RECOVERY_ENABLED 0x0
#define NV000F_FLAGS_CHANNEL_RECOVERY_DISABLED 0x1
#define NV000F_FLAGS_CHANNEL_RECOVERY 0:0
#define NV000F_FLAGS_CHANNEL_RECOVERY_ENABLED 0x0
#define NV000F_FLAGS_CHANNEL_RECOVERY_DISABLED 0x1
typedef struct
{
#define NV000F_ALLOCATION_PARAMETERS_MESSAGE_ID (0x000fU)
typedef struct NV000F_ALLOCATION_PARAMETERS {
//
// capDescriptor is a file descriptor for unix RM clients, but a void
// pointer for windows RM clients.
@@ -52,9 +53,3 @@ typedef struct
NvU32 flags;
} NV000F_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl000f_h_ */

25
src/common/sdk/nvidia/inc/class/cl0060.h
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@@ -21,26 +21,21 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#pragma once
#ifndef _cl0060_h_
#define _cl0060_h_
#include <nvtypes.h>
#ifdef __cplusplus
extern "C" {
#endif
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0060.finn
//
#define NV0060_SYNC_GPU_BOOST (0x00000060)
#define NV0060_SYNC_GPU_BOOST (0x00000060)
/*!
*/
typedef struct {
#define NV0060_ALLOC_PARAMETERS_MESSAGE_ID (0x0060U)
typedef struct NV0060_ALLOC_PARAMETERS {
NvU32 gpuBoostGroupId;
} NV0060_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl0060_h

36
src/common/sdk/nvidia/inc/class/cl0070.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2001-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2001-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,17 +20,17 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0070_h_
#define _cl0070_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0070.finn
//
#define NV01_MEMORY_VIRTUAL (0x00000070)
#define NV01_MEMORY_SYSTEM_DYNAMIC (0x00000070)
#define NV01_MEMORY_VIRTUAL (0x00000070)
#define NV01_MEMORY_SYSTEM_DYNAMIC (0x00000070)
/*
* NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS
@@ -61,17 +61,13 @@ extern "C" {
* limit - When limit is zero the maximum limit used. If a non-zero limit
* is specified then it will be used. The final limit is returned.
*/
typedef struct
{
NvU64 offset NV_ALIGN_BYTES(8); // [IN] - offset into address space
NvU64 limit NV_ALIGN_BYTES(8); // [IN/OUT] - limit of address space
NvHandle hVASpace; // [IN] - Address space handle
#define NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_MESSAGE_ID (0x0070U)
typedef struct NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS {
NV_DECLARE_ALIGNED(NvU64 offset, 8); // [IN] - offset into address space
NV_DECLARE_ALIGNED(NvU64 limit, 8); // [IN/OUT] - limit of address space
NvHandle hVASpace; // [IN] - Address space handle
} NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS;
#define NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE (0xffffffffu)
#define NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE 0xffffffffU
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0070_h_ */

59
src/common/sdk/nvidia/inc/class/cl0080.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,27 +21,23 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0080_h_
#define _cl0080_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl0080.finn
//
#include "nvlimits.h"
#include "nvtypes.h"
#include "cl0080_notification.h"
#define NV01_DEVICE_0 (0x00000080)
/* NvNotification[] fields and values */
#define NV080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0080_tag0 {
NvV32 Reserved00[0x7c0];
} Nv080Typedef, Nv01Device0;
#define NV080_TYPEDEF Nv01Device0
#define NV01_DEVICE_0 (0x00000080)
/* NvAlloc parameteters */
#define NV0080_MAX_DEVICES NV_MAX_DEVICES
#define NV0080_MAX_DEVICES NV_MAX_DEVICES
/**
* @brief Alloc param
*
@@ -51,21 +47,18 @@ typedef volatile struct _cl0080_tag0 {
* NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE
* NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES
* Detailed description of these modes is in nvos.h
**/
typedef struct {
NvU32 deviceId;
NvHandle hClientShare;
NvHandle hTargetClient;
NvHandle hTargetDevice;
NvV32 flags;
NvU64 vaSpaceSize NV_ALIGN_BYTES(8);
NvU64 vaStartInternal NV_ALIGN_BYTES(8);
NvU64 vaLimitInternal NV_ALIGN_BYTES(8);
NvV32 vaMode;
**/
#define NV0080_ALLOC_PARAMETERS_MESSAGE_ID (0x0080U)
typedef struct NV0080_ALLOC_PARAMETERS {
NvU32 deviceId;
NvHandle hClientShare;
NvHandle hTargetClient;
NvHandle hTargetDevice;
NvV32 flags;
NV_DECLARE_ALIGNED(NvU64 vaSpaceSize, 8);
NV_DECLARE_ALIGNED(NvU64 vaStartInternal, 8);
NV_DECLARE_ALIGNED(NvU64 vaLimitInternal, 8);
NvV32 vaMode;
} NV0080_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0080_h_ */

45
src/common/sdk/nvidia/inc/class/cl0080_notification.h Normal file
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@@ -0,0 +1,45 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0080_notification_h_
#define _cl0080_notification_h_
#ifdef __cplusplus
extern "C" {
#endif
/* NvNotification[] fields and values */
#define NV080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0080_tag0 {
NvV32 Reserved00[0x7c0];
} Nv080Typedef, Nv01Device0;
#define NV080_TYPEDEF Nv01Device0
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0080_notification_h_ */

28
src/common/sdk/nvidia/inc/class/cl00c2.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,26 +20,22 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl00c2_h_
#define _cl00c2_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00c2.finn
//
#define NV01_MEMORY_LOCAL_PHYSICAL (0x000000c2)
#define NV01_MEMORY_LOCAL_PHYSICAL (0x000000c2)
typedef struct
{
NvU64 memSize NV_ALIGN_BYTES(8); // [OUT]
#define NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00c2U)
typedef struct NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS {
NV_DECLARE_ALIGNED(NvU64 memSize, 8); // [OUT]
NvU32 format; // [IN] - PTE format to use
NvU32 pageSize; // [IN] - Page size to use
} NV_PHYSICAL_MEMORY_ALLOCATION_PARAMS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl00c2_h_ */

26
src/common/sdk/nvidia/inc/class/cl00c3.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,20 +20,24 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef SDK_CL00C3_H
#define SDK_CL00C3_H
#pragma once
#include "nvtypes.h"
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00c3.finn
//
#define NV01_MEMORY_SYNCPOINT 0x00C3
/*
* NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS - Allocation params to create syncpoint
through NvRmAlloc.
*/
typedef struct
{
NvU32 syncpointId;
* NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS - Allocation params to create syncpoint
* through NvRmAlloc.
*/
#define NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS_MESSAGE_ID (0x00c3U)
typedef struct NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS {
NvU32 syncpointId;
} NV_MEMORY_SYNCPOINT_ALLOCATION_PARAMS;
#endif // SDK_CL00C3_H

26
src/common/sdk/nvidia/inc/class/cl00db.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2010 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,25 +21,23 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl00db_h_
#define _cl00db_h_
#ifdef __cplusplus
extern "C" {
#endif
#pragma once
#include "nvtypes.h"
#include <nvtypes.h>
#define NV40_DEBUG_BUFFER (0x000000db)
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00db.finn
//
#define NV40_DEBUG_BUFFER (0x000000db)
/* NvRmAlloc() parameters */
typedef struct {
#define NV00DB_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00dbU)
typedef struct NV00DB_ALLOCATION_PARAMETERS {
NvU32 size; /* Desired message size / actual size returned */
NvU32 tag; /* Protobuf tag for message location in dump message */
} NV00DB_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl00db_h_ */

51
src/common/sdk/nvidia/inc/class/cl00f3.h
View File

@@ -21,7 +21,16 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00f3.finn
//
/*
* Class definition for creating a memory descriptor from a FLA range in RmAllocMemory.
@@ -31,46 +40,36 @@
* other parameters are passed as Nv01MemoryFla structure.
*/
#ifndef _cl00f3_h_
#define _cl00f3_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV01_MEMORY_FLA (0x000000f3)
#define NV01_MEMORY_FLA (0x000000f3)
/*
* Structure of NV_FLA_MEMORY_ALLOCATION_PARAMS
*
*
*/
typedef struct {
NvU32 type; /* FBMEM: NVOS32_TYPE_* */
NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */
NvU32 attr; /* FBMEM: NVOS32_ATTR_* */
NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */
NvU64 base; /* base of FLA range */
NvU64 align; /* alignment for FLA range*/
NvU64 limit NV_ALIGN_BYTES(8);
#define NV_FLA_MEMORY_ALLOCATION_PARAMS_MESSAGE_ID (0x00f3U)
typedef struct NV_FLA_MEMORY_ALLOCATION_PARAMS {
NvU32 type; /* FBMEM: NVOS32_TYPE_* */
NvU32 flags; /* FBMEM: NVOS32_ALLOC_FLAGS_* */
NvU32 attr; /* FBMEM: NVOS32_ATTR_* */
NvU32 attr2; /* FBMEM: NVOS32_ATTR2_* */
NV_DECLARE_ALIGNED(NvU64 base, 8); /* base of FLA range */
NV_DECLARE_ALIGNED(NvU64 align, 8); /* alignment for FLA range*/
NV_DECLARE_ALIGNED(NvU64 limit, 8);
//
// For Direct connected systems, clients need to program this hSubDevice with
// the exporting GPU, for RM to route the traffic to the destination GPU
// Clients need not program this for NvSwitch connected systems
//
NvHandle hExportSubdevice; /* hSubdevice of the exporting GPU */
NvHandle hExportSubdevice; /* hSubdevice of the exporting GPU */
//
// Instead of base and limit, clients can also pass the FLA handle (or hExportHandle)
// being exported from destination side to import on the access side
//
NvHandle hExportHandle; /* FLA handle being exported or Export handle */
NvHandle hExportHandle; /* FLA handle being exported or Export handle */
// The RM client used to export memory
NvHandle hExportClient;
NvU32 flagsOs02;
NvHandle hExportClient;
NvU32 flagsOs02;
} NV_FLA_MEMORY_ALLOCATION_PARAMS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl00f3_h

37
src/common/sdk/nvidia/inc/class/cl00f8.h
View File

@@ -19,22 +19,24 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00f8.finn
//
#include "nvtypes.h"
/*
* Class definition for allocating a contiguous or discontiguous FLA.
*/
#ifndef _cl00f8_h_
#define _cl00f8_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV_MEMORY_FABRIC (0x000000f8)
#define NV_MEMORY_FABRIC (0x000000f8)
/*
* alignment [IN]
@@ -86,16 +88,18 @@ extern "C" {
* Clients should pass 0 as of now.
*/
#define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000
#define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000
#define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000
#define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000
#define NV00F8_ALLOC_FLAGS_DEFAULT 0
#define NV00F8_ALLOC_FLAGS_DEFAULT 0
#define NV00F8_ALLOC_FLAGS_FLEXIBLE_FLA NVBIT(0)
#define NV00F8_ALLOC_FLAGS_FORCE_NONCONTIGUOUS NVBIT(1)
#define NV00F8_ALLOC_FLAGS_FORCE_CONTIGUOUS NVBIT(2)
#define NV00F8_ALLOC_FLAGS_READ_ONLY NVBIT(3)
typedef struct {
#define NV00F8_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00f8U)
typedef struct NV00F8_ALLOCATION_PARAMETERS {
NV_DECLARE_ALIGNED(NvU64 alignment, 8);
NV_DECLARE_ALIGNED(NvU64 allocSize, 8);
@@ -109,10 +113,5 @@ typedef struct {
NvHandle hVidMem;
NvU32 flags;
} map;
} NV00F8_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl00f8_h_ */

55
src/common/sdk/nvidia/inc/class/cl2080.h
View File

@@ -54,9 +54,9 @@ extern "C" {
#define NV2080_NOTIFIERS_NVDEC2 (16)
#define NV2080_NOTIFIERS_NVDEC3 (17)
#define NV2080_NOTIFIERS_NVDEC4 (18)
#define NV2080_NOTIFIERS_RESERVED19 (19)
#define NV2080_NOTIFIERS_RESERVED20 (20)
#define NV2080_NOTIFIERS_RESERVED21 (21)
#define NV2080_NOTIFIERS_NVDEC5 (19)
#define NV2080_NOTIFIERS_NVDEC6 (20)
#define NV2080_NOTIFIERS_NVDEC7 (21)
#define NV2080_NOTIFIERS_PDEC (22) // also known as VP
#define NV2080_NOTIFIERS_CE0 (23)
#define NV2080_NOTIFIERS_CE1 (24)
@@ -158,19 +158,19 @@ extern "C" {
#define NV2080_NOTIFIERS_CLOCKS_CHANGE (119)
#define NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE (120)
#define NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT (121)
#define NV2080_NOTIFIERS_RESERVED_122 (122)
#define NV2080_NOTIFIERS_RESERVED122 (122)
#define NV2080_NOTIFIERS_NVLINK_ERROR_FATAL (123)
#define NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT (124)
#define NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED (125)
#define NV2080_NOTIFIERS_NVJPG (126)
#define NV2080_NOTIFIERS_NVJPEG0 NV2080_NOTIFIERS_NVJPG
#define NV2080_NOTIFIERS_RESERVED127 (127)
#define NV2080_NOTIFIERS_RESERVED128 (128)
#define NV2080_NOTIFIERS_RESERVED129 (129)
#define NV2080_NOTIFIERS_RESERVED130 (130)
#define NV2080_NOTIFIERS_RESERVED131 (131)
#define NV2080_NOTIFIERS_RESERVED132 (132)
#define NV2080_NOTIFIERS_RESERVED133 (133)
#define NV2080_NOTIFIERS_NVJPEG1 (127)
#define NV2080_NOTIFIERS_NVJPEG2 (128)
#define NV2080_NOTIFIERS_NVJPEG3 (129)
#define NV2080_NOTIFIERS_NVJPEG4 (130)
#define NV2080_NOTIFIERS_NVJPEG5 (131)
#define NV2080_NOTIFIERS_NVJPEG6 (132)
#define NV2080_NOTIFIERS_NVJPEG7 (133)
#define NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE (134)
#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE (135)
#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE (136)
@@ -216,12 +216,10 @@ extern "C" {
#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) (((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2))
// Indexed NVDEC notifier reference
#define NV2080_NOTIFIERS_NVDEC(x) (NV2080_NOTIFIERS_NVDEC0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC4))
#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC7))
// Indexed NVJPEG notifier reference
#define NV2080_NOTIFIERS_NVJPEG(x) (NV2080_NOTIFIERS_NVJPEG0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG0))
#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7))
#define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT+(pin))
#define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT+(pin))
@@ -259,9 +257,9 @@ extern "C" {
#define NV2080_ENGINE_TYPE_NVDEC2 (0x00000015)
#define NV2080_ENGINE_TYPE_NVDEC3 (0x00000016)
#define NV2080_ENGINE_TYPE_NVDEC4 (0x00000017)
#define NV2080_ENGINE_TYPE_RESERVED18 (0x00000018)
#define NV2080_ENGINE_TYPE_RESERVED19 (0x00000019)
#define NV2080_ENGINE_TYPE_RESERVED1A (0x0000001a)
#define NV2080_ENGINE_TYPE_NVDEC5 (0x00000018)
#define NV2080_ENGINE_TYPE_NVDEC6 (0x00000019)
#define NV2080_ENGINE_TYPE_NVDEC7 (0x0000001a)
#define NV2080_ENGINE_TYPE_MSENC (0x0000001b)
#define NV2080_ENGINE_TYPE_NVENC0 NV2080_ENGINE_TYPE_MSENC /* Mutually exclusive alias */
#define NV2080_ENGINE_TYPE_NVENC1 (0x0000001c)
@@ -282,24 +280,21 @@ extern "C" {
#define NV2080_ENGINE_TYPE_FBFLCN (0x0000002a)
#define NV2080_ENGINE_TYPE_NVJPG (0x0000002b)
#define NV2080_ENGINE_TYPE_NVJPEG0 NV2080_ENGINE_TYPE_NVJPG
#define NV2080_ENGINE_TYPE_RESERVED2C (0x0000002c)
#define NV2080_ENGINE_TYPE_RESERVED2D (0x0000002d)
#define NV2080_ENGINE_TYPE_RESERVED2E (0x0000002e)
#define NV2080_ENGINE_TYPE_RESERVED2F (0x0000002f)
#define NV2080_ENGINE_TYPE_RESERVED30 (0x00000030)
#define NV2080_ENGINE_TYPE_RESERVED31 (0x00000031)
#define NV2080_ENGINE_TYPE_RESERVED32 (0x00000032)
#define NV2080_ENGINE_TYPE_NVJPEG1 (0x0000002c)
#define NV2080_ENGINE_TYPE_NVJPEG2 (0x0000002d)
#define NV2080_ENGINE_TYPE_NVJPEG3 (0x0000002e)
#define NV2080_ENGINE_TYPE_NVJPEG4 (0x0000002f)
#define NV2080_ENGINE_TYPE_NVJPEG5 (0x00000030)
#define NV2080_ENGINE_TYPE_NVJPEG6 (0x00000031)
#define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032)
#define NV2080_ENGINE_TYPE_OFA (0x00000033)
#define NV2080_ENGINE_TYPE_LAST (0x00000034)
#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff)
#define NV2080_ENGINE_TYPE_COPY_SIZE 10
#define NV2080_ENGINE_TYPE_NVENC_SIZE 3
#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 1
#define NV2080_ENGINE_TYPE_NVDEC_SIZE 5
#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8
#define NV2080_ENGINE_TYPE_NVDEC_SIZE 8
#define NV2080_ENGINE_TYPE_GR_SIZE 8
// Indexed engines

87
src/common/sdk/nvidia/inc/class/cl30f1.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,77 +21,36 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl30f1_h_
#define _cl30f1_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl30f1.finn
//
#include "cl30f1_notification.h"
/* class NV30_GSYNC */
#define NV30_GSYNC (0x000030F1)
#define NV30_GSYNC (0x000030F1)
/*
* A client should use NV01_EVENT_OS_EVENT as hClass and NV30F1_GSYNC_NOTIFIERS_* as
* notify index when allocating event, if separate event notifications are needed for
* separate event types.
*
* A client should use NV01_EVENT_KERNEL_CALLBACK as hClass and
* NV30F1_GSYNC_NOTIFIERS_ALL as notify index, if a single event is required.
* In this case RM would set event data equal to a pointer to NvNotification structure.
* The info32 field of NvNotification structure would be equal a bitmask of
* NV30F1_GSYNC_NOTIFIERS_* values.
*/
/* NvNotification[] fields and values */
#define NV30F1_GSYNC_CONNECTOR_ONE (0)
#define NV30F1_GSYNC_CONNECTOR_TWO (1)
#define NV30F1_GSYNC_CONNECTOR_THREE (2)
#define NV30F1_GSYNC_CONNECTOR_FOUR (3)
/* Framelock sync gain and loss events. These are connector specific events. */
#define NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(c) (0x00+(c))
#define NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(c) (0x04+(c))
/* Framelock stereo gain and loss events. These are connector specific events. */
#define NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(c) (0x08+(c))
#define NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(c) (0x0C+(c))
/* House cable gain(plug in) and loss(plug out) events. */
#define NV30F1_GSYNC_NOTIFIERS_HOUSE_GAIN (0x10)
#define NV30F1_GSYNC_NOTIFIERS_HOUSE_LOSS (0x11)
/* RJ45 cable gain(plug in) and loss(plug out) events. */
#define NV30F1_GSYNC_NOTIFIERS_RJ45_GAIN (0x12)
#define NV30F1_GSYNC_NOTIFIERS_RJ45_LOSS (0x13)
#define NV30F1_GSYNC_NOTIFIERS_MAXCOUNT (0x14)
/*
* For handling all event types.
* Note for Windows, it only handles NV01_EVENT_KERNEL_CALLBACK_EX; as for NV01_EVENT_OS_EVENT, it can only
* signal an event but not handle over any information.
*/
#define NV30F1_GSYNC_NOTIFIERS_ALL NV30F1_GSYNC_NOTIFIERS_MAXCOUNT
#define NV30F1_GSYNC_CONNECTOR_ONE (0)
#define NV30F1_GSYNC_CONNECTOR_TWO (1)
#define NV30F1_GSYNC_CONNECTOR_THREE (2)
#define NV30F1_GSYNC_CONNECTOR_FOUR (3)
#define NV30F1_GSYNC_CONNECTOR_PRIMARY NV30F1_GSYNC_CONNECTOR_ONE
#define NV30F1_GSYNC_CONNECTOR_SECONDARY NV30F1_GSYNC_CONNECTOR_TWO
#define NV30F1_GSYNC_CONNECTOR_COUNT (4)
#define NV30F1_GSYNC_CONNECTOR_PRIMARY NV30F1_GSYNC_CONNECTOR_ONE
#define NV30F1_GSYNC_CONNECTOR_SECONDARY NV30F1_GSYNC_CONNECTOR_TWO
#define NV30F1_GSYNC_CONNECTOR_COUNT (4)
/* NvRmAlloc parameters */
#define NV30F1_MAX_GSYNCS (0x0000004)
typedef struct {
NvU32 gsyncInstance;
#define NV30F1_MAX_GSYNCS (0x0000004)
#define NV30F1_ALLOC_PARAMETERS_MESSAGE_ID (0x30f1U)
typedef struct NV30F1_ALLOC_PARAMETERS {
NvU32 gsyncInstance;
} NV30F1_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl30f1_h_ */

74
src/common/sdk/nvidia/inc/class/cl30f1_notification.h Normal file
View File

@@ -0,0 +1,74 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl30f1_notification_h_
#define _cl30f1_notification_h_
#ifdef __cplusplus
extern "C" {
#endif
/*
* A client should use NV01_EVENT_OS_EVENT as hClass and NV30F1_GSYNC_NOTIFIERS_* as
* notify index when allocating event, if separate event notifications are needed for
* separate event types.
*
* A client should use NV01_EVENT_KERNEL_CALLBACK as hClass and
* NV30F1_GSYNC_NOTIFIERS_ALL as notify index, if a single event is required.
* In this case RM would set event data equal to a pointer to NvNotification structure.
* The info32 field of NvNotification structure would be equal a bitmask of
* NV30F1_GSYNC_NOTIFIERS_* values.
*/
/* NvNotification[] fields and values */
/* Framelock sync gain and loss events. These are connector specific events. */
#define NV30F1_GSYNC_NOTIFIERS_SYNC_LOSS(c) (0x00+(c))
#define NV30F1_GSYNC_NOTIFIERS_SYNC_GAIN(c) (0x04+(c))
/* Framelock stereo gain and loss events. These are connector specific events. */
#define NV30F1_GSYNC_NOTIFIERS_STEREO_LOSS(c) (0x08+(c))
#define NV30F1_GSYNC_NOTIFIERS_STEREO_GAIN(c) (0x0C+(c))
/* House cable gain(plug in) and loss(plug out) events. */
#define NV30F1_GSYNC_NOTIFIERS_HOUSE_GAIN (0x10)
#define NV30F1_GSYNC_NOTIFIERS_HOUSE_LOSS (0x11)
/* RJ45 cable gain(plug in) and loss(plug out) events. */
#define NV30F1_GSYNC_NOTIFIERS_RJ45_GAIN (0x12)
#define NV30F1_GSYNC_NOTIFIERS_RJ45_LOSS (0x13)
#define NV30F1_GSYNC_NOTIFIERS_MAXCOUNT (0x14)
/*
* For handling all event types.
* Note for Windows, it only handles NV01_EVENT_KERNEL_CALLBACK_EX; as for NV01_EVENT_OS_EVENT, it can only
* signal an event but not handle over any information.
*/
#define NV30F1_GSYNC_NOTIFIERS_ALL NV30F1_GSYNC_NOTIFIERS_MAXCOUNT
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl30f1_notification_h_ */

33
src/common/sdk/nvidia/inc/class/cl503b.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,23 +21,26 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl503b_h_
#define _cl503b_h_
#ifdef __cplusplus
extern "C" {
#endif
#pragma once
#include "nvtypes.h"
#include <nvtypes.h>
#define NV50_P2P (0x0000503b)
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl503b.finn
//
#define NV50_P2P (0x0000503b)
#define NV503B_FLAGS_P2P_TYPE 0:0
#define NV503B_FLAGS_P2P_TYPE_GPA 0
#define NV503B_FLAGS_P2P_TYPE_SPA 1
#define NV503B_FLAGS_P2P_TYPE_GPA 0
#define NV503B_FLAGS_P2P_TYPE_SPA 1
/* NvRmAlloc parameters */
typedef struct {
#define NV503B_ALLOC_PARAMETERS_MESSAGE_ID (0x503bU)
typedef struct NV503B_ALLOC_PARAMETERS {
NvHandle hSubDevice; /* subDevice handle of local GPU */
NvHandle hPeerSubDevice; /* subDevice handle of peer GPU */
NvU32 subDevicePeerIdMask; /* Bit mask of peer ID for SubDevice
@@ -46,15 +49,9 @@ typedef struct {
NvU32 peerSubDevicePeerIdMask; /* Bit mask of peer ID for PeerSubDevice
* A value of 0 defaults to RM selected
* PeerIdMasks must match in loopback */
NvU64 mailboxBar1Addr; /* P2P Mailbox area base offset in BAR1
NV_DECLARE_ALIGNED(NvU64 mailboxBar1Addr, 8); /* P2P Mailbox area base offset in BAR1
* Must have the same value across the GPUs */
NvU32 mailboxTotalSize; /* Size of the P2P Mailbox area
* Must have the same value across the GPUs */
NvU32 flags; /* Flag to indicate types/attib of p2p */
} NV503B_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl503b_h_ */

32
src/common/sdk/nvidia/inc/class/cl503c.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,29 +21,27 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl503c_h_
#define _cl503c_h_
#ifdef __cplusplus
extern "C" {
#endif
#pragma once
#include "nvtypes.h"
#include <nvtypes.h>
#define NV50_THIRD_PARTY_P2P (0x0000503c)
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl503c.finn
//
#define NV50_THIRD_PARTY_P2P (0x0000503c)
/* NvRmAlloc parameters */
typedef struct {
#define NV503C_ALLOC_PARAMETERS_MESSAGE_ID (0x503cU)
typedef struct NV503C_ALLOC_PARAMETERS {
NvU32 flags;
} NV503C_ALLOC_PARAMETERS;
#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE 1:0
#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_PROPRIETARY (0x00000000)
#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_BAR1 (0x00000001)
#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_NVLINK (0x00000002)
#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_PROPRIETARY (0x00000000)
#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_BAR1 (0x00000001)
#define NV503C_ALLOC_PARAMETERS_FLAGS_TYPE_NVLINK (0x00000002)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl503c_h_ */

43
src/common/sdk/nvidia/inc/class/cl5070.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 1993-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,37 +20,24 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl5070_h_
#define _cl5070_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl5070.finn
//
#define NV50_DISPLAY (0x00005070)
#include "cl5070_notification.h"
/* event values */
#define NV5070_NOTIFIERS_SW (0)
#define NV5070_NOTIFIERS_MAXCOUNT (1)
#define NV50_DISPLAY (0x00005070)
#define NV5070_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NV5070_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000)
#define NV5070_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000)
#define NV5070_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000)
#define NV5070_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
#define NV5070_ALLOCATION_PARAMETERS_MESSAGE_ID (0x5070U)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
typedef struct NV5070_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV5070_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl5070_h_ */

44
src/common/sdk/nvidia/inc/class/cl5070_notification.h Normal file
View File

@@ -0,0 +1,44 @@
/*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl5070_notification_h_
#define _cl5070_notification_h_
#ifdef __cplusplus
extern "C" {
#endif
/* event values */
#define NV5070_NOTIFIERS_SW (0)
#define NV5070_NOTIFIERS_MAXCOUNT (1)
#define NV5070_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NV5070_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000)
#define NV5070_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000)
#define NV5070_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000)
#define NV5070_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl5070_notification_h_ */

35
src/common/sdk/nvidia/inc/class/cl5080.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2002 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -20,34 +20,27 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl5080_h_
#define _cl5080_h_
#ifdef __cplusplus
extern "C" {
#endif
#pragma once
#include "nvtypes.h"
#include <nvtypes.h>
#define NV50_DEFERRED_API_CLASS (0x00005080)
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl5080.finn
//
#include "cl5080_notification.h"
#define NV50_DEFERRED_API_CLASS (0x00005080)
/* NvRmAlloc parameters */
typedef struct {
#define NV5080_ALLOC_PARAMS_MESSAGE_ID (0x5080U)
typedef struct NV5080_ALLOC_PARAMS {
// Should the deferred api completion trigger an event
NvBool notifyCompletion;
} NV5080_ALLOC_PARAMS;
/* dma method offsets, fields, and values */
#define NV5080_SET_OBJECT (0x00000000)
#define NV5080_NO_OPERATION (0x00000100)
#define NV5080_DEFERRED_API (0x00000200)
#define NV5080_DEFERRED_API_HANDLE 31:0
// Class-specific allocation capabilities
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl5080_h_ */

43
src/common/sdk/nvidia/inc/class/cl5080_notification.h Normal file
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@@ -0,0 +1,43 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl5080_notification_h_
#define _cl5080_notification_h_
#ifdef __cplusplus
extern "C" {
#endif
/* dma method offsets, fields, and values */
#define NV5080_SET_OBJECT (0x00000000)
#define NV5080_NO_OPERATION (0x00000100)
#define NV5080_DEFERRED_API (0x00000200)
#define NV5080_DEFERRED_API_HANDLE 31:0
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl5080_notification_h_ */

34
src/common/sdk/nvidia/inc/class/cl83de.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2010-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,17 +21,16 @@
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#ifndef _cl83de_h_
#define _cl83de_h_
#include <nvtypes.h>
#ifdef __cplusplus
extern "C" {
#endif
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl83de.finn
//
#include "nvtypes.h"
#define GT200_DEBUGGER (0x000083de)
#define GT200_DEBUGGER (0x000083de)
/*
* Creating the GT200_DEBUGGER object:
@@ -47,15 +46,10 @@ extern "C" {
* NvRmAlloc(hDebuggerClient, hDebuggerClient, hDebugger, GT200_DEBUGGER, &params);
*/
typedef struct {
NvHandle hDebuggerClient_Obsolete; // No longer supported (must be zero)
NvHandle hAppClient;
NvHandle hClass3dObject;
#define NV83DE_ALLOC_PARAMETERS_MESSAGE_ID (0x83deU)
typedef struct NV83DE_ALLOC_PARAMETERS {
NvHandle hDebuggerClient_Obsolete; // No longer supported (must be zero)
NvHandle hAppClient;
NvHandle hClass3dObject;
} NV83DE_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl83de_h_ */

29
src/common/sdk/nvidia/inc/class/cl85b5sw.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,25 +21,18 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#pragma once
#ifndef _cl85b5sw_h_
#define _cl85b5sw_h_
#include <nvtypes.h>
#ifdef __cplusplus
extern "C" {
#endif
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl85b5sw.finn
//
/* This file is *not* auto-generated. */
#define NV85B5_ALLOCATION_PARAMETERS_MESSAGE_ID (0x85b5U)
typedef struct
{
NvU32 version; // set to 0
NvU32 engineInstance; // CE instance
typedef struct NV85B5_ALLOCATION_PARAMETERS {
NvU32 version; // set to 0
NvU32 engineInstance; // CE instance
} NV85B5_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl85b5sw_h_

33
src/common/sdk/nvidia/inc/class/cl9072.h
View File

@@ -21,33 +21,26 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9072_h_
#define _cl9072_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9072.finn
//
#define GF100_DISP_SW 0x00009072
#include "cl9072_notification.h"
#define NV9072_NOTIFIERS_NOTIFY_ON_VBLANK (9)
#define NV9072_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
#define GF100_DISP_SW 0x00009072
#define NV9072_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9072U)
typedef struct
{
NvU32 logicalHeadId;
typedef struct NV9072_ALLOCATION_PARAMETERS {
NvU32 logicalHeadId;
/*
* 0 implies use Head argument only (i.e. whatever is currently setup on this head)
*/
NvU32 displayMask;
NvU32 caps;
NvU32 displayMask;
NvU32 caps;
} NV9072_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9072_h_ */

39
src/common/sdk/nvidia/inc/class/cl9072_notification.h Normal file
View File

@@ -0,0 +1,39 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9072_notification_h_
#define _cl9072_notification_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NV9072_NOTIFIERS_NOTIFY_ON_VBLANK (9)
#define NV9072_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9072_notification_h_ */

35
src/common/sdk/nvidia/inc/class/cl9170.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 1993-2004, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,27 +20,22 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9170_h_
#define _cl9170_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9170.finn
//
#define NV9170_DISPLAY (0x00009170)
#define NV9170_DISPLAY (0x00009170)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
#define NV9170_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9170U)
typedef struct NV9170_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9170_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9170_h_ */

35
src/common/sdk/nvidia/inc/class/cl9270.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 1993-2010, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,27 +20,22 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9270_h_
#define _cl9270_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9270.finn
//
#define NV9270_DISPLAY (0x00009270)
#define NV9270_DISPLAY (0x00009270)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
#define NV9270_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9270U)
typedef struct NV9270_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9270_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9270_h_ */

35
src/common/sdk/nvidia/inc/class/cl9470.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 1993-2012, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,27 +20,22 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9470_h_
#define _cl9470_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9470.finn
//
#define NV9470_DISPLAY (0x00009470)
#define NV9470_DISPLAY (0x00009470)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
#define NV9470_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9470U)
typedef struct NV9470_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9470_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9470_h_ */

35
src/common/sdk/nvidia/inc/class/cl9570.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 1993-2013, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,27 +20,22 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9570_h_
#define _cl9570_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9570.finn
//
#define NV9570_DISPLAY (0x00009570)
#define NV9570_DISPLAY (0x00009570)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
#define NV9570_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9570U)
typedef struct NV9570_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9570_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9570_h_ */

35
src/common/sdk/nvidia/inc/class/cl9770.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,27 +20,22 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9770_h_
#define _cl9770_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9770.finn
//
#define NV9770_DISPLAY (0x00009770)
#define NV9770_DISPLAY (0x00009770)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
#define NV9770_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9770U)
typedef struct NV9770_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9770_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9770_h_ */

35
src/common/sdk/nvidia/inc/class/cl9870.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 1993-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,27 +20,22 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl9870_h_
#define _cl9870_h_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <nvtypes.h>
#include "nvtypes.h"
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl9870.finn
//
#define NV9870_DISPLAY (0x00009870)
#define NV9870_DISPLAY (0x00009870)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
#define NV9870_ALLOCATION_PARAMETERS_MESSAGE_ID (0x9870U)
typedef struct NV9870_ALLOCATION_PARAMETERS {
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numDacs; // Number of DACs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numPiors; // Number of PIORs in this chip/display
} NV9870_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl9870_h_ */

2
src/common/sdk/nvidia/inc/class/cla06fsw.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

2
src/common/sdk/nvidia/inc/class/cla16fsw.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

2
src/common/sdk/nvidia/inc/class/clb06fsw.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

27
src/common/sdk/nvidia/inc/class/clb8b0.h Normal file
View File

@@ -0,0 +1,27 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_clb8b0_h__
#define __gh100_clb8b0_h__
#define NVB8B0_VIDEO_DECODER (0x0000B8B0)
#endif // __gh100_clb8b0_h__

27
src/common/sdk/nvidia/inc/class/clb8d1.h Normal file
View File

@@ -0,0 +1,27 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_clb8d1_h__
#define __gh100_clb8d1_h__
#define NVB8D1_VIDEO_NVJPG (0x0000B8D1)
#endif // __gh100_clb8d1_h__

29
src/common/sdk/nvidia/inc/class/clb8fa.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clb8fa_h_
#define _clb8fa_h_
#define NVB8FA_VIDEO_OFA (0x0000B8FA)
#endif /* _clb8fa_h_ */

2
src/common/sdk/nvidia/inc/class/clc06fsw.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

2
src/common/sdk/nvidia/inc/class/clc36fsw.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

2
src/common/sdk/nvidia/inc/class/clc46fsw.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

2
src/common/sdk/nvidia/inc/class/clc56fsw.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

27
src/common/sdk/nvidia/inc/class/clc661.h Normal file
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@@ -0,0 +1,27 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_clc661_h__
#define __gh100_clc661_h__
#define HOPPER_USERMODE_A (0xc661)
#endif // __gh100_clc661_h__

9
src/common/sdk/nvidia/inc/class/clc770.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -31,13 +31,6 @@ extern "C" {
#define NVC770_DISPLAY (0x0000C770)
typedef struct
{
NvU32 numHeads; // Number of HEADs in this chip/display
NvU32 numSors; // Number of SORs in this chip/display
NvU32 numDsis; // Number of DSIs in this chip/display
} NVC770_ALLOCATION_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif

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src/common/sdk/nvidia/inc/class/clc771.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc771_h_
#define _clc771_h_
#ifdef __cplusplus
extern "C" {
#endif
#define NVC771_DISP_SF_USER (0x000C771)
typedef volatile struct _clc771_tag0 {
NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */
} _NvC771DispSfUser, NvC771DispSfUserMap;
#define NVC771_SF_SHARED_GENERIC_CTRL(i,j) (0x000E0200-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE 4:4 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE_NO 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_SINGLE_YES 0x00000001 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW 16:16 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_NO 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_CHECKSUM_HW_YES 0x00000001 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_CTRL_LOC 9:8 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_VBLANK 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_VSYNC 0x00000001 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_CTRL_LOC_LOADV 0x00000002 /* RW--V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER(i,j) (0x000E0204-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_1 8 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER__SIZE_2 6 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB3 31:24 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_HEADER_HB3_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0(i,j) (0x000E0208-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0__SIZE_1 8 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0__SIZE_2 6 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB0 7:0 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB0_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB1 15:8 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB1_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB2 23:16 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB2_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB3 31:24 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK0_DB3_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1(i,j) (0x000E020C-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1__SIZE_1 8 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1__SIZE_2 6 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB4 7:0 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB4_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB5 15:8 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB5_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB6 23:16 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB6_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB7 31:24 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK1_DB7_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2(i,j) (0x000E0210-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2__SIZE_1 8 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2__SIZE_2 6 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB8 7:0 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB8_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB9 15:8 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB9_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB10 23:16 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB10_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB11 31:24 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK2_DB11_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3(i,j) (0x000E0214-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3__SIZE_1 8 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3__SIZE_2 6 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB12 7:0 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB12_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB13 15:8 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB13_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB14 23:16 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB14_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB15 31:24 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK3_DB15_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4(i,j) (0x000E0218-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4__SIZE_1 8 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4__SIZE_2 6 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB16 7:0 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB16_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB17 15:8 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB17_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB18 23:16 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB18_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB19 31:24 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK4_DB19_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5(i,j) (0x000E021C-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5__SIZE_1 8 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5__SIZE_2 6 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB20 7:0 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB20_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB21 15:8 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB21_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB22 23:16 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB22_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB23 31:24 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK5_DB23_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6(i,j) (0x000E0220-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6__SIZE_1 8 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6__SIZE_2 6 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB24 7:0 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB24_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB25 15:8 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB25_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB26 23:16 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB26_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB27 31:24 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK6_DB27_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7(i,j) (0x000E0224-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7__SIZE_1 8 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7__SIZE_2 6 /* */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB28 7:0 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB28_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB29 15:8 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB29_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB30 23:16 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB30_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB31 31:24 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_INFOFRAME_SUBPACK7_DB31_INIT 0x00000000 /* RWI-V */
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif

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src/common/sdk/nvidia/inc/class/clc773.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc773_h_
#define _clc773_h_
#define NVC773_DISP_CAPABILITIES 0xC773
#endif

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src/common/sdk/nvidia/inc/class/clc77d.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc77d_h_
#define _clc77d_h_
#define NVC77D_CORE_CHANNEL_DMA (0x0000C77D)
#define NVC77D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400)
#define NVC77D_HEAD_SET_RASTER_SIZE_WIDTH 14:0
#define NVC77D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16
#endif

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src/common/sdk/nvidia/inc/class/clc86f.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_clc86f_h__
#define __gh100_clc86f_h__
typedef volatile struct Nvc86fControl_struct {
NvU32 Ignored00[0x010]; /* 0000-003f*/
NvU32 Put; /* put offset, read/write 0040-0043*/
NvU32 Get; /* get offset, read only 0044-0047*/
NvU32 Reference; /* reference value, read only 0048-004b*/
NvU32 PutHi; /* high order put offset bits 004c-004f*/
NvU32 Ignored01[0x002]; /* 0050-0057*/
NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/
NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/
NvU32 GetHi; /* high order get offset bits 0060-0063*/
NvU32 Ignored02[0x007]; /* 0064-007f*/
NvU32 Ignored03; /* used to be engine yield 0080-0083*/
NvU32 Ignored04[0x001]; /* 0084-0087*/
NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/
NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
NvU32 Ignored05[0x5c];
} Nvc86fControl, HopperAControlGPFifo;
#define HOPPER_CHANNEL_GPFIFO_A (0x0000C86F)
#define NVC86F_SET_OBJECT (0x00000000)
#define NVC86F_SEM_ADDR_LO (0x0000005c)
#define NVC86F_SEM_ADDR_LO_OFFSET 31:2
#define NVC86F_SEM_ADDR_HI (0x00000060)
#define NVC86F_SEM_ADDR_HI_OFFSET 24:0
#define NVC86F_SEM_PAYLOAD_LO (0x00000064)
#define NVC86F_SEM_PAYLOAD_HI (0x00000068)
#define NVC86F_SEM_EXECUTE (0x0000006c)
#define NVC86F_SEM_EXECUTE_OPERATION 2:0
#define NVC86F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
#define NVC86F_SEM_EXECUTE_RELEASE_WFI 20:20
#define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
#endif // __gh100_clc86f_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/* This file is *not* auto-generated. */
#ifndef _clc86f_sw_h_
#define _clc86f_sw_h_
#define NVC86F_NOTIFIERS_RC (0)
#define NVC86F_NOTIFIERS_REFCNT (1)
#define NVC86F_NOTIFIERS_NONSTALL (2)
#define NVC86F_NOTIFIERS_EVENTBUFFER (3)
#define NVC86F_NOTIFIERS_IDLECHANNEL (4)
#define NVC86F_NOTIFIERS_ENDCTX (5)
#define NVC86F_NOTIFIERS_SW (6)
#define NVC86F_NOTIFIERS_GR_DEBUG_INTR (7)
#define NVC86F_NOTIFIERS_REPLAYABLE_FAULT (8)
#define NVC86F_NOTIFIERS_MAXCOUNT (9)
/* NvNotification[] fields and values */
#define NVC86F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
#define NVC86F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
#endif /* _clc56f_sw_h_ */

77
src/common/sdk/nvidia/inc/class/clc8b5.h Normal file
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@@ -0,0 +1,77 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_clc8b5_h__
#define __gh100_clc8b5_h__
#define HOPPER_DMA_COPY_A (0x0000C8B5)
#define NVC8B5_SET_SEMAPHORE_A (0x00000240)
#define NVC8B5_SET_SEMAPHORE_A_UPPER 24:0
#define NVC8B5_SET_SEMAPHORE_B (0x00000244)
#define NVC8B5_SET_SEMAPHORE_B_LOWER 31:0
#define NVC8B5_SET_SEMAPHORE_PAYLOAD (0x00000248)
#define NVC8B5_SET_DST_PHYS_MODE (0x00000264)
#define NVC8B5_SET_DST_PHYS_MODE_TARGET 1:0
#define NVC8B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
#define NVC8B5_LAUNCH_DMA (0x00000300)
#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0
#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001)
#define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002)
#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE 2:2
#define NVC8B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001)
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3
#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001)
#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7
#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001)
#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8
#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001)
#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9
#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000)
#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE 10:10
#define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000)
#define NVC8B5_LAUNCH_DMA_SRC_TYPE 12:12
#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001)
#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13
#define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001)
#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23
#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001)
#define NVC8B5_LAUNCH_DMA_DISABLE_PLC 26:26
#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_TRUE (0x00000001)
#define NVC8B5_OFFSET_OUT_UPPER (0x00000408)
#define NVC8B5_OFFSET_OUT_UPPER_UPPER 24:0
#define NVC8B5_OFFSET_OUT_LOWER (0x0000040C)
#define NVC8B5_OFFSET_OUT_LOWER_VALUE 31:0
#define NVC8B5_LINE_LENGTH_IN (0x00000418)
#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS (0x000006FC)
#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE 0:0
#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE (0x00000000)
#define NVC8B5_SET_REMAP_CONST_A (0x00000700)
#define NVC8B5_SET_REMAP_CONST_B (0x00000704)
#define NVC8B5_SET_REMAP_COMPONENTS (0x00000708)
#define NVC8B5_SET_REMAP_COMPONENTS_DST_X 2:0
#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004)
#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005)
#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16
#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000)
#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24
#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000)
#endif // __gh100_clc8b5_h__

29
src/common/sdk/nvidia/inc/class/clc997.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc997_h_
#define _clc997_h_
#define ADA_A 0xC997
#endif

29
src/common/sdk/nvidia/inc/class/clc9b0.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc9b0_h_
#define _clc9b0_h_
#define NVC9B0_VIDEO_DECODER (0x0000C9B0)
#endif

29
src/common/sdk/nvidia/inc/class/clc9b7.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc9b7_h_
#define _clc9b7_h_
#define NVC9B7_VIDEO_ENCODER (0x0000C9B7)
#endif

29
src/common/sdk/nvidia/inc/class/clc9c0.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _clc9c0_h_
#define _clc9c0_h_
#define ADA_COMPUTE_A 0xC9C0
#endif

31
src/common/sdk/nvidia/inc/class/clc9d1.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#ifndef _clc9d1_h_
#define _clc9d1_h_
#define NVC9D1_VIDEO_NVJPG (0x0000C9D1)
#endif // _clc9d1_h

32
src/common/sdk/nvidia/inc/class/clc9fa.h Normal file
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@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvtypes.h"
#ifndef _clc9fa_h_
#define _clc9fa_h_
#define NVC9FA_VIDEO_OFA (0x0000C9FA)
#endif // _clc9fa_h

27
src/common/sdk/nvidia/inc/class/clcb97.h Normal file
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@@ -0,0 +1,27 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_clcb97_h__
#define __gh100_clcb97_h__
#define HOPPER_A 0xCB97
#endif // __gh100_clcb97_h__

27
src/common/sdk/nvidia/inc/class/clcbc0.h Normal file
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@@ -0,0 +1,27 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_clcbc0_h__
#define __gh100_clcbc0_h__
#define HOPPER_COMPUTE_A 0xCBC0
#endif // __gh100_clcbc0_h__

39
src/common/sdk/nvidia/inc/class/clcbca.h Normal file
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@@ -0,0 +1,39 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _CLCBCA_H_
#define _CLCBCA_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV_COUNTER_COLLECTION_UNIT (0x0000CBCA)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _CLCBCA_H_

3
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h
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@@ -28,9 +28,6 @@
// Source file: ctrl/ctrl0000/ctrl0000base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV01_ROOT (client) control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h
View File

@@ -29,9 +29,6 @@
// Source file: ctrl/ctrl0000/ctrl0000client.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h
View File

@@ -29,9 +29,6 @@
// Source file: ctrl/ctrl0000/ctrl0000diag.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0000/ctrl0000event.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0000/ctrl0000gpu.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrl0000/ctrl0000system.h"
#include "ctrl/ctrlxxxx.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h
View File

@@ -29,9 +29,6 @@
// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
/*

3
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h
View File

@@ -29,9 +29,6 @@
// Source file: ctrl/ctrl0000/ctrl0000gsync.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0000/ctrl0000nvd.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0000/ctrl0000proc.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "nvlimits.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h
View File

@@ -29,9 +29,6 @@
// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"

24
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
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@@ -29,9 +29,6 @@
// Source file: ctrl/ctrl0000/ctrl0000system.finn
//
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl0000/ctrl0000base.h"
@@ -223,6 +220,27 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
NvU32 coresOnDie; /* cpu cores per die */
} NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS;
// Macros for CPU family information
#define NV0000_CTRL_SYSTEM_CPU_FAMILY 3:0
#define NV0000_CTRL_SYSTEM_CPU_EXTENDED_FAMILY 11:4
// Macros for CPU model information
#define NV0000_CTRL_SYSTEM_CPU_MODEL 3:0
#define NV0000_CTRL_SYSTEM_CPU_EXTENDED_MODEL 7:4
// Macros for AMD CPU information
#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_FAMILY 0xF
#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_FAMILY 0xA
#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_MODEL 0x0
#define NV0000_CTRL_SYSTEM_CPU_ID_AMD_EXTENDED_MODEL 0x4
// Macros for Intel CPU information
#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_FAMILY 0x6
#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_FAMILY 0x0
#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_S_MODEL 0x7
#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_CORE_P_MODEL 0xA
#define NV0000_CTRL_SYSTEM_CPU_ID_INTEL_EXTENDED_MODEL 0x9
/* processor type values */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000)
/* Intel types */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0000/ctrl0000unix.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl0002.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0002.finn
//
#include "ctrl/ctrlxxxx.h"
#define NV0002_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0002, NV0002_CTRL_##cat, idx)

3
src/common/sdk/nvidia/inc/ctrl/ctrl0004.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0004.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV01_TIMER control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl000f.h
View File

@@ -28,9 +28,6 @@
// Source file: ctrl/ctrl000f.finn
//
#include "ctrl/ctrlxxxx.h"
#define NV000F_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x000f, NV000F_CTRL_##cat, idx)

5
src/common/sdk/nvidia/inc/ctrl/ctrl0020.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0020.finn
//
#include "ctrl/ctrlxxxx.h"
#define NV0020_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0x0020, NV0020_CTRL_##cat, idx)
@@ -72,8 +69,6 @@
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0020_CTRL_CMD_GPU_MGMT_SET_SHUTDOWN_STATE (0x200101) /* finn: Evaluated from "(FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID << 8) | NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID" */
#define NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS_MESSAGE_ID (0x1U)

3
src/common/sdk/nvidia/inc/ctrl/ctrl003e.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl003e.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV01_MEMORY_SYSTEM control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0041.h
View File

@@ -31,9 +31,6 @@
//
#include "nvos.h"
#include "ctrl/ctrlxxxx.h"
/* NV04_MEMORY control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h
View File

@@ -28,9 +28,6 @@
// Source file: ctrl/ctrl0073/ctrl0073base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV04_DISPLAY_COMMON control commands and parameters */

142
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0073/ctrl0073dfp.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */
@@ -1095,11 +1092,53 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS {
* vActive
* This parameter specifies the vertical lines of the active pixel
* data in the raster.
* hFrontPorch
* This parameter specifies the number of horizontal front porch
* blanking pixels in the raster.
* vFrontPorch
* This parameter specifies the numer of lines of the vertical front
* porch in the raster.
* hBackPorch
* This parameter specifies the number of horizontal back porch
* blanking pixels in the raster.
* vBackPorch
* This parameter specifies the numer of lines of the vertical back
* porch in the raster.
* hSyncWidth
* This parameter specifies the number of horizontal sync pixels in
* the raster.
* vSyncWidth
* This parameter specifies the numer of lines of the vertical sync
* in the raster.
* bpp
* This parameter specifies the depth (Bits per Pixel) of the output
* display stream.
* refresh
* This parameter specifies the refresh rate of the panel (in Hz).
* pclkHz
* This parameter specifies the pixel clock rate in Hz.
* numLanes
* Number of DSI data lanes.
* dscEnable
* Flag to indicate if DSC an be enabled, which in turn indicates if
* panel supports DSC.
* dscBpp
* DSC Bits per pixel
* dscNumSlices
* Number of slices for DSC.
* dscDuaDsc
* Flag to indicate if panel supports DSC streams from two DSI
* controllers.
* dscSliceHeight
* Height of DSC slices.
* dscBlockPrediction
* Flag to indicate if DSC Block Prediction needs to be enabled.
* dscDecoderVersionMajor
* Major version number of DSC decoder on Panel.
* dscDecoderVersionMinor
* Minor version number of DSC decoder on Panel.
* dscEncoderCaps
* Capabilities of DSC encoder in SoC.
*
* Possible status values returned are:
* NV_OK
@@ -1116,10 +1155,107 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS {
NvU32 displayId;
NvU32 hActive;
NvU32 vActive;
NvU32 hFrontPorch;
NvU32 vFrontPorch;
NvU32 hBackPorch;
NvU32 vBackPorch;
NvU32 hSyncWidth;
NvU32 vSyncWidth;
NvU32 bpp;
NvU32 refresh;
NvU32 pclkHz;
NvU32 numLanes;
NvU32 dscEnable;
NvU32 dscBpp;
NvU32 dscNumSlices;
NvU32 dscDualDsc;
NvU32 dscSliceHeight;
NvU32 dscBlockPrediction;
NvU32 dscDecoderVersionMajor;
NvU32 dscDecoderVersionMinor;
struct {
NvBool bDscSupported;
NvU32 encoderColorFormatMask;
NvU32 lineBufferSizeKB;
NvU32 rateBufferSizeKB;
NvU32 bitsPerPixelPrecision;
NvU32 maxNumHztSlices;
NvU32 lineBufferBitDepth;
} dscEncoderCaps;
} NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS;
/*
* NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING
*
* This control call is used to retrieve the display mode timing info that's
* specified for a given DFP from an offline configuration blob (e.g., Device Tree).
* This display timing info is intended to replace the timings exposed in a
* sink's EDID.
*
* subDeviceInstance (in)
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.
* displayId (in)
* ID of the display device for which the timings should be retrieved.
* stream (in)
* For MST connectors with static topologies (e.g., DP serializers),
* this parameter further identifies the video stream for which the
* timings should be retrieved.
* valid (out)
* Indicates whether a valid display timing was found for this DFP.
* hActive (out)
* Horizontal active width in pixels
* hFrontPorch (out)
* Horizontal front porch
* hSyncWidth (out)
* Horizontal sync width
* hBackPorch (out)
* Horizontal back porch
* vActive (out)
* Vertical active height in lines
* vFrontPorch (out)
* Vertical front porch
* vSyncWidth (out)
* Vertical sync width
* vBackPorch (out)
* Vertical back porch
* pclkKHz (out)
* Pixel clock frequency in KHz
* rrx1k (out)
* Refresh rate in units of 0.001Hz
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */
#define NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID (0x72U)
typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU8 stream;
NvBool valid;
NvU16 hActive;
NvU16 hFrontPorch;
NvU16 hSyncWidth;
NvU16 hBackPorch;
NvU16 vActive;
NvU16 vFrontPorch;
NvU16 vSyncWidth;
NvU16 vBackPorch;
NvU32 pclkKHz;
NvU32 rrx1k;
} NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS;
/* _ctrl0073dfp_h_ */

93
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
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@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0073/ctrl0073dp.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */
@@ -1839,40 +1836,6 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_2 (0x00000004U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1 (0x00000005U)
/*
* NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES
*
* This command returns the following info
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* should be for DP only
* bEnableMSA
* To enable or disable MSA
* bStereoPhaseInverse
* To enable or disable Stereo Phase Inverse value
* bCacheMsaOverrideForNextModeset
* Cache the values and don't apply them until next modeset
* featureMask
* Enable/Disable mask of individual MSA property
* featureValues
* MSA property value to write
* pFeatureDebugValues
* It will actual MSA property value being written on HW.
* If its NULL then no error but return nothing
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_TIMEOUT
*
*/
#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES (0x73136aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP_MSA_PROPERTIES_SYNC_POLARITY_LOW (0U)
@@ -2730,8 +2693,6 @@ typedef struct NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS {
NvBool bOdStatus;
} NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS;
/* _ctrl0073dp_h_ */
/* valid commands */
#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CAPABLE 0x00000000
#define NV0073_CTRL_CMD_DP_AUXCHQUERY_OD_CTL_CAPABLE 0x00000001
@@ -2742,3 +2703,57 @@ typedef struct NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS {
#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_AUTONOMOUS 0x00000000
#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_DISABLE_OD 0x00000002
#define NV0073_CTRL_CMD_DP_AUXCH_OD_CTL_SET_ENABLE_OD 0x00000003
/*
* NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2
*
* This command returns the following info
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* should be for DP only
* bEnableMSA
* To enable or disable MSA
* bStereoPhaseInverse
* To enable or disable Stereo Phase Inverse value
* bCacheMsaOverrideForNextModeset
* Cache the values and don't apply them until next modeset
* featureMask
* Enable/Disable mask of individual MSA property
* featureValues
* MSA property value to write
* bDebugValues
* To inform whether actual MSA values need to be returned
* pFeatureDebugValues
* It will actual MSA property value being written on HW.
* If its NULL then no error but return nothing
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_TIMEOUT
*
*/
#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2 (0x731381U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS_MESSAGE_ID (0x81U)
typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvBool bEnableMSA;
NvBool bStereoPhaseInverse;
NvBool bCacheMsaOverrideForNextModeset;
NV0073_CTRL_DP_MSA_PROPERTIES_MASK featureMask;
NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureValues;
NvBool bDebugValues;
NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues;
} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS;
/* _ctrl0073dp_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
View File

@@ -28,9 +28,6 @@
// Source file: ctrl/ctrl0073/ctrl0073internal.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
#include "ctrl/ctrl0073/ctrl0073system.h"

54
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0073/ctrl0073specific.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
#include "ctrl/ctrlxxxx.h"
@@ -1790,4 +1787,55 @@ typedef struct NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS {
NvU32 infoframeIndex;
} NV0073_CTRL_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET_PARAMS;
/*
* NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE
*
* This command is used to do I2C R/W to slave on display i2c instance.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* i2cPort
* This parameter specifies the I2C CCB port ID.
* i2cSlaveAddress
* This parameter specifies the I2C slave address.
* readWriteFlag
* This parameter specifies whether its read/write operation.
* readWriteLen
* This parameter specifies the length of the read/write buffer
* readBuffer
* This parameter reads the data from slave address and copies to this
* buffer
* writeBuffer
* This parameter specifies this buffer data that would be written to
* slave address
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0073_CTRL_CMD_SPECIFIC_DISP_I2C_READ_WRITE (0x7302acU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN 128U
#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS_MESSAGE_ID (0xACU)
typedef struct NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS {
NvU32 subDeviceInstance;
NvU32 i2cPort;
NvU32 i2cSlaveAddress;
NvU32 readWriteFlag;
NvU32 readWriteLen;
NvU8 readBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN];
NvU8 writeBuffer[NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_BUF_LEN];
} NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS;
#define NV0073_CTRL_SPECIFIC_DISP_I2C_READ_MODE (0x00000001)
#define NV0073_CTRL_SPECIFIC_DISP_I2C_WRITE_MODE (0x00000000)
/* _ctrl0073specific_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0073/ctrl0073stereo.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0073/ctrl0073system.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/* NV04_DISPLAY_COMMON system-level control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h
View File

@@ -28,9 +28,6 @@
// Source file: ctrl/ctrl0080/ctrl0080base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV01_DEVICE_XX/NV03_DEVICE control commands and parameters */

23
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0080/ctrl0080bif.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/*
@@ -117,5 +114,25 @@ typedef struct NV0080_CTRL_BIF_SET_ASPM_FEATURE_PARAMS {
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_ENABLED 0x000000001
#define NV0080_CTRL_BIF_ASPM_FEATURE_DT_L1_DISABLED 0x000000000
/*
* NV0080_CTRL_BIF_ASPM_CYA_UPDATE
*
* bL0sEnable
* bL1Enable
* ASPM CYA update by client
*
* Possible status values returned are:
* NV_OK
*/
#define NV0080_CTRL_CMD_BIF_ASPM_CYA_UPDATE (0x800105) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_BIF_INTERFACE_ID << 8) | NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS {
NvBool bL0sEnable;
NvBool bL1Enable;
} NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS;
/* _ctrl0080bif_h_ */

4
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -29,8 +29,6 @@
// Source file: ctrl/ctrl0080/ctrl0080bsp.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE bit stream processor control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0080/ctrl0080dma.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE dma control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0080/ctrl0080fb.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE fb control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0080/ctrl0080fifo.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE fifo control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0080/ctrl0080gpu.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
#include "nvlimits.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0080/ctrl0080gr.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
typedef struct NV0080_CTRL_GR_ROUTE_INFO {

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0080/ctrl0080host.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE host control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h
View File

@@ -32,9 +32,6 @@
#include "nvlimits.h"
#include "ctrl0080gr.h"
#include "ctrl/ctrl0080/ctrl0080base.h"
#include "ctrl/ctrl0080/ctrl0080perf.h"

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0080/ctrl0080msenc.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE MSENC control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE NVJPG control commands and parameters */

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h
View File

@@ -30,8 +30,6 @@
// Source file: ctrl/ctrl0080/ctrl0080perf.finn
//
#define NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS {

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h
View File

@@ -28,9 +28,6 @@
// Source file: ctrl/ctrl0080/ctrl0080rc.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h
View File

@@ -30,9 +30,6 @@
// Source file: ctrl/ctrl0080/ctrl0080unix.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE UNIX-specific control commands and parameters */

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