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This commit is contained in:
Andy Ritger
2022-10-10 14:59:24 -07:00
parent fe0728787f
commit 90eb10774f
758 changed files with 88383 additions and 26493 deletions
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3
src/nvidia/inc/kernel/core/prelude.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -40,7 +40,6 @@
/* ------------------------ RM library and utils ---------------------------- */
#include "nvport/nvport.h"
#include "nvoc/runtime.h"
#include "nvoc/utility.h"
#include "core/printf.h"
#include "core/strict.h"
#include "utils/nvassert.h"

53
src/nvidia/inc/kernel/core/printf.h
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@@ -302,59 +302,6 @@ void nvDbgDumpBufferBytes(void *pBuffer, NvU32 length);
#endif
//********************************************************************************
//
// NVRM_TRACE support
// low-overhead runtime state capture
// to enable, define USE_NVRM_TRACE (retail or debug builds)
//
//********************************************************************************
#ifdef USE_NVRM_TRACE
NvU32 NVRM_TRACE_INIT(void);
NvU32 NVRM_TRACE_DISABLE(void);
void NVRM_TRACE_ENABLE(void);
void NVRM_TRACE_DUMP(void);
void NVRM_TRACE(NvU32);
void NVRM_TRACEV(NvU32 *,NvU32);
void NVRM_TRACE1(NvU32);
void NVRM_TRACE2(NvU32, NvU32);
void NVRM_TRACE3(NvU32, NvU32, NvU32);
void NVRM_TRACE4(NvU32, NvU32, NvU32, NvU32);
void NVRM_TRACE5(NvU32, NvU32, NvU32, NvU32, NvU32);
// versions of reg read/write that log to trace buffer
//NvU32 NVRM_TRACE_REG_RD32(OBJGPU *, NvU32);
//void NVRM_TRACE_REG_WR32(OBJGPU *, NvU32, NvU32);
// fifolog format looks like:
// 31:28 = unique file number
// 27:4 = file line number
// 1:0 = fifo state bits (bit1 = puller, bit0 = reassign)
#define FIFOLOG(fn,fa,fb) NVRM_TRACE2('FIFO', ((fn << 28) | (__LINE__ << 4) | \
((fa & 0x1) ? 1 : 0) << 1 | \
((fb & 0x1) ? 1 : 0)) )
#else // ! USE_NVRM_TRACE
#define NVRM_TRACE_INIT()
#define NVRM_TRACE_DISABLE() 0
#define NVRM_TRACE_ENABLE()
#define NVRM_TRACE_DUMP()
#define NVRM_TRACE(c0)
#define NVRM_TRACE1(c0)
#define NVRM_TRACE2(c0, c1)
#define NVRM_TRACE3(c0, c1, c2)
#define NVRM_TRACE4(c0, c1, c2, c3)
#define NVRM_TRACE5(c0, c1, c2, c3, c4)
#define FIFOLOG(a,b,c)
#endif // ! USE_NVRM_TRACE
#define NVRM_TRACE_ERROR(code, status) NVRM_TRACE3('EEEE', (code), (status))
#define NVRM_TRACE_API(code, p0, p1, p2) NVRM_TRACE5('API ', (code), (p0), (p1), (p2))
void nvErrorLog(void *pVoid, NvU32 num, const char *pFormat, va_list arglist);
void nvErrorLog_va(void * pGpu, NvU32 num, const char * pFormat, ...);

3
src/nvidia/inc/kernel/gpu/ccu/kernel_ccu.h Normal file
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@@ -0,0 +1,3 @@
#include "g_kernel_ccu_nvoc.h"

3
src/nvidia/inc/kernel/gpu/ccu/kernel_ccu_api.h Normal file
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@@ -0,0 +1,3 @@
#include "g_kernel_ccu_api_nvoc.h"

46
src/nvidia/inc/kernel/gpu/ce/kernel_ce_gv100_private.h
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@@ -24,52 +24,6 @@
#ifndef KERNEL_CE_GV100_PRIVATE_H
#define KERNEL_CE_GV100_PRIVATE_H
#define MAX_CE_CNT 15
/*
* sysmemLinks
* Represents the number of sysmem links detected
* This affects how many PCEs LCE0(sysmem read CE)
* and LCE1(sysmem write CE) should be mapped to
* maxLinksPerPeer
* Represents the maximum number of peer links
* between this GPU and all its peers. This affects
* how many PCEs LCE3(P2P CE) should be mapped to
* numPeers
* Represents the number of Peer GPUs discovered so far
* bSymmetric
* Represents whether the topology detected so far
* is symmetric i.e. has same number of links to all
* peers connected through nvlink. This affects how
* many PCEs to assign to LCEs3-5 (nvlink P2P CEs)
* bSwitchConfig
* Represents whether the config listed is intended
* for use with nvswitch systems
* pceLceMap
* Value of NV_CE_PCE2LCE_CONFIG0 register with the
* above values for sysmemLinks, maxLinksPerPeer,
* numLinks and bSymmetric
* grceConfig
* Value of NV_CE_GRCE_CONFIG register with the
* above values for sysmemLinks, maxLinksPerPeer,
* numLinks and bSymmetric
* exposeCeMask
* Mask of CEs to expose to clients for the above
* above values for sysmemLinks, maxLinksPerPeer,
* numLinks and bSymmetric
*/
typedef struct NVLINK_CE_AUTO_CONFIG_TABLE
{
NvU32 sysmemLinks;
NvU32 maxLinksPerPeer;
NvU32 numPeers;
NvBool bSymmetric;
NvBool bSwitchConfig;
NvU32 pceLceMap[MAX_CE_CNT];
NvU32 grceConfig[MAX_CE_CNT];
NvU32 exposeCeMask;
} NVLINK_CE_AUTO_CONFIG_TABLE;
//
// General convention decided on between HW and SW:
// - CE2 is for SYSMEM reads

3
src/nvidia/inc/kernel/gpu/fsp/kern_fsp.h Normal file
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@@ -0,0 +1,3 @@
#include "g_kern_fsp_nvoc.h"

28
src/nvidia/inc/kernel/gpu/fsp/kern_fsp_retval.h Normal file
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@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#define FSP_OK (0x00U)
#define FSP_ERR_IFS_ERR_INVALID_STATE (0x9EU)
#define FSP_ERR_IFR_FILE_NOT_FOUND (0x9FU)
#define FSP_ERR_IFS_ERR_NOT_SUPPORTED (0xA0U)
#define FSP_ERR_IFS_ERR_INVALID_DATA (0xA1U)

12
src/nvidia/inc/kernel/gpu/gpu_child_list.h
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@@ -90,6 +90,9 @@
#if GPU_CHILD_MODULE(FBFLCN)
GPU_CHILD_SINGLE_INST( OBJFBFLCN, GPU_GET_FBFLCN, 1, NV_FALSE, NV_FALSE, pFbflcn )
#endif
#if GPU_CHILD_MODULE(HSHUBMANAGER)
GPU_CHILD_SINGLE_INST( OBJHSHUBMANAGER, GPU_GET_HSHUBMANAGER, 1, NV_FALSE, NV_FALSE, pHshMgr )
#endif
#if GPU_CHILD_MODULE(HSHUB)
GPU_CHILD_MULTI_INST ( OBJHSHUB, GPU_GET_HSHUB, GPU_MAX_HSHUBS, NV_FALSE, NV_FALSE, pHshub )
#endif
@@ -120,9 +123,6 @@
#if GPU_CHILD_MODULE(KERNEL_GMMU)
GPU_CHILD_SINGLE_INST( KernelGmmu, GPU_GET_KERNEL_GMMU, 1, NV_FALSE, NV_FALSE, pKernelGmmu )
#endif
#if GPU_CHILD_MODULE(KERNEL_NVDEC)
GPU_CHILD_SINGLE_INST( KernelNvdec, GPU_GET_KERNEL_NVDEC, 1, NV_FALSE, NV_FALSE, pKernelNvdec )
#endif
#if GPU_CHILD_MODULE(KERNEL_SEC2)
GPU_CHILD_SINGLE_INST( KernelSec2, GPU_GET_KERNEL_SEC2, 1, NV_FALSE, NV_FALSE, pKernelSec2 )
#endif
@@ -291,9 +291,15 @@
#if GPU_CHILD_MODULE(GSP)
GPU_CHILD_SINGLE_INST( Gsp, GPU_GET_GSP, 1, NV_FALSE, NV_FALSE, pGsp )
#endif
#if RMCFG_MODULE_KERNEL_FSP && GPU_CHILD_MODULE(KERNEL_FSP)
GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_FALSE, NV_FALSE, pKernelFsp )
#endif
#if GPU_CHILD_MODULE(OFA)
GPU_CHILD_SINGLE_INST( OBJOFA, GPU_GET_OFA, 1, NV_FALSE, NV_FALSE, pOfa )
#endif
#if RMCFG_MODULE_KERNEL_CCU && GPU_CHILD_MODULE(KERNEL_CCU)
GPU_CHILD_SINGLE_INST( KernelCcu, GPU_GET_KERNEL_CCU, 1, NV_FALSE, NV_FALSE, pKernelCcu )
#endif
// Undefine the entry macros to simplify call sites
#undef GPU_CHILD

8
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
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@@ -35,6 +35,7 @@
#include "ctrl/ctrl2080/ctrl2080bios.h"
#include "ctrl/ctrl2080/ctrl2080fb.h"
#include "ctrl/ctrl2080/ctrl2080gpu.h"
#include "ctrl/ctrla083.h"
#include "gpu/gpu.h" // COMPUTE_BRANDING_TYPE
#include "vgpu/rpc_headers.h" // MAX_GPC_COUNT
@@ -109,8 +110,8 @@ typedef struct GspStaticConfigInfo_t
NvBool bClRootportNeedsNosnoopWAR;
VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads;
VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution;
NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads;
NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution;
NvU64 displaylessMaxPixels;
// Client handle for internal RMAPI control.
@@ -121,6 +122,8 @@ typedef struct GspStaticConfigInfo_t
// Subdevice handle for internal RMAPI control.
NvHandle hInternalSubdevice;
NvBool bAtsSupported;
} GspStaticConfigInfo;
// Pushed from CPU-RM to GSP-RM
@@ -133,6 +136,7 @@ typedef struct GspSystemInfo
NvU64 simAccessBufPhysAddr;
NvU64 pcieAtomicsOpMask;
NvU64 consoleMemSize;
NvU64 maxUserVa;
NvU32 pciConfigMirrorBase;
NvU32 pciConfigMirrorSize;
NvU8 oorArch;

21
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
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@@ -81,13 +81,14 @@
#define MC_ENGINE_IDX_NVJPG 42
#define MC_ENGINE_IDX_NVJPEG MC_ENGINE_IDX_NVJPG
#define MC_ENGINE_IDX_NVJPEG0 MC_ENGINE_IDX_NVJPEG
#define MC_ENGINE_IDX_RESERVED43 43
#define MC_ENGINE_IDX_RESERVED44 44
#define MC_ENGINE_IDX_RESERVED45 45
#define MC_ENGINE_IDX_RESERVED46 46
#define MC_ENGINE_IDX_RESERVED47 47
#define MC_ENGINE_IDX_RESERVED48 48
#define MC_ENGINE_IDX_RESERVED49 49
#define MC_ENGINE_IDX_NVJPEG1 43
#define MC_ENGINE_IDX_NVJPEG2 44
#define MC_ENGINE_IDX_NVJPEG3 45
#define MC_ENGINE_IDX_NVJPEG4 46
#define MC_ENGINE_IDX_NVJPEG5 47
#define MC_ENGINE_IDX_NVJPEG6 48
#define MC_ENGINE_IDX_NVJPEG7 49
#define MC_ENGINE_IDX_REPLAYABLE_FAULT 50
#define MC_ENGINE_IDX_ACCESS_CNTR 51
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT 52
@@ -101,9 +102,9 @@
#define MC_ENGINE_IDX_NVDEC2 58
#define MC_ENGINE_IDX_NVDEC3 59
#define MC_ENGINE_IDX_NVDEC4 60
#define MC_ENGINE_IDX_RESERVED61 61
#define MC_ENGINE_IDX_RESERVED62 62
#define MC_ENGINE_IDX_RESERVED63 63
#define MC_ENGINE_IDX_NVDEC5 61
#define MC_ENGINE_IDX_NVDEC6 62
#define MC_ENGINE_IDX_NVDEC7 63
#define MC_ENGINE_IDX_CPU_DOORBELL 64
#define MC_ENGINE_IDX_PRIV_DOORBELL 65
#define MC_ENGINE_IDX_MMU_ECC_ERROR 66

6
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h
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@@ -45,6 +45,12 @@
#include "addrtree.h"
#include "nvmisc.h"
#if defined(SRT_BUILD)
#define RMCFG_MODULE_x 1
#else
#include "rmconfig.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif

3
src/nvidia/inc/kernel/gpu/nvdec/kernel_nvdec.h
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@@ -1,3 +0,0 @@
#include "g_kernel_nvdec_nvoc.h"

31
src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_MAP,
RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL))
NV_STATUS subdeviceCtrlCmdCcuMap(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *pParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP,
RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL))
NV_STATUS subdeviceCtrlCmdCcuUnmap(Subdevice *pSubdevice);

13
src/nvidia/inc/kernel/mem_mgr/pool_alloc.h
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@@ -198,4 +198,15 @@ NvBool rmMemPoolIsScrubSkipped(RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInf
*/
NV_STATUS rmMemPoolGetChunkAndPageSize(RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo, NvU64*, NvU32*);
#endif //_RM_POOL_ALLOC_H_
/*!
* @brief Indicate that pool should be allocated in protected video memory in
* case memory protection is enabled
*
* @param[in] pMemReserveInfo Pointer to the RM_POOL_ALLOC_MEM_RESERVE_INFO data
* @param[in] bProtected Allocate in protected memory
*
* @return
*/
void rmMemPoolAllocateProtectedMemory(RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo, NvBool bProtected);
#endif //_RM_POOL_ALLOC_

52
src/nvidia/inc/kernel/os/os_fixed_mode_timings_props.h Normal file
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@@ -0,0 +1,52 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _OS_FIXED_MODE_TIMINGS_PROPS_H_
#define _OS_FIXED_MODE_TIMINGS_PROPS_H_
#include "gpu/disp/kern_disp_max.h"
#include "nvtypes.h"
typedef struct
{
NvU16 hActive;
NvU16 hFrontPorch;
NvU16 hSyncWidth;
NvU16 hBackPorch;
NvU16 vActive;
NvU16 vFrontPorch;
NvU16 vSyncWidth;
NvU16 vBackPorch;
NvU32 pclkKHz;
NvU32 rrx1k;
} OS_MODE_TIMING;
typedef struct
{
OS_MODE_TIMING timingsPerStream[OBJ_MAX_HEADS];
NvU8 numTimings;
} OS_FIXED_MODE_TIMINGS;
#endif

3
src/nvidia/inc/kernel/platform/acpi_common.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -36,6 +36,7 @@ void cacheDsmSupportedFunction(OBJGPU *, ACPI_DSM_FUNCTION, NvU32, NvU32 *, NvU3
NV_STATUS checkDsmCall(OBJGPU *, ACPI_DSM_FUNCTION *, NvU32 *, NvU32 *, NvU16 *);
void acpiDsmInit(OBJGPU *);
NV_STATUS getLicenseKey(OBJGPU *, NvU32, NvU32 *, NvU16 *);
void uncacheDsmFuncStatus(OBJGPU *, ACPI_DSM_FUNCTION, NvU32);
// useful macros
#if NV_PRINTF_ENABLED

123
src/nvidia/inc/kernel/rmapi/control.h
View File

@@ -132,28 +132,141 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *pParamCopy, RmCtrlParams *pRmC
!RMCFG_FEATURE_PHYSICAL_RM \
)
// per-rmcontrol flags values
//
// 'FLAGS' Attribute
// -----------------
//
// RMCTRL_FLAGS is used to specify per-command state.
//
#define RMCTRL_FLAGS_NONE 0x000000000
#define RMCTRL_FLAGS_NO_STATIC 0x000000000 // internal to chip-config. TODO -- delete
#define RMCTRL_FLAGS_ONLY_IF_CMD_DEFINED 0x000000000 // internal to chip-config. TODO -- delete
//
// If the KERNEL_PRIVILEGED flag is specified, the call will only be allowed
// for kernel mode callers (such as other kernel drivers) using a privileged
// kernel RM client (CliCheckIsKernelClient() returning true). Otherwise,
// NV_ERR_INSUFFICIENT_PERMISSIONS is returned.
//
#define RMCTRL_FLAGS_KERNEL_PRIVILEGED 0x000000000
//
// The resman rmcontrol handler will not grab the "gpus lock"
// before executing the implementing function.
//
// Please be sure you know what you're doing before using this!
//
#define RMCTRL_FLAGS_NO_GPUS_LOCK 0x000000001
//
// Indicate to resman that this rmcontrol does not access any gpu
// resources and can therefore run even when the gpu is powered down.
//
// Please be sure you know what you're doing before using this!
//
#define RMCTRL_FLAGS_NO_GPUS_ACCESS 0x000000002
//
// If the PRIVILEGED flag is specified, the call will only be allowed for
// a) user contexts with admin privleges (osIsAdministrator() returning true), or
// b) kernel mode callers, such as other kernel drivers.
// Otherwise, NV_ERR_INSUFFICIENT_PERMISSIONS is returned.
//
#define RMCTRL_FLAGS_PRIVILEGED 0x000000004
#define RMCTRL_FLAGS_HACK_USED_ON_MULTIPLE_CLASSES 0x000000008
//
// If the NON_PRIVILEGED flag is specified, the call will be allowed from any
// client.
//
#define RMCTRL_FLAGS_NON_PRIVILEGED 0x000000010
#define RMCTRL_FLAGS_BIG_PAYLOAD 0x000000020
//
// The resman rmcontrol handler will grab the per-device lock instead
// of the "gpus lock" before executing the implementing function.
//
// Please be sure you know what you're doing before using this!
//
#define RMCTRL_FLAGS_GPU_LOCK_DEVICE_ONLY 0x000000040
//
// This flag is equivalent to PRIVILEGED when the RM access rights
// implementation is disabled. Otherwise, it has no effect.
//
// The purpose of this flag is to aid in the transition to the access rights
// system, so that access rights can be used for control calls that were
// previously PRIVILEGED. Once access rights are enabled, this flag will no
// longer be necessary.
//
#define RMCTRL_FLAGS_PRIVILEGED_IF_RS_ACCESS_DISABLED 0x000000100 // for Resserv Access Rights migration
//
// This flag specifies that the control shall be directly forwarded to the
// physical object if called on the CPU-RM kernel.
//
#define RMCTRL_FLAGS_ROUTE_TO_PHYSICAL 0x000000200
//
// If the INTERNAL flag is specified, the call will only be allowed
// to be issued from RM itself. Otherwise, NV_ERR_NOT_SUPPORTED is returned.
//
#define RMCTRL_FLAGS_INTERNAL 0x000000400
//
// If the API_LOCK_READONLY flag is specified, the call will acquire the
// read-only API lock and may run concurrently with other operations that have
// also taken the read-only API lock. This flag is ignored if read-only API
// locking is disabled in RM.
//
#define RMCTRL_FLAGS_API_LOCK_READONLY 0x000000800
//
// If the :GPU_LOCK_READONLY flag is specified, the call will acquire a
// read-only GPU lock and may run concurrently with other operations that have
// also taken a read-only GPU lock. This flag is ignored if read-only GPU
// locking is disabled in RM.
//
#define RMCTRL_FLAGS_GPU_LOCK_READONLY 0x000001000
//
// This flag specifies that the control shall be directly forwarded to the
// the VGPU host if called from a guest (where IS_VIRTUAL() is true)
//
#define RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST 0x000002000
//
// This flag specifies that the control output does not depend on the input
// parameters and can be cached on the receiving end.
// The cache is transparent and may not exist on all platforms.
//
#define RMCTRL_FLAGS_CACHEABLE 0x000004000
//
// This flag specifies that the control parameters will be
// copied out back to the caller even if the control call fails.
//
#define RMCTRL_FLAGS_COPYOUT_ON_ERROR 0x000008000
// ??
#define RMCTRL_FLAGS_ALLOW_WITHOUT_SYSMEM_ACCESS 0x000010000
//
// 'ACCESS_RIGHTS' Attribute
// ------------------------
//
// Used to specify a set of access rights that the client must hold on the
// target resource to execute this control call. Note that this can only check
// access rights on the target object; for other objects, such as those
// specified by handles in parameter structs, checks must be done manually.
//
// The definition of each access right and its meaning is provided in the
// README located at drivers/common/shared/accessrights/README. The prefix
// "RS_ACCESS" is appended to each entry in the control call definition;
// for example, :NICE -> RS_ACCESS_NICE.
//
// This attribute only has an effect when the RM access rights implementation
// is enabled; see g_bRsAccessEnabled.
//
#endif // _CONTROL_H_

3
src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -126,6 +126,7 @@ NV_STATUS nvGpuOpsQueryCesCaps(struct gpuDevice *device,
NV_STATUS nvGpuOpsDupAllocation(struct gpuAddressSpace *srcVaSpace,
NvU64 srcAddress,
struct gpuAddressSpace *dstVaSpace,
NvU64 dstVaAlignment,
NvU64 *dstAddress);
NV_STATUS nvGpuOpsDupMemory(struct gpuDevice *device,

4
src/nvidia/inc/kernel/rmapi/rmapi.h
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@@ -191,6 +191,10 @@ struct _RM_API
NV_STATUS (*MapToCpuWithSecInfo)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemory,
NvU64 offset, NvU64 length, NvP64 *ppCpuVirtAddr, NvU32 flags, API_SECURITY_INFO *pSecInfo);
// Map memory v2. Pass in flags as a pointer for in/out access
NV_STATUS (*MapToCpuWithSecInfoV2)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemory,
NvU64 offset, NvU64 length, NvP64 *ppCpuVirtAddr, NvU32 *flags, API_SECURITY_INFO *pSecInfo);
// Unmap memory with default security attributes and local pointers (no NvP64)
NV_STATUS (*UnmapFromCpu)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemory, void *pLinearAddress,
NvU32 flags, NvU32 ProcessId);