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This commit is contained in:
Andy Ritger
2022-10-10 14:59:24 -07:00
parent fe0728787f
commit 90eb10774f
758 changed files with 88383 additions and 26493 deletions
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3
src/nvidia/inc/kernel/gpu/ccu/kernel_ccu.h Normal file
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@@ -0,0 +1,3 @@
#include "g_kernel_ccu_nvoc.h"

3
src/nvidia/inc/kernel/gpu/ccu/kernel_ccu_api.h Normal file
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@@ -0,0 +1,3 @@
#include "g_kernel_ccu_api_nvoc.h"

46
src/nvidia/inc/kernel/gpu/ce/kernel_ce_gv100_private.h
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@@ -24,52 +24,6 @@
#ifndef KERNEL_CE_GV100_PRIVATE_H
#define KERNEL_CE_GV100_PRIVATE_H
#define MAX_CE_CNT 15
/*
* sysmemLinks
* Represents the number of sysmem links detected
* This affects how many PCEs LCE0(sysmem read CE)
* and LCE1(sysmem write CE) should be mapped to
* maxLinksPerPeer
* Represents the maximum number of peer links
* between this GPU and all its peers. This affects
* how many PCEs LCE3(P2P CE) should be mapped to
* numPeers
* Represents the number of Peer GPUs discovered so far
* bSymmetric
* Represents whether the topology detected so far
* is symmetric i.e. has same number of links to all
* peers connected through nvlink. This affects how
* many PCEs to assign to LCEs3-5 (nvlink P2P CEs)
* bSwitchConfig
* Represents whether the config listed is intended
* for use with nvswitch systems
* pceLceMap
* Value of NV_CE_PCE2LCE_CONFIG0 register with the
* above values for sysmemLinks, maxLinksPerPeer,
* numLinks and bSymmetric
* grceConfig
* Value of NV_CE_GRCE_CONFIG register with the
* above values for sysmemLinks, maxLinksPerPeer,
* numLinks and bSymmetric
* exposeCeMask
* Mask of CEs to expose to clients for the above
* above values for sysmemLinks, maxLinksPerPeer,
* numLinks and bSymmetric
*/
typedef struct NVLINK_CE_AUTO_CONFIG_TABLE
{
NvU32 sysmemLinks;
NvU32 maxLinksPerPeer;
NvU32 numPeers;
NvBool bSymmetric;
NvBool bSwitchConfig;
NvU32 pceLceMap[MAX_CE_CNT];
NvU32 grceConfig[MAX_CE_CNT];
NvU32 exposeCeMask;
} NVLINK_CE_AUTO_CONFIG_TABLE;
//
// General convention decided on between HW and SW:
// - CE2 is for SYSMEM reads

3
src/nvidia/inc/kernel/gpu/fsp/kern_fsp.h Normal file
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@@ -0,0 +1,3 @@
#include "g_kern_fsp_nvoc.h"

28
src/nvidia/inc/kernel/gpu/fsp/kern_fsp_retval.h Normal file
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@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#define FSP_OK (0x00U)
#define FSP_ERR_IFS_ERR_INVALID_STATE (0x9EU)
#define FSP_ERR_IFR_FILE_NOT_FOUND (0x9FU)
#define FSP_ERR_IFS_ERR_NOT_SUPPORTED (0xA0U)
#define FSP_ERR_IFS_ERR_INVALID_DATA (0xA1U)

12
src/nvidia/inc/kernel/gpu/gpu_child_list.h
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@@ -90,6 +90,9 @@
#if GPU_CHILD_MODULE(FBFLCN)
GPU_CHILD_SINGLE_INST( OBJFBFLCN, GPU_GET_FBFLCN, 1, NV_FALSE, NV_FALSE, pFbflcn )
#endif
#if GPU_CHILD_MODULE(HSHUBMANAGER)
GPU_CHILD_SINGLE_INST( OBJHSHUBMANAGER, GPU_GET_HSHUBMANAGER, 1, NV_FALSE, NV_FALSE, pHshMgr )
#endif
#if GPU_CHILD_MODULE(HSHUB)
GPU_CHILD_MULTI_INST ( OBJHSHUB, GPU_GET_HSHUB, GPU_MAX_HSHUBS, NV_FALSE, NV_FALSE, pHshub )
#endif
@@ -120,9 +123,6 @@
#if GPU_CHILD_MODULE(KERNEL_GMMU)
GPU_CHILD_SINGLE_INST( KernelGmmu, GPU_GET_KERNEL_GMMU, 1, NV_FALSE, NV_FALSE, pKernelGmmu )
#endif
#if GPU_CHILD_MODULE(KERNEL_NVDEC)
GPU_CHILD_SINGLE_INST( KernelNvdec, GPU_GET_KERNEL_NVDEC, 1, NV_FALSE, NV_FALSE, pKernelNvdec )
#endif
#if GPU_CHILD_MODULE(KERNEL_SEC2)
GPU_CHILD_SINGLE_INST( KernelSec2, GPU_GET_KERNEL_SEC2, 1, NV_FALSE, NV_FALSE, pKernelSec2 )
#endif
@@ -291,9 +291,15 @@
#if GPU_CHILD_MODULE(GSP)
GPU_CHILD_SINGLE_INST( Gsp, GPU_GET_GSP, 1, NV_FALSE, NV_FALSE, pGsp )
#endif
#if RMCFG_MODULE_KERNEL_FSP && GPU_CHILD_MODULE(KERNEL_FSP)
GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_FALSE, NV_FALSE, pKernelFsp )
#endif
#if GPU_CHILD_MODULE(OFA)
GPU_CHILD_SINGLE_INST( OBJOFA, GPU_GET_OFA, 1, NV_FALSE, NV_FALSE, pOfa )
#endif
#if RMCFG_MODULE_KERNEL_CCU && GPU_CHILD_MODULE(KERNEL_CCU)
GPU_CHILD_SINGLE_INST( KernelCcu, GPU_GET_KERNEL_CCU, 1, NV_FALSE, NV_FALSE, pKernelCcu )
#endif
// Undefine the entry macros to simplify call sites
#undef GPU_CHILD

8
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
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@@ -35,6 +35,7 @@
#include "ctrl/ctrl2080/ctrl2080bios.h"
#include "ctrl/ctrl2080/ctrl2080fb.h"
#include "ctrl/ctrl2080/ctrl2080gpu.h"
#include "ctrl/ctrla083.h"
#include "gpu/gpu.h" // COMPUTE_BRANDING_TYPE
#include "vgpu/rpc_headers.h" // MAX_GPC_COUNT
@@ -109,8 +110,8 @@ typedef struct GspStaticConfigInfo_t
NvBool bClRootportNeedsNosnoopWAR;
VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads;
VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution;
NVA083_CTRL_VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS displaylessMaxHeads;
NVA083_CTRL_VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS displaylessMaxResolution;
NvU64 displaylessMaxPixels;
// Client handle for internal RMAPI control.
@@ -121,6 +122,8 @@ typedef struct GspStaticConfigInfo_t
// Subdevice handle for internal RMAPI control.
NvHandle hInternalSubdevice;
NvBool bAtsSupported;
} GspStaticConfigInfo;
// Pushed from CPU-RM to GSP-RM
@@ -133,6 +136,7 @@ typedef struct GspSystemInfo
NvU64 simAccessBufPhysAddr;
NvU64 pcieAtomicsOpMask;
NvU64 consoleMemSize;
NvU64 maxUserVa;
NvU32 pciConfigMirrorBase;
NvU32 pciConfigMirrorSize;
NvU8 oorArch;

21
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
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@@ -81,13 +81,14 @@
#define MC_ENGINE_IDX_NVJPG 42
#define MC_ENGINE_IDX_NVJPEG MC_ENGINE_IDX_NVJPG
#define MC_ENGINE_IDX_NVJPEG0 MC_ENGINE_IDX_NVJPEG
#define MC_ENGINE_IDX_RESERVED43 43
#define MC_ENGINE_IDX_RESERVED44 44
#define MC_ENGINE_IDX_RESERVED45 45
#define MC_ENGINE_IDX_RESERVED46 46
#define MC_ENGINE_IDX_RESERVED47 47
#define MC_ENGINE_IDX_RESERVED48 48
#define MC_ENGINE_IDX_RESERVED49 49
#define MC_ENGINE_IDX_NVJPEG1 43
#define MC_ENGINE_IDX_NVJPEG2 44
#define MC_ENGINE_IDX_NVJPEG3 45
#define MC_ENGINE_IDX_NVJPEG4 46
#define MC_ENGINE_IDX_NVJPEG5 47
#define MC_ENGINE_IDX_NVJPEG6 48
#define MC_ENGINE_IDX_NVJPEG7 49
#define MC_ENGINE_IDX_REPLAYABLE_FAULT 50
#define MC_ENGINE_IDX_ACCESS_CNTR 51
#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT 52
@@ -101,9 +102,9 @@
#define MC_ENGINE_IDX_NVDEC2 58
#define MC_ENGINE_IDX_NVDEC3 59
#define MC_ENGINE_IDX_NVDEC4 60
#define MC_ENGINE_IDX_RESERVED61 61
#define MC_ENGINE_IDX_RESERVED62 62
#define MC_ENGINE_IDX_RESERVED63 63
#define MC_ENGINE_IDX_NVDEC5 61
#define MC_ENGINE_IDX_NVDEC6 62
#define MC_ENGINE_IDX_NVDEC7 63
#define MC_ENGINE_IDX_CPU_DOORBELL 64
#define MC_ENGINE_IDX_PRIV_DOORBELL 65
#define MC_ENGINE_IDX_MMU_ECC_ERROR 66

6
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h
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@@ -45,6 +45,12 @@
#include "addrtree.h"
#include "nvmisc.h"
#if defined(SRT_BUILD)
#define RMCFG_MODULE_x 1
#else
#include "rmconfig.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif

3
src/nvidia/inc/kernel/gpu/nvdec/kernel_nvdec.h
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@@ -1,3 +0,0 @@
#include "g_kernel_nvdec_nvoc.h"

31
src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_ccu_internal.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_MAP,
RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL))
NV_STATUS subdeviceCtrlCmdCcuMap(Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *pParams);
RMCTRL_EXPORT(NV2080_CTRL_CMD_INTERNAL_CCU_UNMAP,
RMCTRL_FLAGS(KERNEL_PRIVILEGED, ROUTE_TO_PHYSICAL, INTERNAL))
NV_STATUS subdeviceCtrlCmdCcuUnmap(Subdevice *pSubdevice);