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525.116.03

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This commit is contained in:
Andy Ritger
2023-04-25 14:05:57 -07:00
parent ebcc6656ff
commit a0e46cabd3
48 changed files with 460 additions and 156 deletions
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8
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -335,6 +335,14 @@ namespace DisplayPort
//
bool bPowerDownPhyBeforeD3;
//
// Reset the MSTM_CTRL registers on Synaptics branch device irrespective of
// IRQ VECTOR register having stale message. Synaptics device needs to reset
// the topology before issue of new LAM message if previous LAM was not finished
// bug 3928070
//
bool bForceClearPendingMsg;
void sharedInit();
ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink);

4
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -5756,7 +5756,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
discoveryManager = new DiscoveryManager(messageManager, this, timer, hal);
// Check and clear if any pending message here
if (hal->clearPendingMsg())
if (hal->clearPendingMsg() || bForceClearPendingMsg)
{
DP_LOG(("DP> Stale MSG found: set branch to D3 and back to D0..."));
if (hal->isAtLeastVersion(1, 4))
@@ -6799,6 +6799,7 @@ bool ConnectorImpl::updatePsrLinkState(bool bTrainLink)
{
// Bug 3438892 If the panel is turned off the reciever on its side,
// force panel link on by writting 600 = 1
this->hal->setDirtyLinkStatus(true);
if (this->isLinkLost())
{
hal->setPowerState(PowerStateD0);
@@ -6963,5 +6964,6 @@ void ConnectorImpl::configInit()
bNoFallbackInPostLQA = 0;
LT2FecLatencyMs = 0;
bDscCapBasedOnParent = false;
bForceClearPendingMsg = false;
}

11
src/common/displayport/src/dp_wardatabase.cpp
View File

@@ -84,6 +84,17 @@ void ConnectorImpl::applyOuiWARs()
//
LT2FecLatencyMs = 57;
//
// This is to reset the MSTM control bit on the branch device. On this
// device, if continuous LAM message are sent very close then IRQ vector
// will fail to see stale/pending message and will not reset the MSTM_CTRL
// register. Currently making this specific to linux so as to have minimum
// effect on windows. Later proper fix for this will be generic.
//
#if defined(NV_UNIX)
bForceClearPendingMsg = true;
#endif
if (bDscMstCapBug3143315)
{
//

22
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r528_79
#define NV_BUILD_BRANCH r528_95
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r528_79
#define NV_PUBLIC_BRANCH r528_95
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r528_79-332"
#define NV_BUILD_CHANGELIST_NUM (32663405)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r528_95-360"
#define NV_BUILD_CHANGELIST_NUM (32748200)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r525/r528_79-332"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32663405)
#define NV_BUILD_NAME "rel/gpu_drv/r525/r528_95-360"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32748200)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r528_79-9"
#define NV_BUILD_CHANGELIST_NUM (32663405)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "528.89"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32663405)
#define NV_BUILD_BRANCH_VERSION "r528_95-2"
#define NV_BUILD_CHANGELIST_NUM (32745585)
#define NV_BUILD_TYPE "Nightly"
#define NV_BUILD_NAME "r528_95-230419"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32745585)
#define NV_BUILD_BRANCH_BASE_VERSION R525
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "525.105.17"
#define NV_VERSION_STRING "525.116.03"
#else

3
src/common/modeset/hdmipacket/nvhdmipkt.c
View File

@@ -315,7 +315,8 @@ NvHdmi_QueryFRLConfig(NvHdmiPkt_Handle libHandle,
}
// if there is no FRL capability reported fail this call
if (pSinkCaps->linkMaxFRLRate == HDMI_FRL_DATA_RATE_NONE)
if ((pSrcCaps->linkMaxFRLRate == HDMI_FRL_DATA_RATE_NONE) ||
(pSinkCaps->linkMaxFRLRate == HDMI_FRL_DATA_RATE_NONE))
{
return NVHDMIPKT_FAIL;
}

14
src/common/nvswitch/common/inc/soe/soeifcore.h
View File

@@ -86,6 +86,11 @@ enum
* Read Power
*/
RM_SOE_CORE_CMD_GET_POWER_VALUES,
/*!
* Set NPORT interrupts
*/
RM_SOE_CORE_CMD_SET_NPORT_INTRS,
};
// Timeout for SOE reset callback function
@@ -162,6 +167,13 @@ typedef struct
NvU8 cmdType;
} RM_SOE_CORE_CMD_GET_POWER;
typedef struct
{
NvU8 cmdType;
NvU32 nport;
NvBool bEnable;
} RM_SOE_CORE_CMD_NPORT_INTRS;
typedef union
{
NvU8 cmdType;
@@ -174,9 +186,9 @@ typedef union
RM_SOE_CORE_CMD_GET_VOLTAGE getVoltage;
RM_SOE_CORE_CMD_L2_STATE l2State;
RM_SOE_CORE_CMD_GET_POWER getPower;
RM_SOE_CORE_CMD_NPORT_INTRS nportIntrs;
} RM_SOE_CORE_CMD;
typedef struct
{
NvU8 msgType;

2
src/common/nvswitch/kernel/inc/ls10/ls10.h
View File

@@ -792,7 +792,6 @@ typedef const struct
#define nvswitch_ctrl_get_info_ls10 nvswitch_ctrl_get_info_lr10
#define nvswitch_ctrl_set_switch_port_config_ls10 nvswitch_ctrl_set_switch_port_config_lr10
#define nvswitch_ctrl_get_fom_values_ls10 nvswitch_ctrl_get_fom_values_lr10
#define nvswitch_ctrl_get_throughput_counters_ls10 nvswitch_ctrl_get_throughput_counters_lr10
#define nvswitch_save_nvlink_seed_data_from_minion_to_inforom_ls10 nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10
@@ -868,7 +867,6 @@ NvlStatus nvswitch_ctrl_get_nvlink_status_ls10(nvswitch_device *device, NVSWITCH
NvlStatus nvswitch_ctrl_get_info_lr10(nvswitch_device *device, NVSWITCH_GET_INFO *p);
NvlStatus nvswitch_ctrl_set_switch_port_config_lr10(nvswitch_device *device, NVSWITCH_SET_SWITCH_PORT_CONFIG *p);
NvlStatus nvswitch_ctrl_get_fom_values_lr10(nvswitch_device *device, NVSWITCH_GET_FOM_VALUES_PARAMS *p);
NvlStatus nvswitch_ctrl_get_throughput_counters_lr10(nvswitch_device *device, NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS *p);
void nvswitch_save_nvlink_seed_data_from_minion_to_inforom_lr10(nvswitch_device *device, NvU32 linkId);
void nvswitch_store_seed_data_from_inforom_to_corelib_lr10(nvswitch_device *device);

2
src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h
View File

@@ -47,5 +47,5 @@ typedef enum _MINION_STATUS
} MINION_STATUS;
#define LINKSTATUS_EMERGENCY_SHUTDOWN 0x29
#define LINKSTATUS_INITPHASE1 0x24
#define LINKSTATUS_INITPHASE1 0x24
#endif // _MINION_NVLINK_DEFINES_PUBLIC_H_

2
src/common/nvswitch/kernel/inc/ls10/soe_ls10.h
View File

@@ -45,5 +45,5 @@ NvlStatus nvswitch_soe_register_event_callbacks_ls10(nvswitch_device *device);
NvlStatus nvswitch_soe_restore_nport_state_ls10(nvswitch_device *device, NvU32 nport);
NvlStatus nvswitch_soe_issue_nport_reset_ls10(nvswitch_device *device, NvU32 nport);
void nvswitch_soe_init_l2_state_ls10(nvswitch_device *device);
NvlStatus nvswitch_soe_set_nport_interrupts_ls10(nvswitch_device *device, NvU32 nport, NvBool bEnable);
#endif //_SOE_LS10_H_

8
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
View File

@@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b,
0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2,
0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc,
0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043,
0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043,
0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200,
0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d,
0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4,
@@ -590,7 +590,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0xb3070bf4, 0xf80a00a4, 0xf8020a02, 0xffb9e400, 0xf4020a0f, 0x7cd9451b, 0x98000029, 0x903e049f,
0xf9180045, 0x00903308, 0x09f91828, 0x21009033, 0x5802f958, 0x93f003fe, 0x0c94b600, 0x08f4b9a6,
0xffe9e40f, 0x0c94b6ff, 0x0df4b9a6, 0x04ff980a, 0xd200f4b3, 0x350acfa0, 0x30f400f8, 0x05dcdff8,
0x52f90000, 0xa4b2ffbf, 0xfe0149fe, 0x99900142, 0xb2b0b21c, 0xa0d5b2c3, 0x0a14bd9f, 0x18229035,
0x52f90000, 0xa4b2ffbf, 0xfe0149fe, 0x99900142, 0xb2b0b21c, 0xa0d5b2c3, 0xbd350a9f, 0x18229014,
0x0046513e, 0x0bb24ab2, 0x2db2040c, 0x0028d77e, 0x8900ad33, 0xb329bf00, 0x900e0094, 0x00902011,
0x46513e04, 0x019eb900, 0x8904e9fd, 0xffff0000, 0xfcf094e9, 0x01f6f00b, 0x00ff00d9, 0x94e9ffff,
0xf00bbcf0, 0xf0d901b6, 0xfff0f0f0, 0xccf094e9, 0x01c6f00b, 0xccccccd9, 0x94e9ffcc, 0xf00bdcf0,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xf4188925, 0x3294f034, 0x06c315a3, 0x41c3e219,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x8cd89b95, 0x33df19d3, 0xaba62f3f, 0x5fd448c8,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xb63be2f4, 0x80eae4c6, 0xf2d546fa, 0xb745274e,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x226d94df, 0xdb2e0eeb, 0xd11c2f47, 0x7666acd9,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

8
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
View File

@@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b,
0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2,
0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc,
0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043,
0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043,
0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200,
0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d,
0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4,
@@ -590,7 +590,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0xb3070bf4, 0xf80a00a4, 0xf8020a02, 0xffb9e400, 0xf4020a0f, 0x7cd9451b, 0x98000029, 0x903e049f,
0xf9180045, 0x00903308, 0x09f91828, 0x21009033, 0x5802f958, 0x93f003fe, 0x0c94b600, 0x08f4b9a6,
0xffe9e40f, 0x0c94b6ff, 0x0df4b9a6, 0x04ff980a, 0xd200f4b3, 0x350acfa0, 0x30f400f8, 0x05dcdff8,
0x52f90000, 0xa4b2ffbf, 0xfe0149fe, 0x99900142, 0xb2b0b21c, 0xa0d5b2c3, 0x0a14bd9f, 0x18229035,
0x52f90000, 0xa4b2ffbf, 0xfe0149fe, 0x99900142, 0xb2b0b21c, 0xa0d5b2c3, 0xbd350a9f, 0x18229014,
0x0046513e, 0x0bb24ab2, 0x2db2040c, 0x0028d77e, 0x8900ad33, 0xb329bf00, 0x900e0094, 0x00902011,
0x46513e04, 0x019eb900, 0x8904e9fd, 0xffff0000, 0xfcf094e9, 0x01f6f00b, 0x00ff00d9, 0x94e9ffff,
0xf00bbcf0, 0xf0d901b6, 0xfff0f0f0, 0xccf094e9, 0x01c6f00b, 0xccccccd9, 0x94e9ffcc, 0xf00bdcf0,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xf4188925, 0x3294f034, 0x06c315a3, 0x41c3e219,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x8cd89b95, 0x33df19d3, 0xaba62f3f, 0x5fd448c8,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xb63be2f4, 0x80eae4c6, 0xf2d546fa, 0xb745274e,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x226d94df, 0xdb2e0eeb, 0xd11c2f47, 0x7666acd9,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

24
src/common/nvswitch/kernel/lr10/lr10.c
View File

@@ -3855,7 +3855,7 @@ nvswitch_initialize_device_state_lr10
}
else
{
NVSWITCH_PRINT(device, ERROR,
NVSWITCH_PRINT(device, WARN,
"%s: Skipping SPI init.\n",
__FUNCTION__);
}
@@ -3874,7 +3874,7 @@ nvswitch_initialize_device_state_lr10
}
else
{
NVSWITCH_PRINT(device, ERROR,
NVSWITCH_PRINT(device, WARN,
"%s: Skipping SMBPBI init.\n",
__FUNCTION__);
}
@@ -4579,17 +4579,6 @@ _nvswitch_get_info_revision_minor_ext
return (DRF_VAL(_PSMC, _BOOT_42, _MINOR_EXTENDED_REVISION, val));
}
static NvU32
_nvswitch_get_info_voltage
(
nvswitch_device *device
)
{
NvU32 voltage = 0;
return voltage;
}
static NvBool
_nvswitch_inforom_nvl_supported
(
@@ -4769,7 +4758,7 @@ nvswitch_ctrl_get_info_lr10
p->info[i] = device->switch_pll.vco_freq_khz;
break;
case NVSWITCH_GET_INFO_INDEX_VOLTAGE_MVOLT:
p->info[i] = _nvswitch_get_info_voltage(device);
retval = -NVL_ERR_NOT_SUPPORTED;
break;
case NVSWITCH_GET_INFO_INDEX_PHYSICAL_ID:
p->info[i] = nvswitch_read_physical_id(device);
@@ -6413,13 +6402,6 @@ nvswitch_ctrl_get_fom_values_lr10
return -NVL_BAD_ARGS;
}
if (nvswitch_is_link_in_reset(device, link))
{
NVSWITCH_PRINT(device, ERROR, "%s: link #%d is in reset\n",
__FUNCTION__, p->linkId);
return -NVL_ERR_INVALID_STATE;
}
status = nvswitch_minion_get_dl_status(device, p->linkId,
NV_NVLSTAT_TR16, 0, &statData);
p->figureOfMeritValues[0] = (NvU16) (statData & 0xFFFF);

2
src/common/nvswitch/kernel/ls10/intr_ls10.c
View File

@@ -6335,7 +6335,7 @@ _nvswitch_service_nvlipt_lnk_nonfatal_ls10
lnkStateRequest = NVSWITCH_LINK_RD32_LS10(device, link_info->linkNumber,
NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_REQUEST);
if(FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _REQUEST, _ACTIVE, lnkStateRequest) &&
if(FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _REQUEST, _ACTIVE, lnkStateRequest) &&
linkState == NV_NVLDL_TOP_LINK_STATE_STATE_FAULT)
{
chip_device->deferredLinkErrors[link].bResetAndDrainRetry = NV_TRUE;

72
src/common/nvswitch/kernel/ls10/ls10.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1103,6 +1103,18 @@ nvswitch_link_disable_interrupts_ls10
instance = link / NVSWITCH_LINKS_PER_NVLIPT_LS10;
localLinkIdx = link % NVSWITCH_LINKS_PER_NVLIPT_LS10;
if (nvswitch_is_soe_supported(device))
{
nvswitch_soe_set_nport_interrupts_ls10(device, link, NV_FALSE);
}
else
{
NVSWITCH_NPORT_WR32_LS10(device, link, _NPORT, _ERR_CONTROL_COMMON_NPORT,
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 0x0) |
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 0x0) |
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 0x0));
}
NVSWITCH_ENG_WR32(device, NVLW, , instance, _NVLW, _LINK_INTR_0_MASK(localLinkIdx),
DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _FATAL, 0x0) |
DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _NONFATAL, 0x0) |
@@ -1133,6 +1145,18 @@ _nvswitch_link_reset_interrupts_ls10
NvU32 eng_instance = link / NVSWITCH_LINKS_PER_NVLIPT_LS10;
NvU32 localLinkNum = link % NVSWITCH_LINKS_PER_NVLIPT_LS10;
if (nvswitch_is_soe_supported(device))
{
nvswitch_soe_set_nport_interrupts_ls10(device, link, NV_TRUE);
}
else
{
NVSWITCH_NPORT_WR32_LS10(device, link, _NPORT, _ERR_CONTROL_COMMON_NPORT,
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _CORRECTABLEENABLE, 0x1) |
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 0x1) |
DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 0x1));
}
NVSWITCH_ENG_WR32(device, NVLW, , eng_instance, _NVLW, _LINK_INTR_0_MASK(localLinkNum),
DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _FATAL, 0x1) |
DRF_NUM(_NVLW, _LINK_INTR_0_MASK, _NONFATAL, 0x0) |
@@ -1477,7 +1501,7 @@ nvswitch_reset_and_drain_links_ls10
// DEBUG_CLEAR (0x144) register
// - Assert NPortWarmReset[i] using the WARMRESET (0x140) register
//
// nvswitch_soe_issue_nport_reset_ls10(device, link);
nvswitch_soe_issue_nport_reset_ls10(device, link);
//
// Step 5.0 : Issue Minion request to perform the link reset sequence
@@ -1555,7 +1579,7 @@ nvswitch_reset_and_drain_links_ls10
// - Assert NPORT INITIALIZATION and program the state tracking RAMS
// - Restore NPORT state after reset
//
// nvswitch_soe_restore_nport_state_ls10(device, link);
nvswitch_soe_restore_nport_state_ls10(device, link);
// Step 7.0 : Re-program the routing table for DBEs
@@ -2715,6 +2739,46 @@ nvswitch_get_num_links_ls10
return NVSWITCH_NUM_LINKS_LS10;
}
NvlStatus
nvswitch_ctrl_get_fom_values_ls10
(
nvswitch_device *device,
NVSWITCH_GET_FOM_VALUES_PARAMS *p
)
{
NvlStatus status;
NvU32 statData;
nvlink_link *link;
link = nvswitch_get_link(device, p->linkId);
if (link == NULL)
{
NVSWITCH_PRINT(device, ERROR, "%s: link #%d invalid\n",
__FUNCTION__, p->linkId);
return -NVL_BAD_ARGS;
}
if (nvswitch_is_link_in_reset(device, link))
{
NVSWITCH_PRINT(device, ERROR, "%s: link #%d is in reset\n",
__FUNCTION__, p->linkId);
return -NVL_ERR_INVALID_STATE;
}
status = nvswitch_minion_get_dl_status(device, p->linkId,
NV_NVLSTAT_TR16, 0, &statData);
p->figureOfMeritValues[0] = (NvU16) (statData & 0xFFFF);
p->figureOfMeritValues[1] = (NvU16) ((statData >> 16) & 0xFFFF);
status = nvswitch_minion_get_dl_status(device, p->linkId,
NV_NVLSTAT_TR17, 0, &statData);
p->figureOfMeritValues[2] = (NvU16) (statData & 0xFFFF);
p->figureOfMeritValues[3] = (NvU16) ((statData >> 16) & 0xFFFF);
p->numLanes = nvswitch_get_sublink_width(device, p->linkId);
return status;
}
void
nvswitch_set_fatal_error_ls10
@@ -5406,7 +5470,7 @@ nvswitch_ctrl_get_board_part_number_ls10
if (!pInforom->OBD.bValid)
{
NVSWITCH_PRINT(device, ERROR, "OBD data is not available\n");
return -NVL_ERR_GENERIC;
return -NVL_ERR_NOT_SUPPORTED;
}
pOBDObj = &pInforom->OBD.object.v2;

61
src/common/nvswitch/kernel/ls10/soe_ls10.c
View File

@@ -400,7 +400,7 @@ nvswitch_soe_init_l2_state_ls10
nvswitch_os_memset(&cmd, 0, sizeof(cmd));
cmd.hdr.unitId = RM_SOE_UNIT_CORE;
cmd.hdr.size = sizeof(cmd);
cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, L2_STATE);
pL2State = &cmd.cmd.core.l2State;
pL2State->cmdType = RM_SOE_CORE_CMD_INIT_L2_STATE;
@@ -420,6 +420,65 @@ nvswitch_soe_init_l2_state_ls10
}
}
/*
* @Brief : Enable/Disable NPORT interrupts
*
* @param[in] device
* @param[in] nport
*/
NvlStatus
nvswitch_soe_set_nport_interrupts_ls10
(
nvswitch_device *device,
NvU32 nport,
NvBool bEnable
)
{
FLCN *pFlcn;
NvU32 cmdSeqDesc = 0;
NV_STATUS status;
RM_FLCN_CMD_SOE cmd;
NVSWITCH_TIMEOUT timeout;
RM_SOE_CORE_CMD_NPORT_INTRS *pNportIntrs;
if (!nvswitch_is_soe_supported(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s: SOE is not supported\n",
__FUNCTION__);
return -NVL_ERR_INVALID_STATE;
}
pFlcn = device->pSoe->pFlcn;
nvswitch_os_memset(&cmd, 0, sizeof(cmd));
cmd.hdr.unitId = RM_SOE_UNIT_CORE;
cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, NPORT_INTRS);
pNportIntrs = &cmd.cmd.core.nportIntrs;
pNportIntrs->cmdType = RM_SOE_CORE_CMD_SET_NPORT_INTRS;
pNportIntrs->nport = nport;
pNportIntrs->bEnable = bEnable;
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&cmd,
NULL, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to send SET_NPORT_INTRS command to SOE, status 0x%x\n",
__FUNCTION__, status);
return -NVL_ERR_GENERIC;
}
return NVL_SUCCESS;
}
/*
* @Brief : Init sequence for SOE FSP RISCV image
*