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This commit is contained in:
Andy Ritger
2023-04-25 14:05:57 -07:00
parent ebcc6656ff
commit a0e46cabd3
48 changed files with 460 additions and 156 deletions
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12
src/nvidia/generated/g_gpu_nvoc.c
View File

@@ -220,6 +220,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
pThis->setProperty(pThis, PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK, ((NvBool)(0 == 0)));
}
pThis->setProperty(pThis, PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE, ((NvBool)(0 == 0)));
pThis->setProperty(pThis, PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322, ((NvBool)(0 != 0)));
pThis->boardId = ~0;
@@ -313,6 +314,17 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
{
pThis->bSriovCapable = ((NvBool)(0 == 0));
}
// Hal field -- bEnableBar1SparseForFillPteMemUnmap
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */
{
pThis->bEnableBar1SparseForFillPteMemUnmap = ((NvBool)(0 == 0));
}
// default
else
{
pThis->bEnableBar1SparseForFillPteMemUnmap = ((NvBool)(0 != 0));
}
}
NV_STATUS __nvoc_ctor_Object(Object* );

13
src/nvidia/generated/g_gpu_nvoc.h
View File

@@ -7,7 +7,7 @@ extern "C" {
#endif
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -843,6 +843,7 @@ struct OBJGPU {
NvBool PDB_PROP_GPU_IN_HIBERNATE;
NvBool PDB_PROP_GPU_IN_PM_CODEPATH;
NvBool PDB_PROP_GPU_IN_PM_RESUME_CODEPATH;
NvBool PDB_PROP_GPU_PM_RESUME_WAR_BUG_3936017_ENABLED;
NvBool PDB_PROP_GPU_STATE_INITIALIZED;
NvBool PDB_PROP_GPU_EMULATION;
NvBool PDB_PROP_GPU_PRIMARY_DEVICE;
@@ -918,6 +919,7 @@ struct OBJGPU {
NvBool PDB_PROP_GPU_IS_MXM_3X;
NvBool PDB_PROP_GPU_GSYNC_III_ATTACHED;
NvBool PDB_PROP_GPU_QSYNC_II_ATTACHED;
NvBool PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322;
OS_GPU_INFO *pOsGpuInfo;
OS_RM_CAPS *pOsRmCaps;
NvU32 halImpl;
@@ -1106,6 +1108,7 @@ struct OBJGPU {
NvU8 fabricProbeSlowdownThreshold;
NvBool bVgpuGspPluginOffloadEnabled;
NvBool bSriovCapable;
NvBool bEnableBar1SparseForFillPteMemUnmap;
};
#ifndef __NVOC_CLASS_OBJGPU_TYPEDEF__
@@ -1237,6 +1240,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU;
#define PDB_PROP_GPU_IS_BR03_PRESENT_BASE_NAME PDB_PROP_GPU_IS_BR03_PRESENT
#define PDB_PROP_GPU_IS_GEMINI_BASE_CAST
#define PDB_PROP_GPU_IS_GEMINI_BASE_NAME PDB_PROP_GPU_IS_GEMINI
#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_CAST
#define PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322_BASE_NAME PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322
#define PDB_PROP_GPU_STATE_INITIALIZED_BASE_CAST
#define PDB_PROP_GPU_STATE_INITIALIZED_BASE_NAME PDB_PROP_GPU_STATE_INITIALIZED
#define PDB_PROP_GPU_NV_USERMODE_ENABLED_BASE_CAST
@@ -1261,12 +1266,14 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU;
#define PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED
#define PDB_PROP_GPU_ZERO_FB_BASE_CAST
#define PDB_PROP_GPU_ZERO_FB_BASE_NAME PDB_PROP_GPU_ZERO_FB
#define PDB_PROP_GPU_PM_RESUME_WAR_BUG_3936017_ENABLED_BASE_CAST
#define PDB_PROP_GPU_PM_RESUME_WAR_BUG_3936017_ENABLED_BASE_NAME PDB_PROP_GPU_PM_RESUME_WAR_BUG_3936017_ENABLED
#define PDB_PROP_GPU_SWRL_GRANULAR_LOCKING_BASE_CAST
#define PDB_PROP_GPU_SWRL_GRANULAR_LOCKING_BASE_NAME PDB_PROP_GPU_SWRL_GRANULAR_LOCKING
#define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_CAST
#define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_NAME PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK
#define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_CAST
#define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_NAME PDB_PROP_GPU_TEGRA_SOC_IGPU
#define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_CAST
#define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_NAME PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK
#define PDB_PROP_GPU_ATS_SUPPORTED_BASE_CAST
#define PDB_PROP_GPU_ATS_SUPPORTED_BASE_NAME PDB_PROP_GPU_ATS_SUPPORTED
#define PDB_PROP_GPU_EMULATION_BASE_CAST

9
src/nvidia/generated/g_nv_name_released.h
View File

@@ -918,6 +918,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x24B9, 0x0000, 0x0000, "NVIDIA RTX A3000 12GB Laptop GPU" },
{ 0x24BA, 0x0000, 0x0000, "NVIDIA RTX A4500 Laptop GPU" },
{ 0x24BB, 0x0000, 0x0000, "NVIDIA RTX A3000 12GB Laptop GPU" },
{ 0x24C7, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060" },
{ 0x24C9, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060 Ti" },
{ 0x24DC, 0x0000, 0x0000, "NVIDIA GeForce RTX 3080 Laptop GPU" },
{ 0x24DD, 0x0000, 0x0000, "NVIDIA GeForce RTX 3070 Laptop GPU" },
@@ -963,6 +964,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x25B9, 0x0000, 0x0000, "NVIDIA RTX A1000 Laptop GPU" },
{ 0x25BA, 0x0000, 0x0000, "NVIDIA RTX A2000 8GB Laptop GPU" },
{ 0x25BB, 0x0000, 0x0000, "NVIDIA RTX A500 Laptop GPU" },
{ 0x25BC, 0x0000, 0x0000, "NVIDIA RTX A1000 6GB Laptop GPU" },
{ 0x25BD, 0x0000, 0x0000, "NVIDIA RTX A500 Laptop GPU" },
{ 0x25E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Ti Laptop GPU" },
{ 0x25E2, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Laptop GPU" },
{ 0x25E5, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Laptop GPU" },
@@ -980,8 +983,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x26B5, 0x17da, 0x10de, "NVIDIA L40" },
{ 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" },
{ 0x2717, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" },
{ 0x2730, 0x0000, 0x0000, "NVIDIA RTX 5000 Ada Generation Laptop GPU" },
{ 0x2757, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" },
{ 0x2782, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Ti" },
{ 0x2786, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070" },
{ 0x27A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" },
{ 0x27B0, 0x16fa, 0x1028, "NVIDIA RTX 4000 SFF Ada Generation" },
{ 0x27B0, 0x16fa, 0x103c, "NVIDIA RTX 4000 SFF Ada Generation" },
@@ -989,11 +994,15 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x27B0, 0x16fa, 0x17aa, "NVIDIA RTX 4000 SFF Ada Generation" },
{ 0x27B8, 0x16ca, 0x10de, "NVIDIA L4" },
{ 0x27B8, 0x16ee, 0x10de, "NVIDIA L4" },
{ 0x27BA, 0x0000, 0x0000, "NVIDIA RTX 4000 Ada Generation Laptop GPU" },
{ 0x27BB, 0x0000, 0x0000, "NVIDIA RTX 3500 Ada Generation Laptop GPU" },
{ 0x27E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" },
{ 0x2820, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" },
{ 0x2838, 0x0000, 0x0000, "NVIDIA RTX 3000 Ada Generation Laptop GPU" },
{ 0x2860, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" },
{ 0x28A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" },
{ 0x28A1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" },
{ 0x28B8, 0x0000, 0x0000, "NVIDIA RTX 2000 Ada Generation Laptop GPU" },
{ 0x28E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" },
{ 0x28E1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" },
{ 0x13BD, 0x11cc, 0x10DE, "GRID M10-0B" },

13
src/nvidia/generated/g_system_nvoc.h
View File

@@ -7,7 +7,7 @@ extern "C" {
#endif
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -322,6 +322,16 @@ typedef struct SYS_STATIC_CONFIG
NvBool bOsSevEnabled;
} SYS_STATIC_CONFIG;
typedef enum
{
CPU_VENDOR_UNKNOWN = 0,
CPU_VENDOR_INTEL,
CPU_VENDOR_AMD,
CPU_VENDOR_WINCHIP,
CPU_VENDOR_CYRIX,
CPU_VENDOR_TRANSM
} CPU_VENDOR;
typedef struct
{
NvBool bInitialized; // Set to true once we id the CPU
@@ -340,6 +350,7 @@ typedef struct
// filled in if CPU has embedded name
NvU32 family; // Vendor defined Family/extended Family
NvU32 model; // Vendor defined Model/extended Model
NvU8 vendor; // Vendor CPU_VENDOR
NvU32 coresOnDie; // # of cores on the die (0 if unknown)
NvU32 platformID; // Chip package type
NvU8 stepping; // Silicon stepping

2
src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

3
src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c
View File

@@ -2310,7 +2310,6 @@ kgrctxIsFinalGlobalBufMapRefDuped_IMPL
}
return NV_FALSE;
}
/**
* @brief Unmap associated ctx buffers (main, patch, global buffers etc).
*
@@ -3071,7 +3070,6 @@ kgrctxIncObjectCount_IMPL
NV_ASSERT_OK_OR_ELSE(status,
kgrctxGetUnicast(pGpu, pKernelGraphicsContext, &pKernelGraphicsContextUnicast),
return;);
switch (objType)
{
case GR_OBJECT_TYPE_COMPUTE:
@@ -3584,4 +3582,3 @@ void shrkgrctxDetach_IMPL
SLI_LOOP_END;
}
}

15
src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c
View File

@@ -1622,9 +1622,7 @@ dmaUpdateVASpace_GF100
NvU32 alignSize = pMemorySystemConfig->comprPageSize;
KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu);
NvBool bFillPteMem = !!(flags & DMA_UPDATE_VASPACE_FLAGS_FILL_PTE_MEM);
NvBool bUnmap = !bFillPteMem &&
(flags & DMA_UPDATE_VASPACE_FLAGS_UPDATE_VALID) &&
(SF_VAL(_MMU, _PTE_VALID, valid) == NV_MMU_PTE_VALID_FALSE);
NvBool bUnmap;
NvBool bIsIndirectPeer;
VAS_PTE_UPDATE_TYPE update_type;
@@ -1635,6 +1633,17 @@ dmaUpdateVASpace_GF100
readDisable = !!(flags & DMA_UPDATE_VASPACE_FLAGS_SHADER_WRITE_ONLY);
bIsIndirectPeer = !!(flags & DMA_UPDATE_VASPACE_FLAGS_INDIRECT_PEER);
if (pGpu->bEnableBar1SparseForFillPteMemUnmap)
{
bUnmap = (flags & DMA_UPDATE_VASPACE_FLAGS_UPDATE_VALID) &&
(SF_VAL(_MMU, _PTE_VALID, valid) == NV_MMU_PTE_VALID_FALSE);
}
else
{
bUnmap = !bFillPteMem &&
(flags & DMA_UPDATE_VASPACE_FLAGS_UPDATE_VALID) &&
(SF_VAL(_MMU, _PTE_VALID, valid) == NV_MMU_PTE_VALID_FALSE);
}
//
// Determine whether we are invalidating or revoking privileges, so we know
// whether to flush page accesses or not. ReadDisable and writeDisable have

5
src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c
View File

@@ -91,6 +91,7 @@ kgmmuValidateFabricBaseAddress_GA100
OBJGPU *pGpu = ENG_GET_GPU(pKernelGmmu);
MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
NvU64 fbSizeBytes;
NvU64 fbUpperLimit;
fbSizeBytes = pMemoryManager->Ram.fbTotalMemSizeMb << 20;
@@ -109,8 +110,10 @@ kgmmuValidateFabricBaseAddress_GA100
// Align fbSize to mapslot size.
fbSizeBytes = RM_ALIGN_UP(fbSizeBytes, NVBIT64(36));
fbUpperLimit = fabricBaseAddr + fbSizeBytes;
// Make sure the address range doesn't go beyond the limit, (2K * 64GB).
if ((fabricBaseAddr + fbSizeBytes) > NVBIT64(47))
if (fbUpperLimit > NVBIT64(47))
{
return NV_ERR_INVALID_ARGUMENT;
}

2
src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c
View File

@@ -133,7 +133,7 @@ kgmmuInvalidateTlb_GM107
// Not using range-based invalidate.
params.regVal = FLD_SET_DRF(_PFB_PRI, _MMU_INVALIDATE, _ALL_VA, _TRUE, params.regVal);
if (NULL != pRootPageDir)
if ((NULL != pRootPageDir) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_SRIOV_HEAVY_FORCE_INVALIDATE_ALL_PDBS_WAR_BUG3896322))
{
// Invalidatating only one VAS.
params.regVal = FLD_SET_DRF(_PFB_PRI, _MMU_INVALIDATE, _ALL_PDB, _FALSE, params.regVal);

5
src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c
View File

@@ -500,6 +500,7 @@ knvlinkValidateFabricBaseAddress_GV100
{
MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
NvU64 fbSizeBytes;
NvU64 fbUpperLimit;
fbSizeBytes = pMemoryManager->Ram.fbTotalMemSizeMb << 20;
@@ -518,8 +519,10 @@ knvlinkValidateFabricBaseAddress_GV100
// Align fbSize to mapslot size.
fbSizeBytes = RM_ALIGN_UP(fbSizeBytes, NVBIT64(34));
fbUpperLimit = fabricBaseAddr + fbSizeBytes;
// Make sure the address range doesn't go beyond the limit, (8K * 16GB).
if ((fabricBaseAddr + fbSizeBytes) > NVBIT64(47))
if (fbUpperLimit > NVBIT64(47))
{
return NV_ERR_INVALID_ARGUMENT;
}

17
src/nvidia/src/kernel/platform/cpu.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -749,16 +749,31 @@ void RmInitCpuInfo(void)
getEmbeddedProcessorName(pSys->cpuInfo.name, sizeof(pSys->cpuInfo.name));
if (IS_INTEL(cpuinfo.Foundry))
{
cpuidInfoIntel(pSys, &cpuinfo);
pSys->cpuInfo.vendor = CPU_VENDOR_INTEL;
}
else if (IS_AMD(cpuinfo.Foundry))
{
cpuidInfoAMD(pSys, &cpuinfo);
pSys->cpuInfo.vendor = CPU_VENDOR_AMD;
}
#if defined(_M_IX86) || defined(NVCPU_X86)
else if (IS_WINCHIP(cpuinfo.Foundry))
{
cpuidInfoWinChip(pSys, &cpuinfo);
pSys->cpuInfo.vendor = CPU_VENDOR_WINCHIP;
}
else if (IS_CYRIX(cpuinfo.Foundry))
{
cpuidInfoCyrix(pSys, &cpuinfo);
pSys->cpuInfo.vendor = CPU_VENDOR_CYRIX;
}
else if (IS_TRANSM(cpuinfo.Foundry))
{
cpuidInfoTransmeta(pSys, &cpuinfo);
pSys->cpuInfo.vendor = CPU_VENDOR_TRANSM;
}
#endif
else
{

90
src/nvidia/src/libraries/resserv/src/rs_client.c
View File

@@ -591,6 +591,50 @@ clientCopyResource_IMPL
return _clientAllocResourceHelper(pClient, pServer, &params, &pParams->hResourceDst);
}
static
void
_refCleanupDependencies
(
RsResourceRef *pResourceRef
)
{
RsResourceRef **ppIndepRef;
while (NULL != (ppIndepRef = multimapFirstItem(&pResourceRef->depBackRefMap)))
{
refRemoveDependant(*ppIndepRef, pResourceRef);
}
}
static
void
_refCleanupDependants
(
RsResourceRef *pResourceRef
)
{
RsResourceRef **ppDepRef;
while (NULL != (ppDepRef = multimapFirstItem(&pResourceRef->depRefMap)))
{
refRemoveDependant(pResourceRef, *ppDepRef);
}
}
static
void
_refRemoveAllDependencies
(
RsResourceRef *pResourceRef
)
{
_refCleanupDependencies(pResourceRef);
if (pResourceRef->pDependantSession != NULL)
sessionRemoveDependency(pResourceRef->pDependantSession, pResourceRef);
if (pResourceRef->pSession != NULL)
sessionRemoveDependant(pResourceRef->pSession, pResourceRef);
}
static
NV_STATUS
_clientAllocResourceHelper
@@ -693,11 +737,7 @@ fail:
pOldContext = NULL;
// First undo dependency tracking since it might access the resource
if (pResourceRef->pDependantSession != NULL)
sessionRemoveDependency(pResourceRef->pDependantSession, pResourceRef);
if (pResourceRef->pSession != NULL)
sessionRemoveDependant(pResourceRef->pSession, pResourceRef);
_refRemoveAllDependencies(pResourceRef);
portMemSet(&params, 0, sizeof(params));
portMemSet(&callContext, 0, sizeof(callContext));
@@ -727,38 +767,6 @@ fail:
return status;
}
static
NV_STATUS
_refCleanupDependencies
(
RsResourceRef *pResourceRef
)
{
RsResourceRef **ppIndepRef;
while (NULL != (ppIndepRef = multimapFirstItem(&pResourceRef->depBackRefMap)))
{
refRemoveDependant(*ppIndepRef, pResourceRef);
}
return NV_OK;
}
static
NV_STATUS
_refCleanupDependants
(
RsResourceRef *pResourceRef
)
{
RsResourceRef **ppDepRef;
while (NULL != (ppDepRef = multimapFirstItem(&pResourceRef->depRefMap)))
{
refRemoveDependant(pResourceRef, *ppDepRef);
}
return NV_OK;
}
NV_STATUS
clientFreeResource_IMPL
(
@@ -814,13 +822,7 @@ clientFreeResource_IMPL
// Remove this resource as a dependency from other resources
pResourceRef->bInvalidated = NV_TRUE;
_refCleanupDependencies(pResourceRef);
if (pResourceRef->pDependantSession != NULL)
sessionRemoveDependency(pResourceRef->pDependantSession, pResourceRef);
if (pResourceRef->pSession != NULL)
sessionRemoveDependant(pResourceRef->pSession, pResourceRef);
_refRemoveAllDependencies(pResourceRef);
status = serverFreeResourceRpcUnderLock(pServer, pParams);
NV_ASSERT(status == NV_OK);