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550.142

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This commit is contained in:
Bernhard Stoeckner
2024-12-17 16:59:50 +01:00
parent 7a6a5a1f9a
commit a62cb468b2
37 changed files with 755 additions and 564 deletions
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8
README.md
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@@ -1,7 +1,7 @@
# NVIDIA Linux Open GPU Kernel Module Source
This is the source release of the NVIDIA Linux open GPU kernel modules,
version 550.135.
version 550.142.
## How to Build
@@ -17,7 +17,7 @@ as root:
Note that the kernel modules built here must be used with GSP
firmware and user-space NVIDIA GPU driver components from a corresponding
550.135 driver release. This can be achieved by installing
550.142 driver release. This can be achieved by installing
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
option. E.g.,
@@ -188,7 +188,7 @@ encountered specific to them.
For details on feature support and limitations, see the NVIDIA GPU driver
end user README here:
https://us.download.nvidia.com/XFree86/Linux-x86_64/550.135/README/kernel_open.html
https://us.download.nvidia.com/XFree86/Linux-x86_64/550.142/README/kernel_open.html
For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
Package for more details.
@@ -755,7 +755,6 @@ Subsystem Device ID.
| NVIDIA H20 | 2329 10DE 198B |
| NVIDIA H20 | 2329 10DE 198C |
| NVIDIA H20-3e | 232C 10DE 2063 |
| NVIDIA H20-3e | 232C 10DE 2064 |
| NVIDIA H100 80GB HBM3 | 2330 10DE 16C0 |
| NVIDIA H100 80GB HBM3 | 2330 10DE 16C1 |
| NVIDIA H100 PCIe | 2331 10DE 1626 |
@@ -920,6 +919,7 @@ Subsystem Device ID.
| NVIDIA GeForce RTX 4060 | 2882 |
| NVIDIA GeForce RTX 4060 Laptop GPU | 28A0 |
| NVIDIA GeForce RTX 4050 Laptop GPU | 28A1 |
| NVIDIA GeForce RTX 3050 A Laptop GPU | 28A3 |
| NVIDIA RTX 2000 Ada Generation | 28B0 1028 1870 |
| NVIDIA RTX 2000 Ada Generation | 28B0 103C 1870 |
| NVIDIA RTX 2000E Ada Generation | 28B0 103C 1871 |

16
kernel-open/Kbuild
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@@ -57,6 +57,20 @@ ifeq ($(NV_UNDEF_BEHAVIOR_SANITIZER),1)
UBSAN_SANITIZE := y
endif
#
# Command to create a symbolic link, explicitly resolving the symlink target
# to an absolute path to abstract away the difference between Linux < 6.13,
# where the CWD is the Linux kernel source tree for Kbuild extmod builds, and
# Linux >= 6.13, where the CWD is the external module source tree.
#
# This is used to create the nv*-kernel.o -> nv*-kernel.o_binary symlinks for
# kernel modules which use precompiled binary object files.
#
quiet_cmd_symlink = SYMLINK $@
cmd_symlink = ln -sf $(abspath $<) $@
$(foreach _module, $(NV_KERNEL_MODULES), \
$(eval include $(src)/$(_module)/$(_module).Kbuild))
@@ -72,7 +86,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
EXTRA_CFLAGS += -I$(src)
EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"550.135\"
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"550.142\"
ifneq ($(SYSSRCHOST1X),)
EXTRA_CFLAGS += -I$(SYSSRCHOST1X)

3
kernel-open/nvidia-modeset/nvidia-modeset.Kbuild
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@@ -40,9 +40,6 @@ NV_KERNEL_MODULE_TARGETS += $(NVIDIA_MODESET_KO)
NVIDIA_MODESET_BINARY_OBJECT := $(src)/nvidia-modeset/nv-modeset-kernel.o_binary
NVIDIA_MODESET_BINARY_OBJECT_O := nvidia-modeset/nv-modeset-kernel.o
quiet_cmd_symlink = SYMLINK $@
cmd_symlink = ln -sf $< $@
targets += $(NVIDIA_MODESET_BINARY_OBJECT_O)
$(obj)/$(NVIDIA_MODESET_BINARY_OBJECT_O): $(NVIDIA_MODESET_BINARY_OBJECT) FORCE

3
kernel-open/nvidia-uvm/uvm.c
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@@ -682,6 +682,9 @@ static void uvm_vm_open_semaphore_pool(struct vm_area_struct *vma)
// Semaphore pool vmas do not have vma wrappers, but some functions will
// assume vm_private_data is a wrapper.
vma->vm_private_data = NULL;
#if defined(VM_WIPEONFORK)
nv_vm_flags_set(vma, VM_WIPEONFORK);
#endif
if (is_fork) {
// If we forked, leave the parent vma alone.

3
kernel-open/nvidia/nvidia.Kbuild
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@@ -40,9 +40,6 @@ NVIDIA_KO = nvidia/nvidia.ko
NVIDIA_BINARY_OBJECT := $(src)/nvidia/nv-kernel.o_binary
NVIDIA_BINARY_OBJECT_O := nvidia/nv-kernel.o
quiet_cmd_symlink = SYMLINK $@
cmd_symlink = ln -sf $< $@
targets += $(NVIDIA_BINARY_OBJECT_O)
$(obj)/$(NVIDIA_BINARY_OBJECT_O): $(NVIDIA_BINARY_OBJECT) FORCE

16
src/common/inc/nvBldVer.h
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@@ -43,18 +43,18 @@
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r550_00-475"
#define NV_BUILD_CHANGELIST_NUM (35120799)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r550_00-505"
#define NV_BUILD_CHANGELIST_NUM (35247928)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r550/r550_00-475"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35120799)
#define NV_BUILD_NAME "rel/gpu_drv/r550/r550_00-505"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35247928)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r550_00-438"
#define NV_BUILD_CHANGELIST_NUM (35120799)
#define NV_BUILD_BRANCH_VERSION "r550_00-470"
#define NV_BUILD_CHANGELIST_NUM (35247928)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "553.35"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35120799)
#define NV_BUILD_NAME "553.50"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35247928)
#define NV_BUILD_BRANCH_BASE_VERSION R550
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "550.135"
#define NV_VERSION_STRING "550.142"
#else

5
src/common/inc/nvlog_defs.h
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@@ -102,9 +102,10 @@ struct _NVLOG_BUFFER
#define NVLOG_MAX_BUFFERS_v11 16
#define NVLOG_MAX_BUFFERS_v12 256
#define NVLOG_MAX_BUFFERS_v13 3840
#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v12
#define NVLOG_LOGGER_VERSION 12 // v1.2
#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v13
#define NVLOG_LOGGER_VERSION 13 // v1.3
// Due to this file's peculiar location, NvPort may or may not be includable
typedef struct PORT_SPINLOCK PORT_SPINLOCK;

4
src/common/nvswitch/kernel/smbpbi_nvswitch.c
View File

@@ -89,10 +89,10 @@ nvswitch_smbpbi_post_init
if (status == NVL_SUCCESS)
{
#if defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS)
#if defined(DEBUG) || defined(DEVELOP)
nvswitch_lib_smbpbi_log_sxid(device, NVSWITCH_ERR_NO_ERROR,
"NVSWITCH SMBPBI server is online.");
#endif // defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS)
#endif // defined(DEBUG) || defined(DEVELOP)
NVSWITCH_PRINT(device, INFO, "%s: SMBPBI POST INIT completed\n", __FUNCTION__);
}

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h
View File

@@ -256,7 +256,7 @@ typedef struct NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS {
#define NV0000_CTRL_NVD_SIGNATURE_SIZE (4)
/* Maximum number of buffers */
#define NV0000_CTRL_NVD_MAX_BUFFERS (256)
#define NV0000_CTRL_NVD_MAX_BUFFERS (3840)
#define NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID (0x4U)

14
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h
View File

@@ -114,4 +114,16 @@ typedef struct NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PAR
NvHandle clientHandles[NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS];
} NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS;
/* ctrl0080internal_h */
#define NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U)
typedef struct NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS {
NvBool bTeardown;
} NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS;
#define NV0080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x802046) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U)
typedef NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS;

13
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
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@@ -863,19 +863,6 @@ typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U)
typedef struct NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS {
NvBool bTeardown;
} NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U)
typedef NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS;
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
NvBool bPerSubCtxheaderSupported;
} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;

2
src/common/uproc/os/common/include/liblogdecode.h
View File

@@ -42,7 +42,7 @@ extern "C" {
# define LIBOS_LOG_DECODE_ENABLE 1
# define LIBOS_LOG_TO_NVLOG 0
# define LIBOS_LOG_MAX_LOGS 160 // Max logs for all GPUs for offline decoder
# define LIBOS_LOG_MAX_LOGS 3840 // Max logs for all GPUs for offline decoder
#else
# error "Need to define either NVRM or LIBOS_LOG_OFFLINE_DECODER."

5
src/nvidia/arch/nvalloc/common/inc/nvcst.h
View File

@@ -66,6 +66,7 @@ CHIPSET_SETUP_FUNC(Intel_4381_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A04_setupFunc)
CHIPSET_SETUP_FUNC(Intel_5795_setupFunc)
CHIPSET_SETUP_FUNC(Intel_1B81_setupFunc)
CHIPSET_SETUP_FUNC(SiS_656_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RS400_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RS480_setupFunc)
@@ -189,8 +190,8 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_INTEL, 0x4385, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL},
{PCI_VENDOR_ID_INTEL, 0x7A8A, CS_INTEL_1B81, "Intel-SapphireRapids", NULL},
{PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", Intel_1B81_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A8A, CS_INTEL_1B81, "Intel-SapphireRapids", Intel_1B81_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", NULL},
{PCI_VENDOR_ID_INTEL, 0x7A04, CS_INTEL_7A04, "Intel-RaptorLake", Intel_7A04_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x5795, CS_INTEL_5795, "Intel-GraniteRapids", Intel_5795_setupFunc},

27
src/nvidia/arch/nvalloc/common/inc/nvpcie.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2000-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -211,18 +211,21 @@
// to any specific hardware.
//
//
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0 0x000000C8
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_ID 7:0
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_NEXT 15:8
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_LENGTH 23:16
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_SIG_LO 31:24
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1 0x000000CC
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_SIG_HI 15:0
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_VERSION 18:16
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_PEER_CLIQUE_ID 22:19
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RSVD 31:23
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0 0x000000C8
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_ID 7:0
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_NEXT 15:8
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_LENGTH 23:16
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_SIG_LO 31:24
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1 0x000000CC
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_SIG_HI 15:0
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_VERSION 18:16
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_PEER_CLIQUE_ID 22:19
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING 23:23
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING_DEFAULT 0x00000000
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING_DISABLE 0x00000001
#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RSVD 31:24
#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250
#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250
// Chipset-specific definitions.
// Intel SantaRosa definitions

21
src/nvidia/generated/g_device_nvoc.c
View File

@@ -1142,6 +1142,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
/*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "deviceCtrlCmdInternalPerfCudaLimitSetControl"
#endif
},
{ /* [63] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) deviceCtrlCmdKGrInternalInitBug4208224War_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u)
/*flags=*/ 0xe40u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x802046u,
/*paramSize=*/ sizeof(NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "deviceCtrlCmdKGrInternalInitBug4208224War"
#endif
},
@@ -1149,7 +1164,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
const struct NVOC_EXPORT_INFO __nvoc_export_info_Device =
{
/*numEntries=*/ 63,
/*numEntries=*/ 64,
/*pExportEntries=*/ __nvoc_exported_method_def_Device
};
@@ -1298,6 +1313,10 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis, RmHalspecOwner *pRmhal
pThis->__deviceCtrlCmdKGrSetTpcPartitionMode__ = &deviceCtrlCmdKGrSetTpcPartitionMode_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u)
pThis->__deviceCtrlCmdKGrInternalInitBug4208224War__ = &deviceCtrlCmdKGrInternalInitBug4208224War_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u)
pThis->__deviceCtrlCmdFbGetCompbitStoreInfo__ = &deviceCtrlCmdFbGetCompbitStoreInfo_IMPL;
#endif

8
src/nvidia/generated/g_device_nvoc.h
View File

@@ -112,6 +112,7 @@ struct Device {
NV_STATUS (*__deviceCtrlCmdKGrGetInfoV2__)(struct Device *, NV0080_CTRL_GR_GET_INFO_V2_PARAMS *);
NV_STATUS (*__deviceCtrlCmdKGrGetTpcPartitionMode__)(struct Device *, NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *);
NV_STATUS (*__deviceCtrlCmdKGrSetTpcPartitionMode__)(struct Device *, NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *);
NV_STATUS (*__deviceCtrlCmdKGrInternalInitBug4208224War__)(struct Device *, NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS *);
NV_STATUS (*__deviceCtrlCmdFbGetCompbitStoreInfo__)(struct Device *, NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS *);
NV_STATUS (*__deviceCtrlCmdFbGetCaps__)(struct Device *, NV0080_CTRL_FB_GET_CAPS_PARAMS *);
NV_STATUS (*__deviceCtrlCmdFbGetCapsV2__)(struct Device *, NV0080_CTRL_FB_GET_CAPS_V2_PARAMS *);
@@ -250,6 +251,7 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT
#define deviceCtrlCmdKGrGetInfoV2(pDevice, pParams) deviceCtrlCmdKGrGetInfoV2_DISPATCH(pDevice, pParams)
#define deviceCtrlCmdKGrGetTpcPartitionMode(pDevice, pParams) deviceCtrlCmdKGrGetTpcPartitionMode_DISPATCH(pDevice, pParams)
#define deviceCtrlCmdKGrSetTpcPartitionMode(pDevice, pParams) deviceCtrlCmdKGrSetTpcPartitionMode_DISPATCH(pDevice, pParams)
#define deviceCtrlCmdKGrInternalInitBug4208224War(pDevice, pParams) deviceCtrlCmdKGrInternalInitBug4208224War_DISPATCH(pDevice, pParams)
#define deviceCtrlCmdFbGetCompbitStoreInfo(pDevice, pCompbitStoreParams) deviceCtrlCmdFbGetCompbitStoreInfo_DISPATCH(pDevice, pCompbitStoreParams)
#define deviceCtrlCmdFbGetCaps(pDevice, pFbCapsParams) deviceCtrlCmdFbGetCaps_DISPATCH(pDevice, pFbCapsParams)
#define deviceCtrlCmdFbGetCapsV2(pDevice, pFbCapsParams) deviceCtrlCmdFbGetCapsV2_DISPATCH(pDevice, pFbCapsParams)
@@ -470,6 +472,12 @@ static inline NV_STATUS deviceCtrlCmdKGrSetTpcPartitionMode_DISPATCH(struct Devi
return pDevice->__deviceCtrlCmdKGrSetTpcPartitionMode__(pDevice, pParams);
}
NV_STATUS deviceCtrlCmdKGrInternalInitBug4208224War_IMPL(struct Device *pDevice, NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS *pParams);
static inline NV_STATUS deviceCtrlCmdKGrInternalInitBug4208224War_DISPATCH(struct Device *pDevice, NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS *pParams) {
return pDevice->__deviceCtrlCmdKGrInternalInitBug4208224War__(pDevice, pParams);
}
NV_STATUS deviceCtrlCmdFbGetCompbitStoreInfo_IMPL(struct Device *pDevice, NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS *pCompbitStoreParams);
static inline NV_STATUS deviceCtrlCmdFbGetCompbitStoreInfo_DISPATCH(struct Device *pDevice, NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS *pCompbitStoreParams) {

15
src/nvidia/generated/g_intr_nvoc.h
View File

@@ -7,7 +7,7 @@ extern "C" {
#endif
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -149,6 +149,11 @@ interruptEntryIsEmpty(const InterruptEntry *pEntry)
// Default value for intrStuckThreshold
#define INTR_STUCK_THRESHOLD 1000
// Minimum length of interrupt to log as long-running
#define LONG_INTR_LOG_LENGTH_NS (1000000LLU) // 1ms
// Maximum frequency of long-running interrupt print, per engine
#define LONG_INTR_LOG_RATELIMIT_NS (10000000000LLU) // 10s
#define INTR_TABLE_INIT_KERNEL (1 << 0)
#define INTR_TABLE_INIT_PHYSICAL (1 << 1)
@@ -265,6 +270,13 @@ typedef struct Device Device;
#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x)
#endif
struct __nvoc_inner_struc_Intr_1__ {
NvU32 intrCount;
NvU64 intrLength;
NvU64 lastPrintTime;
};
struct Intr {
const struct NVOC_RTTI *__nvoc_rtti;
struct OBJENGSTATE __nvoc_base_OBJENGSTATE;
@@ -338,6 +350,7 @@ struct Intr {
NvU32 intrEn0Orig;
NvBool halIntrEnabled;
NvU32 saveIntrEn0;
struct __nvoc_inner_struc_Intr_1__ longIntrStats[171];
};
#ifndef __NVOC_CLASS_Intr_TYPEDEF__

18
src/nvidia/generated/g_kernel_graphics_nvoc.c
View File

@@ -301,6 +301,24 @@ static void __nvoc_init_funcTable_KernelGraphics_1(KernelGraphics *pThis, RmHals
pThis->__kgraphicsServiceNotificationInterrupt__ = &kgraphicsServiceNotificationInterrupt_IMPL;
// Hal function -- kgraphicsTeardownBug4208224State
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
{
pThis->__kgraphicsTeardownBug4208224State__ = &kgraphicsTeardownBug4208224State_b3696a;
}
else
{
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */
{
pThis->__kgraphicsTeardownBug4208224State__ = &kgraphicsTeardownBug4208224State_TU102;
}
// default
else
{
pThis->__kgraphicsTeardownBug4208224State__ = &kgraphicsTeardownBug4208224State_b3696a;
}
}
// Hal function -- kgraphicsCreateBug4208224Channel
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */
{

14
src/nvidia/generated/g_kernel_graphics_nvoc.h
View File

@@ -193,6 +193,7 @@ struct KernelGraphics {
NV_STATUS (*__kgraphicsStatePostLoad__)(OBJGPU *, struct KernelGraphics *, NvU32);
void (*__kgraphicsRegisterIntrService__)(OBJGPU *, struct KernelGraphics *, IntrServiceRecord *);
NV_STATUS (*__kgraphicsServiceNotificationInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceNotificationInterruptArguments *);
void (*__kgraphicsTeardownBug4208224State__)(OBJGPU *, struct KernelGraphics *);
NV_STATUS (*__kgraphicsCreateBug4208224Channel__)(OBJGPU *, struct KernelGraphics *);
NV_STATUS (*__kgraphicsInitializeBug4208224WAR__)(OBJGPU *, struct KernelGraphics *);
NvBool (*__kgraphicsIsBug4208224WARNeeded__)(OBJGPU *, struct KernelGraphics *);
@@ -251,6 +252,7 @@ struct KernelGraphics_PRIVATE {
NV_STATUS (*__kgraphicsStatePostLoad__)(OBJGPU *, struct KernelGraphics *, NvU32);
void (*__kgraphicsRegisterIntrService__)(OBJGPU *, struct KernelGraphics *, IntrServiceRecord *);
NV_STATUS (*__kgraphicsServiceNotificationInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceNotificationInterruptArguments *);
void (*__kgraphicsTeardownBug4208224State__)(OBJGPU *, struct KernelGraphics *);
NV_STATUS (*__kgraphicsCreateBug4208224Channel__)(OBJGPU *, struct KernelGraphics *);
NV_STATUS (*__kgraphicsInitializeBug4208224WAR__)(OBJGPU *, struct KernelGraphics *);
NvBool (*__kgraphicsIsBug4208224WARNeeded__)(OBJGPU *, struct KernelGraphics *);
@@ -331,6 +333,8 @@ NV_STATUS __nvoc_objCreate_KernelGraphics(KernelGraphics**, Dynamic*, NvU32);
#define kgraphicsStatePostLoad(arg0, arg1, flags) kgraphicsStatePostLoad_DISPATCH(arg0, arg1, flags)
#define kgraphicsRegisterIntrService(arg0, arg1, arg2) kgraphicsRegisterIntrService_DISPATCH(arg0, arg1, arg2)
#define kgraphicsServiceNotificationInterrupt(arg0, arg1, arg2) kgraphicsServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2)
#define kgraphicsTeardownBug4208224State(arg0, arg1) kgraphicsTeardownBug4208224State_DISPATCH(arg0, arg1)
#define kgraphicsTeardownBug4208224State_HAL(arg0, arg1) kgraphicsTeardownBug4208224State_DISPATCH(arg0, arg1)
#define kgraphicsCreateBug4208224Channel(arg0, arg1) kgraphicsCreateBug4208224Channel_DISPATCH(arg0, arg1)
#define kgraphicsCreateBug4208224Channel_HAL(arg0, arg1) kgraphicsCreateBug4208224Channel_DISPATCH(arg0, arg1)
#define kgraphicsInitializeBug4208224WAR(arg0, arg1) kgraphicsInitializeBug4208224WAR_DISPATCH(arg0, arg1)
@@ -505,6 +509,16 @@ static inline NV_STATUS kgraphicsServiceNotificationInterrupt_DISPATCH(OBJGPU *a
return arg1->__kgraphicsServiceNotificationInterrupt__(arg0, arg1, arg2);
}
static inline void kgraphicsTeardownBug4208224State_b3696a(OBJGPU *arg0, struct KernelGraphics *arg1) {
return;
}
void kgraphicsTeardownBug4208224State_TU102(OBJGPU *arg0, struct KernelGraphics *arg1);
static inline void kgraphicsTeardownBug4208224State_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1) {
arg1->__kgraphicsTeardownBug4208224State__(arg0, arg1);
}
NV_STATUS kgraphicsCreateBug4208224Channel_TU102(OBJGPU *arg0, struct KernelGraphics *arg1);
static inline NV_STATUS kgraphicsCreateBug4208224Channel_56cd7a(OBJGPU *arg0, struct KernelGraphics *arg1) {

2
src/nvidia/generated/g_nv_name_released.h
View File

@@ -902,7 +902,6 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2329, 0x198b, 0x10de, "NVIDIA H20" },
{ 0x2329, 0x198c, 0x10de, "NVIDIA H20" },
{ 0x232C, 0x2063, 0x10de, "NVIDIA H20-3e" },
{ 0x232C, 0x2064, 0x10de, "NVIDIA H20-3e" },
{ 0x2330, 0x16c0, 0x10de, "NVIDIA H100 80GB HBM3" },
{ 0x2330, 0x16c1, 0x10de, "NVIDIA H100 80GB HBM3" },
{ 0x2331, 0x1626, 0x10de, "NVIDIA H100 PCIe" },
@@ -1067,6 +1066,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2882, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060" },
{ 0x28A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" },
{ 0x28A1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" },
{ 0x28A3, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 A Laptop GPU" },
{ 0x28B0, 0x1870, 0x1028, "NVIDIA RTX 2000 Ada Generation" },
{ 0x28B0, 0x1870, 0x103c, "NVIDIA RTX 2000 Ada Generation" },
{ 0x28B0, 0x1871, 0x103c, "NVIDIA RTX 2000E Ada Generation" },

17
src/nvidia/generated/g_rs_resource_nvoc.h
View File

@@ -81,15 +81,16 @@ typedef struct RsSession RsSession;
*/
struct RS_LOCK_INFO
{
struct RsClient *pClient; ///< Pointer to client that was locked (if any)
struct RsClient *pSecondClient; ///< Pointer to second client, for dual-client locking
RsResourceRef *pContextRef; ///< User-defined reference
struct RsSession *pSession; ///< Session object to be locked, if any
NvU32 flags; ///< RS_LOCK_FLAGS_*
NvU32 state; ///< RS_LOCK_STATE_*
struct RsClient *pClient; ///< Pointer to client that was locked (if any)
struct RsClient *pSecondClient; ///< Pointer to second client, for dual-client locking
RsResourceRef *pContextRef; ///< User-defined reference
RsResourceRef *pResRefToBackRef; ///< Resource from which to infer indirect GPU dependencies
struct RsSession *pSession; ///< Session object to be locked, if any
NvU32 flags; ///< RS_LOCK_FLAGS_*
NvU32 state; ///< RS_LOCK_STATE_*
NvU32 gpuMask;
NvU8 traceOp; ///< RS_LOCK_TRACE_* operation for lock-metering
NvU32 traceClassId; ///< Class of initial resource that was locked for lock metering
NvU8 traceOp; ///< RS_LOCK_TRACE_* operation for lock-metering
NvU32 traceClassId; ///< Class of initial resource that was locked for lock metering
};
struct RS_RES_ALLOC_PARAMS_INTERNAL

829
src/nvidia/generated/g_subdevice_nvoc.c
View File

File diff suppressed because it is too large Load Diff

8
src/nvidia/generated/g_subdevice_nvoc.h
View File

@@ -370,7 +370,6 @@ struct Subdevice {
NV_STATUS (*__subdeviceCtrlCmdGrInternalGetFecsTraceRdOffset__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdGrInternalSetFecsTraceWrOffset__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdGrStaticGetFecsTraceDefines__)(struct Subdevice *, NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdKGrInternalInitBug4208224War__)(struct Subdevice *, NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdGpuGetCachedInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdGpuGetInfoV2__)(struct Subdevice *, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdGpuGetIpVersion__)(struct Subdevice *, NV2080_CTRL_GPU_GET_IP_VERSION_PARAMS *);
@@ -1020,7 +1019,6 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C
#define subdeviceCtrlCmdGrInternalGetFecsTraceRdOffset(pSubdevice, pParams) subdeviceCtrlCmdGrInternalGetFecsTraceRdOffset_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdGrInternalSetFecsTraceWrOffset(pSubdevice, pParams) subdeviceCtrlCmdGrInternalSetFecsTraceWrOffset_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdGrStaticGetFecsTraceDefines(pSubdevice, pParams) subdeviceCtrlCmdGrStaticGetFecsTraceDefines_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdKGrInternalInitBug4208224War(pSubdevice, pParams) subdeviceCtrlCmdKGrInternalInitBug4208224War_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdGpuGetCachedInfo(pSubdevice, pGpuInfoParams) subdeviceCtrlCmdGpuGetCachedInfo_DISPATCH(pSubdevice, pGpuInfoParams)
#define subdeviceCtrlCmdGpuGetInfoV2(pSubdevice, pGpuInfoParams) subdeviceCtrlCmdGpuGetInfoV2_DISPATCH(pSubdevice, pGpuInfoParams)
#define subdeviceCtrlCmdGpuGetIpVersion(pSubdevice, pGpuIpVersionParams) subdeviceCtrlCmdGpuGetIpVersion_DISPATCH(pSubdevice, pGpuIpVersionParams)
@@ -2928,12 +2926,6 @@ static inline NV_STATUS subdeviceCtrlCmdGrStaticGetFecsTraceDefines_DISPATCH(str
return pSubdevice->__subdeviceCtrlCmdGrStaticGetFecsTraceDefines__(pSubdevice, pParams);
}
NV_STATUS subdeviceCtrlCmdKGrInternalInitBug4208224War_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS *pParams);
static inline NV_STATUS subdeviceCtrlCmdKGrInternalInitBug4208224War_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS *pParams) {
return pSubdevice->__subdeviceCtrlCmdKGrInternalInitBug4208224War__(pSubdevice, pParams);
}
NV_STATUS subdeviceCtrlCmdGpuGetCachedInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pGpuInfoParams);
static inline NV_STATUS subdeviceCtrlCmdGpuGetCachedInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pGpuInfoParams) {

17
src/nvidia/inc/libraries/resserv/rs_resource.h
View File

@@ -62,15 +62,16 @@ class RsSession;
*/
struct RS_LOCK_INFO
{
RsClient *pClient; ///< Pointer to client that was locked (if any)
RsClient *pSecondClient; ///< Pointer to second client, for dual-client locking
RsResourceRef *pContextRef; ///< User-defined reference
RsSession *pSession; ///< Session object to be locked, if any
NvU32 flags; ///< RS_LOCK_FLAGS_*
NvU32 state; ///< RS_LOCK_STATE_*
RsClient *pClient; ///< Pointer to client that was locked (if any)
RsClient *pSecondClient; ///< Pointer to second client, for dual-client locking
RsResourceRef *pContextRef; ///< User-defined reference
RsResourceRef *pResRefToBackRef; ///< Resource from which to infer indirect GPU dependencies
RsSession *pSession; ///< Session object to be locked, if any
NvU32 flags; ///< RS_LOCK_FLAGS_*
NvU32 state; ///< RS_LOCK_STATE_*
NvU32 gpuMask;
NvU8 traceOp; ///< RS_LOCK_TRACE_* operation for lock-metering
NvU32 traceClassId; ///< Class of initial resource that was locked for lock metering
NvU8 traceOp; ///< RS_LOCK_TRACE_* operation for lock-metering
NvU32 traceClassId; ///< Class of initial resource that was locked for lock metering
};
struct RS_RES_ALLOC_PARAMS_INTERNAL

5
src/nvidia/kernel/vgpu/nv/objvgpu.c
View File

@@ -142,6 +142,11 @@ vgpuDestructObject
OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu);
NV_STATUS rmStatus = NV_OK;
// TODO This can be called with a NULL OBJVGPU object via _gpumgrCreateGpu
// when trying to init on a CC GPU that has previously been unloaded.
// Bug 4922744
NV_ASSERT_OR_RETURN_VOID(pVGpu != NULL);
NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, rmStatus, NV_FALSE, NV_FALSE, 0);
{

9
src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c
View File

@@ -26,7 +26,6 @@
#include "os/os.h"
#include "nverror.h"
#include "vgpu/rpc.h"
#include "nvrm_registry.h"
#include "published/hopper/gh100/hwproject.h"
#include "published/hopper/gh100/dev_gc6_island.h"
@@ -494,14 +493,6 @@ gpuIsProtectedPcieEnabledInHw_GH100
OBJGPU *pGpu
)
{
NvU32 data;
if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_PPCIE_ENABLED, &data) == NV_OK) &&
(data == NV_REG_STR_RM_PPCIE_ENABLED_YES))
{
return NV_TRUE;
}
return NV_FALSE;
}

71
src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c
View File

@@ -180,6 +180,51 @@ kgraphicsAllocGrGlobalCtxBuffers_TU102
return status;
}
/*!
* @brief Teardown bug 4208224 client and memory
*/
void
kgraphicsTeardownBug4208224State_TU102
(
OBJGPU *pGpu,
KernelGraphics *pKernelGraphics
)
{
NV_ASSERT_OR_RETURN_VOID(gpumgrIsParentGPU(pGpu));
if (pKernelGraphics->bug4208224Info.bConstructed && !IS_VIRTUAL(pGpu) && gpumgrIsParentGPU(pGpu))
{
RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS params = {0};
NvBool bBcStatus;
NvU32 sliLoopReentrancy;
//
// Forcing BC state to enabled here is most likely superfluous
// as the rmapi control stack should detect a call with a device
// handle and automatically enable BC mode. This is force is left
// as a code-maintence reminder, that if linked-SLI is being used,
// we MUST perform this as a broadcast call.
//
bBcStatus = gpumgrGetBcEnabledStatus(pGpu);
gpumgrSetBcEnabledStatus(pGpu, NV_TRUE);
sliLoopReentrancy = gpumgrSLILoopReentrancyPop(pGpu);
params.bTeardown = NV_TRUE;
NV_ASSERT_OK(pRmApi->Control(pRmApi,
pKernelGraphics->bug4208224Info.hClient,
pKernelGraphics->bug4208224Info.hDeviceId,
NV0080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR,
&params,
sizeof(params)));
NV_ASSERT_OK(pRmApi->Free(pRmApi, pKernelGraphics->bug4208224Info.hClient, pKernelGraphics->bug4208224Info.hClient));
gpumgrSLILoopReentrancyPush(pGpu, sliLoopReentrancy);
gpumgrSetBcEnabledStatus(pGpu, bBcStatus);
pKernelGraphics->bug4208224Info.bConstructed = NV_FALSE;
}
}
/**
* @brief Initializes Bug 4208224 by performing the following actions
* 1.) Sets up static handles inside an info struct to be referenced later
@@ -195,9 +240,11 @@ kgraphicsInitializeBug4208224WAR_TU102
{
NV_STATUS status = NV_OK;
RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS params = {0};
NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS params = {0};
NvBool bBcStatus;
NvU32 sliLoopReentrancy;
if (pKernelGraphics->bug4208224Info.bConstructed)
if ((pKernelGraphics->bug4208224Info.bConstructed) || !gpumgrIsParentGPU(pGpu))
{
return NV_OK;
}
@@ -205,11 +252,23 @@ kgraphicsInitializeBug4208224WAR_TU102
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
kgraphicsCreateBug4208224Channel_HAL(pGpu, pKernelGraphics));
//
// Forcing BC state to enabled here is most likely superfluous
// as the rmapi control stack should detect a call with a device
// handle and automatically enable BC mode. This is force is left
// as a code-maintence reminder, that if linked-SLI is being used,
// we MUST perform this as a broadcast call.
//
bBcStatus = gpumgrGetBcEnabledStatus(pGpu);
gpumgrSetBcEnabledStatus(pGpu, NV_TRUE);
// As we have forced here SLI broadcast mode, temporarily reset the reentrancy count
sliLoopReentrancy = gpumgrSLILoopReentrancyPop(pGpu);
params.bTeardown = NV_FALSE;
status = pRmApi->Control(pRmApi,
pKernelGraphics->bug4208224Info.hClient,
pKernelGraphics->bug4208224Info.hSubdeviceId,
NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR,
pKernelGraphics->bug4208224Info.hDeviceId,
NV0080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR,
&params,
sizeof(params));
@@ -220,6 +279,10 @@ kgraphicsInitializeBug4208224WAR_TU102
pKernelGraphics->bug4208224Info.hClient));
}
// Restore the reentrancy count
gpumgrSLILoopReentrancyPush(pGpu, sliLoopReentrancy);
gpumgrSetBcEnabledStatus(pGpu, bBcStatus);
return status;
}

16
src/nvidia/src/kernel/gpu/gr/kernel_graphics.c
View File

@@ -381,21 +381,7 @@ kgraphicsStatePreUnload_IMPL
NvU32 flags
)
{
if (pKernelGraphics->bug4208224Info.bConstructed)
{
RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS params = {0};
params.bTeardown = NV_TRUE;
NV_ASSERT_OK(pRmApi->Control(pRmApi,
pKernelGraphics->bug4208224Info.hClient,
pKernelGraphics->bug4208224Info.hSubdeviceId,
NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR,
&params,
sizeof(params)));
NV_ASSERT_OK(pRmApi->Free(pRmApi, pKernelGraphics->bug4208224Info.hClient, pKernelGraphics->bug4208224Info.hClient));
pKernelGraphics->bug4208224Info.bConstructed = NV_FALSE;
}
kgraphicsTeardownBug4208224State_HAL(pGpu, pKernelGraphics);
fecsBufferUnmap(pGpu, pKernelGraphics);

27
src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c
View File

@@ -2948,33 +2948,12 @@ _kgspShouldRelaxGspInitLocking
relaxGspInitLockingReg = NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_DEFAULT;
}
// Due to bug 4399629, restrict which platforms have parallel init enabled by default
if (relaxGspInitLockingReg == NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_DEFAULT)
if ((relaxGspInitLockingReg == NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_DEFAULT) ||
(relaxGspInitLockingReg == NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_ENABLE))
{
NvU16 devId = (NvU16)(((pGpu->idInfo.PCIDeviceID) >> 16) & 0x0000FFFF);
NvU32 i;
static const NvU16 defaultRelaxGspInitLockingGpus[] = {
0x1EB8, // T4
0x1EB9, // T4
};
if (IsHOPPER(pGpu) || IsADA(pGpu))
{
return NV_TRUE;
}
for (i = 0; i < NV_ARRAY_ELEMENTS(defaultRelaxGspInitLockingGpus); i++)
{
if (devId == defaultRelaxGspInitLockingGpus[i])
{
return NV_TRUE;
}
}
return NV_FALSE;
return NV_TRUE;
}
return (relaxGspInitLockingReg == NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_ENABLE);
return NV_FALSE;
}

43
src/nvidia/src/kernel/gpu/intr/intr.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -57,6 +57,7 @@ static struct
} stuckIntr[MC_ENGINE_IDX_MAX];
static NvBool _intrServiceStallExactList(OBJGPU *pGpu, Intr *pIntr, MC_ENGINE_BITVECTOR *pEngines);
static void _intrLogLongRunningInterrupts(Intr *pIntr);
static void _intrInitServiceTable(OBJGPU *pGpu, Intr *pIntr);
@@ -143,6 +144,8 @@ intrServiceStall_IMPL(OBJGPU *pGpu, Intr *pIntr)
intrProcessDPCQueue_HAL(pGpu, pIntr);
}
_intrLogLongRunningInterrupts(pIntr);
exit:
return;
}
@@ -1100,6 +1103,7 @@ NvU32 intrServiceInterruptRecords_IMPL
IntrService *pIntrService = pIntr->intrServiceTable[engineIdx].pInterruptService;
NvU32 ret = 0;
NvBool bShouldService;
NvU64 intrTiming, intrTiming2;
IntrServiceClearInterruptArguments clearParams = {engineIdx};
IntrServiceServiceInterruptArguments serviceParams = {engineIdx};
@@ -1121,10 +1125,21 @@ NvU32 intrServiceInterruptRecords_IMPL
if (bShouldService)
{
osGetPerformanceCounter(&intrTiming);
GSP_TRACE_RATS_ADD_RECORD(NV_RATS_GSP_TRACE_TYPE_INTR_INFO, pGpu, (NvU32) engineIdx);
GSP_TRACE_RATS_ADD_RECORD(NV_RATS_GSP_TRACE_TYPE_INTR_START, pGpu, 0);
ret = intrservServiceInterrupt(pGpu, pIntrService, &serviceParams);
GSP_TRACE_RATS_ADD_RECORD(NV_RATS_GSP_TRACE_TYPE_INTR_END, pGpu, 0);
osGetPerformanceCounter(&intrTiming2);
intrTiming = intrTiming2 - intrTiming;
if (intrTiming > LONG_INTR_LOG_LENGTH_NS)
{
pIntr->longIntrStats[engineIdx].intrCount++;
if (intrTiming > pIntr->longIntrStats[engineIdx].intrLength)
pIntr->longIntrStats[engineIdx].intrLength = intrTiming;
}
}
return ret;
}
@@ -1449,6 +1464,29 @@ _intrExitCriticalSection
}
}
static void
_intrLogLongRunningInterrupts(Intr *pIntr)
{
NvU64 now;
osGetPerformanceCounter(&now);
for (NvU32 i = 0; i < MC_ENGINE_IDX_MAX; ++i)
{
if (pIntr->longIntrStats[i].intrCount > 0)
{
if (now - pIntr->longIntrStats[i].lastPrintTime > LONG_INTR_LOG_RATELIMIT_NS)
{
NV_PRINTF(LEVEL_WARNING, "%u long-running interrupts (%llu ns or slower) from engine %u, longest taking %llu ns\n",
pIntr->longIntrStats[i].intrCount, LONG_INTR_LOG_LENGTH_NS, i, pIntr->longIntrStats[i].intrLength);
pIntr->longIntrStats[i].intrCount = 0;
pIntr->longIntrStats[i].intrLength = 0;
pIntr->longIntrStats[i].lastPrintTime = now;
}
}
}
}
static NvBool
_intrServiceStallExactList
(
@@ -1631,6 +1669,9 @@ done:
// allow the isr to come in.
_intrExitCriticalSection(pGpu, pIntr, &intrMaskCtx);
// Delay prints until after exiting critical sections to save perf impact
_intrLogLongRunningInterrupts(pIntr);
NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext));
}

1
src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c
View File

@@ -47,6 +47,7 @@
#include "gpu_mgr/gpu_group.h"
#include "kernel/gpu/nvlink/kernel_nvlink.h"
#include "kernel/gpu/rc/kernel_rc.h"
#include "kernel/gpu/gr/kernel_graphics.h"
#include "nvRmReg.h"

11
src/nvidia/src/kernel/platform/chipset/chipset_info.c
View File

@@ -905,6 +905,17 @@ Intel_5795_setupFunc
return NV_OK;
}
static NV_STATUS
Intel_1B81_setupFunc
(
OBJCL *pCl
)
{
pCl->setProperty(pCl, PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE, NV_TRUE);
return NV_OK;
}
static NV_STATUS
Nvidia_T210_setupFunc

20
src/nvidia/src/kernel/platform/chipset/chipset_pcie.c
View File

@@ -71,7 +71,7 @@ static void objClGpuUnmapRootPort(OBJGPU *);
static void objClGpuMapEnhCfgSpace(OBJGPU *, OBJCL *);
static void objClGpuUnmapEnhCfgSpace(OBJGPU *);
static NV_STATUS objClGpuIs3DController(OBJGPU *);
static void objClLoadPcieVirtualP2PApproval(OBJGPU *);
static void objClLoadPcieVirtualP2PApproval(OBJGPU *, OBJCL *);
static void _objClAdjustTcVcMap(OBJGPU *, OBJCL *, PORTDATA *);
static void _objClGetDownstreamAtomicsEnabledMask(void *, NvU32, NvU32 *);
static void _objClGetUpstreamAtomicRoutingCap(void *, NvU32, NvBool *);
@@ -949,7 +949,7 @@ clUpdatePcieConfig_IMPL(OBJGPU *pGpu, OBJCL *pCl)
}
// Load PCI Express virtual P2P approval config
objClLoadPcieVirtualP2PApproval(pGpu);
objClLoadPcieVirtualP2PApproval(pGpu, pCl);
//
// Disable NOSNOOP bit for Passthrough.
@@ -4256,12 +4256,13 @@ clFreePcieConfigSpaceBase_IMPL(OBJCL *pCl)
// other.
//
static void
objClLoadPcieVirtualP2PApproval(OBJGPU *pGpu)
objClLoadPcieVirtualP2PApproval(OBJGPU *pGpu, OBJCL *pCl)
{
void *handle;
NvU32 data32;
NvU8 version;
NvU8 cap;
NvU8 rlxdOrderingCfg = 0;
NvU8 bus = gpuGetBus(pGpu);
NvU8 device = gpuGetDevice(pGpu);
NvU32 domain = gpuGetDomain(pGpu);
@@ -4321,6 +4322,19 @@ objClLoadPcieVirtualP2PApproval(OBJGPU *pGpu)
_PEER_CLIQUE_ID, data32);
pGpu->pciePeerClique.bValid = NV_TRUE;
rlxdOrderingCfg = (NvU8)DRF_VAL(_PCI, _VIRTUAL_P2P_APPROVAL_CAP_1,
_RELAXED_ORDERING, data32);
if (rlxdOrderingCfg == NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING_DISABLE)
{
// Unset relaxed ordering based on hypervisor's request
pCl->setProperty(pCl, PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE, NV_TRUE);
NV_PRINTF(LEVEL_INFO,
"Hypervisor has disabled relaxed ordering on GPU%u\n",
gpuGetInstance(pGpu));
}
NV_PRINTF(LEVEL_INFO,
"Hypervisor has assigned GPU%u to peer clique %u\n",
gpuGetInstance(pGpu), pGpu->pciePeerClique.id);

41
src/nvidia/src/kernel/rmapi/alloc_free.c
View File

@@ -293,6 +293,36 @@ serverTopLock_Epilogue
}
}
static NvU32
_resGetBackRefGpusMask(RsResourceRef *pResourceRef)
{
NvU32 gpuMask = 0x0;
RS_INTER_MAPPING_BACK_REF *pBackRefItem;
if (pResourceRef == NULL)
{
return 0x0;
}
pBackRefItem = listHead(&pResourceRef->interBackRefs);
while (pBackRefItem != NULL)
{
RsInterMapping *pMapping = pBackRefItem->pMapping;
RsResourceRef *pDeviceRef = pMapping->pContextRef;
GpuResource *pGpuResource = dynamicCast(pDeviceRef->pResource, GpuResource);
if (pGpuResource != NULL)
{
OBJGPU *pGpu = GPU_RES_GET_GPU(pGpuResource);
gpuMask |= gpumgrGetGpuMask(pGpu);
}
pBackRefItem = listNext(&pResourceRef->interBackRefs, pBackRefItem);
}
return gpuMask;
}
NV_STATUS
serverResLock_Prologue
(
@@ -410,8 +440,15 @@ serverResLock_Prologue
}
else
{
status = rmGpuGroupLockAcquire(pParentGpu->gpuInstance,
GPU_LOCK_GRP_DEVICE,
//
// Lock the parent GPU and if specified any GPUs that resource
// may backreference via mappings.
//
pLockInfo->gpuMask = gpumgrGetGpuMask(pParentGpu) |
_resGetBackRefGpusMask(pLockInfo->pResRefToBackRef);
status = rmGpuGroupLockAcquire(0,
GPU_LOCK_GRP_MASK,
GPUS_LOCK_FLAGS_NONE,
RM_LOCK_MODULES_CLIENT,
&pLockInfo->gpuMask);

1
src/nvidia/src/libraries/resserv/src/rs_server.c
View File

@@ -157,6 +157,7 @@ NV_STATUS serverFreeResourceTreeUnderLock(RsServer *pServer, RS_RES_FREE_PARAMS
else
{
pLockInfo->flags |= RS_LOCK_FLAGS_FREE_SESSION_LOCK;
pLockInfo->pResRefToBackRef = pResourceRef;
pLockInfo->traceOp = RS_LOCK_TRACE_FREE;
pLockInfo->traceClassId = pResourceRef->externalClassId;
status = serverResLock_Prologue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags);

2
version.mk
View File

@@ -1,4 +1,4 @@
NVIDIA_VERSION = 550.135
NVIDIA_VERSION = 550.142
# This file.
VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))