595.44.05

2026-05-12 16:56:07 +00:00 · 2026-04-02 17:01:33 -07:00
parent 667aaff654
commit b04fce9aeb
17 changed files with 199 additions and 23 deletions
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 # NVIDIA Linux Open GPU Kernel Module Source

 This is the source release of the NVIDIA Linux open GPU kernel modules,
-version 595.44.03.
+version 595.44.05.


 ## How to Build
@@ -17,7 +17,7 @@ as root:

 Note that the kernel modules built here must be used with GSP
 firmware and user-space NVIDIA GPU driver components from a corresponding
-595.44.03 driver release.  This can be achieved by installing
+595.44.05 driver release.  This can be achieved by installing
 the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
 option.  E.g.,

@@ -185,7 +185,7 @@ table below).
 For details on feature support and limitations, see the NVIDIA GPU driver
 end user README here:

-https://us.download.nvidia.com/XFree86/Linux-x86_64/595.44.03/README/kernel_open.html
+https://us.download.nvidia.com/XFree86/Linux-x86_64/595.44.05/README/kernel_open.html

 For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
 Package for more details.
@@ -946,6 +946,7 @@ Subsystem Device ID.
 | NVIDIA B200                                             | 2901 10DE 1999 |
 | NVIDIA B200                                             | 2901 10DE 199B |
 | NVIDIA B200                                             | 2901 10DE 20DA |
+| NVIDIA B200                                             | 2909 10DE 22EB |
 | NVIDIA GB200                                            | 2941 10DE 2046 |
 | NVIDIA GB200                                            | 2941 10DE 20CA |
 | NVIDIA GB200                                            | 2941 10DE 20D5 |
@@ -974,6 +975,8 @@ Subsystem Device ID.
 | NVIDIA RTX PRO 6000 Blackwell Server Edition            | 2BB5 10DE 204E |
 | NVIDIA RTX PRO 6000 Blackwell Server Edition            | 2BB5 10DE 220B |
 | NVIDIA RTX 6000D                                        | 2BB9 10DE 2091 |
+| NVIDIA RTX 6000D                                        | 2BB9 10DE 2092 |
+| NVIDIA RTX 6000D                                        | 2BB9 10DE 2279 |
 | NVIDIA GeForce RTX 5080                                 | 2C02           |
 | NVIDIA GeForce RTX 5070 Ti                              | 2C05           |
 | NVIDIA GeForce RTX 5090 Laptop GPU                      | 2C18           |
@@ -992,6 +995,7 @@ Subsystem Device ID.
 | NVIDIA RTX PRO 4000 Blackwell                           | 2C34 17AA 2052 |
 | NVIDIA RTX PRO 5000 Blackwell Generation Laptop GPU     | 2C38           |
 | NVIDIA RTX PRO 4000 Blackwell Generation Laptop GPU     | 2C39           |
+| NVIDIA RTX PRO 4500 Blackwell Server Edition            | 2C3A 10DE 21F4 |
 | NVIDIA GeForce RTX 5090 Laptop GPU                      | 2C58           |
 | NVIDIA GeForce RTX 5080 Laptop GPU                      | 2C59           |
 | NVIDIA RTX PRO 5000 Blackwell Embedded GPU              | 2C77           |
@@ -1021,3 +1025,4 @@ Subsystem Device ID.
 | NVIDIA GeForce RTX 5070 Ti Laptop GPU                   | 2F58           |
 | NVIDIA B300 SXM6 AC                                     | 3182 10DE 20E6 |
 | NVIDIA GB300                                            | 31C2 10DE 21F1 |
+| NVIDIA GB300                                            | 31C3 10DE 22F8 |
--- a/kernel-open/Kbuild
+++ b/kernel-open/Kbuild
@@ -79,7 +79,7 @@ ccflags-y += -I$(src)/common/inc
 ccflags-y += -I$(src)
 ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
 ccflags-y += -D__KERNEL__ -DMODULE -DNVRM
-ccflags-y += -DNV_VERSION_STRING=\"595.44.03\"
+ccflags-y += -DNV_VERSION_STRING=\"595.44.05\"

 # Include and link Tegra out-of-tree modules.
 ifneq ($(wildcard /usr/src/nvidia/nvidia-public),)
--- a/kernel-open/nvidia-uvm/uvm_gpu.c
+++ b/kernel-open/nvidia-uvm/uvm_gpu.c
@@ -3222,10 +3222,25 @@ uvm_gpu_phys_address_t uvm_gpu_peer_phys_address(uvm_gpu_t *owning_gpu, NvU64 ad
 uvm_gpu_address_t uvm_gpu_peer_copy_address(uvm_gpu_t *owning_gpu, NvU64 address, uvm_gpu_t *accessing_gpu)
 {
    uvm_gpu_identity_mapping_t *gpu_peer_mapping;
+    const bool mig_peers_use_phys = uvm_gpus_are_smc_peers(owning_gpu, accessing_gpu) &&
+        accessing_gpu->parent->ce_phys_vidmem_write_supported;

-    if (accessing_gpu->parent->peer_copy_mode == UVM_GPU_PEER_COPY_MODE_PHYSICAL)
+    // MIG peers do not create peer vidmem mappings like other peers. They do
+    // create their vidmem identity mappings to cover all possible physical
+    // addresses, even those of other MIG peers.
+    // Use vidmem this identity mapping if CEs need to use virtual addresses.
+    if (uvm_gpus_are_smc_peers(owning_gpu, accessing_gpu) && !mig_peers_use_phys) {
+        uvm_gpu_phys_address_t phys_address = uvm_gpu_peer_phys_address(owning_gpu, address, accessing_gpu);
+        return uvm_gpu_address_virtual_from_vidmem_phys(accessing_gpu, phys_address.address);
+    }
+
+    // Use physical addresses for MIGs peers if CE allows it. Irespective of
+    // the peer copy mode.
+    if (accessing_gpu->parent->peer_copy_mode == UVM_GPU_PEER_COPY_MODE_PHYSICAL || mig_peers_use_phys)
        return uvm_gpu_address_from_phys(uvm_gpu_peer_phys_address(owning_gpu, address, accessing_gpu));

+    // MIG peers do not create peer GPU mappings so it should never reach here.
+    UVM_ASSERT(!uvm_gpus_are_smc_peers(owning_gpu, accessing_gpu));
    UVM_ASSERT(accessing_gpu->parent->peer_copy_mode == UVM_GPU_PEER_COPY_MODE_VIRTUAL);
    gpu_peer_mapping = uvm_gpu_get_peer_mapping(accessing_gpu, owning_gpu->id);

--- a/src/common/displayport/inc/dp_connectorimpl2x.h
+++ b/src/common/displayport/inc/dp_connectorimpl2x.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2023-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -110,6 +110,7 @@ namespace DisplayPort
        bool    bStuffDummySymbolsFor128b132b;
        bool    bStuffDummySymbolsFor8b10b;
        bool    bDisableWatermarkCaching;
+        bool    bEnableClearMSAWhenNotUsed;

        // Do not enable downspread while link training.
        bool    bDisableDownspread;
--- a/src/common/displayport/inc/dp_regkeydatabase.h
+++ b/src/common/displayport/inc/dp_regkeydatabase.h
@@ -118,6 +118,9 @@

 #define NV_DP_REGKEY_DISABLE_NATIVE_DISPLAYID2X_SUPPORT    "DISABLE_NATIVE_DISPLAYID2X_SUPPORT"
 #define NV_DP_REGKEY_FORCE_NLPIGNORE_DDS                   "DP_FORCE_NLPIGNORE_DDS"
+
+#define NV_DP_REGKEY_ENABLE_CLEAR_MSA_WHEN_NOT_USED          "DP_ENABLE_CLEAR_MSA_WHEN_NOT_USED"
+
 //
 // Data Base used to store all the regkey values.
 // The actual data base is declared statically in dp_evoadapter.cpp.
@@ -169,6 +172,7 @@ struct DP_REGKEY_DATABASE
    bool  bDisableNativeDisplayId2xSupport;
    bool  bUseMaxDSCCompressionMST;
    bool  bIgnoreUnplugUnlessRequested;
+    bool  bEnableClearMSAWhenNotUsed;
 };

 extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;
--- a/src/common/displayport/src/dp_connectorimpl.cpp
+++ b/src/common/displayport/src/dp_connectorimpl.cpp
@@ -7342,7 +7342,7 @@ void ConnectorImpl::notifyLongPulse(bool statusConnected)
            return;
        }

-        if (existingDev && (existingDev->isPreviouslyFakedMuxDevice() || bIgnoreUnplugUnlessRequested) && !existingDev->isMarkedForDeletion())
+        if (existingDev && existingDev->isPreviouslyFakedMuxDevice() && !existingDev->isMarkedForDeletion())
        {
            DP_PRINTF(DP_NOTICE, "NotifyLongPulse ignored as there is a previously faked device but it is not marked for deletion");
            if (!statusConnected)
@@ -7352,6 +7352,12 @@ void ConnectorImpl::notifyLongPulse(bool statusConnected)
            }
            return;
        }
+
+		if (existingDev && bIgnoreUnplugUnlessRequested && !statusConnected && !existingDev->isMarkedForDeletion())
+		{
+			sink->notifyDetectComplete();
+			return;
+		}
    }

    if (previousPlugged && statusConnected)
--- a/src/common/displayport/src/dp_connectorimpl2x.cpp
+++ b/src/common/displayport/src/dp_connectorimpl2x.cpp
@@ -114,6 +114,7 @@ void ConnectorImpl2x::applyDP2xRegkeyOverrides()
    this->maxLinkRateFromRegkey = dpRegkeyDatabase.applyMaxLinkRateOverrides;
    bSupportInternalUhbrOnFpga  = dpRegkeyDatabase.supportInternalUhbrOnFpga;
    this->bDisableWatermarkCaching = dpRegkeyDatabase.bDisableWatermarkCaching;
+    this->bEnableClearMSAWhenNotUsed = dpRegkeyDatabase.bEnableClearMSAWhenNotUsed;
    if (dpRegkeyDatabase.bIgnoreCableIdCaps)
    {
        hal->setIgnoreCableIdCaps(true);
@@ -935,6 +936,18 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
        main->setDpStereoMSAParameters(!enableInbandStereoSignaling, modesetParams.msaparams);
        main->setDpMSAParameters(!enableInbandStereoSignaling, modesetParams.msaparams);
    }
+    else
+    {
+        // Clear MSA parameters for MST topology
+        if (this->bEnableClearMSAWhenNotUsed)
+        {
+            NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS msaParams = modesetParams.msaparams;
+            msaParams.bEnableMSA        = false;
+
+            main->setDpStereoMSAParameters(false, msaParams);
+            main->setDpMSAParameters(false, msaParams);
+        }
+    }

    NV_DPTRACE_INFO(NOTIFY_ATTACH_BEGIN_STATUS, bLinkTrainingStatus);

--- a/src/common/displayport/src/dp_evoadapter.cpp
+++ b/src/common/displayport/src/dp_evoadapter.cpp
@@ -116,7 +116,8 @@ const struct
    {NV_DP_REGKEY_ENABLE_128b132b_DSC_LNK_CFG_REDUCTION,  &dpRegkeyDatabase.bEnable128b132bDSCLnkCfgReduction,  DP_REG_VAL_BOOL},
    {NV_DP_REGKEY_DISABLE_NATIVE_DISPLAYID2X_SUPPORT,     &dpRegkeyDatabase.bDisableNativeDisplayId2xSupport,   DP_REG_VAL_BOOL},
    {NV_DP_REGKEY_USE_MAX_DSC_COMPRESSION_MST,            &dpRegkeyDatabase.bUseMaxDSCCompressionMST,           DP_REG_VAL_BOOL},
-    {NV_DP_REGKEY_FORCE_NLPIGNORE_DDS,                    &dpRegkeyDatabase.bIgnoreUnplugUnlessRequested,       DP_REG_VAL_BOOL}
+    {NV_DP_REGKEY_FORCE_NLPIGNORE_DDS,                    &dpRegkeyDatabase.bIgnoreUnplugUnlessRequested,       DP_REG_VAL_BOOL},
+    {NV_DP_REGKEY_ENABLE_CLEAR_MSA_WHEN_NOT_USED,         &dpRegkeyDatabase.bEnableClearMSAWhenNotUsed,         DP_REG_VAL_BOOL}
 };

 EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :
--- a/src/common/inc/nvBldVer.h
+++ b/src/common/inc/nvBldVer.h
@@ -43,18 +43,18 @@
 #endif

 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
-#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r595/VK595_35-124"
-#define NV_BUILD_CHANGELIST_NUM         (37628192)
+#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r595/VK595_35-126"
+#define NV_BUILD_CHANGELIST_NUM         (37724599)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "rel/gpu_drv/r595/VK595_35-124"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37628192)
+#define NV_BUILD_NAME                   "rel/gpu_drv/r595/VK595_35-126"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37724599)

 #else     /* Windows builds */
-#define NV_BUILD_BRANCH_VERSION         "VK595_35-7"
-#define NV_BUILD_CHANGELIST_NUM         (37628192)
+#define NV_BUILD_BRANCH_VERSION         "VK595_35-9"
+#define NV_BUILD_CHANGELIST_NUM         (37724599)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "595.92"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37628192)
+#define NV_BUILD_NAME                   "596.10"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37724599)
 #define NV_BUILD_BRANCH_BASE_VERSION    R595
 #endif
 // End buildmeister python edited section
--- a/src/common/inc/nvUnixVersion.h
+++ b/src/common/inc/nvUnixVersion.h
@@ -5,7 +5,7 @@
    (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) || \
    defined(NV_DCECORE)

-#define NV_VERSION_STRING               "595.44.03"
+#define NV_VERSION_STRING               "595.44.05"

 #else

--- a/src/common/shared/inc/g_vgpu_chip_flags.h
+++ b/src/common/shared/inc/g_vgpu_chip_flags.h
@@ -1063,6 +1063,52 @@ ENTRY(0x2BB9, 0x226E, 0x10de, "NVIDIA RTX 6000D-84C"),
 ENTRY(0x2BB9, 0x226F, 0x10de, "NVIDIA RTX 6000D-84"),
 ENTRY(0x2BB9, 0x22EE, 0x10de, "NVIDIA GeForce RTX 3050"),
 ENTRY(0x2BB9, 0x22EF, 0x10de, "NVIDIA GeForce RTX 3060"),
+ENTRY(0x2C3A, 0x2295, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-2Q"),
+ENTRY(0x2C3A, 0x2296, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-2A"),
+ENTRY(0x2C3A, 0x2297, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-2B"),
+ENTRY(0x2C3A, 0x2298, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-2"),
+ENTRY(0x2C3A, 0x2299, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-3B"),
+ENTRY(0x2C3A, 0x229A, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-4Q"),
+ENTRY(0x2C3A, 0x229B, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-4A"),
+ENTRY(0x2C3A, 0x229C, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-4"),
+ENTRY(0x2C3A, 0x229D, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-8Q"),
+ENTRY(0x2C3A, 0x229E, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-8A"),
+ENTRY(0x2C3A, 0x229F, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-8C"),
+ENTRY(0x2C3A, 0x22A0, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-8"),
+ENTRY(0x2C3A, 0x22A1, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-16Q"),
+ENTRY(0x2C3A, 0x22A2, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-16A"),
+ENTRY(0x2C3A, 0x22A3, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-16C"),
+ENTRY(0x2C3A, 0x22A4, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-16"),
+ENTRY(0x2C3A, 0x22A5, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-8Q"),
+ENTRY(0x2C3A, 0x22A6, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-8A"),
+ENTRY(0x2C3A, 0x22A7, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-8C"),
+ENTRY(0x2C3A, 0x22A8, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-8"),
+ENTRY(0x2C3A, 0x22A9, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-16Q"),
+ENTRY(0x2C3A, 0x22AA, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-16A"),
+ENTRY(0x2C3A, 0x22AB, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-16C"),
+ENTRY(0x2C3A, 0x22AC, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-16"),
+ENTRY(0x2C3A, 0x22AD, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-32Q"),
+ENTRY(0x2C3A, 0x22AE, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-32A"),
+ENTRY(0x2C3A, 0x22AF, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-32C"),
+ENTRY(0x2C3A, 0x22B0, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-32"),
+ENTRY(0x2C3A, 0x22B1, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2B"),
+ENTRY(0x2C3A, 0x22B2, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2"),
+ENTRY(0x2C3A, 0x22B3, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-3B"),
+ENTRY(0x2C3A, 0x22B4, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-4Q"),
+ENTRY(0x2C3A, 0x22B5, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-4A"),
+ENTRY(0x2C3A, 0x22B6, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-4"),
+ENTRY(0x2C3A, 0x22B7, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-8Q"),
+ENTRY(0x2C3A, 0x22B8, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-8A"),
+ENTRY(0x2C3A, 0x22B9, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-8C"),
+ENTRY(0x2C3A, 0x22BA, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-8"),
+ENTRY(0x2C3A, 0x22BB, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-16Q"),
+ENTRY(0x2C3A, 0x22BC, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-16A"),
+ENTRY(0x2C3A, 0x22BD, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-16C"),
+ENTRY(0x2C3A, 0x22BE, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-16"),
+ENTRY(0x2C3A, 0x22BF, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-32Q"),
+ENTRY(0x2C3A, 0x22C0, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-32A"),
+ENTRY(0x2C3A, 0x22C1, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-32C"),
+ENTRY(0x2C3A, 0x22C2, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-32"),
 ENTRY(0x3182, 0x22CB, 0x10de, "NVIDIA B300X-1-34CME"),
 ENTRY(0x3182, 0x22CC, 0x10de, "NVIDIA B300X-1-34C"),
 ENTRY(0x3182, 0x22CD, 0x10de, "NVIDIA B300X-1-67C"),
--- a/src/common/shared/inc/g_vgpu_resman_specific.h
+++ b/src/common/shared/inc/g_vgpu_resman_specific.h
@@ -312,6 +312,34 @@ static const struct {
    {0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2206}, // NVIDIA RTX 6000D-2-84
    {0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF)   , 2266}, // NVIDIA GeForce RTX 3050
    {0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF)   , 2267}, // NVIDIA GeForce RTX 3060
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2229}, // NVIDIA RTX PRO 4500 Blackwell DC-1-2Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2230}, // NVIDIA RTX PRO 4500 Blackwell DC-1-2A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2231}, // NVIDIA RTX PRO 4500 Blackwell DC-1-2B
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2232}, // NVIDIA RTX PRO 4500 Blackwell DC-1-2
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2233}, // NVIDIA RTX PRO 4500 Blackwell DC-1-3B
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2234}, // NVIDIA RTX PRO 4500 Blackwell DC-1-4Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2235}, // NVIDIA RTX PRO 4500 Blackwell DC-1-4A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2236}, // NVIDIA RTX PRO 4500 Blackwell DC-1-4
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2237}, // NVIDIA RTX PRO 4500 Blackwell DC-1-8Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2238}, // NVIDIA RTX PRO 4500 Blackwell DC-1-8A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2239}, // NVIDIA RTX PRO 4500 Blackwell DC-1-8C
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2240}, // NVIDIA RTX PRO 4500 Blackwell DC-1-8
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2241}, // NVIDIA RTX PRO 4500 Blackwell DC-1-16Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2242}, // NVIDIA RTX PRO 4500 Blackwell DC-1-16A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2243}, // NVIDIA RTX PRO 4500 Blackwell DC-1-16C
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF)             , 2244}, // NVIDIA RTX PRO 4500 Blackwell DC-1-16
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2245}, // NVIDIA RTX PRO 4500 Blackwell DC-2-8Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2246}, // NVIDIA RTX PRO 4500 Blackwell DC-2-8A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2247}, // NVIDIA RTX PRO 4500 Blackwell DC-2-8C
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2248}, // NVIDIA RTX PRO 4500 Blackwell DC-2-8
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2249}, // NVIDIA RTX PRO 4500 Blackwell DC-2-16Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2250}, // NVIDIA RTX PRO 4500 Blackwell DC-2-16A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2251}, // NVIDIA RTX PRO 4500 Blackwell DC-2-16C
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2252}, // NVIDIA RTX PRO 4500 Blackwell DC-2-16
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2253}, // NVIDIA RTX PRO 4500 Blackwell DC-2-32Q
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2254}, // NVIDIA RTX PRO 4500 Blackwell DC-2-32A
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2255}, // NVIDIA RTX PRO 4500 Blackwell DC-2-32C
+    {0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL)                 , 2256}, // NVIDIA RTX PRO 4500 Blackwell DC-2-32
    {0x318210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 2259}, // NVIDIA B300X-1-34CME
    {0x318210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU                                                                     , 2258}, // NVIDIA B300X-1-34C
    {0x318210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU                                                                 , 2260}, // NVIDIA B300X-1-67C
--- a/src/nvidia/arch/nvalloc/unix/src/osapi.c
+++ b/src/nvidia/arch/nvalloc/unix/src/osapi.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -1376,7 +1376,11 @@ RmDmabufVerifyMemHandle(

    pMemDesc = pSrcMemory->pMemDesc;

-    if (pGpuInstanceInfo != NULL)
+    //
+    // We skip the partitionable heap check when the source memory is in
+    // sysmem as there is no valid heap (pHeap will be NULL).
+    //
+    if (pGpuInstanceInfo != NULL && memdescGetAddressSpace(pMemDesc) != ADDR_SYSMEM)
    {
        KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance;
        pKernelMIGGpuInstance = (KERNEL_MIG_GPU_INSTANCE *) pGpuInstanceInfo;
--- a/src/nvidia/generated/g_nv_name_released.h
+++ b/src/nvidia/generated/g_nv_name_released.h
@@ -782,6 +782,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
    { 0x2901, 0x1999, 0x10de, "NVIDIA B200" },
    { 0x2901, 0x199b, 0x10de, "NVIDIA B200" },
    { 0x2901, 0x20da, 0x10de, "NVIDIA B200" },
+    { 0x2909, 0x22eb, 0x10de, "NVIDIA B200" },
    { 0x2941, 0x2046, 0x10de, "NVIDIA GB200" },
    { 0x2941, 0x20ca, 0x10de, "NVIDIA GB200" },
    { 0x2941, 0x20d5, 0x10de, "NVIDIA GB200" },
@@ -810,6 +811,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
    { 0x2BB5, 0x204e, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Server Edition" },
    { 0x2BB5, 0x220b, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Server Edition" },
    { 0x2BB9, 0x2091, 0x10de, "NVIDIA RTX 6000D" },
+    { 0x2BB9, 0x2092, 0x10de, "NVIDIA RTX 6000D" },
+    { 0x2BB9, 0x2279, 0x10de, "NVIDIA RTX 6000D" },
    { 0x2C02, 0x0000, 0x0000, "NVIDIA GeForce RTX 5080" },
    { 0x2C05, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti" },
    { 0x2C18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 Laptop GPU" },
@@ -828,6 +831,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
    { 0x2C34, 0x2052, 0x17aa, "NVIDIA RTX PRO 4000 Blackwell" },
    { 0x2C38, 0x0000, 0x0000, "NVIDIA RTX PRO 5000 Blackwell Generation Laptop GPU" },
    { 0x2C39, 0x0000, 0x0000, "NVIDIA RTX PRO 4000 Blackwell Generation Laptop GPU" },
+    { 0x2C3A, 0x21f4, 0x10de, "NVIDIA RTX PRO 4500 Blackwell Server Edition" },
    { 0x2C58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 Laptop GPU" },
    { 0x2C59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5080 Laptop GPU" },
    { 0x2C77, 0x0000, 0x0000, "NVIDIA RTX PRO 5000 Blackwell Embedded GPU" },
@@ -857,6 +861,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
    { 0x2F58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },
    { 0x3182, 0x20e6, 0x10de, "NVIDIA B300 SXM6 AC" },
    { 0x31C2, 0x21f1, 0x10de, "NVIDIA GB300" },
+    { 0x31C3, 0x22f8, 0x10de, "NVIDIA GB300" },
    { 0x1E37, 0x1347, 0x10DE, "GeForce RTX T10x-8" },
    { 0x1E37, 0x1348, 0x10DE, "GeForce RTX T10x-4" },
    { 0x1E37, 0x1349, 0x10DE, "GeForce RTX T10x-2" },
@@ -1899,6 +1904,52 @@ static const CHIPS_RELEASED sChipsReleased[] = {
    { 0x2BB9, 0x226f, 0x10DE, "NVIDIA RTX 6000D-84" },
    { 0x2BB9, 0x22ee, 0x10DE, "NVIDIA GeForce RTX 3050" },
    { 0x2BB9, 0x22ef, 0x10DE, "NVIDIA GeForce RTX 3060" },
+    { 0x2C3A, 0x2295, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-2Q" },
+    { 0x2C3A, 0x2296, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-2A" },
+    { 0x2C3A, 0x2297, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-2B" },
+    { 0x2C3A, 0x2298, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-2" },
+    { 0x2C3A, 0x2299, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-3B" },
+    { 0x2C3A, 0x229a, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-4Q" },
+    { 0x2C3A, 0x229b, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-4A" },
+    { 0x2C3A, 0x229c, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-4" },
+    { 0x2C3A, 0x229d, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-8Q" },
+    { 0x2C3A, 0x229e, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-8A" },
+    { 0x2C3A, 0x229f, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-8C" },
+    { 0x2C3A, 0x22a0, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-8" },
+    { 0x2C3A, 0x22a1, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-16Q" },
+    { 0x2C3A, 0x22a2, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-16A" },
+    { 0x2C3A, 0x22a3, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-16C" },
+    { 0x2C3A, 0x22a4, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-1-16" },
+    { 0x2C3A, 0x22a5, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-8Q" },
+    { 0x2C3A, 0x22a6, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-8A" },
+    { 0x2C3A, 0x22a7, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-8C" },
+    { 0x2C3A, 0x22a8, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-8" },
+    { 0x2C3A, 0x22a9, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-16Q" },
+    { 0x2C3A, 0x22aa, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-16A" },
+    { 0x2C3A, 0x22ab, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-16C" },
+    { 0x2C3A, 0x22ac, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-16" },
+    { 0x2C3A, 0x22ad, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-32Q" },
+    { 0x2C3A, 0x22ae, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-32A" },
+    { 0x2C3A, 0x22af, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-32C" },
+    { 0x2C3A, 0x22b0, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2-32" },
+    { 0x2C3A, 0x22b1, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2B" },
+    { 0x2C3A, 0x22b2, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-2" },
+    { 0x2C3A, 0x22b3, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-3B" },
+    { 0x2C3A, 0x22b4, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-4Q" },
+    { 0x2C3A, 0x22b5, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-4A" },
+    { 0x2C3A, 0x22b6, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-4" },
+    { 0x2C3A, 0x22b7, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-8Q" },
+    { 0x2C3A, 0x22b8, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-8A" },
+    { 0x2C3A, 0x22b9, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-8C" },
+    { 0x2C3A, 0x22ba, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-8" },
+    { 0x2C3A, 0x22bb, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-16Q" },
+    { 0x2C3A, 0x22bc, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-16A" },
+    { 0x2C3A, 0x22bd, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-16C" },
+    { 0x2C3A, 0x22be, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-16" },
+    { 0x2C3A, 0x22bf, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-32Q" },
+    { 0x2C3A, 0x22c0, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-32A" },
+    { 0x2C3A, 0x22c1, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-32C" },
+    { 0x2C3A, 0x22c2, 0x10DE, "NVIDIA RTX PRO 4500 Blackwell DC-32" },
    { 0x3182, 0x22cb, 0x10DE, "NVIDIA B300X-1-34CME" },
    { 0x3182, 0x22cc, 0x10DE, "NVIDIA B300X-1-34C" },
    { 0x3182, 0x22cd, 0x10DE, "NVIDIA B300X-1-67C" },
--- a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c
+++ b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c
@@ -389,7 +389,7 @@ fabricvaspaceAllocNonContiguous_IMPL
 {
    NV_STATUS status    = NV_OK;
    NvU64     freeSize  = 0;
-    NvU32     pageCount = (size / pageSize);
+    NvU32     pageCount;
    NvU64     addr;
    NvU32     idx;
    NvBool    bDefaultAllocMode;
@@ -410,6 +410,8 @@ fabricvaspaceAllocNonContiguous_IMPL
    NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(align, pageSize), NV_ERR_INVALID_ARGUMENT);
    NV_ASSERT_OR_RETURN(NV_IS_ALIGNED64(size, pageSize),  NV_ERR_INVALID_ARGUMENT);

+    pageCount = (NvU32)(size / pageSize);
+
    // Check if heap can satisfy the request.
    NV_ASSERT_OK_OR_RETURN(fabricvaspaceGetFreeHeap(pFabricVAS, &freeSize));
    if (freeSize < size)
--- a/src/nvidia/src/kernel/mem_mgr/mem_fabric_import_ref.c
+++ b/src/nvidia/src/kernel/mem_mgr/mem_fabric_import_ref.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2024-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
--- a/version.mk
+++ b/version.mk
@@ -1,5 +1,5 @@
-NVIDIA_VERSION = 595.44.03
-NVIDIA_NVID_VERSION = 595.44.03
+NVIDIA_VERSION = 595.44.05
+NVIDIA_NVID_VERSION = 595.44.05
 NVIDIA_NVID_EXTRA = 

 # This file.