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595.44.05

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This commit is contained in:
russellcnv
2026-04-02 17:01:33 -07:00
parent 667aaff654
commit b04fce9aeb
17 changed files with 199 additions and 23 deletions
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3
src/common/displayport/inc/dp_connectorimpl2x.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -110,6 +110,7 @@ namespace DisplayPort
bool bStuffDummySymbolsFor128b132b;
bool bStuffDummySymbolsFor8b10b;
bool bDisableWatermarkCaching;
bool bEnableClearMSAWhenNotUsed;
// Do not enable downspread while link training.
bool bDisableDownspread;

4
src/common/displayport/inc/dp_regkeydatabase.h
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@@ -118,6 +118,9 @@
#define NV_DP_REGKEY_DISABLE_NATIVE_DISPLAYID2X_SUPPORT "DISABLE_NATIVE_DISPLAYID2X_SUPPORT"
#define NV_DP_REGKEY_FORCE_NLPIGNORE_DDS "DP_FORCE_NLPIGNORE_DDS"
#define NV_DP_REGKEY_ENABLE_CLEAR_MSA_WHEN_NOT_USED "DP_ENABLE_CLEAR_MSA_WHEN_NOT_USED"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -169,6 +172,7 @@ struct DP_REGKEY_DATABASE
bool bDisableNativeDisplayId2xSupport;
bool bUseMaxDSCCompressionMST;
bool bIgnoreUnplugUnlessRequested;
bool bEnableClearMSAWhenNotUsed;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;

8
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -7342,7 +7342,7 @@ void ConnectorImpl::notifyLongPulse(bool statusConnected)
return;
}
if (existingDev && (existingDev->isPreviouslyFakedMuxDevice() || bIgnoreUnplugUnlessRequested) && !existingDev->isMarkedForDeletion())
if (existingDev && existingDev->isPreviouslyFakedMuxDevice() && !existingDev->isMarkedForDeletion())
{
DP_PRINTF(DP_NOTICE, "NotifyLongPulse ignored as there is a previously faked device but it is not marked for deletion");
if (!statusConnected)
@@ -7352,6 +7352,12 @@ void ConnectorImpl::notifyLongPulse(bool statusConnected)
}
return;
}
if (existingDev && bIgnoreUnplugUnlessRequested && !statusConnected && !existingDev->isMarkedForDeletion())
{
sink->notifyDetectComplete();
return;
}
}
if (previousPlugged && statusConnected)

13
src/common/displayport/src/dp_connectorimpl2x.cpp
View File

@@ -114,6 +114,7 @@ void ConnectorImpl2x::applyDP2xRegkeyOverrides()
this->maxLinkRateFromRegkey = dpRegkeyDatabase.applyMaxLinkRateOverrides;
bSupportInternalUhbrOnFpga = dpRegkeyDatabase.supportInternalUhbrOnFpga;
this->bDisableWatermarkCaching = dpRegkeyDatabase.bDisableWatermarkCaching;
this->bEnableClearMSAWhenNotUsed = dpRegkeyDatabase.bEnableClearMSAWhenNotUsed;
if (dpRegkeyDatabase.bIgnoreCableIdCaps)
{
hal->setIgnoreCableIdCaps(true);
@@ -935,6 +936,18 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
main->setDpStereoMSAParameters(!enableInbandStereoSignaling, modesetParams.msaparams);
main->setDpMSAParameters(!enableInbandStereoSignaling, modesetParams.msaparams);
}
else
{
// Clear MSA parameters for MST topology
if (this->bEnableClearMSAWhenNotUsed)
{
NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS msaParams = modesetParams.msaparams;
msaParams.bEnableMSA = false;
main->setDpStereoMSAParameters(false, msaParams);
main->setDpMSAParameters(false, msaParams);
}
}
NV_DPTRACE_INFO(NOTIFY_ATTACH_BEGIN_STATUS, bLinkTrainingStatus);

3
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -116,7 +116,8 @@ const struct
{NV_DP_REGKEY_ENABLE_128b132b_DSC_LNK_CFG_REDUCTION, &dpRegkeyDatabase.bEnable128b132bDSCLnkCfgReduction, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_NATIVE_DISPLAYID2X_SUPPORT, &dpRegkeyDatabase.bDisableNativeDisplayId2xSupport, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_USE_MAX_DSC_COMPRESSION_MST, &dpRegkeyDatabase.bUseMaxDSCCompressionMST, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_NLPIGNORE_DDS, &dpRegkeyDatabase.bIgnoreUnplugUnlessRequested, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_FORCE_NLPIGNORE_DDS, &dpRegkeyDatabase.bIgnoreUnplugUnlessRequested, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_CLEAR_MSA_WHEN_NOT_USED, &dpRegkeyDatabase.bEnableClearMSAWhenNotUsed, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

16
src/common/inc/nvBldVer.h
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@@ -43,18 +43,18 @@
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r595/VK595_35-124"
#define NV_BUILD_CHANGELIST_NUM (37628192)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r595/VK595_35-126"
#define NV_BUILD_CHANGELIST_NUM (37724599)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r595/VK595_35-124"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37628192)
#define NV_BUILD_NAME "rel/gpu_drv/r595/VK595_35-126"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37724599)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "VK595_35-7"
#define NV_BUILD_CHANGELIST_NUM (37628192)
#define NV_BUILD_BRANCH_VERSION "VK595_35-9"
#define NV_BUILD_CHANGELIST_NUM (37724599)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "595.92"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37628192)
#define NV_BUILD_NAME "596.10"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37724599)
#define NV_BUILD_BRANCH_BASE_VERSION R595
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -5,7 +5,7 @@
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) || \
defined(NV_DCECORE)
#define NV_VERSION_STRING "595.44.03"
#define NV_VERSION_STRING "595.44.05"
#else

46
src/common/shared/inc/g_vgpu_chip_flags.h
View File

@@ -1063,6 +1063,52 @@ ENTRY(0x2BB9, 0x226E, 0x10de, "NVIDIA RTX 6000D-84C"),
ENTRY(0x2BB9, 0x226F, 0x10de, "NVIDIA RTX 6000D-84"),
ENTRY(0x2BB9, 0x22EE, 0x10de, "NVIDIA GeForce RTX 3050"),
ENTRY(0x2BB9, 0x22EF, 0x10de, "NVIDIA GeForce RTX 3060"),
ENTRY(0x2C3A, 0x2295, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-2Q"),
ENTRY(0x2C3A, 0x2296, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-2A"),
ENTRY(0x2C3A, 0x2297, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-2B"),
ENTRY(0x2C3A, 0x2298, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-2"),
ENTRY(0x2C3A, 0x2299, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-3B"),
ENTRY(0x2C3A, 0x229A, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-4Q"),
ENTRY(0x2C3A, 0x229B, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-4A"),
ENTRY(0x2C3A, 0x229C, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-4"),
ENTRY(0x2C3A, 0x229D, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-8Q"),
ENTRY(0x2C3A, 0x229E, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-8A"),
ENTRY(0x2C3A, 0x229F, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-8C"),
ENTRY(0x2C3A, 0x22A0, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-8"),
ENTRY(0x2C3A, 0x22A1, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-16Q"),
ENTRY(0x2C3A, 0x22A2, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-16A"),
ENTRY(0x2C3A, 0x22A3, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-16C"),
ENTRY(0x2C3A, 0x22A4, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-1-16"),
ENTRY(0x2C3A, 0x22A5, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-8Q"),
ENTRY(0x2C3A, 0x22A6, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-8A"),
ENTRY(0x2C3A, 0x22A7, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-8C"),
ENTRY(0x2C3A, 0x22A8, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-8"),
ENTRY(0x2C3A, 0x22A9, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-16Q"),
ENTRY(0x2C3A, 0x22AA, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-16A"),
ENTRY(0x2C3A, 0x22AB, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-16C"),
ENTRY(0x2C3A, 0x22AC, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-16"),
ENTRY(0x2C3A, 0x22AD, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-32Q"),
ENTRY(0x2C3A, 0x22AE, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-32A"),
ENTRY(0x2C3A, 0x22AF, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-32C"),
ENTRY(0x2C3A, 0x22B0, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2-32"),
ENTRY(0x2C3A, 0x22B1, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2B"),
ENTRY(0x2C3A, 0x22B2, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-2"),
ENTRY(0x2C3A, 0x22B3, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-3B"),
ENTRY(0x2C3A, 0x22B4, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-4Q"),
ENTRY(0x2C3A, 0x22B5, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-4A"),
ENTRY(0x2C3A, 0x22B6, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-4"),
ENTRY(0x2C3A, 0x22B7, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-8Q"),
ENTRY(0x2C3A, 0x22B8, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-8A"),
ENTRY(0x2C3A, 0x22B9, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-8C"),
ENTRY(0x2C3A, 0x22BA, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-8"),
ENTRY(0x2C3A, 0x22BB, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-16Q"),
ENTRY(0x2C3A, 0x22BC, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-16A"),
ENTRY(0x2C3A, 0x22BD, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-16C"),
ENTRY(0x2C3A, 0x22BE, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-16"),
ENTRY(0x2C3A, 0x22BF, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-32Q"),
ENTRY(0x2C3A, 0x22C0, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-32A"),
ENTRY(0x2C3A, 0x22C1, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-32C"),
ENTRY(0x2C3A, 0x22C2, 0x10de, "NVIDIA RTX PRO 4500 Blackwell DC-32"),
ENTRY(0x3182, 0x22CB, 0x10de, "NVIDIA B300X-1-34CME"),
ENTRY(0x3182, 0x22CC, 0x10de, "NVIDIA B300X-1-34C"),
ENTRY(0x3182, 0x22CD, 0x10de, "NVIDIA B300X-1-67C"),

28
src/common/shared/inc/g_vgpu_resman_specific.h
View File

@@ -312,6 +312,34 @@ static const struct {
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2206}, // NVIDIA RTX 6000D-2-84
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF) , 2266}, // NVIDIA GeForce RTX 3050
{0x2BB910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _MINI_HALF) , 2267}, // NVIDIA GeForce RTX 3060
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2229}, // NVIDIA RTX PRO 4500 Blackwell DC-1-2Q
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2230}, // NVIDIA RTX PRO 4500 Blackwell DC-1-2A
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2231}, // NVIDIA RTX PRO 4500 Blackwell DC-1-2B
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2232}, // NVIDIA RTX PRO 4500 Blackwell DC-1-2
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2233}, // NVIDIA RTX PRO 4500 Blackwell DC-1-3B
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2234}, // NVIDIA RTX PRO 4500 Blackwell DC-1-4Q
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2235}, // NVIDIA RTX PRO 4500 Blackwell DC-1-4A
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2236}, // NVIDIA RTX PRO 4500 Blackwell DC-1-4
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2237}, // NVIDIA RTX PRO 4500 Blackwell DC-1-8Q
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2238}, // NVIDIA RTX PRO 4500 Blackwell DC-1-8A
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2239}, // NVIDIA RTX PRO 4500 Blackwell DC-1-8C
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2240}, // NVIDIA RTX PRO 4500 Blackwell DC-1-8
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2241}, // NVIDIA RTX PRO 4500 Blackwell DC-1-16Q
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2242}, // NVIDIA RTX PRO 4500 Blackwell DC-1-16A
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2243}, // NVIDIA RTX PRO 4500 Blackwell DC-1-16C
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _HALF) , 2244}, // NVIDIA RTX PRO 4500 Blackwell DC-1-16
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2245}, // NVIDIA RTX PRO 4500 Blackwell DC-2-8Q
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2246}, // NVIDIA RTX PRO 4500 Blackwell DC-2-8A
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2247}, // NVIDIA RTX PRO 4500 Blackwell DC-2-8C
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2248}, // NVIDIA RTX PRO 4500 Blackwell DC-2-8
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2249}, // NVIDIA RTX PRO 4500 Blackwell DC-2-16Q
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2250}, // NVIDIA RTX PRO 4500 Blackwell DC-2-16A
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2251}, // NVIDIA RTX PRO 4500 Blackwell DC-2-16C
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2252}, // NVIDIA RTX PRO 4500 Blackwell DC-2-16
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2253}, // NVIDIA RTX PRO 4500 Blackwell DC-2-32Q
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2254}, // NVIDIA RTX PRO 4500 Blackwell DC-2-32A
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2255}, // NVIDIA RTX PRO 4500 Blackwell DC-2-32C
{0x2C3A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _GFX_SIZE, _FULL) , 2256}, // NVIDIA RTX PRO 4500 Blackwell DC-2-32
{0x318210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 2259}, // NVIDIA B300X-1-34CME
{0x318210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 2258}, // NVIDIA B300X-1-34C
{0x318210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 2260}, // NVIDIA B300X-1-67C