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This commit is contained in:
Andy Ritger
2023-10-17 09:25:29 -07:00
parent f59818b751
commit b5bf85a8e3
917 changed files with 132480 additions and 110015 deletions
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157
src/common/sdk/nvidia/inc/class/cl00de.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -28,21 +28,168 @@
extern "C" {
#endif
#include "nvmisc.h"
#include "nvfixedtypes.h"
#define RM_USER_SHARED_DATA (0x000000de)
#define RUSD_TIMESTAMP_WRITE_IN_PROGRESS (NV_U64_MAX)
#define RUSD_TIMESTAMP_INVALID 0
enum {
RUSD_CLK_PUBLIC_DOMAIN_GRAPHICS = 0,
RUSD_CLK_PUBLIC_DOMAIN_MEMORY,
RUSD_CLK_PUBLIC_DOMAIN_VIDEO,
// Put at the end. See bug 1000230 NVML doesn't report SM frequency on Kepler
RUSD_CLK_PUBLIC_DOMAIN_SM,
RUSD_CLK_PUBLIC_DOMAIN_MAX_TYPE,
};
enum {
RUSD_CLK_THROTTLE_REASON_GPU_IDLE = NVBIT(0),
RUSD_CLK_THROTTLE_REASON_APPLICATION_CLOCK_SETTING = NVBIT(1),
RUSD_CLK_THROTTLE_REASON_SW_POWER_CAP = NVBIT(2),
RUSD_CLK_THROTTLE_REASON_HW_SLOWDOWN = NVBIT(3),
RUSD_CLK_THROTTLE_REASON_SYNC_BOOST = NVBIT(4),
RUSD_CLK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN = NVBIT(5),
RUSD_CLK_THROTTLE_REASON_HW_THERMAL_SLOWDOWN = NVBIT(6),
RUSD_CLK_THROTTLE_REASON_HW_POWER_BRAKES_SLOWDOWN = NVBIT(7),
RUSD_CLK_THROTTLE_REASON_DISPLAY_CLOCK_SETTING = NVBIT(8),
};
typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFO {
NvU32 targetClkMHz;
} RUSD_CLK_PUBLIC_DOMAIN_INFO;
typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFOS {
volatile NvU64 lastModifiedTimestamp;
RUSD_CLK_PUBLIC_DOMAIN_INFO info[RUSD_CLK_PUBLIC_DOMAIN_MAX_TYPE];
} RUSD_CLK_PUBLIC_DOMAIN_INFOS;
typedef struct RUSD_PERF_DEVICE_UTILIZATION_INFO {
NvU8 gpuPercentBusy;
NvU8 memoryPercentBusy;
} RUSD_PERF_DEVICE_UTILIZATION_INFO;
typedef struct RUSD_PERF_DEVICE_UTILIZATION {
volatile NvU64 lastModifiedTimestamp;
RUSD_PERF_DEVICE_UTILIZATION_INFO info;
} RUSD_PERF_DEVICE_UTILIZATION;
typedef struct RUSD_PERF_CURRENT_PSTATE {
volatile NvU64 lastModifiedTimestamp;
NvU32 currentPstate;
} RUSD_PERF_CURRENT_PSTATE;
typedef struct RUSD_CLK_THROTTLE_REASON {
volatile NvU64 lastModifiedTimestamp;
NvU32 reasonMask;
} RUSD_CLK_THROTTLE_REASON;
typedef struct RUSD_MEM_ERROR_COUNTS {
NvU64 correctedVolatile;
NvU64 correctedAggregate;
NvU64 uncorrectedVolatile;
NvU64 uncorrectedAggregate;
} RUSD_MEM_ERROR_COUNTS;
#define RUSD_MEMORY_ERROR_TYPE_TOTAL 0
#define RUSD_MEMORY_ERROR_TYPE_DRAM 1
#define RUSD_MEMORY_ERROR_TYPE_SRAM 2
#define RUSD_MEMORY_ERROR_TYPE_COUNT 3
typedef struct RUSD_MEM_ECC {
volatile NvU64 lastModifiedTimestamp;
RUSD_MEM_ERROR_COUNTS count[RUSD_MEMORY_ERROR_TYPE_COUNT];
} RUSD_MEM_ECC;
typedef struct RUSD_POWER_LIMIT_INFO {
NvU32 requestedmW;
NvU32 enforcedmW;
} RUSD_POWER_LIMIT_INFO;
typedef struct RUSD_ENFORCED_POWER_LIMITS {
volatile NvU64 lastModifiedTimestamp;
RUSD_POWER_LIMIT_INFO info;
} RUSD_POWER_LIMITS;
typedef struct RUSD_TEMPERATURE_INFO{
NvTemp gpuTemperature;
NvTemp hbmTemperature;
} RUSD_TEMPERATURE_INFO;
typedef struct RUSD_TEMPERATURE {
volatile NvU64 lastModifiedTimestamp;
RUSD_TEMPERATURE_INFO info;
} RUSD_TEMPERATURE;
typedef struct RUSD_MEM_ROW_REMAP_INFO {
NvU32 histogramMax; // No remapped row is used.
NvU32 histogramHigh; // One remapped row is used.
NvU32 histogramPartial; // More than one remapped rows are used.
NvU32 histogramLow; // One remapped row is available.
NvU32 histogramNone; // All remapped rows are used.
NvU32 correctableRows;
NvU32 uncorrectableRows;
NvBool isPending;
NvBool hasFailureOccurred;
} RUSD_MEM_ROW_REMAP_INFO;
typedef struct RUSD_MEM_ROW_REMAP {
volatile NvU64 lastModifiedTimestamp;
RUSD_MEM_ROW_REMAP_INFO info;
} RUSD_MEM_ROW_REMAP;
typedef struct RUSD_AVG_POWER_INFO {
NvU32 averageGpuPower; // mW
NvU32 averageModulePower; // mW
NvU32 averageMemoryPower; // mW
} RUSD_AVG_POWER_INFO;
typedef struct RUSD_AVG_POWER_USAGE {
volatile NvU64 lastModifiedTimestamp;
RUSD_AVG_POWER_INFO info;
} RUSD_AVG_POWER_USAGE;
typedef struct RUSD_INST_POWER_INFO {
NvU32 instGpuPower; // mW
NvU32 instModulePower; // mW
} RUSD_INST_POWER_INFO;
typedef struct RUSD_INST_POWER_USAGE {
volatile NvU64 lastModifiedTimestamp;
RUSD_INST_POWER_INFO info;
} RUSD_INST_POWER_USAGE;
typedef struct NV00DE_SHARED_DATA {
volatile NvU32 seq;
NvU32 bar1Size;
NvU32 bar1AvailSize;
NvU32 gspAssertCount;
// New data members always add to bottom
// GSP polling data section
NV_DECLARE_ALIGNED(RUSD_CLK_PUBLIC_DOMAIN_INFOS clkPublicDomainInfos, 8);
NV_DECLARE_ALIGNED(RUSD_CLK_THROTTLE_REASON clkThrottleReason, 8);
NV_DECLARE_ALIGNED(RUSD_PERF_DEVICE_UTILIZATION perfDevUtil, 8);
NV_DECLARE_ALIGNED(RUSD_MEM_ECC memEcc, 8);
NV_DECLARE_ALIGNED(RUSD_PERF_CURRENT_PSTATE perfCurrentPstate, 8);
NV_DECLARE_ALIGNED(RUSD_POWER_LIMITS powerLimitGpu, 8); // Module Limit is not supported on Ampere/Hopper
NV_DECLARE_ALIGNED(RUSD_TEMPERATURE temperature, 8);
NV_DECLARE_ALIGNED(RUSD_MEM_ROW_REMAP memRowRemap, 8);
NV_DECLARE_ALIGNED(RUSD_AVG_POWER_USAGE avgPowerUsage, 8);
NV_DECLARE_ALIGNED(RUSD_INST_POWER_USAGE instPowerUsage, 8);
} NV00DE_SHARED_DATA;
#define NV00DE_RUSD_POLL_CLOCK 0x1
#define NV00DE_RUSD_POLL_PERF 0x2
#define NV00DE_RUSD_POLL_MEMORY 0x4
#define NV00DE_RUSD_POLL_POWER 0x8
#define NV00DE_RUSD_POLL_THERMAL 0x10
typedef struct NV00DE_ALLOC_PARAMETERS {
// initialize to 0
NvU32 reserved;
NvU64 polledDataMask; // Bitmask of data to request polling at alloc time, 0 if not needed
} NV00DE_ALLOC_PARAMETERS;
#ifdef __cplusplus

65
src/common/sdk/nvidia/inc/class/cl00e0.h Normal file
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@@ -0,0 +1,65 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: class/cl00e0.finn
//
#include "nvcfg_sdk.h"
#include "cl0080.h"
#define NV_MEMORY_EXPORT (0xe0U) /* finn: Evaluated from "NV00E0_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV_MEM_EXPORT_UUID_LEN 16
#define NV_MEM_EXPORT_PACKET_LEN 32
#define NV_MEM_EXPORT_METADATA_LEN 64
typedef struct NV_EXPORT_MEM_PACKET {
NvU8 uuid[NV_MEM_EXPORT_UUID_LEN];
NvU8 opaque[16];
} NV_EXPORT_MEM_PACKET;
#define NV_MEM_EXPORT_FLAGS_DEFAULT 0x00000000
#define NV_MEM_EXPORT_FLAGS_DUP_BY_UUID 0x00000001
#define NV00E0_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00e0U)
typedef struct NV00E0_ALLOCATION_PARAMETERS {
NvU32 imexChannel;
NV_EXPORT_MEM_PACKET packet;
NvU16 numMaxHandles;
NvU32 flags;
NvU8 metadata[NV_MEM_EXPORT_METADATA_LEN];
NvU32 deviceInstanceMask;
NvU32 giIdMasks[NV_MAX_DEVICES];
NvU16 numCurHandles;
} NV00E0_ALLOCATION_PARAMETERS;

20
src/common/sdk/nvidia/inc/class/cl00fd.h
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@@ -34,7 +34,10 @@
// Source file: class/cl00fd.finn
//
#define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#include "cl00e0.h"
#define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */
/*
* alignment [IN]
@@ -48,8 +51,7 @@
* Requested page size. Can be any of the NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_*
*
* allocFlags [IN]
* Reserved for future use
* Clients should pass 0 as of now.
* Should be one of NV_MEMORY_MULTICAST_FABRIC_ALLOC_FLAGS_*
*
* numGpus [IN]
* Number of unique GPUs to be attached.
@@ -58,16 +60,20 @@
* Optional OS event handle created with NvRmAllocOsEvent().
*/
#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M 0x20000000
#define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M 0x20000000
#define NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00fdU)
typedef struct NV00FD_ALLOCATION_PARAMETERS {
NV_EXPORT_MEM_PACKET expPacket;
NvU16 index;
NV_DECLARE_ALIGNED(NvU64 alignment, 8);
NV_DECLARE_ALIGNED(NvU64 allocSize, 8);
NvU32 pageSize;
NvU32 allocFlags;
NvU32 numGpus;
NvU32 pageSize;
NvU32 allocFlags;
NvU32 numGpus;
NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8);
} NV00FD_ALLOCATION_PARAMETERS;

57
src/common/sdk/nvidia/inc/class/cl2080_notification.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,10 +24,14 @@
#ifndef _cl2080_notification_h_
#define _cl2080_notification_h_
#include "nvcfg_sdk.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "nvcfg_sdk.h"
/* event values */
#define NV2080_NOTIFIERS_SW (0)
#define NV2080_NOTIFIERS_HOTPLUG (1)
@@ -187,6 +191,7 @@ extern "C" {
#define NV2080_NOTIFIERS_GR6 (151)
#define NV2080_NOTIFIERS_GR7 (152)
#define NV2080_NOTIFIERS_OFA (153)
#define NV2080_NOTIFIERS_OFA0 NV2080_NOTIFIERS_OFA
#define NV2080_NOTIFIERS_DSTATE_HDA (154)
#define NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL (155)
#define NV2080_NOTIFIERS_POISON_ERROR_FATAL (156)
@@ -199,18 +204,31 @@ extern "C" {
#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163)
#define NV2080_NOTIFIERS_POSSIBLE_ERROR (164)
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165)
#define NV2080_NOTIFIERS_RESERVED166 (166)
#define NV2080_NOTIFIERS_RESERVED167 (167)
#define NV2080_NOTIFIERS_RESERVED168 (168)
#define NV2080_NOTIFIERS_RESERVED169 (169)
#define NV2080_NOTIFIERS_RESERVED170 (170)
#define NV2080_NOTIFIERS_RESERVED171 (171)
#define NV2080_NOTIFIERS_RESERVED172 (172)
#define NV2080_NOTIFIERS_RESERVED173 (173)
#define NV2080_NOTIFIERS_RESERVED174 (174)
#define NV2080_NOTIFIERS_RESERVED175 (175)
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176)
#define NV2080_NOTIFIERS_NVPCF_EVENTS (177)
#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (178)
#define NV2080_NOTIFIERS_VRR_SET_TIMEOUT (179)
#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (180)
#define NV2080_NOTIFIERS_MAXCOUNT (181)
#define NV2080_NOTIFIERS_RESERVED180 (180)
#define NV2080_NOTIFIERS_AUX_POWER_EVENT (181)
#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (182)
#define NV2080_NOTIFIERS_MAXCOUNT (183)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))
#define NV2080_NOTIFIERS_GR_IDX(x) ((x) - NV2080_NOTIFIERS_GR0)
#define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7)))
// Indexed CE notifier reference
#define NV2080_NOTIFIERS_CE(x) (NV2080_NOTIFIERS_CE0 + (x))
#define NV2080_NOTIFIERS_CE_IDX(x) ((x) - NV2080_NOTIFIERS_CE0)
#define NV2080_NOTIFIER_TYPE_IS_CE(x) (((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9))
@@ -228,6 +246,11 @@ extern "C" {
#define NV2080_NOTIFIERS_NVJPEG_IDX(x) ((x) - NV2080_NOTIFIERS_NVJPEG0)
#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7))
// Indexed OFA notifier reference
#define NV2080_NOTIFIERS_OFAn(x) ((x == 0) ? (NV2080_NOTIFIERS_OFA0) : (NV2080_NOTIFIERS_MAXCOUNT))
#define NV2080_NOTIFIERS_OFA_IDX(x) ((x == NV2080_NOTIFIERS_OFA0) ? (0) : (-1))
#define NV2080_NOTIFIER_TYPE_IS_OFA(x) (((x) == NV2080_NOTIFIERS_OFA0))
#define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT + (pin))
#define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT + (pin))
@@ -295,14 +318,34 @@ extern "C" {
#define NV2080_ENGINE_TYPE_NVJPEG6 (0x00000031)
#define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032)
#define NV2080_ENGINE_TYPE_OFA (0x00000033)
#define NV2080_ENGINE_TYPE_LAST (0x0000003e)
#define NV2080_ENGINE_TYPE_OFA0 NV2080_ENGINE_TYPE_OFA
#define NV2080_ENGINE_TYPE_RESERVED34 (0x00000034)
#define NV2080_ENGINE_TYPE_RESERVED35 (0x00000035)
#define NV2080_ENGINE_TYPE_RESERVED36 (0x00000036)
#define NV2080_ENGINE_TYPE_RESERVED37 (0x00000037)
#define NV2080_ENGINE_TYPE_RESERVED38 (0x00000038)
#define NV2080_ENGINE_TYPE_RESERVED39 (0x00000039)
#define NV2080_ENGINE_TYPE_RESERVED3a (0x0000003a)
#define NV2080_ENGINE_TYPE_RESERVED3b (0x0000003b)
#define NV2080_ENGINE_TYPE_RESERVED3c (0x0000003c)
#define NV2080_ENGINE_TYPE_RESERVED3d (0x0000003d)
#define NV2080_ENGINE_TYPE_RESERVED3e (0x0000003e)
#define NV2080_ENGINE_TYPE_LAST (0x0000003f)
#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff)
#define NV2080_ENGINE_TYPE_COPY_SIZE 10
//
// NV2080_ENGINE_TYPE_COPY_SIZE is now defined as the maximum possible CE size.
// It does not reflect the max supported NV2080_ENGINE_TYPE_COPY counts. Bug 3713687 #90.
// It needs to use NV2080_ENGINE_TYPE_IS_COPY() to check if a CE is valid when
// the clients try to enumerate all NV2080_ENGINE_TYPE_COPYs.
//
#define NV2080_ENGINE_TYPE_COPY_SIZE 64
#define NV2080_ENGINE_TYPE_NVENC_SIZE 3
#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8
#define NV2080_ENGINE_TYPE_NVDEC_SIZE 8
#define NV2080_ENGINE_TYPE_GR_SIZE 8
#define NV2080_ENGINE_TYPE_OFA_SIZE 1
// Indexed engines
#define NV2080_ENGINE_TYPE_COPY(i) (NV2080_ENGINE_TYPE_COPY0+(i))
@@ -325,6 +368,10 @@ extern "C" {
#define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE)))
#define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0)
#define NV2080_ENGINE_TYPE_OFAn(i) ((i == 0) ? (NV2080_ENGINE_TYPE_OFA0) : (NV2080_ENGINE_TYPE_LAST))
#define NV2080_ENGINE_TYPE_IS_OFA(i) (((i) == NV2080_ENGINE_TYPE_OFA0))
#define NV2080_ENGINE_TYPE_OFA_IDX(i) ((i == NV2080_ENGINE_TYPE_OFA0) ? (0) : (-1))
#define NV2080_ENGINE_TYPE_IS_VALID(i) (((i) > (NV2080_ENGINE_TYPE_NULL)) && ((i) < (NV2080_ENGINE_TYPE_LAST)))
/* exported client defines */

11
src/common/sdk/nvidia/inc/class/cl503b.h
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@@ -37,13 +37,14 @@
#define NV503B_FLAGS_P2P_TYPE_GPA 0
#define NV503B_FLAGS_P2P_TYPE_SPA 1
/*
/*
* NV503B_BAR1_P2P_DMA_INFO
*
* The DMA information for BAR1 P2P, it is only valid for BAR1 P2P.
* dma_address will be set to NV_U64_MAX and dma_size will be set to 0
* when the DMA info is not available.
*
* The DMA information for BAR1 P2P.
* The default value for dma_address is NV_U64_MAX and dma_size is 0.
* This BAR1 P2P DMA information is only valid for the kernel-privileged clients.
* For unprivileged clients, all fields will be the default values.
*
*/
typedef struct NV503B_BAR1_P2P_DMA_INFO {
NV_DECLARE_ALIGNED(NvU64 dma_address, 8);

121
src/common/sdk/nvidia/inc/class/cl90cdvideo.h Normal file
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@@ -0,0 +1,121 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl90cdvideo_h_
#define _cl90cdvideo_h_
/* This file defines parameters for FECS context switch events*/
#define NV_EVENT_BUFFER_VIDEO_VERSION 1
#define NV_EVENT_BUFFER_VIDEO_TAG_ENGINE_START 0x00
#define NV_EVENT_BUFFER_VIDEO_TAG_ENGINE_END 0x01
#define NV_EVENT_BUFFER_VIDEO_TAG_PSTATE_CHANGE 0x02
#define NV_EVENT_BUFFER_VIDEO_TAG_LOG_DATA 0x03
#define NV_EVENT_BUFFER_VIDEO_TAG_LAST NV_EVENT_BUFFER_VIDEO_TAG_LOG_DATA
#define NV_EVENT_BUFFER_VIDEO_BITMASK_TAG_ENGINE_START NVBIT(NV_EVENT_BUFFER_VIDEO_TAG_ENGINE_START)
#define NV_EVENT_BUFFER_VIDEO_BITMASK_TAG_ENGINE_END NVBIT(NV_EVENT_BUFFER_VIDEO_TAG_ENGINE_END)
#define NV_EVENT_BUFFER_VIDEO_BITMASK_TAG_PSTATE_CHANGE NVBIT(NV_EVENT_BUFFER_VIDEO_TAG_PSTATE_CHANGE)
#define NV_EVENT_BUFFER_VIDEO_BITMASK_TAG_LOG_DATA NVBIT(NV_EVENT_BUFFER_VIDEO_TAG_LOG_DATA)
/* context_id is set to this value if fecs info doesn't match a known channel/tsg handle*/
#define NV_EVENT_BUFFER_VIDEO_INVALID_CONTEXT 0xFFFFFFFF
/*
* PID/context_id are set to these values if the data is from another user's
* client and the current user is not an administrator
*/
#define NV_EVENT_BUFFER_VIDEO_HIDDEN_PID 0x0
#define NV_EVENT_BUFFER_VIDEO_HIDDEN_CONTEXT 0x0
/*
* PID/context_id are set to these values if the data is from a kernel client
* and the data is being read by a user client
*/
#define NV_EVENT_BUFFER_VIDEO_KERNEL_PID 0xFFFFFFFF
#define NV_EVENT_BUFFER_VIDEO_KERNEL_CONTEXT 0xFFFFFFFF
typedef enum
{
NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__NVDEC = 0,
NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__NVENC,
NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__NVJPEG,
NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__OFA,
NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__LAST = NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE__OFA,
} NV_EVENT_BUFFER_VIDEO_ENGINE_TYPE;
typedef enum
{
NV_EVENT_BUFFER_VIDEO_CODEC_ID__MPEG2 = 0,
NV_EVENT_BUFFER_VIDEO_CODEC_ID__VC1,
NV_EVENT_BUFFER_VIDEO_CODEC_ID__H264,
NV_EVENT_BUFFER_VIDEO_CODEC_ID__MPEG4,
NV_EVENT_BUFFER_VIDEO_CODEC_ID__VP8,
NV_EVENT_BUFFER_VIDEO_CODEC_ID__VP9,
NV_EVENT_BUFFER_VIDEO_CODEC_ID__HEVC,
NV_EVENT_BUFFER_VIDEO_CODEC_ID__AVD,
NV_EVENT_BUFFER_VIDEO_CODEC_ID__LAST = NV_EVENT_BUFFER_VIDEO_CODEC_ID__AVD,
} NV_EVENT_BUFFER_VIDEO_ENGINE_CODEC_ID;
// V1 ------------------------------------------------------------------------
typedef struct
{
NvU8 event_id; ///< NV_EVENT_BUFFER_VIDEO_TAG_*
NvU8 vmid;
NvU16 seqno;
NvU32 context_id; ///< channel/tsg handle
NvU64 pid NV_ALIGN_BYTES(8); ///< process id
NvU64 timestamp NV_ALIGN_BYTES(8);
NvU64 api_id NV_ALIGN_BYTES(8);
union
{
NvU64 event_data;
struct
{
NvU8 engine_type;
NvU8 engine_id;
NvU16 codec_id;
NvU32 status;
} session;
struct
{
NvU16 from;
NvU16 to;
} stateChange;
struct
{
NvU8 engine_type;
NvU8 engine_id;
NvU16 codec_id;
NvU32 size;
} logData;
};
} NV_EVENT_BUFFER_VIDEO_RECORD_V1;
typedef NV_EVENT_BUFFER_VIDEO_RECORD_V1 NV_EVENT_BUFFER_VIDEO_RECORD;
#endif /* _cl90cdvideo_h_ */

38
src/common/sdk/nvidia/inc/class/cl90e7.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl90e7_h_
#define _cl90e7_h_
#ifdef __cplusplus
extern "C" {
#endif
#define GF100_SUBDEVICE_INFOROM (0x000090e7)
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif // _cl90e7_h

2
src/common/sdk/nvidia/inc/class/cla084.h
View File

@@ -54,6 +54,7 @@
* numGuestFbHandles -> number of guest memory handles, the client handle is hPluginClient
* guestFbHandleList -> handle list to guest memory
* hPluginHeapMemory -> plugin heap memory handle, the client handle is hPluginClient
* hMigRmHeapMemory -> MIG-RM heap memory handle
* bDeviceProfilingEnabled -> If set to true, profiling is allowed
*/
#define NVA084_ALLOC_PARAMETERS_MESSAGE_ID (0xa084U)
@@ -74,6 +75,7 @@ typedef struct NVA084_ALLOC_PARAMETERS {
NvU32 numGuestFbHandles;
NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS];
NvHandle hPluginHeapMemory;
NvHandle hMigRmHeapMemory;
NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8);

4
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -179,5 +179,7 @@ typedef struct NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS {
NvBool bDuplicates; /* [out] - Returns true if duplicates */
} NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS;
/* _ctrl0000client_h_ */

48
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
View File

@@ -979,5 +979,53 @@ typedef struct NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS {
NvU8 mode;
} NV0000_CTRL_GPU_GET_NVLINK_BW_MODE_PARAMS;
/*
* NV0000_CTRL_GPU_ACTIVE_DEVICE
*
* This structure describes a single MIG or plain device in the system
* available for use.
*
* gpuId
* ID of an attached GPU.
* gpuInstanceId
* MIG gpu instance id of an instance existing on this GPU.
* NV0000_CTRL_GPU_INVALID_ID if the GPU is not in MIG mode.
* computeInstanceId
* MIG compute instance id of an instance existing on this GPU.
* NV0000_CTRL_GPU_INVALID_ID if the GPU is not in MIG mode.
*
*/
typedef struct NV0000_CTRL_GPU_ACTIVE_DEVICE {
NvU32 gpuId;
NvU32 gpuInstanceId;
NvU32 computeInstanceId;
} NV0000_CTRL_GPU_ACTIVE_DEVICE;
/*
* NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS
*
* This command returns a list of valid GPUs treating uniformly MIG devices
* and GPUs not in MIG mode.
*
* [out] devices
* List of devices aviable for use.
* [out] numDevices
* Number of valid entries in gpus
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_GPU_GET_ACTIVE_DEVICE_IDS (0x288U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES 256U
#define NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS_MESSAGE_ID (0x88U)
typedef struct NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS {
NvU32 numDevices;
NV0000_CTRL_GPU_ACTIVE_DEVICE devices[NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES];
} NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS;
/* _ctrl0000gpu_h_ */

71
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -65,14 +65,21 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS {
/* Valid feature values */
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI 1:1
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING 3:3
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE (0x00000001U)
/*
* NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION
*
@@ -103,7 +110,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U)
@@ -260,6 +267,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011U)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012U)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013U)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_XEON_SPR (0x00000014U)
/* AMD types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030U)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031U)
@@ -432,6 +440,45 @@ typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS {
NvU32 memorySize;
} NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES
*
* This command is used to retrieve the measured times spent holding and waiting for
* the main RM locks (API and GPU).
*
* waitApiLock
* Total time spent by RM API's waiting to acquire the API lock
*
* holdRoApiLock
* Total time spent by RM API's holding the API lock in RO mode.
*
* holdRwApiLock
* Total time spent by RM API's holding the API lock in RW mode.
*
* waitGpuLock
* Total time spent by RM API's waiting to acquire one or more GPU locks.
*
* holdGpuLock
* Total time spent by RM API's holding one or more GPU locks.
*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES (0x109U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS {
NV_DECLARE_ALIGNED(NvU64 waitApiLock, 8);
NV_DECLARE_ALIGNED(NvU64 holdRoApiLock, 8);
NV_DECLARE_ALIGNED(NvU64 holdRwApiLock, 8);
NV_DECLARE_ALIGNED(NvU64 waitGpuLock, 8);
NV_DECLARE_ALIGNED(NvU64 holdGpuLock, 8);
} NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST
*
@@ -2072,16 +2119,16 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
NvU32 subFunc;
/* Configurable TGP offset, in mW */
NvU32 ctgpOffsetmW;
NvS32 ctgpOffsetmW;
/* TPP, as offset in mW */
NvU32 targetTppOffsetmW;
NvS32 targetTppOffsetmW;
/* Maximum allowed output, as offset in mW */
NvU32 maxOutputOffsetmW;
NvS32 maxOutputOffsetmW;
/* Minimum allowed output, as offset in mW */
NvU32 minOutputOffsetmW;
NvS32 minOutputOffsetmW;
/* The System Controller Table Version */
NvU8 version;

9
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h
View File

@@ -225,6 +225,10 @@ typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS {
* NV_MAX_DEVICES is returned if the object is parented by a client instead
* of a device.
*
* gpuInstanceId
* For objects parented by device this parameter returns MIG GPU instance
* id the device is subscribed to or NV_U32_MAX if no subscription was made.
*
* maxObjects
* This parameter returns the maximum number of object handles that may be
* contained in the file descriptor.
@@ -246,9 +250,10 @@ typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS {
#define NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS {
NvS32 fd; /* IN */
NvS32 fd; /* IN */
NvU32 deviceInstance; /* OUT */
NvU16 maxObjects; /* OUT */
NvU32 gpuInstanceId; /* OUT */
NvU16 maxObjects; /* OUT */
NvU8 metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* OUT */
} NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS;

6
src/common/sdk/nvidia/inc/ctrl/ctrl0041.h
View File

@@ -238,6 +238,12 @@ typedef NVXXXX_CTRL_XXX_INFO NV0041_CTRL_SURFACE_INFO;
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_PROTECT NVOS32_ATTR_COHERENCY_WRITE_PROTECT
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_CPU_COHERENCY_WRITE_BACK NVOS32_ATTR_COHERENCY_WRITE_BACK
/* Valid surface info format */
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT NVOS32_ATTR_FORMAT
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT_PITCH NVOS32_ATTR_FORMAT_PITCH
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT_SWIZZLED NVOS32_ATTR_FORMAT_SWIZZLED
#define NV0041_CTRL_SURFACE_INFO_PHYS_ATTR_FORMAT_BLOCK_LINEAR NVOS32_ATTR_FORMAT_BLOCK_LINEAR
/*
* NV0041_CTRL_CMD_GET_SURFACE_INFO
*

36
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -107,8 +107,8 @@
* This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode).
* NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE
* This indicates whether this DFP supports Dynamic MUX
* flags2
* This parameter returns the extra information specific to this dfp.
* UHBRSupportedByDfp
* Bitmask to specify the UHBR link rates supported by this dfp.
*
* Possible status values returned are:
* NV_OK
@@ -123,7 +123,7 @@ typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 flags;
NvU32 flags2;
NvU32 UHBRSupportedByDfp;
} NV0073_CTRL_DFP_GET_INFO_PARAMS;
/* valid display types */
@@ -942,6 +942,10 @@ typedef struct NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS {
#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING 2:2
#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_KNOWN 0x00000000
#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_MUX_SWITCH_IGPU_POWER_TIMING_UNKNOWN 0x00000001
#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE 3:3
#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE_NO 0x00000000U
#define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE_YES 0x00000001U
#define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MIN 0U
#define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MAX 100U
@@ -1231,13 +1235,23 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS {
* Pixel clock frequency in KHz
* rrx1k (out)
* Refresh rate in units of 0.001Hz
* x (out)
* x offset inside superframe at which this view starts
* y (out)
* y offset inside superframe at which this view starts
* width (out)
* Horizontal active width in pixels for this view
* height (out)
* Vertical active height in lines for this view
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */
#define NV0073_CTRL_CMD_DFP_GET_FIXED_MODE_TIMING (0x731172) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8 | NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID)" */
#define NV0073_CTRL_DFP_FIXED_MODE_TIMING_MAX_SUPERFRAME_VIEWS 4U
#define NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS_MESSAGE_ID (0x72U)
@@ -1260,6 +1274,18 @@ typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS {
NvU32 pclkKHz;
NvU32 rrx1k;
struct {
NvU8 numViews;
struct {
NvU16 x;
NvU16 y;
NvU16 width;
NvU16 height;
} view[NV0073_CTRL_DFP_FIXED_MODE_TIMING_MAX_SUPERFRAME_VIEWS];
} superframeInfo;
} NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS;
/* _ctrl0073dfp_h_ */

292
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1394,6 +1394,12 @@ typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS {
* linkBW
* The BW of each lane that the DP transmitter hardware is set up to drive.
* The values returned will be according to the DP specifications.
* dp2LinkBW
* Current BW of each lane that the DP transmitter hardware is set up to drive is UHBR.
* The values returned will be using 10M convention.
*
* Note:
* linkBW and dp2LinkBw are mutual exclusive. Only one of the value will be non-zero.
*
*/
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG (0x731360U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS_MESSAGE_ID" */
@@ -1405,16 +1411,37 @@ typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS {
NvU32 displayId;
NvU32 laneCount;
NvU32 linkBW;
NvU32 dp2LinkBW;
} NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS;
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT 3:0
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_0 (0x00000000U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_1 (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_2 (0x00000002U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_4 (0x00000004U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_0 (0x00000000U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_1 (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_2 (0x00000002U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LANE_COUNT_4 (0x00000004U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW 3:0
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_1_62GBPS (0x00000006U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_70GBPS (0x0000000aU)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_1_62GBPS (0x00000006U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_70GBPS (0x0000000aU)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_5_40GBPS (0x00000014U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_8_10GBPS (0x0000001EU)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_16GBPS (0x00000008U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_2_43GBPS (0x00000009U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_3_24GBPS (0x0000000CU)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_4_32GBPS (0x00000010U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_LINK_BW_6_75GBPS (0x00000019U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW 15:0
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_1_62GBPS (0x000000A2U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_2_70GBPS (0x0000010EU)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_5_40GBPS (0x0000021CU)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_8_10GBPS (0x0000032AU)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_2_16GBPS (0x000000D8U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_2_43GBPS (0x000000F3U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_3_24GBPS (0x00000114U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_4_32GBPS (0x000001B0U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_6_75GBPS (0x000002A3U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_10_0GBPS (0x000003E8U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_13_5GBPS (0x00000546U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_20_0GBPS (0x000007D0U)
/*
* NV0073_CTRL_CMD_DP_GET_EDP_DATA
@@ -1455,7 +1482,7 @@ typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS {
* NV0073_CTRL_DP_GET_EDP_DATA_DPCD_SET_POWER_D3
* This eDP panel is current standby.
*/
#define NV0073_CTRL_CMD_DP_GET_EDP_DATA (0x731361U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP_GET_EDP_DATA (0x731361U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP_GET_EDP_DATA_PARAMS_MESSAGE_ID (0x61U)
@@ -1751,6 +1778,8 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
* Specifies the SOR index.
* dpVersionsSupported
* Specified the DP versions supported by the GPU
* UHBRSupportedByGpu
* Bitmask to specify the UHBR link rates supported by the GPU.
* bIsMultistreamSupported
* Returns NV_TRUE if MST is supported by the GPU else NV_FALSE
* bIsSCEnabled
@@ -1787,7 +1816,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
NvU32 sorIndex;
NvU32 maxLinkRate;
NvU32 dpVersionsSupported;
NvU32 UHBRSupported;
NvU32 UHBRSupportedByGpu;
NvBool bIsMultistreamSupported;
NvBool bIsSCEnabled;
NvBool bHasIncreasedWatermarkLimits;
@@ -2212,7 +2241,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_AUXLOGGER_BUFFER_DATA_PARAMS {
* linkRateTbl
* Link rates in 200KHz as native granularity from eDP 1.4
* linkBwTbl
* Link rates in 270MHz and valid for client to apply to
* Link rates valid for client to apply to
* linkBwCount
* Total valid link rates
*
@@ -2235,7 +2264,7 @@ typedef struct NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS {
NvU16 linkRateTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES];
// Out
NvU8 linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES];
NvU16 linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES];
NvU8 linkBwCount;
} NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS;
@@ -2786,4 +2815,245 @@ typedef struct NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS {
NvU16 manfId;
NvU16 prodId;
} NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS;
/*
* NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL
*
* This command is used to trigger link training on DP2.x device with 128b132b channel encoding.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
*
* displayId
* This parameter specifies the ID of the display for which the dfp
* caps should be returned. The display ID must a dfp display.
* If more than one displayId bit is set or the displayId is not a dfp,
* this call will return NV_ERR_INVALID_ARGUMENT.
*
* cmd
* This parameter is an input to this command.
* Here are the current defined fields:
* 1.Ask RM to enter specific stage
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CHNL_EQ
* _CDS
* _SET_* only valid if _SETTING_TRUE
*
* 2.Ask RM to check the completion of specific stage
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING
* NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_DONE
* _CHNL_EQ_INTERLANE_ALIGN
* _CDS
* _POLL_* only valid if _POLLING_TRUE
*
* _SETTING_TRUE and _POLLING_TRUE are mutual exclusive.
* RM will return NV_ERR_INVALID_ARGUMENT if both bit are set.
*
* 3.Downspread configuration
* NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD
* Specifies whether RM should be forced to enable or disable the DP
* Downspread setting. This can be used along with the Fake link
* training option so that we can configure the GPU to enable/disable
* spread when a real display is not connected.
*
* NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_NO (default behavior)
* RM will enable Downspread when the display supports it.
* NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_YES
* RM will enable/disable Downspread according to _SET_DOWNSPREAD field.
*
* NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD
* Specifies if RM should enable or disable downspread.
* Only valid when _FORCED_DOWNSPREAD is set to _YES
*
* NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_ENABLE
* RM will enable Downspread even if the display does not support it.
* NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_DISABLE
* RM will not enable Downspread even if the display does support it.
*
* 4.NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING
* This field specifies if fake link training is to be done. This will
* program enough of the hardware to avoid any hardware hangs and
* depending upon option chosen by the client, OR will be enabled for
* transmisssion.
*
* NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_NO
* No Fake LT will be performed
* NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION
* SOR will be not powered up during Fake LT
* NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON
* SOR will be powered up during Fake LT
*
* 5.NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG
*
* 6.NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING
* Specifies whether RM should skip HW training of the link.
* If this is the case then RM only updates its SW state without actually
* touching any HW registers. Clients should use this ONLY if it has determined -
* a. link is trained and not lost
* b. desired link config is same as current trained link config
* c. link is not in D3 (should be in D0)
*
* NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_NO
* RM doesn't skip HW LT as the current Link Config is not the same as the
* requested Link Config.
* NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_YES
* RM skips HW LT and only updates its SW state as client has determined that
* the current state of the link and the requested Link Config is the same.
* data
* This parameter is an input and output to this command.
* Here are the current defined fields:
* NV0073_CTRL_DP2X_DATA_LANE_COUNT
* Valid values: 0, 1, 2, 4
* NV0073_CTRL_DP2X_DATA_LINK_BW
* Valid values: all standard link rates defined in DP2.x and ILRs defined in eDP spec.
*
* pollingInfo
* This parameter is an output to this command.
* Here are the current defined fields:
*
* NV0073_CTRL_DP2X_POLLING_INFO_CHNL_EQ_INTERVAL
* For Channel equalization, the polling interval is defined in DPCD 0x2216.
* RM report to DPLib when _SET_STAGE is set to _CHNL_EQ.
* (For CDS stage, the polling interval is fixed at 3ms.)
*
* NV0073_CTRL_DP2X_POLLING_INFO_RESULT
* _DONE: if the specified stage is done.
* _PENDING: if the specified stage is still pending.
*
* err
* This parameter specifies provides info regarding the outcome
* of this calling control call. If zero, no errors were found.
* Otherwise, this parameter will specify the error detected.
* The valid parameter is broken down as follows:
* NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_DONE
* If set to _ERR, link training failed at channel equalization phase.
* NV0073_CTRL_DP2X_ERR_CDS_DONE
* If set to _ERR, link training failed at CDS phase.
* NV0073_CTRL_DP2X_ERR_TIMEOUT
* If set to _ERR, link training failed because of timeout.
* NV0073_CTRL_DP2X_ERR_LT_FAILED
* If set to _ERR, link training failed.
* NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER
* If set to _ERR, link configuration or displayID is invalid.
* NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT
* If set to _ERR, link training failed when setting lane count.
* NV0073_CTRL_DP2X_ERR_SET_LINK_BW
* If set to _ERR, link training failed when setting link rate.
* NV0073_CTRL_DP2X_ERR_ENABLE_FEC
* If set to _ERR, link training failed when enabling FEC.
* NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR
* If set to _ERR, link training failed when setting LTTPR.
* NV0073_CTRL_DP2X_ERR_PRE_LT
* If set to _ERR, link training failed before link training start.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NVOS_STATUS_ERROR
*/
#define NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL (0x731383U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS_MESSAGE_ID (0x83U)
typedef struct NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 cmd;
NvU32 data;
NvU32 pollingInfo;
NvU32 err;
} NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS;
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING 0:0
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING_FALSE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING_TRUE (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET 1:1
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CHNL_EQ (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CDS (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING 8:8
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING_FALSE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING_TRUE (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL 10:9
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_DONE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_INTERLANE_ALIGN (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CDS (0x00000002U)
// Flags for link training.
#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD 16:16
#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_NO (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_YES (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD 17:17
#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_DISABLE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_ENABLE (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING 18:18
#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING 20:19
#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_NO (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U)
#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U)
#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG 21:21
#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG_FALSE (0x00000000U)
#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG_TRUE (0x00000001U)
// Basic Data for Link training: Lane count and bandwidth.
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT 3:0
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_0 (0x00000000U)
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_1 (0x00000001U)
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_2 (0x00000002U)
#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_4 (0x00000004U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW 7:4
#define NV0073_CTRL_DP2X_DATA_LINK_BW_1_62GBPS (0x00000001U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_16GBPS (0x00000002U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_43GBPS (0x00000003U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_70GBPS (0x00000004U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_3_24GBPS (0x00000005U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_4_32GBPS (0x00000006U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_5_40GBPS (0x00000007U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_6_75GBPS (0x00000008U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_8_10GBPS (0x00000009U)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR10_0 (0x0000000AU)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR13_5 (0x0000000BU)
#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR20_0 (0x0000000CU)
#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ 0:0
#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_DONE (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_FAILED (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_CDS 1:1
#define NV0073_CTRL_DP2X_ERR_CDS_DONE (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_CDS_FAILED (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_TIMEOUT 2:2
#define NV0073_CTRL_DP2X_ERR_TIMEOUT_NO (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_TIMEOUT_YES (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_LT_FAILED 3:3
#define NV0073_CTRL_DP2X_ERR_LT_FAILED_NO (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_LT_FAILED_YES (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER 4:4
#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT 5:5
#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW 6:6
#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC 7:7
#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR 8:8
#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_ERR_PRE_LT 9:9
#define NV0073_CTRL_DP2X_ERR_PRE_LT_NOERR (0x00000000U)
#define NV0073_CTRL_DP2X_ERR_PRE_LT_ERR (0x00000001U)
#define NV0073_CTRL_DP2X_POLLING_INFO_CHNL_EQ_INTERVAL 7:0
#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT 31:31
#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT_PENDING (0x00000001U)
#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT_DONE (0x00000000U)
/* _ctrl0073dp_h_ */

11
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
View File

@@ -1164,7 +1164,12 @@ typedef struct NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS {
* The backlight brightness in the range [0,100], inclusive. This
* is an input for SET_BACKLIGHT_BRIGHTNESS, and an output for
* GET_BACKLIGHT_BRIGHTNESS.
*
* brightnessType
* This can take in one of the three parameters:
* NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT100(for percentage brightness with value calibrated to 100 scale),
* NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT1000(for percentage brightness with uncalibrated values),
* NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_NITS(used when panel supports Nits based)
* based on the brightness control method to be used.
*
* Possible status values returned include:
* NV_OK
@@ -1180,7 +1185,11 @@ typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS {
NvU32 displayId;
NvU32 brightness;
NvBool bUncalibrated;
NvU8 brightnessType;
} NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS;
#define NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT100 1
#define NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_PERCENT1000 2
#define NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_TYPE_NITS 3
#define NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID (0x91U)

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

1
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h
View File

@@ -162,6 +162,7 @@ typedef struct NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS {
NvU32 backingStoreCbcBase;
NvU32 comptaglineAllocationPolicy;
NV_DECLARE_ALIGNED(NvU64 privRegionStartOffset, 8);
NvU32 cbcCoveragePerSlice;
} NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS;
#define NV0080_CTRL_CMD_FB_GET_COMPBIT_STORE_INFO_ADDRESS_SPACE_UNKNOWN 0 // ADDR_UNKNOWN

6
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
View File

@@ -465,7 +465,10 @@ typedef struct NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS {
* bClientRmAllocatedCtxBuffer
* Flag for whether engine ctx buffer is managed by client RM.
*
* Possible status values returned are:
* bNonPowerOf2ChannelCountSupported
* Flag for whether non power of 2 VF channels are supported.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
@@ -490,6 +493,7 @@ typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
NvBool bSriovHeavyEnabled;
NvBool bEmulateVFBar0TlbInvalidationRegister;
NvBool bClientRmAllocatedCtxBuffer;
NvBool bNonPowerOf2ChannelCountSupported;
} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS;

7
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
View File

@@ -153,13 +153,16 @@ typedef NVXXXX_CTRL_XXX_INFO NV0080_CTRL_GR_INFO;
#define NV0080_CTRL_GR_INFO_INDEX_DUMMY (0x00000033)
#define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000034)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES (0x00000035)
#define NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS (0x00000036)
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG (0x00000037)
/* When adding a new INDEX, please update MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
* reflects that.
*/
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000034)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x35) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000037)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x38) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
/*
* NV0080_CTRL_CMD_GR_GET_INFO

57
src/common/sdk/nvidia/inc/ctrl/ctrl00de.h Normal file
View File

@@ -0,0 +1,57 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl00de.finn
//
#include "ctrl/ctrlxxxx.h"
#define NV00DE_CTRL_CMD(cat, idx) NVXXXX_CTRL_CMD(0x00de, NV00DE_CTRL_##cat, idx)
/* RM_USER_SHARED_DATA control commands and parameters */
/*
* NV00DE_CTRL_CMD_REQUEST_DATA_POLL
*
* @brief Request some polled data elements to be updated
*
* @param[in] polledDataMask Bitmask of data to be updated
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
*/
#define NV00DE_CTRL_CMD_REQUEST_DATA_POLL (0xde0001U) /* finn: Evaluated from "(FINN_RM_USER_SHARED_DATA_INTERFACE_ID << 8) | NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS_MESSAGE_ID" */
#define NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS {
NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8);
} NV00DE_CTRL_REQUEST_DATA_POLL_PARAMS;
/* _ctrl00de.h_ */

40
src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h
View File

@@ -112,20 +112,54 @@ typedef struct NV00F8_CTRL_GET_INFO_PARAMS {
* numPfns [OUT]
* Number of valid entries in pfnArray.
*
* Note: This ctrl call is only available for kerenl mode client in vGPU platforms.
* attrs [OUT]
* Attributes associated with memory allocation.
*
* physAttrs [OUT]
* Physical attributes associated with memory allocation.
* For flexible mappings, it is not possible to retrieve this information,
* behavior is undefined (returns all zeros).
*
* memFlags [OUT]
* Flags associated with memory allocation.
*
* Note: This control call is only available for privileged clients.
*/
#define NV00F8_CTRL_CMD_DESCRIBE (0xf80102) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID" */
#define NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE 512
/*
* kind
* Kind of memory allocation.
*
* pageSize
* Page size of memory allocation.
*
* size
* Size of memory allocation
*
* cliqueId
* Clique ID of the owner GPU
*/
typedef struct NV_FABRIC_MEMORY_ATTRS {
NvU32 kind;
NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 cliqueId;
} NV_FABRIC_MEMORY_ATTRS;
#define NV00F8_CTRL_DESCRIBE_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV00F8_CTRL_DESCRIBE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NV_DECLARE_ALIGNED(NvU64 totalPfns, 8);
NvU32 pfnArray[NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE];
NvU32 numPfns;
NvU32 pfnArray[NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE];
NvU32 numPfns;
NV_DECLARE_ALIGNED(NV_FABRIC_MEMORY_ATTRS attrs, 8);
NV_PHYSICAL_MEMORY_ATTRS physAttrs;
NvU32 memFlags;
} NV00F8_CTRL_DESCRIBE_PARAMS;
/*

2
src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h
View File

@@ -202,4 +202,6 @@ typedef struct NV00FD_CTRL_DETACH_MEM_PARAMS {
NvU32 flags;
} NV00FD_CTRL_DETACH_MEM_PARAMS;
/* _ctrl00fd_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080.h
View File

@@ -78,7 +78,8 @@
#include "ctrl2080/ctrl2080grmgr.h"
#include "ctrl2080/ctrl2080ucodefuzzer.h"
#include "ctrl2080/ctrl2080vgpumgrinternal.h"
#include "ctrl2080/ctrl2080hshub.h"
/* include appropriate os-specific command header */

38
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
View File

@@ -1467,44 +1467,6 @@ typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS {
NvBool bDisable;
} NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO
*
* This command returns the C2C error info for a C2C links.
*
* errCnts[OUT]
* Array of structure that contains the error counts for
* number of times one of C2C fatal error interrupt has happened.
* The array size should be NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES
* * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE.
*
* nrCrcErrIntr[OUT]
* Number of times CRC error interrupt triggered.
* nrReplayErrIntr[OUT]
* Number of times REPLAY error interrupt triggered.
* nrReplayB2bErrIntr[OUT]
* Number of times REPLAY_B2B error interrupt triggered.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES 2
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE 5
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU)
typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS {
struct {
NvU32 nrCrcErrIntr;
NvU32 nrReplayErrIntr;
NvU32 nrReplayB2bErrIntr;
} errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE];
} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS;
/*

8
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
View File

@@ -186,7 +186,7 @@ typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS {
#define NV2080_CTRL_CMD_CE_SET_PCE_LCE_CONFIG (0x20802a04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MAX_PCES 32
#define NV2080_CTRL_MAX_GRCES 2
#define NV2080_CTRL_MAX_GRCES 4
#define NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS_MESSAGE_ID (0x4U)
@@ -323,11 +323,13 @@ typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS {
#define NV2080_CTRL_CMD_CE_GET_ALL_CAPS (0x20802a0a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_MAX_CES 64
#define NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_MESSAGE_ID (0xaU)
typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS {
NvU8 capsTbl[NV2080_CTRL_MAX_PCES][NV2080_CTRL_CE_CAPS_TBL_SIZE];
NvU32 present;
NvU8 capsTbl[NV2080_CTRL_MAX_CES][NV2080_CTRL_CE_CAPS_TBL_SIZE];
NV_DECLARE_ALIGNED(NvU64 present, 8);
} NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS;
#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */

65
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -266,6 +266,8 @@
* NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE
* Returns the ECC status size (corresponds to subpartitions or channels
* depending on architecture/memory type).
* NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB
* Returns true if FB is not present on this chip
*/
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
@@ -328,9 +330,10 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_TOTAL_KB (0x00000033U)
#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB (0x00000034U)
#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE (0x00000035U)
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000036U)
#define NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB (0x00000036U)
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000037U)
#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x35U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */
#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x36U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */
/* valid fb RAM type values */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN (0x00000000U)
@@ -2328,7 +2331,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
} NV2080_CTRL_FB_FS_INFO_QUERY;
// Max number of queries that can be batched in a single call to NV2080_CTRL_CMD_FB_GET_FS_INFO
#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 96U
#define NV2080_CTRL_FB_FS_INFO_MAX_QUERIES 120U
#define NV2080_CTRL_FB_GET_FS_INFO_PARAMS_MESSAGE_ID (0x46U)
@@ -2651,4 +2654,58 @@ typedef struct NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS {
NvU32 caps;
} NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS;
typedef struct NV2080_CTRL_CMD_FB_STATS_ENTRY {
//! Total physical memory available (accounts row-remapping)
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
//! Total reserved memory (includes both Region 1 and region 2)
NV_DECLARE_ALIGNED(NvU64 rsvdSize, 8);
//! Total usable memory (Region 0) for OS/KMD
NV_DECLARE_ALIGNED(NvU64 osSize, 8);
//! Region 1 (RM Internal) memory
NV_DECLARE_ALIGNED(NvU64 r1Size, 8);
//! Region 2 (Reserved) memory
NV_DECLARE_ALIGNED(NvU64 r2Size, 8);
//! Free memory (reserved but not allocated)
NV_DECLARE_ALIGNED(NvU64 freeSize, 8);
} NV2080_CTRL_CMD_FB_STATS_ENTRY;
typedef struct NV2080_CTRL_CMD_FB_STATS_OWNER_INFO {
//! Total allocated size for this owner
NV_DECLARE_ALIGNED(NvU64 allocSize, 8);
//! Total memory blocks belonging this owner
NvU32 numBlocks;
//! Total reserved size for this owner
NV_DECLARE_ALIGNED(NvU64 rsvdSize, 8);
} NV2080_CTRL_CMD_FB_STATS_OWNER_INFO;
#define NV2080_CTRL_CMD_FB_STATS_MAX_OWNER 200U
/*
* NV2080_CTRL_CMD_FB_STATS_GET
*
* Get the FB allocations info.
*/
#define NV2080_CTRL_CMD_FB_STATS_GET (0x2080132a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_STATS_GET_PARAMS_MESSAGE_ID (0x2AU)
typedef struct NV2080_CTRL_CMD_FB_STATS_GET_PARAMS {
//! Version id for driver and tool matching
NV_DECLARE_ALIGNED(NvU64 version, 8);
//! All sizes info
NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_STATS_ENTRY fbSizeInfo, 8);
//! Level 2 owner info table
NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_STATS_OWNER_INFO fbBlockInfo[NV2080_CTRL_CMD_FB_STATS_MAX_OWNER], 8);
} NV2080_CTRL_CMD_FB_STATS_GET_PARAMS;
/* _ctrl2080fb_h_ */

42
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -35,7 +35,7 @@
#include "nvcfg_sdk.h"
#include "nvstatus.h"
#define NV_GRID_LICENSE_INFO_MAX_LENGTH (128)
#define NV_GRID_LICENSE_INFO_MAX_LENGTH (128)
/* License info strings for vGPU products */
#define NV_GRID_LICENSE_FEATURE_VPC_EDITION "GRID-Virtual-PC,2.0;Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0"
@@ -54,11 +54,6 @@
/* NV20_SUBDEVICE_XX gpu control commands and parameters */
/* Valid feature values */
#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS 0:0
#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_FALSE (0x00000000U)
#define NV2080_CTRL_GPU_GET_FEATURES_CLK_ARCH_DOMAINS_TRUE (0x00000001U)
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
@@ -112,7 +107,10 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000040U)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U)
/* valid minor revision extended values */
#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U)
@@ -750,7 +748,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS {
#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x3EU
#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x3FU
#define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U)
@@ -1123,7 +1121,7 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS {
#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000018U)
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x00000019U)
@@ -2244,16 +2242,6 @@ typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS {
NvU8 oemInfo[NV2080_GPU_MAX_OEM_INFO_LENGTH];
} NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS;
/* NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS
*
* Complete any pending tasks the need to be run after GC6 exit is complete at OS/KMD level
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_READY
*/
#define NV2080_CTRL_CMD_GPU_PROCESS_POST_GC6_EXIT_TASKS (0x2080016aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x6A" */
/*
* NV2080_CTRL_CMD_GPU_GET_VPR_INFO
*
@@ -2286,7 +2274,7 @@ typedef struct NV2080_CTRL_GPU_GET_OEM_INFO_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GPU_GET_VPR_INFO (0x2080016bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_VPR_INFO_QUERY_TYPE {
@@ -2315,6 +2303,8 @@ typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS {
* H.264 encoding capacity on this GPU.
* 2. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC: Use this to query the
* H.265/HEVC encoding capacity on this GPU.
* 3. NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1: Use this to query the
* AV1 encoding capacity on this GPU.
*
* encoderCapacity [out]
* Encoder capacity value from 0 to 100. Value of 0x00 indicates encoder performance
@@ -2330,6 +2320,7 @@ typedef struct NV2080_CTRL_GPU_GET_VPR_INFO_PARAMS {
typedef enum NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE {
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_H264 = 0,
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_HEVC = 1,
NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_AV1 = 2,
} NV2080_CTRL_ENCODER_CAPACITY_QUERY_TYPE;
#define NV2080_CTRL_GPU_GET_ENCODER_CAPACITY_PARAMS_MESSAGE_ID (0x6CU)
@@ -2706,6 +2697,9 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS {
* validCTSIdMask[OUT]
* - Mask of CTS IDs usable by this partition, not reflecting current allocations
*
* validGfxCTSIdMask[OUT]
* - Mask of CTS IDs that contain Gfx capable Grs usable by this partition, not reflecting current allocations
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
@@ -2735,6 +2729,7 @@ typedef struct NV2080_CTRL_GPU_GET_PARTITION_INFO {
NvBool bValid;
NvBool bPartitionError;
NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8);
NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8);
} NV2080_CTRL_GPU_GET_PARTITION_INFO;
/*
@@ -4041,7 +4036,9 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
#define NV2080_GPU_FABRIC_CLUSTER_UUID_LEN 16U
#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0)
#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0)
/*!
* NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS
@@ -4070,6 +4067,8 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
* - Summary of fabric capabilities received from probe resp
* Possible values are
* NV2080_CTRL_GPU_FABRIC_PROBE_CAP_*
* fabricCliqueId[OUT]
* - Unique ID of a set of GPUs within a fabric partition that can perform P2P
*/
#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U)
@@ -4079,6 +4078,7 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
NvU8 clusterUuid[NV2080_GPU_FABRIC_CLUSTER_UUID_LEN];
NvU16 fabricPartitionId;
NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8);
NvU32 fabricCliqueId;
} NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS;
#define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */

53
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -260,6 +260,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_INDEX_DUMMY NV0080_CTRL_GR_INFO_INDEX_DUMMY
#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
#define NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES
#define NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG
/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
@@ -1276,16 +1279,24 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS {
* NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS
* struct to hand in the required info to RM
*
* pControlStructure
* This input is the kernel CPU pointer to the control structure.
* maxSlots
* Max pool slots
* hMemory
* Handle to GFX Pool memory
* offset
* Offset of the control structure in GFX Pool memory
* size
* Size of the control structure
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
NvU32 maxSlots;
NvU32 maxSlots;
NvHandle hMemory;
NvU32 offset;
NvU32 size;
} NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS;
#define NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS 64U
@@ -1301,21 +1312,27 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS {
*
* NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS
*
* pControlStructure
* This input is the kernel CPU pointer to the control structure
* numSlots
* This input indicates how many slots are being added and are contained in the slots parameter
* slots
* This input contains an array of the slots to be added to the control structure
* hMemory
* Handle to GFX Pool memory
* offset
* Offset of the control structure in GFX Pool memory
* size
* Size of the control structure
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
NvU32 numSlots;
NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS];
NvU32 numSlots;
NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS];
NvHandle hMemory;
NvU32 offset;
NvU32 size;
} NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS;
/*
@@ -1330,8 +1347,6 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS {
*
* NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS_PARAMS
*
* pControlStructure
* This input is the kernel CPU pointer to the control structure
* numSlots
* This input indicates how many slots are being removed. if
* bRemoveSpecificSlots is true, then it also indicates how many entries in
@@ -1348,16 +1363,24 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS {
* the number of slots they want removed and RM will pick up to that
* many. If there are not enough slots on the freelist to remove the
* requested amount, RM will return the number it was able to remove.
* hMemory
* Handle to GFX Pool memory
* offset
* Offset of the control structure in GFX Pool memory
* size
* Size of the control structure
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID (0x22U)
typedef struct NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
NvU32 numSlots;
NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS];
NvBool bRemoveSpecificSlots;
NvU32 numSlots;
NvU32 slots[NV2080_CTRL_GR_GFX_POOL_MAX_SLOTS];
NvBool bRemoveSpecificSlots;
NvHandle hMemory;
NvU32 offset;
NvU32 size;
} NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS;

11
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h
View File

@@ -75,9 +75,12 @@ typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS {
} NV2080_CTRL_GSP_GET_FEATURES_PARAMS;
/* Valid feature values */
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED 0:0
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000)
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001)
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED 0:0
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000)
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001)
#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED 1:1
#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_FALSE (0x00000000)
#define NV2080_CTRL_GSP_GET_FEATURES_VGPU_GSP_MIG_REFACTORING_ENABLED_TRUE (0x00000001)
/*
* NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS
@@ -95,7 +98,7 @@ typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS {
* An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to
* the "high water mark" of heap usage since GSP-RM was started.
*/
#define NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS (0x20803602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS (0x20803602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT

18
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h
View File

@@ -52,4 +52,22 @@ typedef struct NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS {
#define NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK (0x20804101) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE
*
* This command sets EC throttle mode registers
*
* ecMode
* EC Mode 0-7 to write to mode register
* status
* return status
*/
#define NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS {
NvU32 ecMode;
NvU32 status;
} NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS;
#define NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE (0x20804102) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_HSHUB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS_MESSAGE_ID" */
/* _ctrl2080hshub_h_ */

115
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -219,6 +219,23 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS {
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS
*
* Set flags for use by the video event buffer
*
* flags
* VIDEO_TRACE_FLAG__*
*
*/
#define NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS {
NvU32 flags;
} NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER
* @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS
@@ -793,37 +810,6 @@ typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS];
} NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
typedef struct NV2080_CTRL_INTERNAL_NV_RANGE {
NV_DECLARE_ALIGNED(NvU64 lo, 8);
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_INTERNAL_NV_RANGE;
/*!
* NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS
*
* This structure specifies a target swizz-id and mem_range to update
*
* swizzId[IN]
* - Targeted swizz-id for which the memRange is being set
*
* memAddrRange[IN]
* - Memory Range for given GPU instance
*/
#define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U)
typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS {
NvU32 swizzId;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8);
} NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U)
typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
/**
* Get GR PDB properties synchronized between Kernel and Physical
*
@@ -1000,6 +986,9 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS {
*
* validCTSIdMask [OUT]
* # mask of CTS IDs which can be assigned under this profile
*
* validGfxCTSIdMask [OUT]
* # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile
*/
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20
@@ -1020,6 +1009,7 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO {
NvU32 nvJpgCount;
NvU32 nvOfaCount;
NV_DECLARE_ALIGNED(NvU64 validCTSIdMask, 8);
NV_DECLARE_ALIGNED(NvU64 validGfxCTSIdMask, 8);
} NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO;
/*!
@@ -1543,6 +1533,11 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS {
#define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15
typedef struct NV2080_CTRL_INTERNAL_NV_RANGE {
NV_DECLARE_ALIGNED(NvU64 lo, 8);
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_INTERNAL_NV_RANGE;
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS {
@@ -1577,12 +1572,6 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS {
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */
/*!
* NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES
* NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES
@@ -1981,7 +1970,7 @@ typedef struct NV2080_CTRL_INTERNAL_PERF_BOOST_CLEAR_PARAMS_3X {
#define NV2080_CTRL_CMD_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO (0x20800aa2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_SKYLINES 8
#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 8
#define NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO_MAX_NON_SINGLETON_VGPCS 12
/*!
* NV2080_CTRL_INTERNAL_GRMGR_SKYLINE_INFO
* skylineVgpcSize[OUT]
@@ -2181,6 +2170,8 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS {
NvBool bPcieGen4Capable;
NvBool bIsC2CLinkUp;
NvBool bIsDeviceMultiFunction;
NvBool bGcxPmuCfgSpaceRestore;
NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8);
} NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS;
@@ -3417,20 +3408,21 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS {
} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE
* NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE
*
* This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3
*
* Possible status return values are:
* NV_OK Success
*/
#define NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_GCX_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U)
#define NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U)
typedef struct NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS {
NvBool bIsSatisfied;
} NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS;
typedef struct NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS {
NvBool bIsGC6Satisfied;
NvBool bIsGCOFFSatisfied;
} NV2080_CTRL_INTERNAL_GCX_ENTRY_PREREQUISITE_PARAMS;
/*
* This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly.
@@ -3910,4 +3902,39 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_P
NvU32 limitBattMax;
} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA
*
* @brief Initialize RM User Shared Data memory mapping on physical RM
*
* @param[in] physAddr Physical address of memdesc to link physical to kernel
* 0 to de-initialize
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
*/
#define NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID (0xFEU)
typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS {
NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
} NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA (0x20800afe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL
*
* @brief Set mask of data to be polled on physical for RUSD
*
* @param[in] polledDataMask Bitmask of data requested, defined in cl00de
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
*/
#define NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID (0xFFU)
typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS {
NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8);
} NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */
/* ctrl2080internal_h */

12
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
View File

@@ -281,6 +281,7 @@ typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD 2
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 3
#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG 4
#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0
#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1
@@ -324,6 +325,16 @@ typedef struct NV2080CtrlNocatJournalSetTag {
NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN];
} NV2080CtrlNocatJournalSetTag;
typedef struct NV2080CtrlNocatJournalRclog {
NvU32 flags;
NvU32 rclogSize; // rclog size
NvU32 rmGpuId; // RMGpuId associated with the adapter
NvU32 APIType; // API Type (dx9, dx1x, ogl, etc.)
NvU32 contextType; // Context type (OGL, DX, etc.)
NvU32 exceptType; // ROBUST_CHANNEL_* error identifier
NvU8 processImageName[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; // process image name (without path)
} NV2080CtrlNocatJournalRclog;
#define NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS {
@@ -333,6 +344,7 @@ typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS {
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8);
NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord insertData, 8);
NV2080CtrlNocatJournalSetTag tagData;
NV2080CtrlNocatJournalRclog rclog;
} nocatJournalData;
} NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS;
/* _ctr2080nvd_h_ */

89
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -2971,8 +2971,91 @@ typedef struct NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS {
NvU32 linkId;
} NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP (0x20803043U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP (0x20803043U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE 64U
/*
* Structure to store port event information
*
* portEventType
* Type of port even that occurred: NVLINK_PORT_EVENT_TYPE*
*
* gpuId
* Gpu that port event occurred on
*
* linkId
* Link id that port event occurred on
*
* time
* Platform time (nsec) when event occurred
*/
typedef struct NV2080_CTRL_NVLINK_PORT_EVENT {
NvU32 portEventType;
NvU32 gpuId;
NvU32 linkId;
NV_DECLARE_ALIGNED(NvU64 time, 8);
} NV2080_CTRL_NVLINK_PORT_EVENT;
/*
* NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS
*
* This command returns the port up and port down events that have occurred
*
* Parameters:
*
* portEventIndex [IN/OUT]
* On input: The index of the first port event at which to start reading out of the driver.
*
* On output: The index of the first port event that wasn't reported through the 'port event' array
* in this call to NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS.
*
* nextPortEventIndex[OUT]
* The index that will be assigned to the next port event that occurs.
* Users of the GET_PORT_EVENTS control call may set 'portEventIndex' to this field on initialization
* to bypass port events that have already occurred without making multiple control calls.
*
* portEventCount [OUT]
* Number of port events returned by the call. Currently, portEventCount is limited
* by NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE. In order to query all the port events, a
* client needs to keep calling the control till portEventCount is zero.
*
* bOverflow [OUT]
* True when the port event log is overflowed and no longer contains all the port
* events that have occurred, false otherwise.
*
* portEvent [OUT]
* The port event entires.
*/
#define NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID (0x44U)
typedef struct NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 portEventIndex, 8);
NV_DECLARE_ALIGNED(NvU64 nextPortEventIndex, 8);
NvU32 portEventCount;
NvBool bOverflow;
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_PORT_EVENT portEvent[NV2080_CTRL_NVLINK_PORT_EVENT_COUNT_SIZE], 8);
} NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_PORT_EVENTS (0x20803044U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_CYCLE_LINK
*
* This command cycles a link by faulting it and then retraining the link
*
* Parameters:
*
* linkId [IN]
* The link id of the link to be cycled
*/
#define NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID (0x45U)
typedef struct NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS {
NvU32 linkId;
} NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_CYCLE_LINK (0x20803045U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG
@@ -2982,13 +3065,13 @@ typedef struct NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS {
* [out] bReducedNvlinkConfig
* Link number which the sequence should be triggered
*/
#define NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID (0x44U)
#define NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID (0x46U)
typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
NvBool bReducedNvlinkConfig;
} NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803044U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803046U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
/* _ctrl2080nvlink_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h
View File

@@ -60,6 +60,9 @@ typedef struct RM_GSP_SPDM_CC_INIT_CTX {
NvU64_ALIGN32 dmaAddr; // The address RM allocate in SYS memory or FB memory.
NvU32 rmBufferSizeInByte; // The memort size allocated by RM(exclude NV_SPDM_DESC_HEADER)
} RM_GSP_SPDM_CC_INIT_CTX;
typedef struct RM_GSP_SPDM_CC_INIT_CTX *PRM_GSP_SPDM_CC_INIT_CTX;

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ucodefuzzer.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

6
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
View File

@@ -52,6 +52,8 @@
* guestFbLengthList - list of guest FB memory length in bytes
* pluginHeapMemoryPhysAddr - plugin heap memory offset
* pluginHeapMemoryLength - plugin heap memory length in bytes
* migRmHeapMemoryPhysAddr - Mig rm heap memory region's physical offset.
* migRmHeapMemoryLength - Mig rm heap memory length in bytes
* bDeviceProfilingEnabled - If set to true, profiling is allowed
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK (0x20804001) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID" */
@@ -59,7 +61,7 @@
#define NV2080_CTRL_MAX_VMMU_SEGMENTS 384
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
#define NV2080_GPU_MAX_ENGINES 0x3e
#define NV2080_GPU_MAX_ENGINES 0x3f
#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U)
@@ -83,6 +85,8 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAM
NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryPhysAddr, 8);
NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryLength, 8);
NvBool bDeviceProfilingEnabled;
} NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS;

2
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

1
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h
View File

@@ -68,6 +68,7 @@ typedef struct NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS {
NvU32 sublocation;
NvU8 unit;
NvU8 errorType;
} NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS;

72
src/common/sdk/nvidia/inc/ctrl/ctrl90e7.h Normal file
View File

@@ -0,0 +1,72 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl90e7.finn
//
#include "nvfixedtypes.h"
#include "ctrl/ctrlxxxx.h"
/* GF100_SUBDEVICE_INFOROM control commands and parameters */
#define NV90E7_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x90E7, NV90E7_CTRL_##cat, idx)
/* Command categories (6 bits) */
#define NV90E7_CTRL_RESERVED (0x00)
#define NV90E7_CTRL_BBX (0x01)
/*
* NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME
*
* This command is used to query the last BBX flush timestamp and duration. If BBX has not yet
* been flushed, the status returned is NV_ERR_NOT_READY.
*
* timestamp
* This parameter specifies the start timestamp of the last BBX flush.
*
* durationUs
* This parameter specifies the duration (us) of the last BBX flush.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_READY
* NV_ERR_NOT_SUPPORTED
*/
#define NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME (0x90e70113) /* finn: Evaluated from "(FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID << 8) | NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID" */
#define NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS {
NV_DECLARE_ALIGNED(NvU64 timestamp, 8);
NvU32 durationUs;
} NV90E7_CTRL_BBX_GET_LAST_FLUSH_TIME_PARAMS;

114
src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -32,6 +32,7 @@
#include "ctrl/ctrlxxxx.h"
#include "mmu_fmt_types.h"
#include "nvcfg_sdk.h"
#define GMMU_FMT_MAX_LEVELS 6U
@@ -85,30 +86,35 @@ typedef struct NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS {
typedef struct NV_CTRL_VASPACE_PAGE_LEVEL {
/*!
* Format of this level.
*/
* Format of this level.
*/
NV_DECLARE_ALIGNED(struct MMU_FMT_LEVEL *pFmt, 8);
/*!
* Level/Sublevel Formats flattened
*/
* Level/Sublevel Formats flattened
*/
NV_DECLARE_ALIGNED(MMU_FMT_LEVEL levelFmt, 8);
NV_DECLARE_ALIGNED(MMU_FMT_LEVEL sublevelFmt[MMU_FMT_MAX_SUB_LEVELS], 8);
/*!
* Physical address of this page level instance.
*/
* Physical address of this page level instance.
*/
NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
/*!
* Aperture in which this page level instance resides.
*/
* Aperture in which this page level instance resides.
*/
NvU32 aperture;
/*!
* Size in bytes allocated for this level instance.
*/
* Size in bytes allocated for this level instance.
*/
NV_DECLARE_ALIGNED(NvU64 size, 8);
/*!
* Entry Index for this offset.
*/
NvU32 entryIndex;
} NV_CTRL_VASPACE_PAGE_LEVEL;
#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U)
@@ -135,6 +141,12 @@ typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS {
*/
NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
/*!
* [in] Flags
* Contains flags to control various aspects of page level info.
*/
NV_DECLARE_ALIGNED(NvU64 flags, 8);
/*!
* [out] Number of levels populated.
*/
@@ -146,6 +158,11 @@ typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS {
NV_DECLARE_ALIGNED(NV_CTRL_VASPACE_PAGE_LEVEL levels[GMMU_FMT_MAX_LEVELS], 8);
} NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS;
/* valid flags parameter values */
#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE 0x0ULL
#define NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_BAR1 NVBIT64(0)
/*!
* Reserve (allocate and bind) page directory/table entries up to
* a given level of the MMU format. Also referred to as "lock-down".
@@ -155,7 +172,7 @@ typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS {
* A particular VA range and level (page size) combination may only be
* locked down once at a given time, but each level is independent.
*/
#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */
#define NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES (0x90f10103U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID" */
#define NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID (0x3U)
@@ -314,4 +331,77 @@ typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS {
} levels[GMMU_FMT_MAX_LEVELS];
} NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS;
/*!
* Retrieve extra VA range that RM needs to reserve from the OS
*/
#define NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE (0x90f10107U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID" */
#define NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS {
/*!
* [in] GPU sub-device handle - this API only supports unicast.
* Pass 0 to use subDeviceId instead.
*/
NvHandle hSubDevice;
/*!
* [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
*/
NvU32 subDeviceId;
/*!
* [out] The required VA range, in Megabytes
*/
NV_DECLARE_ALIGNED(NvU64 requiredVaRange, 8);
} NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS;
/*!
* Retrieve info on a VAS heap - used only for the MODS test RandomVATest
*/
#define NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO (0x90f10108U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID" */
#define NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS {
/*!
* [in] GPU sub-device handle - this API only supports unicast.
* Pass 0 to use subDeviceId instead.
*/
NvHandle hSubDevice;
/*!
* [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
*/
NvU32 subDeviceId;
/*!
* [out] Number of free bytes in the heap
*/
NV_DECLARE_ALIGNED(NvU64 bytesFree, 8);
/*!
* [out] Number of bytes in the heap
*/
NV_DECLARE_ALIGNED(NvU64 bytesTotal, 8);
/*!
* [out] Offset of largest free block
*/
NV_DECLARE_ALIGNED(NvU64 largestFreeOffset, 8);
/*!
* [out] Size of the largest free block
*/
NV_DECLARE_ALIGNED(NvU64 largestFreeSize, 8);
/*!
* [out] Number of usable free bytes
*/
NV_DECLARE_ALIGNED(NvU64 usableBytesFree, 8);
/*!
* [out] Number of free blocks
*/
NvU32 numFreeBlocks;
} NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS;
/* _ctrl90f1_h_ */

37
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -556,4 +556,39 @@ typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS {
NVB0CC_CTRL_HES_TYPE type;
} NVB0CC_CTRL_RELEASE_HES_PARAMS;
/* End of extension construct */
/*!
* NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST
*
* Disable the Dynamic MMA clock boost during profiler lifetime.
*
*/
#define NVB0CC_CTRL_CMD_DISABLE_DYNAMIC_MMA_BOOST (0xb0cc0117) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS_MESSAGE_ID (0x17U)
typedef struct NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS {
/*!
* [in]: En/Disable Dynamic MMA Boost. True = disable Boost; False = re-enable Boost.
*/
NvBool disable;
} NVB0CC_CTRL_DISABLE_DYNAMIC_MMA_BOOST_PARAMS;
/*!
* NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS
*
* Request the Dynamic MMA clock boost feature enablement status.
*
*/
#define NVB0CC_CTRL_CMD_GET_DYNAMIC_MMA_BOOST_STATUS (0xb0cc0118) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS_MESSAGE_ID (0x18U)
typedef struct NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS {
/*!
* [out]: Dynamic MMA Boost status: true = boost enabled/available; False = Boost disabled/unavailable.
*/
NvBool enabled;
} NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS;
/* _ctrlb0ccprofiler_h_ */

169
src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2021,2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -35,6 +35,7 @@
#define NVC372_CTRL_MAX_POSSIBLE_HEADS 8
#define NVC372_CTRL_MAX_POSSIBLE_WINDOWS 32
#define NVC372_CTRL_MAX_POSSIBLE_TILES 8
#define NVC372_CTRL_CMD_IS_MODE_POSSIBLE (0xc3720101) /* finn: Evaluated from "(FINN_NVC372_DISPLAY_SW_CHNCTL_INTERFACE_ID << 8) | NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS_MESSAGE_ID" */
@@ -117,6 +118,10 @@
* bOverfetchEnabled indicates whether or not the vertical overfetch is
* enabled in postcomp scaler.
*
* head.bLtmAllowed
* bLtmAllowed indicates whether or not the Local Tone Mapping (LTM) is
* enabled in postcomp.
*
* head.minFrameIdle.leadingRasterLines
* leadingRasterLines defines the number of lines between the start of the
* frame (vsync) and the start of the active region. This includes Vsync,
@@ -132,6 +137,17 @@
* This parameter specifies whether or not the output LUT is enabled, and
* the size of the LUT. The parameter should be an
* NVC372_CTRL_IMP_LUT_USAGE_xxx value.
* On Volta, the value should be one of these:
* NVC372_CTRL_IMP_LUT_USAGE_1025, NVC372_CTRL_IMP_LUT_USAGE_257 or
* NVC372_CTRL_IMP_LUT_USAGE_NONE
*
* After Volta, the value should be one of these:
* NVC372_CTRL_IMP_LUT_USAGE_HW_MAX (this indicates that LUT is allowed) or
* NVC372_CTRL_IMP_LUT_USAGE_NONE
* (On older post-Volta products, clients may set other
* NVC372_CTRL_IMP_LUT_USAGE_xxx values, but they map to
* NVC372_CTRL_IMP_LUT_USAGE_HW_MAX in RM-SW.)
*
* head.cursorSize32p
* This parameter specifies the width of the cursor, in units of 32 pixels.
@@ -141,6 +157,21 @@
* head.bEnableDsc
* bEnableDsc indicates whether or not DSC is enabled
*
* head.possibleDscSliceCountMask
* This is a bit mask indicating how many DSC slices are allowed in a
* scanline. If a bit n is set in the bit mask, it means that one possible
* configuration has n+1 DSC slices per scanline.
*
* This field is required only on systems that support tiling, and only if
* head.bEnableDsc is true.
*
* head.maxDscSliceWidth
* The maximum allowed DSC slice width is determined by spec restrictions
* and monitor capabilities.
*
* This field is required only on systems that support tiling, and only if
* head.bEnableDsc is true.
*
* head.bYUV420Format
* This parameter indicates output format is YUV420.
* Refer to NVD_YUV420_Output_Functional_Description.docx for more details.
@@ -224,11 +255,31 @@
* This parameter specifies whether or not the input LUT is enabled, and
* the size of the LUT. The parameter should be an
* NVC372_CTRL_IMP_LUT_USAGE_xxx value.
* On Volta, the value should be one of these:
* NVC372_CTRL_IMP_LUT_USAGE_1025, NVC372_CTRL_IMP_LUT_USAGE_257 or
* NVC372_CTRL_IMP_LUT_USAGE_NONE
*
* After Volta, the value should be one of these:
* NVC372_CTRL_IMP_LUT_USAGE_HW_MAX (this indicates that LUT is allowed) or
* NVC372_CTRL_IMP_LUT_USAGE_NONE
* (On older post-Volta products, clients may set other
* NVC372_CTRL_IMP_LUT_USAGE_xxx values, but they map to
* NVC372_CTRL_IMP_LUT_USAGE_HW_MAX in RM-SW.)
*
* window.tmoLut
* This parameter specifies whether or not the tmo LUT is enabled, and
* the size of the LUT. This lut is used for HDR. The parameter should be
* an NVC372_CTRL_IMP_LUT_USAGE_xxx value.
* On Volta, the value should be one of these:
* NVC372_CTRL_IMP_LUT_USAGE_1025, NVC372_CTRL_IMP_LUT_USAGE_257 or
* NVC372_CTRL_IMP_LUT_USAGE_NONE
*
* After Volta, the value should be one of these:
* NVC372_CTRL_IMP_LUT_USAGE_HW_MAX (this indicates that LUT is allowed) or
* NVC372_CTRL_IMP_LUT_USAGE_NONE
* (On older post-Volta products, clients may set other
* NVC372_CTRL_IMP_LUT_USAGE_xxx values, but they map to
* NVC372_CTRL_IMP_LUT_USAGE_HW_MAX in RM-SW.)
*
* numHeads
* This is the number of heads in the "head" array of the
@@ -382,6 +433,101 @@
* Returns a short text string naming the domain for the margin returned in
* "worstCaseMargin". See "worstCaseMargin" for more information.
*
* numTilingAssignments
* This is the number of entries in the tilingAssignments array, each of
* which represents a possible distinct tiling configuration. The client
* will do the actual assignment of tiles during the modeset, but the
* information provided here will help the client to know how many tiles
* to assign to each head.
*
* The first tiling assignment (tilingAssignments[0]) is required; it will
* specify that one or more tiles must be assigned to each active head in
* order for the mode to be possible. Subsequent tiling assignments are
* optional; each higher assignment will reduce the required dispclk to a
* lower frequency, so the client may choose to use some or all of these
* assignments because they might reduce power consumption.
*
* The tiling assignments are incremental; the client may choose how many
* assignments to use (after the first one, which is required), but they
* must be used in sequence. For example, if there are five possible
* assignments (numTilingAssignments = 5), and the client wishes to apply
* the third assignment, the tiles from the first two assignments must also
* be allocated.
*
* If the client decides to use a particular tiling assignment, it should
* assign all tiles specified in that assignment. (Otherwise, there will
* be no benefit from that assignment for reducing dispclk.)
*
* A 3-head example of a set of tiling assignments is:
* numTilingAssignments = 3
* tilingAssignments[0].numTiles = 4
* tilingAssignments[1].numTiles = 2
* tilingAssignments[2].numTiles = 1
* tileList[0].head = 0 (first tile for tilingAssignments[0])
* tileList[0].headDscSlices = 2
* tileList[1].head = 0 (second tile for tilingAssignments[0])
* tileList[1].headDscSlices = xxx (not used, because it is specified in
* tileList[0].headDscSlices)
* tileList[2].head = 1 (third tile for tilingAssignments[0])
* tileList[2].headDscSlices = 1
* tileList[3].head = 2 (fourth tile for tilingAssignments[0])
* tileList[3].headDscSlices = 1
* tileList[4].head = 1 (first tile for tilingAssignments[1])
* tileList[4].headDscSlices = 2
* tileList[5].head = 2 (second tile for tilingAssignments[1])
* tileList[5].headDscSlices = 2
* tileList[6].head = 0 (tile for tilingAssignments[2]
* tileList[6].headDscSlices = 3
*
* tilingAssignments[0] always specifies the minimum tiling assignment
* necessary to make the mode possible. In this example, two tiles are
* required on head 0, but heads 1 and 2 can work with a single tile each.
*
* After the four required tiles are assigned for tilingAssignments[0], the
* client may choose to apply tilingAssignment[1] as well, to reduce
* dispclk further. Two additional tiles would be required for this, one
* on head 1 and one on head 2. Note that there would be no benefit to
* assigning a tile to only one of these two heads; all heads specified in
* the tilingAssignment must be assigned (if the tilingAssignment is to be
* used). After this assignment, head 1 and head 2 would each have two
* tiles assigned (one from tilingAssignment[0] and one from
* tilingAssignent[1]). Head 0 would still have 2 tiles assigned.
*
* If tilingAssignments[2] is also used, an additional tile would be
* assigned to head 0, bringing the tile total to three for that head. The
* number of DSC slices required for that head would be increased to three.
*
* tilingAssignments.numTiles
* This is the number of additional tiles required for the indexed tiling
* assignment. The tilingAssignment does not provide any benefit unless
* all of its specified tiles are assigned.
*
* tileList.head
* This specifies the head to which a tile must be assigned, to receive a
* benefit (dispclk reduction) for a given tiling assignment.
* tileList entries (head indexes) are assigned consecutively, based on the
* tilingAssignments.numTiles entries. For example, if
* tilingAssignments[0].numTiles = 3 and tilingAssignments[1].numTiles = 2,
* then the first three tileList entries (indexes 0, 1, and 2) would be for tiling
* assignment 0 and the next 2 entries (indexes 3 and 4) would be for
* tiling assignment 1.
*
* A single assignment may have multiple tileList.head entries for the same
* head (if a single head requires that more than one additional tile be
* assigned).
*
* tileList.headDscSlices
* headDscSlices gives the recommended number of DSC slices for each
* scanline for the head specified in tileList.head. If a specific tiling
* assignment has multiple tiles assigned to the same head, the
* headDscSlices value for the first tileList entry should be used;
* subsequent entries may be ignored. If multiple tilingAssignments are
* applied, the headDscSlices entry for the highest indexed
* tilingAssignment takes precedence over any entries from lower indexed
* assignments, for the same head.
*
* This field is relevant only if head.bEnableDsc is true.
*
* Possible status values returned are:
* NVOS_STATUS_SUCCESS
* NVOS_STATUS_ERROR_GENERIC
@@ -389,6 +535,7 @@
#define NVC372_CTRL_IMP_LUT_USAGE_NONE 0
#define NVC372_CTRL_IMP_LUT_USAGE_257 1
#define NVC372_CTRL_IMP_LUT_USAGE_1025 2
#define NVC372_CTRL_IMP_LUT_USAGE_HW_MAX 3
typedef struct NVC372_CTRL_IMP_HEAD {
NvU8 headIndex;
@@ -427,6 +574,7 @@ typedef struct NVC372_CTRL_IMP_HEAD {
NvU8 outputScalerVerticalTaps;
NvBool bUpscalingAllowedV;
NvBool bOverfetchEnabled;
NvBool bLtmAllowed;
struct {
NvU16 leadingRasterLines;
@@ -438,6 +586,10 @@ typedef struct NVC372_CTRL_IMP_HEAD {
NvBool bEnableDsc;
NvU32 possibleDscSliceCountMask;
NvU32 maxDscSliceWidth;
NvBool bYUV420Format;
NvBool bIs2Head1Or;
@@ -464,6 +616,15 @@ typedef struct NVC372_CTRL_IMP_WINDOW {
} NVC372_CTRL_IMP_WINDOW;
typedef struct NVC372_CTRL_IMP_WINDOW *PNVC372_CTRL_IMP_WINDOW;
typedef struct NVC372_TILING_ASSIGNMENT {
NvU8 numTiles;
} NVC372_TILING_ASSIGNMENT;
typedef struct NVC372_TILE_ENTRY {
NvU8 head;
NvU8 headDscSlices;
} NVC372_TILE_ENTRY;
#define NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_GET_MARGIN (0x00000001)
#define NVC372_CTRL_IS_MODE_POSSIBLE_OPTIONS_NEED_MIN_VPSTATE (0x00000002)
@@ -506,6 +667,12 @@ typedef struct NVC372_CTRL_IS_MODE_POSSIBLE_PARAMS {
NvU32 dispClkKHz;
NvU32 numTilingAssignments;
NVC372_TILING_ASSIGNMENT tilingAssignments[NVC372_CTRL_MAX_POSSIBLE_TILES];
NVC372_TILE_ENTRY tileList[NVC372_CTRL_MAX_POSSIBLE_TILES];
char worstCaseDomain[8];
NvBool bUseCachedPerfState;

2
src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2008,2013,2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

8
src/common/sdk/nvidia/inc/g_finn_rm_api.h
View File

@@ -294,6 +294,12 @@ typedef FINN_RM_API FINN_NV01_DEVICE_0_OS_UNIX;
typedef FINN_RM_API FINN_NV0090_KERNEL_GRAPHICS_CONTEXT;
#define FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID (0x00da00U)
typedef FINN_RM_API FINN_NV_SEMAPHORE_SURFACE;
#define FINN_RM_USER_SHARED_DATA_INTERFACE_ID (0xde00U)
typedef FINN_RM_API FINN_RM_USER_SHARED_DATA;
#define FINN_NV_MEMORY_EXPORT_RESERVED_INTERFACE_ID (0xE000U)
typedef FINN_RM_API FINN_NV_MEMORY_EXPORT_RESERVED;
#define FINN_NV_MEMORY_EXPORT_INTERFACE_ID (0xE001U)
typedef FINN_RM_API FINN_NV_MEMORY_EXPORT;
#define FINN_IMEX_SESSION_INTERFACE_ID (0xf100U)
typedef FINN_RM_API FINN_IMEX_SESSION;
#define FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf400U)
@@ -558,8 +564,6 @@ typedef FINN_RM_API FINN_GF100_SUBDEVICE_MASTER_MASTER;
typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RESERVED;
#define FINN_GF100_SUBDEVICE_INFOROM_BBX_INTERFACE_ID (0x90e701U)
typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_BBX;
#define FINN_GF100_SUBDEVICE_INFOROM_RPR_INTERFACE_ID (0x90e702U)
typedef FINN_RM_API FINN_GF100_SUBDEVICE_INFOROM_RPR;
#define FINN_GF100_HDACODEC_RESERVED_INTERFACE_ID (0x90ec00U)
typedef FINN_RM_API FINN_GF100_HDACODEC_RESERVED;

2
src/common/sdk/nvidia/inc/nvdisptypes.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2016,2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

13
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -35,7 +35,6 @@
#include "nvcfg_sdk.h"
#define ROBUST_CHANNEL_GR_EXCEPTION (13)
#define ROBUST_CHANNEL_GR_ERROR_SW_NOTIFY (13)
#define ROBUST_CHANNEL_FAKE_ERROR (14)
#define ROBUST_CHANNEL_VBLANK_CALLBACK_TIMEOUT (16)
#define ROBUST_CHANNEL_DISP_MISSED_NOTIFIER (19)
@@ -46,7 +45,7 @@
#define ROBUST_CHANNEL_VP_ERROR (27)
#define ROBUST_CHANNEL_VP2_ERROR (28)
#define ROBUST_CHANNEL_BSP_ERROR (29)
#define ROBUST_CHANNEL_BAD_ADDR_ACCESS (30)
#define ROBUST_CHANNEL_UNUSED_ERROR_30 (30)
#define ROBUST_CHANNEL_FIFO_ERROR_MMU_ERR_FLT (31)
#define ROBUST_CHANNEL_PBDMA_ERROR (32)
#define ROBUST_CHANNEL_SEC_ERROR (33)
@@ -120,7 +119,6 @@
#define ALI_TRAINING_FAIL (136)
#define NVLINK_FLA_PRIV_ERR (137)
#define ROBUST_CHANNEL_DLA_ERROR (138)
#define ROBUST_CHANNEL_FAST_PATH_ERROR (139)
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)
#define ROBUST_CHANNEL_LAST_ERROR (UNRECOVERABLE_ECC_ERROR_ESCAPE)
@@ -219,6 +217,15 @@
(x - ROBUST_CHANNEL_NVJPG0_ERROR) : \
(x - ROBUST_CHANNEL_NVJPG1_ERROR + 1))
#define ROBUST_CHANNEL_OFA_ERROR(x) \
(ROBUST_CHANNEL_OFA0_ERROR)
#define ROBUST_CHANNEL_IS_OFA_ERROR(x) \
(x == ROBUST_CHANNEL_OFA0_ERROR)
#define ROBUST_CHANNEL_OFA_ERROR_IDX(x) \
(x - ROBUST_CHANNEL_OFA0_ERROR)
// Error Levels
#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_INFO (0)
#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_NON_FATAL (1)

46
src/common/sdk/nvidia/inc/nvos.h
View File

@@ -995,13 +995,6 @@ typedef struct
#define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 0x00000009
#define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 0x0000000A
// Tiled region
#define NVOS32_ATTR_TILED 9:8
#define NVOS32_ATTR_TILED_NONE 0x00000000
#define NVOS32_ATTR_TILED_REQUIRED 0x00000001
#define NVOS32_ATTR_TILED_ANY 0x00000002
#define NVOS32_ATTR_TILED_DEFERRED 0x00000003
// Zcull region (NV40 and up)
// If ATTR_ZCULL is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the
// allocation will fail.
@@ -1026,6 +1019,14 @@ typedef struct
#define NVOS32_ATTR_COMPR_PLC_ANY NVOS32_ATTR_COMPR_ANY
#define NVOS32_ATTR_COMPR_DISABLE_PLC_ANY 0x00000003
//
// Force the allocation to go to the reserved heap.
// This flag is used for KMD allocations when MIG is enabled.
//
#define NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP 14:14
#define NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_NO 0x00000000
#define NVOS32_ATTR_ALLOCATE_FROM_RESERVED_HEAP_YES 0x00000001
// Format
// _BLOCK_LINEAR is only available for nv50+.
#define NVOS32_ATTR_FORMAT 17:16
@@ -1169,12 +1170,15 @@ typedef struct
#define NVOS32_ATTR2_32BIT_POINTER_ENABLE 0x00000001
//
// Indicates address conversion to be used, which affects what
// pitch alignment needs to be used
// Whether or not a NUMA Node ID has been specified.
// If yes, the NUMA node ID specified in numaNode will be used.
// If no, memory can be allocated from any socket (numaNode will be ignored).
// Specified numaNode must be of a CPU's memory
//
#define NVOS32_ATTR2_TILED_TYPE 7:7
#define NVOS32_ATTR2_TILED_TYPE_LINEAR 0x00000000
#define NVOS32_ATTR2_TILED_TYPE_XY 0x00000001
#define NVOS32_ATTR2_FIXED_NUMA_NODE_ID 7:7
#define NVOS32_ATTR2_FIXED_NUMA_NODE_ID_NO 0x00000000
#define NVOS32_ATTR2_FIXED_NUMA_NODE_ID_YES 0x00000001
//
// Force SMMU mapping on GPU physical allocation in Tegra
@@ -1316,6 +1320,14 @@ typedef struct
#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO 0x00000000
#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES 0x00000001
//
// When allocating memory, register the memory descriptor to GSP-RM
// so that GSP-RM is aware of and can access it
//
#define NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM 31:31
#define NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_FALSE 0x00000000
#define NVOS32_ATTR2_REGISTER_MEMDESC_TO_PHYS_RM_TRUE 0x00000001
/**
* NVOS32 ALLOC_FLAGS
*
@@ -1631,6 +1643,8 @@ typedef struct
NvU32 internalflags; // [IN] - internal flags to change allocation behaviors from internal paths
NvU32 tag; // [IN] - memory tag used for debugging
NvS32 numaNode; // [IN] - CPU NUMA node from which memory should be allocated
} NV_MEMORY_ALLOCATION_PARAMS;
/*
@@ -1776,7 +1790,7 @@ typedef struct
// - Used for controlling CPU addresses in CUDA's unified CPU+GPU virtual
// address space
// - Only valid on NvRmMapMemory
// - Only implemented on Linux
// - Implemented on Unix but not VMware
#define NVOS33_FLAGS_MAP_FIXED 18:18
#define NVOS33_FLAGS_MAP_FIXED_DISABLE (0x00000000)
#define NVOS33_FLAGS_MAP_FIXED_ENABLE (0x00000001)
@@ -1794,9 +1808,10 @@ typedef struct
// - When combined with MAP_FIXED, this allows the client to exert
// significant control over the CPU heap
// - Used in CUDA's unified CPU+GPU virtual address space
// - Only valid on NvRmMapMemory (specifies RM's behavior whenever the
// - Valid in nvRmUnmapMemory
// - Valid on NvRmMapMemory (specifies RM's behavior whenever the
// mapping is destroyed, regardless of mechanism)
// - Only implemented on Linux
// - Implemented on Unix but not VMware
#define NVOS33_FLAGS_RESERVE_ON_UNMAP 19:19
#define NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE (0x00000000)
#define NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE (0x00000001)
@@ -2551,6 +2566,7 @@ typedef struct
{
NvU32 size;
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of OFA?
NvU32 engineInstance;
} NV_OFA_ALLOCATION_PARAMETERS;
#define NV04_ADD_VBLANK_CALLBACK (0x0000003D)