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580.94.16

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russellcnv
2026-01-22 14:46:29 -08:00
parent a3af2867b7
commit c273d84a8b
68 changed files with 160855 additions and 160151 deletions
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16
src/common/inc/nvBldVer.h
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@@ -43,18 +43,18 @@
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/VK580_65-189"
#define NV_BUILD_CHANGELIST_NUM (37068878)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/VK580_65-192"
#define NV_BUILD_CHANGELIST_NUM (37211220)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r580/VK580_65-189"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37068878)
#define NV_BUILD_NAME "rel/gpu_drv/r580/VK580_65-192"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37211220)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "VK580_65-15"
#define NV_BUILD_CHANGELIST_NUM (37068878)
#define NV_BUILD_BRANCH_VERSION "VK580_65-17"
#define NV_BUILD_CHANGELIST_NUM (37211220)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "582.15"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37068878)
#define NV_BUILD_NAME "582.29"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (37211220)
#define NV_BUILD_BRANCH_BASE_VERSION R580
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "580.94.13"
#define NV_VERSION_STRING "580.94.16"
#else

2
src/common/inc/nvVer.h
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@@ -3,7 +3,7 @@
#define NV_COMPANY_NAME_STRING_SHORT "NVIDIA"
#define NV_COMPANY_NAME_STRING_FULL "NVIDIA Corporation"
#define NV_COMPANY_NAME_STRING NV_COMPANY_NAME_STRING_FULL
#define NV_COPYRIGHT_YEAR "2025"
#define NV_COPYRIGHT_YEAR "2026"
#define NV_COPYRIGHT "(C) " NV_COPYRIGHT_YEAR " NVIDIA Corporation. All rights reserved." // Please do not use the non-ascii copyright symbol for (C).
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \

34
src/common/inc/swref/published/blackwell/gb100/dev_fb.h Normal file
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@@ -0,0 +1,34 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_fb_h_
#define __gb100_dev_fb_h_
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE 0x001FA3E0 /* RW-4R */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE__PRIV_LEVEL_MASK 0x001FA7C4 /* */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_SCALE 3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_SCALE_INIT 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_MAG 27:4 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_MAG_INIT 0x00000000 /* RWE-V */
#endif // __gb100_dev_fb_h_

31
src/common/inc/swref/published/blackwell/gb100/dev_gc6_island.h Normal file
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@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_gc6_island_h__
#define __gb100_dev_gc6_island_h__
#define NV_PGC6_BSI_SECURE_SCRATCH_12 0x001180f0 /* RW-4R */
#define NV_PGC6_BSI_SECURE_SCRATCH_12_DATA 31:0 /* RWIVF */
#define NV_PGC6_BSI_SECURE_SCRATCH_12_DATA_INIT 0x00000000 /* RWI-V */
#endif // __gb100_dev_gc6_island_h__

29
src/common/inc/swref/published/blackwell/gb100/dev_gc6_island_addendum.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_gc6_island_addendum_h__
#define __gb100_dev_gc6_island_addendum_h__
#define NV_PGC6_BSI_SECURE_SCRATCH_MMU_LOCAL_MEMORY_RANGE NV_PGC6_BSI_SECURE_SCRATCH_12
#endif // __gb100_dev_gc6_island_addendum_h__

2
src/common/modeset/timing/nvt_edid.c
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@@ -1265,6 +1265,8 @@ void updateColorFormatAndBpcTiming(NVT_EDID_INFO *pInfo)
// DisplayId2.0 spec has its own way of determining color format support which includes bpc + color format
updateColorFormatForDisplayId20ExtnTimings(pInfo, i);
}
updateBpcForYuv420OnlyTiming(&pInfo->timing[i], &pInfo->ext861);
}
// Go through all the timings and set CTA format accordingly. If a timing is a CTA 861b timing, store the

37
src/common/modeset/timing/nvt_edidext_861.c
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@@ -284,7 +284,8 @@ static const NVT_TIMING EIA861B[]=
// the end
EIA_TIMING(0,0,0,0,'-',0,0,0,0,'-',0,'p',4:3,0,0)
};
static NvU32 MAX_CEA861B_FORMAT = sizeof(EIA861B)/sizeof(EIA861B[0]) - 1;
static const NvU32 MAX_CEA861B_FORMAT = sizeof(EIA861B)/sizeof(EIA861B[0]) - 1;
static const NvU32 EIA861B_DUAL_ASPECT_VICS[][2] =
{
@@ -972,6 +973,40 @@ void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861,
}
}
// If a timing is present in the YUV420 VDB, consider it
// incompatible with other sampling modes
CODE_SEGMENT(PAGE_DD_CODE)
void updateBpcForYuv420OnlyTiming(NVT_TIMING *pT,
const NVT_EDID_CEA861_INFO *p861Info)
{
NvU32 i;
const NvU8 *pYuv420Vic = p861Info->svd_y420vdb;
NvBool yuv420Only = NV_FALSE;
for (i = 0; i < p861Info->total_y420vdb; i++)
{
NVT_TIMING y420vdbTiming;
NvU8 vic = NVT_GET_CTA_8BIT_VIC(pYuv420Vic[i]);
if (vic == 0 || vic > MAX_CEA861B_FORMAT)
continue;
y420vdbTiming = EIA861B[vic-1];
if (NvTiming_IsTimingExactEqual(pT, &y420vdbTiming))
{
yuv420Only = NV_TRUE;
break;
}
}
if (yuv420Only)
{
pT->etc.rgb444.bpcs = 0;
pT->etc.yuv444.bpcs = 0;
pT->etc.yuv422.bpcs = 0;
}
}
// Currently, the SVR both used in the NVRDB and VFPDB.
// "One particular application is a Sink that prefers a Video Format that is not listed as an SVD in a VDB
// but instead listed in a YCBCR 4:2:0 Video Data Block"

1
src/common/modeset/timing/nvtiming_pvt.h
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@@ -77,6 +77,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *pEdid, NvU32 size, NVT_EDID_CEA861_INF
void parse861ExtDetailedTiming(NvU8 *pEdidExt, NvU8 basicCaps, NVT_EDID_INFO *pInfo);
void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void updateBpcForYuv420OnlyTiming(NVT_TIMING *pT, const NVT_EDID_CEA861_INFO *p861Info);
void parseCta861VideoFormatDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo);
void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861VsdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);

13
src/common/nvlink/inband/interface/nvlink_inband_msg.h
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@@ -141,7 +141,6 @@ typedef struct
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED 0
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE 1
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE 2
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE_RESET_REQUIRED 3
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY 7:6
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED 0
@@ -153,10 +152,16 @@ typedef struct
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NONE 1U
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_SYSGUID 2U
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCORRECT_CHASSIS_SN 3U
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NO_PARTITION 4U
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NO_PARTITION 4U // Deprecated
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INSUFFICIENT_NVLINKS 5U
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCOMPATIBLE_GPU_FW 6U
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INVALID_LOCATION 7U
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_GPU_STATE_INVALID 8U
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED 13 : 12
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_NOT_SUPPORTED 0U
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_TRUE 1U
#define NVLINK_INBAND_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_FALSE 2U
#define NVLINK_INBAND_FABRIC_HEALTH_SUMMARY_NOT_SUPPORTED 0U
#define NVLINK_INBAND_FABRIC_HEALTH_SUMMARY_HEALTHY 1U
@@ -374,10 +379,10 @@ static NV_INLINE NvU8 nvlinkGetFabricHealthSummary
}
if (REF_VAL(NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY, fabricHealth) == NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE ||
REF_VAL(NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY, fabricHealth) == NVLINK_INBAND_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE_RESET_REQUIRED ||
REF_VAL(NVLINK_INBAND_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY, fabricHealth) == NVLINK_INBAND_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE ||
(REF_VAL(NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION, fabricHealth) != NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NONE &&
REF_VAL(NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION, fabricHealth) != NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NOT_SUPPORTED))
REF_VAL(NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION, fabricHealth) != NVLINK_INBAND_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_NOT_SUPPORTED) ||
REF_VAL(NVLINK_INBAND_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED, fabricHealth) == NVLINK_INBAND_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_FALSE)
{
return NVLINK_INBAND_FABRIC_HEALTH_SUMMARY_UNHEALTHY;
}

48
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
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@@ -2896,4 +2896,52 @@ typedef struct NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO carveoutRegion[NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_MAX_ENTRIES], 8);
} NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_CPU_COHERENT_RANGE
*
* This command returns the CPU-coherent FB range.
* Only applicable on self-hosted platforms.
*
* coherentCpuFbBase
* FB offset of the start of the CPU-coherent range
* coherentCpuFbEnd
* FB offset of the end (exclusive) of the CPU-coherent range
*/
#define NV2080_CTRL_CMD_FB_GET_CPU_COHERENT_RANGE (0x20801361U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS_MESSAGE_ID (0x61U)
typedef struct NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 coherentCpuFbBase, 8);
NV_DECLARE_ALIGNED(NvU64 coherentCpuFbEnd, 8);
} NV2080_CTRL_FB_GET_CPU_COHERENT_RANGE_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_WPR_REGION_INFO
*
* This command returns information about WPR regions.
*
* wpr1Start
* FB offset of the start of WPR1
* wpr1End
* FB offset of the end (exclusive) of WPR1
* wpr2Start
* FB offset of the start of WPR1
* wpr2End
* FB offset of the end (exclusive) of WPR1
* fbRegionOfWpr2Start
* FB offset of the start of the FB region (as tracked by RM) that contains WPR2
*/
#define NV2080_CTRL_CMD_FB_GET_WPR_REGION_INFO (0x20801362U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS_MESSAGE_ID (0x62U)
typedef struct NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 wpr1Start, 8);
NV_DECLARE_ALIGNED(NvU64 wpr1End, 8);
NV_DECLARE_ALIGNED(NvU64 wpr2Start, 8);
NV_DECLARE_ALIGNED(NvU64 wpr2End, 8);
NV_DECLARE_ALIGNED(NvU64 fbRegionOfWpr2Start, 8);
} NV2080_CTRL_FB_GET_WPR_REGION_INFO_PARAMS;
/* _ctrl2080fb_h_ */

6
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -4198,6 +4198,12 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INSUFFICIENT_NVLINKS 5
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INCOMPATIBLE_GPU_FW 6
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_INVALID_LOCATION 7
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_INCORRECT_CONFIGURATION_GPU_STATE_INVALID 8
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED 13:12
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_PARTITION_ASSIGNED_FALSE 2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_SUMMARY_HEALTHY 1