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This commit is contained in:
Bernhard Stoeckner
2025-05-19 17:24:39 +02:00
parent 8ec351aeb9
commit d5cb404571
71 changed files with 978 additions and 330 deletions
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3
src/nvidia/generated/g_chipset_nvoc.h
View File

@@ -157,6 +157,9 @@ struct PCIECONFIGSPACEBASE
#define CL_AER_ERROR_SOURCE (CL_AER_BEGIN + 0x34)
#define CL_AER_END (CL_AER_BEGIN + 0x34)
// Advanced Error Reporting Root Error Status ERR_COR Subclass Capable Mask
#define CL_AER_ROOT_ERROR_STATUS_ERR_COR_SUBCLASS_MASK (NVBIT32(7) | NVBIT32(8))
// PCI Express Device Capabilities 2
#define CL_PCIE_DEV_CAP_2_ATOMICS_SUPPORTED_BIT NVBIT(6)
#define CL_PCIE_DEV_CAP_2_ATOMIC_32BIT NVBIT(7)

8
src/nvidia/generated/g_gpu_access_nvoc.h
View File

@@ -228,6 +228,14 @@ void regCheckAndLogReadFailure(RegisterAccess *, NvU32 addr, NvU32 mask, NvU32 v
// Get the address of a register given the Aperture and offset.
#define REG_GET_ADDR(ap, offset) ioaprtGetRegAddr(ap, offset)
//
// These UNCHECKED macros are provided for extenuating circumstances to avoid the 0xbadf
// sanity checking done by the usual register read utilities and must not be used generally
//
//
#define GPU_REG_RD08_UNCHECKED(g,a) osDevReadReg008(g, gpuGetDeviceMapping(g, DEVICE_INDEX_GPU, 0), a)
#define GPU_REG_RD32_UNCHECKED(g,a) osDevReadReg032(g, gpuGetDeviceMapping(g, DEVICE_INDEX_GPU, 0), a)
// GPU macros defined in terms of DEV_ macros
#define GPU_REG_RD08(g,a) REG_INST_RD08(g,GPU,0,a)
#define GPU_REG_RD16(g,a) REG_INST_RD16(g,GPU,0,a)

12
src/nvidia/generated/g_gpu_nvoc.c
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@@ -391,6 +391,18 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
pThis->setProperty(pThis, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED, NV_FALSE);
pThis->setProperty(pThis, PDB_PROP_GPU_RECOVERY_DRAIN_P2P_REQUIRED, NV_FALSE);
// NVOC Property Hal field -- PDB_PROP_GPU_REUSE_INIT_CONTING_MEM
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xc0000000UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000ec1UL) )) /* ChipHal: GB100 | GB102 | GB10B | GB202 | GB203 | GB205 | GB206 | GB207 */
{
pThis->setProperty(pThis, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM, NV_TRUE);
}
// default
else
{
pThis->setProperty(pThis, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM, NV_FALSE);
}
// NVOC Property Hal field -- PDB_PROP_GPU_RUSD_POLLING_SUPPORT_MONOLITHIC
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xd1f0f800UL) ) ||
( ((chipHal_HalVarIdx >> 5) == 2UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000ec1UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 | GB100 | GB102 | GB10B | GB202 | GB203 | GB205 | GB206 | GB207 */

7
src/nvidia/generated/g_gpu_nvoc.h
View File

@@ -1073,7 +1073,7 @@ struct OBJGPU {
NvBool (*__gpuIsInternalSkuFuseEnabled__)(struct OBJGPU * /*this*/); // halified (2 hals) body
NvBool (*__gpuGetIsCmpSku__)(struct OBJGPU * /*this*/); // halified (2 hals) body
// 114 PDB properties
// 115 PDB properties
NvBool PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED;
NvBool PDB_PROP_GPU_IN_STANDBY;
NvBool PDB_PROP_GPU_IN_HIBERNATE;
@@ -1187,6 +1187,7 @@ struct OBJGPU {
NvBool PDB_PROP_GPU_FASTPATH_SEQ_ENABLED;
NvBool PDB_PROP_GPU_PREPARING_FULLCHIP_RESET;
NvBool PDB_PROP_GPU_RECOVERY_DRAIN_P2P_REQUIRED;
NvBool PDB_PROP_GPU_REUSE_INIT_CONTING_MEM;
NvBool PDB_PROP_GPU_RUSD_POLLING_SUPPORT_MONOLITHIC;
// Data members
@@ -1247,6 +1248,8 @@ struct OBJGPU {
DEVICE_MAPPING *pDeviceMappingsByDeviceInstance[12];
void *gpuCfgAddr;
TIMEOUT_DATA timeoutData;
NvBool bBug5203024OverrideTimeoutsRegkeySet;
NvU32 bug5203024OverrideTimeouts;
NvU32 computeModeRules;
NvS32 computeModeRefCount;
NvHandle hComputeModeReservation;
@@ -1427,6 +1430,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU;
#define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU_BASE_NAME PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU
#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_CAST
#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_NAME PDB_PROP_GPU_SKIP_TABLE_CE_MAP
#define PDB_PROP_GPU_REUSE_INIT_CONTING_MEM_BASE_CAST
#define PDB_PROP_GPU_REUSE_INIT_CONTING_MEM_BASE_NAME PDB_PROP_GPU_REUSE_INIT_CONTING_MEM
#define PDB_PROP_GPU_IN_FATAL_ERROR_BASE_CAST
#define PDB_PROP_GPU_IN_FATAL_ERROR_BASE_NAME PDB_PROP_GPU_IN_FATAL_ERROR
#define PDB_PROP_GPU_VGA_ENABLED_BASE_CAST

7
src/nvidia/generated/g_kern_disp_nvoc.h
View File

@@ -14,7 +14,7 @@ extern "C" {
#endif
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -212,12 +212,13 @@ struct KernelDisplay {
NvU32 (*__kdispServiceAwakenIntr__)(OBJGPU *, struct KernelDisplay * /*this*/, struct THREAD_STATE_NODE *); // halified (2 hals) body
NV_STATUS (*__kdispComputeDpModeSettings__)(OBJGPU *, struct KernelDisplay * /*this*/, NvU32, DPMODESETDATA *, DPIMPINFO *); // halified (3 hals) body
// 6 PDB properties
// 7 PDB properties
NvBool PDB_PROP_KDISP_IMP_ENABLE;
NvBool PDB_PROP_KDISP_IMP_ALLOC_BW_IN_KERNEL_RM_DEF;
NvBool PDB_PROP_KDISP_FEATURE_STRETCH_VBLANK_CAPABLE;
NvBool PDB_PROP_KDISP_IN_AWAKEN_INTR;
NvBool PDB_PROP_KDISP_HAS_SEPARATE_LOW_LATENCY_LINE;
NvBool PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED;
// Data members
struct DisplayInstanceMemory *pInst;
@@ -302,6 +303,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelDisplay;
#define PDB_PROP_KDISP_IMP_ENABLE_BASE_NAME PDB_PROP_KDISP_IMP_ENABLE
#define PDB_PROP_KDISP_FEATURE_STRETCH_VBLANK_CAPABLE_BASE_CAST
#define PDB_PROP_KDISP_FEATURE_STRETCH_VBLANK_CAPABLE_BASE_NAME PDB_PROP_KDISP_FEATURE_STRETCH_VBLANK_CAPABLE
#define PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED_BASE_CAST
#define PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED_BASE_NAME PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED
NV_STATUS __nvoc_objCreateDynamic_KernelDisplay(KernelDisplay**, Dynamic*, NvU32, va_list);

7
src/nvidia/generated/g_nv_name_released.h
View File

@@ -5420,6 +5420,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2BB1, 0x204b, 0x103c, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
{ 0x2BB1, 0x204b, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
{ 0x2BB1, 0x204b, 0x17aa, "NVIDIA RTX PRO 6000 Blackwell Workstation Edition" },
{ 0x2BB3, 0x204d, 0x1028, "NVIDIA RTX PRO 5000 Blackwell" },
{ 0x2BB3, 0x204d, 0x103c, "NVIDIA RTX PRO 5000 Blackwell" },
{ 0x2BB3, 0x204d, 0x10de, "NVIDIA RTX PRO 5000 Blackwell" },
{ 0x2BB3, 0x204d, 0x17aa, "NVIDIA RTX PRO 5000 Blackwell" },
{ 0x2BB4, 0x204c, 0x1028, "NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition" },
{ 0x2BB4, 0x204c, 0x103c, "NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition" },
{ 0x2BB4, 0x204c, 0x10de, "NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition" },
@@ -5430,6 +5434,9 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2C19, 0x0000, 0x0000, "NVIDIA GeForce RTX 5080 Laptop GPU" },
{ 0x2C58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 Laptop GPU" },
{ 0x2C59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5080 Laptop GPU" },
{ 0x2D04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Ti" },
{ 0x2D18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2F04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070" },
{ 0x2F18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },
{ 0x2F58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },

206
src/nvidia/generated/g_subdevice_nvoc.c
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@@ -8758,6 +8758,66 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
#endif
},
{ /* [576] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccess_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*flags=*/ 0x44u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x20803090u,
/*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccess"
#endif
},
{ /* [577] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccessPPRM_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*flags=*/ 0x44u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x20803091u,
/*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPPRM"
#endif
},
{ /* [578] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccessPTASV2_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*flags=*/ 0x44u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x20803093u,
/*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPTASV2"
#endif
},
{ /* [579] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*flags=*/ 0x44u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x20803094u,
/*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM"
#endif
},
{ /* [580] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8772,7 +8832,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage"
#endif
},
{ /* [577] */
{ /* [581] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8787,7 +8847,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch"
#endif
},
{ /* [578] */
{ /* [582] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8802,7 +8862,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo"
#endif
},
{ /* [579] */
{ /* [583] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8817,7 +8877,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet"
#endif
},
{ /* [580] */
{ /* [584] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8832,7 +8892,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet"
#endif
},
{ /* [581] */
{ /* [585] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8847,7 +8907,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo"
#endif
},
{ /* [582] */
{ /* [586] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8862,7 +8922,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize"
#endif
},
{ /* [583] */
{ /* [587] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8877,7 +8937,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters"
#endif
},
{ /* [584] */
{ /* [588] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8892,7 +8952,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdEccGetVolatileCounts"
#endif
},
{ /* [585] */
{ /* [589] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8907,7 +8967,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlaRange"
#endif
},
{ /* [586] */
{ /* [590] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10244u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8922,7 +8982,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock"
#endif
},
{ /* [587] */
{ /* [591] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10004u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8937,7 +8997,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlaGetRange"
#endif
},
{ /* [588] */
{ /* [592] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x108u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8952,7 +9012,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats"
#endif
},
{ /* [589] */
{ /* [593] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40549u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8967,7 +9027,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGspGetFeatures"
#endif
},
{ /* [590] */
{ /* [594] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8982,7 +9042,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGspGetRmHeapStats"
#endif
},
{ /* [591] */
{ /* [595] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -8997,7 +9057,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGpuGetVgpuHeapStats"
#endif
},
{ /* [592] */
{ /* [596] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x248u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9012,7 +9072,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdLibosGetHeapStats"
#endif
},
{ /* [593] */
{ /* [597] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x248u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9027,7 +9087,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo"
#endif
},
{ /* [594] */
{ /* [598] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9042,7 +9102,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt"
#endif
},
{ /* [595] */
{ /* [599] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9057,7 +9117,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff"
#endif
},
{ /* [596] */
{ /* [600] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9072,7 +9132,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower"
#endif
},
{ /* [597] */
{ /* [601] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xbu)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9087,7 +9147,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus"
#endif
},
{ /* [598] */
{ /* [602] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9102,7 +9162,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus"
#endif
},
{ /* [599] */
{ /* [603] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9117,7 +9177,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask"
#endif
},
{ /* [600] */
{ /* [604] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9132,7 +9192,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask"
#endif
},
{ /* [601] */
{ /* [605] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9147,7 +9207,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType"
#endif
},
{ /* [602] */
{ /* [606] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9162,7 +9222,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu"
#endif
},
{ /* [603] */
{ /* [607] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9177,7 +9237,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo"
#endif
},
{ /* [604] */
{ /* [608] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9192,7 +9252,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage"
#endif
},
{ /* [605] */
{ /* [609] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1d0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9207,7 +9267,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity"
#endif
},
{ /* [606] */
{ /* [610] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9222,7 +9282,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources"
#endif
},
{ /* [607] */
{ /* [611] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9237,7 +9297,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding"
#endif
},
{ /* [608] */
{ /* [612] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9252,7 +9312,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport"
#endif
},
{ /* [609] */
{ /* [613] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9267,7 +9327,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig"
#endif
},
{ /* [610] */
{ /* [614] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9282,7 +9342,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalFreeStates"
#endif
},
{ /* [611] */
{ /* [615] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9297,7 +9357,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetFrameRateLimiterStatus"
#endif
},
{ /* [612] */
{ /* [616] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9312,7 +9372,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuHeterogeneousMode"
#endif
},
{ /* [613] */
{ /* [617] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x158u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9327,7 +9387,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask"
#endif
},
{ /* [614] */
{ /* [618] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x158u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9342,7 +9402,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlSetEcThrottleMode"
#endif
},
{ /* [615] */
{ /* [619] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@@ -9596,7 +9656,7 @@ NV_STATUS __nvoc_up_thunk_Notifier_subdeviceGetOrAllocNotifShare(struct Subdevic
const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice =
{
/*numEntries=*/ 616,
/*numEntries=*/ 620,
/*pExportEntries=*/ __nvoc_exported_method_def_Subdevice
};
@@ -10301,6 +10361,26 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
pThis->__subdeviceCtrlCmdNvlinkPRMAccessPLIB__ = &subdeviceCtrlCmdNvlinkPRMAccessPLIB_IMPL;
#endif
// subdeviceCtrlCmdNvlinkPRMAccessPTASV2 -- exported (id=0x20803093)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
pThis->__subdeviceCtrlCmdNvlinkPRMAccessPTASV2__ = &subdeviceCtrlCmdNvlinkPRMAccessPTASV2_IMPL;
#endif
// subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM -- exported (id=0x20803094)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
pThis->__subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM__ = &subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_IMPL;
#endif
// subdeviceCtrlCmdNvlinkPRMAccessPPRM -- exported (id=0x20803091)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
pThis->__subdeviceCtrlCmdNvlinkPRMAccessPPRM__ = &subdeviceCtrlCmdNvlinkPRMAccessPPRM_IMPL;
#endif
// subdeviceCtrlCmdNvlinkPRMAccess -- exported (id=0x20803090)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
pThis->__subdeviceCtrlCmdNvlinkPRMAccess__ = &subdeviceCtrlCmdNvlinkPRMAccess_IMPL;
#endif
// subdeviceCtrlCmdNvlinkGetPlatformInfo -- exported (id=0x20803083)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
pThis->__subdeviceCtrlCmdNvlinkGetPlatformInfo__ = &subdeviceCtrlCmdNvlinkGetPlatformInfo_IMPL;
@@ -10937,6 +11017,16 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
pThis->__subdeviceCtrlCmdKGrGetCtxswStats__ = &subdeviceCtrlCmdKGrGetCtxswStats_IMPL;
#endif
} // End __nvoc_init_funcTable_Subdevice_1 with approximately 263 basic block(s).
// Vtable initialization 2/3
static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
PORT_UNREFERENCED_VARIABLE(pThis);
PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
// subdeviceCtrlCmdKGrGetCtxBufferSize -- exported (id=0x20801218)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x18u)
@@ -10957,16 +11047,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
pThis->__subdeviceCtrlCmdKGrGetCurrentResidentChannel__ = &subdeviceCtrlCmdKGrGetCurrentResidentChannel_IMPL;
#endif
} // End __nvoc_init_funcTable_Subdevice_1 with approximately 263 basic block(s).
// Vtable initialization 2/3
static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
PORT_UNREFERENCED_VARIABLE(pThis);
PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
// subdeviceCtrlCmdKGrGetVatAlarmData -- exported (id=0x2080121d)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
@@ -12258,6 +12338,16 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400c0u)
pThis->__subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer__ = &subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer_IMPL;
#endif
} // End __nvoc_init_funcTable_Subdevice_2 with approximately 263 basic block(s).
// Vtable initialization 3/3
static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
PORT_UNREFERENCED_VARIABLE(pThis);
PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
// subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer -- exported (id=0x20800a9c)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400c0u)
@@ -12278,16 +12368,6 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
pThis->__subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer__ = &subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer_IMPL;
#endif
} // End __nvoc_init_funcTable_Subdevice_2 with approximately 263 basic block(s).
// Vtable initialization 3/3
static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
PORT_UNREFERENCED_VARIABLE(pThis);
PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
// subdeviceCtrlCmdCeGetPhysicalCaps -- exported (id=0x20802a07)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x301d0u)
@@ -12978,10 +13058,10 @@ static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
pThis->__subdeviceSpdmRetrieveTranscript__ = &subdeviceSpdmRetrieveTranscript_IMPL;
#endif
} // End __nvoc_init_funcTable_Subdevice_3 with approximately 138 basic block(s).
} // End __nvoc_init_funcTable_Subdevice_3 with approximately 142 basic block(s).
// Initialize vtable(s) for 646 virtual method(s).
// Initialize vtable(s) for 650 virtual method(s).
void __nvoc_init_funcTable_Subdevice(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
// Per-class vtable definition
@@ -13100,7 +13180,7 @@ void __nvoc_init_funcTable_Subdevice(Subdevice *pThis, RmHalspecOwner *pRmhalspe
pThis->__nvoc_base_Notifier.__nvoc_vtable = &vtable.Notifier; // (notify) super
pThis->__nvoc_vtable = &vtable; // (subdevice) this
// Initialize vtable(s) with 616 per-object function pointer(s).
// Initialize vtable(s) with 620 per-object function pointer(s).
// To reduce stack pressure with some unoptimized builds, the logic is distributed among 3 functions.
__nvoc_init_funcTable_Subdevice_1(pThis, pRmhalspecowner);
__nvoc_init_funcTable_Subdevice_2(pThis, pRmhalspecowner);

38
src/nvidia/generated/g_subdevice_nvoc.h
View File

@@ -148,7 +148,7 @@ struct Subdevice {
struct Notifier *__nvoc_pbase_Notifier; // notify super
struct Subdevice *__nvoc_pbase_Subdevice; // subdevice
// Vtable with 616 per-object function pointers
// Vtable with 620 per-object function pointers
NV_STATUS (*__subdeviceCtrlCmdBiosGetInfoV2__)(struct Subdevice * /*this*/, NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *); // halified (2 hals) exported (id=0x20800810) body
NV_STATUS (*__subdeviceCtrlCmdBiosGetNbsiV2__)(struct Subdevice * /*this*/, NV2080_CTRL_BIOS_GET_NBSI_V2_PARAMS *); // exported (id=0x2080080e)
NV_STATUS (*__subdeviceCtrlCmdBiosGetSKUInfo__)(struct Subdevice * /*this*/, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *); // halified (2 hals) exported (id=0x20800808)
@@ -269,6 +269,10 @@ struct Subdevice {
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPPSLS__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS *); // exported (id=0x2080307e)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessMLPC__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS *); // exported (id=0x2080307f)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPLIB__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS *); // exported (id=0x20803080)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPTASV2__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS *); // exported (id=0x20803093)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS *); // exported (id=0x20803094)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPPRM__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS *); // exported (id=0x20803091)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccess__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS *); // exported (id=0x20803090)
NV_STATUS (*__subdeviceCtrlCmdNvlinkGetPlatformInfo__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS *); // exported (id=0x20803083)
NV_STATUS (*__subdeviceCtrlCmdI2cReadBuffer__)(struct Subdevice * /*this*/, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *); // exported (id=0x20800601)
NV_STATUS (*__subdeviceCtrlCmdI2cWriteBuffer__)(struct Subdevice * /*this*/, NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS *); // exported (id=0x20800602)
@@ -1121,6 +1125,14 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C
#define subdeviceCtrlCmdNvlinkPRMAccessMLPC(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessMLPC_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccessPLIB_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPLIB__
#define subdeviceCtrlCmdNvlinkPRMAccessPLIB(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessPLIB_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccessPTASV2_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPTASV2__
#define subdeviceCtrlCmdNvlinkPRMAccessPTASV2(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessPTASV2_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM__
#define subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccessPPRM_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPPRM__
#define subdeviceCtrlCmdNvlinkPRMAccessPPRM(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessPPRM_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccess_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccess__
#define subdeviceCtrlCmdNvlinkPRMAccess(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccess_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkGetPlatformInfo_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkGetPlatformInfo__
#define subdeviceCtrlCmdNvlinkGetPlatformInfo(arg_this, arg2) subdeviceCtrlCmdNvlinkGetPlatformInfo_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdI2cReadBuffer_FNPTR(pSubdevice) pSubdevice->__subdeviceCtrlCmdI2cReadBuffer__
@@ -2703,6 +2715,22 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPLIB_DISPATCH(struct Subd
return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPLIB__(arg_this, arg2);
}
static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPTASV2_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS *arg2) {
return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPTASV2__(arg_this, arg2);
}
static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS *arg2) {
return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM__(arg_this, arg2);
}
static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPPRM_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS *arg2) {
return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPPRM__(arg_this, arg2);
}
static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccess_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS *arg2) {
return arg_this->__subdeviceCtrlCmdNvlinkPRMAccess__(arg_this, arg2);
}
static inline NV_STATUS subdeviceCtrlCmdNvlinkGetPlatformInfo_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS *arg2) {
return arg_this->__subdeviceCtrlCmdNvlinkGetPlatformInfo__(arg_this, arg2);
}
@@ -5085,6 +5113,14 @@ NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessMLPC_IMPL(struct Subdevice *arg1, NV208
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPLIB_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS *arg2);
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPTASV2_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PTASV2_PARAMS *arg2);
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessSLLM_5NM_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_SLLM_5NM_PARAMS *arg2);
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPPRM_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PPRM_PARAMS *arg2);
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccess_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PARAMS *arg2);
NV_STATUS subdeviceCtrlCmdNvlinkGetPlatformInfo_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS *arg2);
NV_STATUS subdeviceCtrlCmdI2cReadBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *pI2cParams);

8
src/nvidia/inc/kernel/platform/nvpcf.h
View File

@@ -83,6 +83,7 @@ typedef struct
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_22 (0x22)
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_23 (0x23)
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_24 (0x24)
#define NVPCF_CONTROLLER_STATIC_TABLE_VERSION_25 (0x25)
#define NVPCF_CONTROLLER_STATIC_TABLE_MAX_ENTRIES (8)
// format for 2.0 and 2.1
@@ -184,8 +185,9 @@ typedef struct
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_FILTER_RESERVED 31:16
// Param0
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_PARAM0_QBOOST_INCREASE_GAIN 15:0
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_PARAM0_QBOOST_INCREASE_GAIN 15:0
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_PARAM0_QBOOST_DECREASE_GAIN 31:16
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V25_PARAM0_CPU_TDP_TYPE 4:1
// Param1
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_PARAM1_QBOOST_DC_SUPPORT 0:0
@@ -196,6 +198,10 @@ typedef struct
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_SIZE_05 (0x05U)
#define NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_FMT_SIZE_05 ("1b1d")
// Param0
#define NVPCF_CONTROLLER_SBIOS_TABLE_CPU_TDP_CONTROL_DC_ONLY (0x00)
#define NVPCF_CONTROLLER_SBIOS_TABLE_CPU_TDP_CONTROL_DC_AC (0x01)
/*!
* Static system controller header table v2.2, unpacked
*/

48
src/nvidia/interface/nvrm_registry.h
View File

@@ -64,7 +64,7 @@
// Type Dword
// Change all RM internal timeouts to experiment with Bug 5203024.
//
// Some timeouts may still silently clamp to differnt min/max values and this
// Some timeouts may still silently clamp to different min/max values and this
// regkey does NOT validate their range.
//
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT "RmOverrideInternalTimeoutsMs"
@@ -84,6 +84,20 @@
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_FECS_WATCHDOG_TIMEOUT 26:26
//
// This regkey is experimental
//
// Type Dword
// Change video Watchdog and GP timeouts to experiment with Bug 5203024.
// Stores the timeout value in ms.
// If this regkey is set and has non-zero value, also disables MB timeouts.
//
// Some timeouts may still silently clamp to different min/max values and this
// regkey does NOT validate their range.
//
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_VIDEO_TIMEOUT "RmVideoEngineTimeoutMs"
//
// Type Dword
// Override default RM timeout. Measured in milliseconds.
@@ -1332,6 +1346,11 @@
#define NV_REG_STR_RM_INTR_LOCKING_MODE_DEFAULT (0x00000000)
#define NV_REG_STR_RM_INTR_LOCKING_MODE_INTR_MASK (0x00000001)
#define NV_REG_INTERNAL_PANEL_DISCONNECTED "RMInternalPanelDisconnected"
#define NV_REG_INTERNAL_PANEL_DISCONNECTED_DISABLE 0x00000000
#define NV_REG_INTERNAL_PANEL_DISCONNECTED_ENABLE 0x00000001
#define NV_REG_INTERNAL_PANEL_DISCONNECTED_DEFAULT RM_REG_INTERNAL_PANEL_DISCONNECTED_DISABLE
#define NV_REG_STR_RM_PER_INTR_DPC_QUEUING "RMDisablePerIntrDPCQueueing"
// Type DWORD
// This regkey is used to disable per interrupt DPC queuing.
@@ -1398,14 +1417,14 @@
#define NV_REG_STR_RM_RC_WATCHDOG_DEFAULT NV_REG_STR_RM_RC_WATCHDOG_ENABLE
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT "RmWatchDogTimeOut"
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW 0x00000007
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_HI 0x0000000C
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_DEFAULT NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_LOW 5
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_HI 60
#define NV_REG_STR_RM_WATCHDOG_TIMEOUT_DEFAULT 7
#define NV_REG_STR_RM_WATCHDOG_INTERVAL "RmWatchDogInterval"
#define NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW 0x00000007
#define NV_REG_STR_RM_WATCHDOG_INTERVAL_HI 0x0000000C
#define NV_REG_STR_RM_WATCHDOG_INTERVAL_DEFAULT NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW
#define NV_REG_STR_RM_WATCHDOG_INTERVAL "RmWatchDogInterval"
#define NV_REG_STR_RM_WATCHDOG_INTERVAL_LOW 5
#define NV_REG_STR_RM_WATCHDOG_INTERVAL_HI 30
#define NV_REG_STR_RM_WATCHDOG_INTERVAL_DEFAULT 7
// Enable/Disable watchcat in GSP-Plugin for Guest RPC
// Default is Enabled
@@ -2620,6 +2639,19 @@
#define NV_REG_STR_RM_RUSD_POLLING_INTERVAL_MIN 100
#define NV_REG_STR_RM_RUSD_POLLING_INTERVAL_MAX 1000
//
// Type: DWORD
// This regkey enables some path to reuse the initially allocated continguous memory
// instead of freeing it dynamically which causes memory fragmentation and
// under low available memory configuration the allocation could fail and leads to BSOD
// Enable the key to reuse the initially allocated mem withoug free and reallocate
// - Default for Blackwell and up
// Disable the key to free and allocate dynamically
//
#define NV_REG_STR_RM_INIT_MEM_REUSE "RmInitMemReuse"
#define NV_REG_STR_RM_INIT_MEM_REUSE_ENABLE 0x00000001
#define NV_REG_STR_RM_INIT_MEM_REUSE_DISABLE 0x00000000
//
// Type DWORD (Boolean)
// This regkey controls the use of BAR1 SPA instead of GPA for p2p subsystems

16
src/nvidia/kernel/inc/gpuvideo/rmifvideng.h
View File

@@ -85,8 +85,20 @@ typedef struct
* You can reorder or change below this point but update version.
* Make sure to align it to 16B as ucode expect 16byte alignment to DMA efficiently.
*/
NvU32 videoPgPmuHandshake; // Handshake between PMU and Video Ucode for SW controlled IDLE signal.
NvU64 rsvd2; // reserved field
NvU32 videoPgPmuHandshake; // Handshake between PMU and Video Ucode for SW controlled IDLE signal.
/*
* WAR to avoid triggering HS signing on older chips, as these bootargs are only used on RISCV anyways.
* Always define videngTimeoutMs for RM builds. Assumption is that ENG_TYPE will be undefined for RM builds
* Only define it in video ucode builds that enable GB10X_OVERRIDE_TIMEOUT in build cfgs.
*/
#if (!defined(ENG_TYPE) || defined(GB10X_OVERRIDE_TIMEOUT))
NvU32 videngTimeoutMs; // SW WAR for bug 5203864, increasing timeouts on GB10x via regkey RmOverrideInternalTimeoutsMs.
// Specify the timeout value in ms. If the value is 0, do not override the timeouts sent from KMD and/or UMD.
NvU32 rsvd2; // reserved field
#else
NvU64 rsvd2; // reserved field
#endif
} NV_VIDENG_BOOT_PARAMS, *PNV_VIDENG_BOOT_PARAMS;
#endif // RMIFVIDENG_H

11
src/nvidia/src/kernel/compute/imex_session_api.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -339,7 +339,7 @@ imexsessionapiDestruct_IMPL
if (_checkDanglingExports(RES_GET_CLIENT(pImexSessionApi)))
{
fabricDisableMemAlloc(pFabric);
NV_PRINTF(LEVEL_ERROR, "Abrupt nvidia-imex daemon shutdown detected, disabled fabric allocations!\n");
NV_PRINTF(LEVEL_ERROR, "Abrupt nvidia-imex daemon shutdown detected, disabled fabric allocations\n");
}
// Invalidate export cache to block future imports on this node ID.
@@ -361,7 +361,7 @@ imexsessionapiDestruct_IMPL
{
if (rcAndDisableOutstandingClientsWithImportedMemory(NULL, NV_FABRIC_INVALID_NODE_ID))
{
NV_PRINTF(LEVEL_ERROR, "Abrupt nvidia-imex daemon shutdown detected, robust channel recovery invoked!\n");
NV_PRINTF(LEVEL_ERROR, "Abrupt nvidia-imex daemon shutdown detected, robust channel recovery invoked\n");
}
}
}
@@ -426,7 +426,10 @@ imexsessionapiCtrlCmdDisableImporters_IMPL
return NV_ERR_NOT_SUPPORTED;
if (rcAndDisableOutstandingClientsWithImportedMemory(NULL, pParams->nodeId))
NV_PRINTF(LEVEL_ERROR, "nvidia-imex daemon has invoked robust channel recovery!\n");
{
NV_PRINTF(LEVEL_ERROR, "nvidia-imex daemon has invoked robust channel recovery for remote node: %u\n",
pParams->nodeId);
}
return NV_OK;
}

5
src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -22,6 +22,7 @@
*/
#include "gpu/gpu.h"
#include "gpu/gpu_access.h"
#include "gpu/gpu_child_class_defs.h"
#include "os/os.h"
#include "nverror.h"
@@ -101,7 +102,7 @@ gpuReadPassThruConfigReg_GH100
NvU32 *pData
)
{
*pData = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_EP_PCFGM) + index);
*pData = GPU_REG_RD32_UNCHECKED(pGpu, DEVICE_BASE(NV_EP_PCFGM) + index);
return NV_OK;
}

24
src/nvidia/src/kernel/gpu/disp/kern_disp.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -102,6 +102,7 @@ kdispConstructEngine_IMPL(OBJGPU *pGpu,
ENGDESCRIPTOR engDesc)
{
NV_STATUS status;
NvU32 data;
//
// NOTE: DO NOT call IpVersion _HAL functions in ConstructEngine.
@@ -140,6 +141,20 @@ kdispConstructEngine_IMPL(OBJGPU *pGpu,
pKernelDisplay->pLowLatencySpinLock = (PORT_SPINLOCK *) portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged());
NV_ASSERT_OR_RETURN((pKernelDisplay->pLowLatencySpinLock != NULL), NV_ERR_INSUFFICIENT_RESOURCES);
if ((osReadRegistryDword(pGpu, NV_REG_INTERNAL_PANEL_DISCONNECTED, &data) == NV_OK)
&& (data == NV_REG_INTERNAL_PANEL_DISCONNECTED_ENABLE))
{
pKernelDisplay->setProperty(pKernelDisplay,
PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED,
NV_TRUE);
}
else
{
pKernelDisplay->setProperty(pKernelDisplay,
PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED,
NV_FALSE);
}
return status;
}
@@ -342,14 +357,17 @@ kdispInitBrightcStateLoad_IMPL(OBJGPU *pGpu,
portMemSet(pBrightcInfo, 0, sizeof(*pBrightcInfo));
pBrightcInfo->status = status;
if ((pKernelDisplay != NULL) && (pKernelDisplay->pStaticInfo->internalDispActiveMask != 0) && !bInternalSkuFuseEnabled)
if ((pKernelDisplay != NULL)
&& (pKernelDisplay->pStaticInfo->internalDispActiveMask != 0)
&& !(bInternalSkuFuseEnabled
|| (pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED))))
{
// Fill in the Backlight Method Data.
pBrightcInfo->backLightDataSize = sizeof(pBrightcInfo->backLightData);
status = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_CURRENT, NV_ACPI_GENERIC_FUNC_GETBACKLIGHT,
(NvU32 *)(pBrightcInfo->backLightData),
&pBrightcInfo->backLightDataSize);
pBrightcInfo->status = status;
pBrightcInfo->status = status;
}
status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice,

11
src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -52,6 +52,7 @@ kchangrpAllocFaultMethodBuffers_GV100
HW_ENG_FAULT_METHOD_BUFFER *pFaultMthdBuf = NULL;
NvU32 gfid = pKernelChannelGroup->gfid;
TRANSFER_SURFACE surf = {0};
NvBool bReUseInitMem = pGpu->getProperty(pGpu, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM);
//
// Allocate method buffer if applicable
@@ -91,6 +92,12 @@ kchangrpAllocFaultMethodBuffers_GV100
{
// Get the right aperture/attribute
faultBufApert = ADDR_SYSMEM;
if (bReUseInitMem)
{
faultBufApert = ADDR_FBMEM;
}
faultBufAttr = NV_MEMORY_CACHED;
memdescOverrideInstLoc(DRF_VAL(_REG_STR_RM, _INST_LOC_3, _FAULT_METHOD_BUFFER, pGpu->instLocOverrides3),
"fault method buffer", &faultBufApert, &faultBufAttr);
@@ -112,7 +119,7 @@ kchangrpAllocFaultMethodBuffers_GV100
goto fail;
}
memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_34,
memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_34,
pFaultMthdBuf->pMemDesc);
if (status != NV_OK)
{

37
src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c
View File

@@ -952,7 +952,6 @@ kfspGetGspBootArgs
)
{
NV_STATUS status = NV_OK;
ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu);
NV_ASSERT(pCC != NULL);
@@ -993,6 +992,7 @@ kfspSetupGspImages
PBINDATA_STORAGE pGspImageHash;
PBINDATA_STORAGE pGspImageSignature;
PBINDATA_STORAGE pGspImagePublicKey;
NvBool bReUseInitMem = pGpu->getProperty(pGpu, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM);
NvU32 pGspImageSize;
NvU32 pGspImageMapSize;
NvP64 pVaKernel = NULL;
@@ -1029,15 +1029,17 @@ kfspSetupGspImages
pGspImageSize = bindataGetBufferSize(pGspImage);
pGspImageMapSize = NV_ALIGN_UP(pGspImageSize, 0x1000);
if ((pKernelFsp->pGspFmcMemdesc == NULL) || !bReUseInitMem)
{
NV_ASSERT(pKernelFsp->pGspFmcMemdesc == NULL); // If we assert the pointer becomes a zombie.
status = memdescCreate(&pKernelFsp->pGspFmcMemdesc, pGpu, pGspImageMapSize,
0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags);
NV_ASSERT_OR_GOTO(status == NV_OK, failed);
status = memdescCreate(&pKernelFsp->pGspFmcMemdesc, pGpu, pGspImageMapSize,
0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags);
NV_ASSERT_OR_GOTO(status == NV_OK, failed);
memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_7,
pKernelFsp->pGspFmcMemdesc);
NV_ASSERT_OR_GOTO(status == NV_OK, failed);
memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_7,
pKernelFsp->pGspFmcMemdesc);
NV_ASSERT_OR_GOTO(status == NV_OK, failed);
}
status = memdescMap(pKernelFsp->pGspFmcMemdesc, 0, pGspImageMapSize, NV_TRUE,
NV_PROTECT_READ_WRITE, &pVaKernel, &pPrivKernel);
NV_ASSERT_OR_GOTO(status == NV_OK, failed);
@@ -1292,6 +1294,7 @@ kfspPrepareBootCommands_GH100
NvBool bIsKeepWPRGc6D3Cold = pGpu->getProperty(pGpu, PDB_PROP_GPU_KEEP_WPR_ACROSS_GC6_SUPPORTED) &&
IS_GPU_GC6_STATE_EXITING(pGpu) &&
pKernelFsp->bUseKeepWPRGc6FSPCommand;
NvBool bReUseInitMem = pGpu->getProperty(pGpu, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM);
statusBoot = kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp);
@@ -1374,13 +1377,17 @@ kfspPrepareBootCommands_GH100
// FSP (an unit inside GPU) and hence placed in unprotected sysmem
//
flags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY;
status = memdescCreate(&pKernelFsp->pSysmemFrtsMemdesc, pGpu, frtsSize,
0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags);
NV_ASSERT_OR_GOTO(status == NV_OK, failed);
if ((pKernelFsp->pSysmemFrtsMemdesc == NULL) || !bReUseInitMem)
{
NV_ASSERT(pKernelFsp->pSysmemFrtsMemdesc == NULL); // If we assert the pointer becomes a zombie.
status = memdescCreate(&pKernelFsp->pSysmemFrtsMemdesc, pGpu, frtsSize,
0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags);
NV_ASSERT_OR_GOTO(status == NV_OK, failed);
memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_8,
pKernelFsp->pSysmemFrtsMemdesc);
NV_ASSERT_OR_GOTO(status == NV_OK, failed);
memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_8,
pKernelFsp->pSysmemFrtsMemdesc);
NV_ASSERT_OR_GOTO(status == NV_OK, failed);
}
// Set up a kernel mapping for future use in RM
status = memdescMap(pKernelFsp->pSysmemFrtsMemdesc, 0, frtsSize, NV_TRUE,

1
src/nvidia/src/kernel/gpu/fsp/kern_fsp.c
View File

@@ -242,7 +242,6 @@ kfspStateUnload_IMPL
NvU32 flags
)
{
kfspReleaseProxyImage(pGpu, pKernelFsp);
return NV_OK;
}

9
src/nvidia/src/kernel/gpu/gpu.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -6186,7 +6186,11 @@ gpuLogOobXidMessage_KERNEL
{
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu);
NV_STATUS status;
NvBool bGspFatalError = NV_FALSE;
NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS params = {0};
KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu);
bGspFatalError = pKernelGsp->bFatalError;
// Exclude conditions that indicate issues with GSP communication.
if ((xid == GSP_ERROR) ||
@@ -6196,7 +6200,8 @@ gpuLogOobXidMessage_KERNEL
!pGpu->gspRmInitialized ||
pGpu->getProperty(pGpu, PDB_PROP_GPU_PREPARING_FULLCHIP_RESET) ||
pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST) ||
!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED))
!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED) ||
bGspFatalError)
{
return;
}

6
src/nvidia/src/kernel/gpu/gpu_registry.c
View File

@@ -225,6 +225,12 @@ gpuInitRegistryOverrides_KERNEL
pGpu->userSharedData.pollingFrequencyMs = NV_REG_STR_RM_RUSD_POLLING_INTERVAL_DEFAULT;
pGpu->userSharedData.bPollFrequencyOverridden = NV_FALSE;
}
if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_INIT_MEM_REUSE, &data32) == NV_OK) &&
(data32 == NV_REG_STR_RM_INIT_MEM_REUSE_DISABLE))
{
pGpu->setProperty(pGpu, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM, NV_FALSE);
}
return NV_OK;
}

14
src/nvidia/src/kernel/gpu/gpu_timeout.c
View File

@@ -105,11 +105,15 @@ timeoutRegistryOverride
{
NvU32 data32 = 0;
NvU32 bug5203024OverrideTimeouts = (
(osReadRegistryDword(pGpu, NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT,
&data32) == NV_OK) ?
data32 :
0);
pGpu->bBug5203024OverrideTimeoutsRegkeySet =
(osReadRegistryDword(pGpu,
NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT,
&data32) == NV_OK);
pGpu->bug5203024OverrideTimeouts =
pGpu->bBug5203024OverrideTimeoutsRegkeySet ? data32 : 0;
NvU32 bug5203024OverrideTimeouts = pGpu->bug5203024OverrideTimeouts;
NvBool bOverrideDefaultTimeout = (DRF_VAL(_REG_STR,
_RM_BUG5203024_OVERRIDE_TIMEOUT,

7
src/nvidia/src/kernel/gpu/gsp/arch/blackwell/kernel_gsp_gb100.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -169,6 +169,8 @@ kgspServiceFatalHwError_GB100
NV_PRINTF(LEVEL_ERROR, "NV_PGSP_FALCON_IRQSTAT_FATAL_ERROR PENDING error_code 0x%x\n", errorCode);
MODS_ARCH_ERROR_PRINTF("NV_PGSP_FALCON_IRQSTAT_FATAL_ERROR=0x%x\n", errorCode);
pKernelGsp->bFatalError = NV_TRUE;
// Poison error
if (FLD_TEST_DRF(_PGSP, _RISCV_FAULT_CONTAINMENT_SRCSTAT, _GLOBAL_MEM, _FAULTED, errorCode))
{
@@ -190,9 +192,8 @@ kgspServiceFatalHwError_GB100
else
{
nvErrorLog_va((void *)pGpu, ROBUST_CHANNEL_CONTAINED_ERROR, "GSP-RISCV instance 0 fatal error");
NV_ASSERT_OK(gpuMarkDeviceForReset(pGpu));
}
pKernelGsp->bFatalError = NV_TRUE;
kgspRcAndNotifyAllChannels(pGpu, pKernelGsp, ROBUST_CHANNEL_CONTAINED_ERROR, NV_TRUE);
NV_ASSERT_OK(gpuMarkDeviceForReset(pGpu));
}

7
src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c
View File

@@ -333,6 +333,13 @@ memmgrTestCeUtils
NvU32 vidmemData = 0xAABBCCDD;
NvU32 sysmemData = 0x11223345;
NV_STATUS status;
NvBool bReUseInitMem = pGpu->getProperty(pGpu, PDB_PROP_GPU_REUSE_INIT_CONTING_MEM);
// Under low sysmem case we skip the testing since it requries extra memory
if (bReUseInitMem)
{
return NV_OK;
}
NV_ASSERT_OR_RETURN(pMemoryManager->pCeUtils != NULL, NV_ERR_INVALID_STATE);

4
src/nvidia/src/kernel/gpu/perf/kern_perf_ctrl.c
View File

@@ -111,6 +111,10 @@ subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_KERNEL
pParams,
sizeof(*pParams)));
// Skip translation if the request from root namespace.
if (osIsInitNs())
return NV_OK;
// Now translate the sample's procId.
numEntries = pParams->bufSize / sizeof (NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE);
NV_ASSERT_OR_RETURN(numEntries <= NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL,

46
src/nvidia/src/kernel/gpu/rc/kernel_rc.c
View File

@@ -451,7 +451,6 @@ krcCheckBusError_KERNEL
NvU32 clDevCtrlStatus = 0;
PcieAerCapability clAer;
// PCI-E provides extended error reporting
if (pKernelBif == NULL || kbifGetBusIntfType_HAL(pKernelBif) !=
NV2080_CTRL_BUS_INFO_TYPE_PCI_EXPRESS)
@@ -470,8 +469,8 @@ krcCheckBusError_KERNEL
&clDevCtrlStatus) == NV_OK &&
clDevCtrlStatusFlags != 0)
{
NV_PRINTF(LEVEL_ERROR,
"PCI-E corelogic status has pending errors (CL_PCIE_DEV_CTRL_STATUS = %08X):\n",
NV_PRINTF(LEVEL_INFO,
"PCI-E corelogic: Pending errors in DEV_CTRL_STATUS = %08X\n",
clDevCtrlStatus);
clDevCtrlStatusFlags_Org = clDevCtrlStatusFlags;
@@ -479,7 +478,7 @@ krcCheckBusError_KERNEL
if (clDevCtrlStatusFlags &
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR)
{
NV_PRINTF(LEVEL_ERROR, " _CORR_ERROR_DETECTED\n");
NV_PRINTF(LEVEL_INFO, "PCI-E corelogic: CORR_ERROR_DETECTED\n");
// not much interested in this one
clDevCtrlStatusFlags &=
~NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_CORR_ERROR;
@@ -487,63 +486,64 @@ krcCheckBusError_KERNEL
if (clDevCtrlStatusFlags &
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_NON_FATAL_ERROR)
{
NV_PRINTF(LEVEL_ERROR, " _NON_FATAL_ERROR_DETECTED\n");
NV_PRINTF(LEVEL_INFO, "PCI-E corelogic: NON_FATAL_ERROR_DETECTED\n");
}
if (clDevCtrlStatusFlags &
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_FATAL_ERROR)
{
NV_PRINTF(LEVEL_ERROR, " _FATAL_ERROR_DETECTED\n");
NV_PRINTF(LEVEL_ERROR, "PCI-E corelogic: FATAL_ERROR_DETECTED\n");
}
if (clDevCtrlStatusFlags &
NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_UNSUPP_REQUEST)
{
NV_PRINTF(LEVEL_ERROR, " _UNSUPP_REQUEST_DETECTED\n");
NV_PRINTF(LEVEL_INFO, "PCI-E corelogic: UNSUPP_REQUEST_DETECTED\n");
}
}
// Corelogic AER
if (pCl != NULL && clPcieReadAerCapability(pGpu, pCl, &clAer) == NV_OK &&
(clAer.UncorrErrStatusReg != 0 || clAer.RooErrStatus != 0))
(clAer.UncorrErrStatusReg != 0 ||
(clAer.RooErrStatus & ~CL_AER_ROOT_ERROR_STATUS_ERR_COR_SUBCLASS_MASK) != 0))
{
NV_PRINTF(LEVEL_ERROR,
"PCE-I Advanced Error Reporting Corelogic Info:\n");
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
"PCI-E Advanced Error Reporting Corelogic Info:\n");
NV_PRINTF(LEVEL_NOTICE,
" Uncorr Error Status Register : %08X\n",
clAer.UncorrErrStatusReg);
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
" Uncorr Error Mask Register : %08X\n",
clAer.UncorrErrMaskReg);
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
" Uncorr Error Severity Register : %08X\n",
clAer.UncorrErrSeverityReg);
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
" Corr Error Status Register : %08X\n",
clAer.CorrErrStatusReg);
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
" Corr Error Mask Register : %08X\n",
clAer.CorrErrMaskReg);
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
" Advanced Err Cap & Ctrl Register: %08X\n",
clAer.AEcapCrtlReg);
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
" Header Log [0-3] : %08X\n",
clAer.HeaderLogReg.Header[0]);
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
" Header Log [4-7] : %08X\n",
clAer.HeaderLogReg.Header[1]);
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
" Header Log [8-B] : %08X\n",
clAer.HeaderLogReg.Header[2]);
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
" Header Log [C-F] : %08X\n",
clAer.HeaderLogReg.Header[3]);
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
" Root Error Command Register : %08X\n",
clAer.RootErrCmd);
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
" Root Error Status : %08X\n",
clAer.RooErrStatus);
NV_PRINTF(LEVEL_ERROR,
NV_PRINTF(LEVEL_NOTICE,
" Error Source ID Register : %08X\n",
clAer.ErrSrcReg);

1
src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c
View File

@@ -458,7 +458,6 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams,
data = NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO;
if (osDmabufIsSupported() &&
(!IS_VIRTUAL(pGpu)) &&
(!gpuIsApmFeatureEnabled(pGpu)) &&
(!NVCPU_IS_PPC64LE))
{

16
src/nvidia/src/kernel/platform/acpi_common.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2000-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2000-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -40,6 +40,9 @@
#include "mxm_spec.h"
#include "gpu/gsp/gsp_static_config.h"
#include "platform/nbsi/nbsi_read.h"
#include "nvrm_registry.h"
#include "gpu/disp/kern_disp.h"
//
// DSM ACPI Routines common routines for Linux
@@ -706,6 +709,17 @@ checkDsmCall
NV_ASSERT_OR_RETURN(pInOut, NV_ERR_INVALID_ARGUMENT);
NV_ASSERT_OR_RETURN(pSize, NV_ERR_INVALID_ARGUMENT);
KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu);
if (pKernelDisplay != NULL
&& pKernelDisplay->getProperty(pKernelDisplay, PDB_PROP_KDISP_INTERNAL_PANEL_DISCONNECTED))
{
if (*pAcpiDsmFunction == ACPI_DSM_FUNCTION_NBCI)
{
return NV_ERR_NOT_SUPPORTED;
}
}
// Do any remapping of subfunction if function is current
if (remapDsmFunctionAndSubFunction(pGpu, pAcpiDsmFunction, pAcpiDsmSubFunction) != NV_OK)
{

27
src/nvidia/src/kernel/rmapi/client_resource.c
View File

@@ -2601,6 +2601,7 @@ _controllerParseStaticTable_v22
switch (header.version)
{
case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_25:
case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_24:
case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_23:
case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_22:
@@ -2639,10 +2640,12 @@ _controllerParseStaticTable_v22
}
}
CONTROLLER_STATIC_TABLE_ENTRY_V22 entry = { 0 };
// Parse each entry
for (loop = 0; loop < header.entryCount; loop++)
{
CONTROLLER_STATIC_TABLE_ENTRY_V22 entry = { 0 };
portMemSet(&entry, 0, sizeof(entry));
NvU32 offset = header.headerSize +
(loop * NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V22_SIZE_05);
@@ -2671,6 +2674,28 @@ _controllerParseStaticTable_v22
}
}
if (header.version == NVPCF_CONTROLLER_STATIC_TABLE_VERSION_25)
{
switch(DRF_VAL(PCF_CONTROLLER_STATIC_TABLE_ENTRY_V25, _PARAM0, _CPU_TDP_TYPE,entry.flags0))
{
case NVPCF_CONTROLLER_SBIOS_TABLE_CPU_TDP_CONTROL_DC_ONLY:
{
pParams->cpuTdpControlType = QBOOST_CPU_TDP_CONTROL_TYPE_DC_ONLY;
break;
}
case NVPCF_CONTROLLER_SBIOS_TABLE_CPU_TDP_CONTROL_DC_AC:
{
pParams->cpuTdpControlType = QBOOST_CPU_TDP_CONTROL_TYPE_DC_AC;
break;
}
default:
{
pParams->cpuTdpControlType = QBOOST_CPU_TDP_CONTROL_TYPE_DC_ONLY;
break;
}
}
}
pParams->version = (NvU8)header.version;
pParams->samplingPeriodmS = CONTROLLER_GRP_DEFAULT_BASE_SAMPLING_PERIOD_MS;
*pEntryCount = (NvU8)header.entryCount;

4
src/nvidia/src/kernel/vgpu/rpc.c
View File

@@ -9698,6 +9698,8 @@ NV_STATUS rpcDumpProtobufComponent_v18_12
if (IS_GSP_CLIENT(pGpu))
{
rpc_dump_protobuf_component_v18_12 *rpc_params = &rpc_message->dump_protobuf_component_v18_12;
const NvU32 fixed_param_size = sizeof(rpc_message_header_v) + sizeof(*rpc_params);
NV_ASSERT_OR_RETURN(fixed_param_size <= pRpc->maxRpcSize, NV_ERR_INVALID_STATE);
status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT,
sizeof(*rpc_params));
@@ -9709,7 +9711,7 @@ NV_STATUS rpcDumpProtobufComponent_v18_12
rpc_params->countOnly = ((pPrbEnc->flags & PRB_COUNT_ONLY) != 0);
rpc_params->bugCheckCode = pNvDumpState->bugCheckCode;
rpc_params->internalCode = pNvDumpState->internalCode;
rpc_params->bufferSize = NV_MIN(pRpc->maxRpcSize, prbEncBufLeft(pPrbEnc));
rpc_params->bufferSize = NV_MIN(pRpc->maxRpcSize - fixed_param_size, prbEncBufLeft(pPrbEnc));
status = _issueRpcAndWait(pGpu, pRpc);