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535.43.02

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This commit is contained in:
Andy Ritger
2023-05-30 10:11:36 -07:00
parent 6dd092ddb7
commit eb5c7665a1
1403 changed files with 295367 additions and 86235 deletions
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14
src/common/inc/displayport/displayport.h
View File

@@ -97,6 +97,7 @@ typedef enum
typedef enum
{
// enum value unit = 270M
linkBW_1_62Gbps = 0x06,
linkBW_2_16Gbps = 0x08,
linkBW_2_43Gbps = 0x09,
@@ -104,7 +105,6 @@ typedef enum
linkBW_3_24Gbps = 0x0C,
linkBW_4_32Gbps = 0x10,
linkBW_5_40Gbps = 0x14,
linkBW_6_75Gbps = 0x19,
linkBW_8_10Gbps = 0x1E,
linkBW_Supported
} DP_LINK_BANDWIDTH;
@@ -119,11 +119,9 @@ typedef enum
linkSpeedId_2_43Gbps = 0x05,
linkSpeedId_3_24Gbps = 0x06,
linkSpeedId_4_32Gbps = 0x07,
linkSpeedId_6_75Gbps = 0x08,
linkSpeedId_Supported
} DP_LINK_SPEED_INDEX;
typedef enum
{
postCursor2_Level0 = 0,
@@ -291,7 +289,7 @@ typedef struct
NvBool bSourceControlModeSupported;
NvBool bConcurrentLTSupported;
NvBool bConv444To420Supported;
NvU8 maxTmdsClkRate;
NvU32 maxTmdsClkRate;
NvU8 maxBpc;
NvU8 maxHdmiLinkBandwidthGbps;
} PCONCaps;
@@ -477,7 +475,7 @@ typedef struct
// Multiplier constant to get link frequency in KHZ
// Maximum link rate of Main Link lanes = Value x 270M.
// To get it to KHz unit, we need to multiply 270K.
#define DP_LINK_BW_FREQUENCY_MULTIPLIER_KHZ (270*1000)
#define DP_LINK_BW_FREQUENCY_MULTIPLIER_KHZ (270*1000)
// Multiplier constant to get link rate table's in KHZ
#define DP_LINK_RATE_TABLE_MULTIPLIER_KHZ 200
@@ -553,11 +551,11 @@ typedef struct
#define IS_INTERMEDIATE_LINKBW(val) (((NvU32)(val)==linkBW_2_16Gbps) || \
((NvU32)(val)==linkBW_2_43Gbps) || \
((NvU32)(val)==linkBW_3_24Gbps) || \
((NvU32)(val)==linkBW_4_32Gbps) || \
((NvU32)(val)==linkBW_6_75Gbps))
((NvU32)(val)==linkBW_4_32Gbps))
#define IS_VALID_LINKBW(val) (IS_STANDARD_LINKBW(val) || \
#define IS_VALID_LINKBW(val) (IS_STANDARD_LINKBW(val) || \
IS_INTERMEDIATE_LINKBW(val))
//
// Phy Repeater count read from DPCD offset F0002h is an
// 8 bit value where each bit represents the total count

4
src/common/inc/gps.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -43,6 +43,8 @@
#define GPS_FUNC_GETPPM 0x00000028 // Get system power modes
#define GPS_FUNC_SETPPM 0x00000029 // Set system power modes
#define GPS_FUNC_PSHAREPARAMS 0x0000002A // Get sensor information and capabilities
#define GPS_FUNC_SETEDPPLIMITINFO 0x0000002B // Send the GPU EDPPeak limit info to platform
#define GPS_FUNC_GETEDPPLIMIT 0x0000002C // Get EDPPeak limit from platform
#define GPS_EVENT_STATUS_CHANGE 0x000000C0 // when received call GPS_FUNC_PCONTROL,
// depends on whether system is GPS enabled.

21
src/common/inc/jt.h
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@@ -90,5 +90,26 @@
#define NV_JT_FUNC_CAPS_REVISION_ID_1_03 0x00000103
#define NV_JT_FUNC_CAPS_REVISION_ID_2_00 0x00000200
//
// JT_FUNC_POWERCONTROL argument definitions (Rev 1.0)
//
//
// GPU Power Control
//
#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_CONTROL 2:0
#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_CONTROL_GSS 0x00000000
//
// JT_FUNC_POWERCONTROL return buffer definitions
//
#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE 2:0
#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE_TRANSITION 0x00000000
#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE_ON 0x00000001
#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE_OFF 0x00000002
#define NV_JT_FUNC_POWERCONTROL_GPU_GC_STATE_GC6 0x00000003
#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_STATE 3:3
#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_STATE_OFF 0x00000000
#define NV_JT_FUNC_POWERCONTROL_GPU_POWER_STATE_PWOK 0x00000001
#endif // JT_H

22
src/common/inc/nvBldVer.h
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@@ -36,26 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r531_37
#define NV_BUILD_BRANCH r535_87
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r531_37
#define NV_PUBLIC_BRANCH r535_87
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r530/r531_37-121"
#define NV_BUILD_CHANGELIST_NUM (32603126)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r535_87-122"
#define NV_BUILD_CHANGELIST_NUM (32882771)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r530/r531_37-121"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32603126)
#define NV_BUILD_NAME "rel/gpu_drv/r535/r535_87-122"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32882771)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r531_37-1"
#define NV_BUILD_CHANGELIST_NUM (32601466)
#define NV_BUILD_BRANCH_VERSION "r535_87-4"
#define NV_BUILD_CHANGELIST_NUM (32875904)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "531.40"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32601466)
#define NV_BUILD_BRANCH_BASE_VERSION R530
#define NV_BUILD_NAME "535.93"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32875904)
#define NV_BUILD_BRANCH_BASE_VERSION R535
#endif
// End buildmeister python edited section

19
src/common/inc/nvSemaphoreCommon.h
View File

@@ -63,23 +63,23 @@ ct_assert(sizeof(NvReportSemaphore) == 16);
* the CPU or submitted to be written by the GPU, which is stashed in the
* timestamp field of the semaphore by the CPU in both these cases.
*/
static inline void NvTimeSemFermiSetMaxSubmitted(
NvReportSemaphore32 *report,
static inline void NvTimeSemFermiSetMaxSubmittedVal(
volatile NvU64 *maxSubmittedPtr,
const NvU64 value)
{
NvU64 oldValue =
(NvU64)__NVatomicCompareExchange64((volatile NvS64 *)&report->timer,
(NvU64)__NVatomicCompareExchange64((volatile NvS64 *)maxSubmittedPtr,
0, 0);
// Atomically set report->timer to max(value, report->time).
while (oldValue < value) {
const NvU64 prevValue =
(NvU64)__NVatomicCompareExchange64((volatile NvS64 *)&report->timer,
(NvU64)__NVatomicCompareExchange64((volatile NvS64 *)maxSubmittedPtr,
(NvS64)value,
(NvS64)oldValue);
if (prevValue == oldValue) {
// The specified value was set. Done.
nvAssert(report->timer >= value);
nvAssert(*maxSubmittedPtr >= value);
break;
}
@@ -87,6 +87,13 @@ static inline void NvTimeSemFermiSetMaxSubmitted(
}
}
static inline void NvTimeSemFermiSetMaxSubmitted(
NvReportSemaphore32 *report,
const NvU64 value)
{
NvTimeSemFermiSetMaxSubmittedVal(&report->timer, value);
}
static inline NvU64 NvTimeSemFermiGetPayload(
NvReportSemaphore32 *report)
{
@@ -150,7 +157,7 @@ static inline void NvTimeSemFermiSetPayload(
const NvU64 payload)
{
// First save the actual value to the reserved/timer bits
NvTimeSemFermiSetMaxSubmitted(report, payload);
NvTimeSemFermiSetMaxSubmittedVal(&report->timer, payload);
// Then write the low bits to the GPU-accessible semaphore value.
report->payload = (NvU32)(payload & 0xFFFFFFFFULL);

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "530.41.03"
#define NV_VERSION_STRING "535.43.02"
#else

4
src/common/inc/swref/published/disp/v03_00/dev_disp.h
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@@ -70,4 +70,8 @@
#define NV_PDISP_RG_DPCA_FRM_CNT 31:16 /* R--UF */
#define NV_PDISP_FE_FLIPLOCK 0x0061206C /* RW-4R */
#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME 23:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP 0x00611C30 /* R--4R */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN 8:8 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_PENDING 0x00000001 /* R---V */
#endif // __v03_00_dev_disp_h__

19
src/common/inc/swref/published/disp/v04_00/dev_disp.h
View File

@@ -37,9 +37,18 @@
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_NOT_PENDING 0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_PENDING 0x00000001 /* R---V */
#define NV_PDISP_VGA_WORKSPACE_BASE 0x00625F04 /* RW-4R */
#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS 3:3 /* RWIVF */
#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_VALID 0x00000001 /* RW--V */
#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR 31:8 /* RWIVF */
#define NV_PDISP_VGA_WORKSPACE_BASE 0x00625F04 /* RW-4R */
#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS 3:3 /* RWIVF */
#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_VALID 0x00000001 /* RW--V */
#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR 31:8 /* RWIVF */
#define NV_PDISP_FE_CORE_HEAD_STATE(i) (0x00612078+(i)*2048) /* R--4A */
#define NV_PDISP_FE_CORE_HEAD_STATE_OPERATING_MODE 9:8 /* R--VF */
#define NV_PDISP_FE_CORE_HEAD_STATE_OPERATING_MODE_SLEEP 0x00000000 /* R---V */
#define NV_PDISP_FE_CORE_HEAD_STATE_OPERATING_MODE_SNOOZE 0x00000001 /* R---V */
#define NV_PDISP_FE_CORE_HEAD_STATE_OPERATING_MODE_AWAKE 0x00000002 /* R---V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING(i) (0x00611D80+(i)*4) /* RW-4A */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */
#endif // __v04_00_dev_disp_h__

4
src/common/inc/swref/published/hopper/gh100/dev_fb.h
View File

@@ -21,7 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_fb_h
#ifndef __gh100_dev_fb_h_
#define __gh100_dev_fb_h_
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO 0x00100A34 /* RW-4R */
@@ -29,4 +29,4 @@
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00100A38 /* RW-4R */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#endif // __gh100_dev_fb_h__
#endif // __gh100_dev_fb_h_

32
src/common/inc/swref/published/hopper/gh100/dev_fsp_addendum.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_fsp_addendum_h__
#define __gh100_dev_fsp_addendum_h__
#define NV_GFW_FSP_UCODE_VERSION NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(1)
#define NV_GFW_FSP_UCODE_VERSION_FULL 11:0
#define NV_GFW_FSP_UCODE_VERSION_MAJOR 11:8
#define NV_GFW_FSP_UCODE_VERSION_MINOR 7:0
#endif // __gh100_dev_fsp_addendum_h__

6
src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -64,5 +64,9 @@
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x008f0330+(i)*4) /* RW-4A */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
#endif // __gh100_dev_fsp_pri_h__

52
src/common/inc/swref/published/hopper/gh100/dev_fuse.h Normal file
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@@ -0,0 +1,52 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_fuse_h__
#define __gh100_dev_fuse_h__
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS 0x0082074C /* RW-4R */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA 0:0 /* RWIVF */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */
#define NV_FUSE_SPARE_BIT_0 0x00824E04 /* RW-4R */
#define NV_FUSE_SPARE_BIT_0_DATA 0:0 /* RWIVF */
#define NV_FUSE_SPARE_BIT_0_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_SPARE_BIT_0_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_FUSE_SPARE_BIT_0_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_FUSE_SPARE_BIT_1 0x00824E08 /* RW-4R */
#define NV_FUSE_SPARE_BIT_1_DATA 0:0 /* RWIVF */
#define NV_FUSE_SPARE_BIT_1_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_SPARE_BIT_1_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_FUSE_SPARE_BIT_1_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_FUSE_SPARE_BIT_2 0x00824E0C /* RW-4R */
#define NV_FUSE_SPARE_BIT_2_DATA 0:0 /* RWIVF */
#define NV_FUSE_SPARE_BIT_2_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_SPARE_BIT_2_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_FUSE_SPARE_BIT_2_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_FUSE_SPARE_BIT_3 0x00824E10 /* RW-4R */
#define NV_FUSE_SPARE_BIT_3_DATA 0:0 /* RWIVF */
#define NV_FUSE_SPARE_BIT_3_DATA_INIT 0x00000000 /* RWI-V */
#define NV_FUSE_SPARE_BIT_3_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_FUSE_SPARE_BIT_3_DATA_ENABLE 0x00000001 /* RW--V */
#endif // __gh100_dev_fuse_h__

13
src/common/inc/swref/published/hopper/gh100/dev_gc6_island.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,6 +24,14 @@
#ifndef __gh100_dev_gc6_island_h__
#define __gh100_dev_gc6_island_h__
#define NV_PGC6_SCI_SEC_TIMER_TIME_0 0x00118f54 /* RW-4R */
#define NV_PGC6_SCI_SEC_TIMER_TIME_0_NSEC 31:5 /* RWEUF */
#define NV_PGC6_SCI_SEC_TIMER_TIME_0_NSEC_ZERO 0x00000000 /* RWE-V */
#define NV_PGC6_SCI_SEC_TIMER_TIME_1 0x00118f58 /* RW-4R */
#define NV_PGC6_SCI_SEC_TIMER_TIME_1_NSEC 28:0 /* RWEUF */
#define NV_PGC6_SCI_SEC_TIMER_TIME_1_NSEC_ZERO 0x00000000 /* RWE-V */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0 0x00118df4 /* RW-4R */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE 0:0 /* RWEVF */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_0_UPDATE_DONE 0x00000000 /* R-E-V */
@@ -33,5 +41,8 @@
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_1 0x00118df8 /* RW-4R */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_1_NSEC 28:0 /* RWEUF */
#define NV_PGC6_SCI_SYS_TIMER_OFFSET_1_NSEC_ZERO 0x00000000 /* RWE-V */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20 0x001182cc /* RW-4R */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_DATA 31:0 /* RWIVF */
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_DATA_INIT 0x00000000 /* RWI-V */
#endif // __gh100_dev_gc6_island_h__

8
src/common/inc/swref/published/hopper/gh100/dev_gc6_island_addendum.h
View File

@@ -26,4 +26,12 @@
#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K 0x100
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1
#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0
#endif // __gh100_dev_gc6_island_addendum_h__

16
src/common/inc/swref/published/hopper/gh100/dev_vm.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-23 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -46,5 +46,19 @@
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 16 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER(i) (0x2300+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(i) (0x1000+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(i) (0x1200+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(i) (0x1400+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */
#endif // __gh100_dev_vm_h__

4
src/common/inc/swref/published/hopper/gh100/dev_vm_addendum.h
View File

@@ -50,4 +50,8 @@
//
#define NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT 0x00000081
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT_PTR NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE
#define NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI
#endif // __gh100_dev_vm_addendum_h__

9
src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h
View File

@@ -27,11 +27,20 @@
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS 0x00000004 /* RW-4R */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE 0:0 /* RWIVF */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE_ENABLE 0x00000001 /* RW--V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE 1:1 /* RWIVF */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE_DEFAULT 0x00000000 /* RWI-V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_MEM_SPACE_ENABLE 0x00000001 /* RW--V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER 2:2 /* RWIVF */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER_DISABLE 0x00000000 /* RWI-V */
#define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_BUS_MASTER_ENABLE 0x00000001 /* RW--V */
#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE 0x00000008 /* R--4R */
#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_PGM_INTERFACE 15:8 /* R-IVF */
#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_SUB_CLASSCODE 23:16 /* R-IVF */
#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE 31:24 /* R-IVF */
#define NV_EP_PCFG_GPU_REVISION_ID_AND_CLASSCODE_BASE_CLASSCODE_3D 0x00000003 /* R-I-V */
#define NV_EP_PCFG_GPU_BARREG0 0x00000010 /* RW-4R */
#define NV_EP_PCFG_GPU_BARREG0_REG_BASE_ADDRESS 31:18 /* RWIVF */
#define NV_EP_PCFG_GPU_BARREG0_REG_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_EP_PCFG_GPU_SUBSYSTEM_ID 0x0000002C /* R--4R */
#define NV_EP_PCFG_GPU_MSI_64_HEADER 0x00000048 /* RW-4R */
#define NV_EP_PCFG_GPU_MSI_64_HEADER_MSI_ENABLE 16:16 /* RWIVF */

9
src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h
View File

@@ -31,9 +31,18 @@
#define NV_XVE_DEV_CTRL_CMD_IO_SPACE 0:0 /* RWIVF */
#define NV_XVE_DEV_CTRL_CMD_IO_SPACE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_DEV_CTRL_CMD_IO_SPACE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE 1:1 /* RWIVF */
#define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_DEV_CTRL_CMD_BUS_MASTER 2:2 /* RWIVF */
#define NV_XVE_DEV_CTRL_CMD_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_DEV_CTRL_CMD_BUS_MASTER_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_REV_ID 0x00000008 /* R--4R */
#define NV_XVE_REV_ID_CLASS_CODE 31:8 /* R-CVF */
#define NV_XVE_REV_ID_CLASS_CODE_3D 0x00030200 /* ----V */
#define NV_XVE_BAR0 0x00000010 /* RW-4R */
#define NV_XVE_BAR0_BASE_ADDRESS 31:24 /* RWIVF */
#define NV_XVE_BAR0_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_XVE_SUBSYSTEM 0x0000002C /* R--4R */
#define NV_XVE_MSI_CTRL 0x00000068 /* RW-4R */
#define NV_XVE_MSI_CTRL_MSI 16:16 /* RWIVF */

10
src/common/inc/swref/published/nvswitch/lr10/dev_minion_ip_addendum.h
View File

@@ -12,17 +12,13 @@
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __lr10_dev_minion_ip_addendum_h__
#define __lr10_dev_minion_ip_addendum_h__
#define NV_MINION_NVLINK_DL_CMD_COMMAND_INITRXTXTERM 0x12
#define NV_NVLSTAT 0x00000103:0x00000000 /* RW--D */
#define NV_NVLSTAT_UC01 0x00000001 /* R--4R */
#define NV_NVLSTAT_UC01_PM_STATE 31:31 /* R---F */