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This commit is contained in:
Andy Ritger
2023-05-30 10:11:36 -07:00
parent 6dd092ddb7
commit eb5c7665a1
1403 changed files with 295367 additions and 86235 deletions
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2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000base.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000base.finn
// Source file: ctrl/ctrl0000/ctrl0000base.finn
//
#include "ctrl/ctrlxxxx.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000client.finn
// Source file: ctrl/ctrl0000/ctrl0000client.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000diag.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000diag.finn
// Source file: ctrl/ctrl0000/ctrl0000diag.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000event.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000event.finn
// Source file: ctrl/ctrl0000/ctrl0000event.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

5
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gpu.finn
// Source file: ctrl/ctrl0000/ctrl0000gpu.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
@@ -143,7 +143,8 @@ typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS {
* GPU instance numbers are assigned in bus-probe order beginning with
* zero and are limited to one less the number of GPUs in the system.
* [out] numaId
* This parameter returns the ID of NUMA node for the specified GPU.
* This parameter returns the ID of NUMA node for the specified GPU or
* the subscribed MIG partition when MIG is enabled.
* In case there is no NUMA node, NV0000_CTRL_NO_NUMA_NODE is returned.
*
* Possible status values returned are:

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpuacct.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn
// Source file: ctrl/ctrl0000/ctrl0000gpuacct.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gsync.finn
// Source file: ctrl/ctrl0000/ctrl0000gsync.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000nvd.finn
// Source file: ctrl/ctrl0000/ctrl0000nvd.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000proc.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000proc.finn
// Source file: ctrl/ctrl0000/ctrl0000proc.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000syncgpuboost.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn
// Source file: ctrl/ctrl0000/ctrl0000syncgpuboost.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

56
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
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@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000system.finn
// Source file: ctrl/ctrl0000/ctrl0000system.finn
//
#include "ctrl/ctrlxxxx.h"
@@ -296,8 +296,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
/* Generic types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U)
/* processor capabilities */
#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U)
@@ -322,47 +321,6 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
#define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000U)
#define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000U)
/* feature mask (as opposed to bugs, requirements, etc.) */
#define NV0000_CTRL_SYSTEM_CPU_CAP_FEATURE_MASK (0x1f5e7fU) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_CPU_CAP_MMX | NV0000_CTRL_SYSTEM_CPU_CAP_SSE | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW | NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 | NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE | NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING | NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_CMOV | NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH | NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 | NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE | NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 | NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 | NV0000_CTRL_SYSTEM_CPU_CAP_AVX | NV0000_CTRL_SYSTEM_CPU_CAP_ERMS)" */
/*
* NV0000_CTRL_CMD_SYSTEM_GET_CAPS
*
* This command returns the set of system capabilities in the
* form of an array of unsigned bytes. System capabilities include
* supported features and required workarounds for the system,
* each represented by a byte offset into the table and a bit
* position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the system caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_CAPS (0x103U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x3" */
typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0000_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0000_CTRL_SYSTEM_CAPS_POWER_SLI_SUPPORTED 0:0x01
/* size in bytes of system caps table */
#define NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE 1U
/*
* NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO
*
@@ -419,13 +377,13 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */
/* maximum name string length */
#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U)
#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020U)
/* invalid id */
#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU)
#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffffU)
#define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U)
@@ -1572,9 +1530,11 @@ typedef struct NV0000_CTRL_SYSTEM_GPS_CTRL_PARAMS {
* Please note: as implied above, administrator privileges are
* required to modify security settings.
*/
#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x29" */
#define NV0000_CTRL_CMD_SYSTEM_SET_SECURITY_SETTINGS (0x129U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID" */
#define GPS_MAX_COUNTERS_PER_BLOCK 32U
#define NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS_MESSAGE_ID (0x29U)
typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS {
NvU32 objHndl;
NvU32 blockId;

7
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000unix.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000unix.finn
// Source file: ctrl/ctrl0000/ctrl0000unix.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
@@ -418,8 +418,7 @@ typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS {
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM 1
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC_MC 4
#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU)

2
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn
// Source file: ctrl/ctrl0000/ctrl0000vgpu.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0002.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0002.finn
// Source file: ctrl/ctrl0002.finn
//
#include "ctrl/ctrlxxxx.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0004.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0004.finn
// Source file: ctrl/ctrl0004.finn
//
#include "ctrl/ctrlxxxx.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl000f.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl000f.finn
// Source file: ctrl/ctrl000f.finn
//
#include "ctrl/ctrlxxxx.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0020.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0020.finn
// Source file: ctrl/ctrl0020.finn
//
#include "ctrl/ctrlxxxx.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl003e.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl003e.finn
// Source file: ctrl/ctrl003e.finn
//
#include "ctrl/ctrlxxxx.h"

4
src/common/sdk/nvidia/inc/ctrl/ctrl0041.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0041.finn
// Source file: ctrl/ctrl0041.finn
//
#include "nvos.h"
@@ -378,7 +378,7 @@ typedef struct NV0041_CTRL_SURFACE_FLUSH_GPU_CACHE_PARAMS {
#define NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS_MESSAGE_ID (0x18U)
typedef struct NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS {
NvU32 pageSize; /* [out] - page size */
NV_DECLARE_ALIGNED(NvU64 pageSize, 8); /* [out] - page size */
} NV0041_CTRL_GET_MEM_PAGE_SIZE_PARAMS;
/*

180
src/common/sdk/nvidia/inc/ctrl/ctrl0050.h Normal file
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@@ -0,0 +1,180 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0050.finn
//
#include "ctrl/ctrlxxxx.h"
#define NV0050_CTRL_CMD(cat, idx) NVXXXX_CTRL_CMD(0x0050, NV0050_CTRL_##cat, idx)
#define NV0050_CTRL_RESERVED (0x00U)
#define NV0050_CTRL_MEMORY (0x01U)
#define NV0050_CTRL_CMD_NULL (0x5000U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_RESERVED_INTERFACE_ID << 8) | 0x0" */
/*
* NV0050_CTRL_CMD_MEMSET
*
* Memsets a memory allocation and releases a semaphore on completion.
*
* hMemory [IN]
* Memory handle of the memory descriptor that needs to be memset.
* This is only available for verification purposes.
*
* offset [IN]
* Offset into the memory descriptor.
*
* length [IN]
* Length of physical memory to be memset.
* Must be less than or equal to memory size.
*
* pattern [IN]
* The pattern to memset to
*
* flags [IN]
* Can be any of the NV0050_CTRL_MEMSET_FLAGS_*
* DEFAULT
* By default, the memcopy operation will be synchronous and using
* physical copies
* ASYNC
* This flag forces this memset to be asynchronous.
* VIRTUAL
* This flag forces the memset to use Virtual addresses which are
* identity mapped. To use this feature, users need to pass in the
* hVaspace with identity mapped addresses for the entire memory during
* construct.
*
* submittedWorkId [OUT]
* The work submission token users can poll on to wait for work
* completed by CE. Only valid in case of ASYNC mode.
*/
#define NV0050_CTRL_MEMSET_FLAGS_DEFAULT 0
#define NV0050_CTRL_MEMSET_FLAGS_ASYNC NVBIT(0)
#define NV0050_CTRL_MEMSET_FLAGS_VIRTUAL NVBIT(1)
#define NV0050_CTRL_CMD_MEMSET (0x500101U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8) | NV0050_CTRL_MEMSET_PARAMS_MESSAGE_ID" */
#define NV0050_CTRL_MEMSET_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0050_CTRL_MEMSET_PARAMS {
NvHandle hMemory;
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NV_DECLARE_ALIGNED(NvU64 length, 8);
NvU32 pattern;
NV_DECLARE_ALIGNED(NvU64 flags, 8);
NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8);
} NV0050_CTRL_MEMSET_PARAMS;
/*
* NV0050_CTRL_CMD_MEMCOPY
*
* Copies from a source memoryto ssdestination memory and releases a semaphore
* on completion
*
* hDstMemory [IN]
* Memory handle of the memory descriptor to which data will be copied.
* This is only available for verification purposes.
*
* hSrcMemory [IN]
* Memory handle of the memory descriptor from which data will be copied.
* This is only available for verification purposes.
*
* dstOfffset [IN]
* Offset into the destination memory descriptor.
*
* srcOffset [IN]
* Offset into the source memory descriptor.
*
* length [IN]
* Length of physical memory to be copied.
* Must be less than or equal to both destination and source memory size.
*
* flags [IN]
* Can be any of the NV0050_CTRL_MEMCOPY_FLAGS_*
* DEFAULT
* By default, the memcopy operation will be synchronous and using
* physical copies
* ASYNC
* This flag forces this memset to be asynchronous.
* VIRTUAL
* This flag forces the memset to use Virtual addresses which are
* identity mapped. To use this feature, users need to pass in the
* hVaspace with identity mapped addresses for the entire memory during
* construct.
*
* submittedWorkId [OUT]
* The work submission token users can poll on to wait for work
* completed by CE. Only valid in case of ASYNC mode.
*/
#define NV0050_CTRL_MEMCOPY_FLAGS_DEFAULT 0
#define NV0050_CTRL_MEMCOPY_FLAGS_ASYNC NVBIT(1)
#define NV0050_CTRL_MEMCOPY_FLAGS_VIRTUAL NVBIT(2)
#define NV0050_CTRL_CMD_MEMCOPY (0x500102U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8 | NV0050_CTRL_MEMCOPY_PARAMS_MESSAGE_ID)" */
#define NV0050_CTRL_MEMCOPY_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0050_CTRL_MEMCOPY_PARAMS {
NvHandle hDstMemory;
NvHandle hSrcMemory;
NV_DECLARE_ALIGNED(NvU64 dstOffset, 8);
NV_DECLARE_ALIGNED(NvU64 srcOffset, 8);
NV_DECLARE_ALIGNED(NvU64 length, 8);
NV_DECLARE_ALIGNED(NvU64 flags, 8);
NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8);
} NV0050_CTRL_MEMCOPY_PARAMS;
/*
* NV0050_CTRL_CMD_CHECK_PROGRESS
*
* Check if a previously submitted work item has been completed by HW.
*
* submittedWorkId [IN]
* The work submission token users can poll on to wait for work
* completed by CE.
*
*/
#define NV0050_CTRL_CHECK_PROGRESS_RESULT_DEFAULT 0
#define NV0050_CTRL_CHECK_PROGRESS_RESULT_FINISHED NVBIT(1)
#define NV0050_CTRL_CMD_CHECK_PROGRESS (0x500103U) /* finn: Evaluated from "(FINN_NV_CE_UTILS_UTILS_INTERFACE_ID << 8 | NV0050_CTRL_CHECK_PROGRESS_PARAMS_MESSAGE_ID)" */
#define NV0050_CTRL_CHECK_PROGRESS_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0050_CTRL_CHECK_PROGRESS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 submittedWorkId, 8);
NvU32 result;
} NV0050_CTRL_CHECK_PROGRESS_PARAMS;
/* _ctrl0050_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073.finn
// Source file: ctrl/ctrl0073.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073base.finn
// Source file: ctrl/ctrl0073/ctrl0073base.finn
//
#include "ctrl/ctrlxxxx.h"

40
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h
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@@ -23,11 +23,49 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073common.finn
// Source file: ctrl/ctrl0073/ctrl0073common.finn
//
/*
* DSC caps -
* bDscSupported
* If GPU supports DSC or not
*
* encoderColorFormatMask
* Mask of all color formats for which DSC
* encoding is supported by GPU
*
* lineBufferSizeKB
* Size of line buffer.
*
* rateBufferSizeKB
* Size of rate buffer per slice.
*
* bitsPerPixelPrecision
* Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp
*
* maxNumHztSlices
* Maximum number of horizontal slices supported by DSC encoder
*
* lineBufferBitDepth
* Bit depth used by the GPU to store the reconstructed pixels within
* the line buffer
*/
#define NV0073_CTRL_CMD_DSC_CAP_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS {
NvBool bDscSupported;
NvU32 encoderColorFormatMask;
NvU32 lineBufferSizeKB;
NvU32 rateBufferSizeKB;
NvU32 bitsPerPixelPrecision;
NvU32 maxNumHztSlices;
NvU32 lineBufferBitDepth;
} NV0073_CTRL_CMD_DSC_CAP_PARAMS;
/* _ctrl0073common_h_ */

168
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
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@@ -27,10 +27,13 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073dfp.finn
// Source file: ctrl/ctrl0073/ctrl0073dfp.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
#include "ctrl/ctrl0073/ctrl0073common.h"
#include "nvcfg_sdk.h"
/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */
@@ -84,8 +87,7 @@
* This specifies whether the displayId is capable of sending
* YCBCR444 color format out from the board.
* NV0073_CTRL_DFP_FLAGS_DP_LINK_BANDWIDTH
* This specifies whether the displayId is capable of doing high
* bit-rate (2.7Gbps) or low bit-rate (1.62Gbps) if the DFP is
* This specifies max link rate supported by the displayId, if the DFP is
* display port.
* NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED
* This specifies whether the DFP displayId is allowed to transmit HDMI
@@ -105,6 +107,8 @@
* This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode).
* NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE
* This indicates whether this DFP supports Dynamic MUX
* flags2
* This parameter returns the extra information specific to this dfp.
*
* Possible status values returned are:
* NV_OK
@@ -119,76 +123,77 @@ typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 flags;
NvU32 flags2;
} NV0073_CTRL_DFP_GET_INFO_PARAMS;
/* valid display types */
#define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U)
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U)
#define NV0073_CTRL_DFP_FLAGS_LANE 5:3
#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U)
#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U)
#define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6
#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U)
#define NV0073_CTRL_DFP_FLAGS_LINK 21:20
#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U)
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U)
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U)
@@ -569,7 +574,7 @@ typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO {
* _ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES : RM returns Active SOR which is not Audio capable.
* _ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO : RM is not returning 'Active non-audio capable SOR'.
*
* Possible status values returned are:
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
@@ -1157,40 +1162,31 @@ typedef struct NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS {
#define NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS_MESSAGE_ID (0x66U)
typedef struct NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 hActive;
NvU32 vActive;
NvU32 hFrontPorch;
NvU32 vFrontPorch;
NvU32 hBackPorch;
NvU32 vBackPorch;
NvU32 hSyncWidth;
NvU32 vSyncWidth;
NvU32 bpp;
NvU32 refresh;
NvU32 pclkHz;
NvU32 numLanes;
NvU32 dscEnable;
NvU32 dscBpp;
NvU32 dscNumSlices;
NvU32 dscDualDsc;
NvU32 dscSliceHeight;
NvU32 dscBlockPrediction;
NvU32 dscDecoderVersionMajor;
NvU32 dscDecoderVersionMinor;
NvBool dscUseCustomPPS;
NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT];
struct {
NvBool bDscSupported;
NvU32 encoderColorFormatMask;
NvU32 lineBufferSizeKB;
NvU32 rateBufferSizeKB;
NvU32 bitsPerPixelPrecision;
NvU32 maxNumHztSlices;
NvU32 lineBufferBitDepth;
} dscEncoderCaps;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 hActive;
NvU32 vActive;
NvU32 hFrontPorch;
NvU32 vFrontPorch;
NvU32 hBackPorch;
NvU32 vBackPorch;
NvU32 hSyncWidth;
NvU32 vSyncWidth;
NvU32 bpp;
NvU32 refresh;
NvU32 pclkHz;
NvU32 numLanes;
NvU32 dscEnable;
NvU32 dscBpp;
NvU32 dscNumSlices;
NvU32 dscDualDsc;
NvU32 dscSliceHeight;
NvU32 dscBlockPrediction;
NvU32 dscDecoderVersionMajor;
NvU32 dscDecoderVersionMinor;
NvBool dscUseCustomPPS;
NvU32 dscCustomPPSData[NV0073_CTRL_CMD_DFP_DSI_CUSTOM_PPS_DATA_COUNT];
NV0073_CTRL_CMD_DSC_CAP_PARAMS dscEncoderCaps;
} NV0073_CTRL_CMD_DFP_GET_DSI_MODE_TIMING_PARAMS;

67
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
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@@ -27,10 +27,13 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073dp.finn
// Source file: ctrl/ctrl0073/ctrl0073dp.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
#include "ctrl/ctrl0073/ctrl0073common.h"
#include "nvcfg_sdk.h"
/* NV04_DISPLAY_COMMON dfp-display-specific control commands and parameters */
@@ -1766,29 +1769,7 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
* bOverrideLinkBw
* Returns NV_TRUE if DFP limits defined in DCB have to be honored, else NV_FALSE
*
* DSC caps -
* bDscSupported
* If GPU supports DSC or not
*
* encoderColorFormatMask
* Mask of all color formats for which DSC
* encoding is supported by GPU
*
* lineBufferSizeKB
* Size of line buffer.
*
* rateBufferSizeKB
* Size of rate buffer per slice.
*
* bitsPerPixelPrecision
* Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp
*
* maxNumHztSlices
* Maximum number of horizontal slices supported by DSC encoder
*
* lineBufferBitDepth
* Bit depth used by the GPU to store the reconstructed pixels within
* the line buffer
* DSC caps
*
* Possible status values returned are:
* NV_OK
@@ -1802,28 +1783,20 @@ typedef struct NV0073_CTRL_CMD_DP_SEND_ACT_PARAMS {
#define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U)
typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
NvU32 subDeviceInstance;
NvU32 sorIndex;
NvU32 maxLinkRate;
NvU32 dpVersionsSupported;
NvBool bIsMultistreamSupported;
NvBool bIsSCEnabled;
NvBool bHasIncreasedWatermarkLimits;
NvBool bIsPC2Disabled;
NvBool isSingleHeadMSTSupported;
NvBool bFECSupported;
NvBool bIsTrainPhyRepeater;
NvBool bOverrideLinkBw;
struct {
NvBool bDscSupported;
NvU32 encoderColorFormatMask;
NvU32 lineBufferSizeKB;
NvU32 rateBufferSizeKB;
NvU32 bitsPerPixelPrecision;
NvU32 maxNumHztSlices;
NvU32 lineBufferBitDepth;
} DSC;
NvU32 subDeviceInstance;
NvU32 sorIndex;
NvU32 maxLinkRate;
NvU32 dpVersionsSupported;
NvU32 UHBRSupported;
NvBool bIsMultistreamSupported;
NvBool bIsSCEnabled;
NvBool bHasIncreasedWatermarkLimits;
NvBool bIsPC2Disabled;
NvBool isSingleHeadMSTSupported;
NvBool bFECSupported;
NvBool bIsTrainPhyRepeater;
NvBool bOverrideLinkBw;
NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC;
} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS;
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0
@@ -1834,7 +1807,6 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U)
@@ -1842,6 +1814,7 @@ typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U)
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U)

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h
View File

@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073dpu.finn
// Source file: ctrl/ctrl0073/ctrl0073dpu.finn
//

100
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h
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@@ -27,6 +27,104 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073event.finn
// Source file: ctrl/ctrl0073/ctrl0073event.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/* NV04_DISPLAY_COMMON event-related control commands and parameters */
/*
* NV0073_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* This command sets event notification state for the associated display
* object. This command requires that an instance of NV01_EVENT has been
* previously bound to the associated display object.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* hEvent
* This parameter specifies the handle of the NV01_EVENT instance
* to be bound to the given subDeviceInstance.
* event
* This parameter specifies the type of event to which the specified
* action is to be applied. This parameter must specify a valid
* NV0073_NOTIFIERS value (see cl0073.h for more details) and should
* not exceed one less NV0073_NOTIFIERS_MAXCOUNT.
* action
* This parameter specifies the desired event notification action.
* Valid notification actions include:
* NV0073_CTRL_SET_EVENT_NOTIFICATION_DISABLE
* This action disables event notification for the specified
* event for the associated subdevice object.
* NV0073_CTRL_SET_EVENT_NOTIFICATION_SINGLE
* This action enables single-shot event notification for the
* specified event for the associated subdevice object.
* NV0073_CTRL_SET_EVENT_NOTIFICATION_REPEAT
* This action enables repeated event notification for the specified
* event for the associated system controller object.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0073_CTRL_CMD_EVENT_SET_NOTIFICATION (0x730301U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
NvU32 subDeviceInstance;
NvHandle hEvent;
NvU32 event;
NvU32 action;
} NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000U)
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001U)
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002U)
/*
* NV0073_CTRL_CMD_EVENT_SET_NOTIFIER_MEMORY
*
* hMemory
* This parameter specifies the handle of the memory object
* that identifies the memory address translation for this
* subdevice instance's notification(s). The beginning of the
* translation points to an array of notification data structures.
* The size of the translation must be at least large enough to hold the
* maximum number of notification data structures identified by
* the NV0073_MAX_NOTIFIERS value.
* Legal argument values must be instances of the following classes:
* NV01_NULL
* NV04_MEMORY
* When hMemory specifies the NV01_NULL_OBJECT value then any existing
* memory translation connection is cleared. There must not be any
* pending notifications when this command is issued.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0073_CTRL_CMD_EVENT_SET_MEMORY_NOTIFIES (0x730303U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS {
NvU32 subDeviceInstance;
NvHandle hMemory;
} NV0073_CTRL_EVENT_SET_MEMORY_NOTIFIES_PARAMS;
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_NOTIFIED 0U
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_PENDING 1U
#define NV0073_EVENT_MEMORY_NOTIFIES_STATUS_ERROR 2U
/* _ctrl0073event_h_ */

8
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073internal.finn
// Source file: ctrl/ctrl0073/ctrl0073internal.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
@@ -37,4 +37,10 @@
typedef NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE (0x730402U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID (0x2U)
typedef NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS;
/* ctrl0073internal_h */

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073psr.finn
// Source file: ctrl/ctrl0073/ctrl0073psr.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"

14
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073specific.finn
// Source file: ctrl/ctrl0073/ctrl0073specific.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
@@ -1274,6 +1274,10 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS {
* powerState
* This parameter should be one of the valid
* NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_* values.
* headIdx
* The head id on which power operation needs to be done.
* bForceMonitorState
* Monitor power state that client wants to force in RM.
*
* Possible status values returned are:
* NV_OK
@@ -1285,9 +1289,11 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS {
#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS_MESSAGE_ID (0x95U)
typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 powerState;
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 powerState;
NvU32 headIdx;
NvBool bForceMonitorState;
} NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS;
#define NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_OFF (0x00000000U)

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073stereo.finn
// Source file: ctrl/ctrl0073/ctrl0073stereo.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h
View File

@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073svp.finn
// Source file: ctrl/ctrl0073/ctrl0073svp.finn
//

123
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073system.finn
// Source file: ctrl/ctrl0073/ctrl0073system.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
@@ -809,6 +809,42 @@ typedef struct NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS {
NvU32 availableInternalDisplaysMask;
} NV0073_CTRL_SYSTEM_GET_INTERNAL_DISPLAYS_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED
*
* This command is used to notify RM that all subdevices are ready for ACPI
* calls. The caller must make sure that the OS is ready to handle the ACPI
* calls for each ACPI ID. So, this call must be done after the OS has
* initialized all the display ACPI IDs to this subdevice.
* Besides, the ACPI spec provides a function for the display drivers to read
* the EDID directly from the SBIOS for each display's ACPI ID. This function
* is used to override the EDID found from a I2C or DPAux based transaction.
* This command will also attempt to call the ACPI _DDC function to read the
* EDID from the SBIOS for all displayIDs. If an EDID is found from this call,
* the RM will store that new EDID in the EDID buffer of that OD.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_NOT_SUPPORTED
*
*/
#define NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID (0x5CU)
typedef struct NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS {
NvU32 subDeviceInstance;
} NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS;
#define NV0073_CTRL_CMD_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED (0x73015cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_ACPI_SUBSYSTEM_ACTIVATED_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_SYSTEM_CONNECTOR_INFO
@@ -1229,6 +1265,36 @@ typedef struct NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS {
/*
* NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS
*
* This command is used to update information about VRR capable monitors
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed.This parameter must specify a value between zero and the
* total number of subdevices within the parent device.This parameter
* should be set to zero for default behavior.
*
* displayId
* DisplayId of the panel for which client wants to add or remove from VRR
* capable monitor list
*
* bAddition
* When set to NV_TRUE, signifies that the vrr monitor is to be added.
* When set to NV_FALSE, signifies that the vrr monitor is to be removed.
*
*/
#define NV0073_CTRL_CMD_SYSTEM_VRR_DISPLAY_INFO (0x730185U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS_MESSAGE_ID (0x85U)
typedef struct NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvBool bAddition;
} NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_GET_HOTPLUG_UNPLUG_STATE
*
@@ -1670,5 +1736,60 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS {
NvBool bIsSidebandSrSupported;
} NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE
*
* This command is used by client like nvkms to set up the VRR specific
* memory operation in RM such as mapping the client created shared memory
* into RM and reserving a RGline for processing of self-refresh timeout
* related calculations.
*
* Also the expectation is that the client which calls this command with parameter
* bEnable = TRUE, should also call this command with bEnable = FALSE on the
* same head when VRR needs to be disabled.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_GENERIC
*/
/*
* This is the shared structure that will be used to communicate between
* Physical RM and clients. As of now the access relies on single source of
* truth operation, i.e. only Physical RM writes into the shared location
* and client (nvkms) reads from the same location.
*
* "dataTimeStamp" field is added to capture the timestamp before and after
* updating the flip delay related data fields(all fields except "timeout").
* This timestamp will be used by clients to determine if the data got updated
* in between by RM while clients were reading it.
* As of now "timeout" field does not have such protection, as access to
* this field is only in response to notification from RM.
*/
typedef struct NV0073_CTRL_RM_VRR_SHARED_DATA {
NvU32 expectedFrameNum;
NvU32 timeout;
NV_DECLARE_ALIGNED(NvU64 flipTimeStamp, 8);
NvBool bCheckFlipTime;
NvBool bFlipTimeAdjustment;
NV_DECLARE_ALIGNED(NvU64 dataTimeStamp, 8);
} NV0073_CTRL_RM_VRR_SHARED_DATA;
#define NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE (0x73019eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID (0x9EU)
typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS {
NvU32 subDeviceInstance;
NvBool bEnable;
NvU32 head;
NvU32 height;
NvU32 maxFrameTime;
NvU32 minFrameTime;
NvHandle hMemory;
} NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS;
/* _ctrl0073system_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080.finn
// Source file: ctrl/ctrl0080.finn
//
@@ -45,7 +45,6 @@
#include "ctrl0080/ctrl0080perf.h"
#include "ctrl0080/ctrl0080msenc.h"
#include "ctrl0080/ctrl0080bsp.h"
#include "ctrl0080/ctrl0080rc.h"
#include "ctrl0080/ctrl0080nvjpg.h"
#include "ctrl0080/ctrl0080unix.h"
#include "ctrl0080/ctrl0080internal.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080base.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080base.finn
// Source file: ctrl/ctrl0080/ctrl0080base.finn
//
#include "ctrl/ctrlxxxx.h"

7
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080bif.finn
// Source file: ctrl/ctrl0080/ctrl0080bif.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
@@ -69,6 +69,7 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS {
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE_FUSE 0x4
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE 0x5
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX 0x6
#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER 0x7
/*
* NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR
@@ -138,7 +139,7 @@ typedef struct NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS {
} NV0080_CTRL_BIF_ASPM_CYA_UPDATE_PARAMS;
/*
* NV0080_CTRL_CMD_BIF_GET_PCIE_POWER_CONTROL_MASK
* NV0080_CTRL_BIF_ASPM_FEATURE
*
* pciePowerControlMask
* pciePowerControlIdentifiedKeyOrder

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h
View File

@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080bsp.finn
// Source file: ctrl/ctrl0080/ctrl0080bsp.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h
View File

@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080cipher.finn
// Source file: ctrl/ctrl0080/ctrl0080cipher.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h
View File

@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080clk.finn
// Source file: ctrl/ctrl0080/ctrl0080clk.finn
//

28
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080dma.finn
// Source file: ctrl/ctrl0080/ctrl0080dma.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
@@ -160,7 +160,7 @@ typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK {
#define NV0080_CTRL_CMD_DMA_GET_PTE_INFO (0x801801U) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS 4U
#define NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS 5U
#define NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_MESSAGE_ID (0x1U)
@@ -190,7 +190,7 @@ typedef struct NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS {
#define NV0080_CTRL_CMD_DMA_SET_PTE_INFO (0x80180aU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID" */
#define NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS 4U
#define NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS 5U
#define NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_MESSAGE_ID (0xAU)
@@ -356,9 +356,8 @@ typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS {
NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT pageTable4KFormat[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS];
NvHandle hVASpace;
NV_DECLARE_ALIGNED(NvU64 vaRangeLo, 8);
NvU32 hugePageSize;
NvU32 vaSpaceId;
NvU32 pageSize512MB;
NV_DECLARE_ALIGNED(NvU64 supportedPageSizeMask, 8);
} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS;
/*
@@ -429,7 +428,7 @@ typedef struct NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK {
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_COHERENT_MEMORY (0x00000001U)
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PTE_ADDR_SPACE_SYSTEM_NON_COHERENT_MEMORY (0x00000002U)
#define NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS 4U
#define NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS 5U
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_MESSAGE_ID (0x9U)
@@ -453,23 +452,6 @@ typedef struct NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS {
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_QUARTER 3U
#define NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_PDE_SIZE_EIGHTH 4U
/*
* NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET
*
* This command invalidates PDB target setting in hardware.
* After execeution of this command PDB target would be in undefined state.
*
* Returns error if the PDB target can not be invalidate.
*
* This call is only supported on chips fermi and later chips.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV0080_CTRL_CMD_DMA_INVALIDATE_PDB_TARGET (0x80180bU) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_DMA_INTERFACE_ID << 8) | 0xB" */
/*
* NV0080_CTRL_CMD_DMA_INVALIDATE_TLB
*

3
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080fb.finn
// Source file: ctrl/ctrl0080/ctrl0080fb.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
@@ -86,6 +86,7 @@ typedef struct NV0080_CTRL_FB_GET_CAPS_PARAMS {
#define NV0080_CTRL_FB_CAPS_OS_OWNS_HEAP_NEED_ECC_SCRUB 1:0x10
#define NV0080_CTRL_FB_CAPS_ASYNC_CE_L2_BYPASS_SET 1:0x20 // Deprecated
#define NV0080_CTRL_FB_CAPS_DISABLE_TILED_CACHING_INVALIDATES_WITH_ECC_BUG_1521641 1:0x40
#define NV0080_CTRL_FB_CAPS_GENERIC_PAGE_KIND 1:0x80
#define NV0080_CTRL_FB_CAPS_DISABLE_MSCG_WITH_VR_BUG_1681803 2:0x01
#define NV0080_CTRL_FB_CAPS_VIDMEM_ALLOCS_ARE_CLEARED 2:0x02

69
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080fifo.finn
// Source file: ctrl/ctrl0080/ctrl0080fifo.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
@@ -91,72 +91,7 @@ typedef struct NV0080_CTRL_FIFO_GET_CAPS_PARAMS {
#define NV0080_CTRL_FIFO_CAPS_SUPPORT_WDDM_INTERLEAVING 1:0x40
/* size in bytes of fifo caps table */
#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2
/*
* NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS
*
* This command enables the GPU to place various scheduling events in the
* off chip event buffer (with optional interrupt) for those GPUs that support
* it.
*
* record
* This parameter specifies a mask of event types to record.
* interrupt
* This parameter specifies a mask of event types for which to interrupt
* the CPU when the event occurs.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0080_CTRL_CMD_FIFO_ENABLE_SCHED_EVENTS (0x801703) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FIFO_INTERFACE_ID << 8) | 0x3" */
typedef struct NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS {
NvU32 record;
NvU32 interrupt;
} NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PARAMS;
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX 0:0
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_START_CTX_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX 1:1
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_END_CTX_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST 2:2
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_NEW_RUNLIST_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE 3:3
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_SEM_ACQUIRE_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT 4:4
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PAGE_FAULT_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT 5:5
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_PREEMPT_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD 6:6
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_YIELD_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX 7:7
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_IDLE_CTX_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI 8:8
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_HI_PRI_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED 9:9
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ENG_STALLED_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC 10:10
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_VSYNC_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT 11:11
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_FGCS_FAULT_ENABLE (0x00000001)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL 11:0
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_DISABLE (0x00000000)
#define NV0080_CTRL_FIFO_ENABLE_SCHED_EVENTS_ALL_ENABLE (0x00000fff)
#define NV0080_CTRL_FIFO_CAPS_TBL_SIZE 2
/*
* NV0080_CTRL_CMD_FIFO_START_SELECTED_CHANNELS

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080gpu.finn
// Source file: ctrl/ctrl0080/ctrl0080gpu.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"

12
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
View File

@@ -27,10 +27,11 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080gr.finn
// Source file: ctrl/ctrl0080/ctrl0080gr.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
#include "nvcfg_sdk.h"
typedef struct NV0080_CTRL_GR_ROUTE_INFO {
NvU32 flags;
@@ -148,14 +149,17 @@ typedef NVXXXX_CTRL_XXX_INFO NV0080_CTRL_GR_INFO;
#define NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC (0x00000032)
#define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000033)
#define NV0080_CTRL_GR_INFO_INDEX_DUMMY (0x00000033)
#define NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES (0x00000034)
/* When adding a new INDEX, please update MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
* reflects that.
*/
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000033)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x34) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
#define NV0080_CTRL_GR_INFO_INDEX_MAX (0x00000034)
#define NV0080_CTRL_GR_INFO_MAX_SIZE (0x35) /* finn: Evaluated from "(NV0080_CTRL_GR_INFO_INDEX_MAX + 1)" */
/*
* NV0080_CTRL_CMD_GR_GET_INFO

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080host.finn
// Source file: ctrl/ctrl0080/ctrl0080host.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"

30
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080internal.finn
// Source file: ctrl/ctrl0080/ctrl0080internal.finn
//
#include "nvlimits.h"
@@ -101,4 +101,30 @@ typedef struct NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS {
NvU8 powerDisconnectedGpuCount;
} NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS;
/*
* NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS
*
* This command will RC and disable channels permanently for the given clients.
*
* numClients
* Number of clients
* clientHandles
* List of client handles
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
*/
#define NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS (0x802008) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS 200U
#define NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS_MESSAGE_ID (0x08U)
typedef struct NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS {
NvU32 numClients;
NvHandle clientHandles[NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS];
} NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS;
/* ctrl0080internal_h */

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080msenc.finn
// Source file: ctrl/ctrl0080/ctrl0080msenc.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080nvjpg.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn
// Source file: ctrl/ctrl0080/ctrl0080nvjpg.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080perf.finn
// Source file: ctrl/ctrl0080/ctrl0080perf.finn
//
#define NV0080_CTRL_PERF_SLI_GPU_BOOST_SYNC_CONTROL_PARAMS_MESSAGE_ID (0x7U)

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080unix.finn
// Source file: ctrl/ctrl0080/ctrl0080unix.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl0090.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0090.finn
// Source file: ctrl/ctrl0090.finn
//

199
src/common/sdk/nvidia/inc/ctrl/ctrl00da.h Normal file
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@@ -0,0 +1,199 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl00da.finn
//
/* NV_SEMAPHORE_SURFACE control commands and parameters */
#define NV_SEMAPHORE_SURFACE_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00DA, NV00DA_CTRL_##cat, idx)
/*
* NV_SEMAPHORE_SURFACE_CTRL_CMD_REF_MEMORY
* Duplicate the memory object(s) bound to the semaphore surface into the RM
* client of the caller.
*
* The handle values are generated and returned by resource manager if the
* client specified a handle value of zero.
*
* If the semaphore surface has a valid max submitted value memory object, but
* the GPU + system do not require separate max submitted value and semaphore
* value surfaces, the handles provided by the client must be equal, and the
* handles returned by resource manager will also be equal. In such cases, the
* client must recognize that both handles correspond to a single reference to
* a single object, and hence the handle must be freed only once by the client.
*
* If the GPU does not require a max submitted value memory object, the handle
* value must be set to zero and the returned handle will always be zero as
* well.
*
* RETURNS:
* NVOS_STATUS_SUCCESS if the memory object(s) were successfully duplicated
* into the calling client.
* NVOS_STATUS_ERROR_INVALID_PARAMETER if any of the rules regarding the
* max submitted value handle value were violated.
* An error code forwarded from NvRmDupObject for any other failures.
*/
#define NV_SEMAPHORE_SURFACE_CTRL_CMD_REF_MEMORY (0xda0001) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS_MESSAGE_ID" */
#define NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS_MESSAGE_ID (0x01U)
typedef struct NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS {
NvHandle hSemaphoreMem;
NvHandle hMaxSubmittedMem;
} NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS;
/*
* NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL
* Associates a channel with the semaphore surface. All channels which will
* wait on or signal semaphores in a semaphore surface should first register
* with it to ensure proper event delivery and error handling.
*
* engineMask is a bitfield whose contents should be defined by setting bit
* index <n> to '1' if the corresponding engine index will be used. See
* cl2080.h for a list of engine indices. For example, this would indicate
* a channel making use of the engines GR0(graphics/compute), COPY0-COPY9,
* and host:
*
* NvU64 engineMask = (1ULL << NV2080_ENGINE_TYPE_GR0) |
* (1ULL << NV2080_ENGINE_TYPE_COPY0) |
* (1ULL << NV2080_ENGINE_TYPE_COPY1) |
* (1ULL << NV2080_ENGINE_TYPE_COPY2) |
* (1ULL << NV2080_ENGINE_TYPE_COPY3) |
* (1ULL << NV2080_ENGINE_TYPE_COPY4) |
* (1ULL << NV2080_ENGINE_TYPE_COPY5) |
* (1ULL << NV2080_ENGINE_TYPE_COPY6) |
* (1ULL << NV2080_ENGINE_TYPE_COPY7) |
* (1ULL << NV2080_ENGINE_TYPE_COPY8) |
* (1ULL << NV2080_ENGINE_TYPE_COPY9) |
* (1ULL << NV2080_ENGINE_TYPE_HOST);
*/
#define NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL (0xda0002) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS_MESSAGE_ID (0x02U)
typedef struct NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS {
NvHandle hClient;
NvHandle hDevice;
NvHandle hChannel;
NV_DECLARE_ALIGNED(NvU64 engineMask, 8);
} NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS;
/*
* NV_SEMAPHORE_SURFACE_CTRL_CMD_REGISTER_WAITER
* Ask RM to signal the specified OS event and/or set the semaphore to a new
* value when the value at the specified index is >= a desired value.
*
* index - Specifies the semaphore slot within the surface to which the the wait
* applies.
* waitValue - The value to wait for.
* newValue - Specifies a value to set the semaphore to automatically when the
* specified semaphore slot reaches waitValue. "0" means the semaphore
* value is not altered by this waiter.
* notificationHandle - The OS event (kernel callback or userspace event
* handle) to notify when the value is reached, or 0 if no notification
* is required.
*
* The waiter must specify at least one action.
*
* RETURNS:
* NVOS_STATUS_SUCCESS if the waitValue has not been reached and a waiter was
* successfully registered
* NVOS_STATUS_SUCCESS if the waitValue has been reached, newValue was applied,
* and notificationHandle was 0 (No notification was requested).
* NVOS_STATUS_ERROR_ALREADY_SIGNALLED if the waitValue has been reached and
* newValue was applied if it was not 0, but no notification was registered
* or generated on notificationHandle. Other notifications generated as a
* side effect of newValue being applied, if any, were generated.
* NVOS_STATUS_ERROR_STATE_IN_USE if newValue is not 0 and the specified index
* already has an auto-update value registered. No waiter is registered.
* NVOS_STATUS_ERROR_STATE_IN_USE if the specified notification handle is
* already registered as a waiter for the specified wait_value at the
* specified index.
* already has an auto-update value registered. No waiter is registered.
* NVOS_STATUS_ERROR_* miscelaneous internal errors. No waiter is registered.
*/
#define NV_SEMAPHORE_SURFACE_CTRL_CMD_REGISTER_WAITER (0xda0003) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS_MESSAGE_ID" */
#define NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS_MESSAGE_ID (0x03U)
typedef struct NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS {
NV_DECLARE_ALIGNED(NvU64 index, 8);
NV_DECLARE_ALIGNED(NvU64 waitValue, 8);
NV_DECLARE_ALIGNED(NvU64 newValue, 8);
NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8);
} NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS;
/*
* NV_SEMAPHORE_SURFACE_CTRL_CMD_SET_VALUE
* Modify a semaphore surface semaphore value, awakening any CPU waiters in
* the process. newValue must be >= the current value at the specified index.
*/
#define NV_SEMAPHORE_SURFACE_CTRL_CMD_SET_VALUE (0xda0004) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS_MESSAGE_ID" */
#define NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS_MESSAGE_ID (0x04U)
typedef struct NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 index, 8);
NV_DECLARE_ALIGNED(NvU64 newValue, 8);
} NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS;
/*
* NV_SEMAPHORE_SURFACE_CTRL_CMD_UNREGISTER_WAITER
* Remove a previously registered notification handle from an index + value
* tuple's list of waiters.
*
* index - Specifies the semaphore slot within the surface on which the waiter
* was previously registered.
* waitValue - The value the wait was registered for.
* notificationHandle - The OS event (kernel callback or userspace event
* handle) registered as a waiter.
*
* RETURNS:
* NVOS_STATUS_SUCCESS the waiter was successfully removed from the list of
* pending waiters.
* NVOS_STATUS_ERROR_* miscelaneous internal errors, or the waiter was not
* found in the list of pending waiters. The waiter may have already been
* called, or may be in a list of imminent notifications the RM is
* processing.
*/
#define NV_SEMAPHORE_SURFACE_CTRL_CMD_UNREGISTER_WAITER (0xda0005) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS_MESSAGE_ID" */
#define NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS_MESSAGE_ID (0x05U)
typedef struct NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS {
NV_DECLARE_ALIGNED(NvU64 index, 8);
NV_DECLARE_ALIGNED(NvU64 waitValue, 8);
NV_DECLARE_ALIGNED(NvU64 notificationHandle, 8);
} NV_SEMAPHORE_SURFACE_CTRL_UNREGISTER_WAITER_PARAMS;
/* _ctrl00da_h_ */

51
src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,10 +27,12 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl00f8.finn
// Source file: ctrl/ctrl00f8.finn
//
#include "ctrl/ctrlxxxx.h"
#include "ctrl90f1.h"
#include "mmu_fmt_types.h"
#define NV00F8_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00f8, NV00F8_CTRL_##cat, idx)
@@ -88,7 +90,7 @@ typedef struct NV_PHYSICAL_MEMORY_ATTRS {
typedef struct NV00F8_CTRL_GET_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 pageSize;
NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
NvU32 allocFlags;
NV_PHYSICAL_MEMORY_ATTRS physAttrs;
} NV00F8_CTRL_GET_INFO_PARAMS;
@@ -268,4 +270,47 @@ typedef struct NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS {
NV_DECLARE_ALIGNED(NV00F8_CTRL_ATTACH_MEM_INFO memInfos[NV00F8_MAX_ATTACHED_MEM_INFOS], 8);
} NV00F8_CTRL_GET_ATTACHED_MEM_PARAMS;
/*
* NV00F8_CTRL_CMD_GET_PAGE_LEVEL_INFO
*
* Queries page table information for a specific memory fabric address. This
* call is only supported for Verif platforms. This will return the same info
* as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS.
*
* offset [IN]
* Memory fabric Offset from the base address for which page table
* information is queried. This offset should be aligned to physical page
* size.
*
* numLevels [OUT]
* Number of levels populated.
*
* levels [OUT]
* Per-level information.
*
* pFmt
* Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS.
*
* levelFmt
* Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS.
*
* sublevelFmt
* Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS.
*
* aperture
* Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS.
*
* size
* Same as NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS.
*/
#define NV00F8_CTRL_CMD_GET_PAGE_LEVEL_INFO (0xf80107U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID" */
#define NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NvU32 numLevels;
NV_DECLARE_ALIGNED(NV_CTRL_VASPACE_PAGE_LEVEL levels[GMMU_FMT_MAX_LEVELS], 8);
} NV00F8_CTRL_GET_PAGE_LEVEL_INFO_PARAMS;
/* _ctrl00f8_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl00fd.finn
// Source file: ctrl/ctrl00fd.finn
//
#include "ctrl/ctrlxxxx.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl00fe.finn
// Source file: ctrl/ctrl00fe.finn
//
#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION 0:0

6
src/common/sdk/nvidia/inc/ctrl/ctrl2080.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080.finn
// Source file: ctrl/ctrl2080.finn
//
@@ -42,6 +42,8 @@
#include "ctrl2080/ctrl2080fb.h"
#include "ctrl2080/ctrl2080spdm.h"
#include "ctrl2080/ctrl2080gr.h"
#include "ctrl2080/ctrl2080bus.h"
#include "ctrl2080/ctrl2080thermal.h"
@@ -72,6 +74,7 @@
#include "ctrl2080/ctrl2080cipher.h"
#include "ctrl2080/ctrl2080fla.h"
#include "ctrl2080/ctrl2080gsp.h"
#include "ctrl2080/ctrl2080pmu.h"
#include "ctrl2080/ctrl2080grmgr.h"
@@ -82,3 +85,4 @@
#include "ctrl2080/ctrl2080unix.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080acr.h
View File

@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080acr.finn
// Source file: ctrl/ctrl2080/ctrl2080acr.finn
//

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080base.finn
// Source file: ctrl/ctrl2080/ctrl2080base.finn
//
#include "ctrl/ctrlxxxx.h"
@@ -92,6 +92,7 @@
#define NV2080_CTRL_GRMGR (0x38)
#define NV2080_CTRL_UCODE_FUZZER (0x39)
#define NV2080_CTRL_DMABUF (0x3A)
#define NV2080_CTRL_BIF (0x3B)
// per-OS categories start at highest category and work backwards
#define NV2080_CTRL_OS_WINDOWS (0x3F)

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080bios.finn
// Source file: ctrl/ctrl2080/ctrl2080bios.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobj.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn
// Source file: ctrl/ctrl2080/ctrl2080boardobj.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080boardobjgrpclasses.h
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@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn
// Source file: ctrl/ctrl2080/ctrl2080boardobjgrpclasses.finn
//

8
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080bus.finn
// Source file: ctrl/ctrl2080/ctrl2080bus.finn
//
#include "nvcfg_sdk.h"
@@ -1419,6 +1419,11 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
* NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU - connected to a CPU
*/
/*
* in either self-hosted mode or
* externally-hostedmode.
*/
#define NV2080_CTRL_CMD_BUS_GET_C2C_INFO (0x2080182b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_MESSAGE_ID" */
@@ -1545,6 +1550,7 @@ typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS {
typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS {
NvU32 connectionType;
NvU32 peerId;
NvBool bEgmPeer;
NvBool bSpaAccessOnly;
NvBool bUseUuid;
NvU32 remoteGpuId;

14
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080ce.finn
// Source file: ctrl/ctrl2080/ctrl2080ce.finn
//
@@ -98,8 +98,7 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
#define NV2080_CTRL_CE_CAPS_CE_BL_SIZE_GT_64K_SUPPORTED 0:0x80
#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 1:0x01
#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 1:0x02
#define NV2080_CTRL_CE_CAPS_CE_CC_SECURE 1:0x04
/*
* NV2080_CTRL_CE_CAPS_CE_GRCE
@@ -133,10 +132,11 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
*
* NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL
* Set if the CE supports pipelined Block Linear
*
* NV2080_CTRL_CE_CAPS_CE_CC_SECURE
* Set if the CE is capable of encryption/decryption
*/
/*
* NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK
*
@@ -298,7 +298,7 @@ typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS {
#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK (0x20802a09) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_MAX_HSHUBS 5
#define NV2080_CTRL_CE_MAX_HSHUBS 32
#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_PARAMS_MESSAGE_ID (0x9U)

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080cipher.h
View File

@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080cipher.finn
// Source file: ctrl/ctrl2080/ctrl2080cipher.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clk.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080clk.finn
// Source file: ctrl/ctrl2080/ctrl2080clk.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080clkavfs.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn
// Source file: ctrl/ctrl2080/ctrl2080clkavfs.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080dma.finn
// Source file: ctrl/ctrl2080/ctrl2080dma.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn
// Source file: ctrl/ctrl2080/ctrl2080dmabuf.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080ecc.finn
// Source file: ctrl/ctrl2080/ctrl2080ecc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080event.finn
// Source file: ctrl/ctrl2080/ctrl2080event.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h
View File

@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fan.finn
// Source file: ctrl/ctrl2080/ctrl2080fan.finn
//

347
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fb.finn
// Source file: ctrl/ctrl2080/ctrl2080fb.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -419,27 +419,6 @@ typedef struct NV2080_CTRL_FB_GET_INFO_V2_PARAMS {
NV2080_CTRL_FB_INFO fbInfoList[NV2080_CTRL_FB_INFO_MAX_LIST_SIZE];
} NV2080_CTRL_FB_GET_INFO_V2_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO
*
* This command returns tile addressing information.
*
* StartAddr
* This parameter returns BAR1 plus the size of the local FB.
* SpaceSize
* This parameter returns the BAR1 aperture size less the size of the
* local FB.
*
* Note that both parameters will contain zero if there is no system tile
* address space.
*/
#define NV2080_CTRL_CMD_FB_GET_TILE_ADDRESS_INFO (0x20801302U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2" */
typedef struct NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO {
NV_DECLARE_ALIGNED(NvU64 StartAddr, 8);
NV_DECLARE_ALIGNED(NvU64 SpaceSize, 8);
} NV2080_CTRL_FB_GET_SYSTEM_TILE_ADDRESS_SPACE_INFO;
/*
* NV2080_CTRL_CMD_FB_GET_BAR1_OFFSET
*
@@ -537,53 +516,8 @@ typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS {
} NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS;
/* valid flags parameter values */
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U)
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U)
/*
* NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED
*
* This command specifies to RM if scanout compaction feature is allowed or
* not in the current configuration. In hybrid mode when dGPU is rendering the
* image, the dGPU blit to the scanout surface happens without mGPU's
* knowledge (directly to system memory), which results in stale compacted
* data resulting in corruption.
*
* This control call can be used to disable the compaction whenever the KMD
* (client) is switching to the pref mode in Hybrid i.e., whenever there is a
* possibility of dGPU doing a blit to mGpu scanout surface. Compaction can
* be enabled when system is back in hybrid power mode as mGpu will be
* rendering the image.
*
* allowCompaction
* This parameter specifies if the display compaction feature is allowed
* or not allowed.
* immediate
* This parameter specifies whether compaction has to be enabled or
* disabled immediately (based on the value of allowCompaction field) or
* during the next modeset.
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_INVALID_PARAM_STRUCT
* NVOS_STATUS_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOWED (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xD" */ // Deprecated, removed form RM
typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS {
NvU32 allowCompaction;
NvU32 immediate;
} NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS;
/* valid allowCompaction values */
#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_ALLOW (0x00000001U)
#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_DISALLOW (0x00000000U)
/* valid immediate values */
#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_IMMEDIATE (000000001U)
#define NV2080_CTRL_CMD_FB_SET_SCANOUT_COMPACTION_NOT_IMMEDIATE (000000000U)
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U)
#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U)
/*
* NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE
@@ -628,9 +562,9 @@ typedef struct NV2080_CTRL_FB_SET_SCANOUT_COMPACTION_ALLOWED_PARAMS {
* supports it. Use this call if you want to flush a single allocation and
* you have a memory object describing the physical memory.
*/
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U
#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU)
@@ -1615,239 +1549,6 @@ typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS {
NvBool upper64KBCompbitSel;
} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPBITS64KB_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS < Deprecated >
*
* The PS (Performance Path, or Optimized path, or Per Slice version)
* of PutCompBits.
*
* @params[out] NvU32 *fcbits;
* Buffer to receive Fast Clear Bits.
* @params[out] NvU32 *compbits;
* Buffer to receive Compression Bits.
* @params[out] NvU32 *compCacheLine;
* Buffer to receive Comp Cache Line data.
* @params[in] NvU64 dataPhysicalStart;
* Start Address of Data
* @params[in] NvU64 surfaceOffset;
* Offset in the surface
* @params[in] NvU32 comptagLine;
* Compression Tag Line Number
* @params[in] NvU32 ROPTile_offset;
* Offset in the surface of the ROP tile.
* @params[in] NvBool upper64KBCompbitSel;
* Selects Upper or Lower 64K
* @params[in] NvBool getFcBits;
* Indicates if fast clear bits should be returned.
* @params[in] NvP64 derivedParams
* Actually a CompBitDerivedParams structure.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS (0x2080132eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2E" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS {
NV_DECLARE_ALIGNED(NvU32 *fcbits, 8);
NV_DECLARE_ALIGNED(NvU32 *compbits, 8);
NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8);
NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
NvU32 comptagLine;
NvU32 ROPTile_offset;
NvBool upper64KBCompbitSel;
NvBool getFcBits;
NV_DECLARE_ALIGNED(NvP64 derivedParams, 8);
} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPBITSPS_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS < Deprecated >
*
* The PS (Performance Path, or Optimized path, or Per Slice version)
* of GetCompBits.
*
* @params[in] NvU32 fcbits;
* Buffer with Fast Clear Bits to write.
* @params[in] NvU32 compbits;
* Buffer to receive Compression Bits.
* @params[in] NvBool writeFc
* Indicates of Fast Clear Bits should be written.
* @params[in] NvU32 *compCacheLine;
* Buffer to receive Comp Cache Line data.
* @params[in] NvU64 dataPhysicalStart;
* Start Address of Data
* @params[in] NvU64 surfaceOffset;
* Offset in the surface
* @params[in] NvU32 comptagLine;
* Compression Tag Line Number
* @params[in] NvU32 ROPTile_offset;
* Offset in the surface of the ROP tile.
* @params[in] NvBool upper64KBCompbitSel;
* Selects Upper or Lower 64K
* @params[in] NvP64 derivedParams
* Actually a CompBitDerivedParams structure.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS (0x2080132fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x2F" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS {
NvU32 fcbits;
NvU32 compbits;
NvBool writeFc;
NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8);
NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
NvU32 comptagLine;
NvU32 ROPTile_offset;
NvBool upper64KBCompbitSel;
NV_DECLARE_ALIGNED(NvP64 derivedParams, 8);
} NV2080_CTRL_CMD_FB_COMPBITCOPY_PUT_COMPBITSPS_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS < Deprecated >
*
* The PS (Performance Path, or Optimized path, or Per Slice version)
* of ReadCompCacheLine.
*
* @paramsNvU32 *compCacheLine;
* Buffer for Comp Cache Line Read
* @paramsNvU32 comptagLine;
* Comp Tag Line Number to read
* @paramsNvU32 partition;
* FB Partition of the desired Comp Cache Line
* @paramsNvU32 slice;
* Slice of the desired Comp Cache Line
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS (0x20801330U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x30" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS {
NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8);
NvU32 comptagLine;
NvU32 partition;
NvU32 slice;
} NV2080_CTRL_CMD_FB_COMPBITCOPY_READ_COMPCACHELINEPS_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS < Deprecated >
*
* The PS (Performance Path, or Optimized path, or Per Slice version)
* of WriteCompCacheLine.
*
* @params[in] NvU32 *compCacheLine;
* Buffer for Comp Cache Line to Write
* @params[in] NvU32 comptagLine;
* Comp Tag Line Number to Write
* @params[in] NvU32 partition;
* FB Partition of the desired Comp Cache Line
* @params[in] NvU32 slice;
* Slice of the desired Comp Cache Line
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS (0x20801331U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x31" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS {
NV_DECLARE_ALIGNED(NvU32 *compCacheLine, 8);
NvU32 comptagLine;
NvU32 partition;
NvU32 slice;
} NV2080_CTRL_CMD_FB_COMPBITCOPY_WRITE_COMPCACHELINEPS_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS < Deprecated >
*
* Used by PS (Performance Path, or Optimized path, or Per Slice version)
* to retrieve upper and lower Address of the CompCacheLine.
*
* @params[out] NvU64 *minCPUAddress;
* Minimum (lower bound) of the ComCacheLine.
* @params[out] NvU64 *minCPUAddress;
* Minimum (lower bound) of the ComCacheLine.
* @params[in] NvU32 comptagLine;
* CompTagLine to fetch the bounds of.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS (0x20801332U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x32" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 *minCPUAddress, 8);
NV_DECLARE_ALIGNED(NvU64 *maxCPUAddress, 8);
NvU32 comptagLine;
} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_COMPCACHELINE_BOUNDS_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET < Deprecated >
*
* Used by PS (Performance Path, or Optimized path, or Per Slice version)
* to retrieve partition, slice and ROP Tile Offset of the passed in
* surface location.
*
* @params[out] NvU64 *part;
* Partition in which the target part of the surface resides.
* @params[out] NvU64 *slice;
* Slice in which the target part of the surface resides.
* @params[out] NvU64 *ropTileoffset;
* Offset to the start of the ROP Tile in which the target part of
* the surface resides.
* @params[in] NvU64 *dataPhysicalStart;
* Start address of data for which part/slice/offset is desired.
* @params[in] NvU64 surfaceOffset;
* Byte offset of data for which part/slice/offset is desired.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET (0x20801333U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x33" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS {
NV_DECLARE_ALIGNED(NvU64 *part, 8);
NV_DECLARE_ALIGNED(NvU64 *slice, 8);
NV_DECLARE_ALIGNED(NvU64 *ropTileoffset, 8);
NV_DECLARE_ALIGNED(NvU64 dataPhysicalStart, 8);
NV_DECLARE_ALIGNED(NvU64 surfaceOffset, 8);
} NV2080_CTRL_CMD_FB_COMPBITCOPY_GET_PART_SLICE_OFFSET_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS < Deprecated >
*
* Used by PS (Performance Path, or Optimized path, or Per Slice version)
* to create a CompBitCopy::CompBitDerivedParams object
*
* @params[out] NvP64 derivedParams
* Actually a CompBitDerivedParams structure.
* @params[in] NvU32 comptagLine;
* Compression Tag Line Number
* @params[in] NvU32 ROPTile_offset;
* Offset in the surface of the ROP tile.
* @params[in] NvBool upper64KBCompbitSel;
* Selects Upper or Lower 64K
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS (0x20801334U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x34" */
typedef struct NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS {
NV_DECLARE_ALIGNED(NvP64 derivedParams, 8);
NvU32 comptagLine;
NvBool upper64KBCompbitSel;
} NV2080_CTRL_CMD_FB_COMPBITCOPY_ALLOC_AND_INIT_DERIVEDPARAMS_PARAMS;
/*!
* NV2080_CTRL_CMD_FB_COMPBITCOPY_SET_FORCE_BAR1 < Deprecated >
*
@@ -2876,8 +2577,9 @@ typedef struct NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS {
/*
* NV2080_CTRL_CMD_FB_GET_NUMA_INFO
*
* This control command is used by clients to get per-subdevice NUMA memory
* information as assigned by the system.
* This control command is used by clients to get per-subdevice or
* subscribed MIG partition(when MIG is enabled) NUMA memory information as
* assigned by the system.
*
* numaNodeId[OUT]
* - Specifies the NUMA node ID.
@@ -2916,4 +2618,37 @@ typedef struct NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 numaOfflineAddresses[NV2080_CTRL_FB_NUMA_INFO_MAX_OFFLINE_ADDRESSES], 8);
} NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT
*
* This control command is used by clients to get NV_SEMAPHORE_SURFACE layout/caps before allocation.
* A semaphore surface can be viewed as an array of independent semaphore entries.
*
* maxSubmittedSemaphoreValueOffset[OUT]
* - An offset of the max submitted value, relative to the semaphore surface entry start, if used.
* Used to emulate 64-bit semaphore values on chips where 64-bit semaphores are not supported.
*
* monitoredFenceThresholdOffset[OUT]
* - An offset of the monitored fence memory, relative to the semaphore surface entry start, if supported.
*
* size[OUT]
* - A size of a single semaphore surface entry.
*
* caps[OUT]
* - A mask of NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_* values.
*/
#define NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT (0x20801352U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_MONITORED_FENCE_SUPPORTED (0x00000001U)
#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_CAPS_64BIT_SEMAPHORES_SUPPORTED (0x00000002U)
#define NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS_MESSAGE_ID (0x52U)
typedef struct NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS {
NV_DECLARE_ALIGNED(NvU64 maxSubmittedSemaphoreValueOffset, 8);
NV_DECLARE_ALIGNED(NvU64 monitoredFenceThresholdOffset, 8);
NV_DECLARE_ALIGNED(NvU64 size, 8);
NvU32 caps;
} NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS;
/* _ctrl2080fb_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fifo.finn
// Source file: ctrl/ctrl2080/ctrl2080fifo.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fla.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fla.finn
// Source file: ctrl/ctrl2080/ctrl2080fla.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080flcn.finn
// Source file: ctrl/ctrl2080/ctrl2080flcn.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fuse.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080fuse.finn
// Source file: ctrl/ctrl2080/ctrl2080fuse.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gpio.finn
// Source file: ctrl/ctrl2080/ctrl2080gpio.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

55
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,7 +26,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gpu.finn
// Source file: ctrl/ctrl2080/ctrl2080gpu.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -103,11 +103,16 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY (0x00000037U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY (0x0000003aU)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY (0x0000003bU)
#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU)
#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003fU)
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000040U)
/* valid minor revision extended values */
#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U)
@@ -198,6 +203,16 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED (0x00000001U)
/* valid local EGM supported values */
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES (0x00000001U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_PEERID 31:1
/* valid self hosted values */
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SELF_HOSTED_CAPABILITY_YES (0x00000001U)
/* valid CMP (Crypto Mining Processor) SKU values */
#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU_NO (0x00000000U)
@@ -208,6 +223,10 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY_YES (0x00000001U)
/* valid resetless MIG device supported values */
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES (0x00000001U)
/*
* NV2080_CTRL_CMD_GPU_GET_INFO
*
@@ -2585,7 +2604,7 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 6U
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 8U
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 20U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U
@@ -2598,6 +2617,7 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _HALF))
#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _HALF) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_HALF))
#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _QUARTER))
#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _QUARTER) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _MINI_QUARTER))
#define NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU (DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _MEMORY_SIZE, _EIGHTH) | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _COMPUTE_SIZE, _EIGHTH))
#define NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS_MESSAGE_ID (0x74U)
@@ -3264,7 +3284,7 @@ typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_INFO {
NvU32 gfxGrCount;
NvU32 gpcCount;
NvU32 virtualGpcCount;
NvU32 grGpcCount;
NvU32 gfxGpcCount;
NvU32 veidCount;
NvU32 smCount;
NvU32 ceCount;
@@ -3322,7 +3342,7 @@ typedef struct NV2080_CTRL_GPU_DESCRIBE_PARTITIONS_PARAMS {
#define NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS_MESSAGE_ID (0x88U)
typedef struct NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS {
NvU32 maxSupportedPageSize;
NV_DECLARE_ALIGNED(NvU64 maxSupportedPageSize, 8);
} NV2080_CTRL_GPU_GET_MAX_SUPPORTED_PAGE_SIZE_PARAMS;
@@ -3720,6 +3740,9 @@ typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS {
* bEnable [IN]
* - Set to NV_TRUE if the GPU partition has been activated.
* - Set to NV_FALSE if the GPU partition will be deactivated.
* fabricPartitionId [IN]
* - Set the fabric manager partition ID dring partition activation.
* - Ignored during partition deactivation.
*
* Possible status values returned are:
* NV_OK
@@ -3735,6 +3758,7 @@ typedef struct NV2080_CTRL_GPU_GET_GFID_PARAMS {
typedef struct NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS {
NvU32 gfid;
NvBool bEnable;
NvU32 fabricPartitionId;
} NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS;
/*!
@@ -3763,6 +3787,23 @@ typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS {
NvU32 protection;
} NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR
*
* @brief This command is similar to NV2080_CTRL_CMD_GPU_SET_FABRIC_BASE_ADDR
* but will be used to set the EGM fabric base addr associated with the gpu.
* Note: For EGM FLA, we will be making use of the existing control call i.e
* NV2080_CTRL_CMD_FLA_RANGE
*
*/
#define NV2080_CTRL_CMD_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR (0x20800199U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS_MESSAGE_ID (0x99U)
typedef struct NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS {
NV_DECLARE_ALIGNED(NvU64 egmGpaFabricBaseAddr, 8);
} NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS;
/*
@@ -3788,7 +3829,7 @@ typedef struct NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS {
*/
#define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xA0U
#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC0U
#define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU)

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpumon.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn
// Source file: ctrl/ctrl2080/ctrl2080gpumon.finn
//

7
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gr.finn
// Source file: ctrl/ctrl2080/ctrl2080gr.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -256,6 +256,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
#define NV2080_CTRL_GR_INFO_INDEX_DUMMY NV0080_CTRL_GR_INFO_INDEX_DUMMY
#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080grmgr.h
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@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn
// Source file: ctrl/ctrl2080/ctrl2080grmgr.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

52
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gsp.finn
// Source file: ctrl/ctrl2080/ctrl2080gsp.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -79,4 +79,52 @@ typedef struct NV2080_CTRL_GSP_GET_FEATURES_PARAMS {
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_FALSE (0x00000000)
#define NV2080_CTRL_GSP_GET_FEATURES_UVM_ENABLED_TRUE (0x00000001)
/*
* NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS
*
* This command reports the current GSP-RM heap usage statistics.
*
* managedSize
* The total size in bytes of the underlying heap. Note that not all memory
* will be allocatable, due to fragmentation and memory allocator/tracking
* overhead.
* current
* An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to
* GSP-RM heap usage at the time this command is called.
* peak
* An NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT record corresponding to
* the "high water mark" of heap usage since GSP-RM was started.
*/
#define NV2080_CTRL_CMD_GSP_GET_RM_HEAP_STATS (0x20803602) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT
*
* This record represents a set of heap measurements at a given point in time.
*
* allocatedSize
* Allocated memory size, in bytes. This value does not include overhead used
* by the underlying allocator for padding/metadata, but does include the
* NvPort memory tracking overhead.
* usableSize
* Allocated memory size excluding all metadata, in bytes. This value does
* not include the NvPort memory tracking overhead.
* memTrackOverhead
* Allocated memory size used for NvPort memory tracking.
*/
typedef struct NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT {
NV_DECLARE_ALIGNED(NvU64 allocatedSize, 8);
NV_DECLARE_ALIGNED(NvU64 usableSize, 8);
NV_DECLARE_ALIGNED(NvU64 memTrackOverhead, 8);
NvU32 allocationCount;
} NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT;
#define NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 managedSize, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT current, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT peak, 8);
} NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS;
// _ctrl2080gsp_h_

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080hshub.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080hshub.finn
// Source file: ctrl/ctrl2080/ctrl2080hshub.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080i2c.finn
// Source file: ctrl/ctrl2080/ctrl2080i2c.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080illum.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080illum.finn
// Source file: ctrl/ctrl2080/ctrl2080illum.finn
//

404
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080internal.finn
// Source file: ctrl/ctrl2080/ctrl2080internal.finn
//
#include "nvimpshared.h"
@@ -38,6 +38,7 @@
#include "ctrl/ctrl0080/ctrl0080msenc.h" /* NV0080_CTRL_MSENC_CAPS_TBL_SIZE */
#include "ctrl/ctrl0080/ctrl0080bsp.h" /* NV0080_CTRL_BSP_CAPS_TBL_SIZE */
#include "ctrl/ctrl2080/ctrl2080fifo.h" /* NV2080_CTRL_FIFO_UPDATE_CHANNEL_INFO */
#include "ctrl/ctrl0073/ctrl0073system.h" /* NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS */
#include "ctrl/ctrl0000/ctrl0000system.h"
#include "ctrl/ctrl90f1.h"
#include "ctrl/ctrl30f1.h"
@@ -152,6 +153,9 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
* This command sends access counter buffer pages allocated by CPU-RM
* to be setup and enabled in physical RM.
*
* accessCounterIndex
* Index of access counter buffer to register.
*
* bufferSize
* Size of the access counter buffer to register.
*
@@ -167,6 +171,7 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
#define NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1DU)
typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS {
NvU32 accessCounterIndex;
NvU32 bufferSize;
NV_DECLARE_ALIGNED(NvU64 bufferPteArray[NV2080_CTRL_INTERNAL_UVM_ACCESS_CNTR_BUFFER_MAX_PAGES], 8);
} NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS;
@@ -176,39 +181,19 @@ typedef struct NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS {
*
* This command requests physical RM to disable the access counter buffer.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1E" */
/*
* NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER
*
* This command requests physical RM to service the access counter buffer.
* accessCounterIndex
* Index of access counter buffer to unregister.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_UVM_SERVICE_ACCESS_CNTR_BUFFER (0x20800a21) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x21" */
#define NV2080_CTRL_CMD_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER (0x20800a1e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE
*
* This command retrieves the access counter buffer size from physical RM.
*
* bufferSize[OUT]
* Size of the access counter buffer.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE (0x20800a29) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS_MESSAGE_ID (0x1EU)
#define NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x29U)
typedef struct NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS {
NvU32 bufferSize;
} NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS;
typedef struct NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS {
NvU32 accessCounterIndex;
} NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8
@@ -1362,7 +1347,9 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS {
NvU32 replayableFaultBufferSize;
NvU32 replayableShadowFaultBufferMetadataSize;
NvU32 nonReplayableFaultBufferSize;
NvU32 nonReplayableShadowFaultBufferMetadataSize;
} NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS;
/*!
@@ -1848,12 +1835,13 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS {
*/
#define NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 1500
#define NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES 3000
#define NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9DU)
typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS {
NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8);
NvU32 shadowFaultBufferSize;
NvU32 shadowFaultBufferMetadataSize;
NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8);
NvU32 shadowFaultBufferType;
NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8);
@@ -2288,6 +2276,25 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS {
NvU8 hshubId;
} NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG
*
* Program HSHUB for EGM peer id.
*
* egmPeerId[IN]
* EGM peer id to program in the HSHUB registers.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_HSHUB_EGM_CONFIG (0x20800a8d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS_MESSAGE_ID (0x8dU)
typedef struct NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS {
NvU32 egmPeerId;
} NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS;
/*
@@ -2880,6 +2887,8 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS {
* Handle to SYSMEM memlist object
* [in] gspFbAllocsSysOffset
* Offset in SYSMEM for GSP's FB Allocations
* [in] bEnteringGcoffState
* Value of PDB_PROP_GPU_GCOFF_STATE_ENTERING
*
* Possible status values returned are:
* NV_OK
@@ -2897,6 +2906,7 @@ typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
NvHandle hClient;
NvHandle hSysMem;
NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8);
NvBool bEnteringGcoffState;
} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS;
/*!
@@ -3211,6 +3221,8 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS
*
* bEnable [IN]
* Enable or Reset the settings
* clientLimit [IN]
* Client requested limit
*
* Possible status values returned are:
* NV_OK
@@ -3225,6 +3237,7 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_PM1_STATE_PARAMS
typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS {
NvBool bEnable;
NvU32 clientLimit;
} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_UPDATE_EDPP_LIMIT_PARAMS;
/*!
@@ -3467,4 +3480,335 @@ typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS {
NvBool gpioDirection; // out
} NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS;
/* NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA
*
* This command sets up ACPI DDC Edid data.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA (0x20800adf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID" */
/* From ACPI6.5 spec., the max size of EDID data from SBIOS(_DDC) is 512B */
#define MAX_EDID_SIZE_FROM_SBIOS 512U
typedef struct NV2080_CTRL_INTERNAL_EDID_DATA {
NvU32 status;
NvU32 acpiId;
NvU32 bufferSize;
NvU8 edidBuffer[MAX_EDID_SIZE_FROM_SBIOS];
} NV2080_CTRL_INTERNAL_EDID_DATA;
#define NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS_MESSAGE_ID (0xDFU)
typedef struct NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS {
NvU32 tableLen;
NV2080_CTRL_INTERNAL_EDID_DATA edidTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS];
} NV2080_CTRL_CMD_INTERNAL_SET_STATIC_EDID_DATA_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED
*
* This command intializes display ACPI child devices.
* This command accepts no parameters.
*
*/
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_ACPI_SUBSYSTEM_ACTIVATED (0x20800af0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF0" */
/* NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET */
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_MODESET (0x20800af1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF1" */
/* NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET */
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_MODESET (0x20800af2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xF2" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS
*
* This structure provides the params for getting GPU Fabric Probe Internal
* Info from GSP to CPU RM
*
* numProbes[OUT]
* - Number of probe requests sent
*/
#define NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF4U)
typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 numProbes, 8);
} NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO
*
* This command is used to get NV2080_CTRL_CMD_INTERNAL_GPU_FABRIC_PROBE_INFO_PARAMS
* from GSP to CPU RM.
* This command accepts NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_FABRIC_PROBE_INFO (0x208001f4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS
*
* This structure provides the params for starting GPU Fabric Probe
*
* bwMode[IN]
* - Nvlink Bandwidth mode
*/
#define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U)
typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS {
NvU8 bwMode;
} NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE
*
* This command is used to trigger start of GPU FABRIC PROBE PROCESS on GSP.
* This command accepts NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE (0x208001f5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE
*
* This command is used to trigger stop of GPU FABRIC PROBE PROCESS on GSP.
* This command accepts no parameters
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE (0x208001f6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF6" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE
*
* This command is used to trigger suspend of GPU FABRIC PROBE PROCESS on GSP.
* This command accepts no parameters
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_SUSPEND_FABRIC_PROBE (0x208001f7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF7" */
/*!
* NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS
*
* This structure provides the params for resuming GPU Fabric Probe
*
* bwMode[IN]
* - Nvlink Bandwidth mode
*/
#define NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF8U)
typedef struct NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS {
NvU8 bwMode;
} NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE
*
* This command is used to trigger resume of GPU FABRIC PROBE PROCESS on GSP.
* This command accepts NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_RESUME_FABRIC_PROBE (0x208001f8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_RESUME_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE
*
* This command is used to invalidate/reset GPU_FABRIC_PROBE_INFO on GSP.
* This command accepts no parameters
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GPU_INVALIDATE_FABRIC_PROBE (0x208001f9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xF9" */
/*!
* NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO
*
* This command is an internal command sent from Kernel RM to Physical RM
* to get static conf compute info
*
* bIsBar1Trusted: [OUT]
* Is BAR1 trusted to access CPR
* bIsPcieTrusted: [OUT]
* Is PCIE trusted to access CPR
*/
#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO (0x20800af3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS_MESSAGE_ID (0xF3U)
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS {
NvBool bIsBar1Trusted;
NvBool bIsPcieTrusted;
} NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP
*
* This command is used by CPU-RM to perform memory operations using GSP
*
*
* Possible status values returned are:
* NV_OK
* NVOS_STATUS_TIMEOUT_RETRY
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP (0x20800afa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_MEMMGR_MEMORY_OP {
NV2080_CTRL_MEMMGR_MEMORY_OP_MEMCPY = 0,
NV2080_CTRL_MEMMGR_MEMORY_OP_MEMSET = 1,
} NV2080_CTRL_MEMMGR_MEMORY_OP;
typedef struct NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO {
/*!
* Base physical address of the surface
*/
NV_DECLARE_ALIGNED(NvU64 baseAddr, 8);
/*!
* Size of the surface in bytes
*/
NV_DECLARE_ALIGNED(NvU64 size, 8);
/*!
* Offset in bytes into the surface where read/write must happen
*/
NV_DECLARE_ALIGNED(NvU64 offset, 8);
/*!
* Aperture where the surface is allocated
*/
NvU32 aperture;
/*!
* CPU caching attribute of the surface
*/
NvU32 cpuCacheAttrib;
} NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO;
#define NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS_MESSAGE_ID (0xFAU)
typedef struct NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS {
/*!
* Source surface info
*/
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO src, 8);
/*!
* Destination surface info
*/
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_TRANSFER_SURFACE_INFO dst, 8);
/*!
* Size of the data to be transferred
*/
NV_DECLARE_ALIGNED(NvU64 transferSize, 8);
/*!
* To be set in case of memset
*/
NvU32 value;
/*!
* Memory op to be performed
*/
NV2080_CTRL_MEMMGR_MEMORY_OP memop;
} NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG
*
* This command is an internal command sent from Kernel RM to Physical RM
* to get local GPU's ATS config
*
* addrSysPhys : [OUT]
* System Physical Address
* addrWidth : [OUT]
* Address width value
* mask : [OUT]
* Mask value
* maskWidth : [OUT]
* Mask width value
*/
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG (0x20800afb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFBU)
typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS {
NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8);
NvU32 addrWidth;
NvU32 mask;
NvU32 maskWidth;
} NV2080_CTRL_INTERNAL_MEMSYS_GET_LOCAL_ATS_CONFIG_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG
*
* This command is an internal command sent from Kernel RM to Physical RM
* to set peer ATS config using the parameters passed in.
*
* peerId : [IN]
* Peer Id of the peer for which ATS config is to be programmed
* addrSysPhys : [IN]
* System Physical Address
* addrWidth : [IN]
* Address width value
* mask : [IN]
* Mask value
* maskWidth : [IN]
* Mask width value
*/
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG (0x20800afc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS_MESSAGE_ID (0xFCU)
typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS {
NvU32 peerId;
NV_DECLARE_ALIGNED(NvU64 addrSysPhys, 8);
NvU32 addrWidth;
NvU32 mask;
NvU32 maskWidth;
} NV2080_CTRL_INTERNAL_MEMSYS_SET_PEER_ATS_CONFIG_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO
*
* Get GPU EDPpeak Limit information
*
* limitMin [OUT]
* Minimum allowed limit value on EDPp policy on both AC and DC
* limitRated [OUT]
* Rated/default allowed limit value on EDPp policy on AC
* limitMax [OUT]
* Maximum allowed limit value on EDPp policy on AC
* limitCurr [OUT]
* Current resultant limit effective on EDPp policy on AC and DC
* limitBattRated [OUT]
* Default/rated allowed limit on EDPp policy on DC
* limitBattMax [OUT]
* Maximum allowed limit on EDPp policy on DC
*
* Possible status values returned are:
* NV_OK
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO (0x20800afd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS_MESSAGE_ID (0xFDU)
typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS {
NvU32 limitMin;
NvU32 limitRated;
NvU32 limitMax;
NvU32 limitCurr;
NvU32 limitBattRated;
NvU32 limitBattMax;
} NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_PARAMS;
/* ctrl2080internal_h */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080lpwr.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn
// Source file: ctrl/ctrl2080/ctrl2080lpwr.finn
//

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080mc.finn
// Source file: ctrl/ctrl2080/ctrl2080mc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -79,7 +79,6 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GA100 (0x00000170)
/* valid ARCHITECTURE_T23X implementation values */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080nvd.finn
// Source file: ctrl/ctrl2080/ctrl2080nvd.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

20
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn
// Source file: ctrl/ctrl2080/ctrl2080nvlink.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
@@ -2097,6 +2097,7 @@ typedef struct NV2080_CTRL_NVLINK_UPDATE_HSHUB_MUX_PARAMS {
typedef struct NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS {
NvU32 peerId;
NvU32 peerLinkMask;
NvBool bEgmPeer;
NvBool bNvswitchConn;
} NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRE_SETUP_NVLINK_PEER (0x2080301dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
@@ -2972,5 +2973,22 @@ typedef struct NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP (0x20803043U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG
*
* This command is to check if a GPU has a reduced nvlink configuration
*
* [out] bReducedNvlinkConfig
* Link number which the sequence should be triggered
*/
#define NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID (0x44U)
typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
NvBool bReducedNvlinkConfig;
} NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803044U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
/* _ctrl2080nvlink_h_ */

4
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080perf.finn
// Source file: ctrl/ctrl2080/ctrl2080perf.finn
//
#include "nvfixedtypes.h"
@@ -460,7 +460,7 @@ typedef NV2080_CTRL_GPUMON_SAMPLES NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMP
#define NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL 72
#define NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE \
NV_SIZEOF32(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \
sizeof(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE) * \
NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL
/*!

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn
// Source file: ctrl/ctrl2080/ctrl2080perf_cf.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.h
View File

@@ -25,7 +25,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn
// Source file: ctrl/ctrl2080/ctrl2080perf_cf_pwr_model.finn
//

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmgr.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn
// Source file: ctrl/ctrl2080/ctrl2080pmgr.finn
//

32
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080rc.h → src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h
View File

@@ -1,5 +1,6 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -25,33 +26,16 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0080/ctrl0080rc.finn
// Source file: ctrl/ctrl2080/ctrl2080pmu.finn
//
#include "ctrl/ctrl0080/ctrl0080base.h"
/* NV01_DEVICE_XX/NV03_DEVICE gpu control commands and parameters */
/*
* NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK
#include "nvtypes.h"
/*!
* @file
*
* This command prevents RM from using callbacks when resetting a channel due
* to a page fault.
*
* Possible status return values are:
* NV_OK
* @brief Enumeration of all PMU RMCTRL identifiers.
*/
#define NV0080_CTRL_CMD_RC_DISABLE_RESET_CHANNEL_CALLBACK (0x801d01) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x1" */
/*
* NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK
*
* This command permits RM to use callbacks when resetting a channel due
* to a page fault.
*
* Possible status return values are:
* NV_OK
*/
#define NV0080_CTRL_CMD_RC_ENABLE_RESET_CHANNEL_CALLBACK (0x801d02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_RC_INTERFACE_ID << 8) | 0x2" */
/* _ctrl0080rc_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn
// Source file: ctrl/ctrl2080/ctrl2080pmumon.finn
//

93
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080power.h
View File

@@ -27,6 +27,97 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080power.finn
// Source file: ctrl/ctrl2080/ctrl2080power.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
/*!
* @brief GC6 flavor ids
*/
typedef enum NV2080_CTRL_GC6_FLAVOR_ID {
NV2080_CTRL_GC6_FLAVOR_ID_MSHYBRID = 0,
NV2080_CTRL_GC6_FLAVOR_ID_OPTIMUS = 1,
NV2080_CTRL_GC6_FLAVOR_ID_MAX = 4,
} NV2080_CTRL_GC6_FLAVOR_ID;
/*
* NV2080_CTRL_CMD_GC6_ENTRY
*
* This command executes the steps of GC6 entry sequence
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED (non-fatal)
* NV_ERR_INVALID_STATE (non-fatal)
* NV_ERR_INVALID_ARGUMENT (non-fatal)
* NV_ERR_NOT_READY (non-fatal)
* NV_ERR_TIMEOUT
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_GC6_ENTRY (0x2080270d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID << 8) | NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GC6_ENTRY_PARAMS_MESSAGE_ID (0xDU)
typedef struct NV2080_CTRL_GC6_ENTRY_PARAMS {
NV2080_CTRL_GC6_FLAVOR_ID flavorId;
NvU32 stepMask;
struct {
NvBool bIsRTD3Transition;
NvBool bIsRTD3CoreRailPowerCut;
NvBool bSkipPstateSanity;
} params;
} NV2080_CTRL_GC6_ENTRY_PARAMS;
/*
* NV2080_CTRL_CMD_GC6_EXIT
*
* This command executes the steps of GC6 exit sequence
*
* Possible status return values are:
* NV_OK
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_GC6_EXIT (0x2080270e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_INTERFACE_ID << 8) | NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GC6_EXIT_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_GC6_EXIT_PARAMS {
NV2080_CTRL_GC6_FLAVOR_ID flavorId;
struct {
NvBool bIsGpuSelfWake;
NvBool bIsRTD3Transition;
NvBool bIsRTD3HotTransition; //output
} params;
} NV2080_CTRL_GC6_EXIT_PARAMS;
/*!
* @brief GC6 step ids
*/
typedef enum NV2080_CTRL_GC6_STEP_ID {
NV2080_CTRL_GC6_STEP_ID_SR_ENTRY = 0,
NV2080_CTRL_GC6_STEP_ID_GPU_OFF = 1,
NV2080_CTRL_GC6_STEP_ID_MAX = 2,
} NV2080_CTRL_GC6_STEP_ID;
typedef struct NV2080_CTRL_GC6_FLAVOR_INFO {
NV2080_CTRL_GC6_FLAVOR_ID flavorId;
NvU32 stepMask;
} NV2080_CTRL_GC6_FLAVOR_INFO;
/* _ctrl2080power_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h
View File

@@ -27,7 +27,7 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080rc.finn
// Source file: ctrl/ctrl2080/ctrl2080rc.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"

255
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h Normal file
View File

@@ -0,0 +1,255 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080spdm.finn
//
/*************************** SPDM COMMANDS ************************************/
/*!
* @brief SPDM Command Types
*
*/
#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
#define RSVD7_SIZE 16
#define RSVD8_SIZE 2
/*!
* Guest RM must send RM_GSP_SPDM_CMD_ID_CC_INIT to GSP-RM before SPDM session start
*/
typedef struct RM_GSP_SPDM_CC_INIT_CTX {
NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc
NvU8 dmaIdx; // To indicate DMA engine which DMA idx is needed
NvU64_ALIGN32 dmaAddr; // The address RM allocate in SYS memory or FB memory.
NvU32 addrSpace; // The memory type allocated by RM (SYS or FB ...)
NvU32 regionId; // If memory is in WPR, this is a WPR id.
NvU32 rmBufferSizeInByte; // The memort size allocated by RM(exclude NV_SPDM_DESC_HEADER)
} RM_GSP_SPDM_CC_INIT_CTX;
typedef struct RM_GSP_SPDM_CC_INIT_CTX *PRM_GSP_SPDM_CC_INIT_CTX;
/*!
* Guest RM provides INIT context
*/
typedef struct RM_GSP_SPDM_CMD_CC_INIT {
// Command must be first as this struct is the part of union
NvU8 cmdType;
RM_GSP_SPDM_CC_INIT_CTX ccInitCtx;
} RM_GSP_SPDM_CMD_CC_INIT;
typedef struct RM_GSP_SPDM_CMD_CC_INIT *PRM_GSP_SPDM_CMD_CC_INIT;
#define DEINIT_FLAGS_FORCE_CLEAR (0x1)
/*!
* Guest RM must send RM_GSP_SPDM_CMD_ID_CC_DEINIT to GSP-RM to end a session
*/
typedef struct RM_GSP_SPDM_CC_DEINIT_CTX {
NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc
NvU32 endpointId; // To indicate SPDM endpoint Id
NvU32 flags;
} RM_GSP_SPDM_CC_DEINIT_CTX;
typedef struct RM_GSP_SPDM_CC_DEINIT_CTX *PRM_GSP_SPDM_CC_DEINIT_CTX;
/*!
* Guest RM provides INIT context
*/
typedef struct RM_GSP_SPDM_CMD_CC_DEINIT {
// Command must be first as this struct is the part of union
NvU8 cmdType;
RM_GSP_SPDM_CC_DEINIT_CTX ccDeinitCtx;
} RM_GSP_SPDM_CMD_CC_DEINIT;
typedef struct RM_GSP_SPDM_CMD_CC_DEINIT *PRM_GSP_SPDM_CMD_CC_DEINIT;
/*!
* RM provides SPDM message request context, include header + corresponding payload
*/
typedef struct RM_GSP_SPDM_CC_CTRL_CTX {
NvU32 version;
NvU32 guestId; // To indicate CC client Id, VM0, VM1 ... etc
NvU32 endpointId; // To indicate SPDM endpoint Id
NvU32 ctrlCode; // control code
NvU32 ctrlParam; // Associated with ctrlCode
} RM_GSP_SPDM_CC_CTRL_CTX;
typedef struct RM_GSP_SPDM_CC_CTRL_CTX *PRM_GSP_SPDM_CC_CTRL_CTX;
/*!
* RM provides the SPDM request info to GSP
*/
typedef struct RM_GSP_SPDM_CMD_CC_CTRL {
// Command must be first as this struct is the part of union
NvU8 cmdType;
RM_GSP_SPDM_CC_CTRL_CTX ccCtrlCtx;
} RM_GSP_SPDM_CMD_CC_CTRL;
typedef struct RM_GSP_SPDM_CMD_CC_CTRL *PRM_GSP_SPDM_CMD_CC_CTRL;
typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA {
// Command must be first as this struct is the part of union
NvU8 cmdType;
NvU32 rsvd0[2];
NvU32 rsvd1;
char rsvd2[4];
char rsvd3[2];
char rsvd4[5];
char rsvd5[5];
char rsvd6[2];
char rsvd7[RSVD7_SIZE];
NvU32 rsvd8[RSVD8_SIZE];
} RM_GSP_SPDM_CMD_CC_INIT_RM_DATA;
typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA *PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA;
/*!
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
* getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in
* other structures like RM_FLCN_CMD_GSP / RM_FLCN_MSG_GSP and pragma pack does not produce consistent behavior
* when paired with alignment directives on Linux and Windows.
*/
/*!
* A union of all SPDM Commands.
*/
typedef union RM_GSP_SPDM_CMD {
NvU8 cmdType;
RM_GSP_SPDM_CMD_CC_INIT ccInit;
RM_GSP_SPDM_CMD_CC_DEINIT ccDeinit;
RM_GSP_SPDM_CMD_CC_CTRL ccCtrl;
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd;
} RM_GSP_SPDM_CMD;
typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
/***************************** SPDM MESSAGES *********************************/
/*!
* SPDM Message Status
*/
/*!
* Returns the status for program CE keys to RM
*/
#define RM_GSP_SPDM_MSG_ID_CC_INIT (0x1)
#define RM_GSP_SPDM_MSG_ID_CC_DEINIT (0x2)
#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4)
/*!
* Returns the Error Status for Invalid Command
*/
#define RM_GSP_SPDM_MSG_ID_INVALID_COMMAND (0xFF)
/*!
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
* getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in
* other structures like RM_FLCN_CMD_GSP / RM_FLCN_MSG_GSP and pragma pack does not produce consistent behavior
* when paired with alignment directives on Linux and Windows.
*/
/*!
* SPDM message structure.
*/
typedef struct RM_GSP_SPDM_MSG {
NvU8 msgType;
NvU32 version;
NvU32 guestId;
NvU32 endpointId;
// status returned from GSP message infrastructure.
NvU32 status;
NvU32 rsvd1;
NvU32 rsvd2;
NvU32 rsvd3;
NvU32 rsvd4;
} RM_GSP_SPDM_MSG;
typedef struct RM_GSP_SPDM_MSG *PRM_GSP_SPDM_MSG;
/*
* NV2080_CTRL_CMD_INTERNAL_SPDM_PARTITION
*
* This command does a partition switch to SPDM partition
*
*/
#define NV2080_CTRL_INTERNAL_SPDM_PARTITION (0x20800ad9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS_MESSAGE_ID (0xD9U)
typedef struct NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS {
NvU8 index;
RM_GSP_SPDM_CMD cmd;
RM_GSP_SPDM_MSG msg;
} NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS;

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spi.h
View File

@@ -27,6 +27,6 @@
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080spi.finn
// Source file: ctrl/ctrl2080/ctrl2080spi.finn
//

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