535.43.02

src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -25,8 +25,55 @@
 #define GSP_FW_HEAP_H
 
 // Static defines for the GSP FW WPR Heap
-#define GSP_FW_HEAP_SIZE_LIBOS2            (64u << 20)
-#define GSP_FW_HEAP_SIZE_LIBOS3_BAREMETAL  (84u << 20)
-#define GSP_FW_HEAP_SIZE_LIBOS3_VGPU      (549u << 20)
+#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2                   (0 << 20)   // No FB heap usage
+#define GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3                  (20 << 20)
+
+//
+// Calibrated by observing RM init heap usage - the amount of GSP-RM heap memory
+// used during GSP-RM boot and Kernel RM initialization, up to and including the
+// first client subdevice allocation.
+//
+#define GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X               (8 << 20)   // Turing thru Ada
+#define GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100              (14 << 20)   // Hopper+
+
+//
+// Calibrated by observing RM init heap usage on GPUs with various FB sizes.
+// This seems to fit the data fairly well, but is likely inaccurate (differences
+// in heap usage are more likely correlate with GPU architecture than FB size).
+// TODO: this requires more detailed profiling and tuning.
+//
+#define GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB                  (96 << 10)   // All architectures
+
+//
+// This number is calibrated by profiling the WPR heap usage of a single
+// client channel allocation. In practice, channel allocations on newer
+// architectures are around 44KB-46KB (depending on internal memory
+// tracking overhead configured in GSP-RM).
+//
+// Note: Turing supports 4096 channels vs 2048 on Ampere+, but the heap is
+// sized to support only 2048 channels - otherwise the Turing heap balloons
+// to 176MB+ on already small-FB parts.
+//
+// Note: The 2048 channel limit is per-runlist. GSP-RM currently uses only
+// a single ChID space across all engines, because per-runlist channel RAM is
+// disabled by default in most configurations. If/once per-runlist ChID spaces
+// are used on GSP-RM, this will likely no longer be sufficient/relevant as
+// the memory that could be needed for client channel allocations will far
+// exceed the amount we can carve out for GSP-RM's heap (max ChID will no longer
+// be the limiter).
+//
+#define GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE      ((48 << 10) * 2048)   // Support 2048 channels
+
+#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT                    (549 << 20)   // Default for all VGPU configs
+
+// Min/max bounds for heap size override by regkey
+#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB                (64u)
+#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB               (256u)
+
+#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB      (84u)
+#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB     (276u)
+
+#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB          (549u)
+#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB         (1024u)
 
 #endif // GSP_FW_HEAP_H

src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h

@@ -53,6 +53,12 @@ typedef struct
     MESSAGE_QUEUE_INIT_ARGUMENTS      messageQueueInitArguments;
     GSP_SR_INIT_ARGUMENTS             srInitArguments;
     NvU32                             gpuInstance;
+
+    struct
+    {
+        NvU64                         pa;
+        NvU64                         size;
+    } profilerArgs;
 } GSP_ARGUMENTS_CACHED;
 
 #endif // GSP_INIT_ARGS_H

src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -75,7 +75,7 @@ typedef struct GspStaticConfigInfo_t
     GspSMInfo SM_info;
 
     NvBool poisonFuseEnabled;
-  
+
     NvU64 fb_length;
     NvU32 fbio_mask;
     NvU32 fb_bus_width;
@@ -100,6 +100,7 @@ typedef struct GspStaticConfigInfo_t
     NvBool bIsMobile;
     NvBool bIsGc6Rtd3Allowed;
     NvBool bIsGcOffRtd3Allowed;
+    NvBool bIsGcoffLegacyAllowed;
 
     NvU64 bar1PdeBase;
     NvU64 bar2PdeBase;
@@ -127,7 +128,10 @@ typedef struct GspStaticConfigInfo_t
     // Subdevice handle for internal RMAPI control.
     NvHandle hInternalSubdevice;
 
+    NvBool bSelfHostedMode;
     NvBool bAtsSupported;
+
+    NvBool bIsGpuUefi;
 } GspStaticConfigInfo;
 
 // Pushed from CPU-RM to GSP-RM
@@ -147,6 +151,7 @@ typedef struct GspSystemInfo
     NvU64 clPdbProperties;
     NvU32 Chipset;
     NvBool bGpuBehindBridge;
+    NvBool bMnocAvailable;
     NvBool bUpstreamL0sUnsupported;
     NvBool bUpstreamL1Unsupported;
     NvBool bUpstreamL1PorSupported;
@@ -155,6 +160,9 @@ typedef struct GspSystemInfo
     BUSINFO FHBBusInfo;
     BUSINFO chipsetIDInfo;
     ACPI_METHOD_DATA acpiMethodData;
+    NvU32 hypervisorType;
+    NvBool bIsPassthru;
+    NvU64 sysTimerOffsetNs;
 } GspSystemInfo;
 
 

src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h

@@ -65,6 +65,7 @@ typedef struct _message_queue_info
     msgqHandle             hQueue;              // Do not allow requests when hQueue is null.
     NvU32                  txSeqNum;            // Next sequence number for tx.
     NvU32                  rxSeqNum;            // Next sequence number for rx.
+    NvU32                  txBufferFull;
     NvU32                  queueIdx;            // QueueIndex used to identify which task the message is supposed to be sent to.
 } MESSAGE_QUEUE_INFO;