525.47.04

2026-01-27 19:49:47 +00:00 · 2022-12-18 11:10:28 -08:00
48 changed files with 553 additions and 268 deletions
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 # NVIDIA Linux Open GPU Kernel Module Source

 This is the source release of the NVIDIA Linux open GPU kernel modules,
-version 525.60.13.
+version 525.47.04.


 ## How to Build
@@ -17,7 +17,7 @@ as root:

 Note that the kernel modules built here must be used with GSP
 firmware and user-space NVIDIA GPU driver components from a corresponding
-525.60.13 driver release.  This can be achieved by installing
+525.47.04 driver release.  This can be achieved by installing
 the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
 option.  E.g.,

@@ -167,7 +167,7 @@ for the target kernel.
 ## Compatible GPUs

 The open-gpu-kernel-modules can be used on any Turing or later GPU
-(see the table below). However, in the 525.60.13 release,
+(see the table below). However, in the 525.47.04 release,
 GeForce and Workstation support is still considered alpha-quality.

 To enable use of the open kernel modules on GeForce and Workstation GPUs,
@@ -175,7 +175,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
 parameter to 1. For more details, see the NVIDIA GPU driver end user
 README here:

-https://us.download.nvidia.com/XFree86/Linux-x86_64/525.60.13/README/kernel_open.html
+https://us.download.nvidia.com/XFree86/Linux-x86_64/525.47.04/README/kernel_open.html

 In the below table, if three IDs are listed, the first is the PCI Device 
 ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
--- a/kernel-open/Kbuild
+++ b/kernel-open/Kbuild
@@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
 EXTRA_CFLAGS += -I$(src)
 EXTRA_CFLAGS += -Wall -MD $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
 EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
-EXTRA_CFLAGS += -DNV_VERSION_STRING=\"525.60.13\"
+EXTRA_CFLAGS += -DNV_VERSION_STRING=\"525.47.04\"

 EXTRA_CFLAGS += -Wno-unused-function

--- a/src/common/displayport/inc/dp_configcaps.h
+++ b/src/common/displayport/inc/dp_configcaps.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -245,6 +245,7 @@ namespace DisplayPort
    public:
        virtual bool             getOuiSupported() = 0;
        virtual AuxRetry::status setOuiSource(unsigned ouiId, const char * model, size_t modelNameLength, NvU8 chipRevision) = 0;
+        virtual bool             getOuiSource(unsigned &ouiId, char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision) = 0;
        virtual bool             getOuiSink(unsigned &ouiId, char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision) = 0;
    };

--- a/src/common/displayport/inc/dp_connectorimpl.h
+++ b/src/common/displayport/inc/dp_connectorimpl.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -89,6 +89,11 @@ namespace DisplayPort
        Timer * timer;                          // OS provided timer services
        Connector::EventSink * sink;            // Event Sink

+        // Cached Source OUI for restoring eDP OUI when powering up
+        unsigned cachedSourceOUI;
+        char     cachedSourceModelName[NV_DPCD_SOURCE_DEV_ID_STRING__SIZE + 1];
+        NvU8     cachedSourceChipRevision;
+
        unsigned ouiId;                                             // Sink ouiId
        char modelName[NV_DPCD_SOURCE_DEV_ID_STRING__SIZE + 1];     // Device Model-name
        bool    bIgnoreSrcOuiHandshake;                             // Skip writing source OUI
@@ -294,6 +299,8 @@ namespace DisplayPort
        bool        bEnableFastLT;
        NvU32       maxLinkRateFromRegkey;

+        bool        bEnableOuiRestoring;
+
        //
        // Latency(ms) to apply between link-train and FEC enable for bug
        // 2561206.
@@ -322,6 +329,12 @@ namespace DisplayPort
        //
        bool        bDscCapBasedOnParent;

+        //
+        // MST device connnected to dock may issue IRQ for link lost.
+        // Send PowerDown path msg to suppress that.
+        //
+        bool        bPowerDownPhyBeforeD3;
+
        void sharedInit();
        ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink);

--- a/src/common/displayport/inc/dp_linkconfig.h
+++ b/src/common/displayport/inc/dp_linkconfig.h
@@ -385,6 +385,11 @@ namespace DisplayPort
        void pbnRequired(const ModesetInfo & modesetInfo, unsigned & base_pbn, unsigned & slots, unsigned & slots_pbn)
        {
            base_pbn = pbnForMode(modesetInfo);
+            if (bEnableFEC)
+            {
+                // IF FEC is enabled, we need to consider 3% overhead as per DP1.4 spec.
+                base_pbn = (NvU32)(divide_ceil(base_pbn * 100, 97));
+            }
            slots = slotsForPBN(base_pbn);
            slots_pbn = PBNForSlots(slots);
        }
--- a/src/common/displayport/inc/dp_regkeydatabase.h
+++ b/src/common/displayport/inc/dp_regkeydatabase.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -59,6 +59,12 @@

 #define NV_DP_REGKEY_FORCE_EDP_ILR                    "DP_BYPASS_EDP_ILR_REV_CHECK"

+// Regkey to enable OUI caching/restoring in release branch.
+#define NV_DP_REGKEY_ENABLE_OUI_RESTORING             "DP_ENABLE_OUI_RESTORING"
+
+// Message to power down video stream before power down link (set D3)
+#define NV_DP_REGKEY_POWER_DOWN_PHY                   "DP_POWER_DOWN_PHY"
+
 //
 // DSC capability of downstream device should be decided based on device's own
 // and its parent's DSC capability.
@@ -96,6 +102,8 @@ struct DP_REGKEY_DATABASE
    bool  bOptLinkKeptAliveSst;
    bool  bBypassEDPRevCheck;
    bool  bDscMstCapBug3143315;
+    bool  bEnableOuiRestoring;
+    bool  bPowerDownPhyBeforeD3;
 };

 #endif //INCLUDED_DP_REGKEYDATABASE_H
--- a/src/common/displayport/src/dp_configcaps.cpp
+++ b/src/common/displayport/src/dp_configcaps.cpp
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -863,6 +863,42 @@ struct DPCDHALImpl : DPCDHAL
        return bus.write(NV_DPCD_SOURCE_IEEE_OUI, &ouiBuffer[0], sizeof ouiBuffer);
    }

+    virtual bool getOuiSource(unsigned &ouiId, char * modelName,
+                              size_t modelNameBufferSize, NvU8 & chipRevision)
+    {
+        NvU8 ouiBuffer[16];
+        int address = NV_DPCD_SOURCE_IEEE_OUI;
+
+        if (caps.revisionMajor <= 0)
+            DP_ASSERT(0 && "Something is wrong, revision major should be > 0");
+
+        // If buffer size is larger than dev_id size, the extras are not used.
+        // If buffer size is smaller, than we can only get certain bytes.
+        if (modelNameBufferSize > NV_DPCD_SOURCE_DEV_ID_STRING__SIZE)
+        {
+            modelNameBufferSize = NV_DPCD_SOURCE_DEV_ID_STRING__SIZE;
+        }
+
+        if (AuxRetry::ack != bus.read(address, &ouiBuffer[0], sizeof ouiBuffer))
+        {
+            *modelName = 0;
+            ouiId = 0;
+            chipRevision = 0;
+            return false;
+        }
+        //  The first 3 bytes are IEEE_OUI. 2 hex digits per register.
+        ouiId = ouiBuffer[0] | (ouiBuffer[1] << 8) | (ouiBuffer[2] << 16);
+
+        // Next 6 bytes are Device Identification String, copy as much as we can (limited buffer case).
+        unsigned int i;
+        for (i = 0; i < modelNameBufferSize; i++)
+            modelName[i] = ouiBuffer[3+i];
+
+        chipRevision = ouiBuffer[9];
+
+        return true;
+    }
+
    virtual bool getOuiSink(unsigned &ouiId, char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision)
    {
        NvU8 ouiBuffer[16];
--- a/src/common/displayport/src/dp_connectorimpl.cpp
+++ b/src/common/displayport/src/dp_connectorimpl.cpp
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -188,6 +188,8 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
    this->bDisableSSC                   = dpRegkeyDatabase.bSscDisabled;
    this->bEnableFastLT                 = dpRegkeyDatabase.bFastLinkTrainingEnabled;
    this->bDscMstCapBug3143315          = dpRegkeyDatabase.bDscMstCapBug3143315;
+    this->bEnableOuiRestoring           = dpRegkeyDatabase.bEnableOuiRestoring;
+    this->bPowerDownPhyBeforeD3         = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
 }

 void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -704,6 +706,13 @@ create:

    newDev->applyOUIOverrides();

+    if (main->isEDP() && this->bEnableOuiRestoring)
+    {
+        // Save Source OUI information for eDP.
+        hal->getOuiSource(cachedSourceOUI, &cachedSourceModelName[0],
+                          sizeof(cachedSourceModelName), cachedSourceChipRevision);
+    }
+
    fireEvents();
 }

@@ -1178,7 +1187,7 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
                this->isFECSupported() &&                           // If GPU supports FEC
                pDscParams &&                                       // If client sent DSC info
                pDscParams->bCheckWithDsc &&                        // If client wants to check with DSC
-                (dev && dev->isDSCPossible()) &&                    // Either device or it's parent supports DSC
+                (dev && dev->devDoingDscDecompression) &&           // Either device or it's parent supports DSC
                bFecCapable &&                                      // If path up to dsc decoding device supports FEC
                (modesetParams.modesetInfo.bitsPerComponent != 6))  // DSC doesn't support bpc = 6
            {
@@ -1239,9 +1248,13 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
                            (modesetParams.colorFormat == dpColorFormat_YCbCr444 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCr444) ||
                            (modesetParams.colorFormat == dpColorFormat_YCbCr422 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCrSimple422))
                        {
-                            if (pDscParams->forceDsc == DSC_FORCE_ENABLE)
+                            if ((pDscParams->forceDsc == DSC_FORCE_ENABLE) ||
+                                (modesetParams.modesetInfo.mode == DSC_DUAL))
                            {
-                                // If DSC is force enabled then return failure here
+                                //
+                                // If DSC is force enabled or DSC_DUAL mode is requested, 
+                                // then return failure here
+                                //
                                compoundQueryResult = false;
                                pDscParams->bEnableDsc = false;
                                return false;
@@ -1270,9 +1283,24 @@ bool ConnectorImpl::compoundQueryAttach(Group * target,
                                     (NvU32*)(PPS),
                                     (NvU32*)(&bitsPerPixelX16))) != NVT_STATUS_SUCCESS)
                {
-                    if (pDscParams->forceDsc == DSC_FORCE_ENABLE)
+                    //
+                    // If generating PPS failed 
+                    //          AND
+                    //    (DSC is force enabled
+                    //          OR
+                    //    the requested DSC mode = DUAL)
+                    //then 
+                    //    return failure here
+                    // Else 
+                    //    we will check if non DSC path is possible.
+                    //
+                    // If dsc mode = DUAL failed to generate PPS and if we pursue
+                    // non DSC path, DD will still follow 2Head1OR modeset path with 
+                    // DSC disabled, eventually leading to HW hang. Bug 3632901 
+                    //
+                    if ((pDscParams->forceDsc == DSC_FORCE_ENABLE) ||
+                        (modesetParams.modesetInfo.mode == DSC_DUAL))
                    {
-                        // If DSC is force enabled then return failure here
                        compoundQueryResult = false;
                        pDscParams->bEnableDsc = false;
                        return false;
@@ -2667,6 +2695,21 @@ bool ConnectorImpl::notifyAttachBegin(Group *                target,       // Gr
    this->bFECEnable |= bEnableFEC;
    highestAssessedLC.enableFEC(this->bFECEnable);

+    if (main->isEDP() && this->bEnableOuiRestoring)
+    {
+        // Power-up eDP and restore eDP OUI if it's powered off now.
+        bool bPanelPowerOn;
+        main->getEdpPowerData(&bPanelPowerOn, NULL);
+        if (!bPanelPowerOn)
+        {
+            main->configurePowerState(true);
+            hal->setOuiSource(cachedSourceOUI,
+                              &cachedSourceModelName[0],
+                              6 /* string length of ieeeOuiDevId */,
+                              cachedSourceChipRevision);
+        }
+    }
+
    // if failed, we're guaranteed that assessed link rate didn't meet the mode requirements
    // isZombie() will catch this
    bLinkTrainingStatus = trainLinkOptimized(getMaxLinkConfig());
@@ -3248,6 +3291,22 @@ void ConnectorImpl::powerdownLink(bool bPowerdownPanel)
    powerOff.lanes = 0;
    // Inform Sink about Main Link Power Down.

+    if (linkUseMultistream() && bPowerDownPhyBeforeD3)
+    {
+        PowerDownPhyMessage powerDownPhyMsg;
+        NakData nack;
+
+        for (Device * i = enumDevices(0); i; i=enumDevices(i))
+        {
+            if (i->isPlugged() && i->isVideoSink())
+            {
+                Address devAddress = ((DeviceImpl*)i)->address;
+                powerDownPhyMsg.set(devAddress.parent(), devAddress.tail(), NV_TRUE);
+                this->messageManager->send(&powerDownPhyMsg, nack);
+            }
+        }
+    }
+
    //
    // 1> If it is eDP and the power is not on, we don't need to put it into D3 here
    // 2> If FEC is enabled then we have to put panel in D3 after powering down mainlink
--- a/src/common/displayport/src/dp_deviceimpl.cpp
+++ b/src/common/displayport/src/dp_deviceimpl.cpp
@@ -920,23 +920,31 @@ void DeviceImpl::applyOUIOverrides()
            if ((buffer[3] == 0x53) && (buffer[4] == 0x59) && (buffer[5] == 0x4E) && (buffer[6] == 0x41))
            {
                // For Synaptic VMM5331 and VMM5320, it only support MSA-Over-MST for DP after Firmware 5.4.5
-                if (buffer[7] == 0x53 &&
-                    (buffer[8] == 0x31 || buffer[8] == 0x20))
+                if (buffer[7] == 0x53)
                {
-                    this->bSdpExtCapable = False;
+                    //
+                    // This flag will be checked only in DSC Pass through cases (MST).
+                    // All Synaptics VMM53XX chips which support pass through can only support
+                    // color formats that are listed in 0x69h even in pass through mode.
+                    //
                    this->bDscPassThroughColorFormatWar = true;
-
-                    //
-                    // Check firmware version
-                    // 0x50A: FW/SW Major Revision.
-                    // 0x50B: FW/SW Minor Revision.
-                    // 0x50C: Build Number.
-                    //
-                    if ((buffer[10] >= 0x06) ||
-                        ((buffer[10] == 0x05) && (buffer[11] >= 0x05)) ||
-                        ((buffer[10] == 0x05) && (buffer[11] == 0x04) && (buffer[12] >= 0x05)))
+            
+                    if ((buffer[8] == 0x31) || (buffer[8] == 0x20))
                    {
-                        this->bSdpExtCapable = True;
+                        this->bSdpExtCapable = False;
+
+                        //
+                        // Check firmware version
+                        // 0x50A: FW/SW Major Revision.
+                        // 0x50B: FW/SW Minor Revision.
+                        // 0x50C: Build Number.
+                        //
+                        if ((buffer[10] >= 0x06) ||
+                            ((buffer[10] == 0x05) && (buffer[11] >= 0x05)) ||
+                            ((buffer[10] == 0x05) && (buffer[11] == 0x04) && (buffer[12] >= 0x05)))
+                        {
+                            this->bSdpExtCapable = True;
+                        }
                    }
                }
            }
--- a/src/common/displayport/src/dp_evoadapter.cpp
+++ b/src/common/displayport/src/dp_evoadapter.cpp
@@ -93,7 +93,9 @@ const struct
    {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_MST,          &dpRegkeyDatabase.bOptLinkKeptAliveMst,            DP_REG_VAL_BOOL},
    {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST,          &dpRegkeyDatabase.bOptLinkKeptAliveSst,            DP_REG_VAL_BOOL},
    {NV_DP_REGKEY_FORCE_EDP_ILR,                    &dpRegkeyDatabase.bBypassEDPRevCheck,              DP_REG_VAL_BOOL},
-    {NV_DP_DSC_MST_CAP_BUG_3143315,                 &dpRegkeyDatabase.bDscMstCapBug3143315,            DP_REG_VAL_BOOL}
+    {NV_DP_DSC_MST_CAP_BUG_3143315,                 &dpRegkeyDatabase.bDscMstCapBug3143315,            DP_REG_VAL_BOOL},
+    {NV_DP_REGKEY_ENABLE_OUI_RESTORING,             &dpRegkeyDatabase.bEnableOuiRestoring,             DP_REG_VAL_BOOL},
+    {NV_DP_REGKEY_POWER_DOWN_PHY,                   &dpRegkeyDatabase.bPowerDownPhyBeforeD3,           DP_REG_VAL_BOOL}
 };

 EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :
--- a/src/common/displayport/src/dp_watermark.cpp
+++ b/src/common/displayport/src/dp_watermark.cpp
@@ -852,21 +852,16 @@ bool DisplayPort::isModePossibleMSTWithFEC

 unsigned DisplayPort::pbnForMode(const ModesetInfo & modesetInfo)
 {
+    // When DSC is enabled consider depth will multiplied by 16 
+    unsigned dsc_factor = modesetInfo.bEnableDsc ? 16 : 1;
+
    //
    // Calculate PBN in terms of 54/64 mbyte/sec
    // round up by .6% for spread de-rate. Note: if we're not spreading our link
    // this MUST still be counted.  It's also to allow downstream links to be spread.
    //
    unsigned pbnForMode = (NvU32)(divide_ceil(modesetInfo.pixelClockHz * modesetInfo.depth * 1006 * 64 / 8,
-                                    (NvU64)54000000 *1000));
-
-    if(modesetInfo.bEnableDsc)
-    {
-        //
-        // When DSC is enabled consider depth will multiplied by 16 and also 3% FEC Overhead
-        // as per DP1.4 spec
-        pbnForMode = (NvU32)(divide_ceil(pbnForMode * 100, 97 * DSC_DEPTH_FACTOR));
-    }
+                                    (NvU64)54000000 * 1000 * dsc_factor));

    return pbnForMode;
 }
--- a/src/common/inc/nvBldVer.h
+++ b/src/common/inc/nvBldVer.h
@@ -36,25 +36,25 @@
 // and then checked back in. You cannot make changes to these sections without
 // corresponding changes to the buildmeister script
 #ifndef NV_BUILD_BRANCH
-    #define NV_BUILD_BRANCH             r526_91
+    #define NV_BUILD_BRANCH             VK526_25
 #endif
 #ifndef NV_PUBLIC_BRANCH
-    #define NV_PUBLIC_BRANCH             r526_91
+    #define NV_PUBLIC_BRANCH             VK526_25
 #endif

 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
-#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r525/r526_91-183"
-#define NV_BUILD_CHANGELIST_NUM         (32139144)
+#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r525/VK526_25-147"
+#define NV_BUILD_CHANGELIST_NUM         (32211804)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "rel/gpu_drv/r525/r526_91-183"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32139144)
+#define NV_BUILD_NAME                   "rel/gpu_drv/r525/VK526_25-147"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32211804)

 #else     /* Windows builds */
-#define NV_BUILD_BRANCH_VERSION         "r526_91-9"
-#define NV_BUILD_CHANGELIST_NUM         (32103636)
+#define NV_BUILD_BRANCH_VERSION         "VK526_25-7"
+#define NV_BUILD_CHANGELIST_NUM         (32211804)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "527.27"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32103636)
+#define NV_BUILD_NAME                   "527.86"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32211804)
 #define NV_BUILD_BRANCH_BASE_VERSION    R525
 #endif
 // End buildmeister python edited section
--- a/src/common/inc/nvUnixVersion.h
+++ b/src/common/inc/nvUnixVersion.h
@@ -4,7 +4,7 @@
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
    (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)

-#define NV_VERSION_STRING               "525.60.13"
+#define NV_VERSION_STRING               "525.47.04"

 #else

--- a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c
+++ b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c
@@ -1,5 +1,5 @@
 /*******************************************************************************
-    Copyright (c) 2019-2022 NVidia Corporation
+    Copyright (c) 2019-2020 NVidia Corporation

    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to
--- a/src/common/nvswitch/common/inc/soe/soeifcore.h
+++ b/src/common/nvswitch/common/inc/soe/soeifcore.h
@@ -70,7 +70,18 @@ enum
    /*!
     * Set NPORT TPROD state
     */
-    RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE
+    RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE,
+
+    /*!
+     * Read VRs
+     * Needed to be in sync with chips_a defines
+     */
+    RM_SOE_CORE_CMD_GET_VOLTAGE_VALUES,
+
+    /*!
+     * Init PLM2 protected registers
+     */
+    RM_SOE_CORE_CMD_INIT_L2_STATE
 };

 // Timeout for SOE reset callback function
@@ -132,6 +143,11 @@ typedef struct
    NvU32  nport;
 } RM_SOE_CORE_CMD_NPORT_TPROD_STATE;

+typedef struct
+{
+    NvU8   cmdType;
+} RM_SOE_CORE_CMD_L2_STATE;
+
 typedef union
 {
    NvU8 cmdType;
@@ -141,5 +157,6 @@ typedef union
    RM_SOE_CORE_CMD_NPORT_RESET nportReset;
    RM_SOE_CORE_CMD_NPORT_STATE nportState;
    RM_SOE_CORE_CMD_NPORT_TPROD_STATE nportTprodState;
+    RM_SOE_CORE_CMD_L2_STATE l2State;
 } RM_SOE_CORE_CMD;
 #endif  // _SOECORE_H_
--- a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h
+++ b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h
@@ -119,6 +119,7 @@
    _op(NvlStatus, nvswitch_deassert_link_reset,    (nvswitch_device *device, nvlink_link *link), _arch)  \
    _op(NvBool,    nvswitch_is_soe_supported,       (nvswitch_device *device), _arch)  \
    _op(NvlStatus, nvswitch_init_soe, (nvswitch_device *device), _arch)  \
+    _op(void,      nvswitch_soe_init_l2_state,       (nvswitch_device *device), _arch) \
    _op(NvBool,    nvswitch_is_inforom_supported,   (nvswitch_device *device), _arch)  \
    _op(NvBool,    nvswitch_is_spi_supported,       (nvswitch_device *device), _arch)  \
    _op(NvBool,    nvswitch_is_smbpbi_supported,   (nvswitch_device *device), _arch)  \
--- a/src/common/nvswitch/kernel/inc/lr10/soe_lr10.h
+++ b/src/common/nvswitch/kernel/inc/lr10/soe_lr10.h
@@ -62,4 +62,5 @@ void nvswitch_soe_unregister_events_lr10(nvswitch_device *device);
 void nvswitch_therm_soe_callback_lr10(nvswitch_device *device, union RM_FLCN_MSG *pMsg,
         void *pParams, NvU32 seqDesc, NV_STATUS status);
 NvlStatus nvswitch_soe_register_event_callbacks_lr10(nvswitch_device *device);
+void      nvswitch_soe_init_l2_state_lr10(nvswitch_device *device);
 #endif //_SOE_LR10_H_
--- a/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h
+++ b/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h
@@ -42,5 +42,6 @@ void      nvswitch_soe_unregister_events_ls10(nvswitch_device *device);
 NvlStatus nvswitch_soe_register_event_callbacks_ls10(nvswitch_device *device);
 NvlStatus nvswitch_soe_restore_nport_state_ls10(nvswitch_device *device, NvU32 nport);
 NvlStatus nvswitch_soe_issue_nport_reset_ls10(nvswitch_device *device, NvU32 nport);
+void      nvswitch_soe_init_l2_state_ls10(nvswitch_device *device);

 #endif //_SOE_LS10_H_
--- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
+++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
@@ -272,8 +272,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
   0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9, 
   0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd, 
   0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f, 
-   0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0, 
-   0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, 
+   0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0, 
+   0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, 
   0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d, 
   0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01, 
   0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206, 
@@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
   0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b, 
   0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2, 
   0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc, 
-   0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043, 
+   0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043, 
   0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200, 
   0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d, 
   0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4, 
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
   0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
   0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
   0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
-   0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xa1f0af45, 0xc2521354, 0x427cca67, 0x3b102336, 
-   0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xcdd28e1e, 0x6000ae0f, 0x492dfb26, 0x422cf074, 
+   0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x62f5c2c4, 0xc41c2f31, 0x9af0cbcc, 0xb7efe098, 
+   0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x5f24a73a, 0x55cea6d1, 0x59205a69, 0x18a31f2d, 
   0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
   0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
   0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
--- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
+++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
@@ -272,8 +272,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
   0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9, 
   0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd, 
   0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f, 
-   0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0, 
-   0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, 
+   0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0, 
+   0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, 
   0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d, 
   0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01, 
   0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206, 
@@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
   0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b, 
   0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2, 
   0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc, 
-   0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043, 
+   0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043, 
   0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200, 
   0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d, 
   0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4, 
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
   0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
   0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
   0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
-   0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xa1f0af45, 0xc2521354, 0x427cca67, 0x3b102336, 
-   0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xcdd28e1e, 0x6000ae0f, 0x492dfb26, 0x422cf074, 
+   0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x62f5c2c4, 0xc41c2f31, 0x9af0cbcc, 0xb7efe098, 
+   0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x5f24a73a, 0x55cea6d1, 0x59205a69, 0x18a31f2d, 
   0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
   0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
   0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
--- a/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c
+++ b/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c
@@ -493,7 +493,7 @@ _nvswitch_inforom_read_file
    nvswitch_os_memset(pDmaBuf, 0, transferSize);

    cmdSeqDesc = 0;
-    nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout);
+    nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout);
    status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&soeCmd, NULL, NULL,
                                          SOE_RM_CMDQ_LOG_ID, &cmdSeqDesc, &timeout);
    if (status != NV_OK)
@@ -591,7 +591,8 @@ _nvswitch_inforom_write_file
    }

    cmdSeqDesc = 0;
-    nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout);
+
+    nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout);
    status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&soeCmd, NULL, NULL,
                                          SOE_RM_CMDQ_LOG_ID, &cmdSeqDesc, &timeout);
    if (status != NV_OK)
--- a/src/common/nvswitch/kernel/lr10/lr10.c
+++ b/src/common/nvswitch/kernel/lr10/lr10.c
@@ -6791,6 +6791,8 @@ nvswitch_post_init_device_setup_lr10
        NVSWITCH_PRINT(device, SETUP, "Skipping INFOROM init\n");
    }

+    nvswitch_soe_init_l2_state(device);
+
    return NVL_SUCCESS;
 }

--- a/src/common/nvswitch/kernel/lr10/soe_lr10.c
+++ b/src/common/nvswitch/kernel/lr10/soe_lr10.c
@@ -872,6 +872,17 @@ nvswitch_init_soe_lr10
    return status;
 }

+void
+nvswitch_soe_init_l2_state_lr10
+(
+    nvswitch_device *device
+)
+{
+    NVSWITCH_PRINT(device, WARN,
+        "%s: Function not implemented on lr10\n",
+        __FUNCTION__);
+}
+
 /**
 * @brief  SOE construct
 *
--- a/src/common/nvswitch/kernel/ls10/inforom_ls10.c
+++ b/src/common/nvswitch/kernel/ls10/inforom_ls10.c
@@ -178,7 +178,7 @@ nvswitch_bbx_unload_ls10
    NVSWITCH_TIMEOUT           timeout;

    pFlcn = device->pSoe->pFlcn;
-    nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout);
+    nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout);

    nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd));
    bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR;
@@ -217,7 +217,7 @@ nvswitch_bbx_load_ls10
    NVSWITCH_TIMEOUT           timeout;

    pFlcn = device->pSoe->pFlcn;
-    nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout);
+    nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout);

    nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd));
    bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR;
--- a/src/common/nvswitch/kernel/ls10/intr_ls10.c
+++ b/src/common/nvswitch/kernel/ls10/intr_ls10.c
@@ -455,6 +455,8 @@ _nvswitch_initialize_nport_interrupts_ls10
    nvswitch_device *device
 )
 {
+// Moving this L2 register access to SOE. Refer bug #3747687 
+#if 0 
    NvU32 val;

    val =
@@ -462,6 +464,7 @@ _nvswitch_initialize_nport_interrupts_ls10
        DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 1) |
        DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 1);
    NVSWITCH_NPORT_BCAST_WR32_LS10(device, _NPORT, _ERR_CONTROL_COMMON_NPORT, val);
+#endif // 0

    _nvswitch_initialize_route_interrupts(device);
    _nvswitch_initialize_ingress_interrupts(device);
@@ -494,7 +497,10 @@ _nvswitch_initialize_nxbar_interrupts_ls10
        DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_SIDEBAND_PARITY_ERROR, 1) |
        DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_REDUCTION_PKT_ERROR, 1);

+// Moving this L2 register access to SOE. Refer bug #3747687
+#if 0
    NVSWITCH_BCAST_WR32_LS10(device, NXBAR, _NXBAR_TILE, _ERR_FATAL_INTR_EN, report_fatal);
+#endif // 0

    chip_device->intr_mask.tile.fatal = report_fatal;
    chip_device->intr_mask.tile.nonfatal = 0;
@@ -509,7 +515,10 @@ _nvswitch_initialize_nxbar_interrupts_ls10
        DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, 1)  |
        DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _EGRESS_CDT_PARITY_ERROR, 1);

+// Moving this L2 register access to SOE. Refer bug #3747687 
+#if 0
    NVSWITCH_BCAST_WR32_LS10(device, NXBAR, _NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, report_fatal);
+#endif // 0

    chip_device->intr_mask.tileout.fatal = report_fatal;
    chip_device->intr_mask.tileout.nonfatal = 0;
--- a/src/common/nvswitch/kernel/ls10/ls10.c
+++ b/src/common/nvswitch/kernel/ls10/ls10.c
@@ -2841,14 +2841,21 @@ nvswitch_is_smbpbi_supported_ls10
    nvswitch_device *device
 )
 {
-    NvU64       version;
-    NvlStatus   status;
-
    if (!nvswitch_is_smbpbi_supported_lr10(device))
    {
        return NV_FALSE;
    }

+    //
+    // Temporary driver WAR to disable SMBPBI on the LS10 NVSwitch driver.
+    // This should be removed once 3875091 is resolved.
+    //
+    return NV_FALSE;
+
+#if 0
+    NvU64       version;
+    NvlStatus   status;
+
    status = _nvswitch_get_bios_version(device, &version);
    if (status != NVL_SUCCESS)
    {
@@ -2867,6 +2874,7 @@ nvswitch_is_smbpbi_supported_ls10
            "SMBPBI is not supported on NVSwitch BIOS version %llx.\n", version);
        return NV_FALSE;
    }
+#endif
 }

 /*
@@ -4216,6 +4224,8 @@ _nvswitch_init_nport_ecc_control_ls10
    nvswitch_device *device
 )
 {
+// Moving this L2 register access to SOE. Refer bug #3747687 
+#if 0 
    // Set ingress ECC error limits
    NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER,
        DRF_NUM(_INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER, _ERROR_COUNT, 0x0));
@@ -4274,6 +4284,7 @@ _nvswitch_init_nport_ecc_control_ls10

    NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _SOURCETRACK, _ERR_ECC_CTRL,
        DRF_DEF(_SOURCETRACK, _ERR_ECC_CTRL, _CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE, __PROD));
+#endif // 0
 }

 NvlStatus
@@ -4306,6 +4317,8 @@ nvswitch_init_nport_ls10

    _nvswitch_init_nport_ecc_control_ls10(device);

+// Moving this L2 register access to SOE. Refer bug #3747687 
+#if 0 
    if (DRF_VAL(_SWITCH_REGKEY, _ATO_CONTROL, _DISABLE, device->regkeys.ato_control) ==
        NV_SWITCH_REGKEY_ATO_CONTROL_DISABLE_TRUE)
    {
@@ -4329,7 +4342,7 @@ nvswitch_init_nport_ls10
                DRF_NUM(_TSTATE, _ATO_TIMER_LIMIT, _LIMIT, timeout));
        }
    }
-
+#endif // 0
    if (DRF_VAL(_SWITCH_REGKEY, _STO_CONTROL, _DISABLE, device->regkeys.sto_control) ==
        NV_SWITCH_REGKEY_STO_CONTROL_DISABLE_TRUE)
    {
@@ -4366,17 +4379,7 @@ nvswitch_init_nxbar_ls10
    nvswitch_device *device
 )
 {
-    NvlStatus status = NVL_SUCCESS;
-
-    status = nvswitch_apply_prod_nxbar_ls10(device);
-    if (status != NVL_SUCCESS)
-    {
-        NVSWITCH_PRINT(device, ERROR,
-            "%s: NXBAR PRODs failed\n",
-            __FUNCTION__);
-        return status;
-    }
-
+    NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__);
    return NVL_SUCCESS;
 }

--- a/src/common/nvswitch/kernel/ls10/soe_ls10.c
+++ b/src/common/nvswitch/kernel/ls10/soe_ls10.c
@@ -364,6 +364,57 @@ nvswitch_set_nport_tprod_state_ls10
    return NVL_SUCCESS;
 }

+/*
+ * @Brief : INIT L2 register state in SOE
+ *
+ * @param[in] device
+ * @param[in] nport
+ */
+void
+nvswitch_soe_init_l2_state_ls10
+(
+    nvswitch_device *device
+)
+{
+    FLCN            *pFlcn;
+    NvU32            cmdSeqDesc = 0;
+    NV_STATUS        status;
+    RM_FLCN_CMD_SOE  cmd;
+    NVSWITCH_TIMEOUT timeout;
+    RM_SOE_CORE_CMD_L2_STATE *pL2State;
+
+    if (!nvswitch_is_soe_supported(device))
+    {
+        NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported. skipping!\n",
+                       __FUNCTION__);
+        return;
+    }
+
+    pFlcn       = device->pSoe->pFlcn;
+
+    nvswitch_os_memset(&cmd, 0, sizeof(cmd));
+    cmd.hdr.unitId = RM_SOE_UNIT_CORE;
+    cmd.hdr.size   = sizeof(cmd);
+
+    pL2State = &cmd.cmd.core.l2State;
+    pL2State->cmdType = RM_SOE_CORE_CMD_INIT_L2_STATE;
+
+    nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
+    status = flcnQueueCmdPostBlocking(device, pFlcn,
+                                      (PRM_FLCN_CMD)&cmd,
+                                      NULL,                 // pMsg
+                                      NULL,                 // pPayload
+                                      SOE_RM_CMDQ_LOG_ID,
+                                      &cmdSeqDesc,
+                                      &timeout);
+    if (status != NV_OK)
+    {
+        NVSWITCH_PRINT(device, ERROR, "%s: Failed to send INIT_L2_STATE command to SOE, status 0x%x\n", 
+                       __FUNCTION__, status);
+    }
+}
+
+
 /*
 * @Brief : Init sequence for SOE FSP RISCV image
 *
--- a/src/common/nvswitch/kernel/ls10/sugen_ls10.c
+++ b/src/common/nvswitch/kernel/ls10/sugen_ls10.c
@@ -706,8 +706,8 @@ nvswitch_apply_prod_nxbar_ls10
    nvswitch_device *device
 )
 {
-    
-
+// Moving this L2 register access to SOE. Refer bug #3747687 
+#if 0 
    // .NXBAR PROD value application
    
    NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _CTRL0,
@@ -724,6 +724,7 @@ nvswitch_apply_prod_nxbar_ls10
                      DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, __PROD) |
                      DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_NON_BURSTY_PKT, __PROD) |
                      DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_NON_STICKY_PKT, __PROD));
+#endif // 0
    
    NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG,
                      DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _DI_DT_SKEW_VAL, __PROD) |
@@ -742,7 +743,9 @@ nvswitch_apply_prod_nxbar_ls10
    
    NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG1,
                      DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG1, _MONITOR_CG_EN, __PROD));
-    
+
+// Moving this L2 register access to SOE. Refer bug #3747687 
+#if 0
    NVSWITCH_ENG_WR32(device, TILE, _BCAST, 0, _NXBAR_TILE, _CTRL0,
                      DRF_DEF(_NXBAR_TILE, _CTRL0, _MULTI_VALID_XFN_CTRL, _ENABLE) |
                      DRF_DEF(_NXBAR_TILE, _CTRL0, _PARTIAL_RAM_WR_CTRL, _ENABLE) |
@@ -760,7 +763,7 @@ nvswitch_apply_prod_nxbar_ls10
                      DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_PKT_PARITY_ERROR, __PROD) |
                      DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_REDUCTION_PKT_ERROR, __PROD) |
                      DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_SIDEBAND_PARITY_ERROR, __PROD));
-    
+#endif  // 0
    NVSWITCH_ENG_WR32(device, TILE, _BCAST, 0, _NXBAR_TILE, _PRI_NXBAR_TILE_CG,
                      DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _DI_DT_SKEW_VAL, __PROD) |
                      DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _HALT_CG_EN, __PROD) |
@@ -801,7 +804,8 @@ nvswitch_nvs_top_prod_ls10
    NvU32   i;

    // .NVS_TOP PROD application
-    
+ // Moving this L2 register access to SOE. Refer bug #3747687 
+#if 0 
    NVSWITCH_ENG_WR32(device, CLKS_P0,  , 0, _CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG,
                      DRF_DEF(_CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, _CFGSM, __PROD));
    
@@ -813,7 +817,7 @@ nvswitch_nvs_top_prod_ls10
    
    NVSWITCH_ENG_WR32(device, CLKS_P0,  , 3, _CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG,
                      DRF_DEF(_CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, _CFGSM, __PROD));
-    
+#endif // 0
    NVSWITCH_ENG_WR32(device, GIN,  , 0, _CTRL, _PRI_CTRL_CG1,
                      DRF_DEF(_CTRL, _PRI_CTRL_CG1, _SLCG_CTRLPRI, __PROD) |
                      DRF_DEF(_CTRL, _PRI_CTRL_CG1, _SLCG_MSIX, __PROD));
@@ -855,16 +859,21 @@ nvswitch_nvs_top_prod_ls10
    NVSWITCH_ENG_WR32(device, PTIMER,  , 0, _PTIMER, _PRI_TMR_CG1,
                      DRF_DEF(_PTIMER, _PRI_TMR_CG1, _MONITOR_CG_EN, __PROD) |
                      DRF_DEF(_PTIMER, _PRI_TMR_CG1, _SLCG, __PROD));
-    
+
+// Moving this L2 register access to SOE. Refer bug #3747687 
+#if 0 
    NVSWITCH_ENG_WR32(device, SAW,  , 0, _NVLSAW, _CTRL_CLOCK_GATING,
                      DRF_DEF(_NVLSAW, _CTRL_CLOCK_GATING, _CG1_SLCG_PCIE, __PROD) |
                      DRF_DEF(_NVLSAW, _CTRL_CLOCK_GATING, _CG1_SLCG_SAW, __PROD));
-    
+#endif // 0
    NVSWITCH_ENG_WR32(device, SAW,  , 0, _NVLSAW, _GLBLLATENCYTIMERCTRL,
                      DRF_DEF(_NVLSAW, _GLBLLATENCYTIMERCTRL, _ENABLE, __PROD));
-    
+// Moving this L2 register access to SOE. Refer bug #3747687 
+#if 0     
    NVSWITCH_ENG_WR32(device, SAW,  , 0, _NVLSAW, _PCIE_PRI_CLOCK_GATING,
                      DRF_DEF(_NVLSAW, _PCIE_PRI_CLOCK_GATING, _CG1_SLCG, __PROD));
+#endif // 0
+
    NVSWITCH_REG_WR32(device, _PSE, _CG1,
                           DRF_DEF(_PSE, _CG1, _SLCG, __PROD));
    
--- a/src/common/nvswitch/kernel/nvswitch.c
+++ b/src/common/nvswitch/kernel/nvswitch.c
@@ -743,6 +743,15 @@ nvswitch_init_soe
    return device->hal.nvswitch_init_soe(device);
 }

+void
+nvswitch_soe_init_l2_state
+(
+    nvswitch_device *device
+)
+{
+    device->hal.nvswitch_soe_init_l2_state(device);
+}
+
 static NvlStatus
 _nvswitch_construct_soe
 (
--- a/src/common/sdk/nvidia/inc/class/cla084_notification.h
+++ b/src/common/sdk/nvidia/inc/class/cla084_notification.h
@@ -39,7 +39,8 @@ extern "C" {
 #define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_CRASHED         (2)
 #define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_LOADED              (3)
 #define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_UNLOADED            (4)
-#define NVA084_NOTIFIERS_MAXCOUNT                               (5)
+#define NVA084_NOTIFIERS_EVENT_PRINT_ERROR_MESSAGE              (5)
+#define NVA084_NOTIFIERS_MAXCOUNT                               (6)

 #define NVA084_NOTIFICATION_STATUS_IN_PROGRESS              (0x8000)
 #define NVA084_NOTIFICATION_STATUS_BAD_ARGUMENT             (0x4000)
--- a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h
+++ b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h
@@ -28,6 +28,7 @@

 #include "inforom/ifrecc.h"
 #include "inforom/ifrdem.h"
+#include "inforom/omsdef.h"

 #define INFOROM_OBD_OBJECT_V1_XX_PACKED_SIZE 128

--- a/src/nvidia/arch/nvalloc/common/inc/inforom/omsdef.h
+++ b/src/nvidia/arch/nvalloc/common/inc/inforom/omsdef.h
@@ -35,6 +35,29 @@
 #define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE_NO    0
 #define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE_YES   1

+#define INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY_DATA_RESERVED               23:2
+#define INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY_DATA_ENTRY_CHECKSUM        31:24
+
+typedef struct INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY
+{
+    inforom_U032 data;
+    inforom_U032 clockLimitMin;
+    inforom_U032 clockLimitMax;
+} INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY;
+
+#define INFOROM_OMS_OBJECT_V1G_NUM_SETTINGS_ENTRIES 8
+
+typedef struct INFOROM_OMS_OBJECT_V1G
+{
+    INFOROM_OBJECT_HEADER_V1_00 header;
+    inforom_U032                lifetimeRefreshCount;
+    INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY settings[
+        INFOROM_OMS_OBJECT_V1G_NUM_SETTINGS_ENTRIES];
+    inforom_U032                reserved;
+} INFOROM_OMS_OBJECT_V1G;
+
+#define INFOROM_OMS_OBJECT_V1G_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "26d"
+
 #define INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY_DATA_RESERVED                7:2
 #define INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY_DATA_ENTRY_CHECKSUM         15:8

@@ -62,15 +85,24 @@ typedef struct INFOROM_OMS_V1S_DATA
    INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY *pNext;
 } INFOROM_OMS_V1S_DATA;

+typedef struct INFOROM_OMS_V1G_DATA
+{
+    INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY *pIter;
+    INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY  prev;
+    INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY *pNext;
+} INFOROM_OMS_V1G_DATA;
+
 typedef union
 {
    INFOROM_OBJECT_HEADER_V1_00 header;
    INFOROM_OMS_OBJECT_V1S v1s;
+    INFOROM_OMS_OBJECT_V1G v1g;
 } INFOROM_OMS_OBJECT;

 typedef union
 {
    INFOROM_OMS_V1S_DATA v1s;
+    INFOROM_OMS_V1G_DATA v1g;
 } INFOROM_OMS_DATA;

 typedef struct
--- a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h
+++ b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h
@@ -111,6 +111,7 @@
 #define NV_MSGBOX_CMD_ARG1_TEMP_NUM_SENSORS                              8
 #define NV_MSGBOX_CMD_ARG1_POWER_TOTAL                          0x00000000
 #define NV_MSGBOX_CMD_ARG1_SMBPBI_POWER                         0x00000001
+#define NV_MSGBOX_CMD_ARG1_POWER_FB                             0x00000002
 /* SysId info type encodings for opcode NV_MSGBOX_CMD_OPCODE_GET_SYS_ID_DATA (0x05) */
 #define NV_MSGBOX_CMD_ARG1_BOARD_PART_NUM_V1                    0x00000000
 #define NV_MSGBOX_CMD_ARG1_OEM_INFO_V1                          0x00000001
@@ -171,6 +172,8 @@
 #define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_MIN              0x00000001
 #define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_MAX              0x00000002
 #define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_PAGE_3           0x00000003
+#define NV_MSGBOX_CMD_ARG1_GET_SUPPORTED_CLOCK_THROTTLE_REASONS 0x00000004
+#define NV_MSGBOX_CMD_ARG1_GET_CURRENT_CLOCK_THROTTLE_REASONS   0x00000005
 #define NV_MSGBOX_CMD_ARG1_REMAP_ROWS_RAW_COUNTS                0x00000000
 #define NV_MSGBOX_CMD_ARG1_REMAP_ROWS_STATE_FLAGS               0x00000001
 #define NV_MSGBOX_CMD_ARG1_REMAP_ROWS_HISTOGRAM                 0x00000002
@@ -639,6 +642,9 @@
 #define NV_MSGBOX_DATA_CAP_0_GET_FABRIC_STATE_FLAGS                          29:29
 #define NV_MSGBOX_DATA_CAP_0_GET_FABRIC_STATE_FLAGS_NOT_AVAILABLE       0x00000000
 #define NV_MSGBOX_DATA_CAP_0_GET_FABRIC_STATE_FLAGS_AVAILABLE           0x00000001
+#define NV_MSGBOX_DATA_CAP_0_POWER_FB                                        30:30
+#define NV_MSGBOX_DATA_CAP_0_POWER_FB_NOT_AVAILABLE                     0x00000000
+#define NV_MSGBOX_DATA_CAP_0_POWER_FB_AVAILABLE                         0x00000001

 #define NV_MSGBOX_DATA_CAP_1                                                 1
 #define NV_MSGBOX_DATA_CAP_1_BOARD_PART_NUM_V1                             0:0
@@ -731,6 +737,9 @@
 #define NV_MSGBOX_DATA_CAP_1_ECC_V6                                      30:30
 #define NV_MSGBOX_DATA_CAP_1_ECC_V6_NOT_AVAILABLE                   0x00000000
 #define NV_MSGBOX_DATA_CAP_1_ECC_V6_AVAILABLE                       0x00000001
+#define NV_MSGBOX_DATA_CAP_1_CLOCK_THROTTLE_REASON                       31:31
+#define NV_MSGBOX_DATA_CAP_1_CLOCK_THROTTLE_REASON_NOT_AVAILABLE    0x00000000
+#define NV_MSGBOX_DATA_CAP_1_CLOCK_THROTTLE_REASON_AVAILABLE        0x00000001

 #define NV_MSGBOX_DATA_CAP_2                                                2
 #define NV_MSGBOX_DATA_CAP_2_GPU_DRIVER                                   0:0
@@ -1057,6 +1066,21 @@
 #define NV_MSGBOX_DATA_GET_CLOCK_FREQ_INFO_PAGE_3_CURRENT_PSTATE                 3:0
 #define NV_MSGBOX_DATA_GET_CLOCK_FREQ_INFO_PAGE_3_CURRENT_PSTATE_INVALID  0x0000000F

+/**
+ * Response to
+ * NV_MSGBOX_CMD_ARG1_GET_CLOCK_THROTTLE_REASON
+ */
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON                                   31:0
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_NONE                        0x00000000
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_POWER_CAP                0x00000001
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_SLOWDOWN                 0x00000002
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SYNC_BOOST                  0x00000004
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN_TLIMIT  0x00000008
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN_TAVG    0x00000010
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN_TMEM    0x00000020
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_THERMAL_SLOWDOWN         0x00000040
+#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_POWER_BREAK_SLOWDOWN     0x00000080
+
 /*
 * Number of Nvlink data outputs (dataOut, extData) for
 * NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK queries
@@ -2525,7 +2549,7 @@ typedef union {
            NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0)                         | \
            DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, type)                           | \
            DRF_NUM(_MSGBOX, _CMD, _ARG1_GPM_METRIC, metric)                         | \
-            DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_PARTITION, partition)                     \
+            DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_PARTITION_INDEX, partition)                     \
        )

 #define NV_MSGBOX_CMD_GPM_SET_MULTIPLIER(multiplier)                                   \
--- a/src/nvidia/generated/g_gpu_nvoc.c
+++ b/src/nvidia/generated/g_gpu_nvoc.c
@@ -199,7 +199,15 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
    }

    // NVOC Property Hal field -- PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE
-    pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 != 0)));
+    if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ 
+    {
+        pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 == 0)));
+    }
+    // default
+    else
+    {
+        pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 != 0)));
+    }

    // NVOC Property Hal field -- PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK
    if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ 
--- a/src/nvidia/generated/g_kernel_channel_nvoc.c
+++ b/src/nvidia/generated/g_kernel_channel_nvoc.c
@@ -740,12 +740,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh
 #endif
    },
    {               /*  [34] */
-#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
+#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u)
        /*pFunc=*/      (void (*)(void)) NULL,
 #else
        /*pFunc=*/      (void (*)(void)) kchannelCtrlCmdSetChannelHwState_IMPL,
-#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
-        /*flags=*/      0x102204u,
+#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u)
+        /*flags=*/      0x142204u,
        /*accessRight=*/0x0u,
        /*methodId=*/   0xb06f0110u,
        /*paramSize=*/  sizeof(NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS),
@@ -770,12 +770,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh
 #endif
    },
    {               /*  [36] */
-#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
+#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u)
        /*pFunc=*/      (void (*)(void)) NULL,
 #else
        /*pFunc=*/      (void (*)(void)) kchannelCtrlCmdRestoreEngineCtxData_IMPL,
-#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
-        /*flags=*/      0x102204u,
+#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u)
+        /*flags=*/      0x142204u,
        /*accessRight=*/0x0u,
        /*methodId=*/   0xb06f0112u,
        /*paramSize=*/  sizeof(NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS),
@@ -1166,7 +1166,7 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe
    pThis->__kchannelCtrlCmdGetChannelHwState__ = &kchannelCtrlCmdGetChannelHwState_IMPL;
 #endif

-#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
+#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u)
    pThis->__kchannelCtrlCmdSetChannelHwState__ = &kchannelCtrlCmdSetChannelHwState_IMPL;
 #endif

@@ -1174,7 +1174,7 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe
    pThis->__kchannelCtrlCmdSaveEngineCtxData__ = &kchannelCtrlCmdSaveEngineCtxData_IMPL;
 #endif

-#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u)
+#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u)
    pThis->__kchannelCtrlCmdRestoreEngineCtxData__ = &kchannelCtrlCmdRestoreEngineCtxData_IMPL;
 #endif

--- a/src/nvidia/generated/g_kernel_gsp_nvoc.c
+++ b/src/nvidia/generated/g_kernel_gsp_nvoc.c
@@ -659,7 +659,7 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner *
        }
        else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ 
        {
-            pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_38f3bc;
+            pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_c5ef93;
        }
    }

--- a/src/nvidia/generated/g_kernel_gsp_nvoc.h
+++ b/src/nvidia/generated/g_kernel_gsp_nvoc.h
@@ -791,8 +791,8 @@ static inline NvU64 kgspGetWprHeapSize_e77d51(struct OBJGPU *pGpu, struct Kernel
    return (64 * 1024 * 1024);
 }

-static inline NvU64 kgspGetWprHeapSize_38f3bc(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
-    return (80 * 1024 * 1024);
+static inline NvU64 kgspGetWprHeapSize_c5ef93(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
+    return (96 * 1024 * 1024);
 }

 static inline NvU64 kgspGetWprHeapSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) {
--- a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h
+++ b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h
@@ -149,7 +149,7 @@ struct KernelHostVgpuDeviceApi {
    NV_STATUS (*__kernelhostvgpudeviceapiMap__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *);
    NvBool (*__kernelhostvgpudeviceapiAccessCallback__)(struct KernelHostVgpuDeviceApi *, struct RsClient *, void *, RsAccessRight);
    struct KernelHostVgpuDeviceShr *pShared;
-    NvU32 notifyActions[5];
+    NvU32 notifyActions[6];
 };

 #ifndef __NVOC_CLASS_KernelHostVgpuDeviceApi_TYPEDEF__
--- a/src/nvidia/generated/g_nv_name_released.h
+++ b/src/nvidia/generated/g_nv_name_released.h
@@ -960,8 +960,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
    { 0x25FA, 0x0000, 0x0000, "NVIDIA RTX A2000 Embedded GPU" },
    { 0x25FB, 0x0000, 0x0000, "NVIDIA RTX A500 Embedded GPU" },
    { 0x2684, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090" },
-    { 0x26B1, 0x16a1, 0x10de, "NVIDIA RTX 6000 Ada Generation" },
-    { 0x26B5, 0x169d, 0x10de, "NVIDIA L40" },
+    { 0x26B1, 0x0000, 0x0000, "NVIDIA RTX 6000 Ada Generation" },
    { 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" },
    { 0x13BD, 0x11cc, 0x10DE, "GRID M10-0B" },
    { 0x13BD, 0x11cd, 0x10DE, "GRID M10-1B" },
--- a/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c
+++ b/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c
@@ -144,6 +144,9 @@ kbifGetVFSparseMmapRegions_TU102
    NvU64                   *sizes)
 {
    NvBool bEmulateVfTlbInvalidation = pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE);
+    NvU64 offsetStart = 0;
+    NvU64 offsetEnd = 0;
+    int idx = 0; 

    if (offsets && sizes && pKernelHostVgpuDevice != NULL)
    {
@@ -154,75 +157,71 @@ kbifGetVFSparseMmapRegions_TU102
        if (status != NV_OK)
            return NV_ERR_INVALID_ARGUMENT;

+        // For SRIOV heavy, trap BOOT_0 page
        if (gpuIsWarBug200577889SriovHeavyEnabled(pGpu))
        {
-            // For SRIOV heavy trap BOOT_* and BAR setup registers in plugin
-            offsets[0] = 0 + os_page_size;                                                      // 0x1000 ==> 0x2FFF
-            if (maxInstance > 1 && bEmulateVfTlbInvalidation)
-            {
-                sizes[0]   = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) - offsets[0];
-            }
-            else
-            {
-                sizes[0]   = DRF_BASE(NV_VGPU_EMU) - offsets[0];
-            }
-        }
-        else
-        {
-            offsets[0] = 0;                                                                     // 0x0000 => 0x2FFF
-            if (maxInstance > 1 && bEmulateVfTlbInvalidation)
-            {
-                sizes[0]   = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0);
-            }
-            else
-            {
-                sizes[0]   = DRF_BASE(NV_VGPU_EMU);
-            }
+            offsetStart = os_page_size; 
        }

-        if (hypervisorIsType(OS_HYPERVISOR_HYPERV))
+        // For VF TLB emulation, trap MMU FAULT BUFFER page
+        if ((maxInstance > 1) && bEmulateVfTlbInvalidation)
        {
-            // For Hyperv, we need to mitigate RPC page
-            if (maxInstance > 1 && bEmulateVfTlbInvalidation)
-            {
-                offsets[1] = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + os_page_size;    // 0x4000 ==> 0xEFFF
-                sizes[1]   = DRF_BASE(NV_VGPU_EMU) - offsets[1];
+            offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0);
+            offsets[idx] = offsetStart;
+            sizes[idx] = offsetEnd - offsetStart;
+            idx++;

-                offsets[2] =  DRF_BASE(NV_VGPU_EMU) + os_page_size;                             // 0x10000 ==> 0x40000
-                sizes[2]   = pGpu->sriovState.vfBarSize[0] - offsets[2];
-            }
-            else
-            {
-                offsets[1] = DRF_BASE(NV_VGPU_EMU) + os_page_size;                              // 0x10000 ==> 0x40000
-                sizes[1]   = pGpu->sriovState.vfBarSize[0] - offsets[1];
-            }
+            offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + os_page_size;
        }
-        else
+
+        // For non-GSP, trap VGPU_EMU page
+        if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu))
        {
-            if (maxInstance > 1 && bEmulateVfTlbInvalidation)
-            {
-                offsets[1] = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + os_page_size;    // 0x4000 ==> 0xEFFF
-                sizes[1]   = DRF_BASE(NV_VGPU_EMU) - offsets[1];
+            offsetEnd = DRF_BASE(NV_VGPU_EMU);
+            offsets[idx] = offsetStart;
+            sizes[idx] = offsetEnd - offsetStart;
+            idx++;

-                offsets[2] = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0) + os_page_size;     // 0x11000 ==> 0x40000
-                sizes[2]   = pGpu->sriovState.vfBarSize[0] - offsets[2];
-            }
-            else
-            {
-                offsets[1] = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0) + os_page_size;     // 0x11000 ==> 0x40000
-                sizes[1]   = pGpu->sriovState.vfBarSize[0] - offsets[1];
-            }
+            offsetStart = DRF_BASE(NV_VGPU_EMU) + os_page_size;
+        }

+        // For non-HyperV, trap MSI-X table page
+        if (!hypervisorIsType(OS_HYPERVISOR_HYPERV))
+        {
            // Assert whenever the MSI-X table page is not immediately after
            // the NV_VGPU_EMU page, as it will break the current assumption.
            NV_ASSERT((DRF_BASE(NV_VGPU_EMU) + DRF_SIZE(NV_VGPU_EMU)) ==
                      NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0));
+
+            offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0);
+
+            // Since MSI-X page is immediately after VGPU_EMU, if both are
+            // trapped, skip creating a 0 size region in between
+            if (offsetEnd > offsetStart)
+            {
+                offsets[idx] = offsetStart;
+                sizes[idx] = offsetEnd - offsetStart;
+                idx++;
+            }
+
+            offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0) + os_page_size;
        }
+
+        offsetEnd = pGpu->sriovState.vfBarSize[0];
+        offsets[idx] = offsetStart;
+        sizes[idx] = offsetEnd - offsetStart;
+        idx++;
    }
    else
    {
        return NV_ERR_INVALID_ARGUMENT;
    }

+    for (int i = 0; i < idx; i++)
+    {
+        NV_PRINTF(LEVEL_INFO, "VF Sparse Mmap Region[%u] range 0x%llx - 0x%llx, size 0x%llx\n",
+                  i, offsets[i], offsets[i] + sizes[i], sizes[i]);
+    }
+
    return NV_OK;
 }
--- a/src/nvidia/src/kernel/gpu/bus/p2p.c
+++ b/src/nvidia/src/kernel/gpu/bus/p2p.c
@@ -157,8 +157,6 @@ NV_STATUS _createThirdPartyP2PMappingExtent
    PCLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO pExtentInfoTmp;
    RsClient *pClient;
    Device *pDevice;
-    NvBool bGpuLockTaken = (rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)) ||
-                            rmGpuLockIsOwner());

    status = serverGetClientUnderLock(&g_resServ, hClient, &pClient);
    NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_INVALID_ARGUMENT);
@@ -202,26 +200,12 @@ NV_STATUS _createThirdPartyP2PMappingExtent
                             0,
                             &fbApertureOffset, status);
    }
-    else
+    else if ((status = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK)
    {
-        if (!bGpuLockTaken)
-        {
-            status = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE,
-                                             RM_LOCK_MODULES_P2P);
-            NV_ASSERT_OR_GOTO(status == NV_OK, out);
-        }
-
-        status = kbusMapFbAperture_HAL(pGpu, pKernelBus,
-                                       (*ppExtentInfo)->pMemDesc, 0,
-                                       &fbApertureOffset,
-                                       &fbApertureMapLength,
-                                       BUS_MAP_FB_FLAGS_MAP_UNICAST,
-                                       hClient);
-
-        if (!bGpuLockTaken)
-        {
-            rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
-        }
+        status = kbusMapFbAperture_HAL(pGpu, pKernelBus, (*ppExtentInfo)->pMemDesc, 0,
+                                        &fbApertureOffset, &fbApertureMapLength,
+                                        BUS_MAP_FB_FLAGS_MAP_UNICAST, hClient);
+        rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
    }
    if (status != NV_OK)
    {
@@ -262,32 +246,14 @@ out:
                                       0,
                                       fbApertureOffset, tmpStatus);
            }
-            else
+            else if ((tmpStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK)
            {
-                if (!bGpuLockTaken)
-                {
-                    tmpStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE,
-                                                        RM_LOCK_MODULES_P2P);
-                    NV_ASSERT(tmpStatus == NV_OK);
-
-                    if (tmpStatus != NV_OK)
-                    {
-                        _freeMappingExtentInfo(*ppExtentInfo);
-
-                        return tmpStatus;
-                    }
-                }
-
                tmpStatus = kbusUnmapFbAperture_HAL(pGpu, pKernelBus,
                                                    (*ppExtentInfo)->pMemDesc,
                                                    fbApertureOffset,
                                                    fbApertureMapLength,
                                                    BUS_MAP_FB_FLAGS_MAP_UNICAST);
-
-                if (!bGpuLockTaken)
-                {
-                    rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
-                }
+                rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
            }
            NV_ASSERT(tmpStatus == NV_OK);
        }
@@ -372,11 +338,6 @@ NV_STATUS RmThirdPartyP2PMappingFree
    PCLI_THIRD_PARTY_P2P_MAPPING_EXTENT_INFO pExtentInfoNext = NULL;
    RsClient                           *pClient;
    Device                             *pDevice;
-    NvBool                              bGpuLockTaken;
-    NvBool                              bVgpuRpc;
-
-    bGpuLockTaken = (rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)) ||
-                     rmGpuLockIsOwner());

    NV_ASSERT_OR_RETURN((pGpu != NULL), NV_ERR_INVALID_ARGUMENT);
    NV_ASSERT_OR_RETURN((pMappingInfo != NULL), NV_ERR_INVALID_ARGUMENT);
@@ -396,15 +357,6 @@ NV_STATUS RmThirdPartyP2PMappingFree
    length = pMappingInfo->length;
    address = pMappingInfo->address;

-    bVgpuRpc = IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu);
-
-    if (!bGpuLockTaken && !bVgpuRpc)
-    {
-        status = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE,
-                                         RM_LOCK_MODULES_P2P);
-        NV_ASSERT_OK_OR_RETURN(status);
-    }
-
    for(pExtentInfo = pMappingInfo->pStart; (pExtentInfo != NULL) && (length != 0);
        pExtentInfo = pExtentInfoNext)
    {
@@ -417,7 +369,7 @@ NV_STATUS RmThirdPartyP2PMappingFree
        pExtentInfo->refCount--;
        if (pExtentInfo->refCount == 0)
        {
-            if (bVgpuRpc)
+            if (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))
            {
                NV_RM_RPC_UNMAP_MEMORY(pGpu, hClient,
                                       RES_GET_HANDLE(pDevice),
@@ -425,13 +377,14 @@ NV_STATUS RmThirdPartyP2PMappingFree
                                       0,
                                       pExtentInfo->fbApertureOffset, status);
            }
-            else
+            else if ((status = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK)
            {
                status = kbusUnmapFbAperture_HAL(pGpu, pKernelBus,
                                                 pExtentInfo->pMemDesc,
                                                 pExtentInfo->fbApertureOffset,
                                                 pExtentInfo->length,
                                                 BUS_MAP_FB_FLAGS_MAP_UNICAST);
+                rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
            }
            NV_ASSERT(status == NV_OK);

@@ -441,12 +394,6 @@ NV_STATUS RmThirdPartyP2PMappingFree
            _freeMappingExtentInfo(pExtentInfo);
        }
    }
-
-    if (!bGpuLockTaken && !bVgpuRpc)
-    {
-        rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
-    }
-
    NV_ASSERT(length == 0);

    pMappingInfo->pStart = NULL;
--- a/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c
+++ b/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c
@@ -894,32 +894,13 @@ static NV_STATUS _thirdpartyp2pDelMappingInfoByKey
    NvU64                                    address;
    NvU64                                    startOffset;
    CLI_THIRD_PARTY_P2P_VIDMEM_INFO_MAPIter  vidMemMapIter;
-    NvBool                                   bGpuLockTaken;
-    NvBool                                   bVgpuRpc;

    NV_ASSERT_OR_RETURN((pKey != NULL), NV_ERR_INVALID_ARGUMENT);

-    bGpuLockTaken = (rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)) ||
-                     rmGpuLockIsOwner());
-
-    bVgpuRpc = IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu);
-
    pSubdevice = pThirdPartyP2P->pSubdevice;

    GPU_RES_SET_THREAD_BC_STATE(pThirdPartyP2P);

-    //
-    // vGPU RPC is being called without GPU lock held.
-    // So acquire the lock only for non-vGPU case and if
-    // no locks are held.
-    //
-    if (!bVgpuRpc && !bGpuLockTaken)
-    {
-        status = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE,
-                                         RM_LOCK_MODULES_P2P);
-        NV_ASSERT_OK_OR_RETURN(status);
-    }
-
    vidMemMapIter = mapIterAll(&pThirdPartyP2P->vidmemInfoMap);
    while (mapIterNext(&vidMemMapIter))
    {
@@ -949,7 +930,7 @@ static NV_STATUS _thirdpartyp2pDelMappingInfoByKey
                              "Freeing P2P mapping for gpu VA: 0x%llx, length: 0x%llx\n",
                              pExtentInfo->address, pExtentInfo->length);

-                    if (bVgpuRpc)
+                    if (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))
                    {
                        NV_RM_RPC_UNMAP_MEMORY(pGpu, pThirdPartyP2P->hClient,
                                               RES_GET_PARENT_HANDLE(pSubdevice),
@@ -957,13 +938,14 @@ static NV_STATUS _thirdpartyp2pDelMappingInfoByKey
                                               0,
                                               pExtentInfo->fbApertureOffset, status);
                    }
-                    else
+                    else if ((status = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK)
                    {
                        status = kbusUnmapFbAperture_HAL(pGpu, pKernelBus,
                                                         pExtentInfo->pMemDesc,
                                                         pExtentInfo->fbApertureOffset,
                                                         pExtentInfo->length,
                                                         BUS_MAP_FB_FLAGS_MAP_UNICAST);
+                        rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
                    }
                    NV_ASSERT(status == NV_OK);

@@ -1000,10 +982,6 @@ static NV_STATUS _thirdpartyp2pDelMappingInfoByKey
        }
    }

-    if (!bVgpuRpc && !bGpuLockTaken)
-    {
-        rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
-    }

    return NV_OK;
 }
--- a/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c
+++ b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c
@@ -304,7 +304,7 @@ static _getNvlinkStatus
            }
        }

-        if (pLinkAndClockValues->bLinkConnectedToPeer)
+        if (nvlinkLinks[i].bConnected)
        {
            // Tag as Peer link
            bPeerLink = NV_TRUE;
--- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c
+++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c
@@ -1076,6 +1076,43 @@ knvlinkPrepareForXVEReset_IMPL

            retStatus = (retStatus == NV_OK) ? status : retStatus;
        }
+#if defined(INCLUDE_NVLINK_LIB)
+        else
+        {
+            NvU32 linkId;
+
+            //
+            // The connections have been successfully reset, update connected and disconnected
+            // links masks on both the devices
+            //
+            FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks)
+            {
+                pKernelNvlink->disconnectedLinkMask |=  NVBIT(linkId);
+                pKernelNvlink->connectedLinksMask   &= ~NVBIT(linkId);
+
+                if (pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.deviceType !=
+                                              NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU)
+                {
+                    continue;
+                }
+
+                OBJGPU *pRemoteGpu = gpumgrGetGpuFromBusInfo(
+                                            pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.domain,
+                                            pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bus,
+                                            pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.device);
+
+                if (!API_GPU_IN_RESET_SANITY_CHECK(pRemoteGpu))
+                {
+                    KernelNvlink *pRemoteKernelNvlink = GPU_GET_KERNEL_NVLINK(pRemoteGpu);
+                    NvU32 remoteLinkId = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.linkNumber;
+
+                    pRemoteKernelNvlink->disconnectedLinkMask |=  NVBIT(remoteLinkId);
+                    pRemoteKernelNvlink->connectedLinksMask   &= ~NVBIT(remoteLinkId);
+                }
+            }
+            FOR_EACH_INDEX_IN_MASK_END;
+        }
+#endif

        //
        // knvlinkCoreResetDeviceLinks() only resets the links which have
--- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c
+++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c
@@ -91,7 +91,6 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL
    //
    if (!knvlinkPoweredUpForD3_HAL(pGpu, pKernelNvlink))
    {
-
        //
        // Optimization: Check for nvlink proxy only when system fabric is externally
        // managed. This would avoid RPCs in non-nvswitch cases.
@@ -128,8 +127,8 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL
            {
                NV_PRINTF(LEVEL_ERROR, "Failed to floorsweep valid nvlink config!\n");
                return NV_ERR_NOT_READY;
-                }
-                }
+            }
+        }

        // We only need to look at links that are still considered disconnected
        FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->disconnectedLinkMask)
@@ -145,7 +144,7 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL
                continue;
            }

-            bUpdateConnStatus          = NV_FALSE;
+            bUpdateConnStatus = NV_FALSE;

            if (pKernelNvlink->nvlinkLinks[linkId].core_link)
            {
@@ -210,7 +209,7 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL
                            pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info, flags);
                }

-                 // RPC into GSP-RM to update the link connected status only if its required
+                // RPC into GSP-RM to update the link connected status only if its required
                if (pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bConnected != conn_info.bConnected)
                    bUpdateConnStatus = NV_TRUE;

@@ -581,11 +580,13 @@ knvlinkTrainP2pLinksToActive_IMPL

 #if defined(INCLUDE_NVLINK_LIB)

-    OBJSYS *pSys        = SYS_GET_INSTANCE();
-    NvU32   version     = pKernelNvlink0->ipVerNvlink;
-    NvBool  bTrainLinks = NV_FALSE;
-    NvU32   count       = 0;
-    NvU32   i;
+    OBJSYS       *pSys           = SYS_GET_INSTANCE();
+    KernelNvlink *pKernelNvlink1 = GPU_GET_KERNEL_NVLINK(pGpu1);
+    NvU32         version        = pKernelNvlink0->ipVerNvlink;
+    NvBool        bTrainLinks    = NV_FALSE;
+    NvU32         count          = 0;
+    NvU32         remoteLink;
+    NvU32         i;

    nvlink_link *pLinks[NVLINK_MAX_LINKS_SW] = { 0 };

@@ -638,18 +639,23 @@ knvlinkTrainP2pLinksToActive_IMPL
    //
    if (IsAMPEREorBetter(pGpu0))
    {
-        NvU32 linkMask = 0;
+        NvU32 localMask  = 0;
+        NvU32 remoteMask = 0;

        FOR_EACH_INDEX_IN_MASK(32, i, pKernelNvlink0->enabledLinks)
        {
            if (KNVLINK_IS_LINK_CONNECTED_TO_GPU(pKernelNvlink0, i, pGpu1))
            {
-                linkMask |= BIT(i);
+                remoteLink = pKernelNvlink0->nvlinkLinks[i].remoteEndInfo.linkNumber;
+
+                localMask  |= BIT(i);
+                remoteMask |= BIT(remoteLink);
            }
        }
        FOR_EACH_INDEX_IN_MASK_END;

-        if ((linkMask & pKernelNvlink0->initializedLinks) == linkMask)
+        if (((pKernelNvlink0->initializedLinks & localMask)  == localMask) &&
+            ((pKernelNvlink1->initializedLinks & remoteMask) == remoteMask))
        {
            NV_PRINTF(LEVEL_INFO, "P2P links are all trained already, return\n");
            return NV_OK;
--- a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c
+++ b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c
@@ -726,6 +726,9 @@ static NvBool _gpumgrIsRmFirmwareDefaultChip(NvU32 pmcBoot42)

 static NvBool _gpumgrIsVgxRmFirmwareDefaultChip(NvU32 pmcBoot42)
 {
+    if (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) == NV_PMC_BOOT_42_ARCHITECTURE_AD100)
+        return NV_TRUE;
+
    return NV_FALSE;
 }

@@ -2261,7 +2264,7 @@ gpumgrServiceInterrupts_IMPL(NvU32 gpuMask, MC_ENGINE_BITVECTOR *engineMask, NvB
        if (gpuIsGpuFullPower(pGpu))
        {
            Intr *pIntr = GPU_GET_INTR(pGpu);
-            
+
            //
            // On SLI, one OBJGPU's StateInit functions could attempt to service
            // interrupts on another OBJGPU which has not yet started StateInit.
@@ -3041,7 +3044,7 @@ gpumgrAddSystemMIGInstanceTopo_IMPL
        {
            pGpuMgr->MIGTopologyInfo[i].bValid = NV_TRUE;
            pGpuMgr->MIGTopologyInfo[i].domainBusDevice = domainBusDevice;
-            
+
            // Set MIG enablement to disabled by default
            pGpuMgr->MIGTopologyInfo[i].bMIGEnabled = NV_FALSE;
            break;
@@ -3143,9 +3146,9 @@ gpumgrIsSystemMIGEnabled_IMPL
 * @returns NV_TRUE if entry found
 *          NV_FALSE otherwise
 */
-void 
+void
 gpumgrSetSystemMIGEnabled_IMPL
-(  
+(
    NvU64 domainBusDevice,
    NvBool bMIGEnabled
 )
@@ -3261,7 +3264,7 @@ gpumgrGetGpuBridgeType(void)
 {
    OBJSYS *pSys = SYS_GET_INSTANCE();
    OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys);
-    
+
    return pGpuMgr->gpuBridgeType;
 }

@@ -3283,7 +3286,7 @@ gpumgrInitPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr)
 /**
 * @brief Destroy the PCIE P2P info cache
 */
-void 
+void
 gpumgrDestroyPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr)
 {
    PCIEP2PCAPSINFO *pPcieCapsInfo, *pPcieCapsInfoNext;
@@ -3310,7 +3313,7 @@ gpumgrDestroyPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr)
 * @param[in]   gpuMask             NvU32 value
 * @param[in]   p2pWriteCapsStatus  NvU8 value
 * @param[in]   pP2PReadCapsStatus  NvU8 value
- * 
+ *
 * @return      NV_OK or NV_ERR_NO_MEMORY
 */
 NV_STATUS
@@ -3460,7 +3463,7 @@ gpumgrGetPcieP2PCapsFromCache_IMPL
    OBJSYS    *pSys    = SYS_GET_INSTANCE();
    OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys);
    NvBool     bFound;
-        
+
    portSyncMutexAcquire(pGpuMgr->pcieP2PCapsInfoLock);

    bFound = _gpumgrGetPcieP2PCapsFromCache(gpuMask, pP2PWriteCapsStatus, pP2PReadCapsStatus);
--- a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c
+++ b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c
@@ -432,11 +432,19 @@ gvaspaceReserveSplitVaSpace_IMPL

    if (bServerRm || bClientRm)
    {
+        OBJVASPACE *pVAS = staticCast(pGVAS, OBJVASPACE);
+
        pGVAS->vaStartServerRMOwned = NV_MIN(pGVAS->vaLimitInternal -
                                         SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE + 1,
                                         SPLIT_VAS_SERVER_RM_MANAGED_VA_START);
+
+        if (pVAS->vasStart > pGVAS->vaStartServerRMOwned)
+        {
+            pGVAS->vaStartServerRMOwned = pVAS->vasStart + SPLIT_VAS_SERVER_RM_MANAGED_VA_START;
+        }           
+ 
        pGVAS->vaLimitServerRMOwned = pGVAS->vaStartServerRMOwned +
-                                         SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE - 1;
+                                      SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE - 1;

        // Base and limit + 1 should be aligned to 512MB.
        if (!NV_IS_ALIGNED(pGVAS->vaStartServerRMOwned, NVBIT64(GMMU_PD1_VADDR_BIT_LO)))
--- a/version.mk
+++ b/version.mk
@@ -1,4 +1,4 @@
-NVIDIA_VERSION = 525.60.13
+NVIDIA_VERSION = 525.47.04

 # This file.
 VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))