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18
CHANGELOG.md
18
CHANGELOG.md
@@ -2,6 +2,24 @@
|
||||
|
||||
## Release 535 Entries
|
||||
|
||||
### [535.54.03] 2023-06-14
|
||||
|
||||
### [535.43.22] 2023-12-19
|
||||
|
||||
### [535.43.20] 2023-12-08
|
||||
|
||||
### [535.43.19] 2023-12-01
|
||||
|
||||
### [535.43.16] 2023-11-06
|
||||
|
||||
### [535.43.15] 2023-10-24
|
||||
|
||||
### [535.43.13] 2023-10-11
|
||||
|
||||
### [535.43.11] 2023-10-05
|
||||
|
||||
### [535.43.10] 2023-09-27
|
||||
|
||||
### [535.43.09] 2023-09-01
|
||||
|
||||
### [535.43.08] 2023-08-17
|
||||
|
||||
19
README.md
19
README.md
@@ -1,7 +1,7 @@
|
||||
# NVIDIA Linux Open GPU Kernel Module Source
|
||||
|
||||
This is the source release of the NVIDIA Linux open GPU kernel modules,
|
||||
version 535.43.09.
|
||||
version 535.43.22.
|
||||
|
||||
|
||||
## How to Build
|
||||
@@ -17,7 +17,7 @@ as root:
|
||||
|
||||
Note that the kernel modules built here must be used with GSP
|
||||
firmware and user-space NVIDIA GPU driver components from a corresponding
|
||||
535.43.09 driver release. This can be achieved by installing
|
||||
535.43.22 driver release. This can be achieved by installing
|
||||
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
|
||||
option. E.g.,
|
||||
|
||||
@@ -180,7 +180,7 @@ software applications.
|
||||
## Compatible GPUs
|
||||
|
||||
The open-gpu-kernel-modules can be used on any Turing or later GPU
|
||||
(see the table below). However, in the 535.43.09 release,
|
||||
(see the table below). However, in the 535.43.22 release,
|
||||
GeForce and Workstation support is still considered alpha-quality.
|
||||
|
||||
To enable use of the open kernel modules on GeForce and Workstation GPUs,
|
||||
@@ -188,7 +188,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
|
||||
parameter to 1. For more details, see the NVIDIA GPU driver end user
|
||||
README here:
|
||||
|
||||
https://us.download.nvidia.com/XFree86/Linux-x86_64/535.43.09/README/kernel_open.html
|
||||
https://us.download.nvidia.com/XFree86/Linux-x86_64/535.43.22/README/kernel_open.html
|
||||
|
||||
In the below table, if three IDs are listed, the first is the PCI Device
|
||||
ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
|
||||
@@ -658,6 +658,7 @@ Subsystem Device ID.
|
||||
| NVIDIA A100-SXM4-80GB | 20B2 10DE 147F |
|
||||
| NVIDIA A100-SXM4-80GB | 20B2 10DE 1622 |
|
||||
| NVIDIA A100-SXM4-80GB | 20B2 10DE 1623 |
|
||||
| NVIDIA PG509-210 | 20B2 10DE 1625 |
|
||||
| NVIDIA A100-SXM-64GB | 20B3 10DE 14A7 |
|
||||
| NVIDIA A100-SXM-64GB | 20B3 10DE 14A8 |
|
||||
| NVIDIA A100 80GB PCIe | 20B5 10DE 1533 |
|
||||
@@ -665,6 +666,7 @@ Subsystem Device ID.
|
||||
| NVIDIA PG506-232 | 20B6 10DE 1492 |
|
||||
| NVIDIA A30 | 20B7 10DE 1532 |
|
||||
| NVIDIA A30 | 20B7 10DE 1804 |
|
||||
| NVIDIA A30 | 20B7 10DE 1852 |
|
||||
| NVIDIA A800-SXM4-40GB | 20BD 10DE 17F4 |
|
||||
| NVIDIA A100-PCIE-40GB | 20F1 10DE 145F |
|
||||
| NVIDIA A800-SXM4-80GB | 20F3 10DE 179B |
|
||||
@@ -677,7 +679,10 @@ Subsystem Device ID.
|
||||
| NVIDIA A800-SXM4-80GB | 20F3 10DE 17A2 |
|
||||
| NVIDIA A800 80GB PCIe | 20F5 10DE 1799 |
|
||||
| NVIDIA A800 80GB PCIe LC | 20F5 10DE 179A |
|
||||
| NVIDIA A800 40GB Active | 20F6 1028 180A |
|
||||
| NVIDIA A800 40GB Active | 20F6 103C 180A |
|
||||
| NVIDIA A800 40GB Active | 20F6 10DE 180A |
|
||||
| NVIDIA A800 40GB Active | 20F6 17AA 180A |
|
||||
| NVIDIA GeForce GTX 1660 Ti | 2182 |
|
||||
| NVIDIA GeForce GTX 1660 | 2184 |
|
||||
| NVIDIA GeForce GTX 1650 SUPER | 2187 |
|
||||
@@ -745,6 +750,8 @@ Subsystem Device ID.
|
||||
| NVIDIA H100 PCIe | 2331 10DE 1626 |
|
||||
| NVIDIA H100 | 2339 10DE 17FC |
|
||||
| NVIDIA H800 NVL | 233A 10DE 183A |
|
||||
| NVIDIA GH200 120GB | 2342 10DE 16EB |
|
||||
| NVIDIA GH200 480GB | 2342 10DE 1809 |
|
||||
| NVIDIA GeForce RTX 3060 Ti | 2414 |
|
||||
| NVIDIA GeForce RTX 3080 Ti Laptop GPU | 2420 |
|
||||
| NVIDIA RTX A5500 Laptop GPU | 2438 |
|
||||
@@ -853,6 +860,10 @@ Subsystem Device ID.
|
||||
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 103C 16FA |
|
||||
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 10DE 16FA |
|
||||
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 17AA 16FA |
|
||||
| NVIDIA RTX 4500 Ada Generation | 27B1 1028 180C |
|
||||
| NVIDIA RTX 4500 Ada Generation | 27B1 103C 180C |
|
||||
| NVIDIA RTX 4500 Ada Generation | 27B1 10DE 180C |
|
||||
| NVIDIA RTX 4500 Ada Generation | 27B1 17AA 180C |
|
||||
| NVIDIA RTX 4000 Ada Generation | 27B2 1028 181B |
|
||||
| NVIDIA RTX 4000 Ada Generation | 27B2 103C 181B |
|
||||
| NVIDIA RTX 4000 Ada Generation | 27B2 10DE 181B |
|
||||
|
||||
@@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
|
||||
EXTRA_CFLAGS += -I$(src)
|
||||
EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
|
||||
EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
|
||||
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.43.09\"
|
||||
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.43.22\"
|
||||
|
||||
ifneq ($(SYSSRCHOST1X),)
|
||||
EXTRA_CFLAGS += -I$(SYSSRCHOST1X)
|
||||
|
||||
@@ -43,18 +43,18 @@
|
||||
#endif
|
||||
|
||||
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
|
||||
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/VK535_87-129"
|
||||
#define NV_BUILD_CHANGELIST_NUM (33257513)
|
||||
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/VK535_87-145"
|
||||
#define NV_BUILD_CHANGELIST_NUM (33667820)
|
||||
#define NV_BUILD_TYPE "Official"
|
||||
#define NV_BUILD_NAME "rel/gpu_drv/r535/VK535_87-129"
|
||||
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33257513)
|
||||
#define NV_BUILD_NAME "rel/gpu_drv/r535/VK535_87-145"
|
||||
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33667820)
|
||||
|
||||
#else /* Windows builds */
|
||||
#define NV_BUILD_BRANCH_VERSION "VK535_87-9"
|
||||
#define NV_BUILD_CHANGELIST_NUM (33257513)
|
||||
#define NV_BUILD_BRANCH_VERSION "VK535_87-22"
|
||||
#define NV_BUILD_CHANGELIST_NUM (33665505)
|
||||
#define NV_BUILD_TYPE "Official"
|
||||
#define NV_BUILD_NAME "537.35"
|
||||
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33257513)
|
||||
#define NV_BUILD_NAME "538.09"
|
||||
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33665505)
|
||||
#define NV_BUILD_BRANCH_BASE_VERSION R535
|
||||
#endif
|
||||
// End buildmeister python edited section
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
|
||||
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
|
||||
|
||||
#define NV_VERSION_STRING "535.43.09"
|
||||
#define NV_VERSION_STRING "535.43.22"
|
||||
|
||||
#else
|
||||
|
||||
|
||||
@@ -460,7 +460,6 @@ struct MemoryManager {
|
||||
NvBool bPmaEnabled;
|
||||
NvBool bPmaInitialized;
|
||||
NvBool bPmaForcePersistence;
|
||||
NvBool bPmaAddrTree;
|
||||
NvBool bClientPageTablesPmaManaged;
|
||||
NvBool bScanoutSysmem;
|
||||
NvBool bMixedDensityFbp;
|
||||
@@ -2150,10 +2149,6 @@ static inline void memmgrSetClientPageTablesPmaManaged(struct MemoryManager *pMe
|
||||
pMemoryManager->bClientPageTablesPmaManaged = val;
|
||||
}
|
||||
|
||||
static inline NvBool memmgrIsPmaAddrTree(struct MemoryManager *pMemoryManager) {
|
||||
return pMemoryManager->bPmaAddrTree;
|
||||
}
|
||||
|
||||
static inline NvU64 memmgrGetRsvdMemoryBase(struct MemoryManager *pMemoryManager) {
|
||||
return pMemoryManager->rsvdMemoryBase;
|
||||
}
|
||||
|
||||
@@ -808,6 +808,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
|
||||
{ 0x20B2, 0x147f, 0x10de, "NVIDIA A100-SXM4-80GB" },
|
||||
{ 0x20B2, 0x1622, 0x10de, "NVIDIA A100-SXM4-80GB" },
|
||||
{ 0x20B2, 0x1623, 0x10de, "NVIDIA A100-SXM4-80GB" },
|
||||
{ 0x20B2, 0x1625, 0x10de, "NVIDIA PG509-210" },
|
||||
{ 0x20B3, 0x14a7, 0x10de, "NVIDIA A100-SXM-64GB" },
|
||||
{ 0x20B3, 0x14a8, 0x10de, "NVIDIA A100-SXM-64GB" },
|
||||
{ 0x20B5, 0x1533, 0x10de, "NVIDIA A100 80GB PCIe" },
|
||||
@@ -815,6 +816,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
|
||||
{ 0x20B6, 0x1492, 0x10de, "NVIDIA PG506-232" },
|
||||
{ 0x20B7, 0x1532, 0x10de, "NVIDIA A30" },
|
||||
{ 0x20B7, 0x1804, 0x10de, "NVIDIA A30" },
|
||||
{ 0x20B7, 0x1852, 0x10de, "NVIDIA A30" },
|
||||
{ 0x20BD, 0x17f4, 0x10de, "NVIDIA A800-SXM4-40GB" },
|
||||
{ 0x20F1, 0x145f, 0x10de, "NVIDIA A100-PCIE-40GB" },
|
||||
{ 0x20F3, 0x179b, 0x10de, "NVIDIA A800-SXM4-80GB" },
|
||||
@@ -827,7 +829,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
|
||||
{ 0x20F3, 0x17a2, 0x10de, "NVIDIA A800-SXM4-80GB" },
|
||||
{ 0x20F5, 0x1799, 0x10de, "NVIDIA A800 80GB PCIe" },
|
||||
{ 0x20F5, 0x179a, 0x10de, "NVIDIA A800 80GB PCIe LC" },
|
||||
{ 0x20F6, 0x180a, 0x1028, "NVIDIA A800 40GB Active" },
|
||||
{ 0x20F6, 0x180a, 0x103c, "NVIDIA A800 40GB Active" },
|
||||
{ 0x20F6, 0x180a, 0x10de, "NVIDIA A800 40GB Active" },
|
||||
{ 0x20F6, 0x180a, 0x17aa, "NVIDIA A800 40GB Active" },
|
||||
{ 0x2182, 0x0000, 0x0000, "NVIDIA GeForce GTX 1660 Ti" },
|
||||
{ 0x2184, 0x0000, 0x0000, "NVIDIA GeForce GTX 1660" },
|
||||
{ 0x2187, 0x0000, 0x0000, "NVIDIA GeForce GTX 1650 SUPER" },
|
||||
@@ -896,6 +901,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
|
||||
{ 0x2331, 0x1626, 0x10de, "NVIDIA H100 PCIe" },
|
||||
{ 0x2339, 0x17fc, 0x10de, "NVIDIA H100" },
|
||||
{ 0x233A, 0x183a, 0x10de, "NVIDIA H800 NVL" },
|
||||
{ 0x2342, 0x16eb, 0x10de, "NVIDIA GH200 120GB" },
|
||||
{ 0x2342, 0x1809, 0x10de, "NVIDIA GH200 480GB" },
|
||||
{ 0x2414, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060 Ti" },
|
||||
{ 0x2420, 0x0000, 0x0000, "NVIDIA GeForce RTX 3080 Ti Laptop GPU" },
|
||||
{ 0x2438, 0x0000, 0x0000, "NVIDIA RTX A5500 Laptop GPU" },
|
||||
@@ -1004,6 +1011,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
|
||||
{ 0x27B0, 0x16fa, 0x103c, "NVIDIA RTX 4000 SFF Ada Generation" },
|
||||
{ 0x27B0, 0x16fa, 0x10de, "NVIDIA RTX 4000 SFF Ada Generation" },
|
||||
{ 0x27B0, 0x16fa, 0x17aa, "NVIDIA RTX 4000 SFF Ada Generation" },
|
||||
{ 0x27B1, 0x180c, 0x1028, "NVIDIA RTX 4500 Ada Generation" },
|
||||
{ 0x27B1, 0x180c, 0x103c, "NVIDIA RTX 4500 Ada Generation" },
|
||||
{ 0x27B1, 0x180c, 0x10de, "NVIDIA RTX 4500 Ada Generation" },
|
||||
{ 0x27B1, 0x180c, 0x17aa, "NVIDIA RTX 4500 Ada Generation" },
|
||||
{ 0x27B2, 0x181b, 0x1028, "NVIDIA RTX 4000 Ada Generation" },
|
||||
{ 0x27B2, 0x181b, 0x103c, "NVIDIA RTX 4000 Ada Generation" },
|
||||
{ 0x27B2, 0x181b, 0x10de, "NVIDIA RTX 4000 Ada Generation" },
|
||||
|
||||
@@ -1,227 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Implement PMA address tree
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef ADDRTREE_H
|
||||
#define ADDRTREE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "map_defines.h"
|
||||
|
||||
// Declare this before its definition because it refers to itself
|
||||
typedef struct addrtree_node ADDRTREE_NODE;
|
||||
|
||||
struct addrtree_node
|
||||
{
|
||||
NvU32 level; // The level this node belongs to
|
||||
NvU32 numChildren; // The number of children in the children array
|
||||
NvU64 frame; // The first frame this node holds
|
||||
NvU64 state[PMA_BITS_PER_PAGE]; // Tracks the actual state for each map
|
||||
NvU64 seeChild[PMA_BITS_PER_PAGE]; // Whether this node is partially allocated
|
||||
// If it is partially allocated, we must go to the children
|
||||
// to find the correct information.
|
||||
|
||||
ADDRTREE_NODE *parent; // The node's parent
|
||||
ADDRTREE_NODE *children; // Pointer to an array of children
|
||||
};
|
||||
|
||||
typedef struct addrtree_level
|
||||
{
|
||||
NvU64 nodeCount; // Count of total number of nodes on this level
|
||||
ADDRTREE_NODE *pNodeList; // Pointer to the start of the list of nodes on this level
|
||||
NvU32 pageSizeShift; // Page size this level is tracking
|
||||
NvU32 maxFramesPerNode; // The max number of this level frames per node
|
||||
} ADDRTREE_LEVEL;
|
||||
|
||||
typedef struct pma_addrtree
|
||||
{
|
||||
NvU64 totalFrames; // Total number of 64KB frames being tracked
|
||||
NvU32 levelCount; // Number of levels in this tree
|
||||
ADDRTREE_LEVEL *levels; // List of levels in the tree
|
||||
ADDRTREE_NODE *root; // Start of the node list
|
||||
NvU64 numPaddingFrames; // Number of 64KB frames needed for padding for alignment
|
||||
|
||||
NvU64 frameEvictionsInProcess; // Count of frame evictions in-process
|
||||
PMA_STATS *pPmaStats; // Point back to the public struct in PMA structure
|
||||
NvBool bProtected; // The memory segment tracked by this tree is protected (VPR/CPR)
|
||||
} PMA_ADDRTREE;
|
||||
|
||||
/*!
|
||||
* @brief Initializes the addrtree for PMA uses
|
||||
*
|
||||
* Allocates the address tree structure for all the pages being managed in this tree.
|
||||
* Address Tree implementation will use a default configuration for its own level
|
||||
* structures.
|
||||
*
|
||||
* @param[in] numPages The number of pages being managed in this tree
|
||||
* @param[in] addrBase The base address of this region. Required for addrtree alignment
|
||||
* @param[in] pPmaStats Pointer to the PMA-wide stats structure
|
||||
* @param[in] bProtected The tree tracks pages in protected memory
|
||||
*
|
||||
* @return PMA_ADDRTREE Pointer to the addrtree if succeeded, NULL otherwise
|
||||
*/
|
||||
void *pmaAddrtreeInit(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected);
|
||||
|
||||
/*!
|
||||
* @brief Destroys the addrtree and free the memory
|
||||
*
|
||||
* @param[in] pMap The addrtree to destroy
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
void pmaAddrtreeDestroy(void *pMap);
|
||||
|
||||
/*!
|
||||
* @brief Get/set number of evicting frames
|
||||
* Used for sanity checking in PMA layer as well as performance optimization
|
||||
* for the map layer to scan faster.
|
||||
*/
|
||||
NvU64 pmaAddrtreeGetEvictingFrames(void *pMap);
|
||||
void pmaAddrtreeSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Scans the addrtree for contiguous space that has the certain status.
|
||||
*
|
||||
* @param[in] pMap The addrtree to be scanned
|
||||
* @param[in] addrBase The base address of this region
|
||||
* @param[in] rangeStart The start of the restricted range
|
||||
* @param[in] rangeEnd The end of the restricted range
|
||||
* @param[in] numPages The number of pages we are scanning for
|
||||
* @param[out] freeList A list of free frame numbers -- contains only 1 element
|
||||
* @param[in] pageSize Size of one page
|
||||
* @param[in] alignment Alignment requested by client
|
||||
* @param[out] pagesAllocated Number of pages this call allocated
|
||||
* @param[in] bSkipEvict Whether it's ok to skip the scan for evictable pages
|
||||
*
|
||||
* @return NV_OK if succeeded
|
||||
* @return NV_ERR_IN_USE if found pages that can be evicted
|
||||
* @return NV_ERR_NO_MEMORY if no available pages could be found
|
||||
*/
|
||||
NV_STATUS pmaAddrtreeScanContiguous(
|
||||
void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
|
||||
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
|
||||
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
|
||||
|
||||
NV_STATUS pmaAddrtreeScanDiscontiguous(
|
||||
void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd,
|
||||
NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment,
|
||||
NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc);
|
||||
|
||||
void pmaAddrtreePrintTree(void *pMap, const char* str);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Changes the state & attrib bits specified by mask
|
||||
*
|
||||
* Changes the state of the bits given the physical frame number
|
||||
* TODO: all four interfaces need to be merged from PMA level so we can remove them!
|
||||
*
|
||||
* @param[in] pMap The addrtree to change
|
||||
* @param[in] frameNum The frame number to change
|
||||
* @param[in] newState The new state to change to
|
||||
* @param[in] newStateMask Specific bits to write
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
void pmaAddrtreeChangeState(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState);
|
||||
void pmaAddrtreeChangeStateAttrib(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, NvBool writeAttrib);
|
||||
void pmaAddrtreeChangeStateAttribEx(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState,PMA_PAGESTATUS newStateMask);
|
||||
void pmaAddrtreeChangePageStateAttrib(void * pMap, NvU64 startFrame, NvU64 pageSize,
|
||||
PMA_PAGESTATUS newState, NvBool writeAttrib);
|
||||
|
||||
/*!
|
||||
* @brief Read the page state & attrib bits
|
||||
*
|
||||
* Read the state of the page given the physical frame number
|
||||
*
|
||||
* @param[in] pMap The addrtree to read
|
||||
* @param[in] frameNum The frame number to read
|
||||
* @param[in] readAttrib Read attribute bits as well
|
||||
*
|
||||
* @return PAGESTATUS of the frame
|
||||
*/
|
||||
PMA_PAGESTATUS pmaAddrtreeRead(void *pMap, NvU64 frameNum, NvBool readAttrib);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Gets the total size of specified PMA managed region.
|
||||
*
|
||||
* Gets the total size of current PMA managed region in the FB.
|
||||
*
|
||||
* @param[in] pMap Pointer to the addrtree for the region
|
||||
* @param[in] pBytesTotal Pointer that will return total bytes for current region.
|
||||
*
|
||||
*/
|
||||
void pmaAddrtreeGetSize(void *pMap, NvU64 *pBytesTotal);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Gets the size of the maximum free chunk of memory in specified region.
|
||||
*
|
||||
* Gets the size of the maximum free chunk of memory in the specified PMA managed
|
||||
* region of the FB.
|
||||
*
|
||||
* @param[in] pMap Pointer to the addrtree for the region
|
||||
* @param[in] pLargestFree Pointer that will return largest free in current region.
|
||||
*
|
||||
*/
|
||||
void pmaAddrtreeGetLargestFree(void *pMap, NvU64 *pLargestFree);
|
||||
|
||||
/*!
|
||||
* @brief Returns the address range that is completely available for eviction.
|
||||
* - Should be ALLOC_UNPIN.
|
||||
* In NUMA, OS manages memory and PMA will only track allocated memory in ALLOC_PIN
|
||||
* and ALLOC_UNPIN state. FREE memory is managed by OS and cannot be tracked by PMA
|
||||
* and hence PMA cannot consider FREE memory for eviction and can only consider frames
|
||||
* in known state to PMA or eviction. ALLOC_PIN cannot be evicted and hence only ALLOC_UNPIN
|
||||
* can be evictable.
|
||||
*
|
||||
*
|
||||
* @param[in] pMap Pointer to the regmap for the region
|
||||
* @param[in] addrBase Base address of the region
|
||||
* @param[in] actualSize Size of the eviction range
|
||||
* @param[in] pageSize Pagesize
|
||||
* @param[out] evictStart Starting address of the eviction range
|
||||
* @param[out] evictEnd End address of the eviction range.
|
||||
*
|
||||
* Returns:
|
||||
* - NV_OK If there is evictable range of given size : actualSize
|
||||
*
|
||||
* - NV_ERR_NO_MEMORY if no contiguous range is evictable.
|
||||
*/
|
||||
NV_STATUS pmaAddrtreeScanContiguousNumaEviction(void *pMap, NvU64 addrBase,
|
||||
NvLength actualSize, NvU64 pageSize, NvU64 *evictStart, NvU64 *evictEnd);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // ADDRTREE_H
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -22,7 +22,7 @@
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Contains common defines between addrtree and regmap
|
||||
* @brief Contains common defines for regmap
|
||||
*/
|
||||
|
||||
#ifndef MAP_DEFINES_H
|
||||
|
||||
@@ -42,7 +42,6 @@
|
||||
|
||||
#include "nvport/nvport.h"
|
||||
#include "regmap.h"
|
||||
#include "addrtree.h"
|
||||
#include "nvmisc.h"
|
||||
|
||||
#if defined(SRT_BUILD)
|
||||
@@ -72,7 +71,7 @@ typedef struct SCRUB_NODE SCRUB_NODE;
|
||||
#define PMA_INIT_NUMA NVBIT(2)
|
||||
#define PMA_INIT_INTERNAL NVBIT(3) // Used after heap is removed
|
||||
#define PMA_INIT_FORCE_PERSISTENCE NVBIT(4)
|
||||
#define PMA_INIT_ADDRTREE NVBIT(5)
|
||||
// unused
|
||||
#define PMA_INIT_NUMA_AUTO_ONLINE NVBIT(6)
|
||||
|
||||
// These flags are used for querying PMA's config and/or state.
|
||||
|
||||
@@ -83,10 +83,11 @@ MAKE_LIST(PoolPageHandleList, POOLALLOC_HANDLE);
|
||||
/*!
|
||||
* @brief Callback function to upstream allocators for allocating new pages
|
||||
*
|
||||
* This function only allocate 1 page at a time right now
|
||||
* This function can allocate multiple pages at a time
|
||||
*
|
||||
* @param[in] ctxPtr Provides context to upstream allocator
|
||||
* @param[in] pageSize Not really needed. For debugging only
|
||||
* @param[in] pageSize Size of page to ask for from upstream
|
||||
* @param[in] numPages Number of pages to allocate
|
||||
* @param[out] pPage The output page handle from upstream
|
||||
*
|
||||
* @return NV_OK if successfully allocated NvF32 totalTest, doneTest, failTest; the page
|
||||
@@ -96,7 +97,7 @@ MAKE_LIST(PoolPageHandleList, POOLALLOC_HANDLE);
|
||||
*
|
||||
*/
|
||||
typedef NV_STATUS (*allocCallback_t)(void *ctxPtr, NvU64 pageSize,
|
||||
POOLALLOC_HANDLE *pPage);
|
||||
NvU64 numPages, POOLALLOC_HANDLE *pPage);
|
||||
|
||||
/*!
|
||||
* @brief Callback function to upstream allocators for freeing unused pages
|
||||
|
||||
@@ -826,13 +826,6 @@
|
||||
|
||||
//
|
||||
// Type DWORD
|
||||
// Controls enable of Address Tree memory tracking instead of regmap
|
||||
// for the PMA memory manager.
|
||||
//
|
||||
#define NV_REG_STR_RM_ENABLE_ADDRTREE "RMEnableAddrtree"
|
||||
#define NV_REG_STR_RM_ENABLE_ADDRTREE_YES (0x00000001)
|
||||
#define NV_REG_STR_RM_ENABLE_ADDRTREE_NO (0x00000000)
|
||||
|
||||
#define NV_REG_STR_RM_SCRUB_BLOCK_SHIFT "RMScrubBlockShift"
|
||||
// Type DWORD
|
||||
// Encoding Numeric Value
|
||||
|
||||
@@ -251,19 +251,6 @@ _memmgrInitRegistryOverrides(OBJGPU *pGpu, MemoryManager *pMemoryManager)
|
||||
}
|
||||
}
|
||||
|
||||
if (osReadRegistryDword(pGpu, NV_REG_STR_RM_ENABLE_ADDRTREE, &data32) == NV_OK)
|
||||
{
|
||||
if (data32 == NV_REG_STR_RM_ENABLE_ADDRTREE_YES)
|
||||
{
|
||||
pMemoryManager->bPmaAddrTree = NV_TRUE;
|
||||
NV_PRINTF(LEVEL_ERROR, "Enabled address tree for PMA via regkey.\n");
|
||||
}
|
||||
}
|
||||
else if (RMCFG_FEATURE_PLATFORM_MODS)
|
||||
{
|
||||
pMemoryManager->bPmaAddrTree = NV_TRUE;
|
||||
NV_PRINTF(LEVEL_ERROR, "Enabled address tree for PMA for MODS.\n");
|
||||
}
|
||||
}
|
||||
|
||||
NV_STATUS
|
||||
@@ -2777,11 +2764,6 @@ memmgrPmaInitialize_IMPL
|
||||
pmaInitFlags |= PMA_INIT_NUMA_AUTO_ONLINE;
|
||||
}
|
||||
|
||||
if (memmgrIsPmaAddrTree(pMemoryManager))
|
||||
{
|
||||
pmaInitFlags |= PMA_INIT_ADDRTREE;
|
||||
}
|
||||
|
||||
status = pmaInitialize(pPma, pmaInitFlags);
|
||||
if (status != NV_OK)
|
||||
{
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -240,26 +240,6 @@ pmaInitialize(PMA *pPma, NvU32 initFlags)
|
||||
pPma->bNuma = !!(initFlags & PMA_INIT_NUMA);
|
||||
|
||||
pPma->bNumaAutoOnline = !!(initFlags & PMA_INIT_NUMA_AUTO_ONLINE);
|
||||
|
||||
// If we want to run with address tree instead of regmap
|
||||
if (initFlags & PMA_INIT_ADDRTREE)
|
||||
{
|
||||
pMapInfo->pmaMapInit = pmaAddrtreeInit;
|
||||
pMapInfo->pmaMapDestroy = pmaAddrtreeDestroy;
|
||||
pMapInfo->pmaMapChangeState = pmaAddrtreeChangeState;
|
||||
pMapInfo->pmaMapChangeStateAttrib = pmaAddrtreeChangeStateAttrib;
|
||||
pMapInfo->pmaMapChangeStateAttribEx = pmaAddrtreeChangeStateAttribEx;
|
||||
pMapInfo->pmaMapChangePageStateAttrib = pmaAddrtreeChangePageStateAttrib;
|
||||
pMapInfo->pmaMapRead = pmaAddrtreeRead;
|
||||
pMapInfo->pmaMapScanContiguous = pmaAddrtreeScanContiguous;
|
||||
pMapInfo->pmaMapScanDiscontiguous = pmaAddrtreeScanDiscontiguous;
|
||||
pMapInfo->pmaMapGetSize = pmaAddrtreeGetSize;
|
||||
pMapInfo->pmaMapGetLargestFree = pmaAddrtreeGetLargestFree;
|
||||
pMapInfo->pmaMapScanContiguousNumaEviction = pmaAddrtreeScanContiguousNumaEviction;
|
||||
pMapInfo->pmaMapGetEvictingFrames = pmaAddrtreeGetEvictingFrames;
|
||||
pMapInfo->pmaMapSetEvictingFrames = pmaAddrtreeSetEvictingFrames;
|
||||
NV_PRINTF(LEVEL_WARNING, "Going to use addrtree for PMA init!!\n");
|
||||
}
|
||||
}
|
||||
pPma->pMapInfo = pMapInfo;
|
||||
|
||||
@@ -589,22 +569,12 @@ pmaAllocatePages
|
||||
|
||||
const NvU64 numFramesToAllocateTotal = framesPerPage * allocationCount;
|
||||
|
||||
if (pPma == NULL || pPages == NULL || allocationCount == 0
|
||||
|| (pageSize != _PMA_64KB && pageSize != _PMA_128KB && pageSize != _PMA_2MB && pageSize != _PMA_512MB)
|
||||
|| allocationOptions == NULL)
|
||||
{
|
||||
if (pPma == NULL)
|
||||
NV_PRINTF(LEVEL_ERROR, "NULL PMA object\n");
|
||||
if (pPages == NULL)
|
||||
NV_PRINTF(LEVEL_ERROR, "NULL page list pointer\n");
|
||||
if (allocationCount == 0)
|
||||
NV_PRINTF(LEVEL_ERROR, "count == 0\n");
|
||||
if (pageSize != _PMA_64KB && pageSize != _PMA_128KB && pageSize != _PMA_2MB && pageSize != _PMA_512MB)
|
||||
NV_PRINTF(LEVEL_ERROR, "pageSize=0x%llx (not 64K, 128K, 2M, or 512M)\n", pageSize);
|
||||
if (allocationOptions == NULL)
|
||||
NV_PRINTF(LEVEL_ERROR, "NULL allocationOptions\n");
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
NV_CHECK_OR_RETURN(LEVEL_ERROR, pPma != NULL, NV_ERR_INVALID_ARGUMENT);
|
||||
NV_CHECK_OR_RETURN(LEVEL_ERROR, pPages != NULL, NV_ERR_INVALID_ARGUMENT);
|
||||
NV_CHECK_OR_RETURN(LEVEL_ERROR, allocationCount != 0, NV_ERR_INVALID_ARGUMENT);
|
||||
NV_CHECK_OR_RETURN(LEVEL_ERROR, allocationOptions != NULL, NV_ERR_INVALID_ARGUMENT);
|
||||
NV_CHECK_OR_RETURN(LEVEL_ERROR, portUtilIsPowerOfTwo(pageSize), NV_ERR_INVALID_ARGUMENT);
|
||||
NV_CHECK_OR_RETURN(LEVEL_ERROR, pageSize >= _PMA_64KB, NV_ERR_INVALID_ARGUMENT);
|
||||
|
||||
flags = allocationOptions->flags;
|
||||
evictFlag = !(flags & PMA_ALLOCATE_DONT_EVICT);
|
||||
@@ -673,23 +643,14 @@ pmaAllocatePages
|
||||
//
|
||||
if (alignFlag)
|
||||
{
|
||||
if (!NV_IS_ALIGNED(allocationOptions->alignment, _PMA_64KB) ||
|
||||
!portUtilIsPowerOfTwo(allocationOptions->alignment))
|
||||
{
|
||||
NV_PRINTF(LEVEL_WARNING,
|
||||
"alignment [%llx] is not aligned to 64KB or is not power of two.",
|
||||
alignment);
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
NV_CHECK_OR_RETURN(LEVEL_ERROR,
|
||||
portUtilIsPowerOfTwo(allocationOptions->alignment),
|
||||
NV_ERR_INVALID_ARGUMENT);
|
||||
NV_CHECK_OR_RETURN(LEVEL_ERROR,
|
||||
allocationOptions->alignment >= _PMA_64KB,
|
||||
NV_ERR_INVALID_ARGUMENT);
|
||||
|
||||
alignment = NV_MAX(pageSize, allocationOptions->alignment);
|
||||
if (!contigFlag && alignment > pageSize)
|
||||
{
|
||||
NV_PRINTF(LEVEL_WARNING,
|
||||
"alignment [%llx] larger than the pageSize [%llx] not supported for non-contiguous allocs\n",
|
||||
alignment, pageSize);
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
alignment = allocationOptions->alignment;
|
||||
}
|
||||
|
||||
pinOption = pinFlag ? STATE_PIN : STATE_UNPIN;
|
||||
@@ -836,15 +797,6 @@ pmaAllocatePages_retry:
|
||||
curPages += numPagesAllocatedThisTime;
|
||||
numPagesLeftToAllocate -= numPagesAllocatedThisTime;
|
||||
|
||||
//
|
||||
// PMA must currently catch addrtree shortcomings and fail the request
|
||||
// Just follow the no memory path for now to properly release locks
|
||||
//
|
||||
if (status == NV_ERR_INVALID_ARGUMENT)
|
||||
{
|
||||
status = NV_ERR_NO_MEMORY;
|
||||
}
|
||||
|
||||
if (status == NV_ERR_IN_USE && !tryEvict)
|
||||
{
|
||||
//
|
||||
@@ -1193,13 +1145,6 @@ pmaAllocatePagesBroadcast
|
||||
)
|
||||
{
|
||||
|
||||
if (pPma == NULL || pmaCount == 0 || allocationCount == 0
|
||||
|| (pageSize != _PMA_64KB && pageSize != _PMA_128KB && pageSize != _PMA_2MB && pageSize != _PMA_512MB)
|
||||
|| pPages == NULL)
|
||||
{
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
|
||||
return NV_ERR_GENERIC;
|
||||
}
|
||||
|
||||
@@ -1218,11 +1163,9 @@ pmaPinPages
|
||||
PMA_PAGESTATUS state;
|
||||
framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT);
|
||||
|
||||
if (pPma == NULL || pageCount == 0 || pPages == NULL
|
||||
|| (pageSize != _PMA_64KB && pageSize != _PMA_128KB && pageSize != _PMA_2MB && pageSize != _PMA_512MB))
|
||||
{
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
NV_CHECK_OR_RETURN(LEVEL_ERROR,
|
||||
(pPma != NULL) && (pageCount != 0) && (pPages != NULL),
|
||||
NV_ERR_INVALID_ARGUMENT);
|
||||
|
||||
portSyncSpinlockAcquire(pPma->pPmaLock);
|
||||
|
||||
@@ -1351,14 +1294,6 @@ pmaFreePages
|
||||
NV_ASSERT(pageCount != 0);
|
||||
NV_ASSERT(pPages != NULL);
|
||||
|
||||
if (pageCount != 1)
|
||||
{
|
||||
NV_ASSERT((size == _PMA_64KB) ||
|
||||
(size == _PMA_128KB) ||
|
||||
(size == _PMA_2MB) ||
|
||||
(size == _PMA_512MB));
|
||||
}
|
||||
|
||||
// Fork out new code path for NUMA sub-allocation from OS
|
||||
if (pPma->bNuma)
|
||||
{
|
||||
|
||||
@@ -1074,8 +1074,6 @@ pmaRegmapScanDiscontiguous
|
||||
PMA_PAGESTATUS startStatus, endStatus;
|
||||
PMA_REGMAP *pRegmap = (PMA_REGMAP *)pMap;
|
||||
|
||||
NV_ASSERT(alignment == pageSize);
|
||||
|
||||
framesPerPage = pageSize >> PMA_PAGE_SHIFT;
|
||||
|
||||
//
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
/*
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
@@ -193,7 +193,7 @@ struct RM_POOL_ALLOC_MEM_RESERVE_INFO
|
||||
* pool.
|
||||
*
|
||||
* @param[in] pCtx Context for upstream allocator.
|
||||
* @param[in] pageSize Only for debugging.
|
||||
* @param[in] pageSize Page size to use when allocating from PMA
|
||||
* @param[in] pPage Output page handle from upstream.
|
||||
*
|
||||
* @return NV_STATUS
|
||||
@@ -203,20 +203,23 @@ allocUpstreamTopPool
|
||||
(
|
||||
void *pCtx,
|
||||
NvU64 pageSize,
|
||||
NvU64 numPages,
|
||||
POOLALLOC_HANDLE *pPage
|
||||
)
|
||||
{
|
||||
PMA_ALLOCATION_OPTIONS allocOptions = {0};
|
||||
RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo;
|
||||
NV_STATUS status;
|
||||
NvU64 i;
|
||||
NvU64 *pPageStore = portMemAllocNonPaged(sizeof(NvU64) * numPages);
|
||||
NV_STATUS status = NV_OK;
|
||||
|
||||
NV_ASSERT_OR_RETURN(NULL != pCtx, NV_ERR_INVALID_ARGUMENT);
|
||||
NV_ASSERT_OR_RETURN(NULL != pPage, NV_ERR_INVALID_ARGUMENT);
|
||||
NV_ASSERT_OR_RETURN(NULL != pPageStore, NV_ERR_NO_MEMORY);
|
||||
|
||||
// TODO: Replace the direct call to PMA with function pointer.
|
||||
pMemReserveInfo = (RM_POOL_ALLOC_MEM_RESERVE_INFO *)pCtx;
|
||||
allocOptions.flags = PMA_ALLOCATE_PINNED | PMA_ALLOCATE_PERSISTENT |
|
||||
PMA_ALLOCATE_CONTIGUOUS;
|
||||
allocOptions.flags = PMA_ALLOCATE_PINNED | PMA_ALLOCATE_PERSISTENT | PMA_ALLOCATE_FORCE_ALIGNMENT;
|
||||
allocOptions.alignment = PMA_CHUNK_SIZE_64K;
|
||||
|
||||
if (pMemReserveInfo->bSkipScrub)
|
||||
{
|
||||
@@ -227,20 +230,24 @@ allocUpstreamTopPool
|
||||
{
|
||||
allocOptions.flags |= PMA_ALLOCATE_PROTECTED_REGION;
|
||||
}
|
||||
|
||||
NV_ASSERT_OK_OR_GOTO(status,
|
||||
pmaAllocatePages(pMemReserveInfo->pPma,
|
||||
numPages,
|
||||
pageSize,
|
||||
&allocOptions,
|
||||
pPageStore),
|
||||
free_mem);
|
||||
|
||||
status = pmaAllocatePages(pMemReserveInfo->pPma,
|
||||
pMemReserveInfo->pmaChunkSize/PMA_CHUNK_SIZE_64K,
|
||||
PMA_CHUNK_SIZE_64K,
|
||||
&allocOptions,
|
||||
&pPage->address);
|
||||
if (status != NV_OK)
|
||||
for (i = 0; i < numPages; i++)
|
||||
{
|
||||
return status;
|
||||
pPage[i].address = pPageStore[i];
|
||||
pPage[i].pMetadata = NULL;
|
||||
}
|
||||
|
||||
pPage->pMetadata = NULL;
|
||||
|
||||
free_mem:
|
||||
portMemFree(pPageStore);
|
||||
return status;
|
||||
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -258,17 +265,28 @@ allocUpstreamLowerPools
|
||||
(
|
||||
void *pCtx,
|
||||
NvU64 pageSize,
|
||||
NvU64 numPages,
|
||||
POOLALLOC_HANDLE *pPage
|
||||
)
|
||||
{
|
||||
NV_STATUS status;
|
||||
NvU64 i;
|
||||
|
||||
NV_ASSERT_OR_RETURN(NULL != pCtx, NV_ERR_INVALID_ARGUMENT);
|
||||
NV_ASSERT_OR_RETURN(NULL != pPage, NV_ERR_INVALID_ARGUMENT);
|
||||
|
||||
status = poolAllocate((POOLALLOC *)pCtx, pPage);
|
||||
NV_ASSERT_OR_RETURN(status == NV_OK, status);
|
||||
|
||||
for(i = 0; i < numPages; i++)
|
||||
{
|
||||
NV_ASSERT_OK_OR_GOTO(status,
|
||||
poolAllocate((POOLALLOC *)pCtx, &pPage[i]),
|
||||
cleanup);
|
||||
}
|
||||
return NV_OK;
|
||||
cleanup:
|
||||
for(;i > 0; i--)
|
||||
{
|
||||
poolFree((POOLALLOC *)pCtx, &pPage[i-1]);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
@@ -262,9 +262,12 @@ poolReserve
|
||||
NvU64 numPages
|
||||
)
|
||||
{
|
||||
NvU64 i, freeLength;
|
||||
NvU64 i, freeLength, totalAlloc;
|
||||
NV_STATUS status = NV_ERR_NO_MEMORY;
|
||||
allocCallback_t allocCb;
|
||||
POOLALLOC_HANDLE pageHandle;
|
||||
POOLALLOC_HANDLE *pPageHandle = NULL;
|
||||
POOLNODE *pNode = NULL;
|
||||
|
||||
|
||||
if (pPool == NULL || (pPool->callBackInfo).allocCb == NULL)
|
||||
{
|
||||
@@ -277,32 +280,45 @@ poolReserve
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
totalAlloc = numPages - freeLength;
|
||||
|
||||
allocCb = (pPool->callBackInfo).allocCb;
|
||||
|
||||
for (i = 0; i < (numPages - freeLength); i++)
|
||||
pPageHandle = PORT_ALLOC(pPool->pAllocator, totalAlloc * sizeof(POOLALLOC_HANDLE));
|
||||
NV_ASSERT_OR_GOTO(pPageHandle != NULL, free_none);
|
||||
|
||||
NV_ASSERT_OK_OR_GOTO(status,
|
||||
allocCb(pPool->callBackInfo.pUpstreamCtx, pPool->upstreamPageSize,
|
||||
totalAlloc, pPageHandle),
|
||||
free_page);
|
||||
|
||||
status = NV_ERR_NO_MEMORY;
|
||||
|
||||
for (i = 0; i < totalAlloc; i++)
|
||||
{
|
||||
if ((*allocCb)((pPool->callBackInfo).pUpstreamCtx,
|
||||
pPool->upstreamPageSize, &pageHandle) == NV_OK)
|
||||
{
|
||||
POOLNODE *pNode;
|
||||
pNode = PORT_ALLOC(pPool->pAllocator, sizeof(POOLNODE));
|
||||
NV_ASSERT_OR_GOTO(pNode != NULL, free_alloc);
|
||||
|
||||
pNode = PORT_ALLOC(pPool->pAllocator, sizeof(*pNode));
|
||||
listPrependExisting(&pPool->freeList, pNode);
|
||||
|
||||
pNode->pageAddr = pageHandle.address;
|
||||
pNode->bitmap = NV_U64_MAX;
|
||||
pNode->pParent = pageHandle.pMetadata;
|
||||
}
|
||||
else
|
||||
{
|
||||
return NV_ERR_NO_MEMORY;
|
||||
}
|
||||
listPrependExisting(&pPool->freeList, pNode);
|
||||
pNode->pageAddr = pPageHandle[i].address;
|
||||
pNode->bitmap = NV_U64_MAX;
|
||||
pNode->pParent = pPageHandle[i].pMetadata;
|
||||
}
|
||||
|
||||
status = NV_OK;
|
||||
freeLength = listCount(&pPool->freeList);
|
||||
NV_ASSERT(freeLength == numPages);
|
||||
|
||||
return NV_OK;
|
||||
goto free_page;
|
||||
free_alloc:
|
||||
for(; i < totalAlloc; i++)
|
||||
{
|
||||
pPool->callBackInfo.freeCb(pPool->callBackInfo.pUpstreamCtx,
|
||||
pPool->upstreamPageSize, &pPageHandle[i]);
|
||||
}
|
||||
free_page:
|
||||
PORT_FREE(pPool->pAllocator, pPageHandle);
|
||||
free_none:
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
@@ -383,7 +399,7 @@ poolAllocate
|
||||
//
|
||||
if (FLD_TEST_DRF(_RMPOOL, _FLAGS, _AUTO_POPULATE, _ENABLE, pPool->flags))
|
||||
{
|
||||
if ((*allocCb)(pPool->callBackInfo.pUpstreamCtx, pPool->upstreamPageSize, pPageHandle) == NV_OK)
|
||||
if ((*allocCb)(pPool->callBackInfo.pUpstreamCtx, pPool->upstreamPageSize, 1, pPageHandle) == NV_OK)
|
||||
{
|
||||
POOLNODE *pNode;
|
||||
|
||||
|
||||
@@ -522,7 +522,6 @@ SRCS += src/kernel/gpu/mem_mgr/mem_scrub.c
|
||||
SRCS += src/kernel/gpu/mem_mgr/mem_utils.c
|
||||
SRCS += src/kernel/gpu/mem_mgr/method_notification.c
|
||||
SRCS += src/kernel/gpu/mem_mgr/objheap.c
|
||||
SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c
|
||||
SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c
|
||||
SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c
|
||||
SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
NVIDIA_VERSION = 535.43.09
|
||||
NVIDIA_VERSION = 535.43.22
|
||||
|
||||
# This file.
|
||||
VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))
|
||||
|
||||
Reference in New Issue
Block a user