550.40.55

CHANGELOG.md

@@ -2,7 +2,9 @@
 
 ## Release 550 Entries
 
-### [550.54.14] 2024-02-23
+### [550.40.55] 2024-03-07
+
+### [550.40.53] 2024-02-28
 
 #### Added
 
@@ -13,11 +15,8 @@
 #### Fixed
 
 - Set INSTALL_MOD_DIR only if it's not defined, [#570](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/570) by @keelung-yang
-
 ## Release 545 Entries
 
-### [545.29.06] 2023-11-22
-
 #### Fixed
 
 - The brightness control of NVIDIA seems to be broken, [#573](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/573)

README.md

@@ -1,7 +1,7 @@
 # NVIDIA Linux Open GPU Kernel Module Source
 
 This is the source release of the NVIDIA Linux open GPU kernel modules,
-version 550.54.14.
+version 550.40.55.
 
 
 ## How to Build
@@ -17,7 +17,7 @@ as root:
 
 Note that the kernel modules built here must be used with GSP
 firmware and user-space NVIDIA GPU driver components from a corresponding
-550.54.14 driver release.  This can be achieved by installing
+550.40.55 driver release.  This can be achieved by installing
 the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
 option.  E.g.,
 
@@ -188,7 +188,7 @@ encountered specific to them.
 For details on feature support and limitations, see the NVIDIA GPU driver
 end user README here:
 
-https://us.download.nvidia.com/XFree86/Linux-x86_64/550.54.14/README/kernel_open.html
+https://us.download.nvidia.com/XFree86/Linux-x86_64/550.40.55/README/kernel_open.html
 
 For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
 Package for more details.
@@ -907,6 +907,9 @@ Subsystem Device ID.
 | NVIDIA RTX 2000 Ada Generation                  | 28B0 10DE 1870 |
 | NVIDIA RTX 2000 Ada Generation                  | 28B0 17AA 1870 |
 | NVIDIA RTX 2000 Ada Generation Laptop GPU       | 28B8           |
+| NVIDIA RTX 1000 Ada Generation Laptop GPU       | 28B9           |
+| NVIDIA RTX 500 Ada Generation Laptop GPU        | 28BA           |
+| NVIDIA RTX 500 Ada Generation Laptop GPU        | 28BB           |
 | NVIDIA GeForce RTX 4060 Laptop GPU              | 28E0           |
 | NVIDIA GeForce RTX 4050 Laptop GPU              | 28E1           |
 | NVIDIA RTX 2000 Ada Generation Embedded GPU     | 28F8           |

kernel-open/Kbuild

@@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
 EXTRA_CFLAGS += -I$(src)
 EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
 EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
-EXTRA_CFLAGS += -DNV_VERSION_STRING=\"550.54.14\"
+EXTRA_CFLAGS += -DNV_VERSION_STRING=\"550.40.55\"
 
 ifneq ($(SYSSRCHOST1X),)
  EXTRA_CFLAGS += -I$(SYSSRCHOST1X)

kernel-open/conftest.sh

@@ -3096,6 +3096,22 @@ compile_test() {
 
         ;;
 
+        foll_longterm_present)
+            #
+            # Determine if FOLL_LONGTERM enum is present or not
+            #
+            # Added by commit 932f4a630a69 ("mm/gup: replace
+            # get_user_pages_longterm() with FOLL_LONGTERM") in
+            # v5.2
+            #
+            CODE="
+            #include <linux/mm.h>
+            int foll_longterm = FOLL_LONGTERM;
+            "
+
+            compile_check_conftest "$CODE" "NV_FOLL_LONGTERM_PRESENT" "" "types"
+        ;;
+
         vfio_pin_pages_has_vfio_device_arg)
             #
             # Determine if vfio_pin_pages() kABI accepts "struct vfio_device *"

kernel-open/nvidia-drm/nvidia-drm-drv.c

@@ -1903,8 +1903,33 @@ void nv_drm_remove_devices(void)
  */
 void nv_drm_suspend_resume(NvBool suspend)
 {
+    static DEFINE_MUTEX(nv_drm_suspend_mutex);
+    static NvU32 nv_drm_suspend_count = 0;
+    struct nv_drm_device *nv_dev;
+
+    mutex_lock(&nv_drm_suspend_mutex);
+
+    /*
+     * Count the number of times the driver is asked to suspend. Suspend all DRM
+     * devices on the first suspend call and resume them on the last resume
+     * call.  This is necessary because the kernel may call nvkms_suspend()
+     * simultaneously for each GPU, but NVKMS itself also suspends all GPUs on
+     * the first call.
+     */
+    if (suspend) {
+        if (nv_drm_suspend_count++ > 0) {
+            goto done;
+        }
+    } else {
+        BUG_ON(nv_drm_suspend_count == 0);
+
+        if (--nv_drm_suspend_count > 0) {
+            goto done;
+        }
+    }
+
 #if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
-    struct nv_drm_device *nv_dev = dev_list;
+    nv_dev = dev_list;
 
     /*
      * NVKMS shuts down all heads on suspend. Update DRM state accordingly.
@@ -1930,6 +1955,9 @@ void nv_drm_suspend_resume(NvBool suspend)
         }
     }
 #endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+
+done:
+    mutex_unlock(&nv_drm_suspend_mutex);
 }
 
 #endif /* NV_DRM_AVAILABLE */

kernel-open/nvidia-modeset/nvidia-modeset-linux.c

@@ -56,7 +56,11 @@
 #include "nv-lock.h"
 #include "nv-chardev-numbers.h"
 
-#if !defined(CONFIG_RETPOLINE)
+/*
+ * Commit aefb2f2e619b ("x86/bugs: Rename CONFIG_RETPOLINE =>
+ * CONFIG_MITIGATION_RETPOLINE) in v6.8 renamed CONFIG_RETPOLINE.
+ */
+#if !defined(CONFIG_RETPOLINE) && !defined(CONFIG_MITIGATION_RETPOLINE)
 #include "nv-retpoline.h"
 #endif
 
@@ -499,8 +503,9 @@ nvkms_event_queue_changed(nvkms_per_open_handle_t *pOpenKernel,
 
 static void nvkms_suspend(NvU32 gpuId)
 {
+    nvKmsKapiSuspendResume(NV_TRUE /* suspend */);
+
     if (gpuId == 0) {
-        nvKmsKapiSuspendResume(NV_TRUE /* suspend */);
         nvkms_write_lock_pm_lock();
     }
 
@@ -517,8 +522,9 @@ static void nvkms_resume(NvU32 gpuId)
 
     if (gpuId == 0) {
         nvkms_write_unlock_pm_lock();
-        nvKmsKapiSuspendResume(NV_FALSE /* suspend */);
     }
+
+    nvKmsKapiSuspendResume(NV_FALSE /* suspend */);
 }
 
 

kernel-open/nvidia/nv.c

@@ -57,7 +57,11 @@
 #include "nv-dmabuf.h"
 #include "nv-caps-imex.h"
 
-#if !defined(CONFIG_RETPOLINE)
+/*
+ * Commit aefb2f2e619b ("x86/bugs: Rename CONFIG_RETPOLINE =>
+ * CONFIG_MITIGATION_RETPOLINE) in v6.8 renamed CONFIG_RETPOLINE.
+ */
+#if !defined(CONFIG_RETPOLINE) && !defined(CONFIG_MITIGATION_RETPOLINE)
 #include "nv-retpoline.h"
 #endif
 

kernel-open/nvidia/nvidia.Kbuild

@@ -250,6 +250,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += num_registered_fb
 NV_CONFTEST_TYPE_COMPILE_TESTS += pci_driver_has_driver_managed_dma
 NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags
 NV_CONFTEST_TYPE_COMPILE_TESTS += memory_failure_has_trapno_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += foll_longterm_present
 
 NV_CONFTEST_GENERIC_COMPILE_TESTS += dom0_kernel_present
 NV_CONFTEST_GENERIC_COMPILE_TESTS += nvidia_vgpu_kvm_build

kernel-open/nvidia/os-mlock.c

@@ -26,6 +26,12 @@
 #include "os-interface.h"
 #include "nv-linux.h"
 
+#if defined(NVCPU_FAMILY_X86) && defined(NV_FOLL_LONGTERM_PRESENT) && \
+    (defined(NV_PIN_USER_PAGES_HAS_ARGS_VMAS) ||                      \
+     defined(NV_GET_USER_PAGES_HAS_ARGS_FLAGS_VMAS))
+#define NV_NUM_PIN_PAGES_PER_ITERATION 0x80000
+#endif
+
 static inline int nv_follow_pfn(struct vm_area_struct *vma,
                                 unsigned long address,
                                 unsigned long *pfn)
@@ -163,9 +169,15 @@ NV_STATUS NV_API_CALL os_lock_user_pages(
     NV_STATUS rmStatus;
     struct mm_struct *mm = current->mm;
     struct page **user_pages;
-    NvU64 i, pinned;
+    NvU64 i;
+    NvU64 npages = page_count;
+    NvU64 pinned = 0;
     unsigned int gup_flags = DRF_VAL(_LOCK_USER_PAGES, _FLAGS, _WRITE, flags) ? FOLL_WRITE : 0;
-    int ret;
+    long ret;
+
+#if defined(NVCPU_FAMILY_X86) && defined(NV_FOLL_LONGTERM_PRESENT)
+    gup_flags |= FOLL_LONGTERM;
+#endif
 
     if (!NV_MAY_SLEEP())
     {
@@ -185,16 +197,51 @@ NV_STATUS NV_API_CALL os_lock_user_pages(
 
     nv_mmap_read_lock(mm);
     ret = NV_PIN_USER_PAGES((unsigned long)address,
-                            page_count, gup_flags, user_pages);
-    nv_mmap_read_unlock(mm);
-    pinned = ret;
-
-    if (ret < 0)
+                            npages, gup_flags, user_pages);
+    if (ret > 0)
     {
-        os_free_mem(user_pages);
-        return NV_ERR_INVALID_ADDRESS;
+        pinned = ret;
     }
-    else if (pinned < page_count)
+#if defined(NVCPU_FAMILY_X86) && defined(NV_FOLL_LONGTERM_PRESENT) && \
+    (defined(NV_PIN_USER_PAGES_HAS_ARGS_VMAS) ||                      \
+     defined(NV_GET_USER_PAGES_HAS_ARGS_FLAGS_VMAS))
+    //
+    // NV_PIN_USER_PAGES() passes in NULL for the vmas parameter (if required)
+    // in pin_user_pages() (or get_user_pages() if pin_user_pages() does not
+    // exist). For kernels which do not contain the commit 52650c8b466b
+    // (mm/gup: remove the vma allocation from gup_longterm_locked()), if
+    // FOLL_LONGTERM is passed in, this results in the kernel trying to kcalloc
+    // the vmas array, and since the limit for kcalloc is 4 MB, it results in
+    // NV_PIN_USER_PAGES() failing with ENOMEM if more than
+    // NV_NUM_PIN_PAGES_PER_ITERATION pages are requested on 64-bit systems.
+    //
+    // As a workaround, if we requested more than
+    // NV_NUM_PIN_PAGES_PER_ITERATION pages and failed with ENOMEM, try again
+    // with multiple calls of NV_NUM_PIN_PAGES_PER_ITERATION pages at a time.
+    //
+    else if ((ret == -ENOMEM) &&
+             (page_count > NV_NUM_PIN_PAGES_PER_ITERATION))
+    {
+        for (pinned = 0; pinned < page_count; pinned += ret)
+        {
+            npages = page_count - pinned;
+            if (npages > NV_NUM_PIN_PAGES_PER_ITERATION)
+            {
+                npages = NV_NUM_PIN_PAGES_PER_ITERATION;
+            }
+
+            ret = NV_PIN_USER_PAGES(((unsigned long) address) + (pinned * PAGE_SIZE),
+                                    npages, gup_flags, &user_pages[pinned]);
+            if (ret <= 0)
+            {
+                break;
+            }
+        }
+    }
+#endif
+    nv_mmap_read_unlock(mm);
+
+    if (pinned < page_count)
     {
         for (i = 0; i < pinned; i++)
             NV_UNPIN_USER_PAGE(user_pages[i]);

src/common/displayport/inc/dp_connectorimpl.h

@@ -348,6 +348,9 @@ namespace DisplayPort
         //
         bool        bPowerDownPhyBeforeD3;
 
+        // Force DSC on sink irrespective of LT status
+        bool        bForceDscOnSink;
+
         //
         // Reset the MSTM_CTRL registers on branch device irrespective of
         // IRQ VECTOR register having stale message. Certain branch devices

src/common/displayport/inc/dp_linkconfig.h

@@ -294,8 +294,8 @@ namespace DisplayPort
             else
             {
                 // if FEC is not enabled, link overhead comprises only of
-                // 0.05% downspread.
-                return rate - 5 * rate/ 1000;
+                // 0.6% downspread.
+                return rate - 6 * rate/ 1000;
 
             }
         }

src/common/displayport/inc/dp_regkeydatabase.h

@@ -79,6 +79,11 @@
 //
 #define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED       "DP_BUG_4388987_WAR"
 
+//
+// Bug 4459839 : This regkey will enable DSC irrespective of LT status.
+//
+#define NV_DP_REGKEY_FORCE_DSC_ON_SINK                 "DP_FORCE_DSC_ON_SINK"
+
 //
 // Data Base used to store all the regkey values.
 // The actual data base is declared statically in dp_evoadapter.cpp.
@@ -113,6 +118,7 @@ struct DP_REGKEY_DATABASE
     bool  bPowerDownPhyBeforeD3;
     bool  bReassessMaxLink;
     bool  bMSTPCONCapsReadDisabled;
+    bool  bForceDscOnSink;
 };
 
 #endif //INCLUDED_DP_REGKEYDATABASE_H

src/common/displayport/src/dp_connectorimpl.cpp

@@ -174,6 +174,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
     this->bDscMstCapBug3143315          = dpRegkeyDatabase.bDscMstCapBug3143315;
     this->bPowerDownPhyBeforeD3         = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
     this->bReassessMaxLink              = dpRegkeyDatabase.bReassessMaxLink;
+    this->bForceDscOnSink               = dpRegkeyDatabase.bForceDscOnSink;
 }
 
 void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -3129,7 +3130,7 @@ bool ConnectorImpl::notifyAttachBegin(Group *                target,       // Gr
 
     // if LT is successful, see if panel supports DSC and if so, set DSC enabled/disabled
     // according to the mode requested.
-    if(bLinkTrainingStatus)
+    if(bLinkTrainingStatus || bForceDscOnSink)
     {
         for (Device * dev = target->enumDevices(0); dev; dev = target->enumDevices(dev))
         {
@@ -4631,6 +4632,11 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
                 }
             }
 
+            //
+            // There is no point in fallback here since we are link training  
+            // to loweset link config that can support the mode.
+            //
+            lowestSelected.policy.setSkipFallBack(true);
             bLinkTrainingSuccessful = train(lowestSelected, false);
             //
             // If LT failed, check if skipLT was marked. If so, clear the flag and
@@ -4648,16 +4654,37 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
             }
             if (!bLinkTrainingSuccessful)
             {
-                // Try fall back to max link config and if that fails try original assessed link configuration
+                // If optimized link config fails, try max link config with fallback. 
                 if (!train(getMaxLinkConfig(), false))
                 {
+                    //
+                    // Note here that if highest link config fails and a lower  
+                    // link config passes, link training will be returned as 
+                    // failure but activeLinkConfig will be set to that passing config.
+                    // 
                     if (!willLinkSupportModeSST(activeLinkConfig, groupAttached->lastModesetInfo))
                     {
+                        //
+                        // If none of the link configs pass LT or a fall back link config passed LT 
+                        // but cannot support the mode, then we will force the optimized link config
+                        // on the link and mark LT as fail.
+                        //
                         train(lowestSelected, true);
-
-                        // Mark link training as failed since we forced it
                         bLinkTrainingSuccessful = false;
                     }
+                    else
+                    {
+                        //
+                        // If a fallback link config pass LT and can support 
+                        // the mode, mark LT as pass.
+                        //
+                        bLinkTrainingSuccessful = true;
+                    }
+                }
+                else
+                {
+                    // If LT passes at max link config, mark LT as pass.
+                    bLinkTrainingSuccessful = true;
                 }
             }
         }

src/common/displayport/src/dp_evoadapter.cpp

@@ -94,7 +94,8 @@ const struct
     {NV_DP_DSC_MST_CAP_BUG_3143315,                 &dpRegkeyDatabase.bDscMstCapBug3143315,            DP_REG_VAL_BOOL},
     {NV_DP_REGKEY_POWER_DOWN_PHY,                   &dpRegkeyDatabase.bPowerDownPhyBeforeD3,           DP_REG_VAL_BOOL},
     {NV_DP_REGKEY_REASSESS_MAX_LINK,                &dpRegkeyDatabase.bReassessMaxLink,                DP_REG_VAL_BOOL},
-    {NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED,      &dpRegkeyDatabase.bMSTPCONCapsReadDisabled,        DP_REG_VAL_BOOL}
+    {NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED,      &dpRegkeyDatabase.bMSTPCONCapsReadDisabled,        DP_REG_VAL_BOOL},
+    {NV_DP_REGKEY_FORCE_DSC_ON_SINK,                &dpRegkeyDatabase.bForceDscOnSink,                 DP_REG_VAL_BOOL},
 };
 
 EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

src/common/inc/nvBldVer.h

@@ -36,25 +36,25 @@
 // and then checked back in. You cannot make changes to these sections without
 // corresponding changes to the buildmeister script
 #ifndef NV_BUILD_BRANCH
-    #define NV_BUILD_BRANCH             r551_40
+    #define NV_BUILD_BRANCH             VK551_06
 #endif
 #ifndef NV_PUBLIC_BRANCH
-    #define NV_PUBLIC_BRANCH             r551_40
+    #define NV_PUBLIC_BRANCH             VK551_06
 #endif
 
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
-#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r550/r551_40-170"
-#define NV_BUILD_CHANGELIST_NUM         (33933991)
+#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r550/VK551_06-133"
+#define NV_BUILD_CHANGELIST_NUM         (34004351)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "rel/gpu_drv/r550/r551_40-170"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33933991)
+#define NV_BUILD_NAME                   "rel/gpu_drv/r550/VK551_06-133"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34004351)
 
 #else     /* Windows builds */
-#define NV_BUILD_BRANCH_VERSION         "r551_40-13"
-#define NV_BUILD_CHANGELIST_NUM         (33924744)
-#define NV_BUILD_TYPE                   "Nightly"
-#define NV_BUILD_NAME                   "r551_40-240221"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33921227)
+#define NV_BUILD_BRANCH_VERSION         "VK551_06-6"
+#define NV_BUILD_CHANGELIST_NUM         (34004351)
+#define NV_BUILD_TYPE                   "Official"
+#define NV_BUILD_NAME                   "551.81"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34004351)
 #define NV_BUILD_BRANCH_BASE_VERSION    R550
 #endif
 // End buildmeister python edited section

src/common/inc/nvUnixVersion.h

@@ -4,7 +4,7 @@
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
     (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
 
-#define NV_VERSION_STRING               "550.54.14"
+#define NV_VERSION_STRING               "550.40.55"
 
 #else
 

src/common/nvswitch/kernel/inc/boards_nvswitch.h

@@ -38,6 +38,7 @@
 #define NVSWITCH_BOARD_LS10_5612_0002_ES    0x03D6
 #define NVSWITCH_BOARD_LS10_4697_0000_895   0x03B9
 #define NVSWITCH_BOARD_LS10_4262_0000_895   0x04FE
+#define NVSWITCH_BOARD_LS10_4300_0000_895   0x0571
 
 #define NVSWITCH_BOARD_UNKNOWN_NAME             "UNKNOWN"
 
@@ -48,5 +49,6 @@
 #define NVSWITCH_BOARD_LS10_5612_0002_ES_NAME   "LS10_5612_0002_ES"
 #define NVSWITCH_BOARD_LS10_4697_0000_895_NAME  "LS10_4697_0000_895"
 #define NVSWITCH_BOARD_LS10_4262_0000_895_NAME  "LS10_4262_0000_895"
+#define NVSWITCH_BOARD_LS10_4300_0000_895_NAME  "LS10_4300_0000_895"
 
 #endif // _BOARDS_NVSWITCH_H_

src/common/nvswitch/kernel/ls10/intr_ls10.c

@@ -894,9 +894,9 @@ _nvswitch_collect_error_info_ls10
             {
                 data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR;
                 NVSWITCH_PRINT(device, INFO,
-                    "ROUTE: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
-                    data->data[i-8], data->data[i-7], data->data[i-6], data->data[i-5],
-                    data->data[i-4], data->data[i-3], data->data[i-2], data->data[i-1]);
+                    "ROUTE: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
+                    data->data[i-7], data->data[i-6], data->data[i-5], data->data[i-4],
+                    data->data[i-3], data->data[i-2], data->data[i-1]);
             }
         }
     }
@@ -940,9 +940,9 @@ _nvswitch_collect_error_info_ls10
             {
                 data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR;
                 NVSWITCH_PRINT(device, INFO,
-                    "INGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
-                    data->data[i-7], data->data[i-6], data->data[i-5], data->data[i-4],
-                    data->data[i-3], data->data[i-2], data->data[i-1]);
+                    "INGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
+                    data->data[i-6], data->data[i-5], data->data[i-4], data->data[i-3],
+                    data->data[i-2], data->data[i-1]);
             }
         }
     }

src/common/nvswitch/kernel/ls10/pmgr_ls10.c

@@ -32,6 +32,7 @@
 #include "export_nvswitch.h"
 #include "soe/soe_nvswitch.h"
 #include "soe/soeifcore.h"
+#include "boards_nvswitch.h"
 
 #include "nvswitch/ls10/dev_pmgr.h"
 
@@ -176,6 +177,16 @@ static const NVSWITCH_GPIO_INFO nvswitch_gpio_pin_Default[] =
 
 static const NvU32 nvswitch_gpio_pin_Default_size = NV_ARRAY_ELEMENTS(nvswitch_gpio_pin_Default);
 
+static const NVSWITCH_GPIO_INFO nvswitch_gpio_pin_4300[] =
+{
+    NVSWITCH_DESCRIBE_GPIO_PIN( 0, _INSTANCE_ID0,   0, IN),          // Instance ID bit 0
+    NVSWITCH_DESCRIBE_GPIO_PIN( 1, _INSTANCE_ID1,   0, IN),          // Instance ID bit 1
+    NVSWITCH_DESCRIBE_GPIO_PIN( 2, _INSTANCE_ID2,   0, IN),          // Instance ID bit 2
+    NVSWITCH_DESCRIBE_GPIO_PIN( 6, _INSTANCE_ID3,   0, IN),          // Instance ID bit 3
+    NVSWITCH_DESCRIBE_GPIO_PIN( 7, _INSTANCE_ID4,   0, IN),          // Instance ID bit 4
+};
+static const NvU32 nvswitch_gpio_pin_4300_size = NV_ARRAY_ELEMENTS(nvswitch_gpio_pin_4300);
+
 //
 // Initialize the software state of the switch I2C & GPIO interface
 // Temporarily forcing default GPIO values.
@@ -191,6 +202,8 @@ nvswitch_init_pmgr_devices_ls10
 {
     ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device);
     PNVSWITCH_OBJI2C pI2c = device->pI2c;
+    NvlStatus retval;
+    NvU16 boardId;
 
     if (IS_FMODEL(device) || IS_EMULATION(device) || IS_RTLSIM(device))
     {
@@ -200,8 +213,18 @@ nvswitch_init_pmgr_devices_ls10
     }
     else
     {
-        chip_device->gpio_pin = nvswitch_gpio_pin_Default;
-        chip_device->gpio_pin_size = nvswitch_gpio_pin_Default_size;
+        retval = nvswitch_get_board_id(device, &boardId);
+        if (retval == NVL_SUCCESS &&
+            boardId == NVSWITCH_BOARD_LS10_4300_0000_895)
+        {
+            chip_device->gpio_pin = nvswitch_gpio_pin_4300;
+            chip_device->gpio_pin_size = nvswitch_gpio_pin_4300_size;
+        }
+        else
+        {
+            chip_device->gpio_pin = nvswitch_gpio_pin_Default;
+            chip_device->gpio_pin_size = nvswitch_gpio_pin_Default_size;
+        }
     }
 
     pI2c->device_list = NULL;

src/common/nvswitch/kernel/nvswitch.c

@@ -62,7 +62,7 @@ static NvlStatus _nvswitch_ctrl_inband_flush_data(nvswitch_device *device, NVSWI
 #define NVSWITCH_DEV_CMD_DISPATCH_RESERVED(cmd)                                  \
     case cmd:                                                                    \
     {                                                                            \
-        retval = -NVL_ERR_NOT_IMPLEMENTED;                                       \
+        retval = -NVL_ERR_NOT_SUPPORTED;                                         \
         break;                                                                   \
     }                                                                            \
 

src/nvidia-modeset/Makefile

@@ -95,6 +95,7 @@ endif
 ifeq ($(TARGET_ARCH),aarch64)
   CFLAGS += -mgeneral-regs-only
   CFLAGS += -march=armv8-a
+  CFLAGS += -ffixed-x18
   CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mno-outline-atomics)
 endif
 

src/nvidia/Makefile

@@ -90,6 +90,7 @@ ifeq ($(TARGET_ARCH),aarch64)
   CFLAGS += -mgeneral-regs-only
   CFLAGS += -march=armv8-a
   CFLAGS += -mstrict-align
+  CFLAGS += -ffixed-x18
   CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mno-outline-atomics)
 endif
 

src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c

@@ -74,7 +74,7 @@ NV_STATUS hypervisorInjectInterrupt_IMPL
     NV_STATUS status = NV_ERR_NOT_SUPPORTED;
 
     if (pVgpuNsIntr->pVgpuVfioRef)
-        status = osVgpuInjectInterrupt(pVgpuNsIntr->pVgpuVfioRef);
+        return NV_ERR_NOT_SUPPORTED;
     else
     {
         if (pVgpuNsIntr->guestMSIAddr && pVgpuNsIntr->guestMSIData)

src/nvidia/generated/g_nv_name_released.h

@@ -1054,6 +1054,9 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x28B0, 0x1870, 0x10de, "NVIDIA RTX 2000 Ada Generation" },
     { 0x28B0, 0x1870, 0x17aa, "NVIDIA RTX 2000 Ada Generation" },
     { 0x28B8, 0x0000, 0x0000, "NVIDIA RTX 2000 Ada Generation Laptop GPU" },
+    { 0x28B9, 0x0000, 0x0000, "NVIDIA RTX 1000 Ada Generation Laptop GPU" },
+    { 0x28BA, 0x0000, 0x0000, "NVIDIA RTX 500 Ada Generation Laptop GPU" },
+    { 0x28BB, 0x0000, 0x0000, "NVIDIA RTX 500 Ada Generation Laptop GPU" },
     { 0x28E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" },
     { 0x28E1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" },
     { 0x28F8, 0x0000, 0x0000, "NVIDIA RTX 2000 Ada Generation Embedded GPU" },

src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h

@@ -103,4 +103,24 @@ typedef struct MESSAGE_QUEUE_COLLECTION
 #define GSP_MSG_QUEUE_HEADER_SIZE                                   RM_PAGE_SIZE
 #define GSP_MSG_QUEUE_HEADER_ALIGN                                             4   // 2 ^ 4 = 16
 
+/*!
+ * Calculate 32-bit checksum
+ *
+ * This routine assumes that the data is padded out with zeros to the next
+ * 8-byte alignment, and it is OK to read past the end to the 8-byte alignment.
+ */
+static NV_INLINE NvU32 _checkSum32(void *pData, NvU32 uLen)
+{
+    NvU64 *p        = (NvU64 *)pData;
+    NvU64 *pEnd     = (NvU64 *)((NvUPtr)pData + uLen);
+    NvU64  checkSum = 0;
+
+    NV_ASSERT_CHECKED(uLen > 0);
+
+    while (p < pEnd)
+        checkSum ^= *p++;
+
+    return NvU64_HI32(checkSum) ^ NvU64_LO32(checkSum);
+}
+
 #endif // _MESSAGE_QUEUE_PRIV_H_

src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c

@@ -585,6 +585,13 @@ kbifRestorePcieConfigRegisters_GM107
     NvU64     timeStampStart;
     NvU64     timeStampEnd;
 
+    if (pKernelBif->xveRegmapRef[0].bufBootConfigSpace == NULL)
+    {
+        NV_PRINTF(LEVEL_ERROR, "Config space buffer is NULL!\n");
+        NV_ASSERT(0);
+        return NV_ERR_OBJECT_NOT_FOUND;
+    }
+
     // Restore pcie config space for function 0
     status = _kbifRestorePcieConfigRegisters_GM107(pGpu, pKernelBif,
                                                    &pKernelBif->xveRegmapRef[0]);

src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c

@@ -476,24 +476,6 @@ void GspMsgQueuesCleanup(MESSAGE_QUEUE_COLLECTION **ppMQCollection)
     *ppMQCollection = NULL;
 }
 
-/*!
- * Calculate 32-bit checksum
- *
- * This routine assumes that the data is padded out with zeros to the next
- * 8-byte alignment, and it is OK to read past the end to the 8-byte alignment.
- */
-static NV_INLINE NvU32 _checkSum32(void *pData, NvU32 uLen)
-{
-    NvU64 *p        = (NvU64 *)pData;
-    NvU64 *pEnd     = (NvU64 *)((NvUPtr)pData + uLen);
-    NvU64  checkSum = 0;
-
-    while (p < pEnd)
-        checkSum ^= *p++;
-
-    return NvU64_HI32(checkSum) ^ NvU64_LO32(checkSum);
-}
-
 /*!
  * GspMsgQueueSendCommand
  *
@@ -532,7 +514,7 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu)
 
     pCQE->seqNum    = pMQI->txSeqNum;
     pCQE->elemCount = GSP_MSG_QUEUE_BYTES_TO_ELEMENTS(uElementSize);
-    pCQE->checkSum  = 0;
+    pCQE->checkSum  = 0; // The checkSum field is included in the checksum calculation, so zero it.
 
     if (gpuIsCCFeatureEnabled(pGpu))
     {
@@ -666,7 +648,8 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu)
     NvU32       nRetries;
     NvU32       nMaxRetries  = 3;
     NvU32       nElements    = 1;  // Assume record fits in one queue element for now.
-    NvU32       uElementSize = 0;
+    NvU32       uElementSize;
+    NvU32       checkSum;
     NvU32       seqMismatchDiff = NV_U32_MAX;
     NV_STATUS   nvStatus     = NV_OK;
 
@@ -717,15 +700,23 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu)
         // Retry if checksum fails.
         if (gpuIsCCFeatureEnabled(pGpu))
         {
-            // In Confidential Compute scenario, checksum includes complete element range.
-            if (_checkSum32(pMQI->pCmdQueueElement, (nElements * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN)) != 0)
-            {
-                NV_PRINTF(LEVEL_ERROR, "Bad checksum.\n");
-                nvStatus = NV_ERR_INVALID_DATA;
-                continue;
-            }
+            //
+            // In the Confidential Compute scenario, the actual message length
+            // is inside the encrypted payload, and we can't access it before
+            // decryption, therefore the checksum encompasses the whole element
+            // range. This makes checksum verification significantly slower
+            // because messages are typically much smaller than element size.
+            //
+            checkSum = _checkSum32(pMQI->pCmdQueueElement,
+                                   (nElements * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN));
         } else
-        if (_checkSum32(pMQI->pCmdQueueElement, uElementSize) != 0)
+        {
+            checkSum = _checkSum32(pMQI->pCmdQueueElement,
+                                   (GSP_MSG_QUEUE_ELEMENT_HDR_SIZE +
+                                    pMQI->pCmdQueueElement->rpc.length));
+        }
+
+        if (checkSum != 0)
         {
             NV_PRINTF(LEVEL_ERROR, "Bad checksum.\n");
             nvStatus = NV_ERR_INVALID_DATA;

src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a

src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -475,11 +475,14 @@ _kmemsysGetFbInfos
                         // It will be zero unless VGA display memory is reserved
                         if (pKernelMemorySystem->fbOverrideStartKb != 0)
                         {
+                            status = NV_OK;
                             data = NvU64_LO32(pKernelMemorySystem->fbOverrideStartKb);
-                            NV_ASSERT(((NvU64) data << 10ULL) == pKernelMemorySystem->fbOverrideStartKb);
+                            NV_ASSERT_OR_ELSE((NvU64) data == pKernelMemorySystem->fbOverrideStartKb,
+                                              status = NV_ERR_INVALID_DATA);
+                            
                         }
-					    else
-				    	{
+                        else
+                        {
                             //
                             // Returns start of heap in kbytes. This is zero unless
                             // VGA display memory is reserved.

src/nvidia/src/kernel/mem_mgr/mem_export.c

@@ -606,7 +606,8 @@ _memoryexportVerifyMem
     if (pGpu == NULL)
         return NV_OK;
 
-    if (pKernelMIGGpuInstance != NULL)
+    // MIG is about vidmem partitioning, so limit the check.
+    if ((pKernelMIGGpuInstance != NULL) && (addrSpace == ADDR_FBMEM))
     {
         if ((pKernelMIGGpuInstance->pMemoryPartitionHeap != pSrcMemory->pHeap))
             return NV_ERR_INVALID_OBJECT_PARENT;

src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c

@@ -1396,15 +1396,9 @@ NvU32 kvgpumgrGetPgpuSubdevIdEncoding(OBJGPU *pGpu, NvU8 *pgpuString,
         return NV_U32_MAX;
     }
 
-    switch (chipID)
-    {
-        default:
-            // The encoding of the subdevice ID is its value converted to string
-            bytes = NvU32ToAsciiStr(subID, SUBDEVID_ENCODED_VALUE_SIZE,
+    // The encoding of the subdevice ID is its value converted to string
+    bytes = NvU32ToAsciiStr(subID, SUBDEVID_ENCODED_VALUE_SIZE,
                                     pgpuString, NV_FALSE);
-            break;
-    }
-
     return bytes;
 }
 

version.mk

@@ -1,4 +1,4 @@
-NVIDIA_VERSION = 550.54.14
+NVIDIA_VERSION = 550.40.55
 
 # This file.
 VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))