580.82.09

580.82.07
580.76.05
2026-01-27 11:39:46 +00:00 · 2025-09-09 16:15:34 -07:00 · 2025-09-02 10:35:52 -07:00 · 2025-08-12 12:13:43 -07:00 · 2025-08-04 11:15:02 -07:00 · 2025-07-22 21:09:46 +02:00
1639 changed files with 583155 additions and 345777 deletions
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 # NVIDIA Linux Open GPU Kernel Module Source

 This is the source release of the NVIDIA Linux open GPU kernel modules,
-version 570.133.20.
+version 580.82.09.


 ## How to Build
@@ -17,7 +17,7 @@ as root:

 Note that the kernel modules built here must be used with GSP
 firmware and user-space NVIDIA GPU driver components from a corresponding
-570.133.20 driver release.  This can be achieved by installing
+580.82.09 driver release.  This can be achieved by installing
 the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
 option.  E.g.,

@@ -185,7 +185,7 @@ table below).
 For details on feature support and limitations, see the NVIDIA GPU driver
 end user README here:

-https://us.download.nvidia.com/XFree86/Linux-x86_64/570.133.20/README/kernel_open.html
+https://us.download.nvidia.com/XFree86/Linux-x86_64/580.82.09/README/kernel_open.html

 For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
 Package for more details.
@@ -350,6 +350,7 @@ Subsystem Device ID.
 | Quadro RTX 4000 with Max-Q Design                       | 1EB6 1462 12C6 |
 | Quadro RTX 4000 with Max-Q Design                       | 1EB6 17AA 22B8 |
 | Quadro RTX 4000 with Max-Q Design                       | 1EB6 17AA 22BA |
+| Tesla T4                                                | 1EB8 10DE 12A2 |
 | NVIDIA GeForce RTX 2070 SUPER                           | 1EC2           |
 | NVIDIA GeForce RTX 2070 SUPER                           | 1EC7           |
 | NVIDIA GeForce RTX 2080                                 | 1ED0           |
@@ -748,6 +749,7 @@ Subsystem Device ID.
 | NVIDIA A10                                              | 2236 10DE 1482 |
 | NVIDIA A10G                                             | 2237 10DE 152F |
 | NVIDIA A10M                                             | 2238 10DE 1677 |
+| NVIDIA H20 NVL16                                        | 230E 10DE 20DF |
 | NVIDIA H100 NVL                                         | 2321 10DE 1839 |
 | NVIDIA H800 PCIe                                        | 2322 10DE 17A4 |
 | NVIDIA H800                                             | 2324 10DE 17A6 |
@@ -948,22 +950,63 @@ Subsystem Device ID.
 | NVIDIA GB200                                            | 2941 10DE 20D5 |
 | NVIDIA GB200                                            | 2941 10DE 21C9 |
 | NVIDIA GB200                                            | 2941 10DE 21CA |
+| NVIDIA DRIVE P2021                                      | 29BB 10DE 207C |
 | NVIDIA GeForce RTX 5090                                 | 2B85           |
 | NVIDIA GeForce RTX 5090 D                               | 2B87           |
+| NVIDIA GeForce RTX 5090 D v2                            | 2B8C           |
 | NVIDIA RTX PRO 6000 Blackwell Workstation Edition       | 2BB1 1028 204B |
 | NVIDIA RTX PRO 6000 Blackwell Workstation Edition       | 2BB1 103C 204B |
 | NVIDIA RTX PRO 6000 Blackwell Workstation Edition       | 2BB1 10DE 204B |
 | NVIDIA RTX PRO 6000 Blackwell Workstation Edition       | 2BB1 17AA 204B |
+| NVIDIA RTX PRO 5000 Blackwell                           | 2BB3 1028 204D |
+| NVIDIA RTX PRO 5000 Blackwell                           | 2BB3 103C 204D |
+| NVIDIA RTX PRO 5000 Blackwell                           | 2BB3 10DE 204D |
+| NVIDIA RTX PRO 5000 Blackwell                           | 2BB3 17AA 204D |
 | NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 1028 204C |
 | NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 103C 204C |
 | NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 10DE 204C |
 | NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 17AA 204C |
+| NVIDIA RTX PRO 6000 Blackwell Server Edition            | 2BB5 10DE 204E |
+| NVIDIA RTX 6000D                                        | 2BB9 10DE 2091 |
 | NVIDIA GeForce RTX 5080                                 | 2C02           |
 | NVIDIA GeForce RTX 5070 Ti                              | 2C05           |
 | NVIDIA GeForce RTX 5090 Laptop GPU                      | 2C18           |
 | NVIDIA GeForce RTX 5080 Laptop GPU                      | 2C19           |
+| NVIDIA RTX PRO 4500 Blackwell                           | 2C31 1028 2051 |
+| NVIDIA RTX PRO 4500 Blackwell                           | 2C31 103C 2051 |
+| NVIDIA RTX PRO 4500 Blackwell                           | 2C31 10DE 2051 |
+| NVIDIA RTX PRO 4500 Blackwell                           | 2C31 17AA 2051 |
+| NVIDIA RTX PRO 4000 Blackwell SFF Edition               | 2C33 1028 2053 |
+| NVIDIA RTX PRO 4000 Blackwell SFF Edition               | 2C33 103C 2053 |
+| NVIDIA RTX PRO 4000 Blackwell SFF Edition               | 2C33 10DE 2053 |
+| NVIDIA RTX PRO 4000 Blackwell SFF Edition               | 2C33 17AA 2053 |
+| NVIDIA RTX PRO 4000 Blackwell                           | 2C34 1028 2052 |
+| NVIDIA RTX PRO 4000 Blackwell                           | 2C34 103C 2052 |
+| NVIDIA RTX PRO 4000 Blackwell                           | 2C34 10DE 2052 |
+| NVIDIA RTX PRO 4000 Blackwell                           | 2C34 17AA 2052 |
+| NVIDIA RTX PRO 5000 Blackwell Generation Laptop GPU     | 2C38           |
+| NVIDIA RTX PRO 4000 Blackwell Generation Laptop GPU     | 2C39           |
 | NVIDIA GeForce RTX 5090 Laptop GPU                      | 2C58           |
 | NVIDIA GeForce RTX 5080 Laptop GPU                      | 2C59           |
+| NVIDIA GeForce RTX 5060 Ti                              | 2D04           |
+| NVIDIA GeForce RTX 5060                                 | 2D05           |
+| NVIDIA GeForce RTX 5070 Laptop GPU                      | 2D18           |
+| NVIDIA GeForce RTX 5060 Laptop GPU                      | 2D19           |
+| NVIDIA RTX PRO 2000 Blackwell                           | 2D30 1028 2054 |
+| NVIDIA RTX PRO 2000 Blackwell                           | 2D30 103C 2054 |
+| NVIDIA RTX PRO 2000 Blackwell                           | 2D30 10DE 2054 |
+| NVIDIA RTX PRO 2000 Blackwell                           | 2D30 17AA 2054 |
+| NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU     | 2D39           |
+| NVIDIA GeForce RTX 5070 Laptop GPU                      | 2D58           |
+| NVIDIA GeForce RTX 5060 Laptop GPU                      | 2D59           |
+| NVIDIA GeForce RTX 5050                                 | 2D83           |
+| NVIDIA GeForce RTX 5050 Laptop GPU                      | 2D98           |
+| NVIDIA RTX PRO 1000 Blackwell Generation Laptop GPU     | 2DB8           |
+| NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU      | 2DB9           |
+| NVIDIA GeForce RTX 5050 Laptop GPU                      | 2DD8           |
 | NVIDIA GeForce RTX 5070                                 | 2F04           |
 | NVIDIA GeForce RTX 5070 Ti Laptop GPU                   | 2F18           |
+| NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU     | 2F38           |
 | NVIDIA GeForce RTX 5070 Ti Laptop GPU                   | 2F58           |
+| NVIDIA B300 SXM6 AC                                     | 3182 10DE 20E6 |
+| NVIDIA GB300                                            | 31C2 10DE 21F1 |
--- a/kernel-open/Kbuild
+++ b/kernel-open/Kbuild
@@ -8,7 +8,7 @@
 # NV_KERNEL_SOURCES : The root of the kernel source tree.
 # NV_KERNEL_OUTPUT : The kernel's output tree.
 # NV_KERNEL_MODULES : A whitespace-separated list of modules to build.
-# ARCH : The target CPU architecture: x86_64|arm64|powerpc
+# ARCH : The target CPU architecture: x86_64|arm64
 #
 # Kbuild provides the variables:
 #
@@ -75,21 +75,24 @@ $(foreach _module, $(NV_KERNEL_MODULES), \
 $(eval include $(src)/$(_module)/$(_module).Kbuild))


-#
-# Define CFLAGS that apply to all the NVIDIA kernel modules. EXTRA_CFLAGS
-# is deprecated since 2.6.24 in favor of ccflags-y, but we need to support
-# older kernels which do not have ccflags-y. Newer kernels append
-# $(EXTRA_CFLAGS) to ccflags-y for compatibility.
-#
+ccflags-y += -I$(src)/common/inc
+ccflags-y += -I$(src)
+ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
+ccflags-y += -D__KERNEL__ -DMODULE -DNVRM
+ccflags-y += -DNV_VERSION_STRING=\"580.82.09\"

-EXTRA_CFLAGS += -I$(src)/common/inc
-EXTRA_CFLAGS += -I$(src)
-EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
-EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
-EXTRA_CFLAGS += -DNV_VERSION_STRING=\"570.133.20\"
+# Include and link Tegra out-of-tree modules.
+ifneq ($(wildcard /usr/src/nvidia/nvidia-oot),)
+ SYSSRCNVOOT ?= /usr/src/nvidia/nvidia-oot
+endif

 ifneq ($(SYSSRCHOST1X),)
- EXTRA_CFLAGS += -I$(SYSSRCHOST1X)
+ ccflags-y += -I$(SYSSRCHOST1X)
+endif
+
+ifneq ($(SYSSRCNVOOT),)
+ ccflags-y += -I$(SYSSRCNVOOT)/include
+ KBUILD_EXTRA_SYMBOLS = $(SYSSRCNVOOT)/Module.symvers
 endif

 # Some Android kernels prohibit driver use of filesystem functions like
@@ -99,57 +102,53 @@ endif
 PLATFORM_IS_ANDROID ?= 0

 ifeq ($(PLATFORM_IS_ANDROID),1)
- EXTRA_CFLAGS += -DNV_FILESYSTEM_ACCESS_AVAILABLE=0
+ ccflags-y += -DNV_FILESYSTEM_ACCESS_AVAILABLE=0
 else
- EXTRA_CFLAGS += -DNV_FILESYSTEM_ACCESS_AVAILABLE=1
+ ccflags-y += -DNV_FILESYSTEM_ACCESS_AVAILABLE=1
 endif

-EXTRA_CFLAGS += -Wno-unused-function
+ccflags-y += -Wno-unused-function

 ifneq ($(NV_BUILD_TYPE),debug)
- EXTRA_CFLAGS += -Wuninitialized
+ ccflags-y += -Wuninitialized
 endif

-EXTRA_CFLAGS += -fno-strict-aliasing
+ccflags-y += -fno-strict-aliasing

 ifeq ($(ARCH),arm64)
- EXTRA_CFLAGS += -mstrict-align
+ ccflags-y += -mstrict-align
 endif

 ifeq ($(NV_BUILD_TYPE),debug)
- EXTRA_CFLAGS += -g
+ ccflags-y += -g
 endif

-EXTRA_CFLAGS += -ffreestanding
+ccflags-y += -ffreestanding

 ifeq ($(ARCH),arm64)
- EXTRA_CFLAGS += -mgeneral-regs-only -march=armv8-a
- EXTRA_CFLAGS += $(call cc-option,-mno-outline-atomics,)
+ ccflags-y += -mgeneral-regs-only -march=armv8-a
+ ccflags-y += $(call cc-option,-mno-outline-atomics,)
 endif

 ifeq ($(ARCH),x86_64)
- EXTRA_CFLAGS += -mno-red-zone -mcmodel=kernel
+ ccflags-y += -mno-red-zone -mcmodel=kernel
 endif

-ifeq ($(ARCH),powerpc)
- EXTRA_CFLAGS += -mlittle-endian -mno-strict-align
-endif
-
-EXTRA_CFLAGS += -DNV_UVM_ENABLE
-EXTRA_CFLAGS += $(call cc-option,-Werror=undef,)
-EXTRA_CFLAGS += -DNV_SPECTRE_V2=$(NV_SPECTRE_V2)
-EXTRA_CFLAGS += -DNV_KERNEL_INTERFACE_LAYER
+ccflags-y += -DNV_UVM_ENABLE
+ccflags-y += $(call cc-option,-Werror=undef,)
+ccflags-y += -DNV_SPECTRE_V2=$(NV_SPECTRE_V2)
+ccflags-y += -DNV_KERNEL_INTERFACE_LAYER

 #
 # Detect SGI UV systems and apply system-specific optimizations.
 #

 ifneq ($(wildcard /proc/sgi_uv),)
- EXTRA_CFLAGS += -DNV_CONFIG_X86_UV
+ ccflags-y += -DNV_CONFIG_X86_UV
 endif

 ifdef VGX_FORCE_VFIO_PCI_CORE
- EXTRA_CFLAGS += -DNV_VGPU_FORCE_VFIO_PCI_CORE
+ ccflags-y += -DNV_VGPU_FORCE_VFIO_PCI_CORE
 endif

 WARNINGS_AS_ERRORS ?=
@@ -183,7 +182,8 @@ NV_CONFTEST_CMD := /bin/sh $(NV_CONFTEST_SCRIPT) \

 NV_CFLAGS_FROM_CONFTEST := $(shell $(NV_CONFTEST_CMD) build_cflags)

-NV_CONFTEST_CFLAGS = $(NV_CFLAGS_FROM_CONFTEST) $(EXTRA_CFLAGS) -fno-pie
+NV_CONFTEST_CFLAGS = $(NV_CFLAGS_FROM_CONFTEST) $(ccflags-y) -fno-pie
+NV_CONFTEST_CFLAGS += $(filter -std=%,$(KBUILD_CFLAGS))
 NV_CONFTEST_CFLAGS += $(call cc-disable-warning,pointer-sign)
 NV_CONFTEST_CFLAGS += $(call cc-option,-fshort-wchar,)
 NV_CONFTEST_CFLAGS += $(call cc-option,-Werror=incompatible-pointer-types,)
--- a/kernel-open/Makefile
+++ b/kernel-open/Makefile
@@ -71,12 +71,35 @@ else
  CC ?= cc
  LD ?= ld
  OBJDUMP ?= objdump
+  AWK ?= awk
+  # Bake the following awk program in a string. The program is needed to add C++
+  # to the languages excluded from BTF generation.
+  #
+  # Also, unconditionally return success (0) from the awk program, rather than
+  # propagating pahole's return status (with 'exit system(pahole_cmd)'), to
+  # workaround an DW_TAG_rvalue_reference_type error in
+  # kernel/nvidia-modeset.ko.
+  #
+  # BEGIN {
+  #     pahole_cmd = "pahole"
+  #     for (i = 1; i < ARGC; i++) {
+  #         if (ARGV[i] ~ /--lang_exclude=/) {
+  #             pahole_cmd = pahole_cmd sprintf(" %s,c++", ARGV[i])
+  #         } else {
+  #             pahole_cmd = pahole_cmd sprintf(" %s", ARGV[i])
+  #         }
+  #     }
+  #     system(pahole_cmd)
+  # }
+  PAHOLE_AWK_PROGRAM = BEGIN { pahole_cmd = \"pahole\"; for (i = 1; i < ARGC; i++) { if (ARGV[i] ~ /--lang_exclude=/) { pahole_cmd = pahole_cmd sprintf(\" %s,c++\", ARGV[i]); } else { pahole_cmd = pahole_cmd sprintf(\" %s\", ARGV[i]); } } system(pahole_cmd); }
+  # If scripts/pahole-flags.sh is not present in the kernel tree, add PAHOLE and
+  # PAHOLE_AWK_PROGRAM assignments to PAHOLE_VARIABLES; otherwise assign the
+  # empty string to PAHOLE_VARIABLES.
+  PAHOLE_VARIABLES=$(if $(wildcard $(KERNEL_SOURCES)/scripts/pahole-flags.sh),,"PAHOLE=$(AWK) '$(PAHOLE_AWK_PROGRAM)'")

  ifndef ARCH
    ARCH := $(shell uname -m | sed -e 's/i.86/i386/' \
-      -e 's/armv[0-7]\w\+/arm/' \
      -e 's/aarch64/arm64/' \
-      -e 's/ppc64le/powerpc/' \
      -e 's/riscv64/riscv/' \
    )
  endif
@@ -86,7 +109,7 @@ else
  ifneq ($(filter $(ARCH),i386 x86_64),)
    KERNEL_ARCH = x86
  else
-    ifeq ($(filter $(ARCH),arm64 powerpc),)
+    ifeq ($(filter $(ARCH),arm64 riscv),)
        $(error Unsupported architecture $(ARCH))
    endif
  endif
@@ -112,7 +135,8 @@ else

  .PHONY: modules module clean clean_conftest modules_install
  modules clean modules_install:
-	@$(MAKE) "LD=$(LD)" "CC=$(CC)" "OBJDUMP=$(OBJDUMP)" $(KBUILD_PARAMS) $@
+	@$(MAKE) "LD=$(LD)" "CC=$(CC)" "OBJDUMP=$(OBJDUMP)" \
+	  $(PAHOLE_VARIABLES) $(KBUILD_PARAMS) $@
 	@if [ "$@" = "modules" ]; then \
 	  for module in $(NV_KERNEL_MODULES); do \
 	    if [ -x split-object-file.sh ]; then \
--- a/kernel-open/common/inc/dce_rm_client_ipc.h
+++ b/kernel-open/common/inc/dce_rm_client_ipc.h
@@ -0,0 +1,35 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _OS_DCE_CLIENT_IPC_H_
+#define _OS_DCE_CLIENT_IPC_H_
+
+// RM IPC Client Types
+
+#define DCE_CLIENT_RM_IPC_TYPE_SYNC             0x0
+#define DCE_CLIENT_RM_IPC_TYPE_EVENT            0x1
+#define DCE_CLIENT_RM_IPC_TYPE_MAX              0x2
+
+void dceclientHandleAsyncRpcCallback(NvU32 handle, NvU32 interfaceType,
+                                     NvU32 msgLength, void *data,
+                                     void *usrCtx);
+#endif
--- a/kernel-open/common/inc/nv-firmware.h
+++ b/kernel-open/common/inc/nv-firmware.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -49,6 +49,8 @@ typedef enum
    NV_FIRMWARE_CHIP_FAMILY_GH100 = 6,
    NV_FIRMWARE_CHIP_FAMILY_GB10X = 8,
    NV_FIRMWARE_CHIP_FAMILY_GB20X = 9,
+    NV_FIRMWARE_CHIP_FAMILY_GB10Y = 11,
+    NV_FIRMWARE_CHIP_FAMILY_GB20Y = 12,
    NV_FIRMWARE_CHIP_FAMILY_END,
 } nv_firmware_chip_family_t;

@@ -58,6 +60,8 @@ static inline const char *nv_firmware_chip_family_to_string(
 {
    switch (fw_chip_family) {
        case NV_FIRMWARE_CHIP_FAMILY_GB10X: return "gb10x";
+        case NV_FIRMWARE_CHIP_FAMILY_GB10Y: return "gb10y";
+        case NV_FIRMWARE_CHIP_FAMILY_GB20Y: return "gb20y";
        case NV_FIRMWARE_CHIP_FAMILY_GB20X: return "gb20x";
        case NV_FIRMWARE_CHIP_FAMILY_GH100: return "gh100";
        case NV_FIRMWARE_CHIP_FAMILY_AD10X: return "ad10x";
@@ -68,9 +72,9 @@ static inline const char *nv_firmware_chip_family_to_string(

        case NV_FIRMWARE_CHIP_FAMILY_END:  // fall through
        case NV_FIRMWARE_CHIP_FAMILY_NULL:
-            return NULL;
+            return "";
    }
-    return NULL;
+    return "";
 }

 // The includer may optionally define
@@ -89,6 +93,8 @@ static inline const char *nv_firmware_for_chip_family(
        switch (fw_chip_family)
        {
            case NV_FIRMWARE_CHIP_FAMILY_GB10X:  // fall through
+            case NV_FIRMWARE_CHIP_FAMILY_GB10Y:  // fall through
+            case NV_FIRMWARE_CHIP_FAMILY_GB20Y:  // fall through
            case NV_FIRMWARE_CHIP_FAMILY_GB20X:  // fall through
            case NV_FIRMWARE_CHIP_FAMILY_GH100:  // fall through
            case NV_FIRMWARE_CHIP_FAMILY_AD10X:  // fall through
@@ -110,6 +116,8 @@ static inline const char *nv_firmware_for_chip_family(
        switch (fw_chip_family)
        {
            case NV_FIRMWARE_CHIP_FAMILY_GB10X:  // fall through
+            case NV_FIRMWARE_CHIP_FAMILY_GB10Y:  // fall through
+            case NV_FIRMWARE_CHIP_FAMILY_GB20Y:  // fall through
            case NV_FIRMWARE_CHIP_FAMILY_GB20X:  // fall through
            case NV_FIRMWARE_CHIP_FAMILY_GH100:  // fall through
            case NV_FIRMWARE_CHIP_FAMILY_AD10X:  // fall through
--- a/kernel-open/common/inc/nv-hash.h
+++ b/kernel-open/common/inc/nv-hash.h
@@ -29,17 +29,9 @@
 #include <linux/kernel.h>
 #include <linux/hash.h>

-#if defined(NV_LINUX_STRINGHASH_H_PRESENT)
 #include <linux/stringhash.h>       /* full_name_hash() */
-#else
-#include <linux/dcache.h>
-#endif

-#if (NV_FULL_NAME_HASH_ARGUMENT_COUNT == 3)
 #define nv_string_hash(_str) full_name_hash(NULL, _str, strlen(_str))
-#else
-#define nv_string_hash(_str) full_name_hash(_str, strlen(_str))
-#endif

 /**
 * This naive hashtable was introduced by commit d9b482c8ba19 (v3.7, 2012-10-31).
--- a/kernel-open/common/inc/nv-ioctl.h
+++ b/kernel-open/common/inc/nv-ioctl.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -140,6 +140,7 @@ typedef struct nv_ioctl_export_to_dma_buf_fd
    NvU32       index;
    NvU64       totalSize NV_ALIGN_BYTES(8);
    NvU8        mappingType;
+    NvBool      bAllowMmap;
    NvHandle    handles[NV_DMABUF_EXPORT_MAX_HANDLES];
    NvU64       offsets[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8);
    NvU64       sizes[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8);
--- a/kernel-open/common/inc/nv-linux.h
+++ b/kernel-open/common/inc/nv-linux.h
--- a/kernel-open/common/inc/nv-lock.h
+++ b/kernel-open/common/inc/nv-lock.h
@@ -28,12 +28,9 @@

 #include <linux/spinlock.h>
 #include <linux/rwsem.h>
-#include <linux/sched.h> /* signal_pending, cond_resched */
+#include <linux/sched.h> /* cond_resched */
 #include <linux/semaphore.h>
-
-#if defined(NV_LINUX_SCHED_SIGNAL_H_PRESENT)
-#include <linux/sched/signal.h>     /* signal_pending for kernels >= 4.11 */
-#endif
+#include <linux/sched/signal.h> /* signal_pending */

 #if defined(CONFIG_PREEMPT_RT) || defined(CONFIG_PREEMPT_RT_FULL)
 typedef raw_spinlock_t            nv_spinlock_t;
--- a/kernel-open/common/inc/nv-mm.h
+++ b/kernel-open/common/inc/nv-mm.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2016-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -66,54 +66,17 @@ typedef int vm_fault_t;
 /*
 * get_user_pages()
 *
- * The 8-argument version of get_user_pages() was deprecated by commit
- * cde70140fed8 ("mm/gup: Overload get_user_pages() functions") in v4.6-rc1.
- * (calling get_user_pages with current and current->mm).
- *
- * Completely moved to the 6 argument version of get_user_pages() by
- * commit c12d2da56d0e ("mm/gup: Remove the macro overload API migration
- * helpers from the get_user*() APIs") in v4.6-rc4.
- *
- * write and force parameters were replaced with gup_flags by
- * commit 768ae309a961 ("mm: replace get_user_pages() write/force parameters
- * with gup_flags") in v4.9.
- *
- * A 7-argument version of get_user_pages was introduced into linux-4.4.y by
- * commit 8e50b8b07f462 ("mm: replace get_user_pages() write/force parameters
- * with gup_flags") which cherry-picked the replacement of the write and
- * force parameters with gup_flags.
- *
 * Removed vmas parameter from get_user_pages() by commit 54d020692b34
 * ("mm/gup: remove unused vmas parameter from get_user_pages()") in v6.5.
 *
 */

-#if defined(NV_GET_USER_PAGES_HAS_ARGS_FLAGS)
+#if !defined(NV_GET_USER_PAGES_HAS_VMAS_ARG)
    #define NV_GET_USER_PAGES get_user_pages
-#elif defined(NV_GET_USER_PAGES_HAS_ARGS_FLAGS_VMAS)
+#else
    #define NV_GET_USER_PAGES(start, nr_pages, flags, pages) \
        get_user_pages(start, nr_pages, flags, pages, NULL)
-#elif defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS_VMAS)
-    #define NV_GET_USER_PAGES(start, nr_pages, flags, pages) \
-        get_user_pages(current, current->mm, start, nr_pages, flags, pages, NULL)
-#else
-    static inline long NV_GET_USER_PAGES(unsigned long start,
-                                         unsigned long nr_pages,
-                                         unsigned int flags,
-                                         struct page **pages)
-    {
-        int write = flags & FOLL_WRITE;
-        int force = flags & FOLL_FORCE;
-
-    #if defined(NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE_VMAS)
-        return get_user_pages(start, nr_pages, write, force, pages, NULL);
-    #else
-        // NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE_VMAS
-        return get_user_pages(current, current->mm, start, nr_pages, write,
-                              force, pages, NULL);
-    #endif // NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE_VMAS
-    }
-#endif // NV_GET_USER_PAGES_HAS_ARGS_FLAGS
+#endif

 /*
 * pin_user_pages_remote()
@@ -146,22 +109,12 @@ typedef int vm_fault_t;
 #endif // NV_PIN_USER_PAGES_REMOTE_PRESENT

 /*
- * get_user_pages_remote() was added by commit 1e9877902dc7
- * ("mm/gup: Introduce get_user_pages_remote()") in v4.6.
- *
 * Note that get_user_pages_remote() requires the caller to hold a reference on
- * the task_struct (if non-NULL and if this API has tsk argument) and the mm_struct.
+ * the mm_struct.
 * This will always be true when using current and current->mm. If the kernel passes
 * the driver a vma via driver callback, the kernel holds a reference on vma->vm_mm
 * over that callback.
 *
- * get_user_pages_remote() write/force parameters were replaced
- * with gup_flags by commit 9beae1ea8930 ("mm: replace get_user_pages_remote()
- * write/force parameters with gup_flags") in v4.9.
- *
- * get_user_pages_remote() added 'locked' parameter by commit 5b56d49fc31d
- * ("mm: add locked parameter to get_user_pages_remote()") in v4.10.
- *
 * get_user_pages_remote() removed 'tsk' parameter by
 * commit 64019a2e467a ("mm/gup: remove task_struct pointer for
 * all gup code") in v5.9.
@@ -171,77 +124,16 @@ typedef int vm_fault_t;
 *
 */

-#if defined(NV_GET_USER_PAGES_REMOTE_PRESENT)
-    #if defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED)
-        #define NV_GET_USER_PAGES_REMOTE get_user_pages_remote
+#if defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_VMAS)
+    #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \
+        get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, NULL, locked)
+#elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK)
+    #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \
+        get_user_pages_remote(mm, start, nr_pages, flags, pages, NULL, locked)

-    #elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED_VMAS)
-        #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \
-            get_user_pages_remote(mm, start, nr_pages, flags, pages, NULL, locked)
-
-    #elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED_VMAS)
-        #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \
-            get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, NULL, locked)
-
-    #elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_VMAS)
-        #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \
-            get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, NULL)
-
-    #else
-        // NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE_VMAS
-        static inline long NV_GET_USER_PAGES_REMOTE(struct mm_struct *mm,
-                                                    unsigned long start,
-                                                    unsigned long nr_pages,
-                                                    unsigned int flags,
-                                                    struct page **pages,
-                                                    int *locked)
-        {
-            int write = flags & FOLL_WRITE;
-            int force = flags & FOLL_FORCE;
-
-            return get_user_pages_remote(NULL, mm, start, nr_pages, write, force,
-                                         pages, NULL);
-        }
-    #endif // NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED
 #else
-    #if defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE_VMAS)
-        static inline long NV_GET_USER_PAGES_REMOTE(struct mm_struct *mm,
-                                                    unsigned long start,
-                                                    unsigned long nr_pages,
-                                                    unsigned int flags,
-                                                    struct page **pages,
-                                                    int *locked)
-        {
-            int write = flags & FOLL_WRITE;
-            int force = flags & FOLL_FORCE;
-
-            return get_user_pages(NULL, mm, start, nr_pages, write, force, pages, NULL);
-        }
-
-    #else
-        #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \
-            get_user_pages(NULL, mm, start, nr_pages, flags, pages, NULL)
-    #endif // NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE_VMAS
-#endif // NV_GET_USER_PAGES_REMOTE_PRESENT
-
-/*
- * The .virtual_address field was effectively renamed to .address, by these
- * two commits:
- *
- *  struct vm_fault: .address was added by:
- *   2016-12-14  82b0f8c39a3869b6fd2a10e180a862248736ec6f
- *
- *  struct vm_fault: .virtual_address was removed by:
- *   2016-12-14  1a29d85eb0f19b7d8271923d8917d7b4f5540b3e
- */
-static inline unsigned long nv_page_fault_va(struct vm_fault *vmf)
-{
-#if defined(NV_VM_FAULT_HAS_ADDRESS)
-    return vmf->address;
-#else
-    return (unsigned long)(vmf->virtual_address);
+    #define NV_GET_USER_PAGES_REMOTE get_user_pages_remote
 #endif
-}

 static inline void nv_mmap_read_lock(struct mm_struct *mm)
 {
@@ -297,9 +189,21 @@ static inline struct rw_semaphore *nv_mmap_get_lock(struct mm_struct *mm)
 #endif
 }

+#define NV_CAN_CALL_VMA_START_WRITE 1
+
+#if !NV_CAN_CALL_VMA_START_WRITE
+/*
+ * Commit 45ad9f5290dc updated vma_start_write() to call __vma_start_write().
+ */
+void nv_vma_start_write(struct vm_area_struct *);
+#endif
+
 static inline void nv_vm_flags_set(struct vm_area_struct *vma, vm_flags_t flags)
 {
-#if defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
+#if !NV_CAN_CALL_VMA_START_WRITE
+    nv_vma_start_write(vma);
+    ACCESS_PRIVATE(vma, __vm_flags) |= flags;
+#elif defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
    vm_flags_set(vma, flags);
 #else
    vma->vm_flags |= flags;
@@ -308,7 +212,10 @@ static inline void nv_vm_flags_set(struct vm_area_struct *vma, vm_flags_t flags)

 static inline void nv_vm_flags_clear(struct vm_area_struct *vma, vm_flags_t flags)
 {
-#if defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
+#if !NV_CAN_CALL_VMA_START_WRITE
+    nv_vma_start_write(vma);
+    ACCESS_PRIVATE(vma, __vm_flags) &= ~flags;
+#elif defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
    vm_flags_clear(vma, flags);
 #else
    vma->vm_flags &= ~flags;
--- a/kernel-open/common/inc/nv-msi.h
+++ b/kernel-open/common/inc/nv-msi.h
@@ -26,8 +26,7 @@

 #include "nv-linux.h"

-#if (defined(CONFIG_X86_LOCAL_APIC) || defined(NVCPU_AARCH64) || \
-     defined(NVCPU_PPC64LE)) && \
+#if (defined(CONFIG_X86_LOCAL_APIC) || defined(NVCPU_AARCH64)) && \
    (defined(CONFIG_PCI_MSI) || defined(CONFIG_PCI_USE_VECTOR))
 #define NV_LINUX_PCIE_MSI_SUPPORTED
 #endif
@@ -87,12 +86,6 @@ static inline int nv_pci_enable_msix(nv_linux_state_t *nvl, int nvec)
 {
    int rc = 0;

-    /*
-     * pci_enable_msix_range() replaced pci_enable_msix() in 3.14-rc1:
-     * 2014-01-03  302a2523c277bea0bbe8340312b09507905849ed
-     */
-
-#if defined(NV_PCI_ENABLE_MSIX_RANGE_PRESENT)
    // We require all the vectors we are requesting so use the same min and max
    rc = pci_enable_msix_range(nvl->pci_dev, nvl->msix_entries, nvec, nvec);
    if (rc < 0)
@@ -100,13 +93,6 @@ static inline int nv_pci_enable_msix(nv_linux_state_t *nvl, int nvec)
        return NV_ERR_OPERATING_SYSTEM;
    }
    WARN_ON(nvec != rc);
-#else
-    rc = pci_enable_msix(nvl->pci_dev, nvl->msix_entries, nvec);
-    if (rc != 0)
-    {
-        return NV_ERR_OPERATING_SYSTEM;
-    }
-#endif

    nvl->num_intr = nvec;
    return NV_OK;
--- a/kernel-open/common/inc/nv-pci.h
+++ b/kernel-open/common/inc/nv-pci.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -36,6 +36,6 @@ int nv_pci_count_devices(void);
 NvU8 nv_find_pci_capability(struct pci_dev *, NvU8);
 int nvidia_dev_get_pci_info(const NvU8 *, struct pci_dev **, NvU64 *, NvU64 *);
 nv_linux_state_t * find_pci(NvU32, NvU8, NvU8, NvU8);
-NvBool nv_pci_is_valid_topology_for_direct_pci(nv_state_t *, struct device *);
-
+NvBool nv_pci_is_valid_topology_for_direct_pci(nv_state_t *, struct pci_dev *);
+NvBool nv_pci_has_common_pci_switch(nv_state_t *nv, struct pci_dev *);
 #endif
--- a/kernel-open/common/inc/nv-pgprot.h
+++ b/kernel-open/common/inc/nv-pgprot.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -63,16 +63,10 @@ static inline pgprot_t pgprot_modify_writecombine(pgprot_t old_prot)
 extern NvBool nvos_is_chipset_io_coherent(void);
 /*
 * Don't rely on the kernel's definition of pgprot_noncached(), as on 64-bit
- * ARM that's not for system memory, but device memory instead. For I/O cache
- * coherent systems, use cached mappings instead of uncached.
+ * ARM that's not for system memory, but device memory instead.
 */
 #define NV_PGPROT_UNCACHED(old_prot)   \
-    ((nvos_is_chipset_io_coherent()) ? \
-     (old_prot) :                      \
-     __pgprot_modify((old_prot), PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC)))
-#elif defined(NVCPU_PPC64LE)
-/* Don't attempt to mark sysmem pages as uncached on ppc64le */
-#define NV_PGPROT_UNCACHED(old_prot)          old_prot
+     __pgprot_modify((old_prot), PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
 #else
 #define NV_PGPROT_UNCACHED(old_prot)          pgprot_noncached(old_prot)
 #endif
@@ -94,32 +88,6 @@ extern NvBool nvos_is_chipset_io_coherent(void);
    NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot)
 #define NV_PGPROT_READ_ONLY(old_prot)                                         \
    __pgprot(pgprot_val((old_prot)) & ~_PAGE_RW)
-#elif defined(NVCPU_PPC64LE)
-/*
- * Some kernels use H_PAGE instead of _PAGE
- */
-#if defined(_PAGE_RW)
-#define NV_PAGE_RW _PAGE_RW
-#elif defined(H_PAGE_RW)
-#define NV_PAGE_RW H_PAGE_RW
-#else
-#warning "The kernel does not provide page protection defines!"
-#endif
-
-#if defined(_PAGE_4K_PFN)
-#define NV_PAGE_4K_PFN _PAGE_4K_PFN
-#elif defined(H_PAGE_4K_PFN)
-#define NV_PAGE_4K_PFN H_PAGE_4K_PFN
-#else
-#undef NV_PAGE_4K_PFN
-#endif
-
-#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot)                             \
-    pgprot_writecombine(old_prot)
-/* Don't attempt to mark sysmem pages as write combined on ppc64le */
-#define NV_PGPROT_WRITE_COMBINED(old_prot)    old_prot
-#define NV_PGPROT_READ_ONLY(old_prot)                                         \
-    __pgprot(pgprot_val((old_prot)) & ~NV_PAGE_RW)
 #elif defined(NVCPU_RISCV64)
 #define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot)                             \
    pgprot_writecombine(old_prot)
--- a/kernel-open/common/inc/nv-platform.h
+++ b/kernel-open/common/inc/nv-platform.h
@@ -0,0 +1,48 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NV_PLATFORM_H
+#define NV_PLATFORM_H
+
+#include "nv-linux.h"
+
+irqreturn_t     nvidia_isr              (int, void *);
+irqreturn_t     nvidia_isr_kthread_bh   (int, void *);
+
+int       nv_platform_register_driver(void);
+void      nv_platform_unregister_driver(void);
+int       nv_platform_count_devices(void);
+int       nv_soc_register_irqs(nv_state_t *nv);
+void      nv_soc_free_irqs(nv_state_t *nv);
+
+#define NV_SUPPORTS_PLATFORM_DEVICE NV_IS_EXPORT_SYMBOL_PRESENT___platform_driver_register
+
+#if defined(NV_LINUX_PLATFORM_TEGRA_DCE_DCE_CLIENT_IPC_H_PRESENT)
+#define NV_SUPPORTS_DCE_CLIENT_IPC 1
+#else
+#define NV_SUPPORTS_DCE_CLIENT_IPC 0
+#endif
+
+#define NV_SUPPORTS_PLATFORM_DISPLAY_DEVICE (NV_SUPPORTS_PLATFORM_DEVICE && NV_SUPPORTS_DCE_CLIENT_IPC)
+
+#endif
--- a/kernel-open/common/inc/nv-proto.h
+++ b/kernel-open/common/inc/nv-proto.h
@@ -25,6 +25,7 @@
 #define _NV_PROTO_H_

 #include "nv-pci.h"
+#include "nv-platform.h"

 extern const char *nv_device_name;

@@ -41,7 +42,7 @@ void        nv_procfs_remove_gpu        (nv_linux_state_t *);

 int         nvidia_mmap                 (struct file *, struct vm_area_struct *);
 int         nvidia_mmap_helper          (nv_state_t *, nv_linux_file_private_t *, nvidia_stack_t *, struct vm_area_struct *, void *);
-int         nv_encode_caching           (pgprot_t *, NvU32, NvU32);
+int         nv_encode_caching           (pgprot_t *, NvU32, nv_memory_type_t);
 void        nv_revoke_gpu_mappings_locked(nv_state_t *);

 NvUPtr      nv_vm_map_pages             (struct page **, NvU32, NvBool, NvBool);
--- a/kernel-open/common/inc/nv-time.h
+++ b/kernel-open/common/inc/nv-time.h
@@ -36,13 +36,6 @@
 #define NV_MAX_ISR_DELAY_MS           (NV_MAX_ISR_DELAY_US / 1000)
 #define NV_NSECS_TO_JIFFIES(nsec)     ((nsec) * HZ / 1000000000)

-#if !defined(NV_TIMESPEC64_PRESENT)
-struct timespec64 {
-    __s64 tv_sec;
-    long  tv_nsec;
-};
-#endif
-
 #if !defined(NV_KTIME_GET_RAW_TS64_PRESENT)
 static inline void ktime_get_raw_ts64(struct timespec64 *ts64)
 {
@@ -53,16 +46,6 @@ static inline void ktime_get_raw_ts64(struct timespec64 *ts64)
 }
 #endif

-#if !defined(NV_KTIME_GET_REAL_TS64_PRESENT)
-static inline void ktime_get_real_ts64(struct timespec64 *ts64)
-{
-    struct timeval tv;
-    do_gettimeofday(&tv);
-    ts64->tv_sec = tv.tv_sec;
-    ts64->tv_nsec = tv.tv_usec * (NvU64) NSEC_PER_USEC;
-}
-#endif
-
 static NvBool nv_timer_less_than
 (
    const struct timespec64 *a,
@@ -73,49 +56,6 @@ static NvBool nv_timer_less_than
                                    : (a->tv_sec < b->tv_sec);
 }

-#if !defined(NV_TIMESPEC64_PRESENT)
-static inline struct timespec64 timespec64_add
-(
-    const struct timespec64    a,
-    const struct timespec64    b
-)
-{
-    struct timespec64 result;
-
-    result.tv_sec = a.tv_sec + b.tv_sec;
-    result.tv_nsec = a.tv_nsec + b.tv_nsec;
-    while (result.tv_nsec >= NSEC_PER_SEC)
-    {
-        ++result.tv_sec;
-        result.tv_nsec -= NSEC_PER_SEC;
-    }
-    return result;
-}
-
-static inline struct timespec64  timespec64_sub
-(
-    const struct timespec64    a,
-    const struct timespec64    b
-)
-{
-    struct timespec64 result;
-
-    result.tv_sec = a.tv_sec - b.tv_sec;
-    result.tv_nsec = a.tv_nsec - b.tv_nsec;
-    while (result.tv_nsec < 0)
-    {
-        --(result.tv_sec);
-        result.tv_nsec += NSEC_PER_SEC;
-    }
-    return result;
-}
-
-static inline s64 timespec64_to_ns(struct timespec64 *ts)
-{
-    return ((s64) ts->tv_sec *  NSEC_PER_SEC) + ts->tv_nsec;
-}
-#endif
-
 static inline NvU64 nv_ktime_get_raw_ns(void)
 {
    struct timespec64 ts;
--- a/kernel-open/common/inc/nv-timer.h
+++ b/kernel-open/common/inc/nv-timer.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2017-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -42,24 +42,20 @@ static inline void nv_timer_callback_typed_data(struct timer_list *timer)
    nv_timer->nv_timer_callback(nv_timer);
 }

-static inline void nv_timer_callback_anon_data(unsigned long arg)
-{
-    struct nv_timer *nv_timer = (struct nv_timer *)arg;
-
-    nv_timer->nv_timer_callback(nv_timer);
-}
-
 static inline void nv_timer_setup(struct nv_timer *nv_timer,
                                  void (*callback)(struct nv_timer *nv_timer))
 {
    nv_timer->nv_timer_callback = callback;

-#if defined(NV_TIMER_SETUP_PRESENT)
    timer_setup(&nv_timer->kernel_timer, nv_timer_callback_typed_data, 0);
+}
+
+static inline void nv_timer_delete_sync(struct timer_list *timer)
+{
+#if !defined(NV_BSD) && NV_IS_EXPORT_SYMBOL_PRESENT_timer_delete_sync
+    timer_delete_sync(timer);
 #else
-    init_timer(&nv_timer->kernel_timer);
-    nv_timer->kernel_timer.function = nv_timer_callback_anon_data;
-    nv_timer->kernel_timer.data = (unsigned long)nv_timer;
+    del_timer_sync(timer);
 #endif
 }

--- a/kernel-open/common/inc/nv.h
+++ b/kernel-open/common/inc/nv.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -50,6 +50,9 @@ extern nv_cap_t *nvidia_caps_root;

 extern const NvBool nv_is_rm_firmware_supported_os;

+#include <nvi2c.h>
+#include <nvimpshared.h>
+
 #include <nv-kernel-interface-api.h>

 #define GPU_UUID_LEN    (16)
@@ -83,6 +86,18 @@ extern const NvBool nv_is_rm_firmware_supported_os;

 #define NV_RM_DEVICE_INTR_ADDRESS 0x100

+/*
+ * Clock domain identifier, which is used for fetching the engine
+ * load backed by the specified clock domain for Tegra platforms
+ * conforming linux devfreq framework to realize dynamic frequency
+ * scaling.
+ */
+typedef enum _TEGRASOC_DEVFREQ_CLK
+{
+    TEGRASOC_DEVFREQ_CLK_GPC,
+    TEGRASOC_DEVFREQ_CLK_NVD,
+} TEGRASOC_DEVFREQ_CLK;
+
 /*!
 * @brief The order of the display clocks in the below defined enum
 * should be synced with below mapping array and macro.
@@ -105,6 +120,12 @@ typedef enum _TEGRASOC_WHICH_CLK
    TEGRASOC_WHICH_CLK_NVDISPLAY_DISP,
    TEGRASOC_WHICH_CLK_NVDISPLAY_P0,
    TEGRASOC_WHICH_CLK_NVDISPLAY_P1,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P2,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P3,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P4,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P5,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P6,
+    TEGRASOC_WHICH_CLK_NVDISPLAY_P7,
    TEGRASOC_WHICH_CLK_DPAUX0,
    TEGRASOC_WHICH_CLK_FUSE,
    TEGRASOC_WHICH_CLK_DSIPLL_VCO,
@@ -123,9 +144,21 @@ typedef enum _TEGRASOC_WHICH_CLK
    TEGRASOC_WHICH_CLK_VPLL0_REF,
    TEGRASOC_WHICH_CLK_VPLL0,
    TEGRASOC_WHICH_CLK_VPLL1,
+    TEGRASOC_WHICH_CLK_VPLL2,
+    TEGRASOC_WHICH_CLK_VPLL3,
+    TEGRASOC_WHICH_CLK_VPLL4,
+    TEGRASOC_WHICH_CLK_VPLL5,
+    TEGRASOC_WHICH_CLK_VPLL6,
+    TEGRASOC_WHICH_CLK_VPLL7,
    TEGRASOC_WHICH_CLK_NVDISPLAY_P0_REF,
    TEGRASOC_WHICH_CLK_RG0,
    TEGRASOC_WHICH_CLK_RG1,
+    TEGRASOC_WHICH_CLK_RG2,
+    TEGRASOC_WHICH_CLK_RG3,
+    TEGRASOC_WHICH_CLK_RG4,
+    TEGRASOC_WHICH_CLK_RG5,
+    TEGRASOC_WHICH_CLK_RG6,
+    TEGRASOC_WHICH_CLK_RG7,
    TEGRASOC_WHICH_CLK_DISPPLL,
    TEGRASOC_WHICH_CLK_DISPHUBPLL,
    TEGRASOC_WHICH_CLK_DSI_LP,
@@ -133,9 +166,20 @@ typedef enum _TEGRASOC_WHICH_CLK
    TEGRASOC_WHICH_CLK_DSI_PIXEL,
    TEGRASOC_WHICH_CLK_PRE_SOR0,
    TEGRASOC_WHICH_CLK_PRE_SOR1,
+    TEGRASOC_WHICH_CLK_PRE_SOR2,
+    TEGRASOC_WHICH_CLK_PRE_SOR3,
    TEGRASOC_WHICH_CLK_DP_LINKA_REF,
+    TEGRASOC_WHICH_CLK_DP_LINKB_REF,
+    TEGRASOC_WHICH_CLK_DP_LINKC_REF,
+    TEGRASOC_WHICH_CLK_DP_LINKD_REF,
    TEGRASOC_WHICH_CLK_SOR_LINKA_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_LINKB_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_LINKC_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_LINKD_INPUT,
    TEGRASOC_WHICH_CLK_SOR_LINKA_AFIFO,
+    TEGRASOC_WHICH_CLK_SOR_LINKB_AFIFO,
+    TEGRASOC_WHICH_CLK_SOR_LINKC_AFIFO,
+    TEGRASOC_WHICH_CLK_SOR_LINKD_AFIFO,
    TEGRASOC_WHICH_CLK_SOR_LINKA_AFIFO_M,
    TEGRASOC_WHICH_CLK_RG0_M,
    TEGRASOC_WHICH_CLK_RG1_M,
@@ -144,17 +188,36 @@ typedef enum _TEGRASOC_WHICH_CLK
    TEGRASOC_WHICH_CLK_PLLHUB,
    TEGRASOC_WHICH_CLK_SOR0,
    TEGRASOC_WHICH_CLK_SOR1,
+    TEGRASOC_WHICH_CLK_SOR2,
+    TEGRASOC_WHICH_CLK_SOR3,
    TEGRASOC_WHICH_CLK_SOR_PADA_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_PADB_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_PADC_INPUT,
+    TEGRASOC_WHICH_CLK_SOR_PADD_INPUT,
+    TEGRASOC_WHICH_CLK_SOR0_PAD,
+    TEGRASOC_WHICH_CLK_SOR1_PAD,
+    TEGRASOC_WHICH_CLK_SOR2_PAD,
+    TEGRASOC_WHICH_CLK_SOR3_PAD,
    TEGRASOC_WHICH_CLK_PRE_SF0,
    TEGRASOC_WHICH_CLK_SF0,
    TEGRASOC_WHICH_CLK_SF1,
+    TEGRASOC_WHICH_CLK_SF2,
+    TEGRASOC_WHICH_CLK_SF3,
+    TEGRASOC_WHICH_CLK_SF4,
+    TEGRASOC_WHICH_CLK_SF5,
+    TEGRASOC_WHICH_CLK_SF6,
+    TEGRASOC_WHICH_CLK_SF7,
    TEGRASOC_WHICH_CLK_DSI_PAD_INPUT,
    TEGRASOC_WHICH_CLK_PRE_SOR0_REF,
    TEGRASOC_WHICH_CLK_PRE_SOR1_REF,
    TEGRASOC_WHICH_CLK_SOR0_PLL_REF,
    TEGRASOC_WHICH_CLK_SOR1_PLL_REF,
+    TEGRASOC_WHICH_CLK_SOR2_PLL_REF,
+    TEGRASOC_WHICH_CLK_SOR3_PLL_REF,
    TEGRASOC_WHICH_CLK_SOR0_REF,
    TEGRASOC_WHICH_CLK_SOR1_REF,
+    TEGRASOC_WHICH_CLK_SOR2_REF,
+    TEGRASOC_WHICH_CLK_SOR3_REF,
    TEGRASOC_WHICH_CLK_OSC,
    TEGRASOC_WHICH_CLK_DSC,
    TEGRASOC_WHICH_CLK_MAUD,
@@ -168,6 +231,27 @@ typedef enum _TEGRASOC_WHICH_CLK
    TEGRASOC_WHICH_CLK_PLLA_DISP,
    TEGRASOC_WHICH_CLK_PLLA_DISPHUB,
    TEGRASOC_WHICH_CLK_PLLA,
+    TEGRASOC_WHICH_CLK_VPLLX_SOR0_MUXED,
+    TEGRASOC_WHICH_CLK_VPLLX_SOR1_MUXED,
+    TEGRASOC_WHICH_CLK_VPLLX_SOR2_MUXED,
+    TEGRASOC_WHICH_CLK_VPLLX_SOR3_MUXED,
+    TEGRASOC_WHICH_CLK_SF0_SOR,
+    TEGRASOC_WHICH_CLK_SF1_SOR,
+    TEGRASOC_WHICH_CLK_SF2_SOR,
+    TEGRASOC_WHICH_CLK_SF3_SOR,
+    TEGRASOC_WHICH_CLK_SF4_SOR,
+    TEGRASOC_WHICH_CLK_SF5_SOR,
+    TEGRASOC_WHICH_CLK_SF6_SOR,
+    TEGRASOC_WHICH_CLK_SF7_SOR,
+    TEGRASOC_WHICH_CLK_EMC,
+    TEGRASOC_WHICH_CLK_GPU_FIRST,
+    TEGRASOC_WHICH_CLK_GPU_SYS = TEGRASOC_WHICH_CLK_GPU_FIRST,
+    TEGRASOC_WHICH_CLK_GPU_NVD,
+    TEGRASOC_WHICH_CLK_GPU_UPROC,
+    TEGRASOC_WHICH_CLK_GPU_GPC0,
+    TEGRASOC_WHICH_CLK_GPU_GPC1,
+    TEGRASOC_WHICH_CLK_GPU_GPC2,
+    TEGRASOC_WHICH_CLK_GPU_LAST = TEGRASOC_WHICH_CLK_GPU_GPC2,
    TEGRASOC_WHICH_CLK_MAX, // TEGRASOC_WHICH_CLK_MAX is defined for boundary checks only.
 } TEGRASOC_WHICH_CLK;

@@ -283,7 +367,6 @@ typedef struct nv_usermap_access_params_s
    MemoryArea memArea;
    NvU64    access_start;
    NvU64    access_size;
-    NvU64    remap_prot_extra;
    NvBool   contig;
    NvU32    caching;
 } nv_usermap_access_params_t;
@@ -299,7 +382,6 @@ typedef struct nv_alloc_mapping_context_s {
    MemoryArea memArea;
    NvU64  access_start;
    NvU64  access_size;
-    NvU64  remap_prot_extra;
    NvU32  prot;
    NvBool valid;
    NvU32  caching;
@@ -332,12 +414,8 @@ typedef struct nv_soc_irq_info_s {
 #define NV_MAX_SOC_IRQS              10
 #define NV_MAX_DPAUX_NUM_DEVICES     4

-#define NV_MAX_SOC_DPAUX_NUM_DEVICES 2
+#define NV_MAX_SOC_DPAUX_NUM_DEVICES 4

-
-#define NV_IGPU_LEGACY_STALL_IRQ     70
-#define NV_IGPU_MAX_STALL_IRQS       3
-#define NV_IGPU_MAX_NONSTALL_IRQS    1
 /*
 * per device state
 */
@@ -383,7 +461,6 @@ typedef struct nv_state_t
    nv_aperture_t *mipical_regs;
    nv_aperture_t *fb, ud;
    nv_aperture_t *simregs;
-    nv_aperture_t *emc_regs;

    NvU32  num_dpaux_instance;
    NvU32  interrupt_line;
@@ -397,12 +474,14 @@ typedef struct nv_state_t
    NvU32 soc_dcb_size;
    NvU32 disp_sw_soc_chip_id;
    NvBool soc_is_dpalt_mode_supported;
+    NvBool soc_is_hfrp_supported;

-    NvU32 igpu_stall_irq[NV_IGPU_MAX_STALL_IRQS];
-    NvU32 igpu_nonstall_irq;
-    NvU32 num_stall_irqs;
    NvU64 dma_mask;
-    
+
+    NvBool is_tegra_pci_igpu;
+    NvBool supports_tegra_igpu_rg;
+    NvBool is_tegra_pci_igpu_rg_enabled;
+
    NvBool primary_vga;

    NvU32 sim_env;
@@ -481,6 +560,13 @@ typedef struct nv_state_t
    /* Bool to check if the GPU has a coherent sysmem link */
    NvBool coherent;

+    /*
+     * Bool to check if GPU memory is backed by struct page.
+     * False for non-coherent platforms. May also be false
+     * on coherent platforms if GPU memory is not onlined to the kernel.
+     */
+    NvBool mem_has_struct_page;
+
    /* OS detected GPU has ATS capability */
    NvBool ats_support;
    /*
@@ -501,6 +587,9 @@ typedef struct nv_state_t

    /* Console is managed by drm drivers or NVKMS */
    NvBool client_managed_console;
+
+    /* Bool to check if power management is supported */
+    NvBool is_pm_supported;
 } nv_state_t;

 #define NVFP_TYPE_NONE       0x0
@@ -567,24 +656,24 @@ typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemor
 * flags
 */

-#define NV_FLAG_OPEN                   0x0001
-#define NV_FLAG_EXCLUDE                0x0002
-#define NV_FLAG_CONTROL                0x0004
-// Unused                              0x0008
-#define NV_FLAG_SOC_DISPLAY            0x0010
-#define NV_FLAG_USES_MSI               0x0020
-#define NV_FLAG_USES_MSIX              0x0040
-#define NV_FLAG_PASSTHRU               0x0080
-#define NV_FLAG_SUSPENDED              0x0100
-#define NV_FLAG_SOC_IGPU               0x0200
+#define NV_FLAG_OPEN                            0x0001
+#define NV_FLAG_EXCLUDE                         0x0002
+#define NV_FLAG_CONTROL                         0x0004
+#define NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET     0x0008
+#define NV_FLAG_SOC_DISPLAY                     0x0010
+#define NV_FLAG_USES_MSI                        0x0020
+#define NV_FLAG_USES_MSIX                       0x0040
+#define NV_FLAG_PASSTHRU                        0x0080
+#define NV_FLAG_SUSPENDED                       0x0100
+#define NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT  0x0200
 /* To be set when an FLR needs to be triggered after device shut down. */
-#define NV_FLAG_TRIGGER_FLR            0x0400
-#define NV_FLAG_PERSISTENT_SW_STATE    0x0800
-#define NV_FLAG_IN_RECOVERY            0x1000
-// Unused                              0x2000
-#define NV_FLAG_UNBIND_LOCK            0x4000
+#define NV_FLAG_TRIGGER_FLR                     0x0400
+#define NV_FLAG_PERSISTENT_SW_STATE             0x0800
+#define NV_FLAG_IN_RECOVERY                     0x1000
+#define NV_FLAG_PCI_REMOVE_IN_PROGRESS          0x2000
+#define NV_FLAG_UNBIND_LOCK                     0x4000
 /* To be set when GPU is not present on the bus, to help device teardown */
-#define NV_FLAG_IN_SURPRISE_REMOVAL    0x8000
+#define NV_FLAG_IN_SURPRISE_REMOVAL             0x8000

 typedef enum
 {
@@ -624,18 +713,26 @@ typedef struct
    const char *db_support;
 } nv_power_info_t;

+typedef enum
+{
+    NV_MEMORY_TYPE_SYSTEM,      /* Memory mapped for ROM, SBIOS and physical RAM. */
+    NV_MEMORY_TYPE_REGISTERS,
+    NV_MEMORY_TYPE_FRAMEBUFFER,
+    NV_MEMORY_TYPE_DEVICE_MMIO, /* All kinds of MMIO referred by NVRM e.g. BARs and MCFG of device */
+} nv_memory_type_t;
+
 #define NV_PRIMARY_VGA(nv)      ((nv)->primary_vga)

 #define NV_IS_CTL_DEVICE(nv)    ((nv)->flags & NV_FLAG_CONTROL)
 #define NV_IS_SOC_DISPLAY_DEVICE(nv)    \
        ((nv)->flags & NV_FLAG_SOC_DISPLAY)

-#define NV_IS_SOC_IGPU_DEVICE(nv)    \
-        ((nv)->flags & NV_FLAG_SOC_IGPU)
-
 #define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv)    \
        (((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0)

+#define NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv)    \
+        (((nv)->flags & NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT) != 0)
+
 /*
 * For console setup by EFI GOP, the base address is BAR1.
 * For console setup by VBIOS, the base address is BAR2 + 16MB.
@@ -782,9 +879,9 @@ static inline NvBool IS_IMEM_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length)

 NvU32      NV_API_CALL  nv_get_dev_minor         (nv_state_t *);
 void*      NV_API_CALL  nv_alloc_kernel_mapping  (nv_state_t *, void *, NvU64, NvU32, NvU64, void **);
-NV_STATUS  NV_API_CALL  nv_free_kernel_mapping   (nv_state_t *, void *, void *, void *);
+void       NV_API_CALL  nv_free_kernel_mapping   (nv_state_t *, void *, void *, void *);
 NV_STATUS  NV_API_CALL  nv_alloc_user_mapping    (nv_state_t *, void *, NvU64, NvU32, NvU64, NvU32, NvU64 *, void **);
-NV_STATUS  NV_API_CALL  nv_free_user_mapping     (nv_state_t *, void *, NvU64, void *);
+void       NV_API_CALL  nv_free_user_mapping     (nv_state_t *, void *, NvU64, void *);
 NV_STATUS  NV_API_CALL  nv_add_mapping_context_to_file (nv_state_t *, nv_usermap_access_params_t*, NvU32, void *, NvU64, NvU32);

 NvU64  NV_API_CALL  nv_get_kern_phys_address     (NvU64);
@@ -798,7 +895,7 @@ NV_STATUS  NV_API_CALL  nv_alias_pages           (nv_state_t *, NvU32, NvU64, Nv
 NV_STATUS  NV_API_CALL  nv_alloc_pages           (nv_state_t *, NvU32, NvU64, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **);
 NV_STATUS  NV_API_CALL  nv_free_pages            (nv_state_t *, NvU32, NvBool, NvU32, void *);

-NV_STATUS  NV_API_CALL  nv_register_user_pages   (nv_state_t *, NvU64, NvU64 *, void *, void **);
+NV_STATUS  NV_API_CALL  nv_register_user_pages   (nv_state_t *, NvU64, NvU64 *, void *, void **, NvBool);
 void       NV_API_CALL  nv_unregister_user_pages (nv_state_t *, NvU64, void **, void **);

 NV_STATUS NV_API_CALL   nv_register_peer_io_mem  (nv_state_t *, NvU64 *, NvU64, void **);
@@ -806,7 +903,8 @@ void      NV_API_CALL   nv_unregister_peer_io_mem(nv_state_t *, void *);

 struct sg_table;

-NV_STATUS NV_API_CALL   nv_register_sgt          (nv_state_t *, NvU64 *, NvU64, NvU32, void **, struct sg_table *, void *);
+NV_STATUS NV_API_CALL   nv_register_sgt          (nv_state_t *, NvU64 *, NvU64, NvU32, void **,
+                                                  struct sg_table *, void *, NvBool);
 void      NV_API_CALL   nv_unregister_sgt        (nv_state_t *, struct sg_table **, void **, void *);
 NV_STATUS NV_API_CALL   nv_register_phys_pages   (nv_state_t *, NvU64 *, NvU64, NvU32, void **);
 void      NV_API_CALL   nv_unregister_phys_pages (nv_state_t *, void *);
@@ -817,12 +915,14 @@ NV_STATUS  NV_API_CALL  nv_dma_map_alloc         (nv_dma_device_t *, NvU64, NvU6
 NV_STATUS  NV_API_CALL  nv_dma_unmap_alloc       (nv_dma_device_t *, NvU64, NvU64 *, void **);

 NV_STATUS  NV_API_CALL  nv_dma_map_peer          (nv_dma_device_t *, nv_dma_device_t *, NvU8, NvU64, NvU64 *);
+NV_STATUS  NV_API_CALL  nv_dma_map_non_pci_peer  (nv_dma_device_t *, NvU64, NvU64 *);
 void       NV_API_CALL  nv_dma_unmap_peer        (nv_dma_device_t *, NvU64, NvU64);

 NV_STATUS  NV_API_CALL  nv_dma_map_mmio          (nv_dma_device_t *, NvU64, NvU64 *);
 void       NV_API_CALL  nv_dma_unmap_mmio        (nv_dma_device_t *, NvU64, NvU64);

 void       NV_API_CALL  nv_dma_cache_invalidate  (nv_dma_device_t *, void *);
+NvBool     NV_API_CALL  nv_grdma_pci_topology_supported(nv_state_t *, nv_dma_device_t *);

 NvS32  NV_API_CALL  nv_start_rc_timer            (nv_state_t *);
 NvS32  NV_API_CALL  nv_stop_rc_timer             (nv_state_t *);
@@ -895,8 +995,8 @@ struct drm_gem_object;

 NV_STATUS NV_API_CALL nv_dma_import_sgt  (nv_dma_device_t *, struct sg_table *, struct drm_gem_object *);
 void NV_API_CALL nv_dma_release_sgt(struct sg_table *, struct drm_gem_object *);
-NV_STATUS NV_API_CALL nv_dma_import_dma_buf      (nv_dma_device_t *, struct dma_buf *, NvU32 *, struct sg_table **, nv_dma_buf_t **);
-NV_STATUS NV_API_CALL nv_dma_import_from_fd      (nv_dma_device_t *, NvS32, NvU32 *, struct sg_table **, nv_dma_buf_t **);
+NV_STATUS NV_API_CALL nv_dma_import_dma_buf      (nv_dma_device_t *, struct dma_buf *, NvBool, NvU32 *, struct sg_table **, nv_dma_buf_t **);
+NV_STATUS NV_API_CALL nv_dma_import_from_fd      (nv_dma_device_t *, NvS32, NvBool, NvU32 *, struct sg_table **, nv_dma_buf_t **);
 void      NV_API_CALL nv_dma_release_dma_buf     (nv_dma_buf_t *);

 void      NV_API_CALL nv_schedule_uvm_isr        (nv_state_t *);
@@ -907,6 +1007,10 @@ void      NV_API_CALL nv_schedule_uvm_resume_p2p (NvU8 *);
 NvBool    NV_API_CALL nv_platform_supports_s0ix  (void);
 NvBool    NV_API_CALL nv_s2idle_pm_configured    (void);

+NvBool    NV_API_CALL nv_pci_tegra_register_power_domain    (nv_state_t *, NvBool);
+NvBool    NV_API_CALL nv_pci_tegra_pm_init        (nv_state_t *);
+void      NV_API_CALL nv_pci_tegra_pm_deinit      (nv_state_t *);
+
 NvBool    NV_API_CALL nv_is_chassis_notebook      (void);
 void      NV_API_CALL nv_allow_runtime_suspend    (nv_state_t *nv);
 void      NV_API_CALL nv_disallow_runtime_suspend (nv_state_t *nv);
@@ -915,9 +1019,67 @@ typedef void (*nvTegraDceClientIpcCallback)(NvU32, NvU32, NvU32, void *, void *)

 NV_STATUS NV_API_CALL nv_get_num_phys_pages      (void *, NvU32 *);
 NV_STATUS NV_API_CALL nv_get_phys_pages          (void *, void *, NvU32 *);
-
 void      NV_API_CALL nv_get_disp_smmu_stream_ids (nv_state_t *, NvU32 *, NvU32 *);

+typedef struct TEGRA_IMP_IMPORT_DATA TEGRA_IMP_IMPORT_DATA;
+typedef struct nv_i2c_msg_s nv_i2c_msg_t;
+
+NV_STATUS NV_API_CALL nv_bpmp_send_mrq           (nv_state_t *, NvU32, const void *, NvU32, void *, NvU32, NvS32 *, NvS32 *);
+NV_STATUS NV_API_CALL nv_i2c_transfer(nv_state_t *, NvU32, NvU8, nv_i2c_msg_t *, int);
+void      NV_API_CALL nv_i2c_unregister_clients(nv_state_t *);
+NV_STATUS NV_API_CALL nv_i2c_bus_status(nv_state_t *, NvU32, NvS32 *, NvS32 *);
+NV_STATUS NV_API_CALL nv_imp_get_import_data     (TEGRA_IMP_IMPORT_DATA *);
+NV_STATUS NV_API_CALL nv_imp_enable_disable_rfl  (nv_state_t *nv, NvBool bEnable);
+NV_STATUS NV_API_CALL nv_imp_icc_set_bw          (nv_state_t *nv, NvU32 avg_bw_kbps, NvU32 floor_bw_kbps);
+NV_STATUS NV_API_CALL nv_get_num_dpaux_instances(nv_state_t *nv, NvU32 *num_instances);
+NV_STATUS NV_API_CALL nv_get_tegra_brightness_level(nv_state_t *, NvU32 *);
+NV_STATUS NV_API_CALL nv_set_tegra_brightness_level(nv_state_t *, NvU32);
+
+NV_STATUS NV_API_CALL nv_soc_device_reset        (nv_state_t *);
+NV_STATUS NV_API_CALL nv_soc_pm_powergate        (nv_state_t *);
+NV_STATUS NV_API_CALL nv_soc_pm_unpowergate      (nv_state_t *);
+NV_STATUS NV_API_CALL nv_gpio_get_pin_state(nv_state_t *, NvU32, NvU32 *);
+void      NV_API_CALL nv_gpio_set_pin_state(nv_state_t *, NvU32, NvU32);
+NV_STATUS NV_API_CALL nv_gpio_set_pin_direction(nv_state_t *, NvU32, NvU32);
+NV_STATUS NV_API_CALL nv_gpio_get_pin_direction(nv_state_t *, NvU32, NvU32 *);
+NV_STATUS NV_API_CALL nv_gpio_get_pin_number(nv_state_t *, NvU32, NvU32 *);
+NvBool    NV_API_CALL nv_gpio_get_pin_interrupt_status(nv_state_t *, NvU32, NvU32);
+NV_STATUS NV_API_CALL nv_gpio_set_pin_interrupt(nv_state_t *, NvU32, NvU32);
+NvU32     NV_API_CALL nv_tegra_get_rm_interface_type(NvU32);
+NV_STATUS NV_API_CALL nv_tegra_dce_register_ipc_client(NvU32, void *, nvTegraDceClientIpcCallback, NvU32 *);
+NV_STATUS NV_API_CALL nv_tegra_dce_client_ipc_send_recv(NvU32, void *, NvU32);
+NV_STATUS NV_API_CALL nv_tegra_dce_unregister_ipc_client(NvU32);
+NV_STATUS NV_API_CALL nv_dsi_parse_panel_props(nv_state_t *, void *);
+NvBool    NV_API_CALL nv_dsi_is_panel_connected(nv_state_t *);
+NV_STATUS NV_API_CALL nv_dsi_panel_enable(nv_state_t *, void *);
+NV_STATUS NV_API_CALL nv_dsi_panel_reset(nv_state_t *, void *);
+void      NV_API_CALL nv_dsi_panel_disable(nv_state_t *, void *);
+void      NV_API_CALL nv_dsi_panel_cleanup(nv_state_t *, void *);
+NV_STATUS NV_API_CALL nv_soc_mipi_cal_reset(nv_state_t *);
+NvU32     NV_API_CALL nv_soc_fuse_register_read (NvU32 addr);
+NvBool    NV_API_CALL nv_get_hdcp_enabled(nv_state_t *nv);
+NV_STATUS NV_API_CALL nv_get_valid_window_head_mask(nv_state_t *nv, NvU64 *);
+NV_STATUS NV_API_CALL nv_dp_uphy_pll_init(nv_state_t *, NvU32, NvU32);
+NV_STATUS NV_API_CALL nv_dp_uphy_pll_deinit(nv_state_t *);
+NV_STATUS NV_API_CALL nv_soc_i2c_hsp_semaphore_acquire(NvU32 ownerId, NvBool bAcquire, NvU64 timeout);
+typedef void (*nv_soc_tsec_cb_func_t)(void*, void*);
+NvU32     NV_API_CALL nv_soc_tsec_send_cmd(void* cmd, nv_soc_tsec_cb_func_t cb_func, void* cb_context);
+NvU32     NV_API_CALL nv_soc_tsec_event_register(nv_soc_tsec_cb_func_t cb_func, void* cb_context, NvBool is_init_event);
+NvU32     NV_API_CALL nv_soc_tsec_event_unregister(NvBool is_init_event);
+void*     NV_API_CALL nv_soc_tsec_alloc_mem_desc(NvU32 num_bytes, NvU32 *flcn_addr);
+void      NV_API_CALL nv_soc_tsec_free_mem_desc(void *mem_desc);
+NvBool    NV_API_CALL nv_is_clk_enabled          (nv_state_t *, TEGRASOC_WHICH_CLK);
+NV_STATUS NV_API_CALL nv_set_parent              (nv_state_t *, TEGRASOC_WHICH_CLK, TEGRASOC_WHICH_CLK);
+NV_STATUS NV_API_CALL nv_get_parent              (nv_state_t *, TEGRASOC_WHICH_CLK, TEGRASOC_WHICH_CLK*);
+NV_STATUS NV_API_CALL nv_clk_get_handles         (nv_state_t *);
+void      NV_API_CALL nv_clk_clear_handles       (nv_state_t *);
+NV_STATUS NV_API_CALL nv_enable_clk              (nv_state_t *, TEGRASOC_WHICH_CLK);
+void      NV_API_CALL nv_disable_clk             (nv_state_t *, TEGRASOC_WHICH_CLK);
+NV_STATUS NV_API_CALL nv_get_curr_freq           (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
+NV_STATUS NV_API_CALL nv_get_max_freq            (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
+NV_STATUS NV_API_CALL nv_get_min_freq            (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
+NV_STATUS NV_API_CALL nv_set_freq                (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32);
+
 /*
 * ---------------------------------------------------------------------------
 *
@@ -945,6 +1107,7 @@ NvBool     NV_API_CALL  rm_isr                   (nvidia_stack_t *, nv_state_t *
 void       NV_API_CALL  rm_isr_bh                (nvidia_stack_t *, nv_state_t *);
 void       NV_API_CALL  rm_isr_bh_unlocked       (nvidia_stack_t *, nv_state_t *);
 NvBool     NV_API_CALL  rm_is_msix_allowed       (nvidia_stack_t *, nv_state_t *);
+NV_STATUS  NV_API_CALL  rm_pmu_perfmon_get_load  (nvidia_stack_t *, nv_state_t *, NvU32 *, TEGRASOC_DEVFREQ_CLK);
 NV_STATUS  NV_API_CALL  rm_power_management      (nvidia_stack_t *, nv_state_t *, nv_pm_action_t);
 NV_STATUS  NV_API_CALL  rm_stop_user_channels    (nvidia_stack_t *, nv_state_t *);
 NV_STATUS  NV_API_CALL  rm_restart_user_channels (nvidia_stack_t *, nv_state_t *);
@@ -992,14 +1155,16 @@ void       NV_API_CALL  rm_request_dnotifier_state          (nvidia_stack_t *, n
 void       NV_API_CALL  rm_disable_gpu_state_persistence    (nvidia_stack_t *sp, nv_state_t *);
 NV_STATUS  NV_API_CALL  rm_p2p_init_mapping       (nvidia_stack_t *, NvU64, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU64, NvU64, NvU64, NvU64, void (*)(void *), void *);
 NV_STATUS  NV_API_CALL  rm_p2p_destroy_mapping    (nvidia_stack_t *, NvU64);
-NV_STATUS  NV_API_CALL  rm_p2p_get_pages          (nvidia_stack_t *, NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU8 **, void *);
+NV_STATUS  NV_API_CALL  rm_p2p_get_pages          (nvidia_stack_t *, NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU8 **, void *, NvBool *);
 NV_STATUS  NV_API_CALL  rm_p2p_get_gpu_info       (nvidia_stack_t *, NvU64, NvU64, NvU8 **, void **);
-NV_STATUS  NV_API_CALL  rm_p2p_get_pages_persistent (nvidia_stack_t *,  NvU64, NvU64, void **, NvU64 *, NvU32 *, NvBool, void *, void *, void **);
+NV_STATUS  NV_API_CALL  rm_p2p_get_pages_persistent (nvidia_stack_t *,  NvU64, NvU64, void **, NvU64 *, NvU32 *, NvBool, void *, void *, void **, NvBool *);
 NV_STATUS  NV_API_CALL  rm_p2p_register_callback  (nvidia_stack_t *, NvU64, NvU64, NvU64, void *, void (*)(void *), void *);
 NV_STATUS  NV_API_CALL  rm_p2p_put_pages          (nvidia_stack_t *, NvU64, NvU32, NvU64, void *);
 NV_STATUS  NV_API_CALL  rm_p2p_put_pages_persistent(nvidia_stack_t *, void *, void *, void *);
 NV_STATUS  NV_API_CALL  rm_p2p_dma_map_pages      (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU64, NvU32, NvU64 *, void **);
-NV_STATUS  NV_API_CALL  rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *, void **);
+NV_STATUS  NV_API_CALL  rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle,
+                                                   NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *, void **,
+                                                   NvBool *, NvU32 *, NvBool *, nv_memory_type_t *);
 void       NV_API_CALL  rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle);
 NV_STATUS  NV_API_CALL  rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *,
                                                   NvHandle, NvHandle, MemoryRange,
@@ -1010,7 +1175,7 @@ void       NV_API_CALL  rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t
 NV_STATUS  NV_API_CALL  rm_dma_buf_get_client_and_device(nvidia_stack_t *,
                                                nv_state_t *, NvHandle, NvHandle,
                                                NvU8, NvHandle *, NvHandle *,
-                                                NvHandle *, void **, NvBool *);
+                                                NvHandle *, void **, NvBool *, NvBool *);
 void       NV_API_CALL  rm_dma_buf_put_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, void *);

 void       NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd);
@@ -1030,6 +1195,7 @@ NV_STATUS  NV_API_CALL rm_set_external_kernel_client_count(nvidia_stack_t *, nv_
 NV_STATUS  NV_API_CALL rm_schedule_gpu_wakeup(nvidia_stack_t *, nv_state_t *);
 NvBool     NV_API_CALL rm_disable_iomap_wc(void);

+void       NV_API_CALL rm_init_tegra_dynamic_power_management(nvidia_stack_t *, nv_state_t *);
 void       NV_API_CALL rm_init_dynamic_power_management(nvidia_stack_t *, nv_state_t *, NvBool);
 void       NV_API_CALL rm_cleanup_dynamic_power_management(nvidia_stack_t *, nv_state_t *);
 void       NV_API_CALL rm_enable_dynamic_power_management(nvidia_stack_t *, nv_state_t *);
@@ -1043,6 +1209,9 @@ void       NV_API_CALL rm_acpi_nvpcf_notify(nvidia_stack_t *);

 NvBool     NV_API_CALL rm_is_altstack_in_use(void);

+void       NV_API_CALL rm_notify_gpu_addition(nvidia_stack_t *, nv_state_t *);
+void       NV_API_CALL rm_notify_gpu_removal(nvidia_stack_t *, nv_state_t *);
+
 /* vGPU VFIO specific functions */
 NV_STATUS  NV_API_CALL  nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *,
                                               NvU32 *, NvU32 *, NvU32);
@@ -1051,13 +1220,13 @@ NV_STATUS  NV_API_CALL  nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU
 NV_STATUS  NV_API_CALL  nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8);
 NV_STATUS  NV_API_CALL  nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *,
                                             NvU64 *, NvU64 *, NvU32 *, NvBool *, NvU8 *);
-NV_STATUS  NV_API_CALL  nv_vgpu_update_sysfs_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU32);
+NV_STATUS  NV_API_CALL  nv_vgpu_update_sysfs_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU32 *);
 NV_STATUS  NV_API_CALL  nv_vgpu_get_hbm_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU64 *);
 NV_STATUS  NV_API_CALL  nv_vgpu_process_vf_info(nvidia_stack_t *, nv_state_t *, NvU8, NvU32, NvU8, NvU8, NvU8, NvBool, void *);
 NV_STATUS  NV_API_CALL  nv_gpu_bind_event(nvidia_stack_t *, NvU32, NvBool *);
 NV_STATUS  NV_API_CALL  nv_gpu_unbind_event(nvidia_stack_t *, NvU32, NvBool *);

-NV_STATUS NV_API_CALL nv_get_usermap_access_params(nv_state_t*, nv_usermap_access_params_t*);
+NV_STATUS NV_API_CALL nv_check_usermap_access_params(nv_state_t*, const nv_usermap_access_params_t*);
 nv_soc_irq_type_t NV_API_CALL nv_get_current_irq_type(nv_state_t*);
 void       NV_API_CALL  nv_flush_coherent_cpu_cache_range(nv_state_t *nv, NvU64 cpu_virtual, NvU64 size);

--- a/kernel-open/common/inc/nv_common_utils.h
+++ b/kernel-open/common/inc/nv_common_utils.h
@@ -0,0 +1,120 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NV_COMMON_UTILS_H__
+#define __NV_COMMON_UTILS_H__
+
+#include "nvtypes.h"
+#include "nvmisc.h"
+
+#if !defined(TRUE)
+#define TRUE NV_TRUE
+#endif
+
+#if !defined(FALSE)
+#define FALSE NV_FALSE
+#endif
+
+#define NV_IS_UNSIGNED(x) ((__typeof__(x))-1 > 0)
+
+/* Get the length of a statically-sized array. */
+#define ARRAY_LEN(_arr) (sizeof(_arr) / sizeof(_arr[0]))
+
+#define NV_INVALID_HEAD         0xFFFFFFFF
+
+#define NV_INVALID_CONNECTOR_PHYSICAL_INFORMATION (~0)
+
+#if !defined(NV_MIN)
+# define NV_MIN(a,b) (((a)<(b))?(a):(b))
+#endif
+
+#define NV_MIN3(a,b,c) NV_MIN(NV_MIN(a, b), c)
+#define NV_MIN4(a,b,c,d) NV_MIN3(NV_MIN(a,b),c,d)
+
+#if !defined(NV_MAX)
+# define NV_MAX(a,b) (((a)>(b))?(a):(b))
+#endif
+
+#define NV_MAX3(a,b,c) NV_MAX(NV_MAX(a, b), c)
+#define NV_MAX4(a,b,c,d) NV_MAX3(NV_MAX(a,b),c,d)
+
+static inline int NV_LIMIT_VAL_TO_MIN_MAX(int val, int min, int max)
+{
+    if (val < min) {
+        return min;
+    }
+    if (val > max) {
+        return max;
+    }
+    return val;
+}
+
+#define NV_ROUNDUP_DIV(x,y) ((x) / (y) + (((x) % (y)) ? 1 : 0))
+
+/*
+ * Macros used for computing palette entries:
+ *
+ * NV_UNDER_REPLICATE(val, source_size, result_size) expands a value
+ * of source_size bits into a value of target_size bits by shifting
+ * the source value into the high bits and replicating the high bits
+ * of the value into the low bits of the result.
+ *
+ * PALETTE_DEPTH_SHIFT(val, w) maps a colormap entry for a component
+ * that has w bits to an appropriate entry in a LUT of 256 entries.
+ */
+static inline unsigned int NV_UNDER_REPLICATE(unsigned short val,
+                                              int source_size,
+                                              int result_size)
+{
+    return (val << (result_size - source_size)) |
+        (val >> ((source_size << 1) - result_size));
+}
+
+
+static inline unsigned short PALETTE_DEPTH_SHIFT(unsigned short val, int depth)
+{
+    return NV_UNDER_REPLICATE(val, depth, 8);
+}
+
+/*
+ *  Use __builtin_ffs where it is supported, or provide an equivalent
+ *  implementation for platforms like riscv where it is not.
+ */
+#if defined(__GNUC__) && !NVCPU_IS_RISCV64
+static inline int nv_ffs(int x)
+{
+    return __builtin_ffs(x);
+}
+#else
+static inline int nv_ffs(int x)
+{
+    if (x == 0)
+        return 0;
+
+    LOWESTBITIDX_32(x);
+
+    return 1 + x;
+}
+#endif
+
+#endif /* __NV_COMMON_UTILS_H__ */
--- a/kernel-open/common/inc/nv_dpy_id.h
+++ b/kernel-open/common/inc/nv_dpy_id.h
@@ -0,0 +1,370 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2010-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * This header file defines the types NVDpyId and NVDpyIdList, as well
+ * as inline functions to manipulate these types.  NVDpyId and
+ * NVDpyIdList should be treated as opaque by includers of this header
+ * file.
+ */
+
+#ifndef __NV_DPY_ID_H__
+#define __NV_DPY_ID_H__
+
+#include "nvtypes.h"
+#include "nvmisc.h"
+#include "nv_common_utils.h"
+#include <nvlimits.h> /* NV_MAX_SUBDEVICES */
+
+typedef struct {
+    NvU32 opaqueDpyId;
+} NVDpyId;
+
+typedef struct {
+    NvU32 opaqueDpyIdList;
+} NVDpyIdList;
+
+#define NV_DPY_ID_MAX_SUBDEVICES NV_MAX_SUBDEVICES
+#define NV_DPY_ID_MAX_DPYS_IN_LIST 32
+
+/*
+ * For use in combination with nvDpyIdToPrintFormat(); e.g.,
+ *
+ * printf("dpy id: " NV_DPY_ID_PRINT_FORMAT "\n",
+ *        nvDpyIdToPrintFormat(dpyId));
+ *
+ * The includer should not make assumptions about the return type of
+ * nvDpyIdToPrintFormat().
+ */
+#define NV_DPY_ID_PRINT_FORMAT "0x%08x"
+
+/* functions to return an invalid DpyId and empty DpyIdList */
+
+static inline NVDpyId nvInvalidDpyId(void)
+{
+    NVDpyId dpyId = { 0 };
+    return dpyId;
+}
+
+static inline NVDpyIdList nvEmptyDpyIdList(void)
+{
+    NVDpyIdList dpyIdList = { 0 };
+    return dpyIdList;
+}
+
+static inline NVDpyIdList nvAllDpyIdList(void)
+{
+    NVDpyIdList dpyIdList = { ~0U };
+    return dpyIdList;
+}
+
+static inline void
+nvEmptyDpyIdListSubDeviceArray(NVDpyIdList dpyIdList[NV_DPY_ID_MAX_SUBDEVICES])
+{
+    int dispIndex;
+    for (dispIndex = 0; dispIndex < NV_DPY_ID_MAX_SUBDEVICES; dispIndex++) {
+        dpyIdList[dispIndex] = nvEmptyDpyIdList();
+    }
+}
+
+/* set operations on DpyIds and DpyIdLists: Add, Subtract, Intersect, Xor */
+
+static inline __attribute__ ((warn_unused_result))
+NVDpyIdList nvAddDpyIdToDpyIdList(NVDpyId dpyId, NVDpyIdList dpyIdList)
+{
+    NVDpyIdList tmpDpyIdList;
+    tmpDpyIdList.opaqueDpyIdList = dpyIdList.opaqueDpyIdList |
+        dpyId.opaqueDpyId;
+    return tmpDpyIdList;
+}
+
+/* Passing an invalid display ID makes this function return an empty list. */
+static inline __attribute__ ((warn_unused_result))
+NVDpyIdList nvAddDpyIdToEmptyDpyIdList(NVDpyId dpyId)
+{
+    NVDpyIdList tmpDpyIdList;
+    tmpDpyIdList.opaqueDpyIdList =  dpyId.opaqueDpyId;
+    return tmpDpyIdList;
+}
+
+static inline __attribute__ ((warn_unused_result))
+NVDpyIdList nvAddDpyIdListToDpyIdList(NVDpyIdList dpyIdListA,
+                                      NVDpyIdList dpyIdListB)
+{
+    NVDpyIdList tmpDpyIdList;
+    tmpDpyIdList.opaqueDpyIdList = dpyIdListB.opaqueDpyIdList |
+        dpyIdListA.opaqueDpyIdList;
+    return tmpDpyIdList;
+}
+
+/* Returns: dpyIdList - dpyId */
+static inline __attribute__ ((warn_unused_result))
+NVDpyIdList nvDpyIdListMinusDpyId(NVDpyIdList dpyIdList, NVDpyId dpyId)
+{
+    NVDpyIdList tmpDpyIdList;
+    tmpDpyIdList.opaqueDpyIdList = dpyIdList.opaqueDpyIdList &
+        (~dpyId.opaqueDpyId);
+    return tmpDpyIdList;
+}
+
+/* Returns: dpyIdListA - dpyIdListB */
+static inline __attribute__ ((warn_unused_result))
+NVDpyIdList nvDpyIdListMinusDpyIdList(NVDpyIdList dpyIdListA,
+                                      NVDpyIdList dpyIdListB)
+{
+    NVDpyIdList tmpDpyIdList;
+    tmpDpyIdList.opaqueDpyIdList = dpyIdListA.opaqueDpyIdList &
+        (~dpyIdListB.opaqueDpyIdList);
+    return tmpDpyIdList;
+}
+
+static inline __attribute__ ((warn_unused_result))
+NVDpyIdList nvIntersectDpyIdAndDpyIdList(NVDpyId dpyId, NVDpyIdList dpyIdList)
+{
+    NVDpyIdList tmpDpyIdList;
+    tmpDpyIdList.opaqueDpyIdList = dpyIdList.opaqueDpyIdList &
+        dpyId.opaqueDpyId;
+    return tmpDpyIdList;
+}
+
+static inline __attribute__ ((warn_unused_result))
+NVDpyIdList nvIntersectDpyIdListAndDpyIdList(NVDpyIdList dpyIdListA,
+                                             NVDpyIdList dpyIdListB)
+{
+    NVDpyIdList tmpDpyIdList;
+    tmpDpyIdList.opaqueDpyIdList = dpyIdListA.opaqueDpyIdList &
+        dpyIdListB.opaqueDpyIdList;
+    return tmpDpyIdList;
+}
+
+static inline __attribute__ ((warn_unused_result))
+NVDpyIdList nvXorDpyIdAndDpyIdList(NVDpyId dpyId, NVDpyIdList dpyIdList)
+{
+    NVDpyIdList tmpDpyIdList;
+    tmpDpyIdList.opaqueDpyIdList = dpyIdList.opaqueDpyIdList ^
+        dpyId.opaqueDpyId;
+    return tmpDpyIdList;
+}
+
+static inline __attribute__ ((warn_unused_result))
+NVDpyIdList nvXorDpyIdListAndDpyIdList(NVDpyIdList dpyIdListA,
+                                       NVDpyIdList dpyIdListB)
+{
+    NVDpyIdList tmpDpyIdList;
+    tmpDpyIdList.opaqueDpyIdList = dpyIdListA.opaqueDpyIdList ^
+        dpyIdListB.opaqueDpyIdList;
+    return tmpDpyIdList;
+}
+
+
+/* boolean checks */
+
+static inline NvBool nvDpyIdIsInDpyIdList(NVDpyId dpyId,
+                                          NVDpyIdList dpyIdList)
+{
+    return !!(dpyIdList.opaqueDpyIdList & dpyId.opaqueDpyId);
+}
+
+static inline NvBool nvDpyIdIsInvalid(NVDpyId dpyId)
+{
+    return (dpyId.opaqueDpyId == 0);
+}
+
+static inline NvBool nvDpyIdListIsEmpty(NVDpyIdList dpyIdList)
+{
+    return (dpyIdList.opaqueDpyIdList == 0);
+}
+
+static inline NvBool
+nvDpyIdListSubDeviceArrayIsEmpty(NVDpyIdList
+                                 dpyIdList[NV_DPY_ID_MAX_SUBDEVICES])
+{
+    int dispIndex;
+    for (dispIndex = 0; dispIndex < NV_DPY_ID_MAX_SUBDEVICES; dispIndex++) {
+        if (!nvDpyIdListIsEmpty(dpyIdList[dispIndex])) {
+            return NV_FALSE;
+        }
+    }
+    return NV_TRUE;
+}
+
+
+static inline NvBool nvDpyIdsAreEqual(NVDpyId dpyIdA, NVDpyId dpyIdB)
+{
+    return (dpyIdA.opaqueDpyId == dpyIdB.opaqueDpyId);
+}
+
+static inline NvBool nvDpyIdListsAreEqual(NVDpyIdList dpyIdListA,
+                                          NVDpyIdList dpyIdListB)
+{
+    return (dpyIdListA.opaqueDpyIdList == dpyIdListB.opaqueDpyIdList);
+}
+
+static inline NvBool nvDpyIdListIsASubSetofDpyIdList(NVDpyIdList dpyIdListA,
+                                                     NVDpyIdList dpyIdListB)
+{
+    NVDpyIdList intersectedDpyIdList =
+        nvIntersectDpyIdListAndDpyIdList(dpyIdListA, dpyIdListB);
+
+    return nvDpyIdListsAreEqual(intersectedDpyIdList, dpyIdListA);
+}
+
+
+/*
+ * retrieve the individual dpyIds from dpyIdList; if dpyId is invalid,
+ * start at the beginning of the list; otherwise, start at the dpyId
+ * after the specified dpyId
+ */
+
+static inline __attribute__ ((warn_unused_result))
+NVDpyId nvNextDpyIdInDpyIdListUnsorted(NVDpyId dpyId, NVDpyIdList dpyIdList)
+{
+    if (nvDpyIdIsInvalid(dpyId)) {
+        dpyId.opaqueDpyId = 1;
+    } else {
+        dpyId.opaqueDpyId <<= 1;
+    }
+
+    while (dpyId.opaqueDpyId) {
+
+        if (nvDpyIdIsInDpyIdList(dpyId, dpyIdList)) {
+            return dpyId;
+        }
+
+        dpyId.opaqueDpyId <<= 1;
+    }
+
+    /* no dpyIds left in dpyIdlist; return the invalid dpyId */
+
+    return nvInvalidDpyId();
+}
+
+#define FOR_ALL_DPY_IDS(_dpyId, _dpyIdList)                           \
+    for ((_dpyId) = nvNextDpyIdInDpyIdListUnsorted(nvInvalidDpyId(),  \
+                                                   (_dpyIdList));     \
+         !nvDpyIdIsInvalid(_dpyId);                                   \
+         (_dpyId) = nvNextDpyIdInDpyIdListUnsorted((_dpyId),          \
+                                                   (_dpyIdList)))
+
+/* report how many dpyIds are in the dpyIdList */
+
+static inline int nvCountDpyIdsInDpyIdList(NVDpyIdList dpyIdList)
+{
+    return nvPopCount32(dpyIdList.opaqueDpyIdList);
+}
+
+static inline int
+nvCountDpyIdsInDpyIdListSubDeviceArray(NVDpyIdList
+                                       dpyIdList[NV_DPY_ID_MAX_SUBDEVICES])
+{
+    int dispIndex, n = 0;
+
+    for (dispIndex = 0; dispIndex < NV_DPY_ID_MAX_SUBDEVICES; dispIndex++) {
+        n += nvCountDpyIdsInDpyIdList(dpyIdList[dispIndex]);
+    }
+
+    return n;
+}
+
+/* convert between dpyId/dpyIdList and NV-CONTROL values */
+
+static inline int nvDpyIdToNvControlVal(NVDpyId dpyId)
+{
+    return (int) dpyId.opaqueDpyId;
+}
+
+static inline int nvDpyIdListToNvControlVal(NVDpyIdList dpyIdList)
+{
+    return (int) dpyIdList.opaqueDpyIdList;
+}
+
+static inline NVDpyId nvNvControlValToDpyId(int val)
+{
+    NVDpyId dpyId;
+    dpyId.opaqueDpyId = (val == 0) ? 0 : 1 << (nv_ffs(val)-1);
+    return dpyId;
+}
+
+static inline NVDpyIdList nvNvControlValToDpyIdList(int val)
+{
+    NVDpyIdList dpyIdList;
+    dpyIdList.opaqueDpyIdList = val;
+    return dpyIdList;
+}
+
+
+/* convert between dpyId and NvU32 */
+
+static inline NVDpyId nvNvU32ToDpyId(NvU32 val)
+{
+    NVDpyId dpyId;
+    dpyId.opaqueDpyId = (val == 0) ? 0 : 1 << (nv_ffs(val)-1);
+    return dpyId;
+}
+
+static inline NVDpyIdList nvNvU32ToDpyIdList(NvU32 val)
+{
+    NVDpyIdList dpyIdList;
+    dpyIdList.opaqueDpyIdList = val;
+    return dpyIdList;
+}
+
+static inline NvU32 nvDpyIdToNvU32(NVDpyId dpyId)
+{
+    return dpyId.opaqueDpyId;
+}
+
+static inline NvU32 nvDpyIdListToNvU32(NVDpyIdList dpyIdList)
+{
+    return dpyIdList.opaqueDpyIdList;
+}
+
+/* Return the bit position of dpyId: a number in the range [0..31]. */
+static inline NvU32 nvDpyIdToIndex(NVDpyId dpyId)
+{
+    return nv_ffs(dpyId.opaqueDpyId) - 1;
+}
+
+/* Return a display ID that is not in the list passed in. */
+
+static inline NVDpyId nvNewDpyId(NVDpyIdList excludeList)
+{
+    NVDpyId dpyId;
+    if (~excludeList.opaqueDpyIdList == 0) {
+        return nvInvalidDpyId();
+    }
+    dpyId.opaqueDpyId =
+        1U << (nv_ffs(~excludeList.opaqueDpyIdList) - 1);
+    return dpyId;
+}
+
+/* See comment for NV_DPY_ID_PRINT_FORMAT. */
+static inline NvU32 nvDpyIdToPrintFormat(NVDpyId dpyId)
+{
+    return nvDpyIdToNvU32(dpyId);
+}
+
+/* Prevent usage of opaque values. */
+#define opaqueDpyId __ERROR_ACCESS_ME_VIA_NV_DPY_ID_H
+#define opaqueDpyIdList __ERROR_ACCESS_ME_VIA_NV_DPY_ID_H
+
+#endif /* __NV_DPY_ID_H__ */
--- a/src/common/unix/common/utils/interface/nv_smg.h
+++ b/src/common/unix/common/utils/interface/nv_smg.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -20,8 +20,8 @@
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
-#ifndef __NV_SMG_H__
-#define __NV_SMG_H__
+#ifndef __NV_MIG_TYPES_H__
+#define __NV_MIG_TYPES_H__

 #ifdef __cplusplus
 extern "C" {
@@ -29,25 +29,12 @@ extern "C" {

 #include "nvtypes.h"

-/*
- * The simplest required abstraction for accessing RM independent of the
- * calling component which may be a kernel module or userspace driver.
- */
-typedef NvU32 (*NVSubdevSMGRMControl) (void *ctx, NvU32 object, NvU32 cmd, void *params, NvU32 paramsSize);
-typedef NvU32 (*NVSubdevSMGRMAlloc) (void *ctx, NvU32 parent, NvU32 object, NvU32 cls, void *allocParams);
-typedef NvU32 (*NVSubdevSMGRMFree) (void *ctx, NvU32 parent, NvU32 object);
+typedef NvU32 MIGDeviceId;

-NvBool NVSubdevSMGSetPartition(void *ctx,
-                               NvU32 subdevHandle,
-                               const char *computeInstUuid,
-                               NvU32 gpuInstSubscriptionHdl,
-                               NvU32 computeInstSubscriptionHdl,
-                               NVSubdevSMGRMControl rmControl,
-                               NVSubdevSMGRMAlloc rmAlloc,
-                               NVSubdevSMGRMFree rmFree);
+#define NO_MIG_DEVICE 0L

 #ifdef __cplusplus
 }
 #endif

-#endif /* __NV_SMG_H__ */
+#endif /* __NV_MIG_TYPES_H__ */
--- a/kernel-open/common/inc/nv_uvm_interface.h
+++ b/kernel-open/common/inc/nv_uvm_interface.h
@@ -46,6 +46,7 @@ struct UvmOpsUvmEvents;
 #include "nvgputypes.h"
 #include "nvstatus.h"
 #include "nv_uvm_types.h"
+#include "nv_uvm_user_types.h"


 // Define the type here as it's Linux specific, used only by the Linux specific
@@ -660,14 +661,20 @@ NV_STATUS nvUvmInterfaceServiceDeviceInterruptsRM(uvmGpuDeviceHandle device);
    RM will propagate the update to all channels using the provided VA space.
    All channels must be idle when this call is made.

+    If the pageDirectory is in system memory then a CPU physical address must be
+    provided. RM will establish and manage the DMA mapping for the
+    pageDirectory.
+
    Arguments:
      vaSpace[IN}         - VASpace Object
-      physAddress[IN]     - Physical address of new page directory
+      physAddress[IN]     - Physical address of new page directory. If
+                            !bVidMemAperture this is a CPU physical address.
      numEntries[IN]      - Number of entries including previous PDE which will be copied
      bVidMemAperture[IN] - If set pageDirectory will reside in VidMem aperture else sysmem
      pasid[IN]           - PASID (Process Address Space IDentifier) of the process
                            corresponding to the VA space. Ignored unless the VA space
                            object has ATS enabled.
+      dmaAddress[OUT]     - DMA mapping created for physAddress.

    Error codes:
      NV_ERR_GENERIC
@@ -675,7 +682,8 @@ NV_STATUS nvUvmInterfaceServiceDeviceInterruptsRM(uvmGpuDeviceHandle device);
 */
 NV_STATUS nvUvmInterfaceSetPageDirectory(uvmGpuAddressSpaceHandle vaSpace,
                                         NvU64 physAddress, unsigned numEntries,
-                                         NvBool bVidMemAperture, NvU32 pasid);
+                                         NvBool bVidMemAperture, NvU32 pasid,
+                                         NvU64 *dmaAddress);

 /*******************************************************************************
    nvUvmInterfaceUnsetPageDirectory
@@ -1862,5 +1870,4 @@ NV_STATUS nvUvmInterfaceCslIncrementIv(UvmCslContext *uvmCslContext,
 NV_STATUS nvUvmInterfaceCslLogEncryption(UvmCslContext *uvmCslContext,
                                         UvmCslOperation operation,
                                         NvU32 bufferSize);
-
 #endif // _NV_UVM_INTERFACE_H_
--- a/kernel-open/common/inc/nv_uvm_types.h
+++ b/kernel-open/common/inc/nv_uvm_types.h
@@ -22,7 +22,8 @@
 */

 //
-// This file provides common types for both UVM driver and RM's UVM interface.
+// This file provides common types for both the UVM kernel driver and RM's UVM
+// interface.
 //

 #ifndef _NV_UVM_TYPES_H_
@@ -32,21 +33,9 @@
 #include "nvstatus.h"
 #include "nvgputypes.h"
 #include "nvCpuUuid.h"
+#include "nv_uvm_user_types.h" // For UvmGpuCachingType, UvmGpuMappingType, etc


-//
-// Default Page Size if left "0" because in RM BIG page size is default & there
-// are multiple BIG page sizes in RM. These defines are used as flags to "0"
-// should be OK when user is not sure which pagesize allocation it wants
-//
-#define UVM_PAGE_SIZE_DEFAULT    0x0ULL
-#define UVM_PAGE_SIZE_4K         0x1000ULL
-#define UVM_PAGE_SIZE_64K        0x10000ULL
-#define UVM_PAGE_SIZE_128K       0x20000ULL
-#define UVM_PAGE_SIZE_2M         0x200000ULL
-#define UVM_PAGE_SIZE_512M       0x20000000ULL
-#define UVM_PAGE_SIZE_256G       0x4000000000ULL
-
 //
 // When modifying flags, make sure they are compatible with the mirrored
 // PMA_* flags in phys_mem_allocator.h.
@@ -81,9 +70,6 @@
 //
 #define UVM_PMA_CALLED_FROM_PMA_EVICTION        16384

-#define UVM_UUID_LEN 16
-#define UVM_SW_OBJ_SUBCHANNEL 5
-
 typedef unsigned long long UvmGpuPointer;

 //
@@ -268,6 +254,7 @@ typedef struct UvmGpuChannelInfo_tag

    // The errorNotifier is filled out when the channel hits an RC error.
    NvNotification    *errorNotifier;
+
    NvNotification    *keyRotationNotifier;

    NvU32              hwRunlistId;
@@ -297,6 +284,7 @@ typedef struct UvmGpuChannelInfo_tag
    NvU64              gpFifoGpuVa;
    NvU64              gpPutGpuVa;
    NvU64              gpGetGpuVa;
+
    // GPU VA of work submission offset is needed in Confidential Computing
    // so CE channels can ring doorbell of other channels as required for
    // WLC/LCIC work submission
@@ -374,6 +362,9 @@ typedef struct
    // True if the CE can be used for P2P transactions
    NvBool p2p:1;

+    // True if the CE supports encryption
+    NvBool secure:1;
+
    // Mask of physical CEs assigned to this LCE
    //
    // The value returned by RM for this field may change when a GPU is
@@ -442,80 +433,22 @@ typedef struct UvmGpuAllocInfo_tag
                                      // SEV or GPU CC modes are enabled. Ignored otherwise
 } UvmGpuAllocInfo;

-typedef enum
-{
-    UVM_VIRT_MODE_NONE = 0,             // Baremetal or passthrough virtualization
-    UVM_VIRT_MODE_LEGACY = 1,           // Virtualization without SRIOV support
-    UVM_VIRT_MODE_SRIOV_HEAVY = 2,      // Virtualization with SRIOV Heavy configured
-    UVM_VIRT_MODE_SRIOV_STANDARD = 3,   // Virtualization with SRIOV Standard configured
-    UVM_VIRT_MODE_COUNT = 4,
-} UVM_VIRT_MODE;
-
-// !!! The following enums (with UvmRm prefix) are defined and documented in
-// mm/uvm/interface/uvm_types.h and must be mirrored. Please refer to that file
-// for more details.
-
-// UVM GPU mapping types
-typedef enum
-{
-    UvmRmGpuMappingTypeDefault = 0,
-    UvmRmGpuMappingTypeReadWriteAtomic = 1,
-    UvmRmGpuMappingTypeReadWrite = 2,
-    UvmRmGpuMappingTypeReadOnly = 3,
-    UvmRmGpuMappingTypeCount = 4
-} UvmRmGpuMappingType;
-
-// UVM GPU caching types
-typedef enum
-{
-    UvmRmGpuCachingTypeDefault = 0,
-    UvmRmGpuCachingTypeForceUncached = 1,
-    UvmRmGpuCachingTypeForceCached = 2,
-    UvmRmGpuCachingTypeCount = 3
-} UvmRmGpuCachingType;
-
-// UVM GPU format types
-typedef enum {
-   UvmRmGpuFormatTypeDefault = 0,
-   UvmRmGpuFormatTypeBlockLinear = 1,
-   UvmRmGpuFormatTypeCount = 2
-} UvmRmGpuFormatType;
-
-// UVM GPU Element bits types
-typedef enum {
-   UvmRmGpuFormatElementBitsDefault = 0,
-   UvmRmGpuFormatElementBits8 = 1,
-   UvmRmGpuFormatElementBits16 = 2,
-   // Cuda does not support 24-bit width
-   UvmRmGpuFormatElementBits32 = 4,
-   UvmRmGpuFormatElementBits64 = 5,
-   UvmRmGpuFormatElementBits128 = 6,
-   UvmRmGpuFormatElementBitsCount = 7
-} UvmRmGpuFormatElementBits;
-
-// UVM GPU Compression types
-typedef enum {
-    UvmRmGpuCompressionTypeDefault = 0,
-    UvmRmGpuCompressionTypeEnabledNoPlc = 1,
-    UvmRmGpuCompressionTypeCount = 2
-} UvmRmGpuCompressionType;
-
 typedef struct UvmGpuExternalMappingInfo_tag
 {
    // In: GPU caching ability.
-    UvmRmGpuCachingType cachingType;
+    UvmGpuCachingType cachingType;

    // In: Virtual permissions.
-    UvmRmGpuMappingType mappingType;
+    UvmGpuMappingType mappingType;

    // In: RM virtual mapping memory format
-    UvmRmGpuFormatType formatType;
+    UvmGpuFormatType formatType;

    // In: RM virtual mapping element bits
-    UvmRmGpuFormatElementBits elementBits;
+    UvmGpuFormatElementBits elementBits;

    // In: RM virtual compression type
-    UvmRmGpuCompressionType compressionType;
+    UvmGpuCompressionType compressionType;

    // In: Size of the buffer to store PTEs (in bytes).
    NvU64 pteBufferSize;
@@ -541,6 +474,9 @@ typedef struct UvmGpuExternalMappingInfo_tag

    // Out: PTE size (in bytes)
    NvU32 pteSize;
+
+    // Out: UVM needs to invalidate L2 at unmap
+    NvBool bNeedL2InvalidateAtUnmap;
 } UvmGpuExternalMappingInfo;

 typedef struct UvmGpuExternalPhysAddrInfo_tag
@@ -548,7 +484,7 @@ typedef struct UvmGpuExternalPhysAddrInfo_tag
    // In: Virtual permissions. Returns
    // NV_ERR_INVALID_ACCESS_TYPE if input is
    // inaccurate
-    UvmRmGpuMappingType mappingType;
+    UvmGpuMappingType mappingType;

    // In: Size of the buffer to store PhysAddrs (in bytes).
    NvU64 physAddrBufferSize;
@@ -598,6 +534,11 @@ typedef struct UvmGpuP2PCapsParams_tag
    // second, not taking into account the protocols overhead. The reported
    // bandwidth for indirect peers is zero.
    NvU32 totalLinkLineRateMBps;
+
+    // Out: IOMMU/DMA mappings of bar1 of the respective peer vidmem.
+    // Size is 0 if bar1 p2p is not supported.
+    NvU64 bar1DmaAddress[2];
+    NvU64 bar1DmaSize[2];
 } UvmGpuP2PCapsParams;

 // Platform-wide information
@@ -741,6 +682,9 @@ typedef struct UvmGpuInfo_tag

    // GPU supports ATS capability
    NvBool atsSupport;
+
+    // GPU supports Non-PASID ATS capability
+    NvBool nonPasidAtsSupport;
 } UvmGpuInfo;

 typedef struct UvmGpuFbInfo_tag
@@ -754,6 +698,7 @@ typedef struct UvmGpuFbInfo_tag
    NvBool bZeroFb;            // Zero FB mode enabled.
    NvU64  maxVidmemPageSize;  // Largest GPU page size to access vidmem.
    NvBool bStaticBar1Enabled; // Static BAR1 mode is enabled
+    NvBool bStaticBar1WriteCombined; // Write combined is enabled
    NvU64  staticBar1StartOffset;  // The start offset of the the static mapping
    NvU64  staticBar1Size;     // The size of the static mapping
    NvU32  heapStart;          // The start offset of heap in KB, helpful for MIG
@@ -790,19 +735,6 @@ typedef struct UvmPmaAllocationOptions_tag
    NvU32 resultFlags;          // valid if the allocation function returns NV_OK
 } UvmPmaAllocationOptions;

-//
-// Mirrored in PMA (PMA_STATS)
-//
-typedef struct UvmPmaStatistics_tag
-{
-    volatile NvU64 numPages2m;                // PMA-wide 2MB pages count across all regions
-    volatile NvU64 numFreePages64k;           // PMA-wide free 64KB page count across all regions
-    volatile NvU64 numFreePages2m;            // PMA-wide free 2MB pages count across all regions
-    volatile NvU64 numPages2mProtected;       // PMA-wide 2MB pages count in protected memory
-    volatile NvU64 numFreePages64kProtected;  // PMA-wide free 64KB page count in protected memory
-    volatile NvU64 numFreePages2mProtected;   // PMA-wide free 2MB pages count in protected memory
-} UvmPmaStatistics;
-
 /*******************************************************************************
    uvmEventSuspend
    This function will be called by the GPU driver to signal to UVM that the
@@ -1007,17 +939,17 @@ typedef struct UvmGpuFaultInfo_tag
        NvU32 replayableFaultMask;

        // Fault buffer CPU mapping
-        void*  bufferAddress;
-        //
        // When Confidential Computing is disabled, the mapping points to the
        // actual HW fault buffer.
        //
        // When Confidential Computing is enabled, the mapping points to a
        // copy of the HW fault buffer. This "shadow buffer" is maintained
        // by GSP-RM.
+        void*  bufferAddress;

        // Size, in bytes, of the fault buffer pointed by bufferAddress.
        NvU32  bufferSize;
+
        // Mapping pointing to the start of the fault buffer metadata containing
        // a 16Byte authentication tag and a valid byte. Always NULL when
        // Confidential Computing is disabled.
@@ -1095,14 +1027,6 @@ typedef struct UvmGpuAccessCntrInfo_tag
    NvHandle accessCntrBufferHandle;
 } UvmGpuAccessCntrInfo;

-typedef enum
-{
-    UVM_ACCESS_COUNTER_GRANULARITY_64K = 1,
-    UVM_ACCESS_COUNTER_GRANULARITY_2M  = 2,
-    UVM_ACCESS_COUNTER_GRANULARITY_16M = 3,
-    UVM_ACCESS_COUNTER_GRANULARITY_16G = 4,
-} UVM_ACCESS_COUNTER_GRANULARITY;
-
 typedef struct UvmGpuAccessCntrConfig_tag
 {
    NvU32 granularity;
--- a/kernel-open/common/inc/nv_uvm_user_types.h
+++ b/kernel-open/common/inc/nv_uvm_user_types.h
@@ -0,0 +1,166 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+//
+// This file provides common types for the UVM kernel driver, UVM user layer,
+// and RM's UVM interface.
+//
+
+#ifndef _NV_UVM_USER_TYPES_H_
+#define _NV_UVM_USER_TYPES_H_
+
+#include "nvtypes.h"
+
+//
+// Default Page Size if left "0" because in RM BIG page size is default & there
+// are multiple BIG page sizes in RM. These defines are used as flags to "0"
+// should be OK when user is not sure which pagesize allocation it wants
+//
+#define UVM_PAGE_SIZE_DEFAULT    0x0ULL
+#define UVM_PAGE_SIZE_4K         0x1000ULL
+#define UVM_PAGE_SIZE_64K        0x10000ULL
+#define UVM_PAGE_SIZE_128K       0x20000ULL
+#define UVM_PAGE_SIZE_2M         0x200000ULL
+#define UVM_PAGE_SIZE_512M       0x20000000ULL
+#define UVM_PAGE_SIZE_256G       0x4000000000ULL
+
+typedef enum
+{
+    UVM_VIRT_MODE_NONE = 0,             // Baremetal or passthrough virtualization
+    UVM_VIRT_MODE_LEGACY = 1,           // Virtualization without SRIOV support
+    UVM_VIRT_MODE_SRIOV_HEAVY = 2,      // Virtualization with SRIOV Heavy configured
+    UVM_VIRT_MODE_SRIOV_STANDARD = 3,   // Virtualization with SRIOV Standard configured
+    UVM_VIRT_MODE_COUNT = 4,
+} UVM_VIRT_MODE;
+
+//------------------------------------------------------------------------------
+// UVM GPU mapping types
+//
+// These types indicate the kinds of accesses allowed from a given GPU at the
+// specified virtual address range. There are 3 basic kinds of accesses: read,
+// write and atomics. Each type indicates what kinds of accesses are allowed.
+// Accesses of any disallowed kind are fatal. The "Default" type specifies that
+// the UVM driver should decide on the types of accesses allowed.
+//------------------------------------------------------------------------------
+typedef enum
+{
+    UvmGpuMappingTypeDefault = 0,
+    UvmGpuMappingTypeReadWriteAtomic = 1,
+    UvmGpuMappingTypeReadWrite = 2,
+    UvmGpuMappingTypeReadOnly = 3,
+    UvmGpuMappingTypeCount = 4
+} UvmGpuMappingType;
+
+//------------------------------------------------------------------------------
+// UVM GPU caching types
+//
+// These types indicate the cacheability of the specified virtual address range
+// from a given GPU. The "Default" type specifies that the UVM driver should
+// set caching on or off as required to follow the UVM coherence model. The
+// "ForceUncached" and "ForceCached" types will always turn caching off or on
+// respectively. These two types override the cacheability specified by the UVM
+// coherence model.
+//------------------------------------------------------------------------------
+typedef enum
+{
+    UvmGpuCachingTypeDefault = 0,
+    UvmGpuCachingTypeForceUncached = 1,
+    UvmGpuCachingTypeForceCached = 2,
+    UvmGpuCachingTypeCount = 3
+} UvmGpuCachingType;
+
+//------------------------------------------------------------------------------
+// UVM GPU format types
+//
+// These types indicate the memory format of the specified virtual address
+// range for a given GPU. The "Default" type specifies that the UVM driver will
+// detect the format based on the allocation and is mutually inclusive with
+// UvmGpuFormatElementBitsDefault.
+//------------------------------------------------------------------------------
+typedef enum {
+   UvmGpuFormatTypeDefault = 0,
+   UvmGpuFormatTypeBlockLinear = 1,
+   UvmGpuFormatTypeCount = 2
+} UvmGpuFormatType;
+
+//------------------------------------------------------------------------------
+// UVM GPU Element bits types
+//
+// These types indicate the element size of the specified virtual address range
+// for a given GPU. The "Default" type specifies that the UVM driver will
+// detect the element size based on the allocation and is mutually inclusive
+// with UvmGpuFormatTypeDefault. The element size is specified in bits:
+// UvmGpuFormatElementBits8 uses the 8-bits format.
+//------------------------------------------------------------------------------
+typedef enum {
+   UvmGpuFormatElementBitsDefault = 0,
+   UvmGpuFormatElementBits8 = 1,
+   UvmGpuFormatElementBits16 = 2,
+   // Cuda does not support 24-bit width
+   UvmGpuFormatElementBits32 = 4,
+   UvmGpuFormatElementBits64 = 5,
+   UvmGpuFormatElementBits128 = 6,
+   UvmGpuFormatElementBitsCount = 7
+} UvmGpuFormatElementBits;
+
+//------------------------------------------------------------------------------
+// UVM GPU Compression types
+//
+// These types indicate the compression type of the specified virtual address
+// range for a given GPU. The "Default" type specifies that the UVM driver will
+// detect the compression attributes based on the allocation. Any type other
+// than the default will override the compression behavior of the physical
+// allocation. UvmGpuCompressionTypeEnabledNoPlc will disable PLC but enables
+// generic compression. UvmGpuCompressionTypeEnabledNoPlc type is only supported
+// on Turing plus GPUs. Since UvmGpuCompressionTypeEnabledNoPlc type enables
+// generic compression, it can only be used when the compression attribute of
+// the underlying physical allocation is enabled.
+//------------------------------------------------------------------------------
+typedef enum {
+    UvmGpuCompressionTypeDefault = 0,
+    UvmGpuCompressionTypeEnabledNoPlc = 1,
+    UvmGpuCompressionTypeCount = 2
+} UvmGpuCompressionType;
+
+//
+// Mirrored in PMA (PMA_STATS)
+//
+typedef struct UvmPmaStatistics_tag
+{
+    volatile NvU64 numPages2m;                // PMA-wide 2MB pages count across all regions
+    volatile NvU64 numFreePages64k;           // PMA-wide free 64KB page count across all regions
+    volatile NvU64 numFreePages2m;            // PMA-wide free 2MB pages count across all regions
+    volatile NvU64 numPages2mProtected;       // PMA-wide 2MB pages count in protected memory
+    volatile NvU64 numFreePages64kProtected;  // PMA-wide free 64KB page count in protected memory
+    volatile NvU64 numFreePages2mProtected;   // PMA-wide free 2MB pages count in protected memory
+} UvmPmaStatistics;
+
+typedef enum
+{
+    UVM_ACCESS_COUNTER_GRANULARITY_64K = 1,
+    UVM_ACCESS_COUNTER_GRANULARITY_2M  = 2,
+    UVM_ACCESS_COUNTER_GRANULARITY_16M = 3,
+    UVM_ACCESS_COUNTER_GRANULARITY_16G = 4,
+} UVM_ACCESS_COUNTER_GRANULARITY;
+
+#endif // _NV_UVM_USER_TYPES_H_
--- a/kernel-open/common/inc/nvi2c.h
+++ b/kernel-open/common/inc/nvi2c.h
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _NV_I2C_H_
+#define _NV_I2C_H_
+
+#define NV_I2C_MSG_WR 0x0000
+#define NV_I2C_MSG_RD 0x0001
+
+typedef struct nv_i2c_msg_s
+{
+    NvU16 addr;
+    NvU16 flags;
+    NvU16 len;
+    NvU8* buf;
+} nv_i2c_msg_t;
+
+#endif
--- a/kernel-open/common/inc/nvimpshared.h
+++ b/kernel-open/common/inc/nvimpshared.h
@@ -0,0 +1,96 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/******************************************************************************\
+*                                                                              *
+*  Description:                                                                *
+*    Accommodates sharing of IMP-related structures between kernel interface   *
+*    files and core RM.                                                        *
+*                                                                              *
+\******************************************************************************/
+
+#pragma once
+
+#include <nvtypes.h>
+#if defined(_MSC_VER)
+#pragma warning(disable:4324)
+#endif
+
+//
+// This file was generated with FINN, an NVIDIA coding tool.
+// Source file:      nvimpshared.finn
+//
+
+
+
+
+//
+// There are only a small number of discrete dramclk frequencies available on
+// the system.  This structure contains IMP-relevant information associated
+// with a specific dramclk frequency.
+//
+typedef struct DRAM_CLK_INSTANCE {
+    NvU32 dram_clk_freq_khz;
+
+    NvU32 mchub_clk_khz;
+
+    NvU32 mc_clk_khz;
+
+    NvU32 max_iso_bw_kbps;
+
+    //
+    // switch_latency_ns is the maximum time required to switch the dramclk
+    // frequency to the frequency specified in dram_clk_freq_khz.
+    //
+    NvU32 switch_latency_ns;
+} DRAM_CLK_INSTANCE;
+
+//
+// This table is used to collect information from other modules that is needed
+// for RM IMP calculations.  (Used on Tegra only.)
+//
+typedef struct TEGRA_IMP_IMPORT_DATA {
+    //
+    // max_iso_bw_kbps stores the maximum possible ISO bandwidth available to
+    // display, assuming display is the only active ISO client.  (Note that ISO
+    // bandwidth will typically be allocated to multiple clients, so display
+    // will generally not have access to the maximum possible bandwidth.)
+    //
+    NvU32             max_iso_bw_kbps;
+
+    // On Orin, each dram channel is 16 bits wide.
+    NvU32             num_dram_channels;
+
+    //
+    // dram_clk_instance stores entries for all possible dramclk frequencies,
+    // sorted by dramclk frequency in increasing order.
+    //
+    // "24" is expected to be larger than the actual number of required entries
+    // (which is provided by a BPMP API), but it can be increased if necessary.
+    //
+    // num_dram_clk_entries is filled in with the actual number of distinct
+    // dramclk entries.
+    //
+    NvU32             num_dram_clk_entries;
+    DRAM_CLK_INSTANCE dram_clk_instance[24];
+} TEGRA_IMP_IMPORT_DATA;
--- a/kernel-open/common/inc/nvkms-api-types.h
+++ b/kernel-open/common/inc/nvkms-api-types.h
@@ -640,22 +640,28 @@ enum NvKmsInputColorRange {
     * If DEFAULT is provided, driver will assume full range for RGB formats
     * and limited range for YUV formats.
     */
-    NVKMS_INPUT_COLORRANGE_DEFAULT = 0,
+    NVKMS_INPUT_COLOR_RANGE_DEFAULT = 0,

-    NVKMS_INPUT_COLORRANGE_LIMITED = 1,
+    NVKMS_INPUT_COLOR_RANGE_LIMITED = 1,

-    NVKMS_INPUT_COLORRANGE_FULL = 2,
+    NVKMS_INPUT_COLOR_RANGE_FULL = 2,
 };

 enum NvKmsInputColorSpace {
-    /* Unknown colorspace; no de-gamma will be applied */
-    NVKMS_INPUT_COLORSPACE_NONE = 0,
+    /* Unknown colorspace */
+    NVKMS_INPUT_COLOR_SPACE_NONE = 0,

-    /* Linear, Rec.709 [-0.5, 7.5) */
-    NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR = 1,
+    NVKMS_INPUT_COLOR_SPACE_BT601 = 1,
+    NVKMS_INPUT_COLOR_SPACE_BT709 = 2,
+    NVKMS_INPUT_COLOR_SPACE_BT2020 = 3,
+    NVKMS_INPUT_COLOR_SPACE_BT2100 = NVKMS_INPUT_COLOR_SPACE_BT2020,

-    /* PQ, Rec.2020 unity */
-    NVKMS_INPUT_COLORSPACE_BT2100_PQ = 2,
+    NVKMS_INPUT_COLOR_SPACE_SCRGB = 4
+};
+
+enum NvKmsInputTf {
+    NVKMS_INPUT_TF_LINEAR = 0,
+    NVKMS_INPUT_TF_PQ = 1
 };

 enum NvKmsOutputColorimetry {
--- a/kernel-open/common/inc/nvkms-kapi.h
+++ b/kernel-open/common/inc/nvkms-kapi.h
@@ -24,8 +24,10 @@
 #if !defined(__NVKMS_KAPI_H__)

 #include "nvtypes.h"
+#include "nv_mig_types.h"

 #include "nv-gpu-info.h"
+#include "nv_dpy_id.h"
 #include "nvkms-api-types.h"
 #include "nvkms-format.h"

@@ -173,12 +175,18 @@ struct NvKmsKapiDeviceResourcesInfo {
        NvBool  supportsSyncpts;

        NvBool requiresVrrSemaphores;
+
+        NvBool  supportsInputColorRange;
+        NvBool  supportsInputColorSpace;
    } caps;

    NvU64 supportedSurfaceMemoryFormats[NVKMS_KAPI_LAYER_MAX];
    NvBool supportsICtCp[NVKMS_KAPI_LAYER_MAX];

    struct NvKmsKapiLutCaps lutCaps;
+
+    NvU64 vtFbBaseAddress;
+    NvU64 vtFbSize;
 };

 #define NVKMS_KAPI_LAYER_MASK(layerType) (1 << (layerType))
@@ -204,6 +212,7 @@ struct NvKmsKapiConnectorInfo {
    NvU32        numIncompatibleConnectors;
    NvKmsKapiConnector incompatibleConnectorHandles[NVKMS_KAPI_MAX_CONNECTORS];

+    NVDpyIdList dynamicDpyIdList;
 };

 struct NvKmsKapiStaticDisplayInfo {
@@ -222,6 +231,8 @@ struct NvKmsKapiStaticDisplayInfo {
    NvKmsKapiDisplay possibleCloneHandles[NVKMS_KAPI_MAX_CLONE_DISPLAYS];

    NvU32 headMask;
+
+    NvBool isDpMST;
 };

 struct NvKmsKapiSyncParams {
@@ -260,7 +271,8 @@ struct NvKmsKapiLayerConfig {
        NvBool enabled;
    } hdrMetadata;

-    enum NvKmsOutputTf tf;
+    enum NvKmsInputTf inputTf;
+    enum NvKmsOutputTf outputTf;

    NvU8 minPresentInterval;
    NvBool tearing;
@@ -272,6 +284,7 @@ struct NvKmsKapiLayerConfig {
    NvU16 dstWidth, dstHeight;

    enum NvKmsInputColorSpace inputColorSpace;
+    enum NvKmsInputColorRange inputColorRange;

    struct {
        NvBool enabled;
@@ -315,7 +328,10 @@ struct NvKmsKapiLayerRequestedConfig {
        NvBool dstXYChanged            : 1;
        NvBool dstWHChanged            : 1;
        NvBool cscChanged              : 1;
-        NvBool tfChanged               : 1;
+        NvBool inputTfChanged          : 1;
+        NvBool outputTfChanged         : 1;
+        NvBool inputColorSpaceChanged  : 1;
+        NvBool inputColorRangeChanged  : 1;
        NvBool hdrMetadataChanged      : 1;
        NvBool matrixOverridesChanged  : 1;
        NvBool ilutChanged             : 1;
@@ -481,6 +497,8 @@ struct NvKmsKapiEvent {
 struct NvKmsKapiAllocateDeviceParams {
    /* [IN] GPU ID obtained from enumerateGpus() */
    NvU32 gpuId;
+    /* [IN] MIG device if requested */
+    MIGDeviceId migDevice;

    /* [IN] Private data of device allocator */
    void *privateData;
@@ -544,9 +562,6 @@ struct NvKmsKapiCreateSurfaceParams {
     *      explicit_layout is NV_TRUE and layout is
     *      NvKmsSurfaceMemoryLayoutBlockLinear */
    NvU8 log2GobsPerBlockY;
-
-    /* [IN] Whether a surface can be updated directly on the screen */
-    NvBool noDisplayCaching;
 };

 enum NvKmsKapiAllocationType {
@@ -555,6 +570,28 @@ enum NvKmsKapiAllocationType {
    NVKMS_KAPI_ALLOCATION_TYPE_OFFSCREEN = 2,
 };

+struct NvKmsKapiAllocateMemoryParams {
+    /* [IN] BlockLinear or Pitch */
+    enum NvKmsSurfaceMemoryLayout layout;
+
+    /* [IN] Allocation type */
+    enum NvKmsKapiAllocationType type;
+
+    /* [IN] Size, in bytes, of the memory to allocate */
+    NvU64 size;
+
+    /* [IN] Whether memory can be updated directly on the screen */
+    NvBool noDisplayCaching;
+
+    /* [IN] Whether to allocate memory from video memory or system memory */
+    NvBool useVideoMemory;
+
+    /* [IN/OUT] For input, non-zero if compression backing store should be
+     * allocated for the memory, for output, non-zero if compression backing
+     * store was allocated for the memory */
+    NvU8 *compressible;
+};
+
 typedef enum NvKmsKapiRegisterWaiterResultRec {
    NVKMS_KAPI_REG_WAITER_FAILED,
    NVKMS_KAPI_REG_WAITER_SUCCESS,
@@ -563,6 +600,11 @@ typedef enum NvKmsKapiRegisterWaiterResultRec {

 typedef void NvKmsKapiSuspendResumeCallbackFunc(NvBool suspend);

+struct NvKmsKapiGpuInfo {
+    nv_gpu_info_t gpuInfo;
+    MIGDeviceId   migDevice;
+};
+
 struct NvKmsKapiFunctionsTable {

    /*!
@@ -579,14 +621,19 @@ struct NvKmsKapiFunctionsTable {
    } systemInfo;

    /*!
-     * Enumerate the available physical GPUs that can be used with NVKMS.
+     * Enumerate the available GPUs that can be used with NVKMS.
     *
-     * \param [out]  gpuInfo  The information of the enumerated GPUs.
-     *                        It is an array of NVIDIA_MAX_GPUS elements.
+     * The gpuCallback will be called with a NvKmsKapiGpuInfo for each
+     * physical and MIG GPU currently available in the system.
+     *
+     * \param [in] gpuCallback          Client function to handle each GPU.
     *
     * \return  Count of enumerated gpus.
     */
-    NvU32 (*enumerateGpus)(nv_gpu_info_t *gpuInfo);
+    NvU32 (*enumerateGpus)
+    (
+        void (*gpuCallback)(const struct NvKmsKapiGpuInfo *info)
+    );

    /*!
     * Allocate an NVK device using which you can query/allocate resources on
@@ -816,66 +863,22 @@ struct NvKmsKapiFunctionsTable {
    );

    /*!
-     * Allocate some unformatted video memory of the specified size.
+     * Allocate some unformatted video or system memory of the specified size.
     *
-     * This function allocates video memory on the specified GPU.
-     * It should be suitable for mapping on the CPU as a pitch
-     * linear or block-linear surface.
+     * This function allocates video or system memory on the specified GPU. It
+     * should be suitable for mapping on the CPU as a pitch linear or
+     * block-linear surface.
     *
-     * \param [in] device  A device allocated using allocateDevice().
+     * \param [in]     device  A device allocated using allocateDevice().
     *
-     * \param [in] layout  BlockLinear or Pitch.
-     * 
-     * \param [in] type    Allocation type.
-     *
-     * \param [in] size    Size, in bytes, of the memory to allocate.
-     *
-     * \param [in/out] compressible For input, non-zero if compression
-     *                              backing store should be allocated for
-     *                              the memory, for output, non-zero if
-     *                              compression backing store was
-     *                              allocated for the memory.
+     * \param [in/out] params  Parameters required for memory allocation.
     *
     * \return An valid memory handle on success, NULL on failure.
     */
-    struct NvKmsKapiMemory* (*allocateVideoMemory)
+    struct NvKmsKapiMemory* (*allocateMemory)
    (
        struct NvKmsKapiDevice *device,
-        enum NvKmsSurfaceMemoryLayout layout,
-        enum NvKmsKapiAllocationType type,
-        NvU64 size,
-        NvU8 *compressible
-    );
-
-    /*!
-     * Allocate some unformatted system memory of the specified size.
-     *
-     * This function allocates system memory . It should be suitable
-     * for mapping on the CPU as a pitch linear or block-linear surface.
-     *
-     * \param [in] device  A device allocated using allocateDevice().
-     *
-     * \param [in] layout  BlockLinear or Pitch.
-     * 
-     * \param [in] type    Allocation type.
-     *
-     * \param [in] size    Size, in bytes, of the memory to allocate.
-     *
-     * \param [in/out] compressible For input, non-zero if compression
-     *                              backing store should be allocated for
-     *                              the memory, for output, non-zero if
-     *                              compression backing store was
-     *                              allocated for the memory.
-     *
-     * \return An valid memory handle on success, NULL on failure.
-     */
-    struct NvKmsKapiMemory* (*allocateSystemMemory)
-    (
-        struct NvKmsKapiDevice *device,
-        enum NvKmsSurfaceMemoryLayout layout,
-        enum NvKmsKapiAllocationType type,
-        NvU64 size,
-        NvU8 *compressible
+        struct NvKmsKapiAllocateMemoryParams *params
    );

    /*!
@@ -1559,6 +1562,26 @@ struct NvKmsKapiFunctionsTable {
        NvS32 index
    );

+    /*!
+     * Check or wait on a head's LUT notifier.
+     *
+     * \param [in]  device              A device allocated using allocateDevice().
+     *
+     * \param [in]  head                The head to check for LUT completion.
+     *
+     * \param [in]  waitForCompletion   If true, wait for the notifier in NvKms
+     *                                  before returning.
+     *
+     * \param [out] complete            Returns whether the notifier has completed.
+     */
+    NvBool
+    (*checkLutNotifier)
+    (
+        struct NvKmsKapiDevice *device,
+        NvU32 head,
+        NvBool waitForCompletion
+    );
+
    /*
     * Notify NVKMS that the system's framebuffer console has been disabled and
     * the reserved allocation for the old framebuffer console can be unmapped.
--- a/kernel-open/common/inc/nvmisc.h
+++ b/kernel-open/common/inc/nvmisc.h
@@ -580,7 +580,6 @@ nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
    n64 = BIT_IDX_64(LOWESTBIT(n64));\
 }

-
 // Destructive operation on n32
 #define HIGHESTBITIDX_32(n32)   \
 {                               \
@@ -592,6 +591,17 @@ nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
    n32 = count;                \
 }

+// Destructive operation on n64
+#define HIGHESTBITIDX_64(n64)   \
+{                               \
+    NvU64 count = 0;            \
+    while (n64 >>= 1)           \
+    {                           \
+        count++;                \
+    }                           \
+    n64 = count;                \
+}
+
 // Destructive operation on n32
 #define ROUNDUP_POW2(n32) \
 {                         \
@@ -701,11 +711,6 @@ nvPrevPow2_U64(const NvU64 x )
    }                                                       \
 }

-//
-// Bug 4851259: Newly added functions must be hidden from certain HS-signed
-// ucode compilers to avoid signature mismatch.
-//
-#ifndef NVDEC_1_0
 /*!
 * Returns the position of nth set bit in the given mask.
 *
@@ -735,8 +740,6 @@ nvGetNthSetBitIndex32(NvU32 mask, NvU32 n)
    return -1;
 }

-#endif // NVDEC_1_0
-
 //
 // Size to use when declaring variable-sized arrays
 //
@@ -780,12 +783,15 @@ nvGetNthSetBitIndex32(NvU32 mask, NvU32 n)
 // Returns the offset (in bytes) of 'member' in struct 'type'.
 #ifndef NV_OFFSETOF
    #if defined(__GNUC__) && (__GNUC__ > 3)
-        #define NV_OFFSETOF(type, member)   ((NvU32)__builtin_offsetof(type, member))
+        #define NV_OFFSETOF(type, member)   ((NvUPtr) __builtin_offsetof(type, member))
    #else
-        #define NV_OFFSETOF(type, member)    ((NvU32)(NvU64)&(((type *)0)->member)) // shouldn't we use PtrToUlong? But will need to include windows header.
+        #define NV_OFFSETOF(type, member)    ((NvUPtr) &(((type *)0)->member))
    #endif
 #endif

+// Given a pointer and the member it is of the parent struct, return a pointer to the parent struct
+#define NV_CONTAINEROF(ptr, type, member) ((type *) (((NvUPtr) ptr) - NV_OFFSETOF(type, member)))
+
 //
 // Performs a rounded division of b into a (unsigned). For SIGNED version of
 // NV_ROUNDED_DIV() macro check the comments in bug 769777.
--- a/kernel-open/common/inc/nvstatuscodes.h
+++ b/kernel-open/common/inc/nvstatuscodes.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -159,7 +159,12 @@ NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_NOT_READY,         0x00000081, "Nvlink Fabri
 NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_FAILURE,           0x00000082, "Nvlink Fabric Probe failed")
 NV_STATUS_CODE(NV_ERR_GPU_MEMORY_ONLINING_FAILURE,     0x00000083, "GPU Memory Onlining failed")
 NV_STATUS_CODE(NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE, 0x00000084, "Reduction Manager is not available")
+NV_STATUS_CODE(NV_ERR_THRESHOLD_CROSSED,               0x00000085, "A fatal threshold has been crossed")
 NV_STATUS_CODE(NV_ERR_RESOURCE_RETIREMENT_ERROR,       0x00000086, "An error occurred while trying to retire a resource")
+NV_STATUS_CODE(NV_ERR_FABRIC_STATE_OUT_OF_SYNC,        0x00000087, "NVLink fabric state cached by the driver is out of sync")
+NV_STATUS_CODE(NV_ERR_BUFFER_FULL,                     0x00000088, "Buffer is full")
+NV_STATUS_CODE(NV_ERR_BUFFER_EMPTY,                    0x00000089, "Buffer is empty")
+NV_STATUS_CODE(NV_ERR_MC_FLA_OFFSET_TABLE_FULL,        0x0000008A, "Multicast FLA offset table has no available slots")

 // Warnings:
 NV_STATUS_CODE(NV_WARN_HOT_SWITCH,                     0x00010001, "WARNING Hot switch")
@@ -170,5 +175,6 @@ NV_STATUS_CODE(NV_WARN_MORE_PROCESSING_REQUIRED,       0x00010005, "WARNING More
 NV_STATUS_CODE(NV_WARN_NOTHING_TO_DO,                  0x00010006, "WARNING Nothing to do")
 NV_STATUS_CODE(NV_WARN_NULL_OBJECT,                    0x00010007, "WARNING NULL object found")
 NV_STATUS_CODE(NV_WARN_OUT_OF_RANGE,                   0x00010008, "WARNING value out of range")
+NV_STATUS_CODE(NV_WARN_THRESHOLD_CROSSED,              0x00010009, "WARNING Threshold has been crossed")

 #endif /* SDK_NVSTATUSCODES_H */
--- a/kernel-open/common/inc/nvtypes.h
+++ b/kernel-open/common/inc/nvtypes.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,10 +24,6 @@
 #ifndef NVTYPES_INCLUDED
 #define NVTYPES_INCLUDED

-#ifdef __cplusplus
-extern "C" {
-#endif
-
 #include "cpuopsys.h"

 #ifndef NVTYPES_USE_STDINT
@@ -55,6 +51,10 @@ extern "C" {
 #endif
 #endif // __cplusplus

+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #if defined(MAKE_NV64TYPES_8BYTES_ALIGNED) && defined(__i386__)
 // ensure or force 8-bytes alignment of NV 64-bit types
 #define OPTIONAL_ALIGN8_ATTR __attribute__((aligned(8)))
--- a/kernel-open/common/inc/os-interface.h
+++ b/kernel-open/common/inc/os-interface.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -70,144 +70,145 @@ typedef struct os_wait_queue os_wait_queue;
 * ---------------------------------------------------------------------------
 */

-NV_STATUS   NV_API_CALL  os_alloc_mem                (void **, NvU64);
-void        NV_API_CALL  os_free_mem                 (void *);
-NV_STATUS   NV_API_CALL  os_get_current_time         (NvU32 *, NvU32 *);
-NvU64       NV_API_CALL  os_get_current_tick         (void);
-NvU64       NV_API_CALL  os_get_current_tick_hr      (void);
-NvU64       NV_API_CALL  os_get_tick_resolution      (void);
-NV_STATUS   NV_API_CALL  os_delay                    (NvU32);
-NV_STATUS   NV_API_CALL  os_delay_us                 (NvU32);
-NvU64       NV_API_CALL  os_get_cpu_frequency        (void);
-NvU32       NV_API_CALL  os_get_current_process      (void);
-void        NV_API_CALL  os_get_current_process_name (char *, NvU32);
-NV_STATUS   NV_API_CALL  os_get_current_thread       (NvU64 *);
-char*       NV_API_CALL  os_string_copy              (char *, const char *);
-NvU32       NV_API_CALL  os_string_length            (const char *);
-NvU32       NV_API_CALL  os_strtoul                  (const char *, char **, NvU32);
-NvS32       NV_API_CALL  os_string_compare           (const char *, const char *);
-NvS32       NV_API_CALL  os_snprintf                 (char *, NvU32, const char *, ...);
-NvS32       NV_API_CALL  os_vsnprintf                (char *, NvU32, const char *, va_list);
-void        NV_API_CALL  os_log_error                (const char *, va_list);
-void*       NV_API_CALL  os_mem_copy                 (void *, const void *, NvU32);
-NV_STATUS   NV_API_CALL  os_memcpy_from_user         (void *, const void *, NvU32);
-NV_STATUS   NV_API_CALL  os_memcpy_to_user           (void *, const void *, NvU32);
-void*       NV_API_CALL  os_mem_set                  (void *, NvU8, NvU32);
-NvS32       NV_API_CALL  os_mem_cmp                  (const NvU8 *, const NvU8 *, NvU32);
-void*       NV_API_CALL  os_pci_init_handle          (NvU32, NvU8, NvU8, NvU8, NvU16 *, NvU16 *);
-NV_STATUS   NV_API_CALL  os_pci_read_byte            (void *, NvU32, NvU8 *);
-NV_STATUS   NV_API_CALL  os_pci_read_word            (void *, NvU32, NvU16 *);
-NV_STATUS   NV_API_CALL  os_pci_read_dword           (void *, NvU32, NvU32 *);
-NV_STATUS   NV_API_CALL  os_pci_write_byte           (void *, NvU32, NvU8);
-NV_STATUS   NV_API_CALL  os_pci_write_word           (void *, NvU32, NvU16);
-NV_STATUS   NV_API_CALL  os_pci_write_dword          (void *, NvU32, NvU32);
-NvBool      NV_API_CALL  os_pci_remove_supported     (void);
-void        NV_API_CALL  os_pci_remove               (void *);
-void*       NV_API_CALL  os_map_kernel_space         (NvU64, NvU64, NvU32);
-void        NV_API_CALL  os_unmap_kernel_space       (void *, NvU64);
+NV_STATUS   NV_API_CALL  os_alloc_mem                     (void **, NvU64);
+void        NV_API_CALL  os_free_mem                      (void *);
+NV_STATUS   NV_API_CALL  os_get_system_time               (NvU32 *, NvU32 *);
+NvU64       NV_API_CALL  os_get_monotonic_time_ns         (void);
+NvU64       NV_API_CALL  os_get_monotonic_time_ns_hr      (void);
+NvU64       NV_API_CALL  os_get_monotonic_tick_resolution_ns (void);
+NV_STATUS   NV_API_CALL  os_delay                         (NvU32);
+NV_STATUS   NV_API_CALL  os_delay_us                      (NvU32);
+NvU64       NV_API_CALL  os_get_cpu_frequency             (void);
+NvU32       NV_API_CALL  os_get_current_process           (void);
+void        NV_API_CALL  os_get_current_process_name      (char *, NvU32);
+NV_STATUS   NV_API_CALL  os_get_current_thread            (NvU64 *);
+char*       NV_API_CALL  os_string_copy                   (char *, const char *);
+NvU32       NV_API_CALL  os_string_length                 (const char *);
+NvU32       NV_API_CALL  os_strtoul                       (const char *, char **, NvU32);
+NvS32       NV_API_CALL  os_string_compare                (const char *, const char *);
+NvS32       NV_API_CALL  os_snprintf                      (char *, NvU32, const char *, ...);
+NvS32       NV_API_CALL  os_vsnprintf                     (char *, NvU32, const char *, va_list);
+void        NV_API_CALL  os_log_error                     (const char *, va_list);
+void*       NV_API_CALL  os_mem_copy                      (void *, const void *, NvU32);
+NV_STATUS   NV_API_CALL  os_memcpy_from_user              (void *, const void *, NvU32);
+NV_STATUS   NV_API_CALL  os_memcpy_to_user                (void *, const void *, NvU32);
+void*       NV_API_CALL  os_mem_set                       (void *, NvU8, NvU32);
+NvS32       NV_API_CALL  os_mem_cmp                       (const NvU8 *, const NvU8 *, NvU32);
+void*       NV_API_CALL  os_pci_init_handle               (NvU32, NvU8, NvU8, NvU8, NvU16 *, NvU16 *);
+NV_STATUS   NV_API_CALL  os_pci_read_byte                 (void *, NvU32, NvU8 *);
+NV_STATUS   NV_API_CALL  os_pci_read_word                 (void *, NvU32, NvU16 *);
+NV_STATUS   NV_API_CALL  os_pci_read_dword                (void *, NvU32, NvU32 *);
+NV_STATUS   NV_API_CALL  os_pci_write_byte                (void *, NvU32, NvU8);
+NV_STATUS   NV_API_CALL  os_pci_write_word                (void *, NvU32, NvU16);
+NV_STATUS   NV_API_CALL  os_pci_write_dword               (void *, NvU32, NvU32);
+NvBool      NV_API_CALL  os_pci_remove_supported          (void);
+void        NV_API_CALL  os_pci_remove                    (void *);
+void*       NV_API_CALL  os_map_kernel_space              (NvU64, NvU64, NvU32);
+void        NV_API_CALL  os_unmap_kernel_space            (void *, NvU64);
 #if defined(NV_VMWARE)
-void*       NV_API_CALL  os_map_user_space           (MemoryArea *, NvU32, NvU32, void **);
-void        NV_API_CALL  os_unmap_user_space         (void *, NvU64, void *);
+void*       NV_API_CALL  os_map_user_space                (MemoryArea *, NvU32, NvU32, void **);
+void        NV_API_CALL  os_unmap_user_space              (void *, NvU64, void *);
 #endif
-NV_STATUS   NV_API_CALL  os_flush_cpu_cache_all      (void);
-NV_STATUS   NV_API_CALL  os_flush_user_cache         (void);
+NV_STATUS   NV_API_CALL  os_flush_cpu_cache_all           (void);
+NV_STATUS   NV_API_CALL  os_flush_user_cache              (void);
 void        NV_API_CALL  os_flush_cpu_write_combine_buffer(void);
-NvU8        NV_API_CALL  os_io_read_byte             (NvU32);
-NvU16       NV_API_CALL  os_io_read_word             (NvU32);
-NvU32       NV_API_CALL  os_io_read_dword            (NvU32);
-void        NV_API_CALL  os_io_write_byte            (NvU32, NvU8);
-void        NV_API_CALL  os_io_write_word            (NvU32, NvU16);
-void        NV_API_CALL  os_io_write_dword           (NvU32, NvU32);
-NvBool      NV_API_CALL  os_is_administrator         (void);
-NvBool      NV_API_CALL  os_check_access             (RsAccessRight accessRight);
-void        NV_API_CALL  os_dbg_init                 (void);
-void        NV_API_CALL  os_dbg_breakpoint           (void);
-void        NV_API_CALL  os_dbg_set_level            (NvU32);
-NvU32       NV_API_CALL  os_get_cpu_count            (void);
-NvU32       NV_API_CALL  os_get_cpu_number           (void);
-void        NV_API_CALL  os_disable_console_access   (void);
-void        NV_API_CALL  os_enable_console_access    (void);
-NV_STATUS   NV_API_CALL  os_registry_init            (void);
-NvU64       NV_API_CALL  os_get_max_user_va          (void);
-NV_STATUS   NV_API_CALL  os_schedule                 (void);
-NV_STATUS   NV_API_CALL  os_alloc_spinlock           (void **);
-void        NV_API_CALL  os_free_spinlock            (void *);
-NvU64       NV_API_CALL  os_acquire_spinlock         (void *);
-void        NV_API_CALL  os_release_spinlock         (void *, NvU64);
-NV_STATUS   NV_API_CALL  os_queue_work_item          (struct os_work_queue *, void *);
-NV_STATUS   NV_API_CALL  os_flush_work_queue         (struct os_work_queue *, NvBool);
-NvBool      NV_API_CALL  os_is_queue_flush_ongoing   (struct os_work_queue *);
-NV_STATUS   NV_API_CALL  os_alloc_mutex              (void **);
-void        NV_API_CALL  os_free_mutex               (void *);
-NV_STATUS   NV_API_CALL  os_acquire_mutex            (void *);
-NV_STATUS   NV_API_CALL  os_cond_acquire_mutex       (void *);
-void        NV_API_CALL  os_release_mutex            (void *);
-void*       NV_API_CALL  os_alloc_semaphore          (NvU32);
-void        NV_API_CALL  os_free_semaphore           (void *);
-NV_STATUS   NV_API_CALL  os_acquire_semaphore        (void *);
-NV_STATUS   NV_API_CALL  os_cond_acquire_semaphore   (void *);
-NV_STATUS   NV_API_CALL  os_release_semaphore        (void *);
-void*       NV_API_CALL  os_alloc_rwlock             (void);
-void        NV_API_CALL  os_free_rwlock              (void *);
-NV_STATUS   NV_API_CALL  os_acquire_rwlock_read      (void *);
-NV_STATUS   NV_API_CALL  os_acquire_rwlock_write     (void *);
-NV_STATUS   NV_API_CALL  os_cond_acquire_rwlock_read (void *);
-NV_STATUS   NV_API_CALL  os_cond_acquire_rwlock_write(void *);
-void        NV_API_CALL  os_release_rwlock_read      (void *);
-void        NV_API_CALL  os_release_rwlock_write     (void *);
-NvBool      NV_API_CALL  os_semaphore_may_sleep      (void);
-NV_STATUS   NV_API_CALL  os_get_version_info         (os_version_info*);
-NV_STATUS   NV_API_CALL  os_get_is_openrm            (NvBool *);
-NvBool      NV_API_CALL  os_is_isr                   (void);
-NvBool      NV_API_CALL  os_pat_supported            (void);
-void        NV_API_CALL  os_dump_stack               (void);
-NvBool      NV_API_CALL  os_is_efi_enabled           (void);
-NvBool      NV_API_CALL  os_is_xen_dom0              (void);
-NvBool      NV_API_CALL  os_is_vgx_hyper             (void);
-NV_STATUS   NV_API_CALL  os_inject_vgx_msi           (NvU16, NvU64, NvU32);
-NvBool      NV_API_CALL  os_is_grid_supported        (void);
-NvU32       NV_API_CALL  os_get_grid_csp_support     (void);
-void        NV_API_CALL  os_bug_check                (NvU32, const char *);
-NV_STATUS   NV_API_CALL  os_lock_user_pages          (void *, NvU64, void **, NvU32);
-NV_STATUS   NV_API_CALL  os_lookup_user_io_memory    (void *, NvU64, NvU64 **);
-NV_STATUS   NV_API_CALL  os_unlock_user_pages        (NvU64, void *, NvU32);
-NV_STATUS   NV_API_CALL  os_match_mmap_offset        (void *, NvU64, NvU64 *);
-NV_STATUS   NV_API_CALL  os_get_euid                 (NvU32 *);
-NV_STATUS   NV_API_CALL  os_get_smbios_header        (NvU64 *pSmbsAddr);
-NV_STATUS   NV_API_CALL  os_get_acpi_rsdp_from_uefi  (NvU32 *);
-void        NV_API_CALL  os_add_record_for_crashLog  (void *, NvU32);
-void        NV_API_CALL  os_delete_record_for_crashLog (void *);
-NV_STATUS   NV_API_CALL  os_call_vgpu_vfio           (void *, NvU32);
-NV_STATUS   NV_API_CALL  os_device_vm_present        (void);
-NV_STATUS   NV_API_CALL  os_numa_memblock_size       (NvU64 *);
-NV_STATUS   NV_API_CALL  os_alloc_pages_node         (NvS32, NvU32, NvU32, NvU64 *);
-NV_STATUS   NV_API_CALL  os_get_page                 (NvU64 address);
-NV_STATUS   NV_API_CALL  os_put_page                 (NvU64 address);
-NvU32       NV_API_CALL  os_get_page_refcount        (NvU64 address);
-NvU32       NV_API_CALL  os_count_tail_pages         (NvU64 address);
-void        NV_API_CALL  os_free_pages_phys          (NvU64, NvU32);
-NV_STATUS   NV_API_CALL  os_open_temporary_file      (void **);
-void        NV_API_CALL  os_close_file               (void *);
-NV_STATUS   NV_API_CALL  os_write_file               (void *, NvU8 *, NvU64, NvU64);
-NV_STATUS   NV_API_CALL  os_read_file                (void *, NvU8 *, NvU64, NvU64);
-NV_STATUS   NV_API_CALL  os_open_readonly_file       (const char *, void **);
-NV_STATUS   NV_API_CALL  os_open_and_read_file       (const char *, NvU8 *, NvU64);
-NvBool      NV_API_CALL  os_is_nvswitch_present      (void);
-NV_STATUS   NV_API_CALL  os_get_random_bytes         (NvU8 *, NvU16);
-NV_STATUS   NV_API_CALL  os_alloc_wait_queue         (os_wait_queue **);
-void        NV_API_CALL  os_free_wait_queue          (os_wait_queue *);
-void        NV_API_CALL  os_wait_uninterruptible     (os_wait_queue *);
-void        NV_API_CALL  os_wait_interruptible       (os_wait_queue *);
-void        NV_API_CALL  os_wake_up                  (os_wait_queue *);
-nv_cap_t*   NV_API_CALL  os_nv_cap_init               (const char *);
-nv_cap_t*   NV_API_CALL  os_nv_cap_create_dir_entry   (nv_cap_t *, const char *, int);
-nv_cap_t*   NV_API_CALL  os_nv_cap_create_file_entry  (nv_cap_t *, const char *, int);
-void        NV_API_CALL  os_nv_cap_destroy_entry      (nv_cap_t *);
-int         NV_API_CALL  os_nv_cap_validate_and_dup_fd(const nv_cap_t *, int);
-void        NV_API_CALL  os_nv_cap_close_fd           (int);
-NvS32       NV_API_CALL  os_imex_channel_get          (NvU64);
-NvS32       NV_API_CALL  os_imex_channel_count        (void);
+NvU8        NV_API_CALL  os_io_read_byte                  (NvU32);
+NvU16       NV_API_CALL  os_io_read_word                  (NvU32);
+NvU32       NV_API_CALL  os_io_read_dword                 (NvU32);
+void        NV_API_CALL  os_io_write_byte                 (NvU32, NvU8);
+void        NV_API_CALL  os_io_write_word                 (NvU32, NvU16);
+void        NV_API_CALL  os_io_write_dword                (NvU32, NvU32);
+NvBool      NV_API_CALL  os_is_administrator              (void);
+NvBool      NV_API_CALL  os_check_access                  (RsAccessRight accessRight);
+void        NV_API_CALL  os_dbg_init                      (void);
+void        NV_API_CALL  os_dbg_breakpoint                (void);
+void        NV_API_CALL  os_dbg_set_level                 (NvU32);
+NvU32       NV_API_CALL  os_get_cpu_count                 (void);
+NvU32       NV_API_CALL  os_get_cpu_number                (void);
+void        NV_API_CALL  os_disable_console_access        (void);
+void        NV_API_CALL  os_enable_console_access         (void);
+NV_STATUS   NV_API_CALL  os_registry_init                 (void);
+NvU64       NV_API_CALL  os_get_max_user_va               (void);
+NV_STATUS   NV_API_CALL  os_schedule                      (void);
+NV_STATUS   NV_API_CALL  os_alloc_spinlock                (void **);
+void        NV_API_CALL  os_free_spinlock                 (void *);
+NvU64       NV_API_CALL  os_acquire_spinlock              (void *);
+void        NV_API_CALL  os_release_spinlock              (void *, NvU64);
+NV_STATUS   NV_API_CALL  os_queue_work_item               (struct os_work_queue *, void *);
+NV_STATUS   NV_API_CALL  os_flush_work_queue              (struct os_work_queue *, NvBool);
+NvBool      NV_API_CALL  os_is_queue_flush_ongoing        (struct os_work_queue *);
+NV_STATUS   NV_API_CALL  os_alloc_mutex                   (void **);
+void        NV_API_CALL  os_free_mutex                    (void *);
+NV_STATUS   NV_API_CALL  os_acquire_mutex                 (void *);
+NV_STATUS   NV_API_CALL  os_cond_acquire_mutex            (void *);
+void        NV_API_CALL  os_release_mutex                 (void *);
+void*       NV_API_CALL  os_alloc_semaphore               (NvU32);
+void        NV_API_CALL  os_free_semaphore                (void *);
+NV_STATUS   NV_API_CALL  os_acquire_semaphore             (void *);
+NV_STATUS   NV_API_CALL  os_cond_acquire_semaphore        (void *);
+NV_STATUS   NV_API_CALL  os_release_semaphore             (void *);
+void*       NV_API_CALL  os_alloc_rwlock                  (void);
+void        NV_API_CALL  os_free_rwlock                   (void *);
+NV_STATUS   NV_API_CALL  os_acquire_rwlock_read           (void *);
+NV_STATUS   NV_API_CALL  os_acquire_rwlock_write          (void *);
+NV_STATUS   NV_API_CALL  os_cond_acquire_rwlock_read      (void *);
+NV_STATUS   NV_API_CALL  os_cond_acquire_rwlock_write     (void *);
+void        NV_API_CALL  os_release_rwlock_read           (void *);
+void        NV_API_CALL  os_release_rwlock_write          (void *);
+NvBool      NV_API_CALL  os_semaphore_may_sleep           (void);
+NV_STATUS   NV_API_CALL  os_get_version_info              (os_version_info*);
+NV_STATUS   NV_API_CALL  os_get_is_openrm                 (NvBool *);
+NvBool      NV_API_CALL  os_is_isr                        (void);
+NvBool      NV_API_CALL  os_pat_supported                 (void);
+void        NV_API_CALL  os_dump_stack                    (void);
+NvBool      NV_API_CALL  os_is_efi_enabled                (void);
+NvBool      NV_API_CALL  os_is_xen_dom0                   (void);
+NvBool      NV_API_CALL  os_is_vgx_hyper                  (void);
+NV_STATUS   NV_API_CALL  os_inject_vgx_msi                (NvU16, NvU64, NvU32);
+NvBool      NV_API_CALL  os_is_grid_supported             (void);
+NvU32       NV_API_CALL  os_get_grid_csp_support          (void);
+void        NV_API_CALL  os_bug_check                     (NvU32, const char *);
+NV_STATUS   NV_API_CALL  os_lock_user_pages               (void *, NvU64, void **, NvU32);
+NV_STATUS   NV_API_CALL  os_lookup_user_io_memory         (void *, NvU64, NvU64 **);
+NV_STATUS   NV_API_CALL  os_unlock_user_pages             (NvU64, void *, NvU32);
+NV_STATUS   NV_API_CALL  os_match_mmap_offset             (void *, NvU64, NvU64 *);
+NV_STATUS   NV_API_CALL  os_get_euid                      (NvU32 *);
+NV_STATUS   NV_API_CALL  os_get_smbios_header             (NvU64 *pSmbsAddr);
+NV_STATUS   NV_API_CALL  os_get_acpi_rsdp_from_uefi       (NvU32 *);
+void        NV_API_CALL  os_add_record_for_crashLog       (void *, NvU32);
+void        NV_API_CALL  os_delete_record_for_crashLog    (void *);
+NV_STATUS   NV_API_CALL  os_call_vgpu_vfio                (void *, NvU32);
+NV_STATUS   NV_API_CALL  os_device_vm_present             (void);
+NV_STATUS   NV_API_CALL  os_numa_memblock_size            (NvU64 *);
+NV_STATUS   NV_API_CALL  os_alloc_pages_node              (NvS32, NvU32, NvU32, NvU64 *);
+NV_STATUS   NV_API_CALL  os_get_page                      (NvU64 address);
+NV_STATUS   NV_API_CALL  os_put_page                      (NvU64 address);
+NvU32       NV_API_CALL  os_get_page_refcount             (NvU64 address);
+NvU32       NV_API_CALL  os_count_tail_pages              (NvU64 address);
+void        NV_API_CALL  os_free_pages_phys               (NvU64, NvU32);
+NV_STATUS   NV_API_CALL  os_open_temporary_file           (void **);
+void        NV_API_CALL  os_close_file                    (void *);
+NV_STATUS   NV_API_CALL  os_write_file                    (void *, NvU8 *, NvU64, NvU64);
+NV_STATUS   NV_API_CALL  os_read_file                     (void *, NvU8 *, NvU64, NvU64);
+NV_STATUS   NV_API_CALL  os_open_readonly_file            (const char *, void **);
+NV_STATUS   NV_API_CALL  os_open_and_read_file            (const char *, NvU8 *, NvU64);
+NvBool      NV_API_CALL  os_is_nvswitch_present           (void);
+NV_STATUS   NV_API_CALL  os_get_random_bytes              (NvU8 *, NvU16);
+NV_STATUS   NV_API_CALL  os_alloc_wait_queue              (os_wait_queue **);
+void        NV_API_CALL  os_free_wait_queue               (os_wait_queue *);
+void        NV_API_CALL  os_wait_uninterruptible          (os_wait_queue *);
+void        NV_API_CALL  os_wait_interruptible            (os_wait_queue *);
+void        NV_API_CALL  os_wake_up                       (os_wait_queue *);
+nv_cap_t*   NV_API_CALL  os_nv_cap_init                   (const char *);
+nv_cap_t*   NV_API_CALL  os_nv_cap_create_dir_entry       (nv_cap_t *, const char *, int);
+nv_cap_t*   NV_API_CALL  os_nv_cap_create_file_entry      (nv_cap_t *, const char *, int);
+void        NV_API_CALL  os_nv_cap_destroy_entry          (nv_cap_t *);
+int         NV_API_CALL  os_nv_cap_validate_and_dup_fd    (const nv_cap_t *, int);
+void        NV_API_CALL  os_nv_cap_close_fd               (int);
+NvS32       NV_API_CALL  os_imex_channel_get              (NvU64);
+NvS32       NV_API_CALL  os_imex_channel_count            (void);

+NV_STATUS   NV_API_CALL  os_get_tegra_platform       (NvU32 *);
 enum os_pci_req_atomics_type {
    OS_INTF_PCIE_REQ_ATOMICS_32BIT,
    OS_INTF_PCIE_REQ_ATOMICS_64BIT,
@@ -223,12 +224,16 @@ void*       NV_API_CALL  os_get_pid_info(void);
 void        NV_API_CALL  os_put_pid_info(void *pid_info);
 NV_STATUS   NV_API_CALL  os_find_ns_pid(void *pid_info, NvU32 *ns_pid);
 NvBool      NV_API_CALL  os_is_init_ns(void);
+NV_STATUS   NV_API_CALL  os_iommu_sva_bind(void *arg, void **handle, NvU32 *pasid);
+void        NV_API_CALL  os_iommu_sva_unbind(void *handle);

-extern NvU32 os_page_size;
+extern NvU64 os_page_size;
+extern NvU64 os_max_page_size;
 extern NvU64 os_page_mask;
 extern NvU8  os_page_shift;
 extern NvBool os_cc_enabled;
 extern NvBool os_cc_sev_snp_enabled;
+extern NvBool os_cc_sme_enabled;
 extern NvBool os_cc_snp_vtom_enabled;
 extern NvBool os_cc_tdx_enabled;
 extern NvBool os_dma_buf_enabled;
@@ -265,4 +270,9 @@ int  NV_API_CALL  nv_printf(NvU32 debuglevel, const char *printf_format, ...);
 #define NV_LOCK_USER_PAGES_FLAGS_WRITE_NO                  0x00000000
 #define NV_LOCK_USER_PAGES_FLAGS_WRITE_YES                 0x00000001

+// NV OS Tegra platform type defines
+#define NV_OS_TEGRA_PLATFORM_SIM        0
+#define NV_OS_TEGRA_PLATFORM_FPGA       1
+#define NV_OS_TEGRA_PLATFORM_SILICON    2
+
 #endif /* OS_INTERFACE_H */
--- a/kernel-open/common/inc/os_dsi_panel_props.h
+++ b/kernel-open/common/inc/os_dsi_panel_props.h
@@ -0,0 +1,387 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _OS_DSI_PANEL_PARAMS_H_
+#define _OS_DSI_PANEL_PARAMS_H_
+
+#define DSI_GENERIC_LONG_WRITE                  0x29
+#define DSI_DCS_LONG_WRITE                      0x39
+#define DSI_GENERIC_SHORT_WRITE_1_PARAMS        0x13
+#define DSI_GENERIC_SHORT_WRITE_2_PARAMS        0x23
+#define DSI_DCS_WRITE_0_PARAM                   0x05
+#define DSI_DCS_WRITE_1_PARAM                   0x15
+#define DSI_DCS_READ_PARAM                      0x06
+#define DSI_DCS_COMPRESSION_MODE		        0x07
+#define DSI_DCS_PPS_LONG_WRITE			        0x0A
+
+#define DSI_DCS_SET_ADDR_MODE                   0x36
+#define DSI_DCS_EXIT_SLEEP_MODE                 0x11
+#define DSI_DCS_ENTER_SLEEP_MODE                0x10
+#define DSI_DCS_SET_DISPLAY_ON                  0x29
+#define DSI_DCS_SET_DISPLAY_OFF                 0x28
+#define DSI_DCS_SET_TEARING_EFFECT_OFF          0x34
+#define DSI_DCS_SET_TEARING_EFFECT_ON           0x35
+#define DSI_DCS_NO_OP                           0x0
+#define DSI_NULL_PKT_NO_DATA                    0x9
+#define DSI_BLANKING_PKT_NO_DATA                0x19
+#define DSI_DCS_SET_COMPRESSION_METHOD          0xC0
+
+/* DCS commands for command mode */
+#define DSI_ENTER_PARTIAL_MODE                  0x12
+#define DSI_SET_PIXEL_FORMAT                    0x3A
+#define DSI_AREA_COLOR_MODE                     0x4C
+#define DSI_SET_PARTIAL_AREA                    0x30
+#define DSI_SET_PAGE_ADDRESS                    0x2B
+#define DSI_SET_ADDRESS_MODE                    0x36
+#define DSI_SET_COLUMN_ADDRESS                  0x2A
+#define DSI_WRITE_MEMORY_START                  0x2C
+#define DSI_WRITE_MEMORY_CONTINUE               0x3C
+
+#define PKT_ID0(id)     ((((id) & 0x3f) << 3) | \
+                        (((DSI_ENABLE) & 0x1) << 9))
+#define PKT_LEN0(len)   (((len) & 0x7) << 0)
+#define PKT_ID1(id)     ((((id) & 0x3f) << 13) | \
+                        (((DSI_ENABLE) & 0x1) << 19))
+#define PKT_LEN1(len)   (((len) & 0x7) << 10)
+#define PKT_ID2(id)     ((((id) & 0x3f) << 23) | \
+                        (((DSI_ENABLE) & 0x1) << 29))
+#define PKT_LEN2(len)   (((len) & 0x7) << 20)
+#define PKT_ID3(id)     ((((id) & 0x3f) << 3) | \
+                        (((DSI_ENABLE) & 0x1) << 9))
+#define PKT_LEN3(len)   (((len) & 0x7) << 0)
+#define PKT_ID4(id)     ((((id) & 0x3f) << 13) | \
+                        (((DSI_ENABLE) & 0x1) << 19))
+#define PKT_LEN4(len)   (((len) & 0x7) << 10)
+#define PKT_ID5(id)     ((((id) & 0x3f) << 23) | \
+                        (((DSI_ENABLE) & 0x1) << 29))
+#define PKT_LEN5(len)   (((len) & 0x7) << 20)
+#define PKT_LP          (((DSI_ENABLE) & 0x1) << 30)
+#define NUMOF_PKT_SEQ   12
+
+/* DSI pixel data format, enum values should match with dt-bindings in tegra-panel.h */
+typedef enum
+{
+    DSI_PIXEL_FORMAT_16BIT_P,
+    DSI_PIXEL_FORMAT_18BIT_P,
+    DSI_PIXEL_FORMAT_18BIT_NP,
+    DSI_PIXEL_FORMAT_24BIT_P,
+    DSI_PIXEL_FORMAT_8BIT_DSC,
+    DSI_PIXEL_FORMAT_12BIT_DSC,
+    DSI_PIXEL_FORMAT_16BIT_DSC,
+    DSI_PIXEL_FORMAT_10BIT_DSC,
+    DSI_PIXEL_FORMAT_30BIT_P,
+    DSI_PIXEL_FORMAT_36BIT_P,
+} DSIPIXELFORMAT;
+
+/* DSI virtual channel number */
+typedef enum
+{
+    DSI_VIRTUAL_CHANNEL_0,
+    DSI_VIRTUAL_CHANNEL_1,
+    DSI_VIRTUAL_CHANNEL_2,
+    DSI_VIRTUAL_CHANNEL_3,
+} DSIVIRTUALCHANNEL;
+
+/* DSI transmit method for video data */
+typedef enum
+{
+    DSI_VIDEO_TYPE_VIDEO_MODE,
+    DSI_VIDEO_TYPE_COMMAND_MODE,
+} DSIVIDEODATAMODE;
+
+/* DSI HS clock mode */
+typedef enum
+{
+    DSI_VIDEO_CLOCK_CONTINUOUS,
+    DSI_VIDEO_CLOCK_TX_ONLY,
+} DSICLOCKMODE;
+
+/* DSI burst mode setting in video mode. Each mode is assigned with a
+ * fixed value. The rationale behind this is to avoid change of these
+ * values, since the calculation of dsi clock depends on them. */
+typedef enum
+{
+    DSI_VIDEO_NON_BURST_MODE = 0,
+    DSI_VIDEO_NON_BURST_MODE_WITH_SYNC_END = 1,
+    DSI_VIDEO_BURST_MODE_LOWEST_SPEED = 2,
+    DSI_VIDEO_BURST_MODE_LOW_SPEED = 3,
+    DSI_VIDEO_BURST_MODE_MEDIUM_SPEED = 4,
+    DSI_VIDEO_BURST_MODE_FAST_SPEED = 5,
+    DSI_VIDEO_BURST_MODE_FASTEST_SPEED = 6,
+} DSIVIDEOBURSTMODE;
+
+/* DSI Ganged Mode */
+typedef enum
+{
+    DSI_GANGED_SYMMETRIC_LEFT_RIGHT = 1,
+    DSI_GANGED_SYMMETRIC_EVEN_ODD = 2,
+    DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP = 3,
+} DSIGANGEDTYPE;
+
+typedef enum
+{
+    DSI_LINK0,
+    DSI_LINK1,
+} DSILINKNUM;
+
+/* DSI Command Packet type */
+typedef enum
+{
+    DSI_PACKET_CMD,
+    DSI_DELAY_MS,
+    DSI_GPIO_SET,
+    DSI_SEND_FRAME,
+    DSI_PACKET_VIDEO_VBLANK_CMD,
+    DSI_DELAY_US,
+} DSICMDPKTTYPE;
+
+/* DSI Phy type */
+typedef enum
+{
+    DSI_DPHY,
+    DSI_CPHY,
+} DSIPHYTYPE;
+
+enum {
+    DSI_GPIO_LCD_RESET,
+    DSI_GPIO_PANEL_EN,
+    DSI_GPIO_PANEL_EN_1,
+    DSI_GPIO_BL_ENABLE,
+    DSI_GPIO_BL_PWM,
+    DSI_GPIO_AVDD_AVEE_EN,
+    DSI_GPIO_VDD_1V8_LCD_EN,
+    DSI_GPIO_TE,
+    DSI_GPIO_BRIDGE_EN_0,
+    DSI_GPIO_BRIDGE_EN_1,
+    DSI_GPIO_BRIDGE_REFCLK_EN,
+    DSI_N_GPIO_PANEL, /* add new gpio above this entry */
+};
+
+enum
+{
+    DSI_DISABLE,
+    DSI_ENABLE,
+};
+
+
+typedef struct
+{
+    NvU8      cmd_type;
+    NvU8      data_id;
+    union
+    {
+        NvU16 data_len;
+        NvU16 delay_ms;
+        NvU16 delay_us;
+        NvU32 gpio;
+        NvU16 frame_cnt;
+        struct
+        {
+            NvU8 data0;
+            NvU8 data1;
+        } sp;
+    } sp_len_dly;
+    NvU32      *pdata;
+    NvU8      link_id;
+    NvBool    club_cmd;
+} DSI_CMD, *PDSICMD;
+
+typedef struct
+{
+    NvU16             t_hsdexit_ns;
+    NvU16             t_hstrail_ns;
+    NvU16             t_datzero_ns;
+    NvU16             t_hsprepare_ns;
+    NvU16             t_hsprebegin_ns;
+    NvU16             t_hspost_ns;
+
+    NvU16             t_clktrail_ns;
+    NvU16             t_clkpost_ns;
+    NvU16             t_clkzero_ns;
+    NvU16             t_tlpx_ns;
+
+    NvU16             t_clkprepare_ns;
+    NvU16             t_clkpre_ns;
+    NvU16             t_wakeup_ns;
+
+    NvU16             t_taget_ns;
+    NvU16             t_tasure_ns;
+    NvU16             t_tago_ns;
+} DSI_PHY_TIMING_IN_NS;
+
+typedef struct
+{
+    NvU32 hActive;
+    NvU32 vActive;
+    NvU32 hFrontPorch;
+    NvU32 vFrontPorch;
+    NvU32 hBackPorch;
+    NvU32 vBackPorch;
+    NvU32 hSyncWidth;
+    NvU32 vSyncWidth;
+    NvU32 hPulsePolarity;
+    NvU32 vPulsePolarity;
+    NvU32 pixelClkRate;
+} DSITIMINGS, *PDSITIMINGS;
+
+typedef struct
+{
+    NvU8              n_data_lanes;                   /* required */
+    NvU8              pixel_format;                   /* required */
+    NvU8              refresh_rate;                   /* required */
+    NvU8              rated_refresh_rate;
+    NvU8              panel_reset;                    /* required */
+    NvU8              virtual_channel;                /* required */
+    NvU8              dsi_instance;
+    NvU16             dsi_panel_rst_gpio;
+    NvU16             dsi_panel_bl_en_gpio;
+    NvU16             dsi_panel_bl_pwm_gpio;
+    NvU16             even_odd_split_width;
+    NvU8              controller_vs;
+
+    NvBool            panel_has_frame_buffer; /* required*/
+
+    /* Deprecated. Use DSI_SEND_FRAME panel command instead. */
+    NvBool            panel_send_dc_frames;
+
+    DSI_CMD           *dsi_init_cmd;          /* required */
+    NvU16             n_init_cmd;             /* required */
+    NvU32             *dsi_init_cmd_array;
+    NvU32             init_cmd_array_size;
+    NvBool            sendInitCmdsEarly;
+
+    DSI_CMD           *dsi_early_suspend_cmd;
+    NvU16             n_early_suspend_cmd;
+    NvU32             *dsi_early_suspend_cmd_array;
+    NvU32             early_suspend_cmd_array_size;
+
+    DSI_CMD           *dsi_late_resume_cmd;
+    NvU16             n_late_resume_cmd;
+    NvU32             *dsi_late_resume_cmd_array;
+    NvU32             late_resume_cmd_array_size;
+
+    DSI_CMD           *dsi_postvideo_cmd;
+    NvU16             n_postvideo_cmd;
+    NvU32             *dsi_postvideo_cmd_array;
+    NvU32             postvideo_cmd_array_size;
+
+    DSI_CMD           *dsi_suspend_cmd;               /* required */
+    NvU16             n_suspend_cmd;                  /* required */
+    NvU32             *dsi_suspend_cmd_array;
+    NvU32             suspend_cmd_array_size;
+
+    NvU8              video_data_type;                /* required */
+    NvU8              video_clock_mode;
+    NvU8              video_burst_mode;
+    NvU8              ganged_type;
+    NvU16             ganged_overlap;
+    NvBool            ganged_swap_links;
+    NvBool            ganged_write_to_all_links;
+    NvU8              split_link_type;
+
+    NvU8              suspend_aggr;
+
+    NvU16             panel_buffer_size_byte;
+    NvU16             panel_reset_timeout_msec;
+
+    NvBool            hs_cmd_mode_supported;
+    NvBool            hs_cmd_mode_on_blank_supported;
+    NvBool            enable_hs_clock_on_lp_cmd_mode;
+    NvBool            no_pkt_seq_eot; /* 1st generation panel may not
+                                       * support eot. Don't set it for
+                                       * most panels.*/
+    const NvU32       *pktSeq;
+    NvU32             *pktSeq_array;
+    NvU32             pktSeq_array_size;
+    NvBool            skip_dsi_pkt_header;
+    NvBool            power_saving_suspend;
+    NvBool            suspend_stop_stream_late;
+    NvBool            dsi2lvds_bridge_enable;
+    NvBool            dsi2edp_bridge_enable;
+
+    NvU32             max_panel_freq_khz;
+    NvU32             lp_cmd_mode_freq_khz;
+    NvU32             lp_read_cmd_mode_freq_khz;
+    NvU32             hs_clk_in_lp_cmd_mode_freq_khz;
+    NvU32             burst_mode_freq_khz;
+    NvU32             fpga_freq_khz;
+
+    NvU32             te_gpio;
+    NvBool            te_polarity_low;
+    NvBool            dsiEnVRR;
+    NvBool            dsiVrrPanelSupportsTe;
+    NvBool            dsiForceSetTePin;
+
+    int               panel_gpio[DSI_N_GPIO_PANEL];
+    NvBool            panel_gpio_populated;
+
+    NvU32             dpd_dsi_pads;
+
+    DSI_PHY_TIMING_IN_NS phyTimingNs;
+
+    NvU8              *bl_name;
+
+    NvBool            lp00_pre_panel_wakeup;
+    NvBool            ulpm_not_supported;
+    NvBool            use_video_host_fifo_for_cmd;
+    NvBool            dsi_csi_loopback;
+    NvBool            set_max_timeout;
+    NvBool            use_legacy_dphy_core;
+    // Swap P/N pins polarity of all data lanes
+    NvBool            swap_data_lane_polarity;
+    // Swap P/N pins polarity of clock lane
+    NvBool            swap_clock_lane_polarity;
+    // Reverse clock polarity for partition A/B. 1st SOT bit goes on negedge of Clock lane
+    NvBool            reverse_clock_polarity;
+    // DSI Lane Crossbar. Allocating xbar array for max number of lanes
+    NvBool            lane_xbar_exists;
+    NvU32             lane_xbar_ctrl[8];
+    NvU32             refresh_rate_adj;
+
+    NvU8              dsiPhyType;
+    NvBool            en_data_scrambling;
+
+    NvU32             dsipll_vco_rate_hz;
+    NvU32             dsipll_clkoutpn_rate_hz;
+    NvU32             dsipll_clkouta_rate_hz;
+    NvU32             vpll0_rate_hz;
+
+    DSITIMINGS        dsiTimings;
+
+    // DSC Parameters
+    NvBool            dsiDscEnable;
+    NvU32             dsiDscBpp;
+    NvU32             dsiDscNumSlices;
+    NvU32             dsiDscSliceWidth;
+    NvU32             dsiDscSliceHeight;
+    NvBool            dsiDscEnBlockPrediction;
+    NvBool            dsiDscEnDualDsc;
+    NvU32             dsiDscDecoderMajorVersion;
+    NvU32             dsiDscDecoderMinorVersion;
+    NvBool            dsiDscUseCustomPPS;
+    NvU32             dsiDscCustomPPSData[32];
+
+    // Driver allocates memory for PPS cmd to be sent to Panel
+    NvBool            ppsCmdMemAllocated;
+} DSI_PANEL_INFO;
+
+#endif
--- a/kernel-open/common/inc/os_gpio.h
+++ b/kernel-open/common/inc/os_gpio.h
@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020 - 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _OS_GPIO_H_
+#define _OS_GPIO_H_
+
+typedef enum
+{
+    NV_OS_GPIO_FUNC_HOTPLUG_A,
+    NV_OS_GPIO_FUNC_HOTPLUG_B,
+    NV_OS_GPIO_FUNC_HOTPLUG_C,
+    NV_OS_GPIO_FUNC_HOTPLUG_D,
+} NV_OS_GPIO_FUNC_NAMES;
+
+#endif
--- a/kernel-open/common/inc/rm-gpu-ops.h
+++ b/kernel-open/common/inc/rm-gpu-ops.h
@@ -83,7 +83,7 @@ NV_STATUS  NV_API_CALL rm_gpu_ops_destroy_access_cntr_info(nvidia_stack_t *, nvg
 NV_STATUS  NV_API_CALL rm_gpu_ops_own_access_cntr_intr(nvidia_stack_t *, nvgpuSessionHandle_t, nvgpuAccessCntrInfo_t, NvBool);
 NV_STATUS  NV_API_CALL rm_gpu_ops_enable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t, const nvgpuAccessCntrConfig_t *);
 NV_STATUS  NV_API_CALL rm_gpu_ops_disable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t);
-NV_STATUS  NV_API_CALL  rm_gpu_ops_set_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, unsigned, NvBool, NvU32);
+NV_STATUS  NV_API_CALL  rm_gpu_ops_set_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, unsigned, NvBool, NvU32, NvU64 *);
 NV_STATUS  NV_API_CALL  rm_gpu_ops_unset_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t);
 NV_STATUS  NV_API_CALL rm_gpu_ops_get_nvlink_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuNvlinkInfo_t);
 NV_STATUS  NV_API_CALL rm_gpu_ops_p2p_object_create(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuDeviceHandle_t, NvHandle *);
--- a/kernel-open/conftest.sh
+++ b/kernel-open/conftest.sh
--- a/kernel-open/header-presence-tests.mk
+++ b/kernel-open/header-presence-tests.mk
@@ -4,108 +4,40 @@ NV_HEADER_PRESENCE_TESTS = \
  asm/system.h \
  drm/drmP.h \
  drm/drm_aperture.h \
-  drm/drm_auth.h \
-  drm/drm_gem.h \
-  drm/drm_crtc.h \
-  drm/drm_color_mgmt.h \
-  drm/drm_atomic.h \
-  drm/drm_atomic_helper.h \
  drm/drm_atomic_state_helper.h \
-  drm/drm_encoder.h \
  drm/drm_atomic_uapi.h \
-  drm/drm_drv.h \
  drm/drm_fbdev_generic.h \
  drm/drm_fbdev_ttm.h \
  drm/drm_client_setup.h \
-  drm/drm_framebuffer.h \
-  drm/drm_connector.h \
  drm/drm_probe_helper.h \
-  drm/drm_blend.h \
-  drm/drm_fourcc.h \
-  drm/drm_prime.h \
-  drm/drm_plane.h \
-  drm/drm_vblank.h \
-  drm/drm_file.h \
-  drm/drm_ioctl.h \
-  drm/drm_device.h \
-  drm/drm_mode_config.h \
-  drm/drm_modeset_lock.h \
-  drm/drm_property.h \
  drm/clients/drm_client_setup.h \
  dt-bindings/interconnect/tegra_icc_id.h \
  generated/autoconf.h \
  generated/compile.h \
  generated/utsrelease.h \
+  linux/pfn_t.h \
  linux/aperture.h \
  linux/dma-direct.h \
-  linux/efi.h \
-  linux/kconfig.h \
  linux/platform/tegra/mc_utils.h \
-  linux/printk.h \
-  linux/ratelimit.h \
-  linux/prio_tree.h \
-  linux/log2.h \
-  linux/of.h \
-  linux/bug.h \
-  linux/sched.h \
-  linux/sched/mm.h \
-  linux/sched/signal.h \
-  linux/sched/task.h \
-  linux/sched/task_stack.h \
  xen/ioemu.h \
  linux/fence.h \
-  linux/dma-fence.h \
  linux/dma-resv.h \
-  soc/tegra/chip-id.h \
-  soc/tegra/fuse.h \
-  soc/tegra/fuse-helper.h \
  soc/tegra/tegra_bpmp.h \
-  video/nv_internal.h \
  linux/platform/tegra/dce/dce-client-ipc.h \
  linux/nvhost.h \
  linux/nvhost_t194.h \
  linux/host1x-next.h \
-  asm/book3s/64/hash-64k.h \
  asm/set_memory.h \
-  asm/prom.h \
-  asm/powernv.h \
-  linux/atomic.h \
-  asm/barrier.h \
-  asm/opal-api.h \
-  sound/hdaudio.h \
  asm/pgtable_types.h \
-  asm/page.h \
-  linux/stringhash.h \
  linux/dma-map-ops.h \
-  rdma/peer_mem.h \
  sound/hda_codec.h \
-  linux/dma-buf.h \
-  linux/time.h \
-  linux/platform_device.h \
-  linux/mutex.h \
-  linux/reset.h \
-  linux/of_platform.h \
-  linux/of_device.h \
-  linux/of_gpio.h \
-  linux/gpio.h \
-  linux/gpio/consumer.h \
  linux/interconnect.h \
-  linux/pm_runtime.h \
-  linux/clk.h \
-  linux/clk-provider.h \
  linux/ioasid.h \
  linux/stdarg.h \
  linux/iosys-map.h \
-  asm/coco.h \
  linux/vfio_pci_core.h \
-  linux/mdev.h \
-  soc/tegra/bpmp-abi.h \
-  soc/tegra/bpmp.h \
-  linux/sync_file.h \
  linux/cc_platform.h \
-  asm/cpufeature.h \
-  linux/mpi.h \
+  linux/slub_def.h \
  asm/mshyperv.h \
-  crypto/sig.h \
-  linux/pfn_t.h
+  crypto/sig.h

--- a/kernel-open/nvidia-drm/nv-kthread-q.c
+++ b/kernel-open/nvidia-drm/nv-kthread-q.c
@@ -29,12 +29,7 @@
 #include <linux/completion.h>
 #include <linux/module.h>
 #include <linux/mm.h>
-
-#if defined(NV_LINUX_BUG_H_PRESENT)
-    #include <linux/bug.h>
-#else
-    #include <asm/bug.h>
-#endif
+#include <linux/bug.h>

 // Today's implementation is a little simpler and more limited than the
 // API description allows for in nv-kthread-q.h. Details include:
--- a/kernel-open/nvidia-drm/nvidia-dma-fence-helper.h
+++ b/kernel-open/nvidia-drm/nvidia-dma-fence-helper.h
@@ -1,156 +0,0 @@
-/*
- * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef __NVIDIA_DMA_FENCE_HELPER_H__
-#define __NVIDIA_DMA_FENCE_HELPER_H__
-
-#include "nvidia-drm-conftest.h"
-
-#if defined(NV_DRM_FENCE_AVAILABLE)
-
-/*
- * Fence headers are moved to file dma-fence.h and struct fence has
- * been renamed to dma_fence by commit -
- *
- *      2016-10-25 : f54d1867005c3323f5d8ad83eed823e84226c429
- */
-
-#if defined(NV_LINUX_FENCE_H_PRESENT)
-#include <linux/fence.h>
-#else
-#include <linux/dma-fence.h>
-#endif
-
-#if defined(NV_LINUX_FENCE_H_PRESENT)
-typedef struct fence nv_dma_fence_t;
-typedef struct fence_ops nv_dma_fence_ops_t;
-typedef struct fence_cb nv_dma_fence_cb_t;
-typedef fence_func_t nv_dma_fence_func_t;
-#else
-typedef struct dma_fence nv_dma_fence_t;
-typedef struct dma_fence_ops nv_dma_fence_ops_t;
-typedef struct dma_fence_cb nv_dma_fence_cb_t;
-typedef dma_fence_func_t nv_dma_fence_func_t;
-#endif
-
-#if defined(NV_LINUX_FENCE_H_PRESENT)
-#define NV_DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT FENCE_FLAG_ENABLE_SIGNAL_BIT
-#else
-#define NV_DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT
-#endif
-
-static inline bool nv_dma_fence_is_signaled(nv_dma_fence_t *fence) {
-#if defined(NV_LINUX_FENCE_H_PRESENT)
-    return fence_is_signaled(fence);
-#else
-    return dma_fence_is_signaled(fence);
-#endif
-}
-
-static inline nv_dma_fence_t *nv_dma_fence_get(nv_dma_fence_t *fence)
-{
-#if defined(NV_LINUX_FENCE_H_PRESENT)
-    return fence_get(fence);
-#else
-    return dma_fence_get(fence);
-#endif
-}
-
-static inline void nv_dma_fence_put(nv_dma_fence_t *fence) {
-#if defined(NV_LINUX_FENCE_H_PRESENT)
-    fence_put(fence);
-#else
-    dma_fence_put(fence);
-#endif
-}
-
-static inline signed long
-nv_dma_fence_default_wait(nv_dma_fence_t *fence,
-                          bool intr, signed long timeout) {
-#if defined(NV_LINUX_FENCE_H_PRESENT)
-    return fence_default_wait(fence, intr, timeout);
-#else
-    return dma_fence_default_wait(fence, intr, timeout);
-#endif
-}
-
-static inline int nv_dma_fence_signal(nv_dma_fence_t *fence) {
-#if defined(NV_LINUX_FENCE_H_PRESENT)
-    return fence_signal(fence);
-#else
-    return dma_fence_signal(fence);
-#endif
-}
-
-static inline int nv_dma_fence_signal_locked(nv_dma_fence_t *fence) {
-#if defined(NV_LINUX_FENCE_H_PRESENT)
-    return fence_signal_locked(fence);
-#else
-    return dma_fence_signal_locked(fence);
-#endif
-}
-
-static inline u64 nv_dma_fence_context_alloc(unsigned num) {
-#if defined(NV_LINUX_FENCE_H_PRESENT)
-    return fence_context_alloc(num);
-#else
-    return dma_fence_context_alloc(num);
-#endif
-}
-
-static inline void
-nv_dma_fence_init(nv_dma_fence_t *fence,
-                  const nv_dma_fence_ops_t *ops,
-                  spinlock_t *lock, u64 context, uint64_t seqno) {
-#if defined(NV_LINUX_FENCE_H_PRESENT)
-    fence_init(fence, ops, lock, context, seqno);
-#else
-    dma_fence_init(fence, ops, lock, context, seqno);
-#endif
-}
-
-static inline void
-nv_dma_fence_set_error(nv_dma_fence_t *fence,
-                       int error) {
-#if defined(NV_DMA_FENCE_SET_ERROR_PRESENT)
-    return dma_fence_set_error(fence, error);
-#elif defined(NV_FENCE_SET_ERROR_PRESENT)
-    return fence_set_error(fence, error);
-#else
-    fence->status = error;
-#endif
-}
-
-static inline int
-nv_dma_fence_add_callback(nv_dma_fence_t *fence,
-                          nv_dma_fence_cb_t *cb,
-                          nv_dma_fence_func_t func) {
-#if defined(NV_LINUX_FENCE_H_PRESENT)
-    return fence_add_callback(fence, cb, func);
-#else
-    return dma_fence_add_callback(fence, cb, func);
-#endif
-}
-
-#endif /* defined(NV_DRM_FENCE_AVAILABLE) */
-
-#endif /* __NVIDIA_DMA_FENCE_HELPER_H__ */
--- a/kernel-open/nvidia-drm/nvidia-dma-resv-helper.h
+++ b/kernel-open/nvidia-drm/nvidia-dma-resv-helper.h
@@ -25,8 +25,6 @@

 #include "nvidia-drm-conftest.h"

-#if defined(NV_DRM_FENCE_AVAILABLE)
-
 /*
 * linux/reservation.h is renamed to linux/dma-resv.h, by commit
 * 52791eeec1d9 (dma-buf: rename reservation_object to dma_resv)
@@ -39,7 +37,7 @@
 #include <linux/reservation.h>
 #endif

-#include <nvidia-dma-fence-helper.h>
+#include <linux/dma-fence.h>

 #if defined(NV_LINUX_DMA_RESV_H_PRESENT)
 typedef struct dma_resv nv_dma_resv_t;
@@ -108,7 +106,7 @@ static inline int nv_dma_resv_reserve_fences(nv_dma_resv_t *obj,
 }

 static inline void nv_dma_resv_add_excl_fence(nv_dma_resv_t *obj,
-                                              nv_dma_fence_t *fence)
+                                              struct dma_fence *fence)
 {
 #if defined(NV_LINUX_DMA_RESV_H_PRESENT)
 #if defined(NV_DMA_RESV_ADD_FENCE_PRESENT)
@@ -122,7 +120,7 @@ static inline void nv_dma_resv_add_excl_fence(nv_dma_resv_t *obj,
 }

 static inline void nv_dma_resv_add_shared_fence(nv_dma_resv_t *obj,
-                                                nv_dma_fence_t *fence)
+                                                struct dma_fence *fence)
 {
 #if defined(NV_LINUX_DMA_RESV_H_PRESENT)
 #if defined(NV_DMA_RESV_ADD_FENCE_PRESENT)
@@ -135,6 +133,4 @@ static inline void nv_dma_resv_add_shared_fence(nv_dma_resv_t *obj,
 #endif
 }

-#endif /* defined(NV_DRM_FENCE_AVAILABLE) */
-
 #endif /* __NVIDIA_DMA_RESV_HELPER_H__ */
--- a/kernel-open/nvidia-drm/nvidia-drm-conftest.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-conftest.h
@@ -55,11 +55,24 @@

 #endif

-#if defined(NV_DRM_DRIVER_HAS_GEM_PRIME_RES_OBJ) || \
-    defined(NV_DRM_GEM_OBJECT_HAS_RESV)
-#define NV_DRM_FENCE_AVAILABLE
-#else
-#undef NV_DRM_FENCE_AVAILABLE
+#include <linux/kconfig.h> // for IS_ENABLED()
+
+#if IS_ENABLED(CONFIG_DRM) || defined(__FreeBSD__)
+#define NV_DRM_AVAILABLE
+#endif
+
+#if defined(NV_DRM_FBDEV_GENERIC_SETUP_PRESENT) &&                             \
+    defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PRESENT)
+#define NV_DRM_FBDEV_AVAILABLE
+#define NV_DRM_FBDEV_GENERIC_AVAILABLE
+#endif
+
+#if defined(NV_DRM_FBDEV_TTM_SETUP_PRESENT) &&                                 \
+    defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PRESENT)
+#if IS_ENABLED(CONFIG_DRM_TTM_HELPER)
+#define NV_DRM_FBDEV_AVAILABLE
+#define NV_DRM_FBDEV_TTM_AVAILABLE
+#endif
 #endif

 #if defined(NV_DRM_CLIENT_SETUP_PRESENT) &&                                    \
@@ -73,17 +86,6 @@
 #endif
 #endif

-/*
- * We can support color management if either drm_helper_crtc_enable_color_mgmt()
- * or drm_crtc_enable_color_mgmt() exist.
- */
-#if defined(NV_DRM_HELPER_CRTC_ENABLE_COLOR_MGMT_PRESENT) || \
-    defined(NV_DRM_CRTC_ENABLE_COLOR_MGMT_PRESENT)
-#define NV_DRM_COLOR_MGMT_AVAILABLE
-#else
-#undef NV_DRM_COLOR_MGMT_AVAILABLE
-#endif
-
 /*
 * Adapt to quirks in FreeBSD's Linux kernel compatibility layer.
 */
--- a/kernel-open/nvidia-drm/nvidia-drm-connector.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-connector.c
@@ -20,9 +20,9 @@
 * DEALINGS IN THE SOFTWARE.
 */

-#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#include "nvidia-drm-conftest.h" /* NV_DRM_AVAILABLE */

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #include "nvidia-drm-helper.h"
 #include "nvidia-drm-priv.h"
@@ -228,9 +228,6 @@ nv_drm_connector_detect(struct drm_connector *connector, bool force)
 }

 static struct drm_connector_funcs nv_connector_funcs = {
-#if defined NV_DRM_ATOMIC_HELPER_CONNECTOR_DPMS_PRESENT
-    .dpms                   = drm_atomic_helper_connector_dpms,
-#endif
    .destroy                = nv_drm_connector_destroy,
    .reset                  = drm_atomic_helper_connector_reset,
    .force                  = __nv_drm_connector_force,
@@ -314,7 +311,11 @@ static int nv_drm_connector_get_modes(struct drm_connector *connector)
 }

 static int nv_drm_connector_mode_valid(struct drm_connector    *connector,
+#if defined(NV_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_HAS_CONST_MODE_ARG)
+                                       const struct drm_display_mode *mode)
+#else
                                       struct drm_display_mode *mode)
+#endif
 {
    struct drm_device *dev = connector->dev;
    struct nv_drm_device *nv_dev = to_nv_device(dev);
@@ -584,16 +585,11 @@ nv_drm_get_connector(struct drm_device *dev,
                     char dpAddress[NVKMS_DP_ADDRESS_STRING_LENGTH])
 {
    struct drm_connector *connector = NULL;
-#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT)
    struct drm_connector_list_iter conn_iter;
-    nv_drm_connector_list_iter_begin(dev, &conn_iter);
-#else
-    struct drm_mode_config *config = &dev->mode_config;
-    mutex_lock(&config->mutex);
-#endif
+    drm_connector_list_iter_begin(dev, &conn_iter);

    /* Lookup for existing connector with same physical index */
-    nv_drm_for_each_connector(connector, &conn_iter, dev) {
+    drm_for_each_connector_iter(connector, &conn_iter) {
        struct nv_drm_connector *nv_connector = to_nv_connector(connector);

        if (nv_connector->physicalIndex == physicalIndex) {
@@ -608,11 +604,7 @@ nv_drm_get_connector(struct drm_device *dev,
    connector = NULL;

 done:
-#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT)
-    nv_drm_connector_list_iter_end(&conn_iter);
-#else
-    mutex_unlock(&config->mutex);
-#endif
+    drm_connector_list_iter_end(&conn_iter);

    if (!connector) {
        connector = nv_drm_connector_new(dev,
--- a/kernel-open/nvidia-drm/nvidia-drm-connector.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-connector.h
@@ -25,15 +25,13 @@

 #include "nvidia-drm-conftest.h"

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #if defined(NV_DRM_DRMP_H_PRESENT)
 #include <drm/drmP.h>
 #endif

-#if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT)
 #include <drm/drm_connector.h>
-#endif

 #include "nvtypes.h"
 #include "nvkms-api-types.h"
@@ -101,6 +99,6 @@ nv_drm_get_connector(struct drm_device *dev,
 bool nv_drm_connector_revoke_permissions(struct drm_device *dev,
                                         struct nv_drm_connector *nv_connector);

-#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#endif /* NV_DRM_AVAILABLE */

 #endif /* __NVIDIA_DRM_CONNECTOR_H__ */
--- a/kernel-open/nvidia-drm/nvidia-drm-crtc.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-crtc.c
@@ -20,9 +20,9 @@
 * DEALINGS IN THE SOFTWARE.
 */

-#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#include "nvidia-drm-conftest.h" /* NV_DRM_AVAILABLE */

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #include "nvidia-drm-helper.h"
 #include "nvidia-drm-priv.h"
@@ -42,10 +42,7 @@

 #include <drm/drm_atomic.h>
 #include <drm/drm_atomic_helper.h>
-
-#if defined(NV_DRM_DRM_COLOR_MGMT_H_PRESENT)
 #include <drm/drm_color_mgmt.h>
-#endif

 /*
 * The two arrays below specify the PQ EOTF transfer function that's used to
@@ -150,15 +147,15 @@ nv_drm_atomic_replace_property_blob_from_id(struct drm_device *dev,

        if ((expected_size > 0) &&
            (new_blob->length != expected_size)) {
-            nv_drm_property_blob_put(new_blob);
+            drm_property_blob_put(new_blob);
            return -EINVAL;
        }
    }

    if (old_blob != new_blob) {
-        nv_drm_property_blob_put(old_blob);
+        drm_property_blob_put(old_blob);
        if (new_blob) {
-            nv_drm_property_blob_get(new_blob);
+            drm_property_blob_get(new_blob);
        }
        *blob = new_blob;
        *replaced = true;
@@ -166,7 +163,7 @@ nv_drm_atomic_replace_property_blob_from_id(struct drm_device *dev,
        *replaced = false;
    }

-    nv_drm_property_blob_put(new_blob);
+    drm_property_blob_put(new_blob);

    return 0;
 }
@@ -204,6 +201,15 @@ plane_req_config_disable(struct NvKmsKapiLayerRequestedConfig *req_config)
    req_config->flags.srcWHChanged = NV_TRUE;
    req_config->flags.dstXYChanged = NV_TRUE;
    req_config->flags.dstWHChanged = NV_TRUE;
+    req_config->flags.cscChanged = NV_TRUE;
+    req_config->flags.inputTfChanged = NV_TRUE;
+    req_config->flags.outputTfChanged = NV_TRUE;
+    req_config->flags.inputColorSpaceChanged = NV_TRUE;
+    req_config->flags.inputColorRangeChanged = NV_TRUE;
+    req_config->flags.hdrMetadataChanged = NV_TRUE;
+    req_config->flags.matrixOverridesChanged = NV_TRUE;
+    req_config->flags.ilutChanged = NV_TRUE;
+    req_config->flags.tmoChanged = NV_TRUE;
 }

 static inline void
@@ -244,7 +250,6 @@ static NvU64 ctm_val_to_csc_val(NvU64 ctm_val)
    return csc_val;
 }

-#if defined(NV_DRM_COLOR_MGMT_AVAILABLE)
 static void ctm_to_csc(struct NvKmsCscMatrix *nvkms_csc,
                       struct drm_color_ctm  *drm_ctm)
 {
@@ -261,7 +266,6 @@ static void ctm_to_csc(struct NvKmsCscMatrix *nvkms_csc,
        }
    }
 }
-#endif /* NV_DRM_COLOR_MGMT_AVAILABLE */

 static void ctm_3x4_to_csc(struct NvKmsCscMatrix    *nvkms_csc,
                           struct drm_color_ctm_3x4 *drm_ctm_3x4)
@@ -372,23 +376,82 @@ cursor_plane_req_config_update(struct drm_plane *plane,
        old_config.dstY != req_config->dstY;
 }

-static void free_drm_lut_surface(struct kref *ref)
+static void release_drm_nvkms_surface(struct nv_drm_nvkms_surface *drm_nvkms_surface)
 {
-    struct nv_drm_lut_surface *drm_lut_surface =
-        container_of(ref, struct nv_drm_lut_surface, refcount);
-    struct NvKmsKapiDevice *pDevice = drm_lut_surface->pDevice;
+    struct NvKmsKapiDevice *pDevice = drm_nvkms_surface->pDevice;

-    BUG_ON(drm_lut_surface->nvkms_surface == NULL);
-    BUG_ON(drm_lut_surface->nvkms_memory == NULL);
-    BUG_ON(drm_lut_surface->buffer == NULL);
+    BUG_ON(drm_nvkms_surface->nvkms_surface == NULL);
+    BUG_ON(drm_nvkms_surface->nvkms_memory == NULL);
+    BUG_ON(drm_nvkms_surface->buffer == NULL);

-    nvKms->destroySurface(pDevice, drm_lut_surface->nvkms_surface);
-    nvKms->unmapMemory(pDevice, drm_lut_surface->nvkms_memory,
+    nvKms->destroySurface(pDevice, drm_nvkms_surface->nvkms_surface);
+    nvKms->unmapMemory(pDevice, drm_nvkms_surface->nvkms_memory,
                       NVKMS_KAPI_MAPPING_TYPE_KERNEL,
-                       drm_lut_surface->buffer);
-    nvKms->freeMemory(pDevice, drm_lut_surface->nvkms_memory);
+                       drm_nvkms_surface->buffer);
+    nvKms->freeMemory(pDevice, drm_nvkms_surface->nvkms_memory);
+}

-    nv_drm_free(drm_lut_surface);
+static int init_drm_nvkms_surface(struct nv_drm_device *nv_dev,
+    struct nv_drm_nvkms_surface *drm_nvkms_surface,
+    struct nv_drm_nvkms_surface_params *surface_params)
+{
+    struct NvKmsKapiDevice *pDevice = nv_dev->pDevice;
+    NvU8 compressible = 0; // No compression
+
+    struct NvKmsKapiAllocateMemoryParams allocParams = {
+        .layout         = NvKmsSurfaceMemoryLayoutPitch,
+        .type           = NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT,
+        .size           = surface_params->surface_size,
+        .useVideoMemory = nv_dev->hasVideoMemory,
+        .compressible   = &compressible,
+    };
+
+    struct NvKmsKapiCreateSurfaceParams params = {};
+    struct NvKmsKapiMemory *surface_mem;
+    struct NvKmsKapiSurface *surface;
+    void *buffer;
+
+    params.format = surface_params->format;
+    params.width = surface_params->width;
+    params.height = surface_params->height;
+
+    /* Allocate displayable memory. */
+    surface_mem = nvKms->allocateMemory(nv_dev->pDevice, &allocParams);
+    if (surface_mem == NULL) {
+        return -ENOMEM;
+    }
+
+    /* Map memory in order to populate it. */
+    if (!nvKms->mapMemory(pDevice, surface_mem,
+                          NVKMS_KAPI_MAPPING_TYPE_KERNEL,
+                          &buffer)) {
+        nvKms->freeMemory(pDevice, surface_mem);
+        return -ENOMEM;
+    }
+
+    params.planes[0].memory = surface_mem;
+    params.planes[0].offset = 0;
+    params.planes[0].pitch = surface_params->surface_size;
+
+    /* Create surface. */
+    surface = nvKms->createSurface(pDevice, &params);
+    if (surface == NULL) {
+        nvKms->unmapMemory(pDevice, surface_mem,
+                           NVKMS_KAPI_MAPPING_TYPE_KERNEL, buffer);
+        nvKms->freeMemory(pDevice, surface_mem);
+        return -ENOMEM;
+    }
+
+    /* Pack into struct nv_drm_nvkms_surface. */
+    drm_nvkms_surface->pDevice = pDevice;
+    drm_nvkms_surface->nvkms_memory = surface_mem;
+    drm_nvkms_surface->nvkms_surface = surface;
+    drm_nvkms_surface->buffer = buffer;
+
+    /* Init refcount. */
+    kref_init(&drm_nvkms_surface->refcount);
+
+    return 0;
 }

 static struct nv_drm_lut_surface *alloc_drm_lut_surface(
@@ -399,86 +462,49 @@ static struct nv_drm_lut_surface *alloc_drm_lut_surface(
    NvU32 num_vss_header_entries,
    NvU32 num_entries)
 {
-    struct NvKmsKapiDevice *pDevice = nv_dev->pDevice;
    struct nv_drm_lut_surface *drm_lut_surface;
-    NvU8 compressible = 0; // No compression
-    size_t size =
+    const size_t surface_size =
        (((num_vss_header_entries + num_entries) *
          NVKMS_LUT_CAPS_LUT_ENTRY_SIZE) + 255) & ~255; // 256-byte aligned

-    struct NvKmsKapiMemory *surface_mem;
-    struct NvKmsKapiSurface *surface;
-    struct NvKmsKapiCreateSurfaceParams params = {};
-    NvU16 *lut_data;
+    struct nv_drm_nvkms_surface_params params = {};

-    /* Allocate displayable memory. */
-    if (nv_dev->hasVideoMemory) {
-        surface_mem =
-            nvKms->allocateVideoMemory(pDevice,
-                                       NvKmsSurfaceMemoryLayoutPitch,
-                                       NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT,
-                                       size,
-                                       &compressible);
-    } else {
-        surface_mem =
-            nvKms->allocateSystemMemory(pDevice,
-                                        NvKmsSurfaceMemoryLayoutPitch,
-                                        NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT,
-                                        size,
-                                        &compressible);
-    }
-    if (surface_mem == NULL) {
-        return NULL;
-    }
-
-    /* Map memory in order to populate it. */
-    if (!nvKms->mapMemory(pDevice, surface_mem,
-                          NVKMS_KAPI_MAPPING_TYPE_KERNEL,
-                          (void **) &lut_data)) {
-        nvKms->freeMemory(pDevice, surface_mem);
-        return NULL;
-    }
-
-    /* Create surface. */
    params.format = NvKmsSurfaceMemoryFormatR16G16B16A16;
    params.width = num_vss_header_entries + num_entries;
    params.height = 1;
-    params.planes[0].memory = surface_mem;
-    params.planes[0].offset = 0;
-    params.planes[0].pitch = size;
+    params.surface_size = surface_size;

-    surface = nvKms->createSurface(pDevice, &params);
-    if (surface == NULL) {
-        nvKms->unmapMemory(pDevice, surface_mem,
-                           NVKMS_KAPI_MAPPING_TYPE_KERNEL, (void *) lut_data);
-        nvKms->freeMemory(pDevice, surface_mem);
-        return NULL;
-    }
-
-    /* Pack into struct nv_drm_lut_surface. */
    drm_lut_surface = nv_drm_calloc(1, sizeof(struct nv_drm_lut_surface));
    if (drm_lut_surface == NULL) {
-        nvKms->destroySurface(pDevice, surface);
-        nvKms->unmapMemory(pDevice, surface_mem,
-                           NVKMS_KAPI_MAPPING_TYPE_KERNEL, (void *) lut_data);
-        nvKms->freeMemory(pDevice, surface_mem);
        return NULL;
    }
-    drm_lut_surface->pDevice = pDevice;
-    drm_lut_surface->nvkms_memory = surface_mem;
-    drm_lut_surface->nvkms_surface = surface;
-    drm_lut_surface->buffer = lut_data;
+
+    if (init_drm_nvkms_surface(nv_dev, &drm_lut_surface->base, &params) != 0) {
+        nv_drm_free(drm_lut_surface);
+        return NULL;
+    }
+
    drm_lut_surface->properties.vssSegments = num_vss_header_segments;
    drm_lut_surface->properties.vssType = vss_type;
    drm_lut_surface->properties.lutEntries = num_entries;
    drm_lut_surface->properties.entryFormat = entry_format;

-    /* Init refcount. */
-    kref_init(&drm_lut_surface->refcount);
-
    return drm_lut_surface;
 }

+static void free_drm_lut_surface(struct kref *ref)
+{
+    struct nv_drm_nvkms_surface *drm_nvkms_surface =
+        container_of(ref, struct nv_drm_nvkms_surface, refcount);
+    struct nv_drm_lut_surface *drm_lut_surface =
+        container_of(drm_nvkms_surface, struct nv_drm_lut_surface, base);
+
+    // Clean up base
+    release_drm_nvkms_surface(drm_nvkms_surface);
+
+    nv_drm_free(drm_lut_surface);
+}
+
 static NvU32 fp32_lut_interp(
    NvU16 entry0,
    NvU16 entry1,
@@ -582,7 +608,7 @@ static struct nv_drm_lut_surface *create_drm_ilut_surface_vss(
        return NULL;
    }

-    lut_data = (NvU16 *) drm_lut_surface->buffer;
+    lut_data = (NvU16 *) drm_lut_surface->base.buffer;

    /* Calculate VSS header. */
    if (vss_header_seg_sizes != NULL) {
@@ -733,7 +759,7 @@ static struct nv_drm_lut_surface *create_drm_ilut_surface_legacy(
        return NULL;
    }

-    lut_data = (NvU16 *) drm_lut_surface->buffer;
+    lut_data = (NvU16 *) drm_lut_surface->base.buffer;

    /* Fill LUT surface. */
    for (entry_idx = 0; entry_idx < NVKMS_LUT_ARRAY_SIZE; entry_idx++) {
@@ -799,7 +825,7 @@ static struct nv_drm_lut_surface *create_drm_tmo_surface(
        return NULL;
    }

-    lut_data = (NvU16 *) drm_lut_surface->buffer;
+    lut_data = (NvU16 *) drm_lut_surface->base.buffer;

    /* Calculate linear VSS header. */
    for (entry_idx = 0; entry_idx < NUM_VSS_HEADER_ENTRIES; entry_idx++) {
@@ -901,7 +927,7 @@ static struct nv_drm_lut_surface *create_drm_olut_surface_vss(
        return NULL;
    }

-    lut_data = (NvU16 *) drm_lut_surface->buffer;
+    lut_data = (NvU16 *) drm_lut_surface->base.buffer;

    /* Calculate VSS header. */
    if (vss_header_seg_sizes != NULL) {
@@ -1021,7 +1047,7 @@ static struct nv_drm_lut_surface *create_drm_olut_surface_legacy(
        return NULL;
    }

-    lut_data = (NvU16 *) drm_lut_surface->buffer;
+    lut_data = (NvU16 *) drm_lut_surface->base.buffer;

    /* Fill LUT surface. */
    for (entry_idx = 0; entry_idx < NVKMS_LUT_ARRAY_SIZE; entry_idx++) {
@@ -1057,6 +1083,74 @@ update_matrix_override(struct drm_property_blob *blob,
    return enabled;
 }

+static enum NvKmsInputColorSpace nv_get_nvkms_input_colorspace(
+    enum nv_drm_input_color_space colorSpace)
+{
+    switch (colorSpace) {
+        case NV_DRM_INPUT_COLOR_SPACE_NONE:
+            return NVKMS_INPUT_COLOR_SPACE_NONE;
+        case NV_DRM_INPUT_COLOR_SPACE_SCRGB_LINEAR:
+            return NVKMS_INPUT_COLOR_SPACE_BT709;
+        case NV_DRM_INPUT_COLOR_SPACE_BT2100_PQ:
+            return NVKMS_INPUT_COLOR_SPACE_BT2100;
+        default:
+            /* We shouldn't hit this */
+            WARN_ON("Unsupported input colorspace");
+            return NVKMS_INPUT_COLOR_SPACE_NONE;
+    }
+}
+
+static enum NvKmsInputTf nv_get_nvkms_input_tf(
+    enum nv_drm_input_color_space colorSpace)
+{
+    switch (colorSpace) {
+        case NV_DRM_INPUT_COLOR_SPACE_NONE:
+            return NVKMS_INPUT_TF_LINEAR;
+        case NV_DRM_INPUT_COLOR_SPACE_SCRGB_LINEAR:
+            return NVKMS_INPUT_TF_LINEAR;
+        case NV_DRM_INPUT_COLOR_SPACE_BT2100_PQ:
+            return NVKMS_INPUT_TF_PQ;
+        default:
+            /* We shouldn't hit this */
+            WARN_ON("Unsupported input colorspace");
+            return NVKMS_INPUT_TF_LINEAR;
+    }
+}
+
+#if defined(NV_DRM_PLANE_CREATE_COLOR_PROPERTIES_PRESENT)
+static enum NvKmsInputColorSpace nv_drm_color_encoding_to_nvkms_colorspace(
+    enum drm_color_encoding color_encoding)
+{
+    switch(color_encoding) {
+        case DRM_COLOR_YCBCR_BT601:
+            return NVKMS_INPUT_COLOR_SPACE_BT601;
+        case DRM_COLOR_YCBCR_BT709:
+            return NVKMS_INPUT_COLOR_SPACE_BT709;
+        case DRM_COLOR_YCBCR_BT2020:
+            return NVKMS_INPUT_COLOR_SPACE_BT2020;
+        default:
+            /* We shouldn't hit this */
+            WARN_ON("Unsupported DRM color_encoding");
+            return NVKMS_INPUT_COLOR_SPACE_NONE;
+    }
+}
+
+static enum NvKmsInputColorRange nv_drm_color_range_to_nvkms_color_range(
+    enum drm_color_range color_range)
+{
+    switch(color_range) {
+        case DRM_COLOR_YCBCR_FULL_RANGE:
+            return NVKMS_INPUT_COLOR_RANGE_FULL;
+        case DRM_COLOR_YCBCR_LIMITED_RANGE:
+            return NVKMS_INPUT_COLOR_RANGE_LIMITED;
+        default:
+            /* We shouldn't hit this */
+            WARN_ON("Unsupported DRM color_range");
+            return NVKMS_INPUT_COLOR_RANGE_DEFAULT;
+    }
+}
+#endif
+
 static int
 plane_req_config_update(struct drm_plane *plane,
                        struct drm_plane_state *plane_state,
@@ -1091,7 +1185,6 @@ plane_req_config_update(struct drm_plane *plane,

    req_config->config.csc = old_config.csc;

-#if defined(NV_DRM_ROTATION_AVAILABLE)
    /*
     * plane_state->rotation is only valid when plane->rotation_property
     * is non-NULL.
@@ -1129,7 +1222,6 @@ plane_req_config_update(struct drm_plane *plane,
                break;
        }
    }
-#endif

 #if defined(NV_DRM_ALPHA_BLENDING_AVAILABLE)
    if (plane->blend_mode_property != NULL && plane->alpha_property != NULL) {
@@ -1190,8 +1282,37 @@ plane_req_config_update(struct drm_plane *plane,
        nv_plane->defaultCompositionMode;
 #endif

-    req_config->config.inputColorSpace =
-        nv_drm_plane_state->input_colorspace;
+#if defined(NV_DRM_PLANE_CREATE_COLOR_PROPERTIES_PRESENT)
+    if ((nv_drm_plane_state->input_colorspace == NV_DRM_INPUT_COLOR_SPACE_NONE) &&
+        nv_drm_format_is_yuv(plane_state->fb->format->format)) {
+
+        if (nv_plane->supportsColorProperties) {
+            req_config->config.inputColorSpace =
+                nv_drm_color_encoding_to_nvkms_colorspace(plane_state->color_encoding);
+            req_config->config.inputColorRange =
+                nv_drm_color_range_to_nvkms_color_range(plane_state->color_range);
+        } else {
+            req_config->config.inputColorSpace = NVKMS_INPUT_COLOR_SPACE_NONE;
+            req_config->config.inputColorRange = NVKMS_INPUT_COLOR_RANGE_DEFAULT;
+        }
+        req_config->config.inputTf = NVKMS_INPUT_TF_LINEAR;
+    } else {
+#endif
+        req_config->config.inputColorSpace =
+            nv_get_nvkms_input_colorspace(nv_drm_plane_state->input_colorspace);
+        req_config->config.inputColorRange = NVKMS_INPUT_COLOR_RANGE_DEFAULT;
+        req_config->config.inputTf =
+            nv_get_nvkms_input_tf(nv_drm_plane_state->input_colorspace);
+#if defined(NV_DRM_PLANE_CREATE_COLOR_PROPERTIES_PRESENT)
+    }
+#endif
+
+    req_config->flags.inputTfChanged =
+        (old_config.inputTf != req_config->config.inputTf);
+    req_config->flags.inputColorSpaceChanged =
+        (old_config.inputColorSpace != req_config->config.inputColorSpace);
+    req_config->flags.inputColorRangeChanged =
+        (old_config.inputColorRange != req_config->config.inputColorRange);

    req_config->config.syncParams.preSyncptSpecified = false;
    req_config->config.syncParams.postSyncptRequested = false;
@@ -1240,10 +1361,10 @@ plane_req_config_update(struct drm_plane *plane,

        switch (info_frame->eotf) {
            case HDMI_EOTF_SMPTE_ST2084:
-                req_config->config.tf = NVKMS_OUTPUT_TF_PQ;
+                req_config->config.outputTf = NVKMS_OUTPUT_TF_PQ;
                break;
            case HDMI_EOTF_TRADITIONAL_GAMMA_SDR:
-                req_config->config.tf =
+                req_config->config.outputTf =
                    NVKMS_OUTPUT_TF_TRADITIONAL_GAMMA_SDR;
                break;
            default:
@@ -1254,7 +1375,7 @@ plane_req_config_update(struct drm_plane *plane,
        req_config->config.hdrMetadata.enabled = true;
    } else {
        req_config->config.hdrMetadata.enabled = false;
-        req_config->config.tf = NVKMS_OUTPUT_TF_NONE;
+        req_config->config.outputTf = NVKMS_OUTPUT_TF_NONE;
    }

    req_config->flags.hdrMetadataChanged =
@@ -1264,7 +1385,7 @@ plane_req_config_update(struct drm_plane *plane,
                &req_config->config.hdrMetadata.val,
                sizeof(struct NvKmsHDRStaticMetadata)));

-    req_config->flags.tfChanged = (old_config.tf != req_config->config.tf);
+    req_config->flags.outputTfChanged = (old_config.outputTf != req_config->config.outputTf);
 #endif

    req_config->config.matrixOverrides.enabled.lmsCtm =
@@ -1295,7 +1416,7 @@ plane_req_config_update(struct drm_plane *plane,

    if (nv_drm_plane_state->degamma_changed) {
        if (nv_drm_plane_state->degamma_drm_lut_surface != NULL) {
-            kref_put(&nv_drm_plane_state->degamma_drm_lut_surface->refcount,
+            kref_put(&nv_drm_plane_state->degamma_drm_lut_surface->base.refcount,
                     free_drm_lut_surface);
            nv_drm_plane_state->degamma_drm_lut_surface = NULL;
        }
@@ -1327,7 +1448,7 @@ plane_req_config_update(struct drm_plane *plane,
        if (nv_drm_plane_state->degamma_drm_lut_surface != NULL) {
            req_config->config.ilut.enabled = NV_TRUE;
            req_config->config.ilut.lutSurface =
-                nv_drm_plane_state->degamma_drm_lut_surface->nvkms_surface;
+                nv_drm_plane_state->degamma_drm_lut_surface->base.nvkms_surface;
            req_config->config.ilut.offset = 0;
            req_config->config.ilut.vssSegments =
                nv_drm_plane_state->degamma_drm_lut_surface->properties.vssSegments;
@@ -1346,7 +1467,7 @@ plane_req_config_update(struct drm_plane *plane,

    if (nv_drm_plane_state->tmo_changed) {
        if (nv_drm_plane_state->tmo_drm_lut_surface != NULL) {
-            kref_put(&nv_drm_plane_state->tmo_drm_lut_surface->refcount,
+            kref_put(&nv_drm_plane_state->tmo_drm_lut_surface->base.refcount,
                     free_drm_lut_surface);
            nv_drm_plane_state->tmo_drm_lut_surface = NULL;
        }
@@ -1363,7 +1484,7 @@ plane_req_config_update(struct drm_plane *plane,
        if (nv_drm_plane_state->tmo_drm_lut_surface != NULL) {
            req_config->config.tmo.enabled = NV_TRUE;
            req_config->config.tmo.lutSurface =
-                nv_drm_plane_state->tmo_drm_lut_surface->nvkms_surface;
+                nv_drm_plane_state->tmo_drm_lut_surface->base.nvkms_surface;
            req_config->config.tmo.offset = 0;
            req_config->config.tmo.vssSegments =
                nv_drm_plane_state->tmo_drm_lut_surface->properties.vssSegments;
@@ -1505,7 +1626,6 @@ static int nv_drm_plane_atomic_check(struct drm_plane *plane,
                return ret;
            }

-#if defined(NV_DRM_COLOR_MGMT_AVAILABLE)
            if (crtc_state->color_mgmt_changed) {
                /*
                 * According to the comment in the Linux kernel's
@@ -1521,7 +1641,6 @@ static int nv_drm_plane_atomic_check(struct drm_plane *plane,
                plane_requested_config->config.cscUseMain = NV_FALSE;
                plane_requested_config->flags.cscChanged = NV_TRUE;
            }
-#endif /* NV_DRM_COLOR_MGMT_AVAILABLE */

            if (__is_async_flip_requested(plane, crtc_state)) {
                /*
@@ -1541,7 +1660,6 @@ static int nv_drm_plane_atomic_check(struct drm_plane *plane,
    return 0;
 }

-#if defined(NV_DRM_UNIVERSAL_PLANE_INIT_HAS_FORMAT_MODIFIERS_ARG)
 static bool nv_drm_plane_format_mod_supported(struct drm_plane *plane,
                                              uint32_t format,
                                              uint64_t modifier)
@@ -1549,7 +1667,6 @@ static bool nv_drm_plane_format_mod_supported(struct drm_plane *plane,
    /* All supported modifiers are compatible with all supported formats */
    return true;
 }
-#endif

 static int nv_drm_atomic_crtc_get_property(
    struct drm_crtc *crtc,
@@ -1836,86 +1953,81 @@ nv_drm_plane_atomic_duplicate_state(struct drm_plane *plane)
 #if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA)
    nv_plane_state->hdr_output_metadata = nv_old_plane_state->hdr_output_metadata;
    if (nv_plane_state->hdr_output_metadata) {
-        nv_drm_property_blob_get(nv_plane_state->hdr_output_metadata);
+        drm_property_blob_get(nv_plane_state->hdr_output_metadata);
    }
 #endif

    nv_plane_state->lms_ctm = nv_old_plane_state->lms_ctm;
    if (nv_plane_state->lms_ctm) {
-        nv_drm_property_blob_get(nv_plane_state->lms_ctm);
+        drm_property_blob_get(nv_plane_state->lms_ctm);
    }

    nv_plane_state->lms_to_itp_ctm = nv_old_plane_state->lms_to_itp_ctm;
    if (nv_plane_state->lms_to_itp_ctm) {
-        nv_drm_property_blob_get(nv_plane_state->lms_to_itp_ctm);
+        drm_property_blob_get(nv_plane_state->lms_to_itp_ctm);
    }

    nv_plane_state->itp_to_lms_ctm = nv_old_plane_state->itp_to_lms_ctm;
    if (nv_plane_state->itp_to_lms_ctm) {
-        nv_drm_property_blob_get(nv_plane_state->itp_to_lms_ctm);
+        drm_property_blob_get(nv_plane_state->itp_to_lms_ctm);
    }

    nv_plane_state->blend_ctm = nv_old_plane_state->blend_ctm;
    if (nv_plane_state->blend_ctm) {
-        nv_drm_property_blob_get(nv_plane_state->blend_ctm);
+        drm_property_blob_get(nv_plane_state->blend_ctm);
    }

    nv_plane_state->degamma_tf = nv_old_plane_state->degamma_tf;
    nv_plane_state->degamma_lut = nv_old_plane_state->degamma_lut;
    if (nv_plane_state->degamma_lut) {
-        nv_drm_property_blob_get(nv_plane_state->degamma_lut);
+        drm_property_blob_get(nv_plane_state->degamma_lut);
    }
    nv_plane_state->degamma_multiplier = nv_old_plane_state->degamma_multiplier;
    nv_plane_state->degamma_changed = false;
    nv_plane_state->degamma_drm_lut_surface =
        nv_old_plane_state->degamma_drm_lut_surface;
    if (nv_plane_state->degamma_drm_lut_surface) {
-        kref_get(&nv_plane_state->degamma_drm_lut_surface->refcount);
+        kref_get(&nv_plane_state->degamma_drm_lut_surface->base.refcount);
    }

    nv_plane_state->tmo_lut = nv_old_plane_state->tmo_lut;
    if (nv_plane_state->tmo_lut) {
-        nv_drm_property_blob_get(nv_plane_state->tmo_lut);
+        drm_property_blob_get(nv_plane_state->tmo_lut);
    }
    nv_plane_state->tmo_changed = false;
    nv_plane_state->tmo_drm_lut_surface =
        nv_old_plane_state->tmo_drm_lut_surface;
    if (nv_plane_state->tmo_drm_lut_surface) {
-        kref_get(&nv_plane_state->tmo_drm_lut_surface->refcount);
+        kref_get(&nv_plane_state->tmo_drm_lut_surface->base.refcount);
    }

    return &nv_plane_state->base;
 }

 static inline void __nv_drm_plane_atomic_destroy_state(
-    struct drm_plane *plane,
    struct drm_plane_state *state)
 {
    struct nv_drm_plane_state *nv_drm_plane_state =
        to_nv_drm_plane_state(state);
-#if defined(NV_DRM_ATOMIC_HELPER_PLANE_DESTROY_STATE_HAS_PLANE_ARG)
-    __drm_atomic_helper_plane_destroy_state(plane, state);
-#else
    __drm_atomic_helper_plane_destroy_state(state);
-#endif

 #if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA)
-    nv_drm_property_blob_put(nv_drm_plane_state->hdr_output_metadata);
+    drm_property_blob_put(nv_drm_plane_state->hdr_output_metadata);
 #endif
-    nv_drm_property_blob_put(nv_drm_plane_state->lms_ctm);
-    nv_drm_property_blob_put(nv_drm_plane_state->lms_to_itp_ctm);
-    nv_drm_property_blob_put(nv_drm_plane_state->itp_to_lms_ctm);
-    nv_drm_property_blob_put(nv_drm_plane_state->blend_ctm);
+    drm_property_blob_put(nv_drm_plane_state->lms_ctm);
+    drm_property_blob_put(nv_drm_plane_state->lms_to_itp_ctm);
+    drm_property_blob_put(nv_drm_plane_state->itp_to_lms_ctm);
+    drm_property_blob_put(nv_drm_plane_state->blend_ctm);

-    nv_drm_property_blob_put(nv_drm_plane_state->degamma_lut);
+    drm_property_blob_put(nv_drm_plane_state->degamma_lut);
    if (nv_drm_plane_state->degamma_drm_lut_surface != NULL) {
-        kref_put(&nv_drm_plane_state->degamma_drm_lut_surface->refcount,
+        kref_put(&nv_drm_plane_state->degamma_drm_lut_surface->base.refcount,
                 free_drm_lut_surface);
    }

-    nv_drm_property_blob_put(nv_drm_plane_state->tmo_lut);
+    drm_property_blob_put(nv_drm_plane_state->tmo_lut);
    if (nv_drm_plane_state->tmo_drm_lut_surface != NULL) {
-        kref_put(&nv_drm_plane_state->tmo_drm_lut_surface->refcount,
+        kref_put(&nv_drm_plane_state->tmo_drm_lut_surface->base.refcount,
                 free_drm_lut_surface);
    }
 }
@@ -1924,7 +2036,7 @@ static void nv_drm_plane_atomic_destroy_state(
    struct drm_plane *plane,
    struct drm_plane_state *state)
 {
-    __nv_drm_plane_atomic_destroy_state(plane, state);
+    __nv_drm_plane_atomic_destroy_state(state);

    nv_drm_free(to_nv_drm_plane_state(state));
 }
@@ -1938,9 +2050,7 @@ static const struct drm_plane_funcs nv_plane_funcs = {
    .atomic_set_property    = nv_drm_plane_atomic_set_property,
    .atomic_duplicate_state = nv_drm_plane_atomic_duplicate_state,
    .atomic_destroy_state   = nv_drm_plane_atomic_destroy_state,
-#if defined(NV_DRM_UNIVERSAL_PLANE_INIT_HAS_FORMAT_MODIFIERS_ARG)
    .format_mod_supported   = nv_drm_plane_format_mod_supported,
-#endif
 };

 static const struct drm_plane_helper_funcs nv_plane_helper_funcs = {
@@ -1956,17 +2066,6 @@ static void nv_drm_crtc_destroy(struct drm_crtc *crtc)
    nv_drm_free(nv_crtc);
 }

-static inline void
-__nv_drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc,
-                                          struct drm_crtc_state *crtc_state)
-{
-#if defined(NV_DRM_ATOMIC_HELPER_CRTC_DESTROY_STATE_HAS_CRTC_ARG)
-    __drm_atomic_helper_crtc_destroy_state(crtc, crtc_state);
-#else
-    __drm_atomic_helper_crtc_destroy_state(crtc_state);
-#endif
-}
-
 static inline bool nv_drm_crtc_duplicate_req_head_modeset_config(
    const struct NvKmsKapiHeadRequestedConfig *old,
    struct NvKmsKapiHeadRequestedConfig *new)
@@ -2109,11 +2208,11 @@ nv_drm_atomic_crtc_duplicate_state(struct drm_crtc *crtc)
    nv_state->regamma_tf = nv_old_state->regamma_tf;
    nv_state->regamma_lut = nv_old_state->regamma_lut;
    if (nv_state->regamma_lut) {
-        nv_drm_property_blob_get(nv_state->regamma_lut);
+        drm_property_blob_get(nv_state->regamma_lut);
    }
    nv_state->regamma_divisor = nv_old_state->regamma_divisor;
    if (nv_state->regamma_drm_lut_surface) {
-        kref_get(&nv_state->regamma_drm_lut_surface->refcount);
+        kref_get(&nv_state->regamma_drm_lut_surface->base.refcount);
    }
    nv_state->regamma_changed = false;

@@ -2138,11 +2237,11 @@ static void nv_drm_atomic_crtc_destroy_state(struct drm_crtc *crtc,
        nv_state->nv_flip = NULL;
    }

-    __nv_drm_atomic_helper_crtc_destroy_state(crtc, &nv_state->base);
+    __drm_atomic_helper_crtc_destroy_state(&nv_state->base);

-    nv_drm_property_blob_put(nv_state->regamma_lut);
+    drm_property_blob_put(nv_state->regamma_lut);
    if (nv_state->regamma_drm_lut_surface != NULL) {
-        kref_put(&nv_state->regamma_drm_lut_surface->refcount,
+        kref_put(&nv_state->regamma_drm_lut_surface->base.refcount,
                 free_drm_lut_surface);
    }

@@ -2166,21 +2265,6 @@ static struct drm_crtc_funcs nv_crtc_funcs = {
 #endif
 };

-/*
- * In kernel versions before the addition of
- * drm_crtc_state::connectors_changed, connector changes were
- * reflected in drm_crtc_state::mode_changed.
- */
-static inline bool
-nv_drm_crtc_state_connectors_changed(struct drm_crtc_state *crtc_state)
-{
-#if defined(NV_DRM_CRTC_STATE_HAS_CONNECTORS_CHANGED)
-    return crtc_state->connectors_changed;
-#else
-    return crtc_state->mode_changed;
-#endif
-}
-
 static int head_modeset_config_attach_connector(
    struct nv_drm_connector *nv_connector,
    struct NvKmsKapiHeadModeSetConfig *head_modeset_config)
@@ -2197,7 +2281,6 @@ static int head_modeset_config_attach_connector(
    return 0;
 }

-#if defined(NV_DRM_COLOR_MGMT_AVAILABLE)
 static int color_mgmt_config_copy_lut(struct NvKmsLutRamps *nvkms_lut,
                                      struct drm_color_lut *drm_lut,
                                      uint64_t lut_len)
@@ -2309,7 +2392,6 @@ static int color_mgmt_config_set_luts(struct nv_drm_crtc_state *nv_crtc_state,

    return 0;
 }
-#endif /* NV_DRM_COLOR_MGMT_AVAILABLE */

 /**
 * nv_drm_crtc_atomic_check() can fail after it has modified
@@ -2341,7 +2423,7 @@ static int nv_drm_crtc_atomic_check(struct drm_crtc *crtc,
        req_config->flags.modeChanged = NV_TRUE;
    }

-    if (nv_drm_crtc_state_connectors_changed(crtc_state)) {
+    if (crtc_state->connectors_changed) {
        struct NvKmsKapiHeadModeSetConfig *config = &req_config->modeSetConfig;
        struct drm_connector *connector;
        struct drm_connector_state *connector_state;
@@ -2376,17 +2458,15 @@ static int nv_drm_crtc_atomic_check(struct drm_crtc *crtc,
    req_config->modeSetConfig.vrrEnabled = crtc_state->vrr_enabled;
 #endif

-#if defined(NV_DRM_COLOR_MGMT_AVAILABLE)
    if (crtc_state->color_mgmt_changed) {
        if ((ret = color_mgmt_config_set_luts(nv_crtc_state, req_config)) != 0) {
            return ret;
        }
    }
-#endif

    if (nv_crtc_state->regamma_changed) {
        if (nv_crtc_state->regamma_drm_lut_surface != NULL) {
-            kref_put(&nv_crtc_state->regamma_drm_lut_surface->refcount,
+            kref_put(&nv_crtc_state->regamma_drm_lut_surface->base.refcount,
                     free_drm_lut_surface);
            nv_crtc_state->regamma_drm_lut_surface = NULL;
        }
@@ -2417,7 +2497,7 @@ static int nv_drm_crtc_atomic_check(struct drm_crtc *crtc,
        if (nv_crtc_state->regamma_drm_lut_surface != NULL) {
            req_config->modeSetConfig.olut.enabled = NV_TRUE;
            req_config->modeSetConfig.olut.lutSurface =
-                nv_crtc_state->regamma_drm_lut_surface->nvkms_surface;
+                nv_crtc_state->regamma_drm_lut_surface->base.nvkms_surface;
            req_config->modeSetConfig.olut.offset = 0;
            req_config->modeSetConfig.olut.vssSegments =
                nv_crtc_state->regamma_drm_lut_surface->properties.vssSegments;
@@ -2521,7 +2601,7 @@ static void nv_drm_plane_install_properties(
    if (nv_dev->nv_input_colorspace_property) {
        drm_object_attach_property(
            &plane->base, nv_dev->nv_input_colorspace_property,
-            NVKMS_INPUT_COLORSPACE_NONE);
+            NV_DRM_INPUT_COLOR_SPACE_NONE);
    }

    if (supportsICtCp) {
@@ -2531,17 +2611,14 @@ static void nv_drm_plane_install_properties(
                &plane->base, nv_dev->nv_hdr_output_metadata_property, 0);
        }
 #endif
+    }

-        /*
-         * The old DRM_OBJECT_MAX_PROPERTY limit of 24 is too small to
-         * accomodate all of the properties for the ICtCp pipeline.
-         *
-         * Commit 1e13c5644c44 ("drm/drm_mode_object: increase max objects to
-         * accommodate new color props") in Linux v6.8 increased the limit to
-         * 64. To be safe, require this before attaching any properties for the
-         * ICtCp pipeline.
-         */
-        if (DRM_OBJECT_MAX_PROPERTY >= 64) {
+    /*
+     * Per-plane HDR properties get us dangerously close to the 24 property
+     * limit on kernels that don't support NV_DRM_USE_EXTENDED_PROPERTIES.
+     */
+    if (NV_DRM_USE_EXTENDED_PROPERTIES) {
+        if (supportsICtCp) {
            if (nv_dev->nv_plane_lms_ctm_property) {
                drm_object_attach_property(
                    &plane->base, nv_dev->nv_plane_lms_ctm_property, 0);
@@ -2568,36 +2645,36 @@ static void nv_drm_plane_install_properties(
                    NVKMS_LUT_ARRAY_SIZE);
            }
        }
-    }

-    if (nv_dev->nv_plane_blend_ctm_property) {
-        drm_object_attach_property(
-            &plane->base, nv_dev->nv_plane_blend_ctm_property, 0);
-    }
+        if (nv_dev->nv_plane_blend_ctm_property) {
+            drm_object_attach_property(
+                &plane->base, nv_dev->nv_plane_blend_ctm_property, 0);
+        }

-    if (nv_plane->ilut_caps.supported) {
-        if (nv_plane->ilut_caps.vssSupport == NVKMS_LUT_VSS_SUPPORTED) {
-            if (nv_dev->nv_plane_degamma_tf_property) {
-                drm_object_attach_property(
-                    &plane->base, nv_dev->nv_plane_degamma_tf_property,
-                    NV_DRM_TRANSFER_FUNCTION_DEFAULT);
+        if (nv_plane->ilut_caps.supported) {
+            if (nv_plane->ilut_caps.vssSupport == NVKMS_LUT_VSS_SUPPORTED) {
+                if (nv_dev->nv_plane_degamma_tf_property) {
+                    drm_object_attach_property(
+                        &plane->base, nv_dev->nv_plane_degamma_tf_property,
+                        NV_DRM_TRANSFER_FUNCTION_DEFAULT);
+                }
+                if (nv_dev->nv_plane_degamma_multiplier_property) {
+                    /* Default to 1 in S31.32 Sign-Magnitude Format */
+                    nv_plane_state->degamma_multiplier = ((uint64_t) 1) << 32;
+                    drm_object_attach_property(
+                        &plane->base, nv_dev->nv_plane_degamma_multiplier_property,
+                        nv_plane_state->degamma_multiplier);
+                }
            }
-            if (nv_dev->nv_plane_degamma_multiplier_property) {
-                /* Default to 1 in S31.32 Sign-Magnitude Format */
-                nv_plane_state->degamma_multiplier = ((uint64_t) 1) << 32;
+            if (nv_dev->nv_plane_degamma_lut_property) {
                drm_object_attach_property(
-                    &plane->base, nv_dev->nv_plane_degamma_multiplier_property,
-                    nv_plane_state->degamma_multiplier);
+                    &plane->base, nv_dev->nv_plane_degamma_lut_property, 0);
+            }
+            if (nv_dev->nv_plane_degamma_lut_size_property) {
+                drm_object_attach_property(
+                    &plane->base, nv_dev->nv_plane_degamma_lut_size_property,
+                    NVKMS_LUT_ARRAY_SIZE);
            }
-        }
-        if (nv_dev->nv_plane_degamma_lut_property) {
-            drm_object_attach_property(
-                &plane->base, nv_dev->nv_plane_degamma_lut_property, 0);
-        }
-        if (nv_dev->nv_plane_degamma_lut_size_property) {
-            drm_object_attach_property(
-                &plane->base, nv_dev->nv_plane_degamma_lut_size_property,
-                NVKMS_LUT_ARRAY_SIZE);
        }
    }
 }
@@ -2632,7 +2709,6 @@ static void
 __nv_drm_plane_create_rotation_property(struct drm_plane *plane,
                                        NvU16 validLayerRRTransforms)
 {
-#if defined(NV_DRM_ROTATION_AVAILABLE)
    enum NvKmsRotation curRotation;
    NvU32 supported_rotations = 0;
    struct NvKmsRRParams rrParams = {
@@ -2681,7 +2757,6 @@ __nv_drm_plane_create_rotation_property(struct drm_plane *plane,
        drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
                                           supported_rotations);
    }
-#endif
 }

 static struct drm_plane*
@@ -2691,13 +2766,11 @@ nv_drm_plane_create(struct drm_device *dev,
                    NvU32 head,
                    const struct NvKmsKapiDeviceResourcesInfo *pResInfo)
 {
-#if defined(NV_DRM_UNIVERSAL_PLANE_INIT_HAS_FORMAT_MODIFIERS_ARG)
    struct nv_drm_device *nv_dev = to_nv_device(dev);
    const NvU64 linear_modifiers[] = {
        DRM_FORMAT_MOD_LINEAR,
        DRM_FORMAT_MOD_INVALID,
    };
-#endif
    enum NvKmsCompositionBlendingMode defaultCompositionMode;
    struct nv_drm_plane *nv_plane = NULL;
    struct nv_drm_plane_state *nv_plane_state = NULL;
@@ -2762,20 +2835,37 @@ nv_drm_plane_create(struct drm_device *dev,
        (1 << head) : 0,
        &nv_plane_funcs,
        formats, formats_count,
-#if defined(NV_DRM_UNIVERSAL_PLANE_INIT_HAS_FORMAT_MODIFIERS_ARG)
        (plane_type == DRM_PLANE_TYPE_CURSOR) ?
-        linear_modifiers : nv_dev->modifiers,
-#endif
-        plane_type
-#if defined(NV_DRM_UNIVERSAL_PLANE_INIT_HAS_NAME_ARG)
-        , NULL
-#endif
-        );
-
+            linear_modifiers : nv_dev->modifiers,
+        plane_type,
+        NULL);
    if (ret != 0) {
        goto failed_plane_init;
    }

+#if defined(NV_DRM_PLANE_CREATE_COLOR_PROPERTIES_PRESENT)
+    if (pResInfo->caps.supportsInputColorSpace &&
+        pResInfo->caps.supportsInputColorRange) {
+
+        nv_plane->supportsColorProperties = true;
+
+        drm_plane_create_color_properties(
+            plane,
+            NVBIT(DRM_COLOR_YCBCR_BT601) |
+            NVBIT(DRM_COLOR_YCBCR_BT709) |
+            NVBIT(DRM_COLOR_YCBCR_BT2020),
+            NVBIT(DRM_COLOR_YCBCR_FULL_RANGE) |
+            NVBIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
+            DRM_COLOR_YCBCR_BT709,
+            DRM_COLOR_YCBCR_FULL_RANGE
+        );
+    } else {
+        nv_plane->supportsColorProperties = false;
+    }
+#else
+    nv_plane->supportsColorProperties = false;
+#endif
+
    drm_plane_helper_add(plane, &nv_plane_helper_funcs);

    if (plane_type != DRM_PLANE_TYPE_CURSOR) {
@@ -2845,12 +2935,8 @@ static struct drm_crtc *__nv_drm_crtc_create(struct nv_drm_device *nv_dev,
    ret = drm_crtc_init_with_planes(nv_dev->dev,
                                    &nv_crtc->base,
                                    primary_plane, cursor_plane,
-                                    &nv_crtc_funcs
-#if defined(NV_DRM_CRTC_INIT_WITH_PLANES_HAS_NAME_ARG)
-                                    , NULL
-#endif
-                                    );
-
+                                    &nv_crtc_funcs,
+                                    NULL);
    if (ret != 0) {
        NV_DRM_DEV_LOG_ERR(
            nv_dev,
@@ -2866,21 +2952,14 @@ static struct drm_crtc *__nv_drm_crtc_create(struct nv_drm_device *nv_dev,

    nv_drm_crtc_install_properties(&nv_crtc->base);

-#if defined(NV_DRM_COLOR_MGMT_AVAILABLE)
-#if defined(NV_DRM_CRTC_ENABLE_COLOR_MGMT_PRESENT)
    drm_crtc_enable_color_mgmt(&nv_crtc->base, NVKMS_LUT_ARRAY_SIZE, true,
                               NVKMS_LUT_ARRAY_SIZE);
-#else
-    drm_helper_crtc_enable_color_mgmt(&nv_crtc->base, NVKMS_LUT_ARRAY_SIZE,
-                                      NVKMS_LUT_ARRAY_SIZE);
-#endif
    ret = drm_mode_crtc_set_gamma_size(&nv_crtc->base, NVKMS_LUT_ARRAY_SIZE);
    if (ret != 0) {
        NV_DRM_DEV_LOG_WARN(
            nv_dev,
            "Failed to initialize legacy gamma support for head %u", head);
    }
-#endif

    return &nv_crtc->base;

@@ -3015,7 +3094,7 @@ int nv_drm_get_crtc_crc32_v2_ioctl(struct drm_device *dev,
        return -EOPNOTSUPP;
    }

-    crtc = nv_drm_crtc_find(dev, filep, params->crtc_id);
+    crtc = drm_crtc_find(dev, filep, params->crtc_id);
    if (!crtc) {
        return -ENOENT;
    }
@@ -3043,7 +3122,7 @@ int nv_drm_get_crtc_crc32_ioctl(struct drm_device *dev,
        return -EOPNOTSUPP;
    }

-    crtc = nv_drm_crtc_find(dev, filep, params->crtc_id);
+    crtc = drm_crtc_find(dev, filep, params->crtc_id);
    if (!crtc) {
        return -ENOENT;
    }
--- a/kernel-open/nvidia-drm/nvidia-drm-crtc.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-crtc.h
@@ -25,7 +25,7 @@

 #include "nvidia-drm-conftest.h"

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #include "nvidia-drm-helper.h"

@@ -191,6 +191,13 @@ struct nv_drm_plane {
     */
    uint32_t layer_idx;

+    /**
+     * @supportsColorProperties
+     *
+     * If true, supports the COLOR_ENCODING and COLOR_RANGE properties.
+     */
+    bool supportsColorProperties;
+
    struct NvKmsLUTCaps ilut_caps;
    struct NvKmsLUTCaps tmo_caps;
 };
@@ -203,10 +210,23 @@ static inline struct nv_drm_plane *to_nv_plane(struct drm_plane *plane)
    return container_of(plane, struct nv_drm_plane, base);
 }

-struct nv_drm_lut_surface {
+struct nv_drm_nvkms_surface {
    struct NvKmsKapiDevice *pDevice;
    struct NvKmsKapiMemory *nvkms_memory;
    struct NvKmsKapiSurface *nvkms_surface;
+    void *buffer;
+    struct kref refcount;
+};
+
+struct nv_drm_nvkms_surface_params {
+    NvU32 width;
+    NvU32 height;
+    size_t surface_size;
+    enum NvKmsSurfaceMemoryFormat format;
+};
+
+struct nv_drm_lut_surface {
+    struct nv_drm_nvkms_surface base;
    struct {
        NvU32 vssSegments;
        enum NvKmsLUTVssType vssType;
@@ -215,14 +235,12 @@ struct nv_drm_lut_surface {
        enum NvKmsLUTFormat entryFormat;

    } properties;
-    void *buffer;
-    struct kref refcount;
 };

 struct nv_drm_plane_state {
    struct drm_plane_state base;
    s32 __user *fd_user_ptr;
-    enum NvKmsInputColorSpace input_colorspace;
+    enum nv_drm_input_color_space input_colorspace;
 #if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA)
    struct drm_property_blob *hdr_output_metadata;
 #endif
@@ -331,6 +349,6 @@ int nv_drm_get_crtc_crc32_ioctl(struct drm_device *dev,
 int nv_drm_get_crtc_crc32_v2_ioctl(struct drm_device *dev,
                                   void *data, struct drm_file *filep);

-#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#endif /* NV_DRM_AVAILABLE */

 #endif /* __NVIDIA_DRM_CRTC_H__ */
--- a/kernel-open/nvidia-drm/nvidia-drm-drv.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-drv.c
--- a/kernel-open/nvidia-drm/nvidia-drm-drv.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-drv.h
@@ -27,13 +27,15 @@

 #if defined(NV_DRM_AVAILABLE)

+struct NvKmsKapiGpuInfo;
+
 int nv_drm_probe_devices(void);

 void nv_drm_remove_devices(void);

 void nv_drm_suspend_resume(NvBool suspend);

-void nv_drm_register_drm_device(const nv_gpu_info_t *);
+void nv_drm_register_drm_device(const struct NvKmsKapiGpuInfo *);

 void nv_drm_update_drm_driver_features(void);

--- a/kernel-open/nvidia-drm/nvidia-drm-encoder.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-encoder.c
@@ -20,9 +20,9 @@
 * DEALINGS IN THE SOFTWARE.
 */

-#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#include "nvidia-drm-conftest.h" /* NV_DRM_AVAILABLE */

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #include "nvidia-drm-priv.h"
 #include "nvidia-drm-encoder.h"
@@ -139,12 +139,8 @@ nv_drm_encoder_new(struct drm_device *dev,

    ret = drm_encoder_init(dev,
                           &nv_encoder->base, &nv_encoder_funcs,
-                           nvkms_connector_signal_to_drm_encoder_signal(format)
-#if defined(NV_DRM_ENCODER_INIT_HAS_NAME_ARG)
-                           , NULL
-#endif
-                           );
-
+                           nvkms_connector_signal_to_drm_encoder_signal(format),
+                           NULL);
    if (ret != 0) {
        nv_drm_free(nv_encoder);

@@ -319,7 +315,7 @@ void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
    nv_encoder = get_nv_encoder_from_nvkms_display(dev, hDisplay);

    if (nv_encoder != NULL) {
-        NV_DRM_DEV_LOG_ERR(
+        NV_DRM_DEV_LOG_INFO(
            nv_dev,
            "Encoder with NvKmsKapiDisplay 0x%08x already exists.",
            hDisplay);
@@ -336,17 +332,6 @@ void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
        return;
    }

-    /*
-     * On some kernels, DRM has the notion of a "primary group" that
-     * tracks the global mode setting state for the device.
-     *
-     * On kernels where DRM has a primary group, we need to reinitialize
-     * after adding encoders and connectors.
-     */
-#if defined(NV_DRM_REINIT_PRIMARY_MODE_GROUP_PRESENT)
-    drm_reinit_primary_mode_group(dev);
-#endif
-
    schedule_delayed_work(&nv_dev->hotplug_event_work, 0);
 }
 #endif
--- a/kernel-open/nvidia-drm/nvidia-drm-encoder.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-encoder.h
@@ -25,15 +25,11 @@

 #include "nvidia-drm-conftest.h"

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #include "nvidia-drm-priv.h"

-#if defined(NV_DRM_DRM_ENCODER_H_PRESENT)
 #include <drm/drm_encoder.h>
-#else
-#include <drm/drmP.h>
-#endif

 #include "nvkms-kapi.h"

@@ -63,6 +59,6 @@ void nv_drm_handle_display_change(struct nv_drm_device *nv_dev,
 void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
                                             NvKmsKapiDisplay hDisplay);

-#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#endif /* NV_DRM_AVAILABLE */

 #endif /* __NVIDIA_DRM_ENCODER_H__ */
--- a/kernel-open/nvidia-drm/nvidia-drm-fb.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-fb.c
@@ -20,9 +20,9 @@
 * DEALINGS IN THE SOFTWARE.
 */

-#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#include "nvidia-drm-conftest.h" /* NV_DRM_AVAILABLE */

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #include "nvidia-drm-priv.h"
 #include "nvidia-drm-ioctl.h"
@@ -41,7 +41,7 @@ static void __nv_drm_framebuffer_free(struct nv_drm_framebuffer *nv_fb)

    /* Unreference gem object */
    for (i = 0; i < NVKMS_MAX_PLANES_PER_SURFACE; i++) {
-        struct drm_gem_object *gem = nv_fb_get_gem_obj(fb, i);
+        struct drm_gem_object *gem = fb->obj[i];
        if (gem != NULL) {
            struct nv_drm_gem_object *nv_gem = to_nv_gem_object(gem);
            nv_drm_gem_object_unreference_unlocked(nv_gem);
@@ -73,7 +73,7 @@ nv_drm_framebuffer_create_handle(struct drm_framebuffer *fb,
                                 struct drm_file *file, unsigned int *handle)
 {
    return nv_drm_gem_handle_create(file,
-                                    to_nv_gem_object(nv_fb_get_gem_obj(fb, 0)),
+                                    to_nv_gem_object(fb->obj[0]),
                                    handle);
 }

@@ -83,11 +83,10 @@ static struct drm_framebuffer_funcs nv_framebuffer_funcs = {
 };

 static struct nv_drm_framebuffer *nv_drm_framebuffer_alloc(
-    struct drm_device *dev,
+    struct nv_drm_device *nv_dev,
    struct drm_file *file,
-    struct drm_mode_fb_cmd2 *cmd)
+    const struct drm_mode_fb_cmd2 *cmd)
 {
-    struct nv_drm_device *nv_dev = to_nv_device(dev);
    struct nv_drm_framebuffer *nv_fb;
    struct nv_drm_gem_object *nv_gem;
    const int num_planes = nv_drm_format_num_planes(cmd->pixel_format);
@@ -109,7 +108,7 @@ static struct nv_drm_framebuffer *nv_drm_framebuffer_alloc(
    }

    for (i = 0; i < num_planes; i++) {
-        nv_gem = nv_drm_gem_object_lookup(dev, file, cmd->handles[i]);
+        nv_gem = nv_drm_gem_object_lookup(file, cmd->handles[i]);

        if (nv_gem == NULL) {
            NV_DRM_DEV_DEBUG_DRIVER(
@@ -118,7 +117,7 @@ static struct nv_drm_framebuffer *nv_drm_framebuffer_alloc(
            goto failed;
        }

-        nv_fb_set_gem_obj(&nv_fb->base, i, &nv_gem->base);
+        nv_fb->base.obj[i] = &nv_gem->base;
    }

     return nv_fb;
@@ -154,27 +153,13 @@ static int nv_drm_framebuffer_init(struct drm_device *dev,
    }

    for (i = 0; i < NVKMS_MAX_PLANES_PER_SURFACE; i++) {
-        struct drm_gem_object *gem = nv_fb_get_gem_obj(fb, i);
+        struct drm_gem_object *gem = fb->obj[i];
        if (gem != NULL) {
            nv_gem = to_nv_gem_object(gem);

            params.planes[i].memory = nv_gem->pMemory;
            params.planes[i].offset = fb->offsets[i];
            params.planes[i].pitch = fb->pitches[i];
-
-            /*
-             * XXX Use drm_framebuffer_funcs.dirty and
-             * drm_fb_helper_funcs.fb_dirty instead
-             *
-             * Currently using noDisplayCaching when registering surfaces with
-             * NVKMS that are using memory allocated through the DRM
-             * Dumb-Buffers API. This prevents Display Idle Frame Rate from
-             * kicking in and preventing CPU updates to the surface memory from
-             * not being reflected on the display. Ideally, DIFR would be
-             * dynamically disabled whenever a user of the memory blits to the
-             * frontbuffer. DRM provides the needed callbacks to achieve this.
-             */
-            params.noDisplayCaching |= !!nv_gem->is_drm_dumb;
        }
    }
    params.height = fb->height;
@@ -202,6 +187,43 @@ static int nv_drm_framebuffer_init(struct drm_device *dev,
        params.explicit_layout = false;
    }

+    /*
+     * XXX work around an invalid pitch assumption in DRM.
+     *
+     * The smallest pitch the display hardware allows is 256.
+     *
+     * If a DRM client allocates a 32x32 cursor surface through
+     * DRM_IOCTL_MODE_CREATE_DUMB, we'll correctly round the pitch to 256:
+     *
+     *     pitch = round(32width * 4Bpp, 256) = 256
+     *
+     * and then allocate an 8k surface:
+     *
+     *     size = pitch * 32height = 8196
+     *
+     * and report the rounded pitch and size back to the client through the
+     * struct drm_mode_create_dumb ioctl params.
+     *
+     * But when the DRM client passes that buffer object handle to
+     * DRM_IOCTL_MODE_CURSOR, the client has no way to specify the pitch.  This
+     * path in drm:
+     *
+     *    DRM_IOCTL_MODE_CURSOR
+     *     drm_mode_cursor_ioctl()
+     *      drm_mode_cursor_common()
+     *       drm_mode_cursor_universal()
+     *
+     * will implicitly create a framebuffer from the buffer object, and compute
+     * the pitch as width x 32 (without aligning to our minimum pitch).
+     *
+     * Intercept this case and force the pitch back to 256.
+     */
+    if ((params.width == 32) &&
+        (params.height == 32) &&
+        (params.planes[0].pitch == 128)) {
+        params.planes[0].pitch = 256;
+    }
+
    /* Create NvKmsKapiSurface */

    nv_fb->pSurface = nvKms->createSurface(nv_dev->pDevice, &params);
@@ -217,19 +239,20 @@ fail:
    return -EINVAL;
 }

-struct drm_framebuffer *nv_drm_internal_framebuffer_create(
+struct drm_framebuffer *nv_drm_framebuffer_create(
    struct drm_device *dev,
    struct drm_file *file,
-    struct drm_mode_fb_cmd2 *cmd)
+#if defined(NV_DRM_FB_CREATE_TAKES_FORMAT_INFO)
+    const struct drm_format_info *info,
+#endif
+    const struct drm_mode_fb_cmd2 *cmd)
 {
    struct nv_drm_device *nv_dev = to_nv_device(dev);
    struct nv_drm_framebuffer *nv_fb;
    uint64_t modifier = 0;
    int ret;
    enum NvKmsSurfaceMemoryFormat format;
-#if defined(NV_DRM_FORMAT_MODIFIERS_PRESENT)
    int i;
-#endif
    bool have_modifier = false;

    /* Check whether NvKms supports the given pixel format */
@@ -240,7 +263,6 @@ struct drm_framebuffer *nv_drm_internal_framebuffer_create(
        return ERR_PTR(-EINVAL);
    }

-#if defined(NV_DRM_FORMAT_MODIFIERS_PRESENT)
    if (cmd->flags & DRM_MODE_FB_MODIFIERS) {
        have_modifier = true;
        modifier = cmd->modifier[0];
@@ -259,9 +281,8 @@ struct drm_framebuffer *nv_drm_internal_framebuffer_create(
            return ERR_PTR(-EINVAL);
        }
    }
-#endif

-    nv_fb = nv_drm_framebuffer_alloc(dev, file, cmd);
+    nv_fb = nv_drm_framebuffer_alloc(nv_dev, file, cmd);
    if (IS_ERR(nv_fb)) {
        return (struct drm_framebuffer *)nv_fb;
    }
@@ -269,10 +290,11 @@ struct drm_framebuffer *nv_drm_internal_framebuffer_create(
    /* Fill out framebuffer metadata from the userspace fb creation request */

    drm_helper_mode_fill_fb_struct(
-        #if defined(NV_DRM_HELPER_MODE_FILL_FB_STRUCT_HAS_DEV_ARG)
        dev,
-        #endif
        &nv_fb->base,
+#if defined(NV_DRM_FB_CREATE_TAKES_FORMAT_INFO)
+        info,
+#endif
        cmd);

    /*
--- a/kernel-open/nvidia-drm/nvidia-drm-fb.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-fb.h
@@ -25,27 +25,19 @@

 #include "nvidia-drm-conftest.h"

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #if defined(NV_DRM_DRMP_H_PRESENT)
 #include <drm/drmP.h>
 #endif

-#if defined(NV_DRM_DRM_FRAMEBUFFER_H_PRESENT)
 #include <drm/drm_framebuffer.h>
-#endif

-#include "nvidia-drm-gem-nvkms-memory.h"
 #include "nvkms-kapi.h"

 struct nv_drm_framebuffer {
    struct NvKmsKapiSurface *pSurface;

-#if !defined(NV_DRM_FRAMEBUFFER_OBJ_PRESENT)
-    struct drm_gem_object*
-        obj[NVKMS_MAX_PLANES_PER_SURFACE];
-#endif
-
    struct drm_framebuffer base;
 };

@@ -58,34 +50,14 @@ static inline struct nv_drm_framebuffer *to_nv_framebuffer(
    return container_of(fb, struct nv_drm_framebuffer, base);
 }

-static inline struct drm_gem_object *nv_fb_get_gem_obj(
-    struct drm_framebuffer *fb,
-    uint32_t plane)
-{
-#if defined(NV_DRM_FRAMEBUFFER_OBJ_PRESENT)
-    return fb->obj[plane];
-#else
-    return to_nv_framebuffer(fb)->obj[plane];
-#endif
-}
-
-static inline void nv_fb_set_gem_obj(
-    struct drm_framebuffer *fb,
-    uint32_t plane,
-    struct drm_gem_object *obj)
-{
-#if defined(NV_DRM_FRAMEBUFFER_OBJ_PRESENT)
-    fb->obj[plane] = obj;
-#else
-    to_nv_framebuffer(fb)->obj[plane] = obj;
-#endif
-}
-
-struct drm_framebuffer *nv_drm_internal_framebuffer_create(
+struct drm_framebuffer *nv_drm_framebuffer_create(
    struct drm_device *dev,
    struct drm_file *file,
-    struct drm_mode_fb_cmd2 *cmd);
+#if defined(NV_DRM_FB_CREATE_TAKES_FORMAT_INFO)
+    const struct drm_format_info *info,
+#endif
+    const struct drm_mode_fb_cmd2 *cmd);

-#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#endif /* NV_DRM_AVAILABLE */

 #endif /* __NVIDIA_DRM_FB_H__ */
--- a/kernel-open/nvidia-drm/nvidia-drm-fence.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-fence.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2016-2025, NVIDIA CORPORATION. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -34,9 +34,7 @@
 #include "nvidia-drm-fence.h"
 #include "nvidia-dma-resv-helper.h"

-#if defined(NV_DRM_FENCE_AVAILABLE)
-
-#include "nvidia-dma-fence-helper.h"
+#include <linux/dma-fence.h>

 #define NV_DRM_SEMAPHORE_SURFACE_FENCE_MAX_TIMEOUT_MS 5000

@@ -83,42 +81,42 @@ struct nv_drm_prime_fence_context {

 struct nv_drm_prime_fence {
    struct list_head list_entry;
-    nv_dma_fence_t base;
+    struct dma_fence base;
    spinlock_t lock;
 };

 static inline
-struct nv_drm_prime_fence *to_nv_drm_prime_fence(nv_dma_fence_t *fence)
+struct nv_drm_prime_fence *to_nv_drm_prime_fence(struct dma_fence *fence)
 {
    return container_of(fence, struct nv_drm_prime_fence, base);
 }

 static const char*
-nv_drm_gem_fence_op_get_driver_name(nv_dma_fence_t *fence)
+nv_drm_gem_fence_op_get_driver_name(struct dma_fence *fence)
 {
    return "NVIDIA";
 }

 static const char*
-nv_drm_gem_prime_fence_op_get_timeline_name(nv_dma_fence_t *fence)
+nv_drm_gem_prime_fence_op_get_timeline_name(struct dma_fence *fence)
 {
    return "nvidia.prime";
 }

-static bool nv_drm_gem_prime_fence_op_enable_signaling(nv_dma_fence_t *fence)
+static bool nv_drm_gem_prime_fence_op_enable_signaling(struct dma_fence *fence)
 {
    // DO NOTHING
    return true;
 }

-static void nv_drm_gem_prime_fence_op_release(nv_dma_fence_t *fence)
+static void nv_drm_gem_prime_fence_op_release(struct dma_fence *fence)
 {
    struct nv_drm_prime_fence *nv_fence = to_nv_drm_prime_fence(fence);
    nv_drm_free(nv_fence);
 }

 static signed long
-nv_drm_gem_prime_fence_op_wait(nv_dma_fence_t *fence,
+nv_drm_gem_prime_fence_op_wait(struct dma_fence *fence,
                               bool intr, signed long timeout)
 {
    /*
@@ -131,12 +129,12 @@ nv_drm_gem_prime_fence_op_wait(nv_dma_fence_t *fence,
     * that it should never get hit during normal operation, but not so long
     * that the system becomes unresponsive.
     */
-    return nv_dma_fence_default_wait(fence, intr,
+    return dma_fence_default_wait(fence, intr,
                              (timeout == MAX_SCHEDULE_TIMEOUT) ?
                                  msecs_to_jiffies(96) : timeout);
 }

-static const nv_dma_fence_ops_t nv_drm_gem_prime_fence_ops = {
+static const struct dma_fence_ops nv_drm_gem_prime_fence_ops = {
    .get_driver_name = nv_drm_gem_fence_op_get_driver_name,
    .get_timeline_name = nv_drm_gem_prime_fence_op_get_timeline_name,
    .enable_signaling = nv_drm_gem_prime_fence_op_enable_signaling,
@@ -148,8 +146,8 @@ static inline void
 __nv_drm_prime_fence_signal(struct nv_drm_prime_fence *nv_fence)
 {
    list_del(&nv_fence->list_entry);
-    nv_dma_fence_signal(&nv_fence->base);
-    nv_dma_fence_put(&nv_fence->base);
+    dma_fence_signal(&nv_fence->base);
+    dma_fence_put(&nv_fence->base);
 }

 static void nv_drm_gem_prime_force_fence_signal(
@@ -289,13 +287,13 @@ __nv_drm_prime_fence_context_new(
    }

    /*
-     * nv_dma_fence_context_alloc() cannot fail, so we do not need
+     * dma_fence_context_alloc() cannot fail, so we do not need
     * to check a return value.
     */

    nv_prime_fence_context->base.ops = &nv_drm_prime_fence_context_ops;
    nv_prime_fence_context->base.nv_dev = nv_dev;
-    nv_prime_fence_context->base.context = nv_dma_fence_context_alloc(1);
+    nv_prime_fence_context->base.context = dma_fence_context_alloc(1);
    nv_prime_fence_context->base.fenceSemIndex = p->index;
    nv_prime_fence_context->pSemSurface = pSemSurface;
    nv_prime_fence_context->pLinearAddress = pLinearAddress;
@@ -343,7 +341,7 @@ failed:
    return NULL;
 }

-static nv_dma_fence_t *__nv_drm_prime_fence_context_create_fence(
+static struct dma_fence *__nv_drm_prime_fence_context_create_fence(
    struct nv_drm_prime_fence_context *nv_prime_fence_context,
    unsigned int seqno)
 {
@@ -369,12 +367,12 @@ static nv_dma_fence_t *__nv_drm_prime_fence_context_create_fence(

    spin_lock_init(&nv_fence->lock);

-    nv_dma_fence_init(&nv_fence->base, &nv_drm_gem_prime_fence_ops,
-                      &nv_fence->lock, nv_prime_fence_context->base.context,
-                      seqno);
+    dma_fence_init(&nv_fence->base, &nv_drm_gem_prime_fence_ops,
+                   &nv_fence->lock, nv_prime_fence_context->base.context,
+                   seqno);

    /* The context maintains a reference to any pending fences. */
-    nv_dma_fence_get(&nv_fence->base);
+    dma_fence_get(&nv_fence->base);

    list_add_tail(&nv_fence->list_entry, &nv_prime_fence_context->pending);

@@ -424,12 +422,11 @@ const struct nv_drm_gem_object_funcs nv_fence_context_gem_ops = {
 static inline
 struct nv_drm_fence_context *
 __nv_drm_fence_context_lookup(
-    struct drm_device *dev,
    struct drm_file *filp,
    u32 handle)
 {
    struct nv_drm_gem_object *nv_gem =
-            nv_drm_gem_object_lookup(dev, filp, handle);
+            nv_drm_gem_object_lookup(filp, handle);

    if (nv_gem != NULL && nv_gem->ops != &nv_fence_context_gem_ops) {
        nv_drm_gem_object_unreference_unlocked(nv_gem);
@@ -491,7 +488,7 @@ done:
 }

 static int __nv_drm_gem_attach_fence(struct nv_drm_gem_object *nv_gem,
-                                     nv_dma_fence_t *fence,
+                                     struct dma_fence *fence,
                                     bool shared)
 {
    nv_dma_resv_t *resv = nv_drm_gem_res_obj(nv_gem);
@@ -524,7 +521,7 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev,

    struct nv_drm_gem_object *nv_gem;
    struct nv_drm_fence_context *nv_fence_context;
-    nv_dma_fence_t *fence;
+    struct dma_fence *fence;

    if (nv_dev->pDevice == NULL) {
        ret = -EOPNOTSUPP;
@@ -536,7 +533,7 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev,
        goto done;
    }

-    nv_gem = nv_drm_gem_object_lookup(nv_dev->dev, filep, p->handle);
+    nv_gem = nv_drm_gem_object_lookup(filep, p->handle);

    if (!nv_gem) {
        NV_DRM_DEV_LOG_ERR(
@@ -548,7 +545,6 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev,
    }

    if((nv_fence_context = __nv_drm_fence_context_lookup(
-                nv_dev->dev,
                filep,
                p->fence_context_handle)) == NULL) {

@@ -587,7 +583,7 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev,

    ret = __nv_drm_gem_attach_fence(nv_gem, fence, true /* exclusive */);

-    nv_dma_fence_put(fence);
+    dma_fence_put(fence);

 fence_context_create_fence_failed:
    nv_drm_gem_object_unreference_unlocked(&nv_fence_context->base);
@@ -600,7 +596,7 @@ done:
 }

 struct nv_drm_semsurf_fence {
-    nv_dma_fence_t base;
+    struct dma_fence base;
    spinlock_t lock;

    /*
@@ -628,7 +624,7 @@ struct nv_drm_semsurf_fence_callback {
 };

 struct nv_drm_sync_fd_wait_data {
-    nv_dma_fence_cb_t dma_fence_cb;
+    struct dma_fence_cb dma_fence_cb;
    struct nv_drm_semsurf_fence_ctx *ctx;
    nv_drm_work work; /* Deferred second half of fence wait callback */

@@ -759,15 +755,15 @@ __nv_drm_semsurf_force_complete_pending(struct nv_drm_semsurf_fence_ctx *ctx)
            &ctx->pending_fences,
            typeof(*nv_fence),
            pending_node);
-        nv_dma_fence_t *fence = &nv_fence->base;
+        struct dma_fence *fence = &nv_fence->base;

        list_del(&nv_fence->pending_node);

-        nv_dma_fence_set_error(fence, -ETIMEDOUT);
-        nv_dma_fence_signal(fence);
+        dma_fence_set_error(fence, -ETIMEDOUT);
+        dma_fence_signal(fence);

        /* Remove the pending list's reference */
-        nv_dma_fence_put(fence);
+        dma_fence_put(fence);
    }

    /*
@@ -824,7 +820,7 @@ __nv_drm_semsurf_ctx_process_completed(struct nv_drm_semsurf_fence_ctx *ctx,
    struct list_head finished;
    struct list_head timed_out;
    struct nv_drm_semsurf_fence *nv_fence;
-    nv_dma_fence_t *fence;
+    struct dma_fence *fence;
    NvU64 currentSeqno = __nv_drm_get_semsurf_ctx_seqno(ctx);
    NvU64 fenceSeqno = 0;
    unsigned long flags;
@@ -888,8 +884,8 @@ __nv_drm_semsurf_ctx_process_completed(struct nv_drm_semsurf_fence_ctx *ctx,
        nv_fence = list_first_entry(&finished, typeof(*nv_fence), pending_node);
        list_del_init(&nv_fence->pending_node);
        fence = &nv_fence->base;
-        nv_dma_fence_signal(fence);
-        nv_dma_fence_put(fence); /* Drops the pending list's reference */
+        dma_fence_signal(fence);
+        dma_fence_put(fence); /* Drops the pending list's reference */
    }

    while (!list_empty(&timed_out)) {
@@ -897,9 +893,9 @@ __nv_drm_semsurf_ctx_process_completed(struct nv_drm_semsurf_fence_ctx *ctx,
                                    pending_node);
        list_del_init(&nv_fence->pending_node);
        fence = &nv_fence->base;
-        nv_dma_fence_set_error(fence, -ETIMEDOUT);
-        nv_dma_fence_signal(fence);
-        nv_dma_fence_put(fence); /* Drops the pending list's reference */
+        dma_fence_set_error(fence, -ETIMEDOUT);
+        dma_fence_signal(fence);
+        dma_fence_put(fence); /* Drops the pending list's reference */
    }
 }

@@ -1132,7 +1128,7 @@ static void __nv_drm_semsurf_fence_ctx_destroy(
     */
    nv_drm_workthread_shutdown(&ctx->worker);

-    nv_drm_del_timer_sync(&ctx->timer);
+    nv_timer_delete_sync(&ctx->timer.kernel_timer);

    /*
     * The semaphore surface could still be sending callbacks, so it is still
@@ -1265,13 +1261,13 @@ __nv_drm_semsurf_fence_ctx_new(
    }

    /*
-     * nv_dma_fence_context_alloc() cannot fail, so we do not need
+     * dma_fence_context_alloc() cannot fail, so we do not need
     * to check a return value.
     */

    ctx->base.ops = &nv_drm_semsurf_fence_ctx_ops;
    ctx->base.nv_dev = nv_dev;
-    ctx->base.context = nv_dma_fence_context_alloc(1);
+    ctx->base.context = dma_fence_context_alloc(1);
    ctx->base.fenceSemIndex = p->index;
    ctx->pSemSurface = pSemSurface;
    ctx->pSemMapping.pVoid = semMapping;
@@ -1343,26 +1339,26 @@ int nv_drm_semsurf_fence_ctx_create_ioctl(struct drm_device *dev,
 }

 static inline struct nv_drm_semsurf_fence*
-to_nv_drm_semsurf_fence(nv_dma_fence_t *fence)
+to_nv_drm_semsurf_fence(struct dma_fence *fence)
 {
    return container_of(fence, struct nv_drm_semsurf_fence, base);
 }

 static const char*
-__nv_drm_semsurf_fence_op_get_timeline_name(nv_dma_fence_t *fence)
+__nv_drm_semsurf_fence_op_get_timeline_name(struct dma_fence *fence)
 {
    return "nvidia.semaphore_surface";
 }

 static bool
-__nv_drm_semsurf_fence_op_enable_signaling(nv_dma_fence_t *fence)
+__nv_drm_semsurf_fence_op_enable_signaling(struct dma_fence *fence)
 {
    // DO NOTHING - Could defer RM callback registration until this point
    return true;
 }

 static void
-__nv_drm_semsurf_fence_op_release(nv_dma_fence_t *fence)
+__nv_drm_semsurf_fence_op_release(struct dma_fence *fence)
 {
    struct nv_drm_semsurf_fence *nv_fence =
        to_nv_drm_semsurf_fence(fence);
@@ -1370,12 +1366,12 @@ __nv_drm_semsurf_fence_op_release(nv_dma_fence_t *fence)
    nv_drm_free(nv_fence);
 }

-static const nv_dma_fence_ops_t nv_drm_semsurf_fence_ops = {
+static const struct dma_fence_ops nv_drm_semsurf_fence_ops = {
    .get_driver_name = nv_drm_gem_fence_op_get_driver_name,
    .get_timeline_name = __nv_drm_semsurf_fence_op_get_timeline_name,
    .enable_signaling = __nv_drm_semsurf_fence_op_enable_signaling,
    .release = __nv_drm_semsurf_fence_op_release,
-    .wait = nv_dma_fence_default_wait,
+    .wait = dma_fence_default_wait,
 #if defined(NV_DMA_FENCE_OPS_HAS_USE_64BIT_SEQNO)
    .use_64bit_seqno = true,
 #endif
@@ -1401,7 +1397,7 @@ __nv_drm_semsurf_ctx_add_pending(struct nv_drm_semsurf_fence_ctx *ctx,
    }

    /* Add a reference to the fence for the list */
-    nv_dma_fence_get(&nv_fence->base);
+    dma_fence_get(&nv_fence->base);
    INIT_LIST_HEAD(&nv_fence->pending_node);

    nv_fence->timeout = nv_drm_timeout_from_ms(timeoutMS);
@@ -1434,14 +1430,14 @@ __nv_drm_semsurf_ctx_add_pending(struct nv_drm_semsurf_fence_ctx *ctx,
    __nv_drm_semsurf_ctx_reg_callbacks(ctx);
 }

-static nv_dma_fence_t *__nv_drm_semsurf_fence_ctx_create_fence(
+static struct dma_fence *__nv_drm_semsurf_fence_ctx_create_fence(
    struct nv_drm_device *nv_dev,
    struct nv_drm_semsurf_fence_ctx *ctx,
    NvU64 wait_value,
    NvU64 timeout_value_ms)
 {
    struct nv_drm_semsurf_fence *nv_fence;
-    nv_dma_fence_t *fence;
+    struct dma_fence *fence;
    int ret = 0;

    if (timeout_value_ms == 0 ||
@@ -1461,9 +1457,9 @@ static nv_dma_fence_t *__nv_drm_semsurf_fence_ctx_create_fence(
 #endif

    /* Initializes the fence with one reference (for the caller) */
-    nv_dma_fence_init(fence, &nv_drm_semsurf_fence_ops,
-                      &nv_fence->lock,
-                      ctx->base.context, wait_value);
+    dma_fence_init(fence, &nv_drm_semsurf_fence_ops,
+                   &nv_fence->lock,
+                   ctx->base.context, wait_value);

    __nv_drm_semsurf_ctx_add_pending(ctx, nv_fence, timeout_value_ms);

@@ -1479,7 +1475,7 @@ int nv_drm_semsurf_fence_create_ioctl(struct drm_device *dev,
    struct nv_drm_device *nv_dev = to_nv_device(dev);
    struct drm_nvidia_semsurf_fence_create_params *p = data;
    struct nv_drm_fence_context *nv_fence_context;
-    nv_dma_fence_t *fence;
+    struct dma_fence *fence;
    int ret = -EINVAL;
    int fd;

@@ -1494,7 +1490,6 @@ int nv_drm_semsurf_fence_create_ioctl(struct drm_device *dev,
    }

    if ((nv_fence_context = __nv_drm_fence_context_lookup(
-                                nv_dev->dev,
                                filep,
                                p->fence_context_handle)) == NULL) {
        NV_DRM_DEV_LOG_ERR(
@@ -1550,7 +1545,7 @@ fence_context_create_sync_failed:
     * FD will still hold a reference, and the pending list (if the fence hasn't
     * already been signaled) will also retain a reference.
     */
-    nv_dma_fence_put(fence);
+    dma_fence_put(fence);

 fence_context_create_fence_failed:
    nv_drm_gem_object_unreference_unlocked(&nv_fence_context->base);
@@ -1608,8 +1603,8 @@ __nv_drm_semsurf_wait_fence_work_cb
 static void
 __nv_drm_semsurf_wait_fence_cb
 (
-    nv_dma_fence_t *fence,
-    nv_dma_fence_cb_t *cb
+    struct dma_fence *fence,
+    struct dma_fence_cb *cb
 )
 {
    struct nv_drm_sync_fd_wait_data *wait_data =
@@ -1634,7 +1629,7 @@ __nv_drm_semsurf_wait_fence_cb
    }

    /* Don't need to reference the fence anymore, just the fence context. */
-    nv_dma_fence_put(fence);
+    dma_fence_put(fence);
 }

 int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev,
@@ -1646,7 +1641,7 @@ int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev,
    struct nv_drm_fence_context *nv_fence_context;
    struct nv_drm_semsurf_fence_ctx *ctx;
    struct nv_drm_sync_fd_wait_data *wait_data = NULL;
-    nv_dma_fence_t *fence;
+    struct dma_fence *fence;
    unsigned long flags;
    int ret = -EINVAL;

@@ -1663,7 +1658,6 @@ int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev,
    }

    if ((nv_fence_context = __nv_drm_fence_context_lookup(
-                                nv_dev->dev,
                                filep,
                                p->fence_context_handle)) == NULL) {
        NV_DRM_DEV_LOG_ERR(
@@ -1716,9 +1710,9 @@ int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev,
    list_add(&wait_data->pending_node, &ctx->pending_waits);
    spin_unlock_irqrestore(&ctx->lock, flags);

-    ret = nv_dma_fence_add_callback(fence,
-                                    &wait_data->dma_fence_cb,
-                                    __nv_drm_semsurf_wait_fence_cb);
+    ret = dma_fence_add_callback(fence,
+                                 &wait_data->dma_fence_cb,
+                                 __nv_drm_semsurf_wait_fence_cb);

    if (ret) {
       if (ret == -ENOENT) {
@@ -1730,7 +1724,7 @@ int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev,
       }

       /* Execute second half of wait immediately, avoiding the worker thread */
-       nv_dma_fence_put(fence);
+       dma_fence_put(fence);
        __nv_drm_semsurf_wait_fence_work_cb(wait_data);
    }

@@ -1759,7 +1753,7 @@ int nv_drm_semsurf_fence_attach_ioctl(struct drm_device *dev,
    struct drm_nvidia_semsurf_fence_attach_params *p = data;
    struct nv_drm_gem_object *nv_gem = NULL;
    struct nv_drm_fence_context *nv_fence_context = NULL;
-    nv_dma_fence_t *fence;
+    struct dma_fence *fence;
    int ret = -EINVAL;

    if (nv_dev->pDevice == NULL) {
@@ -1767,7 +1761,7 @@ int nv_drm_semsurf_fence_attach_ioctl(struct drm_device *dev,
        goto done;
    }

-    nv_gem = nv_drm_gem_object_lookup(nv_dev->dev, filep, p->handle);
+    nv_gem = nv_drm_gem_object_lookup(filep, p->handle);

    if (!nv_gem) {
        NV_DRM_DEV_LOG_ERR(
@@ -1779,7 +1773,6 @@ int nv_drm_semsurf_fence_attach_ioctl(struct drm_device *dev,
    }

    nv_fence_context = __nv_drm_fence_context_lookup(
-        nv_dev->dev,
        filep,
        p->fence_context_handle);

@@ -1819,7 +1812,7 @@ int nv_drm_semsurf_fence_attach_ioctl(struct drm_device *dev,

    ret = __nv_drm_gem_attach_fence(nv_gem, fence, p->shared);

-    nv_dma_fence_put(fence);
+    dma_fence_put(fence);

 done:
    if (nv_fence_context) {
@@ -1833,6 +1826,4 @@ done:
    return ret;
 }

-#endif /* NV_DRM_FENCE_AVAILABLE */
-
 #endif /* NV_DRM_AVAILABLE */
--- a/kernel-open/nvidia-drm/nvidia-drm-fence.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-fence.h
@@ -30,8 +30,6 @@
 struct drm_file;
 struct drm_device;

-#if defined(NV_DRM_FENCE_AVAILABLE)
-
 int nv_drm_fence_supported_ioctl(struct drm_device *dev,
                                 void *data, struct drm_file *filep);

@@ -57,8 +55,6 @@ int nv_drm_semsurf_fence_attach_ioctl(struct drm_device *dev,
                                      void *data,
                                      struct drm_file *filep);

-#endif /* NV_DRM_FENCE_AVAILABLE */
-
 #endif /* NV_DRM_AVAILABLE */

 #endif /* __NVIDIA_DRM_PRIME_FENCE_H__ */
--- a/kernel-open/nvidia-drm/nvidia-drm-format.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-format.c
@@ -20,9 +20,9 @@
 * DEALINGS IN THE SOFTWARE.
 */

-#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#include "nvidia-drm-conftest.h" /* NV_DRM_AVAILABLE */

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #if defined(NV_DRM_DRMP_H_PRESENT)
 #include <drm/drmP.h>
@@ -166,4 +166,37 @@ uint32_t *nv_drm_format_array_alloc(
    return array;
 }

+bool nv_drm_format_is_yuv(u32 format)
+{
+#if defined(NV_DRM_FORMAT_INFO_HAS_IS_YUV)
+    const struct drm_format_info *format_info = drm_format_info(format);
+    return (format_info != NULL) && format_info->is_yuv;
+#else
+    switch (format) {
+        case DRM_FORMAT_YUYV:
+        case DRM_FORMAT_UYVY:
+
+        case DRM_FORMAT_NV24:
+        case DRM_FORMAT_NV42:
+        case DRM_FORMAT_NV16:
+        case DRM_FORMAT_NV61:
+        case DRM_FORMAT_NV12:
+        case DRM_FORMAT_NV21:
+
+#if defined(DRM_FORMAT_P210)
+        case DRM_FORMAT_P210:
+#endif
+#if defined(DRM_FORMAT_P010)
+        case DRM_FORMAT_P010:
+#endif
+#if defined(DRM_FORMAT_P012)
+        case DRM_FORMAT_P012:
+#endif
+            return true;
+        default:
+            return false;
+    }
+#endif
+}
+
 #endif
--- a/kernel-open/nvidia-drm/nvidia-drm-format.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-format.h
@@ -25,7 +25,7 @@

 #include "nvidia-drm-conftest.h"

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #include <drm/drm_fourcc.h>

@@ -38,6 +38,8 @@ uint32_t *nv_drm_format_array_alloc(
    unsigned int *count,
    const long unsigned int nvkms_format_mask);

-#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+bool nv_drm_format_is_yuv(u32 format);
+
+#endif /* NV_DRM_AVAILABLE */

 #endif /* __NVIDIA_DRM_FORMAT_H__ */
--- a/kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.c
@@ -24,17 +24,13 @@

 #if defined(NV_DRM_AVAILABLE)

-#if defined(NV_DRM_DRM_PRIME_H_PRESENT)
 #include <drm/drm_prime.h>
-#endif

 #if defined(NV_DRM_DRMP_H_PRESENT)
 #include <drm/drmP.h>
 #endif

-#if defined(NV_DRM_DRM_DRV_H_PRESENT)
 #include <drm/drm_drv.h>
-#endif

 #include "nvidia-drm-gem-dma-buf.h"
 #include "nvidia-drm-ioctl.h"
@@ -47,12 +43,10 @@ void __nv_drm_gem_dma_buf_free(struct nv_drm_gem_object *nv_gem)
    struct nv_drm_device *nv_dev = nv_gem->nv_dev;
    struct nv_drm_gem_dma_buf *nv_dma_buf = to_nv_dma_buf(nv_gem);

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
    if (nv_dma_buf->base.pMemory) {
        /* Free NvKmsKapiMemory handle associated with this gem object */
        nvKms->freeMemory(nv_dev->pDevice, nv_dma_buf->base.pMemory);
    }
-#endif

    drm_prime_gem_destroy(&nv_gem->base, nv_dma_buf->sgt);

@@ -157,13 +151,11 @@ nv_drm_gem_prime_import_sg_table(struct drm_device *dev,
    BUG_ON(dma_buf->size % PAGE_SIZE);

    pMemory = NULL;
-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
    if (drm_core_check_feature(dev, DRIVER_MODESET)) {
        pMemory = nvKms->getSystemMemoryHandleFromDmaBuf(nv_dev->pDevice,
                                                  (NvP64)(NvUPtr)dma_buf,
                                                  dma_buf->size - 1);
    }
-#endif

    nv_drm_gem_object_init(nv_dev, &nv_dma_buf->base,
                           &__nv_gem_dma_buf_ops, dma_buf->size, pMemory);
@@ -194,7 +186,7 @@ int nv_drm_gem_export_dmabuf_memory_ioctl(struct drm_device *dev,
    }

    if ((nv_dma_buf = nv_drm_gem_object_dma_buf_lookup(
-             dev, filep, p->handle)) == NULL) {
+             filep, p->handle)) == NULL) {
        ret = -EINVAL;
        NV_DRM_DEV_LOG_ERR(
            nv_dev,
@@ -203,7 +195,6 @@ int nv_drm_gem_export_dmabuf_memory_ioctl(struct drm_device *dev,
        goto done;
    }

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
    if (drm_core_check_feature(dev, DRIVER_MODESET)) {
        if (!nv_dma_buf->base.pMemory) {
            /*
@@ -218,7 +209,6 @@ int nv_drm_gem_export_dmabuf_memory_ioctl(struct drm_device *dev,
                             nv_dma_buf->base.base.size - 1);
        }
    }
-#endif

    if (!nv_dma_buf->base.pMemory && !pTmpMemory) {
        ret = -ENOMEM;
--- a/kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.h
@@ -48,12 +48,11 @@ static inline struct nv_drm_gem_dma_buf *to_nv_dma_buf(

 static inline
 struct nv_drm_gem_dma_buf *nv_drm_gem_object_dma_buf_lookup(
-    struct drm_device *dev,
    struct drm_file *filp,
    u32 handle)
 {
    struct nv_drm_gem_object *nv_gem =
-            nv_drm_gem_object_lookup(dev, filp, handle);
+            nv_drm_gem_object_lookup(filp, handle);

    if (nv_gem != NULL && nv_gem->ops != &__nv_gem_dma_buf_ops) {
        nv_drm_gem_object_unreference_unlocked(nv_gem);
--- a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c
@@ -22,27 +22,20 @@

 #include "nvidia-drm-conftest.h"

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #include "nvidia-drm-gem-nvkms-memory.h"
 #include "nvidia-drm-helper.h"
 #include "nvidia-drm-ioctl.h"

-#if defined(NV_DRM_DRM_DRV_H_PRESENT)
 #include <drm/drm_drv.h>
-#endif
-
-#if defined(NV_DRM_DRM_PRIME_H_PRESENT)
 #include <drm/drm_prime.h>
-#endif

 #include <linux/io.h>
 #if defined(NV_BSD)
 #include <vm/vm_pageout.h>
 #endif

-#include "nv-mm.h"
-
 static void __nv_drm_gem_nvkms_memory_free(struct nv_drm_gem_object *nv_gem)
 {
    struct nv_drm_device *nv_dev = nv_gem->nv_dev;
@@ -94,10 +87,9 @@ static vm_fault_t __nv_drm_gem_nvkms_handle_vma_fault(
    struct vm_area_struct *vma,
    struct vm_fault *vmf)
 {
-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory =
        to_nv_nvkms_memory(nv_gem);
-    unsigned long address = nv_page_fault_va(vmf);
+    unsigned long address = vmf->address;
    struct drm_gem_object *gem = vma->vm_private_data;
    unsigned long page_offset, pfn;
    vm_fault_t ret;
@@ -146,8 +138,6 @@ static vm_fault_t __nv_drm_gem_nvkms_handle_vma_fault(
    }
 #endif /* defined(NV_VMF_INSERT_PFN_PRESENT) */
    return ret;
-#endif /* defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) */
-    return VM_FAULT_SIGBUS;
 }

 static struct drm_gem_object *__nv_drm_gem_nvkms_prime_dup(
@@ -308,12 +298,12 @@ static int __nv_drm_nvkms_gem_obj_init(
    nv_nvkms_memory->pWriteCombinedIORemapAddress = NULL;
    nv_nvkms_memory->physically_mapped = false;

-    if (!nvKms->getMemoryPages(nv_dev->pDevice,
+    if (!nvKms->isVidmem(pMemory) &&
+        !nvKms->getMemoryPages(nv_dev->pDevice,
                               pMemory,
                               &pages,
-                               &numPages) &&
-        !nvKms->isVidmem(pMemory)) {
-        /* GetMemoryPages may fail for vidmem allocations,
+                               &numPages)) {
+        /* GetMemoryPages will fail for vidmem allocations,
         * but it should not fail for sysmem allocations. */
        NV_DRM_DEV_LOG_ERR(nv_dev,
            "Failed to get memory pages for NvKmsKapiMemory 0x%p",
@@ -340,6 +330,7 @@ int nv_drm_dumb_create(
    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory;
    uint8_t compressible = 0;
    struct NvKmsKapiMemory *pMemory;
+    struct NvKmsKapiAllocateMemoryParams allocParams = { };
    int ret = 0;

    args->pitch = roundup(args->width * ((args->bpp + 7) >> 3),
@@ -357,20 +348,14 @@ int nv_drm_dumb_create(
        goto fail;
    }

-    if (nv_dev->hasVideoMemory) {
-        pMemory = nvKms->allocateVideoMemory(nv_dev->pDevice,
-                                             NvKmsSurfaceMemoryLayoutPitch,
-                                             NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT,
-                                             args->size,
-                                             &compressible);
-    } else {
-        pMemory = nvKms->allocateSystemMemory(nv_dev->pDevice,
-                                              NvKmsSurfaceMemoryLayoutPitch,
-                                              NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT,
-                                              args->size,
-                                              &compressible);
-    }
+    allocParams.layout = NvKmsSurfaceMemoryLayoutPitch;
+    allocParams.type = NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT;
+    allocParams.size = args->size;
+    allocParams.noDisplayCaching = true;
+    allocParams.useVideoMemory = nv_dev->hasVideoMemory;
+    allocParams.compressible = &compressible;

+    pMemory = nvKms->allocateMemory(nv_dev->pDevice, &allocParams);
    if (pMemory == NULL) {
        ret = -ENOMEM;
        NV_DRM_DEV_LOG_ERR(
@@ -385,8 +370,6 @@ int nv_drm_dumb_create(
        goto nvkms_gem_obj_init_failed;
    }

-    nv_nvkms_memory->base.is_drm_dumb = true;
-
    /* Always map dumb buffer memory up front.  Clients are only expected
     * to use dumb buffers for software rendering, so they're not much use
     * without a CPU mapping.
@@ -482,7 +465,6 @@ int nv_drm_gem_export_nvkms_memory_ioctl(struct drm_device *dev,
    }

    if ((nv_nvkms_memory = nv_drm_gem_object_nvkms_memory_lookup(
-                    dev,
                    filep,
                    p->handle)) == NULL) {
        ret = -EINVAL;
@@ -519,8 +501,7 @@ int nv_drm_gem_alloc_nvkms_memory_ioctl(struct drm_device *dev,
    struct drm_nvidia_gem_alloc_nvkms_memory_params *p = data;
    struct nv_drm_gem_nvkms_memory *nv_nvkms_memory = NULL;
    struct NvKmsKapiMemory *pMemory;
-    enum NvKmsSurfaceMemoryLayout layout;
-    enum NvKmsKapiAllocationType type;
+    struct NvKmsKapiAllocateMemoryParams allocParams = { };
    int ret = 0;

    if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
@@ -540,25 +521,15 @@ int nv_drm_gem_alloc_nvkms_memory_ioctl(struct drm_device *dev,
        goto failed;
    }

-    layout = p->block_linear ?
+    allocParams.layout = p->block_linear ?
        NvKmsSurfaceMemoryLayoutBlockLinear : NvKmsSurfaceMemoryLayoutPitch;
-    type = (p->flags & NV_GEM_ALLOC_NO_SCANOUT) ?
+    allocParams.type = (p->flags & NV_GEM_ALLOC_NO_SCANOUT) ?
        NVKMS_KAPI_ALLOCATION_TYPE_OFFSCREEN : NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT;
+    allocParams.size = p->memory_size;
+    allocParams.useVideoMemory = nv_dev->hasVideoMemory;
+    allocParams.compressible = &p->compressible;

-    if (nv_dev->hasVideoMemory) {
-        pMemory = nvKms->allocateVideoMemory(nv_dev->pDevice,
-                                             layout,
-                                             type,
-                                             p->memory_size,
-                                             &p->compressible);
-    } else {
-        pMemory = nvKms->allocateSystemMemory(nv_dev->pDevice,
-                                              layout,
-                                              type,
-                                              p->memory_size,
-                                              &p->compressible);
-    }
-
+    pMemory = nvKms->allocateMemory(nv_dev->pDevice, &allocParams);
    if (pMemory == NULL) {
        ret = -EINVAL;
        NV_DRM_DEV_LOG_ERR(nv_dev,
@@ -640,7 +611,6 @@ int nv_drm_dumb_map_offset(struct drm_file *file,
    int ret = -EINVAL;

    if ((nv_nvkms_memory = nv_drm_gem_object_nvkms_memory_lookup(
-                    dev,
                    file,
                    handle)) == NULL) {
        NV_DRM_DEV_LOG_ERR(
--- a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h
@@ -25,7 +25,7 @@

 #include "nvidia-drm-conftest.h"

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #include "nvidia-drm-gem.h"

@@ -72,12 +72,11 @@ static inline struct nv_drm_gem_nvkms_memory *to_nv_nvkms_memory_const(

 static inline
 struct nv_drm_gem_nvkms_memory *nv_drm_gem_object_nvkms_memory_lookup(
-    struct drm_device *dev,
    struct drm_file *filp,
    u32 handle)
 {
    struct nv_drm_gem_object *nv_gem =
-            nv_drm_gem_object_lookup(dev, filp, handle);
+            nv_drm_gem_object_lookup(filp, handle);

    if (nv_gem != NULL && nv_gem->ops != &nv_gem_nvkms_memory_ops) {
        nv_drm_gem_object_unreference_unlocked(nv_gem);
--- a/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c
@@ -24,9 +24,7 @@

 #if defined(NV_DRM_AVAILABLE)

-#if defined(NV_DRM_DRM_PRIME_H_PRESENT)
 #include <drm/drm_prime.h>
-#endif

 #include "nvidia-drm-gem-user-memory.h"
 #include "nvidia-drm-helper.h"
@@ -116,11 +114,7 @@ static vm_fault_t __nv_vm_insert_mixed_helper(
 {
    int ret;

-#if defined(NV_PFN_TO_PFN_T_PRESENT)
    ret = vm_insert_mixed(vma, address, pfn_to_pfn_t(pfn));
-#else
-    ret = vm_insert_mixed(vma, address, pfn);
-#endif

    switch (ret) {
        case 0:
@@ -145,7 +139,7 @@ static vm_fault_t __nv_drm_gem_user_memory_handle_vma_fault(
    struct vm_fault *vmf)
 {
    struct nv_drm_gem_user_memory *nv_user_memory = to_nv_user_memory(nv_gem);
-    unsigned long address = nv_page_fault_va(vmf);
+    unsigned long address = vmf->address;
    struct drm_gem_object *gem = vma->vm_private_data;
    unsigned long page_offset;
    unsigned long pfn;
@@ -157,7 +151,13 @@ static vm_fault_t __nv_drm_gem_user_memory_handle_vma_fault(
 #if !defined(NV_LINUX)
    return vmf_insert_pfn(vma, address, pfn);
 #elif defined(NV_VMF_INSERT_MIXED_PRESENT)
+
+#if defined(NV_LINUX_PFN_T_H_PRESENT)
    return vmf_insert_mixed(vma, address, pfn_to_pfn_t(pfn));
+#else
+    return vmf_insert_mixed(vma, address, pfn);
+#endif
+
 #else
    return __nv_vm_insert_mixed_helper(vma, address, pfn);
 #endif
--- a/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.h
@@ -52,12 +52,11 @@ int nv_drm_gem_import_userspace_memory_ioctl(struct drm_device *dev,

 static inline
 struct nv_drm_gem_user_memory *nv_drm_gem_object_user_memory_lookup(
-    struct drm_device *dev,
    struct drm_file *filp,
    u32 handle)
 {
    struct nv_drm_gem_object *nv_gem =
-            nv_drm_gem_object_lookup(dev, filp, handle);
+            nv_drm_gem_object_lookup(filp, handle);

    if (nv_gem != NULL && nv_gem->ops != &__nv_gem_user_memory_ops) {
        nv_drm_gem_object_unreference_unlocked(nv_gem);
--- a/kernel-open/nvidia-drm/nvidia-drm-gem.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-gem.c
@@ -35,17 +35,10 @@
 #include "nvidia-drm-gem-dma-buf.h"
 #include "nvidia-drm-gem-nvkms-memory.h"

-#if defined(NV_DRM_DRM_DRV_H_PRESENT)
 #include <drm/drm_drv.h>
-#endif
-
-#if defined(NV_DRM_DRM_PRIME_H_PRESENT)
 #include <drm/drm_prime.h>
-#endif
-
-#if defined(NV_DRM_DRM_FILE_H_PRESENT)
 #include <drm/drm_file.h>
-#endif
+#include <drm/drm_vma_manager.h>

 #include "linux/dma-buf.h"

@@ -58,7 +51,7 @@ void nv_drm_gem_free(struct drm_gem_object *gem)
    /* Cleanup core gem object */
    drm_gem_object_release(&nv_gem->base);

-#if defined(NV_DRM_FENCE_AVAILABLE) && !defined(NV_DRM_GEM_OBJECT_HAS_RESV)
+#if !defined(NV_DRM_GEM_OBJECT_HAS_RESV)
    nv_dma_resv_fini(&nv_gem->resv);
 #endif

@@ -135,7 +128,7 @@ void nv_drm_gem_object_init(struct nv_drm_device *nv_dev,

    /* Initialize the gem object */

-#if defined(NV_DRM_FENCE_AVAILABLE) && !defined(NV_DRM_GEM_OBJECT_HAS_RESV)
+#if !defined(NV_DRM_GEM_OBJECT_HAS_RESV)
    nv_dma_resv_init(&nv_gem->resv);
 #endif

@@ -155,7 +148,6 @@ void nv_drm_gem_object_init(struct nv_drm_device *nv_dev,
 struct drm_gem_object *nv_drm_gem_prime_import(struct drm_device *dev,
                                               struct dma_buf *dma_buf)
 {
-#if defined(NV_DMA_BUF_OWNER_PRESENT)
    struct drm_gem_object *gem_dst;
    struct nv_drm_gem_object *nv_gem_src;

@@ -179,7 +171,6 @@ struct drm_gem_object *nv_drm_gem_prime_import(struct drm_device *dev,
            return gem_dst;
        }
    }
-#endif /* NV_DMA_BUF_OWNER_PRESENT */

    return drm_gem_prime_import(dev, dma_buf);
 }
@@ -231,8 +222,7 @@ int nv_drm_gem_map_offset_ioctl(struct drm_device *dev,
    struct nv_drm_gem_object *nv_gem;
    int ret;

-    if ((nv_gem = nv_drm_gem_object_lookup(dev,
-                                           filep,
+    if ((nv_gem = nv_drm_gem_object_lookup(filep,
                                           params->handle)) == NULL) {
        NV_DRM_DEV_LOG_ERR(
            nv_dev,
@@ -257,7 +247,6 @@ int nv_drm_gem_map_offset_ioctl(struct drm_device *dev,
    return ret;
 }

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
 int nv_drm_mmap(struct file *file, struct vm_area_struct *vma)
 {
    struct drm_file *priv = file->private_data;
@@ -268,8 +257,8 @@ int nv_drm_mmap(struct file *file, struct vm_area_struct *vma)
    struct nv_drm_gem_object *nv_gem;

    drm_vma_offset_lock_lookup(dev->vma_offset_manager);
-    node = nv_drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
-                                                 vma->vm_pgoff, vma_pages(vma));
+    node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
+                                              vma->vm_pgoff, vma_pages(vma));
    if (likely(node)) {
        obj = container_of(node, struct drm_gem_object, vma_node);
        /*
@@ -295,7 +284,7 @@ int nv_drm_mmap(struct file *file, struct vm_area_struct *vma)
        goto done;
    }

-    if (!nv_drm_vma_node_is_allowed(node, file)) {
+    if (!drm_vma_node_is_allowed(node, file->private_data)) {
        ret = -EACCES;
        goto done;
    }
@@ -317,7 +306,6 @@ done:

    return ret;
 }
-#endif

 int nv_drm_gem_identify_object_ioctl(struct drm_device *dev,
                                     void *data, struct drm_file *filep)
@@ -332,23 +320,21 @@ int nv_drm_gem_identify_object_ioctl(struct drm_device *dev,
        return -EOPNOTSUPP;
    }

-    nv_dma_buf = nv_drm_gem_object_dma_buf_lookup(dev, filep, p->handle);
+    nv_dma_buf = nv_drm_gem_object_dma_buf_lookup(filep, p->handle);
    if (nv_dma_buf) {
        p->object_type = NV_GEM_OBJECT_DMABUF;
        nv_gem = &nv_dma_buf->base;
        goto done;
    }

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
-    nv_nvkms_memory = nv_drm_gem_object_nvkms_memory_lookup(dev, filep, p->handle);
+    nv_nvkms_memory = nv_drm_gem_object_nvkms_memory_lookup(filep, p->handle);
    if (nv_nvkms_memory) {
        p->object_type = NV_GEM_OBJECT_NVKMS;
        nv_gem = &nv_nvkms_memory->base;
        goto done;
    }
-#endif

-    nv_user_memory = nv_drm_gem_object_user_memory_lookup(dev, filep, p->handle);
+    nv_user_memory = nv_drm_gem_object_user_memory_lookup(filep, p->handle);
    if (nv_user_memory) {
        p->object_type = NV_GEM_OBJECT_USERMEMORY;
        nv_gem = &nv_user_memory->base;
--- a/kernel-open/nvidia-drm/nvidia-drm-gem.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-gem.h
@@ -33,17 +33,12 @@
 #include <drm/drmP.h>
 #endif

-#if defined(NV_DRM_DRM_GEM_H_PRESENT)
 #include <drm/drm_gem.h>
-#endif

 #include "nvkms-kapi.h"
 #include "nv-mm.h"

-#if defined(NV_DRM_FENCE_AVAILABLE)
-#include "nvidia-dma-fence-helper.h"
 #include "nvidia-dma-resv-helper.h"
-#endif

 #include "linux/dma-buf.h"

@@ -73,9 +68,7 @@ struct nv_drm_gem_object {

    struct NvKmsKapiMemory *pMemory;

-    bool is_drm_dumb;
-
-#if defined(NV_DRM_FENCE_AVAILABLE) && !defined(NV_DRM_GEM_OBJECT_HAS_RESV)
+#if !defined(NV_DRM_GEM_OBJECT_HAS_RESV)
    nv_dma_resv_t  resv;
 #endif
 };
@@ -90,47 +83,14 @@ static inline struct nv_drm_gem_object *to_nv_gem_object(
    return NULL;
 }

-/*
- * drm_gem_object_{get/put}() added by commit
- * e6b62714e87c8811d5564b6a0738dcde63a51774 (2017-02-28) and
- * drm_gem_object_{reference/unreference}() removed by commit
- * 3e70fd160cf0b1945225eaa08dd2cb8544f21cb8 (2018-11-15).
- */
-
-static inline void
-nv_drm_gem_object_reference(struct nv_drm_gem_object *nv_gem)
-{
-#if defined(NV_DRM_GEM_OBJECT_GET_PRESENT)
-    drm_gem_object_get(&nv_gem->base);
-#else
-    drm_gem_object_reference(&nv_gem->base);
-#endif
-}
-
 static inline void
 nv_drm_gem_object_unreference_unlocked(struct nv_drm_gem_object *nv_gem)
 {
-#if defined(NV_DRM_GEM_OBJECT_GET_PRESENT)
-
 #if defined(NV_DRM_GEM_OBJECT_PUT_UNLOCK_PRESENT)
    drm_gem_object_put_unlocked(&nv_gem->base);
 #else
    drm_gem_object_put(&nv_gem->base);
 #endif
-
-#else
-    drm_gem_object_unreference_unlocked(&nv_gem->base);
-#endif
-}
-
-static inline void
-nv_drm_gem_object_unreference(struct nv_drm_gem_object *nv_gem)
-{
-#if defined(NV_DRM_GEM_OBJECT_GET_PRESENT)
-    drm_gem_object_put(&nv_gem->base);
-#else
-    drm_gem_object_unreference(&nv_gem->base);
-#endif
 }

 static inline int nv_drm_gem_handle_create_drop_reference(
@@ -171,17 +131,10 @@ done:
 void nv_drm_gem_free(struct drm_gem_object *gem);

 static inline struct nv_drm_gem_object *nv_drm_gem_object_lookup(
-    struct drm_device *dev,
    struct drm_file *filp,
    u32 handle)
 {
-#if (NV_DRM_GEM_OBJECT_LOOKUP_ARGUMENT_COUNT == 3)
-    return to_nv_gem_object(drm_gem_object_lookup(dev, filp, handle));
-#elif (NV_DRM_GEM_OBJECT_LOOKUP_ARGUMENT_COUNT == 2)
    return to_nv_gem_object(drm_gem_object_lookup(filp, handle));
-#else
-    #error "Unknown argument count of drm_gem_object_lookup()"
-#endif
 }

 static inline int nv_drm_gem_handle_create(struct drm_file *filp,
@@ -191,7 +144,6 @@ static inline int nv_drm_gem_handle_create(struct drm_file *filp,
    return drm_gem_handle_create(filp, &nv_gem->base, handle);
 }

-#if defined(NV_DRM_FENCE_AVAILABLE)
 static inline nv_dma_resv_t *nv_drm_gem_res_obj(struct nv_drm_gem_object *nv_gem)
 {
 #if defined(NV_DRM_GEM_OBJECT_HAS_RESV)
@@ -200,7 +152,6 @@ static inline nv_dma_resv_t *nv_drm_gem_res_obj(struct nv_drm_gem_object *nv_gem
    return nv_gem->base.dma_buf ? nv_gem->base.dma_buf->resv : &nv_gem->resv;
 #endif
 }
-#endif

 void nv_drm_gem_object_init(struct nv_drm_device *nv_dev,
                            struct nv_drm_gem_object *nv_gem,
--- a/kernel-open/nvidia-drm/nvidia-drm-helper.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-helper.c
@@ -33,7 +33,7 @@

 #include "nvmisc.h"

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #if defined(NV_DRM_DRMP_H_PRESENT)
 #include <drm/drmP.h>
@@ -43,27 +43,7 @@
 #include <drm/drm_atomic_uapi.h>
 #endif

-/*
- * The inclusion of drm_framebuffer.h was removed from drm_crtc.h by commit
- * 720cf96d8fec ("drm: Drop drm_framebuffer.h from drm_crtc.h") in v6.0.
- *
- * We only need drm_framebuffer.h for drm_framebuffer_put(), and it is always
- * present (v4.9+) when drm_framebuffer_{put,get}() is present (v4.12+), so it
- * is safe to unconditionally include it when drm_framebuffer_get() is present.
- */
-#if defined(NV_DRM_FRAMEBUFFER_GET_PRESENT)
 #include <drm/drm_framebuffer.h>
-#endif
-
-static void __nv_drm_framebuffer_put(struct drm_framebuffer *fb)
-{
-#if defined(NV_DRM_FRAMEBUFFER_GET_PRESENT)
-    drm_framebuffer_put(fb);
-#else
-    drm_framebuffer_unreference(fb);
-#endif
-
-}

 /*
 * drm_atomic_helper_disable_all() has been added by commit
@@ -149,7 +129,6 @@ int nv_drm_atomic_helper_disable_all(struct drm_device *dev,
            goto free;
    }

-#if defined(NV_DRM_ROTATION_AVAILABLE)
    nv_drm_for_each_plane(plane, dev) {
        plane_state = drm_atomic_get_plane_state(state, plane);
        if (IS_ERR(plane_state)) {
@@ -159,7 +138,6 @@ int nv_drm_atomic_helper_disable_all(struct drm_device *dev,

        plane_state->rotation = DRM_MODE_ROTATE_0;
    }
-#endif

    nv_drm_for_each_connector_in_state(state, conn, conn_state, i) {
        ret = drm_atomic_set_crtc_for_connector(conn_state, NULL);
@@ -189,29 +167,15 @@ free:
                WARN_ON(plane->state->crtc);

                if (plane->old_fb)
-                    __nv_drm_framebuffer_put(plane->old_fb);
+                    drm_framebuffer_put(plane->old_fb);
           }
           plane->old_fb = NULL;
       }
    }

-#if defined(NV_DRM_ATOMIC_STATE_REF_COUNTING_PRESENT)
    drm_atomic_state_put(state);
-#else
-    if (ret != 0) {
-        drm_atomic_state_free(state);
-    } else {
-        /*
-         * In case of success, drm_atomic_commit() takes care to cleanup and
-         * free @state.
-         *
-         * Comment placed above drm_atomic_commit() says: The caller must not
-         * free or in any other way access @state. If the function fails then
-         * the caller must clean up @state itself.
-         */
-    }
-#endif
+
    return ret;
 }

-#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#endif /* NV_DRM_AVAILABLE */
--- a/kernel-open/nvidia-drm/nvidia-drm-helper.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-helper.h
@@ -31,67 +31,26 @@
 #include <drm/drmP.h>
 #endif

-#if defined(NV_DRM_DRM_DRV_H_PRESENT)
 #include <drm/drm_drv.h>
-#endif

-#if defined(NV_DRM_ALPHA_BLENDING_AVAILABLE) || defined(NV_DRM_ROTATION_AVAILABLE)
-/* For DRM_ROTATE_* , DRM_REFLECT_* */
+#if defined(NV_DRM_ALPHA_BLENDING_AVAILABLE)
 #include <drm/drm_blend.h>
 #endif

-#if defined(NV_DRM_ROTATION_AVAILABLE) || \
-    defined(NV_DRM_COLOR_CTM_3X4_PRESENT) || \
-    defined(NV_DRM_COLOR_LUT_PRESENT)
 /*
 * For DRM_MODE_ROTATE_*, DRM_MODE_REFLECT_*, struct drm_color_ctm_3x4, and
 * struct drm_color_lut.
 */
 #include <uapi/drm/drm_mode.h>
-#endif
-
-#if defined(NV_DRM_ROTATION_AVAILABLE)
-/*
- * 19-05-2017 c2c446ad29437bb92b157423c632286608ebd3ec has added
- * DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* to UAPI and removed
- * DRM_ROTATE_* and DRM_REFLECT_*
- */
-#if !defined(DRM_MODE_ROTATE_0)
-#define DRM_MODE_ROTATE_0       DRM_ROTATE_0
-#define DRM_MODE_ROTATE_90      DRM_ROTATE_90
-#define DRM_MODE_ROTATE_180     DRM_ROTATE_180
-#define DRM_MODE_ROTATE_270     DRM_ROTATE_270
-#define DRM_MODE_REFLECT_X      DRM_REFLECT_X
-#define DRM_MODE_REFLECT_Y      DRM_REFLECT_Y
-#define DRM_MODE_ROTATE_MASK    DRM_ROTATE_MASK
-#define DRM_MODE_REFLECT_MASK   DRM_REFLECT_MASK
-#endif
-
-#endif //NV_DRM_ROTATION_AVAILABLE

 /*
- * drm_dev_put() is added by commit 9a96f55034e41b4e002b767e9218d55f03bdff7d
- * (2017-09-26) and drm_dev_unref() is removed by
- * ba1d345401476a5f7fbad622607c5a1f95e59b31 (2018-11-15).
- *
- * drm_dev_unref() has been added and drm_dev_free() removed by commit -
- *
- *      2014-01-29: 099d1c290e2ebc3b798961a6c177c3aef5f0b789
+ * Commit 1e13c5644c44 ("drm/drm_mode_object: increase max objects to
+ * accommodate new color props") in Linux v6.8 increased the pre-object
+ * property limit to from 24 to 64.
 */
-static inline void nv_drm_dev_free(struct drm_device *dev)
-{
-#if defined(NV_DRM_DEV_PUT_PRESENT)
-    drm_dev_put(dev);
-#elif defined(NV_DRM_DEV_UNREF_PRESENT)
-    drm_dev_unref(dev);
-#else
-    drm_dev_free(dev);
-#endif
-}
+#define NV_DRM_USE_EXTENDED_PROPERTIES (DRM_OBJECT_MAX_PROPERTY >= 64)

-#if defined(NV_DRM_DRM_PRIME_H_PRESENT)
 #include <drm/drm_prime.h>
-#endif

 static inline struct sg_table*
 nv_drm_prime_pages_to_sg(struct drm_device *dev,
@@ -104,8 +63,6 @@ nv_drm_prime_pages_to_sg(struct drm_device *dev,
 #endif
 }

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
-
 /*
 * drm_for_each_connector(), drm_for_each_crtc(), drm_for_each_fb(),
 * drm_for_each_encoder and drm_for_each_plane() were added by kernel
@@ -159,18 +116,6 @@ nv_drm_prime_pages_to_sg(struct drm_device *dev,
    list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 #endif

-#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT)
-#define nv_drm_for_each_connector(connector, conn_iter, dev) \
-        drm_for_each_connector_iter(connector, conn_iter)
-#elif defined(drm_for_each_connector)
-#define nv_drm_for_each_connector(connector, conn_iter, dev) \
-    drm_for_each_connector(connector, dev)
-#else
-#define nv_drm_for_each_connector(connector, conn_iter, dev) \
-    WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));      \
-    list_for_each_entry(connector, &(dev)->mode_config.connector_list, head)
-#endif
-
 #if defined(drm_for_each_encoder)
 #define nv_drm_for_each_encoder(encoder, dev) \
    drm_for_each_encoder(encoder, dev)
@@ -341,72 +286,8 @@ int nv_drm_atomic_helper_disable_all(struct drm_device *dev,
    for_each_new_plane_in_state(__state, plane, new_plane_state, __i)
 #endif

-static inline struct drm_connector *
-nv_drm_connector_lookup(struct drm_device *dev, struct drm_file *filep,
-                        uint32_t id)
-{
-#if !defined(NV_DRM_CONNECTOR_LOOKUP_PRESENT)
-    return drm_connector_find(dev, id);
-#elif defined(NV_DRM_MODE_OBJECT_FIND_HAS_FILE_PRIV_ARG)
-    return drm_connector_lookup(dev, filep, id);
-#else
-    return drm_connector_lookup(dev, id);
-#endif
-}
-
-static inline void nv_drm_connector_put(struct drm_connector *connector)
-{
-#if defined(NV_DRM_CONNECTOR_PUT_PRESENT)
-    drm_connector_put(connector);
-#elif defined(NV_DRM_CONNECTOR_LOOKUP_PRESENT)
-    drm_connector_unreference(connector);
-#endif
-}
-
-static inline void nv_drm_property_blob_put(struct drm_property_blob *blob)
-{
-#if defined(NV_DRM_PROPERTY_BLOB_PUT_PRESENT)
-    drm_property_blob_put(blob);
-#else
-    drm_property_unreference_blob(blob);
-#endif
-}
-
-static inline void nv_drm_property_blob_get(struct drm_property_blob *blob)
-{
-#if defined(NV_DRM_PROPERTY_BLOB_PUT_PRESENT)
-    drm_property_blob_get(blob);
-#else
-    drm_property_reference_blob(blob);
-#endif
-}
-
-static inline struct drm_crtc *
-nv_drm_crtc_find(struct drm_device *dev, struct drm_file *filep, uint32_t id)
-{
-#if defined(NV_DRM_MODE_OBJECT_FIND_HAS_FILE_PRIV_ARG)
-    return drm_crtc_find(dev, filep, id);
-#else
-    return drm_crtc_find(dev, id);
-#endif
-}
-
-static inline struct drm_encoder *nv_drm_encoder_find(struct drm_device *dev,
-    uint32_t id)
-{
-#if defined(NV_DRM_MODE_OBJECT_FIND_HAS_FILE_PRIV_ARG)
-    return drm_encoder_find(dev, NULL /* file_priv */, id);
-#else
-    return drm_encoder_find(dev, id);
-#endif
-}
-
-#if defined(NV_DRM_DRM_AUTH_H_PRESENT)
 #include <drm/drm_auth.h>
-#endif
-#if defined(NV_DRM_DRM_FILE_H_PRESENT)
 #include <drm/drm_file.h>
-#endif

 /*
 * drm_file_get_master() added by commit 56f0729a510f ("drm: protect drm_master
@@ -431,10 +312,6 @@ static inline struct drm_master *nv_drm_file_get_master(struct drm_file *filep)
 *     Ville Syrjälä <ville.syrjala@linux.intel.com>
 *
 * drm_connector_for_each_possible_encoder() is copied from
- * include/drm/drm_connector.h and modified to use nv_drm_encoder_find()
- * instead of drm_encoder_find().
- *
- * drm_connector_for_each_possible_encoder() is copied from
 *      include/drm/drm_connector.h @
 *      83aefbb887b59df0b3520965c3701e01deacfc52
 * which has the following copyright and license information:
@@ -460,9 +337,7 @@ static inline struct drm_master *nv_drm_file_get_master(struct drm_file *filep)
 * OF THIS SOFTWARE.
 */

-#if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT)
 #include <drm/drm_connector.h>
-#endif

 /**
 * nv_drm_connector_for_each_possible_encoder - iterate connector's possible
@@ -481,8 +356,9 @@ static inline struct drm_master *nv_drm_file_get_master(struct drm_file *filep)
       for ((__i) = 0; (__i) < ARRAY_SIZE((connector)->encoder_ids) &&        \
                    (connector)->encoder_ids[(__i)] != 0; (__i)++)            \
               for_each_if((encoder) =                                        \
-                           nv_drm_encoder_find((connector)->dev,              \
-                                               (connector)->encoder_ids[(__i)]))
+                           drm_encoder_find((connector)->dev, NULL,           \
+                                            (connector)->encoder_ids[(__i)]))
+

 #define nv_drm_connector_for_each_possible_encoder(connector, encoder) \
    {                                                                  \
@@ -537,80 +413,14 @@ nv_drm_connector_update_edid_property(struct drm_connector *connector,
 #endif
 }

-#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT)
-#include <drm/drm_connector.h>
-
-static inline
-void nv_drm_connector_list_iter_begin(struct drm_device *dev,
-                                      struct drm_connector_list_iter *iter)
-{
-#if defined(NV_DRM_CONNECTOR_LIST_ITER_BEGIN_PRESENT)
-    drm_connector_list_iter_begin(dev, iter);
-#else
-    drm_connector_list_iter_get(dev, iter);
-#endif
-}
-
-static inline
-void nv_drm_connector_list_iter_end(struct drm_connector_list_iter *iter)
-{
-#if defined(NV_DRM_CONNECTOR_LIST_ITER_BEGIN_PRESENT)
-    drm_connector_list_iter_end(iter);
-#else
-    drm_connector_list_iter_put(iter);
-#endif
-}
-#endif
-
-/*
- * The drm_format_num_planes() function was added by commit d0d110e09629 drm:
- * Add drm_format_num_planes() utility function in v3.3 (2011-12-20). Prototype
- * was moved from drm_crtc.h to drm_fourcc.h by commit ae4df11a0f53 (drm: Move
- * format-related helpers to drm_fourcc.c) in v4.8 (2016-06-09).
- * drm_format_num_planes() has been removed by commit 05c452c115bf (drm: Remove
- * users of drm_format_num_planes) in v5.3 (2019-05-16).
- *
- * drm_format_info() is available only from v4.10 (2016-10-18), added by commit
- * 84770cc24f3a (drm: Centralize format information).
- */
-#include <drm/drm_crtc.h>
 #include <drm/drm_fourcc.h>

 static inline int nv_drm_format_num_planes(uint32_t format)
 {
-#if defined(NV_DRM_FORMAT_NUM_PLANES_PRESENT)
-    return drm_format_num_planes(format);
-#else
    const struct drm_format_info *info = drm_format_info(format);
    return info != NULL ? info->num_planes : 1;
-#endif
 }

-#if defined(NV_DRM_FORMAT_MODIFIERS_PRESENT)
-/*
- * DRM_FORMAT_MOD_LINEAR was also defined after the original modifier support
- * was added to the kernel, as a more explicit alias of DRM_FORMAT_MOD_NONE
- */
-#if !defined(DRM_FORMAT_MOD_VENDOR_NONE)
-#define DRM_FORMAT_MOD_VENDOR_NONE 0
-#endif
-
-#if !defined(DRM_FORMAT_MOD_LINEAR)
-#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
-#endif
-
-/*
- * DRM_FORMAT_MOD_INVALID was defined after the original modifier support was
- * added to the kernel, for use as a sentinel value.
- */
-#if !defined(DRM_FORMAT_RESERVED)
-#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
-#endif
-
-#if !defined(DRM_FORMAT_MOD_INVALID)
-#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
-#endif
-
 /*
 * DRM_FORMAT_MOD_VENDOR_NVIDIA was previously called
 * DRM_FORMAT_MOD_VNEDOR_NV.
@@ -633,8 +443,6 @@ static inline int nv_drm_format_num_planes(uint32_t format)
                             (((c) & 0x7) << 23)))
 #endif

-#endif /* defined(NV_DRM_FORMAT_MODIFIERS_PRESENT) */
-
 /*
 * DRM_UNLOCKED was removed with commit 2798ffcc1d6a ("drm: Remove locking for
 * legacy ioctls and DRM_UNLOCKED") in v6.8, but it was previously made
@@ -659,92 +467,6 @@ struct drm_color_ctm_3x4 {
 };
 #endif

-/*
- * struct drm_color_lut was added by commit 5488dc16fde7 ("drm: introduce pipe
- * color correction properties") in v4.6. For backwards compatibility, define it
- * when not present.
- */
-#if !defined(NV_DRM_COLOR_LUT_PRESENT)
-struct drm_color_lut {
-    __u16 red;
-    __u16 green;
-    __u16 blue;
-    __u16 reserved;
-};
-#endif
-
-/*
- * drm_vma_offset_exact_lookup_locked() were added
- * by kernel commit 2225cfe46bcc which was Signed-off-by:
- *      Daniel Vetter <daniel.vetter@intel.com>
- *
- * drm_vma_offset_exact_lookup_locked() were copied from
- *      include/drm/drm_vma_manager.h @ 2225cfe46bcc
- * which has the following copyright and license information:
- *
- * Copyright (c) 2013 David Herrmann <dh.herrmann@gmail.com>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <drm/drm_vma_manager.h>
-
-/**
- * nv_drm_vma_offset_exact_lookup_locked() - Look up node by exact address
- * @mgr: Manager object
- * @start: Start address (page-based, not byte-based)
- * @pages: Size of object (page-based)
- *
- * Same as drm_vma_offset_lookup_locked() but does not allow any offset into the node.
- * It only returns the exact object with the given start address.
- *
- * RETURNS:
- * Node at exact start address @start.
- */
-static inline struct drm_vma_offset_node *
-nv_drm_vma_offset_exact_lookup_locked(struct drm_vma_offset_manager *mgr,
-                                      unsigned long start,
-                                      unsigned long pages)
-{
-#if defined(NV_DRM_VMA_OFFSET_EXACT_LOOKUP_LOCKED_PRESENT)
-    return drm_vma_offset_exact_lookup_locked(mgr, start, pages);
-#else
-    struct drm_vma_offset_node *node;
-
-    node = drm_vma_offset_lookup_locked(mgr, start, pages);
-    return (node && node->vm_node.start == start) ? node : NULL;
-#endif
-}
-
-static inline bool
-nv_drm_vma_node_is_allowed(struct drm_vma_offset_node *node,
-                           struct file *filp)
-{
-#if defined(NV_DRM_VMA_NODE_IS_ALLOWED_HAS_TAG_ARG)
-    return drm_vma_node_is_allowed(node, filp->private_data);
-#else
-    return drm_vma_node_is_allowed(node, filp);
-#endif
-}
-
-#endif /* defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) */
-
 #endif /* defined(NV_DRM_AVAILABLE) */

 #endif /* __NVIDIA_DRM_HELPER_H__ */
--- a/kernel-open/nvidia-drm/nvidia-drm-ioctl.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-ioctl.h
@@ -182,6 +182,7 @@ struct drm_nvidia_gem_import_userspace_memory_params {

 struct drm_nvidia_get_dev_info_params {
    uint32_t gpu_id;             /* OUT */
+    uint32_t mig_device;         /* OUT */
    uint32_t primary_index;      /* OUT; the "card%d" value */

    uint32_t supports_alloc;     /* OUT */
--- a/kernel-open/nvidia-drm/nvidia-drm-modeset.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-modeset.c
@@ -20,9 +20,9 @@
 * DEALINGS IN THE SOFTWARE.
 */

-#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#include "nvidia-drm-conftest.h" /* NV_DRM_AVAILABLE */

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #include "nvidia-drm-priv.h"
 #include "nvidia-drm-modeset.h"
@@ -34,10 +34,7 @@
 #include <drm/drmP.h>
 #endif

-#if defined(NV_DRM_DRM_VBLANK_H_PRESENT)
 #include <drm/drm_vblank.h>
-#endif
-
 #include <drm/drm_atomic.h>
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
@@ -48,9 +45,7 @@
 #include <linux/host1x-next.h>
 #endif

-#if defined(NV_DRM_FENCE_AVAILABLE)
-#include "nvidia-dma-fence-helper.h"
-#endif
+#include <linux/dma-fence.h>

 struct nv_drm_atomic_state {
    struct NvKmsKapiRequestedModeSetConfig config;
@@ -156,24 +151,23 @@ static int __nv_drm_put_back_post_fence_fd(
    return ret;
 }

-#if defined(NV_DRM_FENCE_AVAILABLE)
 struct nv_drm_plane_fence_cb_data {
-    nv_dma_fence_cb_t dma_fence_cb;
+    struct dma_fence_cb dma_fence_cb;
    struct nv_drm_device *nv_dev;
    NvU32 semaphore_index;
 };

 static void
 __nv_drm_plane_fence_cb(
-    nv_dma_fence_t *fence,
-    nv_dma_fence_cb_t *cb_data
+    struct dma_fence *fence,
+    struct dma_fence_cb *cb_data
 )
 {
    struct nv_drm_plane_fence_cb_data *fence_data =
        container_of(cb_data, typeof(*fence_data), dma_fence_cb);
    struct nv_drm_device *nv_dev = fence_data->nv_dev;

-    nv_dma_fence_put(fence);
+    dma_fence_put(fence);
    nvKms->signalDisplaySemaphore(nv_dev->pDevice, fence_data->semaphore_index);
    nv_drm_free(fence_data);
 }
@@ -279,9 +273,9 @@ static int __nv_drm_convert_in_fences(
        fence_data->nv_dev = nv_dev;
        fence_data->semaphore_index = semaphore_index;

-        ret = nv_dma_fence_add_callback(plane_state->fence,
-                                        &fence_data->dma_fence_cb,
-                                        __nv_drm_plane_fence_cb);
+        ret = dma_fence_add_callback(plane_state->fence,
+                                     &fence_data->dma_fence_cb,
+                                     __nv_drm_plane_fence_cb);

        switch (ret) {
        case -ENOENT:
@@ -313,7 +307,6 @@ static int __nv_drm_convert_in_fences(

    return 0;
 }
-#endif /* defined(NV_DRM_FENCE_AVAILABLE) */

 static int __nv_drm_get_syncpt_data(
    struct nv_drm_device *nv_dev,
@@ -414,7 +407,6 @@ nv_drm_atomic_apply_modeset_config(struct drm_device *dev,
        return -EINVAL;
    }

-#if defined(NV_DRM_FRAMEBUFFER_OBJ_PRESENT)
    if (commit) {
        /*
         * This function does what is necessary to prepare the framebuffers
@@ -426,10 +418,6 @@ nv_drm_atomic_apply_modeset_config(struct drm_device *dev,
         * in the new state, prefering explicit sync fences when appropriate.
         * This must be done prior to converting the per-plane fences to
         * semaphore waits below.
-         *
-         * Note this only works when the drm_framebuffer:obj[] field is present
-         * and populated, so skip calling this function on kernels where that
-         * field is not present.
         */
        ret = drm_atomic_helper_prepare_planes(dev, state);

@@ -437,7 +425,6 @@ nv_drm_atomic_apply_modeset_config(struct drm_device *dev,
            return ret;
        }
    }
-#endif /* defined(NV_DRM_FRAMEBUFFER_OBJ_PRESENT) */

    memset(requested_config, 0, sizeof(*requested_config));

@@ -472,7 +459,6 @@ nv_drm_atomic_apply_modeset_config(struct drm_device *dev,
                nv_new_crtc_state->nv_flip = NULL;
            }

-#if defined(NV_DRM_FENCE_AVAILABLE)
            ret = __nv_drm_convert_in_fences(nv_dev,
                                             state,
                                             crtc,
@@ -481,7 +467,6 @@ nv_drm_atomic_apply_modeset_config(struct drm_device *dev,
            if (ret != 0) {
                return ret;
            }
-#endif /* defined(NV_DRM_FENCE_AVAILABLE) */
        }

        /*
@@ -534,7 +519,6 @@ int nv_drm_atomic_check(struct drm_device *dev,
 {
    int ret = 0;

-#if defined(NV_DRM_COLOR_MGMT_AVAILABLE)
    struct drm_crtc *crtc;
    struct drm_crtc_state *crtc_state;
    int i;
@@ -550,7 +534,6 @@ int nv_drm_atomic_check(struct drm_device *dev,
            }
        }
    }
-#endif /* NV_DRM_COLOR_MGMT_AVAILABLE */

    if ((ret = drm_atomic_helper_check(dev, state)) != 0) {
        goto done;
@@ -677,9 +660,32 @@ int nv_drm_atomic_commit(struct drm_device *dev,
                    "Flip event timeout on head %u", nv_crtc->head);
            }
        }
-    }

-#if defined(NV_DRM_ATOMIC_HELPER_SWAP_STATE_HAS_STALL_ARG)
+        /*
+         * If the legacy LUT needs to be updated, ensure that the previous LUT
+         * update is complete first.
+         */
+        if (crtc_state->color_mgmt_changed) {
+            NvBool complete = nvKms->checkLutNotifier(nv_dev->pDevice,
+                                                      nv_crtc->head,
+                                                      !nonblock /* waitForCompletion */);
+
+            /* If checking the LUT notifier failed, assume no LUT notifier is set. */
+            if (!complete) {
+                if (nonblock) {
+                    return -EBUSY;
+                } else {
+                    /*
+                     * checkLutNotifier should wait on the notifier in this
+                     * case, so we should only get here if the wait timed out.
+                     */
+                    NV_DRM_DEV_LOG_ERR(
+                        nv_dev,
+                        "LUT notifier timeout on head %u", nv_crtc->head);
+                }
+            }
+        }
+    }

    /*
     * nv_drm_atomic_commit_internal()
@@ -691,18 +697,18 @@ int nv_drm_atomic_commit(struct drm_device *dev,
     * expected.
     */

-#if defined(NV_DRM_ATOMIC_HELPER_SWAP_STATE_RETURN_INT)
    ret = drm_atomic_helper_swap_state(state, false /* stall */);
    if (WARN_ON(ret != 0)) {
        return ret;
    }
-#else
-    drm_atomic_helper_swap_state(state, false /* stall */);
-#endif

-#else
-    drm_atomic_helper_swap_state(dev, state);
-#endif
+    /*
+     * Used to update legacy modeset state pointers to support UAPIs not updated
+     * by the core atomic modeset infrastructure.
+     *
+     * Example: /sys/class/drm/<card connector>/enabled
+     */
+    drm_atomic_helper_update_legacy_modeset_state(dev, state);

    /*
     * nv_drm_atomic_commit_internal() must not return failure after
@@ -803,19 +809,25 @@ int nv_drm_atomic_commit(struct drm_device *dev,
                    __nv_drm_handle_flip_event(nv_crtc);
                }
            }
+
+            if (crtc_state->color_mgmt_changed) {
+                NvBool complete = nvKms->checkLutNotifier(nv_dev->pDevice,
+                                                          nv_crtc->head,
+                                                          true /* waitForCompletion */);
+                if (!complete) {
+                    NV_DRM_DEV_LOG_ERR(
+                        nv_dev,
+                        "LUT notifier timeout on head %u", nv_crtc->head);
+                }
+            }
        }
    }

 done:

-#if defined(NV_DRM_ATOMIC_STATE_REF_COUNTING_PRESENT)
    /*
-     * If ref counting is present, state will be freed when the caller
-     * drops its reference after we return.
+     * State will be freed when the caller drops its reference after we return.
     */
-#else
-    drm_atomic_state_free(state);
-#endif

    return 0;
 }
--- a/kernel-open/nvidia-drm/nvidia-drm-modeset.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-modeset.h
@@ -25,7 +25,7 @@

 #include "nvidia-drm-conftest.h"

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #include "nvkms-kapi.h"

@@ -48,6 +48,6 @@ void nv_drm_handle_flip_occurred(struct nv_drm_device *nv_dev,

 int nv_drm_shut_down_all_crtcs(struct drm_device *dev);

-#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#endif /* NV_DRM_AVAILABLE */

 #endif /* __NVIDIA_DRM_MODESET_H__ */
--- a/kernel-open/nvidia-drm/nvidia-drm-os-interface.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-os-interface.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2023, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2015-2025, NVIDIA CORPORATION. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -26,11 +26,8 @@

 #if defined(NV_DRM_AVAILABLE)

-#if defined(NV_LINUX_SYNC_FILE_H_PRESENT)
 #include <linux/file.h>
 #include <linux/sync_file.h>
-#endif
-
 #include <linux/vmalloc.h>
 #include <linux/sched.h>
 #include <linux/device.h>
@@ -66,18 +63,6 @@ void nv_drm_free(void *ptr)
    kfree(ptr);
 }

-char *nv_drm_asprintf(const char *fmt, ...)
-{
-    va_list ap;
-    char *p;
-
-    va_start(ap, fmt);
-    p = kvasprintf(GFP_KERNEL, fmt, ap);
-    va_end(ap);
-
-    return p;
-}
-
 #if defined(NVCPU_X86) || defined(NVCPU_X86_64)
  #define WRITE_COMBINE_FLUSH()    asm volatile("sfence":::"memory")
 #elif defined(NVCPU_PPC64LE)
@@ -236,19 +221,8 @@ unsigned long nv_drm_timeout_from_ms(NvU64 relative_timeout_ms)
    return jiffies + msecs_to_jiffies(relative_timeout_ms);
 }

-bool nv_drm_del_timer_sync(nv_drm_timer *timer)
+int nv_drm_create_sync_file(struct dma_fence *fence)
 {
-    if (del_timer_sync(&timer->kernel_timer)) {
-        return true;
-    } else {
-        return false;
-    }
-}
-
-#if defined(NV_DRM_FENCE_AVAILABLE)
-int nv_drm_create_sync_file(nv_dma_fence_t *fence)
-{
-#if defined(NV_LINUX_SYNC_FILE_H_PRESENT)
    struct sync_file *sync;
    int fd = get_unused_fd_flags(O_CLOEXEC);

@@ -267,20 +241,12 @@ int nv_drm_create_sync_file(nv_dma_fence_t *fence)
    fd_install(fd, sync->file);

    return fd;
-#else /* defined(NV_LINUX_SYNC_FILE_H_PRESENT) */
-    return -EINVAL;
-#endif  /* defined(NV_LINUX_SYNC_FILE_H_PRESENT) */
 }

-nv_dma_fence_t *nv_drm_sync_file_get_fence(int fd)
+struct dma_fence *nv_drm_sync_file_get_fence(int fd)
 {
-#if defined(NV_SYNC_FILE_GET_FENCE_PRESENT)
    return sync_file_get_fence(fd);
-#else /* defined(NV_SYNC_FILE_GET_FENCE_PRESENT) */
-    return NULL;
-#endif  /* defined(NV_SYNC_FILE_GET_FENCE_PRESENT) */
 }
-#endif /* defined(NV_DRM_FENCE_AVAILABLE) */

 void nv_drm_yield(void)
 {
--- a/kernel-open/nvidia-drm/nvidia-drm-os-interface.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-os-interface.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2015-2025, NVIDIA CORPORATION. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -29,9 +29,7 @@

 #if defined(NV_DRM_AVAILABLE)

-#if defined(NV_DRM_FENCE_AVAILABLE)
-#include "nvidia-dma-fence-helper.h"
-#endif
+#include "linux/dma-fence.h"

 #if defined(NV_LINUX) || defined(NV_BSD)
 #include "nv-kthread-q.h"
@@ -58,16 +56,6 @@ typedef struct nv_timer nv_drm_timer;
 #error "Need to define kernel timer callback primitives for this OS"
 #endif

-#if defined(NV_DRM_FBDEV_GENERIC_SETUP_PRESENT) && defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PRESENT)
-#define NV_DRM_FBDEV_AVAILABLE
-#define NV_DRM_FBDEV_GENERIC_AVAILABLE
-#endif
-
-#if defined(NV_DRM_FBDEV_TTM_SETUP_PRESENT) && defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PRESENT)
-#define NV_DRM_FBDEV_AVAILABLE
-#define NV_DRM_FBDEV_TTM_AVAILABLE
-#endif
-
 struct page;

 /* Set to true when the atomic modeset feature is enabled. */
@@ -81,8 +69,6 @@ void *nv_drm_calloc(size_t nmemb, size_t size);

 void nv_drm_free(void *ptr);

-char *nv_drm_asprintf(const char *fmt, ...);
-
 void nv_drm_write_combine_flush(void);

 int nv_drm_lock_user_pages(unsigned long address,
@@ -111,17 +97,13 @@ void nv_drm_timer_setup(nv_drm_timer *timer,

 void nv_drm_mod_timer(nv_drm_timer *timer, unsigned long relative_timeout_ms);

-bool nv_drm_del_timer_sync(nv_drm_timer *timer);
-
 unsigned long nv_drm_timer_now(void);

 unsigned long nv_drm_timeout_from_ms(NvU64 relative_timeout_ms);

-#if defined(NV_DRM_FENCE_AVAILABLE)
-int nv_drm_create_sync_file(nv_dma_fence_t *fence);
+int nv_drm_create_sync_file(struct dma_fence *fence);

-nv_dma_fence_t *nv_drm_sync_file_get_fence(int fd);
-#endif /* defined(NV_DRM_FENCE_AVAILABLE) */
+struct dma_fence *nv_drm_sync_file_get_fence(int fd);

 void nv_drm_yield(void);

--- a/kernel-open/nvidia-drm/nvidia-drm-priv.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-priv.h
@@ -31,13 +31,8 @@
 #include <drm/drmP.h>
 #endif

-#if defined(NV_DRM_DRM_DEVICE_H_PRESENT)
 #include <drm/drm_device.h>
-#endif
-
-#if defined(NV_DRM_DRM_GEM_H_PRESENT)
 #include <drm/drm_gem.h>
-#endif

 #include "nvidia-drm-os-interface.h"

@@ -85,14 +80,20 @@
    DRM_DEBUG_DRIVER("[GPU ID 0x%08x] " __fmt,     \
                     __dev->gpu_info.gpu_id, ##__VA_ARGS__)

+enum nv_drm_input_color_space {
+    NV_DRM_INPUT_COLOR_SPACE_NONE,
+    NV_DRM_INPUT_COLOR_SPACE_SCRGB_LINEAR,
+    NV_DRM_INPUT_COLOR_SPACE_BT2100_PQ
+};
+
 struct nv_drm_device {
    nv_gpu_info_t gpu_info;
+    MIGDeviceId gpu_mig_device;

    struct drm_device *dev;

    struct NvKmsKapiDevice *pDevice;

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
    /*
     * Lock to protect drm-subsystem and fields of this structure
     * from concurrent access.
@@ -122,9 +123,7 @@ struct nv_drm_device {
    NvU8 genericPageKind;
    NvU8 pageKindGeneration;
    NvU8 sectorLayout;
-#if defined(NV_DRM_FORMAT_MODIFIERS_PRESENT)
    NvU64 modifiers[6 /* block linear */ + 1 /* linear */ + 1 /* terminator */];
-#endif

    struct delayed_work hotplug_event_work;
    atomic_t enable_event_handling;
@@ -137,12 +136,8 @@ struct nv_drm_device {
     */
    wait_queue_head_t flip_event_wq;

-#endif
-
-#if defined(NV_DRM_FENCE_AVAILABLE)
    NvU64 semsurf_stride;
    NvU64 semsurf_max_submitted_offset;
-#endif

    NvBool hasVideoMemory;

@@ -182,6 +177,9 @@ struct nv_drm_device {
    struct drm_property *nv_crtc_regamma_divisor_property;

    struct nv_drm_device *next;
+
+    NvU64 vtFbBaseAddress;
+    NvU64 vtFbSize;
 };

 static inline NvU32 nv_drm_next_display_semaphore(
--- a/kernel-open/nvidia-drm/nvidia-drm-sources.mk
+++ b/kernel-open/nvidia-drm/nvidia-drm-sources.mk
@@ -30,41 +30,27 @@ NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-os-interface.c
 # Register the conftests needed by nvidia-drm.ko
 #

-NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_available
-NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_atomic_available
 NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl_refcount_inc
 NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl_refcount_dec_and_test
 NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_alpha_blending_available
 NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_fd_to_handle
 NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_handle_to_fd
+NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_timer_delete_sync
+NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl___vma_start_write

-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_unref
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_reinit_primary_mode_group
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_user_pages_remote
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_user_pages
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += pin_user_pages_remote
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += pin_user_pages
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_lookup
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_state_ref_counting
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_driver_has_gem_prime_res_obj
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_helper_connector_dpms
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_funcs_have_mode_in_name
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_has_vrr_capable_property
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += vmf_insert_pfn
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_framebuffer_get
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_get
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_put
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_format_num_planes
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_for_each_possible_encoder
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_rotation_available
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_vma_offset_exact_lookup_locked
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_put_unlocked
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += nvhost_dma_fence_unpack
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += list_is_first
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += timer_setup
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_fence_set_error
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += fence_set_error
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += sync_file_get_fence
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_aperture_remove_conflicting_framebuffers
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffers
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += aperture_remove_conflicting_devices
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += aperture_remove_conflicting_pci_devices
@@ -72,42 +58,20 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_fbdev_generic_setup
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_fbdev_ttm_setup
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_client_setup
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_attach_hdr_output_metadata_property
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_helper_crtc_enable_color_mgmt
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_crtc_enable_color_mgmt
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_plane_create_color_properties
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_helper_legacy_gamma_set
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += vmf_insert_mixed
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += pfn_to_pfn_t
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_prime_mmap

-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_present
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_bus_type
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_get_irq
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_get_name
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_device_list
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_legacy_dev_list
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_set_busid
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_connectors_changed
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_init_function_args
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_helper_mode_fill_fb_struct
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_master_drop_has_from_release_arg
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_unload_has_int_return_type
-NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_has_address
 NV_CONFTEST_TYPE_COMPILE_TESTS += vm_ops_fault_removed_vma_arg
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_helper_crtc_destroy_state_has_crtc_arg
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_helper_plane_destroy_state_has_plane_arg
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_object_find_has_file_priv_arg
-NV_CONFTEST_TYPE_COMPILE_TESTS += dma_buf_owner
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_list_iter
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_helper_swap_state_has_stall_arg
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_prime_flag_present
 NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_t
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_gem_object_has_resv
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_async_flip
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_pageflip_flags
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_vrr_enabled
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_format_modifiers_present
 NV_CONFTEST_TYPE_COMPILE_TESTS += mm_has_mmap_lock
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_vma_node_is_allowed_has_tag_arg
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_vma_offset_node_has_readonly
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_display_mode_has_vrefresh
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_master_set_has_int_return_type
@@ -125,23 +89,21 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_add_fence
 NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_reserve_fences
 NV_CONFTEST_TYPE_COMPILE_TESTS += reservation_object_reserve_shared_has_num_fences_arg
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_has_override_edid
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_master_has_leases
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_file_get_master
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_modeset_lock_all_end
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_lookup
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_put
 NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_dumb_destroy
 NV_CONFTEST_TYPE_COMPILE_TESTS += fence_ops_use_64bit_seqno
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_framebuffers_has_driver_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_framebuffers_has_no_primary_arg
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffers_has_driver_arg
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_create_dp_colorspace_property_has_supported_colorspaces_arg
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_syncobj_features_present
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_unlocked_ioctl_flag_present
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_framebuffer_obj_present
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_color_ctm_3x4_present
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_color_lut
-NV_CONFTEST_TYPE_COMPILE_TESTS += drm_property_blob_put
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_format_info_has_is_yuv
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_gem_prime_mmap
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_output_poll_changed
 NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_date
-NV_CONFTEST_TYPE_COMPILE_TESTS += file_operations_fop_unsigned_offset_present
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_helper_funcs_mode_valid_has_const_mode_arg
+NV_CONFTEST_TYPE_COMPILE_TESTS += drm_fb_create_takes_format_info
--- a/kernel-open/nvidia-drm/nvidia-drm-utils.c
+++ b/kernel-open/nvidia-drm/nvidia-drm-utils.c
@@ -20,18 +20,15 @@
 * DEALINGS IN THE SOFTWARE.
 */

-#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#include "nvidia-drm-conftest.h" /* NV_DRM_AVAILABLE */

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #if defined(NV_DRM_DRMP_H_PRESENT)
 #include <drm/drmP.h>
 #endif

-#if defined(NV_DRM_DRM_PLANE_H_PRESENT)
 #include <drm/drm_plane.h>
-#endif
-
 #include <drm/drm_modes.h>
 #include <uapi/drm/drm_fourcc.h>

--- a/kernel-open/nvidia-drm/nvidia-drm-utils.h
+++ b/kernel-open/nvidia-drm/nvidia-drm-utils.h
@@ -25,7 +25,7 @@

 #include "nvidia-drm-conftest.h"

-#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
+#if defined(NV_DRM_AVAILABLE)

 #include "nvkms-kapi.h"

@@ -49,6 +49,6 @@ void nvkms_display_mode_to_drm_mode(
 void drm_mode_to_nvkms_display_mode(const struct drm_display_mode *src,
                                    struct NvKmsKapiDisplayMode *dst);

-#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
+#endif /* NV_DRM_AVAILABLE */

 #endif /* __NVIDIA_DRM_UTILS_H__ */
--- a/kernel-open/nvidia-modeset/nv-kthread-q.c
+++ b/kernel-open/nvidia-modeset/nv-kthread-q.c
@@ -29,12 +29,7 @@
 #include <linux/completion.h>
 #include <linux/module.h>
 #include <linux/mm.h>
-
-#if defined(NV_LINUX_BUG_H_PRESENT)
-    #include <linux/bug.h>
-#else
-    #include <asm/bug.h>
-#endif
+#include <linux/bug.h>

 // Today's implementation is a little simpler and more limited than the
 // API description allows for in nv-kthread-q.h. Details include:
--- a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c
+++ b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -53,6 +53,7 @@
 #include "nv-procfs.h"
 #include "nv-kthread-q.h"
 #include "nv-time.h"
+#include "nv-timer.h"
 #include "nv-lock.h"
 #include "nv-chardev-numbers.h"

@@ -102,6 +103,11 @@ MODULE_PARM_DESC(malloc_verbose, "Report information about malloc calls on modul
 static bool malloc_verbose = false;
 module_param_named(malloc_verbose, malloc_verbose, bool, 0400);

+MODULE_PARM_DESC(conceal_vrr_caps, 
+                 "Conceal all display VRR capabilities");
+static bool conceal_vrr_caps = false;
+module_param_named(conceal_vrr_caps, conceal_vrr_caps, bool, 0400);
+
 /* Fail allocating the RM core channel for NVKMS using the i-th method (see
 * FailAllocCoreChannelMethod). Failures not using the i-th method are ignored. */
 MODULE_PARM_DESC(fail_alloc_core_channel, "Control testing for hardware core channel allocation failure");
@@ -135,7 +141,12 @@ NvBool nvkms_test_fail_alloc_core_channel(

    return NV_TRUE;
 }
-    
+
+NvBool nvkms_conceal_vrr_caps(void)
+{
+    return conceal_vrr_caps;
+}
+
 NvBool nvkms_output_rounding_fix(void)
 {
    return output_rounding_fix;
@@ -198,6 +209,225 @@ NvBool nvkms_kernel_supports_syncpts(void)
 /*************************************************************************
 * NVKMS interface for nvhost unit for sync point APIs.
 *************************************************************************/
+#if defined(NV_LINUX_NVHOST_H_PRESENT) && defined(CONFIG_TEGRA_GRHOST)
+
+#undef NVKMS_SYNCPT_STUBS_NEEDED
+
+#include <linux/nvhost.h>
+
+NvBool nvkms_syncpt_op(
+    enum NvKmsSyncPtOp op,
+    NvKmsSyncPtOpParams *params)
+{
+    struct platform_device *pdev = nvhost_get_default_device();
+
+    switch (op) {
+
+    case NVKMS_SYNCPT_OP_ALLOC:
+        params->alloc.id = nvhost_get_syncpt_client_managed(
+                                pdev, params->alloc.syncpt_name);
+        break;
+
+    case NVKMS_SYNCPT_OP_PUT:
+        nvhost_syncpt_put_ref_ext(pdev, params->put.id);
+        break;
+
+    case NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH: {
+
+        struct nvhost_fence *fence;
+        NvU32 id, thresh;
+
+        fence = nvhost_fence_get(params->fd_to_id_and_thresh.fd);
+        if (fence == NULL) {
+            return NV_FALSE;
+        }
+
+        if (nvhost_fence_num_pts(fence) > 1) {
+            /*! Syncpoint fence fd contains more than one syncpoint */
+            nvhost_fence_put(fence);
+            return NV_FALSE;
+        }
+
+        if (nvhost_fence_get_pt(fence, 0, &id, &thresh) != 0) {
+            nvhost_fence_put(fence);
+            return NV_FALSE;
+        }
+
+        params->fd_to_id_and_thresh.id = id;
+        params->fd_to_id_and_thresh.thresh = thresh;
+
+        nvhost_fence_put(fence);
+
+        break;
+    }
+
+    case NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD:
+        nvhost_syncpt_create_fence_single_ext(
+                pdev,
+                params->id_and_thresh_to_fd.id,
+                params->id_and_thresh_to_fd.thresh,
+                "nvkms-fence",
+                &params->id_and_thresh_to_fd.fd);
+        break;
+
+    case NVKMS_SYNCPT_OP_READ_MINVAL:
+        params->read_minval.minval =
+                nvhost_syncpt_read_minval(pdev, params->read_minval.id);
+        break;
+
+    }
+
+    return NV_TRUE;
+}
+
+#elif defined(NV_LINUX_HOST1X_NEXT_H_PRESENT) && defined(NV_LINUX_NVHOST_H_PRESENT)
+
+#include <linux/dma-fence.h>
+#include <linux/file.h>
+#include <linux/host1x-next.h>
+#include <linux/sync_file.h>
+
+/*
+ * If the host1x.h header is present, then we are using the upstream
+ * host1x driver and so make sure CONFIG_TEGRA_HOST1X is defined to pick
+ * up the correct prototypes/definitions in nvhost.h.
+ */
+#define CONFIG_TEGRA_HOST1X
+
+#include <linux/nvhost.h>
+
+#undef NVKMS_SYNCPT_STUBS_NEEDED
+
+NvBool nvkms_syncpt_op(
+    enum NvKmsSyncPtOp op,
+    NvKmsSyncPtOpParams *params)
+{
+    struct host1x_syncpt *host1x_sp;
+    struct platform_device *pdev;
+    struct host1x *host1x;
+
+    pdev = nvhost_get_default_device();
+    if (pdev == NULL) {
+        nvkms_log(NVKMS_LOG_LEVEL_ERROR, NVKMS_LOG_PREFIX,
+                  "Failed to get nvhost default pdev");
+         return NV_FALSE;
+    }
+
+    host1x = nvhost_get_host1x(pdev);
+    if (host1x == NULL) {
+        nvkms_log(NVKMS_LOG_LEVEL_ERROR, NVKMS_LOG_PREFIX,
+                  "Failed to get host1x");
+        return  NV_FALSE;
+    }
+
+    switch (op) {
+
+    case NVKMS_SYNCPT_OP_ALLOC:
+        host1x_sp = host1x_syncpt_alloc(host1x,
+                                        HOST1X_SYNCPT_CLIENT_MANAGED,
+                                        params->alloc.syncpt_name);
+        if (host1x_sp == NULL) {
+            return NV_FALSE;
+        }
+
+        params->alloc.id = host1x_syncpt_id(host1x_sp);
+        break;
+
+    case NVKMS_SYNCPT_OP_PUT:
+        host1x_sp = host1x_syncpt_get_by_id_noref(host1x, params->put.id);
+        if (host1x_sp == NULL) {
+            return NV_FALSE;
+        }
+
+        host1x_syncpt_put(host1x_sp);
+        break;
+
+    case NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH: {
+
+        struct dma_fence *f;
+        NvU32 id, thresh;
+        int err;
+
+        f = sync_file_get_fence(params->fd_to_id_and_thresh.fd);
+        if (f == NULL) {
+            return NV_FALSE;
+        }
+
+        if (dma_fence_is_array(f)) {
+            struct dma_fence_array *array = to_dma_fence_array(f);
+
+            if (array->num_fences > 1) {
+                /* Syncpoint fence fd contains more than one syncpoint */
+                dma_fence_put(f);
+                return NV_FALSE;
+            }
+
+            f = array->fences[0];
+        }
+
+        err = host1x_fence_extract(f, &id, &thresh);
+        dma_fence_put(f);
+
+        if (err < 0) {
+            return NV_FALSE;
+        }
+
+        params->fd_to_id_and_thresh.id = id;
+        params->fd_to_id_and_thresh.thresh = thresh;
+
+        break;
+    }
+
+    case NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD: {
+
+        struct sync_file *file;
+        struct dma_fence *f;
+        int fd;
+
+        host1x_sp = host1x_syncpt_get_by_id_noref(host1x,
+                                params->id_and_thresh_to_fd.id);
+        if (host1x_sp == NULL) {
+            return NV_FALSE;
+        }
+
+        f = host1x_fence_create(host1x_sp,
+                                params->id_and_thresh_to_fd.thresh, true);
+        if (IS_ERR(f)) {
+            return NV_FALSE;
+        }
+
+        fd = get_unused_fd_flags(O_CLOEXEC);
+        if (fd < 0) {
+            dma_fence_put(f);
+            return NV_FALSE;
+        }
+
+        file = sync_file_create(f);
+        dma_fence_put(f);
+
+        if (!file) {
+            return NV_FALSE;
+        }
+
+        fd_install(fd, file->file);
+
+        params->id_and_thresh_to_fd.fd = fd;
+        break;
+    }
+
+    case NVKMS_SYNCPT_OP_READ_MINVAL:
+        host1x_sp = host1x_syncpt_get_by_id_noref(host1x, params->read_minval.id);
+        if (host1x_sp == NULL) {
+            return NV_FALSE;
+        }
+
+        params->read_minval.minval = host1x_syncpt_read(host1x_sp);
+        break;
+    }
+
+    return NV_TRUE;
+}
+#endif

 #ifdef NVKMS_SYNCPT_STUBS_NEEDED
 /* Unsupported STUB for nvkms_syncpt APIs */
@@ -738,7 +968,7 @@ static void nvkms_kthread_q_callback(void *arg)
     * pending timers and than waiting for workqueue callbacks.
     */
    if (timer->kernel_timer_created) {
-        del_timer_sync(&timer->kernel_timer);
+        nv_timer_delete_sync(&timer->kernel_timer);
    }

    /*
@@ -808,12 +1038,6 @@ inline static void nvkms_timer_callback_typed_data(struct timer_list *timer)
    _nvkms_timer_callback_internal(nvkms_timer);
 }

-inline static void nvkms_timer_callback_anon_data(unsigned long arg)
-{
-    struct nvkms_timer_t *nvkms_timer = (struct nvkms_timer_t *) arg;
-    _nvkms_timer_callback_internal(nvkms_timer);
-}
-
 static void
 nvkms_init_timer(struct nvkms_timer_t *timer, nvkms_timer_proc_t *proc,
                 void *dataPtr, NvU32 dataU32, NvBool isRefPtr, NvU64 usec)
@@ -846,13 +1070,7 @@ nvkms_init_timer(struct nvkms_timer_t *timer, nvkms_timer_proc_t *proc,
        timer->kernel_timer_created = NV_FALSE;
        nvkms_queue_work(&nvkms_kthread_q, &timer->nv_kthread_q_item);
    } else {
-#if defined(NV_TIMER_SETUP_PRESENT)
        timer_setup(&timer->kernel_timer, nvkms_timer_callback_typed_data, 0);
-#else
-        init_timer(&timer->kernel_timer);
-        timer->kernel_timer.function = nvkms_timer_callback_anon_data;
-        timer->kernel_timer.data = (unsigned long) timer;
-#endif

        timer->kernel_timer_created = NV_TRUE;
        mod_timer(&timer->kernel_timer, jiffies + NVKMS_USECS_TO_JIFFIES(usec));
@@ -1131,6 +1349,7 @@ static void nvkms_kapi_event_kthread_q_callback(void *arg)

 static struct nvkms_per_open *nvkms_open_common(enum NvKmsClientType type,
                                         struct NvKmsKapiDevice *device,
+                                         NvBool interruptible,
                                         int *status)
 {
    struct nvkms_per_open *popen = NULL;
@@ -1144,10 +1363,13 @@ static struct nvkms_per_open *nvkms_open_common(enum NvKmsClientType type,

    popen->type = type;

-    *status = down_interruptible(&nvkms_lock);
-
-    if (*status != 0) {
-        goto failed;
+    if (interruptible) {
+        *status = down_interruptible(&nvkms_lock);
+        if (*status != 0) {
+            goto failed;
+        }
+    } else {
+        down(&nvkms_lock);
    }

    popen->data = nvKmsOpen(current->tgid, type, popen);
@@ -1247,15 +1469,19 @@ static void nvkms_close_popen(struct nvkms_per_open *popen)
 static int nvkms_ioctl_common
 (
    struct nvkms_per_open *popen,
-    NvU32 cmd, NvU64 address, const size_t size
+    NvU32 cmd, NvU64 address, const size_t size,
+    NvBool interruptible
 )
 {
-    int status;
    NvBool ret;

-    status = down_interruptible(&nvkms_lock);
-    if (status != 0) {
-        return status;
+    if (interruptible) {
+        int status = down_interruptible(&nvkms_lock);
+        if (status != 0) {
+            return status;
+        }
+    } else {
+        down(&nvkms_lock);
    }

    if (popen->data != NULL) {
@@ -1282,7 +1508,10 @@ struct nvkms_per_open* nvkms_open_from_kapi
    struct nvkms_per_open *ret;

    nvkms_read_lock_pm_lock();
-    ret = nvkms_open_common(NVKMS_CLIENT_KERNEL_SPACE, device, &status);
+    ret = nvkms_open_common(NVKMS_CLIENT_KERNEL_SPACE,
+                            device,
+                            NV_FALSE /* interruptible */,
+                            &status);
    nvkms_read_unlock_pm_lock();

    return ret;
@@ -1301,13 +1530,15 @@ NvBool nvkms_ioctl_from_kapi_try_pmlock
 {
    NvBool ret;

+    // XXX PM lock must be allowed to fail, see bug 4432810.
    if (nvkms_read_trylock_pm_lock()) {
        return NV_FALSE;
    }

    ret = nvkms_ioctl_common(popen,
                             cmd,
-                             (NvU64)(NvUPtr)params_address, param_size) == 0;
+                             (NvU64)(NvUPtr)params_address, param_size,
+                             NV_FALSE /* interruptible */) == 0;
    nvkms_read_unlock_pm_lock();

    return ret;
@@ -1324,7 +1555,8 @@ NvBool nvkms_ioctl_from_kapi
    nvkms_read_lock_pm_lock();
    ret = nvkms_ioctl_common(popen,
                             cmd,
-                             (NvU64)(NvUPtr)params_address, param_size) == 0;
+                             (NvU64)(NvUPtr)params_address, param_size,
+                             NV_FALSE /* interruptible */) == 0;
    nvkms_read_unlock_pm_lock();

    return ret;
@@ -1493,9 +1725,7 @@ static size_t nvkms_config_file_open
    struct inode *file_inode;
    size_t file_size = 0;
    size_t read_size = 0;
-#if defined(NV_KERNEL_READ_HAS_POINTER_POS_ARG)
    loff_t pos = 0;
-#endif

    *buff = NULL;
    
@@ -1538,14 +1768,8 @@ static size_t nvkms_config_file_open
     * kernel_read_file for kernels >= 4.6
     */
    while ((read_size < file_size) && (i++ < NVKMS_READ_FILE_MAX_LOOPS)) {
-#if defined(NV_KERNEL_READ_HAS_POINTER_POS_ARG)
        ssize_t ret = kernel_read(file, *buff + read_size,
                                  file_size - read_size, &pos);
-#else
-        ssize_t ret = kernel_read(file, read_size,
-                                  *buff + read_size,
-                                  file_size - read_size);
-#endif
        if (ret <= 0) {
            break;
        }
@@ -1666,7 +1890,10 @@ static int nvkms_open(struct inode *inode, struct file *filp)
    }

    filp->private_data =
-        nvkms_open_common(NVKMS_CLIENT_USER_SPACE, NULL, &status);
+        nvkms_open_common(NVKMS_CLIENT_USER_SPACE,
+                          NULL,
+                          NV_TRUE /* interruptible */,
+                          &status);

    nvkms_read_unlock_pm_lock();

@@ -1725,7 +1952,8 @@ static int nvkms_ioctl(struct inode *inode, struct file *filp,
    status = nvkms_ioctl_common(popen,
                                params.cmd,
                                params.address,
-                                params.size);
+                                params.size,
+                                NV_TRUE /* interruptible */);

    nvkms_read_unlock_pm_lock();

@@ -1922,7 +2150,11 @@ restart:
             * completion, and we wait for queue completion with
             * nv_kthread_q_stop below.
             */
+#if !defined(NV_BSD) && NV_IS_EXPORT_SYMBOL_PRESENT_timer_delete_sync
+            if (timer_delete_sync(&timer->kernel_timer) == 1) {
+#else
            if (del_timer_sync(&timer->kernel_timer) == 1) {
+#endif
                /*  We've deactivated timer so we need to clean after it */
                list_del(&timer->timers_list);

--- a/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h
+++ b/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h
@@ -110,6 +110,7 @@ enum FailAllocCoreChannelMethod {
 };

 NvBool nvkms_test_fail_alloc_core_channel(enum FailAllocCoreChannelMethod method);
+NvBool nvkms_conceal_vrr_caps(void);
 NvBool nvkms_output_rounding_fix(void);
 NvBool nvkms_disable_hdmi_frl(void);
 NvBool nvkms_disable_vrr_memclk_switch(void);
--- a/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild
+++ b/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild
@@ -52,7 +52,7 @@ nvidia-modeset-y += $(NVIDIA_MODESET_BINARY_OBJECT_O)
 # Define nvidia-modeset.ko-specific CFLAGS.
 #

-NVIDIA_MODESET_CFLAGS += -I$(src)/nvidia-modeset
+NVIDIA_MODESET_CFLAGS += -I$(src)/nvidia-modeset -I$(src)/common/inc
 NVIDIA_MODESET_CFLAGS += -UDEBUG -U_DEBUG -DNDEBUG -DNV_BUILD_MODULE_INSTANCES=0

 # Some Android kernels prohibit driver use of filesystem functions like
@@ -94,13 +94,10 @@ $(obj)/$(NVIDIA_MODESET_INTERFACE): $(addprefix $(obj)/,$(NVIDIA_MODESET_OBJECTS

 NV_OBJECTS_DEPEND_ON_CONFTEST += $(NVIDIA_MODESET_OBJECTS)

-NV_CONFTEST_TYPE_COMPILE_TESTS += timespec64
 NV_CONFTEST_TYPE_COMPILE_TESTS += proc_ops
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += pde_data
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += timer_setup
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += list_is_first
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_real_ts64
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += acpi_video_backlight_use_native
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += acpi_video_register_backlight
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += kernel_read_has_pointer_pos_arg
+NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_timer_delete_sync
--- a/kernel-open/nvidia-peermem/nv-p2p.h
+++ b/kernel-open/nvidia-peermem/nv-p2p.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2011-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -132,11 +132,16 @@ struct nvidia_p2p_page {
    } registers;
 } nvidia_p2p_page_t;

-#define NVIDIA_P2P_PAGE_TABLE_VERSION   0x00010002
+#define NVIDIA_P2P_PAGE_TABLE_VERSION   0x00020000

 #define NVIDIA_P2P_PAGE_TABLE_VERSION_COMPATIBLE(p) \
    NVIDIA_P2P_VERSION_COMPATIBLE(p, NVIDIA_P2P_PAGE_TABLE_VERSION)

+/*
+ * Page Table Flags
+ */
+#define NVIDIA_P2P_PAGE_TABLE_FLAGS_CPU_CACHEABLE 0x1
+
 typedef
 struct nvidia_p2p_page_table {
    uint32_t version;
@@ -144,6 +149,7 @@ struct nvidia_p2p_page_table {
    struct nvidia_p2p_page **pages;
    uint32_t entries;
    uint8_t *gpu_uuid;
+    uint32_t flags;
 } nvidia_p2p_page_table_t;

 /*
@@ -153,6 +159,9 @@ struct nvidia_p2p_page_table {
 *
 *   This API only supports pinned, GPU-resident memory, such as that provided
 *   by cudaMalloc().
+ *   This API does not support Coherent Driver-based Memory Management(CDMM) mode.
+ *   CDMM allows coherent GPU memory to be managed by the driver and not the OS.
+ *   This is done by the driver not onlining the memory as a NUMA node.
 *
 *   This API may sleep.
 *
@@ -201,7 +210,7 @@ int nvidia_p2p_get_pages( uint64_t p2p_token, uint32_t va_space,
 *   accessible to a third-party device. The pages will persist until
 *   explicitly freed by nvidia_p2p_put_pages_persistent().
 *
- *   Persistent GPU memory mappings are not supported on PowerPC,
+ *   Persistent GPU memory mappings are not supported on
 *   MIG-enabled devices and vGPU.
 *
 *   This API only supports pinned, GPU-resident memory, such as that provided
@@ -453,35 +462,19 @@ typedef struct nvidia_p2p_rsync_reg_info {

 /*
 * @brief
- *   Gets rsync (GEN-ID) register information associated with the supported
- *   NPUs.
- *
- *   The caller would use the returned information {GPU device, NPU device,
- *   socket-id, cluster-id} to pick the optimal generation registers to issue
- *   RSYNC (NVLink HW flush).
- *
- *   The interface allocates structures to return the information, hence
- *   nvidia_p2p_put_rsync_registers() must be called to free the structures.
- *
- *   Note, cluster-id is hardcoded to zero as early system configurations would
- *   only support cluster mode i.e. all devices would share the same cluster-id
- *   (0). In the future, appropriate kernel support would be needed to query
- *   cluster-ids.
- *
- * @param[out]     reg_info
- *   A pointer to the rsync reg info structure.
+ *   This interface is no longer supported and will always return an error.  It
+ *   is left in place (for now) to allow third-party callers to build without
+ *   any errors.
 *
 * @Returns
- *   0 Upon successful completion. Otherwise, returns negative value.
+ *   -ENODEV
 */
 int nvidia_p2p_get_rsync_registers(nvidia_p2p_rsync_reg_info_t **reg_info);

 /*
 * @brief
- *   Frees the structures allocated by nvidia_p2p_get_rsync_registers().
- *
- * @param[in]     reg_info
- *   A pointer to the rsync reg info structure.
+ *   This interface is no longer supported.  It is left in place (for now) to
+ *   allow third-party callers to build without any errors.
 */
 void nvidia_p2p_put_rsync_registers(nvidia_p2p_rsync_reg_info_t *reg_info);

--- a/kernel-open/nvidia-peermem/nvidia-peermem.c
+++ b/kernel-open/nvidia-peermem/nvidia-peermem.c
@@ -242,6 +242,61 @@ err:
    return 0;
 }

+/* acquire return code: 1 mine, 0 - not mine */
+static int nv_mem_acquire_nc(unsigned long addr, size_t size, void *peer_mem_private_data,
+                             char *peer_mem_name, void **client_context)
+{
+
+    int ret = 0;
+    struct nv_mem_context *nv_mem_context;
+
+    nv_mem_context = kzalloc(sizeof *nv_mem_context, GFP_KERNEL);
+    if (!nv_mem_context)
+        /* Error case handled as not mine */
+        return 0;
+
+    nv_mem_context->pad1 = NV_MEM_CONTEXT_MAGIC;
+    nv_mem_context->page_virt_start = addr & GPU_PAGE_MASK;
+    nv_mem_context->page_virt_end   = (addr + size + GPU_PAGE_SIZE - 1) & GPU_PAGE_MASK;
+    nv_mem_context->mapped_size  = nv_mem_context->page_virt_end - nv_mem_context->page_virt_start;
+    nv_mem_context->pad2 = NV_MEM_CONTEXT_MAGIC;
+
+#ifdef NVIDIA_P2P_CAP_GET_PAGES_PERSISTENT_API
+    ret = nvidia_p2p_get_pages_persistent(nv_mem_context->page_virt_start,
+                                          nv_mem_context->mapped_size,
+                                          &nv_mem_context->page_table, 0);
+#else
+    ret = nvidia_p2p_get_pages(0, 0, nv_mem_context->page_virt_start, nv_mem_context->mapped_size,
+                               &nv_mem_context->page_table, NULL, NULL);
+#endif
+    if (ret < 0)
+        goto err;
+
+#ifdef NVIDIA_P2P_CAP_GET_PAGES_PERSISTENT_API
+    ret = nvidia_p2p_put_pages_persistent(nv_mem_context->page_virt_start,
+                                          nv_mem_context->page_table, 0);
+#else
+    ret = nvidia_p2p_put_pages(0, 0, nv_mem_context->page_virt_start,
+                               nv_mem_context->page_table);
+#endif
+    if (ret < 0) {
+        peer_err("nv_mem_acquire -- error %d while calling nvidia_p2p_put_pages()\n", ret);
+        goto err;
+    }
+
+    /* 1 means mine */
+    *client_context = nv_mem_context;
+    __module_get(THIS_MODULE);
+    return 1;
+
+err:
+    memset(nv_mem_context, 0, sizeof(*nv_mem_context));
+    kfree(nv_mem_context);
+
+    /* Error case handled as not mine */
+    return 0;
+}
+
 static int nv_dma_map(struct sg_table *sg_head, void *context,
                      struct device *dma_device, int dmasync,
                      int *nmap)
@@ -477,7 +532,7 @@ static int nv_mem_get_pages_nc(unsigned long addr,
 }

 static struct peer_memory_client nv_mem_client_nc = {
-    .acquire        = nv_mem_acquire,
+    .acquire        = nv_mem_acquire_nc,
    .get_pages      = nv_mem_get_pages_nc,
    .dma_map        = nv_dma_map,
    .dma_unmap      = nv_dma_unmap,
--- a/kernel-open/nvidia-uvm/clc86f.h
+++ b/kernel-open/nvidia-uvm/clc86f.h
@@ -1,51 +1,31 @@
-/*******************************************************************************
-    Copyright (c) 2012-2015 NVIDIA Corporation
-
-    Permission is hereby granted, free of charge, to any person obtaining a copy
-    of this software and associated documentation files (the "Software"), to
-    deal in the Software without restriction, including without limitation the
-    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-    sell copies of the Software, and to permit persons to whom the Software is
-    furnished to do so, subject to the following conditions:
-
-    The above copyright notice and this permission notice shall be
-    included in all copies or substantial portions of the Software.
-
-    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-    DEALINGS IN THE SOFTWARE.
-
-*******************************************************************************/
-
-
-#ifndef _clc86f_h_
-#define _clc86f_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "nvtypes.h"
-
-/* class HOPPER_CHANNEL_GPFIFO  */
 /*
- * Documentation for HOPPER_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
- * chapter "User Control Registers". It is documented as device NV_UDMA.
- * The GPFIFO format itself is also documented in dev_pbdma.ref,
- * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
- * chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
 *
- * Note there is no .mfs file for this class.
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
 */
+
+#ifndef __gh100_clc86f_h__
+#define __gh100_clc86f_h__
+
 #define  HOPPER_CHANNEL_GPFIFO_A                           (0x0000C86F)

-#define NVC86F_TYPEDEF                             HOPPER_CHANNELChannelGPFifoA
-
-/* dma flow control data structure */
 typedef volatile struct Nvc86fControl_struct {
 NvU32 Ignored00[0x010];        /*                                  0000-003f*/
 NvU32 Put;                     /* put offset, read/write           0040-0043*/
@@ -64,54 +44,7 @@ typedef volatile struct Nvc86fControl_struct {
 NvU32 Ignored05[0x5c];
 } Nvc86fControl, HopperAControlGPFifo;

-/* fields and values */
-#define NVC86F_NUMBER_OF_SUBCHANNELS                               (8)
 #define NVC86F_SET_OBJECT                                          (0x00000000)
-#define NVC86F_SET_OBJECT_NVCLASS                                         15:0
-#define NVC86F_SET_OBJECT_ENGINE                                         20:16
-#define NVC86F_SET_OBJECT_ENGINE_SW                                 0x0000001f
-#define NVC86F_ILLEGAL                                             (0x00000004)
-#define NVC86F_ILLEGAL_HANDLE                                             31:0
-#define NVC86F_NOP                                                 (0x00000008)
-#define NVC86F_NOP_HANDLE                                                 31:0
-#define NVC86F_SEMAPHOREA                                          (0x00000010)
-#define NVC86F_SEMAPHOREA_OFFSET_UPPER                                     7:0
-#define NVC86F_SEMAPHOREB                                          (0x00000014)
-#define NVC86F_SEMAPHOREB_OFFSET_LOWER                                    31:2
-#define NVC86F_SEMAPHOREC                                          (0x00000018)
-#define NVC86F_SEMAPHOREC_PAYLOAD                                         31:0
-#define NVC86F_SEMAPHORED                                          (0x0000001C)
-#define NVC86F_SEMAPHORED_OPERATION                                        4:0
-#define NVC86F_SEMAPHORED_OPERATION_ACQUIRE                         0x00000001
-#define NVC86F_SEMAPHORED_OPERATION_RELEASE                         0x00000002
-#define NVC86F_SEMAPHORED_OPERATION_ACQ_GEQ                         0x00000004
-#define NVC86F_SEMAPHORED_OPERATION_ACQ_AND                         0x00000008
-#define NVC86F_SEMAPHORED_OPERATION_REDUCTION                       0x00000010
-#define NVC86F_SEMAPHORED_ACQUIRE_SWITCH                                 12:12
-#define NVC86F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED                   0x00000000
-#define NVC86F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED                    0x00000001
-#define NVC86F_SEMAPHORED_RELEASE_WFI                                    20:20
-#define NVC86F_SEMAPHORED_RELEASE_WFI_EN                            0x00000000
-#define NVC86F_SEMAPHORED_RELEASE_WFI_DIS                           0x00000001
-#define NVC86F_SEMAPHORED_RELEASE_SIZE                                   24:24
-#define NVC86F_SEMAPHORED_RELEASE_SIZE_16BYTE                       0x00000000
-#define NVC86F_SEMAPHORED_RELEASE_SIZE_4BYTE                        0x00000001
-#define NVC86F_SEMAPHORED_REDUCTION                                      30:27
-#define NVC86F_SEMAPHORED_REDUCTION_MIN                             0x00000000
-#define NVC86F_SEMAPHORED_REDUCTION_MAX                             0x00000001
-#define NVC86F_SEMAPHORED_REDUCTION_XOR                             0x00000002
-#define NVC86F_SEMAPHORED_REDUCTION_AND                             0x00000003
-#define NVC86F_SEMAPHORED_REDUCTION_OR                              0x00000004
-#define NVC86F_SEMAPHORED_REDUCTION_ADD                             0x00000005
-#define NVC86F_SEMAPHORED_REDUCTION_INC                             0x00000006
-#define NVC86F_SEMAPHORED_REDUCTION_DEC                             0x00000007
-#define NVC86F_SEMAPHORED_FORMAT                                         31:31
-#define NVC86F_SEMAPHORED_FORMAT_SIGNED                             0x00000000
-#define NVC86F_SEMAPHORED_FORMAT_UNSIGNED                           0x00000001
-#define NVC86F_NON_STALL_INTERRUPT                                 (0x00000020)
-#define NVC86F_NON_STALL_INTERRUPT_HANDLE                                 31:0
-#define NVC86F_FB_FLUSH                                            (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR
-#define NVC86F_FB_FLUSH_HANDLE                                            31:0
 // NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
 // specifying the page address for a targeted TLB invalidate and the uTLB for
 // a targeted REPLAY_CANCEL for UVM.
@@ -206,67 +139,31 @@ typedef volatile struct Nvc86fControl_struct {
 #define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE                               23:20
 #define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED                 0x00000000
 #define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP   0x00000001
-#define NVC86F_SET_REFERENCE                                       (0x00000050)
-#define NVC86F_SET_REFERENCE_COUNT                                        31:0
 #define NVC86F_SEM_ADDR_LO                                         (0x0000005c)
 #define NVC86F_SEM_ADDR_LO_OFFSET                                         31:2
 #define NVC86F_SEM_ADDR_HI                                         (0x00000060)
 #define NVC86F_SEM_ADDR_HI_OFFSET                                         24:0
 #define NVC86F_SEM_PAYLOAD_LO                                      (0x00000064)
-#define NVC86F_SEM_PAYLOAD_LO_PAYLOAD                                     31:0
 #define NVC86F_SEM_PAYLOAD_HI                                      (0x00000068)
-#define NVC86F_SEM_PAYLOAD_HI_PAYLOAD                                     31:0
 #define NVC86F_SEM_EXECUTE                                         (0x0000006c)
 #define NVC86F_SEM_EXECUTE_OPERATION                                       2:0
 #define NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE                        0x00000000
 #define NVC86F_SEM_EXECUTE_OPERATION_RELEASE                        0x00000001
-#define NVC86F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ                 0x00000002
 #define NVC86F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ                   0x00000003
-#define NVC86F_SEM_EXECUTE_OPERATION_ACQ_AND                        0x00000004
-#define NVC86F_SEM_EXECUTE_OPERATION_ACQ_NOR                        0x00000005
-#define NVC86F_SEM_EXECUTE_OPERATION_REDUCTION                      0x00000006
 #define NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG                            12:12
-#define NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS                   0x00000000
 #define NVC86F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN                    0x00000001
 #define NVC86F_SEM_EXECUTE_RELEASE_WFI                                   20:20
 #define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS                          0x00000000
-#define NVC86F_SEM_EXECUTE_RELEASE_WFI_EN                           0x00000001
 #define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE                                  24:24
 #define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT                       0x00000000
-#define NVC86F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT                       0x00000001
 #define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP                             25:25
 #define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS                    0x00000000
 #define NVC86F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN                     0x00000001
-#define NVC86F_SEM_EXECUTE_REDUCTION                                     30:27
-#define NVC86F_SEM_EXECUTE_REDUCTION_IMIN                           0x00000000
-#define NVC86F_SEM_EXECUTE_REDUCTION_IMAX                           0x00000001
-#define NVC86F_SEM_EXECUTE_REDUCTION_IXOR                           0x00000002
-#define NVC86F_SEM_EXECUTE_REDUCTION_IAND                           0x00000003
-#define NVC86F_SEM_EXECUTE_REDUCTION_IOR                            0x00000004
-#define NVC86F_SEM_EXECUTE_REDUCTION_IADD                           0x00000005
-#define NVC86F_SEM_EXECUTE_REDUCTION_INC                            0x00000006
-#define NVC86F_SEM_EXECUTE_REDUCTION_DEC                            0x00000007
-#define NVC86F_SEM_EXECUTE_REDUCTION_FORMAT                              31:31
-#define NVC86F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED                  0x00000000
-#define NVC86F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED                0x00000001
 #define NVC86F_WFI                                                 (0x00000078)
 #define NVC86F_WFI_SCOPE                                                   0:0
 #define NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE                           0x00000000
 #define NVC86F_WFI_SCOPE_CURRENT_VEID                               0x00000000
 #define NVC86F_WFI_SCOPE_ALL                                        0x00000001
-#define NVC86F_YIELD                                               (0x00000080)
-#define NVC86F_YIELD_OP                                                    1:0
-#define NVC86F_YIELD_OP_NOP                                         0x00000000
-#define NVC86F_YIELD_OP_TSG                                         0x00000003
-#define NVC86F_CLEAR_FAULTED                                       (0x00000084)
-// Note: RM provides the HANDLE as an opaque value; the internal detail fields
-// are intentionally not exposed to the driver through these defines.
-#define NVC86F_CLEAR_FAULTED_HANDLE                                       30:0
-#define NVC86F_CLEAR_FAULTED_TYPE                                        31:31
-#define NVC86F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED                     0x00000000
-#define NVC86F_CLEAR_FAULTED_TYPE_ENG_FAULTED                       0x00000001
-#define NVC86F_QUADRO_VERIFY                                       (0x000000a0)
-

 /* GPFIFO entry format */
 #define NVC86F_GP_ENTRY__SIZE                                          8
@@ -291,85 +188,4 @@ typedef volatile struct Nvc86fControl_struct {
 #define NVC86F_GP_ENTRY1_OPCODE_PB_CRC                        0x00000003
 #define NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE  0x00000004

-/* dma method formats */
-#define NVC86F_DMA_METHOD_ADDRESS_OLD                              12:2
-#define NVC86F_DMA_METHOD_ADDRESS                                  11:0
-#define NVC86F_DMA_SUBDEVICE_MASK                                  15:4
-#define NVC86F_DMA_METHOD_SUBCHANNEL                               15:13
-#define NVC86F_DMA_TERT_OP                                         17:16
-#define NVC86F_DMA_TERT_OP_GRP0_INC_METHOD                         (0x00000000)
-#define NVC86F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK                   (0x00000001)
-#define NVC86F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK                 (0x00000002)
-#define NVC86F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK                   (0x00000003)
-#define NVC86F_DMA_TERT_OP_GRP2_NON_INC_METHOD                     (0x00000000)
-#define NVC86F_DMA_METHOD_COUNT_OLD                                28:18
-#define NVC86F_DMA_METHOD_COUNT                                    28:16
-#define NVC86F_DMA_IMMD_DATA                                       28:16
-#define NVC86F_DMA_SEC_OP                                          31:29
-#define NVC86F_DMA_SEC_OP_GRP0_USE_TERT                            (0x00000000)
-#define NVC86F_DMA_SEC_OP_INC_METHOD                               (0x00000001)
-#define NVC86F_DMA_SEC_OP_GRP2_USE_TERT                            (0x00000002)
-#define NVC86F_DMA_SEC_OP_NON_INC_METHOD                           (0x00000003)
-#define NVC86F_DMA_SEC_OP_IMMD_DATA_METHOD                         (0x00000004)
-#define NVC86F_DMA_SEC_OP_ONE_INC                                  (0x00000005)
-#define NVC86F_DMA_SEC_OP_RESERVED6                                (0x00000006)
-#define NVC86F_DMA_SEC_OP_END_PB_SEGMENT                           (0x00000007)
-/* dma incrementing method format */
-#define NVC86F_DMA_INCR_ADDRESS                                    11:0
-#define NVC86F_DMA_INCR_SUBCHANNEL                                 15:13
-#define NVC86F_DMA_INCR_COUNT                                      28:16
-#define NVC86F_DMA_INCR_OPCODE                                     31:29
-#define NVC86F_DMA_INCR_OPCODE_VALUE                               (0x00000001)
-#define NVC86F_DMA_INCR_DATA                                       31:0
-/* dma non-incrementing method format */
-#define NVC86F_DMA_NONINCR_ADDRESS                                 11:0
-#define NVC86F_DMA_NONINCR_SUBCHANNEL                              15:13
-#define NVC86F_DMA_NONINCR_COUNT                                   28:16
-#define NVC86F_DMA_NONINCR_OPCODE                                  31:29
-#define NVC86F_DMA_NONINCR_OPCODE_VALUE                            (0x00000003)
-#define NVC86F_DMA_NONINCR_DATA                                    31:0
-/* dma increment-once method format */
-#define NVC86F_DMA_ONEINCR_ADDRESS                                 11:0
-#define NVC86F_DMA_ONEINCR_SUBCHANNEL                              15:13
-#define NVC86F_DMA_ONEINCR_COUNT                                   28:16
-#define NVC86F_DMA_ONEINCR_OPCODE                                  31:29
-#define NVC86F_DMA_ONEINCR_OPCODE_VALUE                            (0x00000005)
-#define NVC86F_DMA_ONEINCR_DATA                                    31:0
-/* dma no-operation format */
-#define NVC86F_DMA_NOP                                             (0x00000000)
-/* dma immediate-data format */
-#define NVC86F_DMA_IMMD_ADDRESS                                    11:0
-#define NVC86F_DMA_IMMD_SUBCHANNEL                                 15:13
-#define NVC86F_DMA_IMMD_DATA                                       28:16
-#define NVC86F_DMA_IMMD_OPCODE                                     31:29
-#define NVC86F_DMA_IMMD_OPCODE_VALUE                               (0x00000004)
-/* dma set sub-device mask format */
-#define NVC86F_DMA_SET_SUBDEVICE_MASK_VALUE                        15:4
-#define NVC86F_DMA_SET_SUBDEVICE_MASK_OPCODE                       31:16
-#define NVC86F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE                 (0x00000001)
-/* dma store sub-device mask format */
-#define NVC86F_DMA_STORE_SUBDEVICE_MASK_VALUE                      15:4
-#define NVC86F_DMA_STORE_SUBDEVICE_MASK_OPCODE                     31:16
-#define NVC86F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE               (0x00000002)
-/* dma use sub-device mask format */
-#define NVC86F_DMA_USE_SUBDEVICE_MASK_OPCODE                       31:16
-#define NVC86F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE                 (0x00000003)
-/* dma end-segment format */
-#define NVC86F_DMA_ENDSEG_OPCODE                                   31:29
-#define NVC86F_DMA_ENDSEG_OPCODE_VALUE                             (0x00000007)
-/* dma legacy incrementing/non-incrementing formats */
-#define NVC86F_DMA_ADDRESS                                         12:2
-#define NVC86F_DMA_SUBCH                                           15:13
-#define NVC86F_DMA_OPCODE3                                         17:16
-#define NVC86F_DMA_OPCODE3_NONE                                    (0x00000000)
-#define NVC86F_DMA_COUNT                                           28:18
-#define NVC86F_DMA_OPCODE                                          31:29
-#define NVC86F_DMA_OPCODE_METHOD                                   (0x00000000)
-#define NVC86F_DMA_OPCODE_NONINC_METHOD                            (0x00000002)
-#define NVC86F_DMA_DATA                                            31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-
-#endif /* _clc86f_h_ */
+#endif // __gh100_clc86f_h__
--- a/kernel-open/nvidia-uvm/clc8b5.h
+++ b/kernel-open/nvidia-uvm/clc8b5.h
@@ -1,160 +1,46 @@
-/*******************************************************************************
-    Copyright (c) 1993-2004 NVIDIA Corporation
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */

-    Permission is hereby granted, free of charge, to any person obtaining a copy
-    of this software and associated documentation files (the "Software"), to
-    deal in the Software without restriction, including without limitation the
-    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-    sell copies of the Software, and to permit persons to whom the Software is
-    furnished to do so, subject to the following conditions:
+#ifndef __gh100_clc8b5_h__
+#define __gh100_clc8b5_h__

-    The above copyright notice and this permission notice shall be
-    included in all copies or substantial portions of the Software.
-
-    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-    DEALINGS IN THE SOFTWARE.
-
-*******************************************************************************/
-
-
-
-#include "nvtypes.h"
-
-#ifndef _clc8b5_h_
-#define _clc8b5_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define HOPPER_DMA_COPY_A                                                            (0x0000C8B5)
-
-typedef volatile struct _clc8b5_tag0 {
-    NvV32 Reserved00[0x40];
-    NvV32 Nop;                                                                  // 0x00000100 - 0x00000103
-    NvV32 Reserved01[0xF];
-    NvV32 PmTrigger;                                                            // 0x00000140 - 0x00000143
-    NvV32 Reserved02[0x36];
-    NvV32 SetMonitoredFenceType;                                                // 0x0000021C - 0x0000021F
-    NvV32 SetMonitoredFenceSignalAddrBaseUpper;                                 // 0x00000220 - 0x00000223
-    NvV32 SetMonitoredFenceSignalAddrBaseLower;                                 // 0x00000224 - 0x00000227
-    NvV32 Reserved03[0x6];
-    NvV32 SetSemaphoreA;                                                        // 0x00000240 - 0x00000243
-    NvV32 SetSemaphoreB;                                                        // 0x00000244 - 0x00000247
-    NvV32 SetSemaphorePayload;                                                  // 0x00000248 - 0x0000024B
-    NvV32 SetSemaphorePayloadUpper;                                             // 0x0000024C - 0x0000024F
-    NvV32 Reserved04[0x1];
-    NvV32 SetRenderEnableA;                                                     // 0x00000254 - 0x00000257
-    NvV32 SetRenderEnableB;                                                     // 0x00000258 - 0x0000025B
-    NvV32 SetRenderEnableC;                                                     // 0x0000025C - 0x0000025F
-    NvV32 SetSrcPhysMode;                                                       // 0x00000260 - 0x00000263
-    NvV32 SetDstPhysMode;                                                       // 0x00000264 - 0x00000267
-    NvV32 Reserved05[0x26];
-    NvV32 LaunchDma;                                                            // 0x00000300 - 0x00000303
-    NvV32 Reserved06[0x3F];
-    NvV32 OffsetInUpper;                                                        // 0x00000400 - 0x00000403
-    NvV32 OffsetInLower;                                                        // 0x00000404 - 0x00000407
-    NvV32 OffsetOutUpper;                                                       // 0x00000408 - 0x0000040B
-    NvV32 OffsetOutLower;                                                       // 0x0000040C - 0x0000040F
-    NvV32 PitchIn;                                                              // 0x00000410 - 0x00000413
-    NvV32 PitchOut;                                                             // 0x00000414 - 0x00000417
-    NvV32 LineLengthIn;                                                         // 0x00000418 - 0x0000041B
-    NvV32 LineCount;                                                            // 0x0000041C - 0x0000041F
-    NvV32 Reserved07[0x38];
-    NvV32 SetSecureCopyMode;                                                    // 0x00000500 - 0x00000503
-    NvV32 SetDecryptIv0;                                                        // 0x00000504 - 0x00000507
-    NvV32 SetDecryptIv1;                                                        // 0x00000508 - 0x0000050B
-    NvV32 SetDecryptIv2;                                                        // 0x0000050C - 0x0000050F
-    NvV32 Reserved_SetAESCounter;                                               // 0x00000510 - 0x00000513
-    NvV32 SetDecryptAuthTagCompareAddrUpper;                                    // 0x00000514 - 0x00000517
-    NvV32 SetDecryptAuthTagCompareAddrLower;                                    // 0x00000518 - 0x0000051B
-    NvV32 Reserved08[0x5];
-    NvV32 SetEncryptAuthTagAddrUpper;                                           // 0x00000530 - 0x00000533
-    NvV32 SetEncryptAuthTagAddrLower;                                           // 0x00000534 - 0x00000537
-    NvV32 SetEncryptIvAddrUpper;                                                // 0x00000538 - 0x0000053B
-    NvV32 SetEncryptIvAddrLower;                                                // 0x0000053C - 0x0000053F
-    NvV32 Reserved09[0x6F];
-    NvV32 SetMemoryScrubParameters;                                             // 0x000006FC - 0x000006FF
-    NvV32 SetRemapConstA;                                                       // 0x00000700 - 0x00000703
-    NvV32 SetRemapConstB;                                                       // 0x00000704 - 0x00000707
-    NvV32 SetRemapComponents;                                                   // 0x00000708 - 0x0000070B
-    NvV32 SetDstBlockSize;                                                      // 0x0000070C - 0x0000070F
-    NvV32 SetDstWidth;                                                          // 0x00000710 - 0x00000713
-    NvV32 SetDstHeight;                                                         // 0x00000714 - 0x00000717
-    NvV32 SetDstDepth;                                                          // 0x00000718 - 0x0000071B
-    NvV32 SetDstLayer;                                                          // 0x0000071C - 0x0000071F
-    NvV32 SetDstOrigin;                                                         // 0x00000720 - 0x00000723
-    NvV32 Reserved10[0x1];
-    NvV32 SetSrcBlockSize;                                                      // 0x00000728 - 0x0000072B
-    NvV32 SetSrcWidth;                                                          // 0x0000072C - 0x0000072F
-    NvV32 SetSrcHeight;                                                         // 0x00000730 - 0x00000733
-    NvV32 SetSrcDepth;                                                          // 0x00000734 - 0x00000737
-    NvV32 SetSrcLayer;                                                          // 0x00000738 - 0x0000073B
-    NvV32 SetSrcOrigin;                                                         // 0x0000073C - 0x0000073F
-    NvV32 Reserved11[0x1];
-    NvV32 SrcOriginX;                                                           // 0x00000744 - 0x00000747
-    NvV32 SrcOriginY;                                                           // 0x00000748 - 0x0000074B
-    NvV32 DstOriginX;                                                           // 0x0000074C - 0x0000074F
-    NvV32 DstOriginY;                                                           // 0x00000750 - 0x00000753
-    NvV32 Reserved12[0x270];
-    NvV32 PmTriggerEnd;                                                         // 0x00001114 - 0x00001117
-    NvV32 Reserved13[0x3BA];
-} hopper_dma_copy_aControlPio;
-
-#define NVC8B5_NOP                                                              (0x00000100)
-#define NVC8B5_NOP_PARAMETER                                                    31:0
-#define NVC8B5_PM_TRIGGER                                                       (0x00000140)
-#define NVC8B5_PM_TRIGGER_V                                                     31:0
-#define NVC8B5_SET_MONITORED_FENCE_TYPE                                         (0x0000021C)
-#define NVC8B5_SET_MONITORED_FENCE_TYPE_TYPE                                    0:0
-#define NVC8B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE                    (0x00000000)
-#define NVC8B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT                (0x00000001)
-#define NVC8B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER                       (0x00000220)
-#define NVC8B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER                 24:0
-#define NVC8B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER                       (0x00000224)
-#define NVC8B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER                 31:0
+#define HOPPER_DMA_COPY_A                                                       (0x0000C8B5)
 #define NVC8B5_SET_SEMAPHORE_A                                                  (0x00000240)
 #define NVC8B5_SET_SEMAPHORE_A_UPPER                                            24:0
 #define NVC8B5_SET_SEMAPHORE_B                                                  (0x00000244)
 #define NVC8B5_SET_SEMAPHORE_B_LOWER                                            31:0
 #define NVC8B5_SET_SEMAPHORE_PAYLOAD                                            (0x00000248)
-#define NVC8B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD                                    31:0
-#define NVC8B5_SET_SEMAPHORE_PAYLOAD_UPPER                                      (0x0000024C)
-#define NVC8B5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD                              31:0
-#define NVC8B5_SET_RENDER_ENABLE_A                                              (0x00000254)
-#define NVC8B5_SET_RENDER_ENABLE_A_UPPER                                        24:0
-#define NVC8B5_SET_RENDER_ENABLE_B                                              (0x00000258)
-#define NVC8B5_SET_RENDER_ENABLE_B_LOWER                                        31:0
-#define NVC8B5_SET_RENDER_ENABLE_C                                              (0x0000025C)
-#define NVC8B5_SET_RENDER_ENABLE_C_MODE                                         2:0
-#define NVC8B5_SET_RENDER_ENABLE_C_MODE_FALSE                                   (0x00000000)
-#define NVC8B5_SET_RENDER_ENABLE_C_MODE_TRUE                                    (0x00000001)
-#define NVC8B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                             (0x00000002)
-#define NVC8B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                         (0x00000003)
-#define NVC8B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                     (0x00000004)
-#define NVC8B5_SET_SRC_PHYS_MODE                                                (0x00000260)
 #define NVC8B5_SET_SRC_PHYS_MODE_TARGET                                         1:0
 #define NVC8B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB                                (0x00000000)
 #define NVC8B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM                         (0x00000001)
-#define NVC8B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM                      (0x00000002)
 #define NVC8B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM                                 (0x00000003)
-#define NVC8B5_SET_SRC_PHYS_MODE_BASIC_KIND                                     5:2
 #define NVC8B5_SET_SRC_PHYS_MODE_PEER_ID                                        8:6
 #define NVC8B5_SET_SRC_PHYS_MODE_FLA                                            9:9
 #define NVC8B5_SET_DST_PHYS_MODE                                                (0x00000264)
 #define NVC8B5_SET_DST_PHYS_MODE_TARGET                                         1:0
 #define NVC8B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB                                (0x00000000)
 #define NVC8B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM                         (0x00000001)
-#define NVC8B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM                      (0x00000002)
 #define NVC8B5_SET_DST_PHYS_MODE_TARGET_PEERMEM                                 (0x00000003)
-#define NVC8B5_SET_DST_PHYS_MODE_BASIC_KIND                                     5:2
-#define NVC8B5_SET_DST_PHYS_MODE_PEER_ID                                        8:6
-#define NVC8B5_SET_DST_PHYS_MODE_FLA                                            9:9
 #define NVC8B5_LAUNCH_DMA                                                       (0x00000300)
 #define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE                                    1:0
 #define NVC8B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE                               (0x00000000)
@@ -167,80 +53,41 @@ typedef volatile struct _clc8b5_tag0 {
 #define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_SYS                                        (0x00000000)
 #define NVC8B5_LAUNCH_DMA_FLUSH_TYPE_GL                                         (0x00000001)
 #define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE                                        4:3
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE                                   (0x00000000)
 #define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP         (0x00000001)
 #define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP       (0x00000002)
 #define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE             (0x00000001)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE            (0x00000002)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE     (0x00000003)
-#define NVC8B5_LAUNCH_DMA_INTERRUPT_TYPE                                        6:5
-#define NVC8B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                   (0x00000000)
-#define NVC8B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING                               (0x00000001)
-#define NVC8B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING                           (0x00000002)
 #define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT                                     7:7
-#define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR                         (0x00000000)
 #define NVC8B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH                               (0x00000001)
 #define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT                                     8:8
-#define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                         (0x00000000)
 #define NVC8B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                               (0x00000001)
 #define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE                                     9:9
 #define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE                               (0x00000000)
-#define NVC8B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE                                (0x00000001)
 #define NVC8B5_LAUNCH_DMA_REMAP_ENABLE                                          10:10
 #define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_FALSE                                    (0x00000000)
 #define NVC8B5_LAUNCH_DMA_REMAP_ENABLE_TRUE                                     (0x00000001)
-#define NVC8B5_LAUNCH_DMA_FORCE_RMWDISABLE                                      11:11
-#define NVC8B5_LAUNCH_DMA_FORCE_RMWDISABLE_FALSE                                (0x00000000)
-#define NVC8B5_LAUNCH_DMA_FORCE_RMWDISABLE_TRUE                                 (0x00000001)
 #define NVC8B5_LAUNCH_DMA_SRC_TYPE                                              12:12
-#define NVC8B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL                                      (0x00000000)
 #define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL                                     (0x00000001)
 #define NVC8B5_LAUNCH_DMA_DST_TYPE                                              13:13
 #define NVC8B5_LAUNCH_DMA_DST_TYPE_VIRTUAL                                      (0x00000000)
 #define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL                                     (0x00000001)
 #define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION                                   17:14
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN                              (0x00000000)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX                              (0x00000001)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR                              (0x00000002)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND                              (0x00000003)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR                               (0x00000004)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD                              (0x00000005)
 #define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC                               (0x00000006)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC                               (0x00000007)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA                          (0x00000008)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB                          (0x00000009)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD                              (0x0000000A)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN                              (0x0000000B)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX                              (0x0000000C)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC                          (0x0000000D)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD                          (0x0000000E)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE                          (0x0000000F)
 #define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN                              18:18
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED                       (0x00000000)
 #define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED                     (0x00000001)
 #define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE                            19:19
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE                      (0x00000000)
 #define NVC8B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE                       (0x00000001)
 #define NVC8B5_LAUNCH_DMA_COPY_TYPE                                             21:20
 #define NVC8B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT                                   (0x00000000)
 #define NVC8B5_LAUNCH_DMA_COPY_TYPE_DEFAULT                                     (0x00000000)
 #define NVC8B5_LAUNCH_DMA_COPY_TYPE_SECURE                                      (0x00000001)
 #define NVC8B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT                             (0x00000002)
-#define NVC8B5_LAUNCH_DMA_COPY_TYPE_RESERVED                                    (0x00000003)
-#define NVC8B5_LAUNCH_DMA_VPRMODE                                               22:22
-#define NVC8B5_LAUNCH_DMA_VPRMODE_VPR_NONE                                      (0x00000000)
-#define NVC8B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID                                   (0x00000001)
 #define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE                                   23:23
 #define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE                             (0x00000000)
 #define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE                              (0x00000001)
-#define NVC8B5_LAUNCH_DMA_RESERVED_START_OF_COPY                                24:24
 #define NVC8B5_LAUNCH_DMA_DISABLE_PLC                                           26:26
-#define NVC8B5_LAUNCH_DMA_DISABLE_PLC_FALSE                                     (0x00000000)
 #define NVC8B5_LAUNCH_DMA_DISABLE_PLC_TRUE                                      (0x00000001)
 #define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE                                27:27
 #define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD                       (0x00000000)
-#define NVC8B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD                       (0x00000001)
-#define NVC8B5_LAUNCH_DMA_RESERVED_ERR_CODE                                     31:28
 #define NVC8B5_OFFSET_IN_UPPER                                                  (0x00000400)
 #define NVC8B5_OFFSET_IN_UPPER_UPPER                                            24:0
 #define NVC8B5_OFFSET_IN_LOWER                                                  (0x00000404)
@@ -249,41 +96,11 @@ typedef volatile struct _clc8b5_tag0 {
 #define NVC8B5_OFFSET_OUT_UPPER_UPPER                                           24:0
 #define NVC8B5_OFFSET_OUT_LOWER                                                 (0x0000040C)
 #define NVC8B5_OFFSET_OUT_LOWER_VALUE                                           31:0
-#define NVC8B5_PITCH_IN                                                         (0x00000410)
-#define NVC8B5_PITCH_IN_VALUE                                                   31:0
-#define NVC8B5_PITCH_OUT                                                        (0x00000414)
-#define NVC8B5_PITCH_OUT_VALUE                                                  31:0
 #define NVC8B5_LINE_LENGTH_IN                                                   (0x00000418)
-#define NVC8B5_LINE_LENGTH_IN_VALUE                                             31:0
-#define NVC8B5_LINE_COUNT                                                       (0x0000041C)
-#define NVC8B5_LINE_COUNT_VALUE                                                 31:0
 #define NVC8B5_SET_SECURE_COPY_MODE                                             (0x00000500)
 #define NVC8B5_SET_SECURE_COPY_MODE_MODE                                        0:0
 #define NVC8B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT                                (0x00000000)
 #define NVC8B5_SET_SECURE_COPY_MODE_MODE_DECRYPT                                (0x00000001)
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET                         20:19
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_LOCAL_FB                (0x00000000)
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_COHERENT_SYSMEM         (0x00000001)
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_NONCOHERENT_SYSMEM      (0x00000002)
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_PEERMEM                 (0x00000003)
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_PEER_ID                        23:21
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_SRC_FLA                            24:24
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET                         26:25
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_LOCAL_FB                (0x00000000)
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_COHERENT_SYSMEM         (0x00000001)
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_NONCOHERENT_SYSMEM      (0x00000002)
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_PEERMEM                 (0x00000003)
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_PEER_ID                        29:27
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_DST_FLA                            30:30
-#define NVC8B5_SET_SECURE_COPY_MODE_RESERVED_END_OF_COPY                        31:31
-#define NVC8B5_SET_DECRYPT_IV0                                                  (0x00000504)
-#define NVC8B5_SET_DECRYPT_IV0_VALUE                                            31:0
-#define NVC8B5_SET_DECRYPT_IV1                                                  (0x00000508)
-#define NVC8B5_SET_DECRYPT_IV1_VALUE                                            31:0
-#define NVC8B5_SET_DECRYPT_IV2                                                  (0x0000050C)
-#define NVC8B5_SET_DECRYPT_IV2_VALUE                                            31:0
-#define NVC8B5_RESERVED_SET_AESCOUNTER                                          (0x00000510)
-#define NVC8B5_RESERVED_SET_AESCOUNTER_VALUE                                    31:0
 #define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER                          (0x00000514)
 #define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER                    24:0
 #define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER                          (0x00000518)
@@ -299,132 +116,18 @@ typedef volatile struct _clc8b5_tag0 {
 #define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS                                      (0x000006FC)
 #define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE                          0:0
 #define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE                    (0x00000000)
-#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE                     (0x00000001)
 #define NVC8B5_SET_REMAP_CONST_A                                                (0x00000700)
-#define NVC8B5_SET_REMAP_CONST_A_V                                              31:0
 #define NVC8B5_SET_REMAP_CONST_B                                                (0x00000704)
-#define NVC8B5_SET_REMAP_CONST_B_V                                              31:0
 #define NVC8B5_SET_REMAP_COMPONENTS                                             (0x00000708)
 #define NVC8B5_SET_REMAP_COMPONENTS_DST_X                                       2:0
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_SRC_X                                 (0x00000000)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y                                 (0x00000001)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z                                 (0x00000002)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_SRC_W                                 (0x00000003)
 #define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_A                               (0x00000004)
 #define NVC8B5_SET_REMAP_COMPONENTS_DST_X_CONST_B                               (0x00000005)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE                              (0x00000006)
 #define NVC8B5_SET_REMAP_COMPONENTS_DST_Y                                       6:4
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X                                 (0x00000000)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y                                 (0x00000001)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z                                 (0x00000002)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W                                 (0x00000003)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A                               (0x00000004)
 #define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B                               (0x00000005)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE                              (0x00000006)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z                                       10:8
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X                                 (0x00000000)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y                                 (0x00000001)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z                                 (0x00000002)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W                                 (0x00000003)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A                               (0x00000004)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B                               (0x00000005)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE                              (0x00000006)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_W                                       14:12
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_SRC_X                                 (0x00000000)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y                                 (0x00000001)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z                                 (0x00000002)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_SRC_W                                 (0x00000003)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_CONST_A                               (0x00000004)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_CONST_B                               (0x00000005)
-#define NVC8B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE                              (0x00000006)
 #define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE                              17:16
 #define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE                          (0x00000000)
-#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO                          (0x00000001)
-#define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE                        (0x00000002)
 #define NVC8B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR                         (0x00000003)
-#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS                          21:20
-#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE                      (0x00000000)
-#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO                      (0x00000001)
-#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE                    (0x00000002)
-#define NVC8B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR                     (0x00000003)
 #define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS                          25:24
 #define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE                      (0x00000000)
 #define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO                      (0x00000001)
-#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE                    (0x00000002)
-#define NVC8B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR                     (0x00000003)
-#define NVC8B5_SET_DST_BLOCK_SIZE                                               (0x0000070C)
-#define NVC8B5_SET_DST_BLOCK_SIZE_WIDTH                                         3:0
-#define NVC8B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                 (0x00000000)
-#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT                                        7:4
-#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                (0x00000000)
-#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                               (0x00000001)
-#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                              (0x00000002)
-#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                             (0x00000003)
-#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                           (0x00000004)
-#define NVC8B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                         (0x00000005)
-#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH                                         11:8
-#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                 (0x00000000)
-#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                (0x00000001)
-#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                               (0x00000002)
-#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                              (0x00000003)
-#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                            (0x00000004)
-#define NVC8B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                          (0x00000005)
-#define NVC8B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT                                    15:12
-#define NVC8B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8                 (0x00000001)
-#define NVC8B5_SET_DST_WIDTH                                                    (0x00000710)
-#define NVC8B5_SET_DST_WIDTH_V                                                  31:0
-#define NVC8B5_SET_DST_HEIGHT                                                   (0x00000714)
-#define NVC8B5_SET_DST_HEIGHT_V                                                 31:0
-#define NVC8B5_SET_DST_DEPTH                                                    (0x00000718)
-#define NVC8B5_SET_DST_DEPTH_V                                                  31:0
-#define NVC8B5_SET_DST_LAYER                                                    (0x0000071C)
-#define NVC8B5_SET_DST_LAYER_V                                                  31:0
-#define NVC8B5_SET_DST_ORIGIN                                                   (0x00000720)
-#define NVC8B5_SET_DST_ORIGIN_X                                                 15:0
-#define NVC8B5_SET_DST_ORIGIN_Y                                                 31:16
-#define NVC8B5_SET_SRC_BLOCK_SIZE                                               (0x00000728)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_WIDTH                                         3:0
-#define NVC8B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB                                 (0x00000000)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT                                        7:4
-#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB                                (0x00000000)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS                               (0x00000001)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS                              (0x00000002)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                             (0x00000003)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                           (0x00000004)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                         (0x00000005)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH                                         11:8
-#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB                                 (0x00000000)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS                                (0x00000001)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS                               (0x00000002)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS                              (0x00000003)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                            (0x00000004)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                          (0x00000005)
-#define NVC8B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT                                    15:12
-#define NVC8B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8                 (0x00000001)
-#define NVC8B5_SET_SRC_WIDTH                                                    (0x0000072C)
-#define NVC8B5_SET_SRC_WIDTH_V                                                  31:0
-#define NVC8B5_SET_SRC_HEIGHT                                                   (0x00000730)
-#define NVC8B5_SET_SRC_HEIGHT_V                                                 31:0
-#define NVC8B5_SET_SRC_DEPTH                                                    (0x00000734)
-#define NVC8B5_SET_SRC_DEPTH_V                                                  31:0
-#define NVC8B5_SET_SRC_LAYER                                                    (0x00000738)
-#define NVC8B5_SET_SRC_LAYER_V                                                  31:0
-#define NVC8B5_SET_SRC_ORIGIN                                                   (0x0000073C)
-#define NVC8B5_SET_SRC_ORIGIN_X                                                 15:0
-#define NVC8B5_SET_SRC_ORIGIN_Y                                                 31:16
-#define NVC8B5_SRC_ORIGIN_X                                                     (0x00000744)
-#define NVC8B5_SRC_ORIGIN_X_VALUE                                               31:0
-#define NVC8B5_SRC_ORIGIN_Y                                                     (0x00000748)
-#define NVC8B5_SRC_ORIGIN_Y_VALUE                                               31:0
-#define NVC8B5_DST_ORIGIN_X                                                     (0x0000074C)
-#define NVC8B5_DST_ORIGIN_X_VALUE                                               31:0
-#define NVC8B5_DST_ORIGIN_Y                                                     (0x00000750)
-#define NVC8B5_DST_ORIGIN_Y_VALUE                                               31:0
-#define NVC8B5_PM_TRIGGER_END                                                   (0x00001114)
-#define NVC8B5_PM_TRIGGER_END_V                                                 31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _clc8b5_h
-
+#endif // __gh100_clc8b5_h__
--- a/kernel-open/nvidia-uvm/clc96f.h
+++ b/kernel-open/nvidia-uvm/clc96f.h
@@ -1,84 +1,42 @@
-/*******************************************************************************
-    Copyright (c) 2012-2015 NVIDIA Corporation
-
-    Permission is hereby granted, free of charge, to any person obtaining a copy
-    of this software and associated documentation files (the "Software"), to
-    deal in the Software without restriction, including without limitation the
-    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-    sell copies of the Software, and to permit persons to whom the Software is
-    furnished to do so, subject to the following conditions:
-
-    The above copyright notice and this permission notice shall be
-    included in all copies or substantial portions of the Software.
-
-    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-    DEALINGS IN THE SOFTWARE.
-
-*******************************************************************************/
-
-
-#ifndef _clc96f_h_
-#define _clc96f_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "nvtypes.h"
-
-/* class BLACKWELL_CHANNEL_GPFIFO  */
 /*
- * Documentation for BLACKWELL_CHANNEL_GPFIFO can be found in dev_pbdma.ref,
- * chapter "User Control Registers". It is documented as device NV_UDMA.
- * The GPFIFO format itself is also documented in dev_pbdma.ref,
- * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref,
- * chapter "FIFO DMA RAM", NV_FIFO_DMA_*.
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
 *
- * Note there is no .mfs file for this class.
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
 */
+
+#ifndef __gb100_clc96f_h__
+#define __gb100_clc96f_h__
+
 #define  BLACKWELL_CHANNEL_GPFIFO_A                           (0x0000C96F)

-#define NVC96F_TYPEDEF                             BLACKWELL_CHANNELChannelGPFifoA
-
-/* dma flow control data structure */
 typedef volatile struct Nvc96fControl_struct {
 NvU32 Ignored00[0x23];        /*                                  0000-008b*/
 NvU32 GPPut;                   /* GP FIFO put offset               008c-008f*/
 NvU32 Ignored01[0x5c];
 } Nvc96fControl, BlackwellAControlGPFifo;

-/* fields and values */
-#define NVC96F_NUMBER_OF_SUBCHANNELS                               (8)
 #define NVC96F_SET_OBJECT                                          (0x00000000)
-#define NVC96F_SET_OBJECT_NVCLASS                                         15:0
-#define NVC96F_SET_OBJECT_ENGINE                                         20:16
-#define NVC96F_SET_OBJECT_ENGINE_SW                                 0x0000001f
-#define NVC96F_NOP                                                 (0x00000008)
-#define NVC96F_NOP_HANDLE                                                 31:0
-#define NVC96F_NON_STALL_INTERRUPT                                 (0x00000020)
-#define NVC96F_NON_STALL_INTERRUPT_HANDLE                                 31:0
-#define NVC96F_FB_FLUSH                                            (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR
-#define NVC96F_FB_FLUSH_HANDLE                                            31:0
-// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
-// specifying the page address for a targeted TLB invalidate and the uTLB for
-// a targeted REPLAY_CANCEL for UVM.
-// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly
-// rearranged fields.
 #define NVC96F_MEM_OP_A                                            (0x00000028)
-#define NVC96F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID        5:0  // only relevant for REPLAY_CANCEL_TARGETED
 #define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE                   5:0  // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type
-#define NVC96F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID               10:6  // only relevant for REPLAY_CANCEL_TARGETED
 #define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE                         7:6  // only relevant for invalidates with NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE for invalidating  link TLB only, or non-link TLB only or all TLBs
-#define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS                  0
-#define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS                 1
 #define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS             2
-#define NVC96F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD                    3
-#define NVC96F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID                8:0  // only relevant for REPLAY_CANCEL_VA_GLOBAL
 #define NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR                         11:11
 #define NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN                 0x00000001
 #define NVC96F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS                0x00000000
@@ -86,9 +44,6 @@ typedef volatile struct Nvc96fControl_struct {
 #define NVC96F_MEM_OP_B                                            (0x0000002c)
 #define NVC96F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI                     31:0
 #define NVC96F_MEM_OP_C                                            (0x00000030)
-#define NVC96F_MEM_OP_C_MEMBAR_TYPE                                        2:0
-#define NVC96F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR                      0x00000000
-#define NVC96F_MEM_OP_C_MEMBAR_TYPE_MEMBAR                          0x00000001
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB                                 0:0
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE                      0x00000000
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL                      0x00000001  // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
@@ -97,130 +52,40 @@ typedef volatile struct Nvc96fControl_struct {
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE                  0x00000001
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY                              4:2  // only relevant if GPC ENABLE
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE                  0x00000000
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START                 0x00000001
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL         0x00000002
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED       0x00000003
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL         0x00000004
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL      0x00000005
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE                            6:5  // only relevant if GPC ENABLE
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE                0x00000000
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY            0x00000001
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE           0x00000002
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE                         9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ                 0
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE                1
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG        2
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD               3
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK          4
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL           5
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC     6
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL                  7
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL                    9:7  // Invalidate affects this level and all below
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL         0x00000000  // Invalidate tlb caches at all levels of the page table
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY    0x00000001
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0  0x00000002
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1  0x00000003
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2  0x00000004
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3  0x00000005
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4  0x00000006
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5  0x00000007
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE                          11:10  // only relevant if PDB_ONE
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM             0x00000000
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT    0x00000002
-#define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003
 #define NVC96F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO                       31:12  // only relevant if PDB_ONE
-#define NVC96F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG            19:0
-// MEM_OP_D MUST be preceded by MEM_OPs A-C.
+
 #define NVC96F_MEM_OP_D                                            (0x00000034)
 #define NVC96F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI                        26:0  // only relevant if PDB_ONE
 #define NVC96F_MEM_OP_D_OPERATION                                        31:27
-#define NVC96F_MEM_OP_D_OPERATION_MEMBAR                            0x00000005
 #define NVC96F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE                0x00000009
 #define NVC96F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED       0x0000000a
-#define NVC96F_MEM_OP_D_OPERATION_MMU_OPERATION                     0x0000000b
-#define NVC96F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE             0x0000000d
-#define NVC96F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE              0x0000000e
-// CLEAN_LINES is an alias for Tegra/GPU IP usage
-#define NVC96F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES         0x0000000e
-#define NVC96F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS                 0x0000000f
 #define NVC96F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY                    0x00000010
 #define NVC96F_MEM_OP_D_OPERATION_L2_SYSMEM_NCOH_INVALIDATE         0x00000011
-#define NVC96F_MEM_OP_D_OPERATION_L2_SYSMEM_COH_INVALIDATE          0x00000012
-#define NVC96F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS     0x00000015
-#define NVC96F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR                0x00000016
-#define NVC96F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE                            1:0
-#define NVC96F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC                0x00000000
-#define NVC96F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC                0x00000001
-#define NVC96F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL                 0x00000002
-#define NVC96F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED            0x00000003
-#define NVC96F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE                   2:2
-#define NVC96F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC       0x00000000
-#define NVC96F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC       0x00000001
-#define NVC96F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK                   6:3
-#define NVC96F_MEM_OP_D_MMU_OPERATION_TYPE                               23:20
-#define NVC96F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED                 0x00000000
-#define NVC96F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP   0x00000001
+
 #define NVC96F_SEM_ADDR_LO                                         (0x0000005c)
 #define NVC96F_SEM_ADDR_LO_OFFSET                                         31:2
 #define NVC96F_SEM_ADDR_HI                                         (0x00000060)
 #define NVC96F_SEM_ADDR_HI_OFFSET                                         24:0
 #define NVC96F_SEM_PAYLOAD_LO                                      (0x00000064)
-#define NVC96F_SEM_PAYLOAD_LO_PAYLOAD                                     31:0
 #define NVC96F_SEM_PAYLOAD_HI                                      (0x00000068)
-#define NVC96F_SEM_PAYLOAD_HI_PAYLOAD                                     31:0
 #define NVC96F_SEM_EXECUTE                                         (0x0000006c)
 #define NVC96F_SEM_EXECUTE_OPERATION                                       2:0
 #define NVC96F_SEM_EXECUTE_OPERATION_ACQUIRE                        0x00000000
 #define NVC96F_SEM_EXECUTE_OPERATION_RELEASE                        0x00000001
-#define NVC96F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ                 0x00000002
-#define NVC96F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ                   0x00000003
-#define NVC96F_SEM_EXECUTE_OPERATION_ACQ_AND                        0x00000004
-#define NVC96F_SEM_EXECUTE_OPERATION_ACQ_NOR                        0x00000005
-#define NVC96F_SEM_EXECUTE_OPERATION_REDUCTION                      0x00000006
-#define NVC96F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG                            12:12
-#define NVC96F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS                   0x00000000
-#define NVC96F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN                    0x00000001
-#define NVC96F_SEM_EXECUTE_ACQUIRE_RECHECK                               18:18
-#define NVC96F_SEM_EXECUTE_ACQUIRE_RECHECK_DIS                      0x00000000
-#define NVC96F_SEM_EXECUTE_ACQUIRE_RECHECK_EN                       0x00000001
 #define NVC96F_SEM_EXECUTE_RELEASE_WFI                                   20:20
 #define NVC96F_SEM_EXECUTE_RELEASE_WFI_DIS                          0x00000000
-#define NVC96F_SEM_EXECUTE_RELEASE_WFI_EN                           0x00000001
 #define NVC96F_SEM_EXECUTE_PAYLOAD_SIZE                                  24:24
 #define NVC96F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT                       0x00000000
-#define NVC96F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT                       0x00000001
-#define NVC96F_SEM_EXECUTE_RELEASE_TIMESTAMP                             25:25
-#define NVC96F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS                    0x00000000
-#define NVC96F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN                     0x00000001
-#define NVC96F_SEM_EXECUTE_REDUCTION                                     30:27
-#define NVC96F_SEM_EXECUTE_REDUCTION_IMIN                           0x00000000
-#define NVC96F_SEM_EXECUTE_REDUCTION_IMAX                           0x00000001
-#define NVC96F_SEM_EXECUTE_REDUCTION_IXOR                           0x00000002
-#define NVC96F_SEM_EXECUTE_REDUCTION_IAND                           0x00000003
-#define NVC96F_SEM_EXECUTE_REDUCTION_IOR                            0x00000004
-#define NVC96F_SEM_EXECUTE_REDUCTION_IADD                           0x00000005
-#define NVC96F_SEM_EXECUTE_REDUCTION_INC                            0x00000006
-#define NVC96F_SEM_EXECUTE_REDUCTION_DEC                            0x00000007
-#define NVC96F_SEM_EXECUTE_REDUCTION_FORMAT                              31:31
-#define NVC96F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED                  0x00000000
-#define NVC96F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED                0x00000001
-#define NVC96F_WFI                                                 (0x00000078)
-#define NVC96F_WFI_SCOPE                                                   0:0
-#define NVC96F_WFI_SCOPE_CURRENT_SCG_TYPE                           0x00000000
-#define NVC96F_WFI_SCOPE_CURRENT_VEID                               0x00000000
-#define NVC96F_WFI_SCOPE_ALL                                        0x00000001
-#define NVC96F_YIELD                                               (0x00000080)
-#define NVC96F_YIELD_OP                                                    1:0
-#define NVC96F_YIELD_OP_NOP                                         0x00000000
-#define NVC96F_YIELD_OP_TSG                                         0x00000003
-#define NVC96F_CLEAR_FAULTED                                       (0x00000084)
-// Note: RM provides the HANDLE as an opaque value; the internal detail fields
-// are intentionally not exposed to the driver through these defines.
-#define NVC96F_CLEAR_FAULTED_HANDLE                                       30:0
-#define NVC96F_CLEAR_FAULTED_TYPE                                        31:31
-#define NVC96F_CLEAR_FAULTED_TYPE_PBDMA_FAULTED                     0x00000000
-#define NVC96F_CLEAR_FAULTED_TYPE_ENG_FAULTED                       0x00000001
-

 /* GPFIFO entry format */
 #define NVC96F_GP_ENTRY__SIZE                                          8
@@ -245,85 +110,4 @@ typedef volatile struct Nvc96fControl_struct {
 #define NVC96F_GP_ENTRY1_OPCODE_PB_CRC                        0x00000003
 #define NVC96F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE  0x00000004

-/* dma method formats */
-#define NVC96F_DMA_METHOD_ADDRESS_OLD                              12:2
-#define NVC96F_DMA_METHOD_ADDRESS                                  11:0
-#define NVC96F_DMA_SUBDEVICE_MASK                                  15:4
-#define NVC96F_DMA_METHOD_SUBCHANNEL                               15:13
-#define NVC96F_DMA_TERT_OP                                         17:16
-#define NVC96F_DMA_TERT_OP_GRP0_INC_METHOD                         (0x00000000)
-#define NVC96F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK                   (0x00000001)
-#define NVC96F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK                 (0x00000002)
-#define NVC96F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK                   (0x00000003)
-#define NVC96F_DMA_TERT_OP_GRP2_NON_INC_METHOD                     (0x00000000)
-#define NVC96F_DMA_METHOD_COUNT_OLD                                28:18
-#define NVC96F_DMA_METHOD_COUNT                                    28:16
-#define NVC96F_DMA_IMMD_DATA                                       28:16
-#define NVC96F_DMA_SEC_OP                                          31:29
-#define NVC96F_DMA_SEC_OP_GRP0_USE_TERT                            (0x00000000)
-#define NVC96F_DMA_SEC_OP_INC_METHOD                               (0x00000001)
-#define NVC96F_DMA_SEC_OP_GRP2_USE_TERT                            (0x00000002)
-#define NVC96F_DMA_SEC_OP_NON_INC_METHOD                           (0x00000003)
-#define NVC96F_DMA_SEC_OP_IMMD_DATA_METHOD                         (0x00000004)
-#define NVC96F_DMA_SEC_OP_ONE_INC                                  (0x00000005)
-#define NVC96F_DMA_SEC_OP_RESERVED6                                (0x00000006)
-#define NVC96F_DMA_SEC_OP_END_PB_SEGMENT                           (0x00000007)
-/* dma incrementing method format */
-#define NVC96F_DMA_INCR_ADDRESS                                    11:0
-#define NVC96F_DMA_INCR_SUBCHANNEL                                 15:13
-#define NVC96F_DMA_INCR_COUNT                                      28:16
-#define NVC96F_DMA_INCR_OPCODE                                     31:29
-#define NVC96F_DMA_INCR_OPCODE_VALUE                               (0x00000001)
-#define NVC96F_DMA_INCR_DATA                                       31:0
-/* dma non-incrementing method format */
-#define NVC96F_DMA_NONINCR_ADDRESS                                 11:0
-#define NVC96F_DMA_NONINCR_SUBCHANNEL                              15:13
-#define NVC96F_DMA_NONINCR_COUNT                                   28:16
-#define NVC96F_DMA_NONINCR_OPCODE                                  31:29
-#define NVC96F_DMA_NONINCR_OPCODE_VALUE                            (0x00000003)
-#define NVC96F_DMA_NONINCR_DATA                                    31:0
-/* dma increment-once method format */
-#define NVC96F_DMA_ONEINCR_ADDRESS                                 11:0
-#define NVC96F_DMA_ONEINCR_SUBCHANNEL                              15:13
-#define NVC96F_DMA_ONEINCR_COUNT                                   28:16
-#define NVC96F_DMA_ONEINCR_OPCODE                                  31:29
-#define NVC96F_DMA_ONEINCR_OPCODE_VALUE                            (0x00000005)
-#define NVC96F_DMA_ONEINCR_DATA                                    31:0
-/* dma no-operation format */
-#define NVC96F_DMA_NOP                                             (0x00000000)
-/* dma immediate-data format */
-#define NVC96F_DMA_IMMD_ADDRESS                                    11:0
-#define NVC96F_DMA_IMMD_SUBCHANNEL                                 15:13
-#define NVC96F_DMA_IMMD_DATA                                       28:16
-#define NVC96F_DMA_IMMD_OPCODE                                     31:29
-#define NVC96F_DMA_IMMD_OPCODE_VALUE                               (0x00000004)
-/* dma set sub-device mask format */
-#define NVC96F_DMA_SET_SUBDEVICE_MASK_VALUE                        15:4
-#define NVC96F_DMA_SET_SUBDEVICE_MASK_OPCODE                       31:16
-#define NVC96F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE                 (0x00000001)
-/* dma store sub-device mask format */
-#define NVC96F_DMA_STORE_SUBDEVICE_MASK_VALUE                      15:4
-#define NVC96F_DMA_STORE_SUBDEVICE_MASK_OPCODE                     31:16
-#define NVC96F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE               (0x00000002)
-/* dma use sub-device mask format */
-#define NVC96F_DMA_USE_SUBDEVICE_MASK_OPCODE                       31:16
-#define NVC96F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE                 (0x00000003)
-/* dma end-segment format */
-#define NVC96F_DMA_ENDSEG_OPCODE                                   31:29
-#define NVC96F_DMA_ENDSEG_OPCODE_VALUE                             (0x00000007)
-/* dma legacy incrementing/non-incrementing formats */
-#define NVC96F_DMA_ADDRESS                                         12:2
-#define NVC96F_DMA_SUBCH                                           15:13
-#define NVC96F_DMA_OPCODE3                                         17:16
-#define NVC96F_DMA_OPCODE3_NONE                                    (0x00000000)
-#define NVC96F_DMA_COUNT                                           28:18
-#define NVC96F_DMA_OPCODE                                          31:29
-#define NVC96F_DMA_OPCODE_METHOD                                   (0x00000000)
-#define NVC96F_DMA_OPCODE_NONINC_METHOD                            (0x00000002)
-#define NVC96F_DMA_DATA                                            31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-
-#endif /* _clc96f_h_ */
+#endif // __gb100_clc96f_h__
--- a/kernel-open/nvidia-uvm/clc9b5.h
+++ b/kernel-open/nvidia-uvm/clc9b5.h
@@ -1,460 +1,29 @@
-/*******************************************************************************
-    Copyright (c) 1993-2004 NVIDIA Corporation
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */

-    Permission is hereby granted, free of charge, to any person obtaining a copy
-    of this software and associated documentation files (the "Software"), to
-    deal in the Software without restriction, including without limitation the
-    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-    sell copies of the Software, and to permit persons to whom the Software is
-    furnished to do so, subject to the following conditions:
-
-    The above copyright notice and this permission notice shall be
-    included in all copies or substantial portions of the Software.
-
-    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-    DEALINGS IN THE SOFTWARE.
-
-*******************************************************************************/
-
-
-
-#include "nvtypes.h"
-
-#ifndef _clc9b5_h_
-#define _clc9b5_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
+#ifndef __gb100_clc9b5_h__
+#define __gb100_clc9b5_h__

 #define BLACKWELL_DMA_COPY_A                                                            (0x0000C9B5)

-typedef volatile struct _clc9b5_tag0 {
-    NvV32 Reserved00[0x40];
-    NvV32 Nop;                                                                  // 0x00000100 - 0x00000103
-    NvV32 Reserved01[0xF];
-    NvV32 PmTrigger;                                                            // 0x00000140 - 0x00000143
-    NvV32 Reserved02[0x36];
-    NvV32 SetMonitoredFenceType;                                                // 0x0000021C - 0x0000021F
-    NvV32 SetMonitoredFenceSignalAddrBaseUpper;                                 // 0x00000220 - 0x00000223
-    NvV32 SetMonitoredFenceSignalAddrBaseLower;                                 // 0x00000224 - 0x00000227
-    NvV32 Reserved03[0x6];
-    NvV32 SetSemaphoreA;                                                        // 0x00000240 - 0x00000243
-    NvV32 SetSemaphoreB;                                                        // 0x00000244 - 0x00000247
-    NvV32 SetSemaphorePayload;                                                  // 0x00000248 - 0x0000024B
-    NvV32 SetSemaphorePayloadUpper;                                             // 0x0000024C - 0x0000024F
-    NvV32 Reserved04[0x1];
-    NvV32 SetRenderEnableA;                                                     // 0x00000254 - 0x00000257
-    NvV32 SetRenderEnableB;                                                     // 0x00000258 - 0x0000025B
-    NvV32 SetRenderEnableC;                                                     // 0x0000025C - 0x0000025F
-    NvV32 SetSrcPhysMode;                                                       // 0x00000260 - 0x00000263
-    NvV32 SetDstPhysMode;                                                       // 0x00000264 - 0x00000267
-    NvV32 Reserved05[0x26];
-    NvV32 LaunchDma;                                                            // 0x00000300 - 0x00000303
-    NvV32 Reserved06[0x3F];
-    NvV32 OffsetInUpper;                                                        // 0x00000400 - 0x00000403
-    NvV32 OffsetInLower;                                                        // 0x00000404 - 0x00000407
-    NvV32 OffsetOutUpper;                                                       // 0x00000408 - 0x0000040B
-    NvV32 OffsetOutLower;                                                       // 0x0000040C - 0x0000040F
-    NvV32 PitchIn;                                                              // 0x00000410 - 0x00000413
-    NvV32 PitchOut;                                                             // 0x00000414 - 0x00000417
-    NvV32 LineLengthIn;                                                         // 0x00000418 - 0x0000041B
-    NvV32 LineCount;                                                            // 0x0000041C - 0x0000041F
-    NvV32 Reserved07[0x38];
-    NvV32 SetSecureCopyMode;                                                    // 0x00000500 - 0x00000503
-    NvV32 SetDecryptIv0;                                                        // 0x00000504 - 0x00000507
-    NvV32 SetDecryptIv1;                                                        // 0x00000508 - 0x0000050B
-    NvV32 SetDecryptIv2;                                                        // 0x0000050C - 0x0000050F
-    NvV32 Reserved_SetAESCounter;                                               // 0x00000510 - 0x00000513
-    NvV32 SetDecryptAuthTagCompareAddrUpper;                                    // 0x00000514 - 0x00000517
-    NvV32 SetDecryptAuthTagCompareAddrLower;                                    // 0x00000518 - 0x0000051B
-    NvV32 Reserved08[0x5];
-    NvV32 SetEncryptAuthTagAddrUpper;                                           // 0x00000530 - 0x00000533
-    NvV32 SetEncryptAuthTagAddrLower;                                           // 0x00000534 - 0x00000537
-    NvV32 SetEncryptIvAddrUpper;                                                // 0x00000538 - 0x0000053B
-    NvV32 SetEncryptIvAddrLower;                                                // 0x0000053C - 0x0000053F
-    NvV32 Reserved09[0x10];
-    NvV32 SetCompressionParameters;                                             // 0x00000580 - 0x00000583
-    NvV32 SetDecompressOutLength;                                               // 0x00000584 - 0x00000587
-    NvV32 SetDecompressOutLengthAddrUpper;                                      // 0x00000588 - 0x0000058B
-    NvV32 SetDecompressOutLengthAddrLower;                                      // 0x0000058C - 0x0000058F
-    NvV32 SetDecompressChecksum;                                                // 0x00000590 - 0x00000593
-    NvV32 Reserved10[0x5A];
-    NvV32 SetMemoryScrubParameters;                                             // 0x000006FC - 0x000006FF
-    NvV32 SetRemapConstA;                                                       // 0x00000700 - 0x00000703
-    NvV32 SetRemapConstB;                                                       // 0x00000704 - 0x00000707
-    NvV32 SetRemapComponents;                                                   // 0x00000708 - 0x0000070B
-    NvV32 SetDstBlockSize;                                                      // 0x0000070C - 0x0000070F
-    NvV32 SetDstWidth;                                                          // 0x00000710 - 0x00000713
-    NvV32 SetDstHeight;                                                         // 0x00000714 - 0x00000717
-    NvV32 SetDstDepth;                                                          // 0x00000718 - 0x0000071B
-    NvV32 SetDstLayer;                                                          // 0x0000071C - 0x0000071F
-    NvV32 SetDstOrigin;                                                         // 0x00000720 - 0x00000723
-    NvV32 Reserved11[0x1];
-    NvV32 SetSrcBlockSize;                                                      // 0x00000728 - 0x0000072B
-    NvV32 SetSrcWidth;                                                          // 0x0000072C - 0x0000072F
-    NvV32 SetSrcHeight;                                                         // 0x00000730 - 0x00000733
-    NvV32 SetSrcDepth;                                                          // 0x00000734 - 0x00000737
-    NvV32 SetSrcLayer;                                                          // 0x00000738 - 0x0000073B
-    NvV32 SetSrcOrigin;                                                         // 0x0000073C - 0x0000073F
-    NvV32 Reserved12[0x1];
-    NvV32 SrcOriginX;                                                           // 0x00000744 - 0x00000747
-    NvV32 SrcOriginY;                                                           // 0x00000748 - 0x0000074B
-    NvV32 DstOriginX;                                                           // 0x0000074C - 0x0000074F
-    NvV32 DstOriginY;                                                           // 0x00000750 - 0x00000753
-    NvV32 Reserved13[0x270];
-    NvV32 PmTriggerEnd;                                                         // 0x00001114 - 0x00001117
-    NvV32 Reserved14[0x3BA];
-} blackwell_dma_copy_aControlPio;
-
-#define NVC9B5_NOP                                                              (0x00000100)
-#define NVC9B5_NOP_PARAMETER                                                    31:0
-#define NVC9B5_PM_TRIGGER                                                       (0x00000140)
-#define NVC9B5_PM_TRIGGER_V                                                     31:0
-#define NVC9B5_SET_MONITORED_FENCE_TYPE                                         (0x0000021C)
-#define NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE                                    0:0
-#define NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE                    (0x00000000)
-#define NVC9B5_SET_MONITORED_FENCE_TYPE_TYPE_MONITORED_FENCE_EXT                (0x00000001)
-#define NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER                       (0x00000220)
-#define NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_UPPER_UPPER                 24:0
-#define NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER                       (0x00000224)
-#define NVC9B5_SET_MONITORED_FENCE_SIGNAL_ADDR_BASE_LOWER_LOWER                 31:0
-#define NVC9B5_SET_SEMAPHORE_A                                                  (0x00000240)
-#define NVC9B5_SET_SEMAPHORE_A_UPPER                                            24:0
-#define NVC9B5_SET_SEMAPHORE_B                                                  (0x00000244)
-#define NVC9B5_SET_SEMAPHORE_B_LOWER                                            31:0
-#define NVC9B5_SET_SEMAPHORE_PAYLOAD                                            (0x00000248)
-#define NVC9B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD                                    31:0
-#define NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER                                      (0x0000024C)
-#define NVC9B5_SET_SEMAPHORE_PAYLOAD_UPPER_PAYLOAD                              31:0
-#define NVC9B5_SET_RENDER_ENABLE_A                                              (0x00000254)
-#define NVC9B5_SET_RENDER_ENABLE_A_UPPER                                        24:0
-#define NVC9B5_SET_RENDER_ENABLE_B                                              (0x00000258)
-#define NVC9B5_SET_RENDER_ENABLE_B_LOWER                                        31:0
-#define NVC9B5_SET_RENDER_ENABLE_C                                              (0x0000025C)
-#define NVC9B5_SET_RENDER_ENABLE_C_MODE                                         2:0
-#define NVC9B5_SET_RENDER_ENABLE_C_MODE_FALSE                                   (0x00000000)
-#define NVC9B5_SET_RENDER_ENABLE_C_MODE_TRUE                                    (0x00000001)
-#define NVC9B5_SET_RENDER_ENABLE_C_MODE_CONDITIONAL                             (0x00000002)
-#define NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL                         (0x00000003)
-#define NVC9B5_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL                     (0x00000004)
-#define NVC9B5_SET_SRC_PHYS_MODE                                                (0x00000260)
-#define NVC9B5_SET_SRC_PHYS_MODE_TARGET                                         1:0
-#define NVC9B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB                                (0x00000000)
-#define NVC9B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM                         (0x00000001)
-#define NVC9B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM                      (0x00000002)
-#define NVC9B5_SET_SRC_PHYS_MODE_TARGET_PEERMEM                                 (0x00000003)
-#define NVC9B5_SET_SRC_PHYS_MODE_BASIC_KIND                                     5:2
-#define NVC9B5_SET_SRC_PHYS_MODE_PEER_ID                                        8:6
-#define NVC9B5_SET_SRC_PHYS_MODE_FLA                                            9:9
-#define NVC9B5_SET_DST_PHYS_MODE                                                (0x00000264)
-#define NVC9B5_SET_DST_PHYS_MODE_TARGET                                         1:0
-#define NVC9B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB                                (0x00000000)
-#define NVC9B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM                         (0x00000001)
-#define NVC9B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM                      (0x00000002)
-#define NVC9B5_SET_DST_PHYS_MODE_TARGET_PEERMEM                                 (0x00000003)
-#define NVC9B5_SET_DST_PHYS_MODE_BASIC_KIND                                     5:2
-#define NVC9B5_SET_DST_PHYS_MODE_PEER_ID                                        8:6
-#define NVC9B5_SET_DST_PHYS_MODE_FLA                                            9:9
-#define NVC9B5_LAUNCH_DMA                                                       (0x00000300)
-#define NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE                                    1:0
-#define NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE                               (0x00000000)
-#define NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED                          (0x00000001)
-#define NVC9B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED                      (0x00000002)
-#define NVC9B5_LAUNCH_DMA_FLUSH_ENABLE                                          2:2
-#define NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE                                    (0x00000000)
-#define NVC9B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE                                     (0x00000001)
-#define NVC9B5_LAUNCH_DMA_FLUSH_TYPE                                            25:25
-#define NVC9B5_LAUNCH_DMA_FLUSH_TYPE_SYS                                        (0x00000000)
-#define NVC9B5_LAUNCH_DMA_FLUSH_TYPE_GL                                         (0x00000001)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE                                        4:3
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE                                   (0x00000000)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_NO_TIMESTAMP         (0x00000001)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_SEMAPHORE_WITH_TIMESTAMP       (0x00000002)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE             (0x00000001)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE            (0x00000002)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_CONDITIONAL_INTR_SEMAPHORE     (0x00000003)
-#define NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE                                        6:5
-#define NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE                                   (0x00000000)
-#define NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING                               (0x00000001)
-#define NVC9B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING                           (0x00000002)
-#define NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT                                     7:7
-#define NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR                         (0x00000000)
-#define NVC9B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH                               (0x00000001)
-#define NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT                                     8:8
-#define NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR                         (0x00000000)
-#define NVC9B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH                               (0x00000001)
-#define NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE                                     9:9
-#define NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE                               (0x00000000)
-#define NVC9B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE                                (0x00000001)
-#define NVC9B5_LAUNCH_DMA_REMAP_ENABLE                                          10:10
-#define NVC9B5_LAUNCH_DMA_REMAP_ENABLE_FALSE                                    (0x00000000)
-#define NVC9B5_LAUNCH_DMA_REMAP_ENABLE_TRUE                                     (0x00000001)
-#define NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE                                    11:11
-#define NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_FALSE                              (0x00000000)
-#define NVC9B5_LAUNCH_DMA_COMPRESSION_ENABLE_TRUE                               (0x00000001)
-#define NVC9B5_LAUNCH_DMA_SRC_TYPE                                              12:12
-#define NVC9B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL                                      (0x00000000)
-#define NVC9B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL                                     (0x00000001)
-#define NVC9B5_LAUNCH_DMA_DST_TYPE                                              13:13
-#define NVC9B5_LAUNCH_DMA_DST_TYPE_VIRTUAL                                      (0x00000000)
-#define NVC9B5_LAUNCH_DMA_DST_TYPE_PHYSICAL                                     (0x00000001)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION                                   17:14
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN                              (0x00000000)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX                              (0x00000001)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR                              (0x00000002)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND                              (0x00000003)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR                               (0x00000004)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD                              (0x00000005)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC                               (0x00000006)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC                               (0x00000007)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDA                          (0x00000008)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDB                          (0x00000009)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD                              (0x0000000A)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN                              (0x0000000B)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX                              (0x0000000C)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDC                          (0x0000000D)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDD                          (0x0000000E)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INVALIDE                          (0x0000000F)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN                              18:18
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED                       (0x00000000)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED                     (0x00000001)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE                            19:19
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE                      (0x00000000)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE                       (0x00000001)
-#define NVC9B5_LAUNCH_DMA_COPY_TYPE                                             21:20
-#define NVC9B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT                                   (0x00000000)
-#define NVC9B5_LAUNCH_DMA_COPY_TYPE_DEFAULT                                     (0x00000000)
-#define NVC9B5_LAUNCH_DMA_COPY_TYPE_SECURE                                      (0x00000001)
-#define NVC9B5_LAUNCH_DMA_COPY_TYPE_NONPROT2NONPROT                             (0x00000002)
-#define NVC9B5_LAUNCH_DMA_COPY_TYPE_RESERVED                                    (0x00000003)
-#define NVC9B5_LAUNCH_DMA_VPRMODE                                               22:22
-#define NVC9B5_LAUNCH_DMA_VPRMODE_VPR_NONE                                      (0x00000000)
-#define NVC9B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID                                   (0x00000001)
-#define NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE                                   23:23
-#define NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_FALSE                             (0x00000000)
-#define NVC9B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE                              (0x00000001)
-#define NVC9B5_LAUNCH_DMA_RESERVED_START_OF_COPY                                24:24
-#define NVC9B5_LAUNCH_DMA_DISABLE_PLC                                           26:26
-#define NVC9B5_LAUNCH_DMA_DISABLE_PLC_FALSE                                     (0x00000000)
-#define NVC9B5_LAUNCH_DMA_DISABLE_PLC_TRUE                                      (0x00000001)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE                                27:27
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_ONE_WORD                       (0x00000000)
-#define NVC9B5_LAUNCH_DMA_SEMAPHORE_PAYLOAD_SIZE_TWO_WORD                       (0x00000001)
-#define NVC9B5_LAUNCH_DMA_RESERVED_ERR_CODE                                     31:28
-#define NVC9B5_OFFSET_IN_UPPER                                                  (0x00000400)
-#define NVC9B5_OFFSET_IN_UPPER_UPPER                                            24:0
-#define NVC9B5_OFFSET_IN_LOWER                                                  (0x00000404)
-#define NVC9B5_OFFSET_IN_LOWER_VALUE                                            31:0
-#define NVC9B5_OFFSET_OUT_UPPER                                                 (0x00000408)
-#define NVC9B5_OFFSET_OUT_UPPER_UPPER                                           24:0
-#define NVC9B5_OFFSET_OUT_LOWER                                                 (0x0000040C)
-#define NVC9B5_OFFSET_OUT_LOWER_VALUE                                           31:0
-#define NVC9B5_PITCH_IN                                                         (0x00000410)
-#define NVC9B5_PITCH_IN_VALUE                                                   31:0
-#define NVC9B5_PITCH_OUT                                                        (0x00000414)
-#define NVC9B5_PITCH_OUT_VALUE                                                  31:0
-#define NVC9B5_LINE_LENGTH_IN                                                   (0x00000418)
-#define NVC9B5_LINE_LENGTH_IN_VALUE                                             31:0
-#define NVC9B5_LINE_COUNT                                                       (0x0000041C)
-#define NVC9B5_LINE_COUNT_VALUE                                                 31:0
-#define NVC9B5_SET_SECURE_COPY_MODE                                             (0x00000500)
-#define NVC9B5_SET_SECURE_COPY_MODE_MODE                                        0:0
-#define NVC9B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT                                (0x00000000)
-#define NVC9B5_SET_SECURE_COPY_MODE_MODE_DECRYPT                                (0x00000001)
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET                         20:19
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_LOCAL_FB                (0x00000000)
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_COHERENT_SYSMEM         (0x00000001)
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_NONCOHERENT_SYSMEM      (0x00000002)
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_TARGET_PEERMEM                 (0x00000003)
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_PEER_ID                        23:21
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_SRC_FLA                            24:24
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET                         26:25
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_LOCAL_FB                (0x00000000)
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_COHERENT_SYSMEM         (0x00000001)
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_NONCOHERENT_SYSMEM      (0x00000002)
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_TARGET_PEERMEM                 (0x00000003)
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_PEER_ID                        29:27
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_DST_FLA                            30:30
-#define NVC9B5_SET_SECURE_COPY_MODE_RESERVED_END_OF_COPY                        31:31
-#define NVC9B5_SET_DECRYPT_IV0                                                  (0x00000504)
-#define NVC9B5_SET_DECRYPT_IV0_VALUE                                            31:0
-#define NVC9B5_SET_DECRYPT_IV1                                                  (0x00000508)
-#define NVC9B5_SET_DECRYPT_IV1_VALUE                                            31:0
-#define NVC9B5_SET_DECRYPT_IV2                                                  (0x0000050C)
-#define NVC9B5_SET_DECRYPT_IV2_VALUE                                            31:0
-#define NVC9B5_RESERVED_SET_AESCOUNTER                                          (0x00000510)
-#define NVC9B5_RESERVED_SET_AESCOUNTER_VALUE                                    31:0
-#define NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER                          (0x00000514)
-#define NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER                    24:0
-#define NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER                          (0x00000518)
-#define NVC9B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER_LOWER                    31:0
-#define NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER                                  (0x00000530)
-#define NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER_UPPER                            24:0
-#define NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER                                  (0x00000534)
-#define NVC9B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER_LOWER                            31:0
-#define NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER                                        (0x00000538)
-#define NVC9B5_SET_ENCRYPT_IV_ADDR_UPPER_UPPER                                  24:0
-#define NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER                                        (0x0000053C)
-#define NVC9B5_SET_ENCRYPT_IV_ADDR_LOWER_LOWER                                  31:0
-#define NVC9B5_SET_COMPRESSION_PARAMETERS                                       (0x00000580)
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION                             0:0
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_DECOMPRESS                  (0x00000000)
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_OPERATION_COMPRESS                    (0x00000001)
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO                                  3:1
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY                           (0x00000000)
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_DATA_ONLY                    (0x00000001)
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK                        (0x00000002)
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_LZ4_BLOCK_CHECKSUM               (0x00000003)
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_DEFLATE                          (0x00000004)
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_ALGO_SNAPPY_WITH_LONG_FETCH           (0x00000005)
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM                             29:28
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_NONE                        (0x00000000)
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_ADLER32                     (0x00000001)
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_CRC32                       (0x00000002)
-#define NVC9B5_SET_COMPRESSION_PARAMETERS_CHECK_SUM_SNAPPY_CRC                  (0x00000003)
-#define NVC9B5_SET_DECOMPRESS_OUT_LENGTH                                        (0x00000584)
-#define NVC9B5_SET_DECOMPRESS_OUT_LENGTH_V                                      31:0
-#define NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_UPPER                             (0x00000588)
-#define NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_UPPER_UPPER                       24:0
-#define NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_LOWER                             (0x0000058C)
-#define NVC9B5_SET_DECOMPRESS_OUT_LENGTH_ADDR_LOWER_LOWER                       31:0
-#define NVC9B5_SET_DECOMPRESS_CHECKSUM                                          (0x00000590)
-#define NVC9B5_SET_DECOMPRESS_CHECKSUM_V                                        31:0
-#define NVC9B5_SET_MEMORY_SCRUB_PARAMETERS                                      (0x000006FC)
-#define NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE                          0:0
-#define NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE                    (0x00000000)
-#define NVC9B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_TRUE                     (0x00000001)
-#define NVC9B5_SET_REMAP_CONST_A                                                (0x00000700)
-#define NVC9B5_SET_REMAP_CONST_A_V                                              31:0
-#define NVC9B5_SET_REMAP_CONST_B                                                (0x00000704)
-#define NVC9B5_SET_REMAP_CONST_B_V                                              31:0
-#define NVC9B5_SET_REMAP_COMPONENTS                                             (0x00000708)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_X                                       2:0
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_X                                 (0x00000000)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y                                 (0x00000001)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z                                 (0x00000002)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_X_SRC_W                                 (0x00000003)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_A                               (0x00000004)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_X_CONST_B                               (0x00000005)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE                              (0x00000006)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Y                                       6:4
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X                                 (0x00000000)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y                                 (0x00000001)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z                                 (0x00000002)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W                                 (0x00000003)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A                               (0x00000004)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B                               (0x00000005)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE                              (0x00000006)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Z                                       10:8
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X                                 (0x00000000)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y                                 (0x00000001)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z                                 (0x00000002)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W                                 (0x00000003)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A                               (0x00000004)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B                               (0x00000005)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE                              (0x00000006)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_W                                       14:12
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_X                                 (0x00000000)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y                                 (0x00000001)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z                                 (0x00000002)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_W_SRC_W                                 (0x00000003)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_A                               (0x00000004)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_W_CONST_B                               (0x00000005)
-#define NVC9B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE                              (0x00000006)
-#define NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE                              17:16
-#define NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE                          (0x00000000)
-#define NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO                          (0x00000001)
-#define NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE                        (0x00000002)
-#define NVC9B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR                         (0x00000003)
-#define NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS                          21:20
-#define NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE                      (0x00000000)
-#define NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO                      (0x00000001)
-#define NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE                    (0x00000002)
-#define NVC9B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR                     (0x00000003)
-#define NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS                          25:24
-#define NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE                      (0x00000000)
-#define NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO                      (0x00000001)
-#define NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE                    (0x00000002)
-#define NVC9B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR                     (0x00000003)
-#define NVC9B5_SET_DST_BLOCK_SIZE                                               (0x0000070C)
-#define NVC9B5_SET_DST_BLOCK_SIZE_WIDTH                                         3:0
-#define NVC9B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB                                 (0x00000000)
-#define NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT                                        7:4
-#define NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB                                (0x00000000)
-#define NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS                               (0x00000001)
-#define NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS                              (0x00000002)
-#define NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                             (0x00000003)
-#define NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                           (0x00000004)
-#define NVC9B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                         (0x00000005)
-#define NVC9B5_SET_DST_BLOCK_SIZE_DEPTH                                         11:8
-#define NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB                                 (0x00000000)
-#define NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS                                (0x00000001)
-#define NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS                               (0x00000002)
-#define NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS                              (0x00000003)
-#define NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                            (0x00000004)
-#define NVC9B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                          (0x00000005)
-#define NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT                                    15:12
-#define NVC9B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8                 (0x00000001)
-#define NVC9B5_SET_DST_WIDTH                                                    (0x00000710)
-#define NVC9B5_SET_DST_WIDTH_V                                                  31:0
-#define NVC9B5_SET_DST_HEIGHT                                                   (0x00000714)
-#define NVC9B5_SET_DST_HEIGHT_V                                                 31:0
-#define NVC9B5_SET_DST_DEPTH                                                    (0x00000718)
-#define NVC9B5_SET_DST_DEPTH_V                                                  31:0
-#define NVC9B5_SET_DST_LAYER                                                    (0x0000071C)
-#define NVC9B5_SET_DST_LAYER_V                                                  31:0
-#define NVC9B5_SET_DST_ORIGIN                                                   (0x00000720)
-#define NVC9B5_SET_DST_ORIGIN_X                                                 15:0
-#define NVC9B5_SET_DST_ORIGIN_Y                                                 31:16
-#define NVC9B5_SET_SRC_BLOCK_SIZE                                               (0x00000728)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_WIDTH                                         3:0
-#define NVC9B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB                                 (0x00000000)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT                                        7:4
-#define NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB                                (0x00000000)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS                               (0x00000001)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS                              (0x00000002)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS                             (0x00000003)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS                           (0x00000004)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS                         (0x00000005)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH                                         11:8
-#define NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB                                 (0x00000000)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS                                (0x00000001)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS                               (0x00000002)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS                              (0x00000003)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS                            (0x00000004)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS                          (0x00000005)
-#define NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT                                    15:12
-#define NVC9B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8                 (0x00000001)
-#define NVC9B5_SET_SRC_WIDTH                                                    (0x0000072C)
-#define NVC9B5_SET_SRC_WIDTH_V                                                  31:0
-#define NVC9B5_SET_SRC_HEIGHT                                                   (0x00000730)
-#define NVC9B5_SET_SRC_HEIGHT_V                                                 31:0
-#define NVC9B5_SET_SRC_DEPTH                                                    (0x00000734)
-#define NVC9B5_SET_SRC_DEPTH_V                                                  31:0
-#define NVC9B5_SET_SRC_LAYER                                                    (0x00000738)
-#define NVC9B5_SET_SRC_LAYER_V                                                  31:0
-#define NVC9B5_SET_SRC_ORIGIN                                                   (0x0000073C)
-#define NVC9B5_SET_SRC_ORIGIN_X                                                 15:0
-#define NVC9B5_SET_SRC_ORIGIN_Y                                                 31:16
-#define NVC9B5_SRC_ORIGIN_X                                                     (0x00000744)
-#define NVC9B5_SRC_ORIGIN_X_VALUE                                               31:0
-#define NVC9B5_SRC_ORIGIN_Y                                                     (0x00000748)
-#define NVC9B5_SRC_ORIGIN_Y_VALUE                                               31:0
-#define NVC9B5_DST_ORIGIN_X                                                     (0x0000074C)
-#define NVC9B5_DST_ORIGIN_X_VALUE                                               31:0
-#define NVC9B5_DST_ORIGIN_Y                                                     (0x00000750)
-#define NVC9B5_DST_ORIGIN_Y_VALUE                                               31:0
-#define NVC9B5_PM_TRIGGER_END                                                   (0x00001114)
-#define NVC9B5_PM_TRIGGER_END_V                                                 31:0
-
-#ifdef __cplusplus
-};     /* extern "C" */
-#endif
-#endif // _clc9b5_h
-
+#endif // __gb100_clc9b5_h__
--- a/kernel-open/nvidia-uvm/clcba2.h
+++ b/kernel-open/nvidia-uvm/clcba2.h
@@ -151,6 +151,7 @@ typedef volatile struct _clcba2_tag0 {
 #define NVCBA2_ERROR_SCRUBBER_INSUFFICIENT_PERMISSIONS                          (0x0000001b)
 #define NVCBA2_ERROR_SCRUBBER_MUTEX_ACQUIRE_FAILURE                             (0x0000001c)
 #define NVCBA2_ERROR_SCRUB_SIZE_MAX_EXCEEDED                                    (0x0000001d)
+#define NVCBA2_ERROR_SIZE_ZERO                                                  (0x0000001e)

 #ifdef __cplusplus
 };     /* extern "C" */
--- a/kernel-open/nvidia-uvm/ctrl2080mc.h
+++ b/kernel-open/nvidia-uvm/ctrl2080mc.h
@@ -43,4 +43,7 @@

 #define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA100              (0x00000000)
 #define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GA000              (0x00000001)
+
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB10B              (0x0000000B)
+#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20B              (0x0000000B)
 #endif /* _ctrl2080mc_h_ */
--- a/kernel-open/nvidia-uvm/hwref/hopper/gh100/dev_mmu.h
+++ b/kernel-open/nvidia-uvm/hwref/hopper/gh100/dev_mmu.h
@@ -534,9 +534,6 @@
 #define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD                             0x0000001F /* RW--V */
 #define NV_MMU_VER3_PTE_KIND                                           11:8 /* RWXVF */
 #define NV_MMU_VER3_PTE_ADDRESS                                         51:12 /* RWXVF */
-#define NV_MMU_VER3_PTE_ADDRESS_SYS                                     51:12 /* RWXVF */
-#define NV_MMU_VER3_PTE_ADDRESS_PEER                                    51:12 /* RWXVF */
-#define NV_MMU_VER3_PTE_ADDRESS_VID                                     39:12 /* RWXVF */
 #define NV_MMU_VER3_PTE_PEER_ID                63:(64-3) /* RWXVF */
 #define NV_MMU_VER3_PTE_PEER_ID_0                                 0x00000000 /* RW--V */
 #define NV_MMU_VER3_PTE_PEER_ID_1                                 0x00000001 /* RW--V */
--- a/kernel-open/nvidia-uvm/nv-kthread-q.c
+++ b/kernel-open/nvidia-uvm/nv-kthread-q.c
@@ -29,12 +29,7 @@
 #include <linux/completion.h>
 #include <linux/module.h>
 #include <linux/mm.h>
-
-#if defined(NV_LINUX_BUG_H_PRESENT)
-    #include <linux/bug.h>
-#else
-    #include <asm/bug.h>
-#endif
+#include <linux/bug.h>

 // Today's implementation is a little simpler and more limited than the
 // API description allows for in nv-kthread-q.h. Details include:
--- a/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild
+++ b/kernel-open/nvidia-uvm/nvidia-uvm-sources.Kbuild
@@ -21,6 +21,7 @@ NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_rm_mem.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_channel.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_lock.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_hal.c
+NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_fd_type.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_processors.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_range_tree.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_rb_tree.c
@@ -95,7 +96,6 @@ NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_perf_heuristics.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_perf_thrashing.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_perf_prefetch.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ats.c
-NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ats_ibm.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ats_faults.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_ats_sva.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_conf_computing.c
@@ -127,3 +127,4 @@ NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_range_group_tree_test.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_thread_context_test.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_rb_tree_test.c
 NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_sec2_test.c
+NVIDIA_UVM_SOURCES += nvidia-uvm/uvm_test_file.c
--- a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild
+++ b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild
@@ -48,36 +48,27 @@ $(call ASSIGN_PER_OBJ_CFLAGS, $(NVIDIA_UVM_OBJECTS), $(NVIDIA_UVM_CFLAGS))

 NV_OBJECTS_DEPEND_ON_CONFTEST += $(NVIDIA_UVM_OBJECTS)

-NV_CONFTEST_FUNCTION_COMPILE_TESTS += radix_tree_empty
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += radix_tree_replace_slot
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += pnv_npu2_init_context
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += cpumask_of_node
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += list_is_first
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioasid_get
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += mm_pasid_drop
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmget_not_zero
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmgrab
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += iommu_sva_bind_device_has_drvdata_arg
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += vm_fault_to_errno
-NV_CONFTEST_FUNCTION_COMPILE_TESTS += find_next_bit_wrap
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += iommu_is_dma_domain
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += for_each_sgtable_dma_page
 NV_CONFTEST_FUNCTION_COMPILE_TESTS += folio_test_swapcache
+NV_CONFTEST_FUNCTION_COMPILE_TESTS += page_pgmap

-NV_CONFTEST_TYPE_COMPILE_TESTS += vm_ops_fault_removed_vma_arg
-NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_notifier_ops_invalidate_range
 NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_notifier_ops_arch_invalidate_secondary_tlbs
 NV_CONFTEST_TYPE_COMPILE_TESTS += migrate_vma_added_flags
 NV_CONFTEST_TYPE_COMPILE_TESTS += migrate_device_range
-NV_CONFTEST_TYPE_COMPILE_TESTS += handle_mm_fault_has_mm_arg
 NV_CONFTEST_TYPE_COMPILE_TESTS += handle_mm_fault_has_pt_regs_arg
 NV_CONFTEST_TYPE_COMPILE_TESTS += mempolicy_has_unified_nodes
 NV_CONFTEST_TYPE_COMPILE_TESTS += mempolicy_has_home_node
 NV_CONFTEST_TYPE_COMPILE_TESTS += mpol_preferred_many_present
 NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_interval_notifier
-NV_CONFTEST_TYPE_COMPILE_TESTS += fault_flag_remote_present
 NV_CONFTEST_TYPE_COMPILE_TESTS += sg_dma_page_iter
 NV_CONFTEST_TYPE_COMPILE_TESTS += struct_page_has_zone_device_data

 NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_int_active_memcg
 NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_migrate_vma_setup
+NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present___iowrite64_lo_hi
+NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_make_device_exclusive
--- a/kernel-open/nvidia-uvm/uvm.c
+++ b/kernel-open/nvidia-uvm/uvm.c
@@ -1,5 +1,5 @@
 /*******************************************************************************
-    Copyright (c) 2015-2024 NVIDIA Corporation
+    Copyright (c) 2015-2025 NVIDIA Corporation

    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to
@@ -33,10 +33,12 @@
 #include "uvm_va_block.h"
 #include "uvm_tools.h"
 #include "uvm_common.h"
+#include "uvm_fd_type.h"
 #include "uvm_linux_ioctl.h"
 #include "uvm_hmm.h"
 #include "uvm_mem.h"
 #include "uvm_kvmalloc.h"
+#include "uvm_test_file.h"

 #define NVIDIA_UVM_DEVICE_NAME          "nvidia-uvm"

@@ -49,55 +51,9 @@ bool uvm_file_is_nvidia_uvm(struct file *filp)
    return (filp != NULL) && (filp->f_op == &uvm_fops);
 }

-uvm_fd_type_t uvm_fd_type(struct file *filp, void **ptr_val)
+bool uvm_file_is_nvidia_uvm_va_space(struct file *filp)
 {
-    unsigned long uptr;
-    uvm_fd_type_t type;
-    void *ptr;
-
-    UVM_ASSERT(uvm_file_is_nvidia_uvm(filp));
-
-    uptr = atomic_long_read_acquire((atomic_long_t *) (&filp->private_data));
-    type = (uvm_fd_type_t)(uptr & UVM_FD_TYPE_MASK);
-    ptr = (void *)(uptr & ~UVM_FD_TYPE_MASK);
-    BUILD_BUG_ON(UVM_FD_COUNT > UVM_FD_TYPE_MASK + 1);
-
-    switch (type) {
-        case UVM_FD_UNINITIALIZED:
-        case UVM_FD_INITIALIZING:
-            UVM_ASSERT(!ptr);
-            break;
-
-        case UVM_FD_VA_SPACE:
-            UVM_ASSERT(ptr);
-            BUILD_BUG_ON(__alignof__(uvm_va_space_t) < (1UL << UVM_FD_TYPE_BITS));
-            break;
-
-        case UVM_FD_MM:
-            UVM_ASSERT(ptr);
-            BUILD_BUG_ON(__alignof__(struct file) < (1UL << UVM_FD_TYPE_BITS));
-            break;
-
-        default:
-            UVM_ASSERT(0);
-    }
-
-    if (ptr_val)
-        *ptr_val = ptr;
-
-    return type;
-}
-
-void *uvm_fd_get_type(struct file *filp, uvm_fd_type_t type)
-{
-    void *ptr;
-
-    UVM_ASSERT(uvm_file_is_nvidia_uvm(filp));
-
-    if (uvm_fd_type(filp, &ptr) == type)
-        return ptr;
-    else
-        return NULL;
+    return uvm_file_is_nvidia_uvm(filp) && uvm_fd_type(filp, NULL) == UVM_FD_VA_SPACE;
 }

 static NV_STATUS uvm_api_mm_initialize(UVM_MM_INITIALIZE_PARAMS *params, struct file *filp)
@@ -105,7 +61,6 @@ static NV_STATUS uvm_api_mm_initialize(UVM_MM_INITIALIZE_PARAMS *params, struct
    uvm_va_space_t *va_space;
    uvm_va_space_mm_t *va_space_mm;
    struct file *uvm_file;
-    uvm_fd_type_t old_fd_type;
    struct mm_struct *mm;
    NV_STATUS status;

@@ -127,14 +82,9 @@ static NV_STATUS uvm_api_mm_initialize(UVM_MM_INITIALIZE_PARAMS *params, struct
        goto err;
    }

-    old_fd_type = atomic_long_cmpxchg((atomic_long_t *)&filp->private_data,
-                                      UVM_FD_UNINITIALIZED,
-                                      UVM_FD_INITIALIZING);
-    old_fd_type &= UVM_FD_TYPE_MASK;
-    if (old_fd_type != UVM_FD_UNINITIALIZED) {
-        status = NV_ERR_IN_USE;
+    status = uvm_fd_type_init(filp);
+    if (status != NV_OK)
        goto err;
-    }

    va_space_mm = &va_space->va_space_mm;
    uvm_spin_lock(&va_space_mm->lock);
@@ -173,13 +123,13 @@ static NV_STATUS uvm_api_mm_initialize(UVM_MM_INITIALIZE_PARAMS *params, struct
            break;
    }
    uvm_spin_unlock(&va_space_mm->lock);
-    atomic_long_set_release((atomic_long_t *)&filp->private_data, (long)uvm_file | UVM_FD_MM);
+    uvm_fd_type_set(filp, UVM_FD_MM, uvm_file);

    return NV_OK;

 err_release_unlock:
    uvm_spin_unlock(&va_space_mm->lock);
-    atomic_long_set_release((atomic_long_t *)&filp->private_data, UVM_FD_UNINITIALIZED);
+    uvm_fd_type_set(filp, UVM_FD_UNINITIALIZED, NULL);

 err:
    if (uvm_file)
@@ -249,44 +199,10 @@ static void uvm_release_deferred(void *data)
    uvm_up_read(&g_uvm_global.pm.lock);
 }

-static void uvm_mm_release(struct file *filp, struct file *uvm_file)
+static void uvm_release_va_space(struct file *filp, uvm_va_space_t *va_space)
 {
-    uvm_va_space_t *va_space = uvm_va_space_get(uvm_file);
-    uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm;
-    struct mm_struct *mm = va_space_mm->mm;
-
-    if (uvm_va_space_mm_enabled(va_space)) {
-        uvm_va_space_mm_unregister(va_space);
-
-        if (uvm_va_space_mm_enabled(va_space))
-            uvm_mmput(mm);
-
-        va_space_mm->mm = NULL;
-        fput(uvm_file);
-    }
-}
-
-static int uvm_release(struct inode *inode, struct file *filp)
-{
-    void *ptr;
-    uvm_va_space_t *va_space;
-    uvm_fd_type_t fd_type;
    int ret;

-    fd_type = uvm_fd_type(filp, &ptr);
-    UVM_ASSERT(fd_type != UVM_FD_INITIALIZING);
-    if (fd_type == UVM_FD_UNINITIALIZED) {
-        uvm_kvfree(filp->f_mapping);
-        return 0;
-    }
-    else if (fd_type == UVM_FD_MM) {
-        uvm_kvfree(filp->f_mapping);
-        uvm_mm_release(filp, (struct file *)ptr);
-        return 0;
-    }
-
-    UVM_ASSERT(fd_type == UVM_FD_VA_SPACE);
-    va_space = (uvm_va_space_t *)ptr;
    filp->private_data = NULL;
    filp->f_mapping = NULL;

@@ -310,6 +226,52 @@ static int uvm_release(struct inode *inode, struct file *filp)
        ret = nv_kthread_q_schedule_q_item(&g_uvm_global.deferred_release_q, &va_space->deferred_release_q_item);
        UVM_ASSERT(ret != 0);
    }
+}
+
+static void uvm_release_mm(struct file *filp, struct file *uvm_file)
+{
+    uvm_va_space_t *va_space = uvm_va_space_get(uvm_file);
+    uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm;
+    struct mm_struct *mm = va_space_mm->mm;
+
+    uvm_kvfree(filp->f_mapping);
+
+    if (uvm_va_space_mm_enabled(va_space)) {
+        uvm_va_space_mm_unregister(va_space);
+
+        if (uvm_va_space_mm_enabled(va_space))
+            uvm_mmput(mm);
+
+        va_space_mm->mm = NULL;
+        fput(uvm_file);
+    }
+}
+
+static int uvm_release(struct inode *inode, struct file *filp)
+{
+    void *ptr;
+    uvm_fd_type_t fd_type = uvm_fd_type(filp, &ptr);
+
+    switch (fd_type) {
+        case UVM_FD_UNINITIALIZED:
+            uvm_kvfree(filp->f_mapping);
+            break;
+
+        case UVM_FD_VA_SPACE:
+            uvm_release_va_space(filp, (uvm_va_space_t *)ptr);
+            break;
+
+        case UVM_FD_MM:
+            uvm_release_mm(filp, (struct file *)ptr);
+            break;
+
+        case UVM_FD_TEST:
+            uvm_test_file_release(filp, (uvm_test_file_t *)ptr);
+            break;
+
+        default:
+            UVM_ASSERT_MSG(0, "Unexpected fd type: %d\n", fd_type);
+    }

    return 0;
 }
@@ -360,41 +322,23 @@ static void uvm_destroy_vma_semaphore_pool(struct vm_area_struct *vma)
    uvm_mem_unmap_cpu_user(semaphore_pool_range->mem);
 }

-// If a fault handler is not set, paths like handle_pte_fault in older kernels
-// assume the memory is anonymous. That would make debugging this failure harder
-// so we force it to fail instead.
-static vm_fault_t uvm_vm_fault_sigbus(struct vm_area_struct *vma, struct vm_fault *vmf)
+// The kernel will also SIGBUS faults to vmas with valid ops but no fault
+// handler, but it didn't always do that. Make it explicit so we don't rely on
+// the kernel's implementation.
+static vm_fault_t uvm_vm_fault_sigbus(struct vm_fault *vmf)
 {
-    UVM_DBG_PRINT_RL("Fault to address 0x%lx in disabled vma\n", nv_page_fault_va(vmf));
+    UVM_DBG_PRINT_RL("Fault to address 0x%lx in disabled vma\n", vmf->address);
    return VM_FAULT_SIGBUS;
 }

-static vm_fault_t uvm_vm_fault_sigbus_entry(struct vm_area_struct *vma, struct vm_fault *vmf)
+static vm_fault_t uvm_vm_fault_sigbus_entry(struct vm_fault *vmf)
 {
-    UVM_ENTRY_RET(uvm_vm_fault_sigbus(vma, vmf));
-}
-
-static vm_fault_t uvm_vm_fault_sigbus_wrapper(struct vm_fault *vmf)
-{
-#if defined(NV_VM_OPS_FAULT_REMOVED_VMA_ARG)
-    return uvm_vm_fault_sigbus(vmf->vma, vmf);
-#else
-    return uvm_vm_fault_sigbus(NULL, vmf);
-#endif
-}
-
-static vm_fault_t uvm_vm_fault_sigbus_wrapper_entry(struct vm_fault *vmf)
-{
-    UVM_ENTRY_RET(uvm_vm_fault_sigbus_wrapper(vmf));
+    UVM_ENTRY_RET(uvm_vm_fault_sigbus(vmf));
 }

 static struct vm_operations_struct uvm_vm_ops_disabled =
 {
-#if defined(NV_VM_OPS_FAULT_REMOVED_VMA_ARG)
-    .fault = uvm_vm_fault_sigbus_wrapper_entry
-#else
-    .fault = uvm_vm_fault_sigbus_entry
-#endif
+    .fault = uvm_vm_fault_sigbus_entry,
 };

 static void uvm_disable_vma(struct vm_area_struct *vma)
@@ -611,44 +555,23 @@ static void uvm_vm_close_managed_entry(struct vm_area_struct *vma)
    UVM_ENTRY_VOID(uvm_vm_close_managed(vma));
 }

-static vm_fault_t uvm_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+static vm_fault_t uvm_vm_fault(struct vm_fault *vmf)
 {
-    uvm_va_space_t *va_space = uvm_va_space_get(vma->vm_file);
-
-    return uvm_va_space_cpu_fault_managed(va_space, vma, vmf);
+    uvm_va_space_t *va_space = uvm_va_space_get(vmf->vma->vm_file);
+    return uvm_va_space_cpu_fault_managed(va_space, vmf);
 }

-static vm_fault_t uvm_vm_fault_entry(struct vm_area_struct *vma, struct vm_fault *vmf)
+static vm_fault_t uvm_vm_fault_entry(struct vm_fault *vmf)
 {
-    UVM_ENTRY_RET(uvm_vm_fault(vma, vmf));
-}
-
-static vm_fault_t uvm_vm_fault_wrapper(struct vm_fault *vmf)
-{
-#if defined(NV_VM_OPS_FAULT_REMOVED_VMA_ARG)
-    return uvm_vm_fault(vmf->vma, vmf);
-#else
-    return uvm_vm_fault(NULL, vmf);
-#endif
-}
-
-static vm_fault_t uvm_vm_fault_wrapper_entry(struct vm_fault *vmf)
-{
-    UVM_ENTRY_RET(uvm_vm_fault_wrapper(vmf));
+    UVM_ENTRY_RET(uvm_vm_fault(vmf));
 }

 static struct vm_operations_struct uvm_vm_ops_managed =
 {
    .open         = uvm_vm_open_managed_entry,
    .close        = uvm_vm_close_managed_entry,
-
-#if defined(NV_VM_OPS_FAULT_REMOVED_VMA_ARG)
-    .fault        = uvm_vm_fault_wrapper_entry,
-    .page_mkwrite = uvm_vm_fault_wrapper_entry,
-#else
    .fault        = uvm_vm_fault_entry,
    .page_mkwrite = uvm_vm_fault_entry,
-#endif
 };

 // vm operations on semaphore pool allocations only control CPU mappings. Unmapping GPUs,
@@ -744,12 +667,7 @@ static struct vm_operations_struct uvm_vm_ops_semaphore_pool =
 {
    .open         = uvm_vm_open_semaphore_pool_entry,
    .close        = uvm_vm_close_semaphore_pool_entry,
-
-#if defined(NV_VM_OPS_FAULT_REMOVED_VMA_ARG)
-    .fault        = uvm_vm_fault_sigbus_wrapper_entry,
-#else
    .fault        = uvm_vm_fault_sigbus_entry,
-#endif
 };

 static void uvm_vm_open_device_p2p(struct vm_area_struct *vma)
@@ -791,7 +709,7 @@ static void uvm_vm_open_device_p2p(struct vm_area_struct *vma)
        origin_vma->vm_private_data = NULL;
        origin_vma->vm_ops = &uvm_vm_ops_disabled;
        vma->vm_ops = &uvm_vm_ops_disabled;
-        unmap_mapping_range(va_space->mapping, va_range->node.start, va_range->node.end - va_range->node.start + 1, 1);
+        unmap_mapping_range(va_space->mapping, va_range->node.start, uvm_va_range_size(va_range), 1);
    }

    uvm_va_space_up_write(va_space);
@@ -819,16 +737,28 @@ static struct vm_operations_struct uvm_vm_ops_device_p2p =
 {
    .open         = uvm_vm_open_device_p2p_entry,
    .close        = uvm_vm_close_device_p2p_entry,
-
-#if defined(NV_VM_OPS_FAULT_REMOVED_VMA_ARG)
-    .fault        = uvm_vm_fault_sigbus_wrapper_entry,
-#else
    .fault        = uvm_vm_fault_sigbus_entry,
-#endif
 };

+static bool va_range_type_expects_mmap(uvm_va_range_type_t type)
+{
+    switch (type) {
+        case UVM_VA_RANGE_TYPE_SEMAPHORE_POOL:
+        case UVM_VA_RANGE_TYPE_DEVICE_P2P:
+            return true;
+
+        // Although UVM_VA_RANGE_TYPE_MANAGED does support mmap, it doesn't
+        // expect mmap to be called on a pre-existing range. mmap itself creates
+        // the managed va range.
+
+        default:
+            return false;
+    }
+}
+
 static int uvm_mmap(struct file *filp, struct vm_area_struct *vma)
 {
+    void *fd_type_ptr;
    uvm_va_space_t *va_space;
    NV_STATUS status = uvm_global_get_status();
    int ret = 0;
@@ -837,9 +767,17 @@ static int uvm_mmap(struct file *filp, struct vm_area_struct *vma)
    if (status != NV_OK)
        return -nv_status_to_errno(status);

-    va_space = uvm_fd_va_space(filp);
-    if (!va_space)
-        return -EBADFD;
+    switch (uvm_fd_type(filp, &fd_type_ptr)) {
+        case UVM_FD_VA_SPACE:
+            va_space = (uvm_va_space_t *)fd_type_ptr;
+            break;
+
+        case UVM_FD_TEST:
+            return uvm_test_file_mmap((uvm_test_file_t *)fd_type_ptr, vma);
+
+        default:
+            return -EBADFD;
+    }

    // When the VA space is associated with an mm, all vmas under the VA space
    // must come from that mm.
@@ -920,28 +858,38 @@ static int uvm_mmap(struct file *filp, struct vm_area_struct *vma)
    status = uvm_va_range_create_mmap(va_space, current->mm, vma->vm_private_data, NULL);

    if (status == NV_ERR_UVM_ADDRESS_IN_USE) {
-        uvm_va_range_semaphore_pool_t *semaphore_pool_range;
-        uvm_va_range_device_p2p_t *device_p2p_range;
-        // If the mmap is for a semaphore pool, the VA range will have been
-        // allocated by a previous ioctl, and the mmap just creates the CPU
-        // mapping.
-        semaphore_pool_range = uvm_va_range_semaphore_pool_find(va_space, vma->vm_start);
-        device_p2p_range = uvm_va_range_device_p2p_find(va_space, vma->vm_start);
-        if (semaphore_pool_range && semaphore_pool_range->va_range.node.start == vma->vm_start &&
-                semaphore_pool_range->va_range.node.end + 1 == vma->vm_end) {
+        uvm_va_range_t *existing_range = uvm_va_range_find(va_space, vma->vm_start);
+
+        // Does the existing range exactly match the vma and expects mmap?
+        if (existing_range &&
+            existing_range->node.start == vma->vm_start &&
+            existing_range->node.end + 1 == vma->vm_end &&
+            va_range_type_expects_mmap(existing_range->type)) {
+
+            // We speculatively initialized the managed vma before checking for
+            // collisions because we expect successful insertion to be the
+            // common case. Undo that.
            uvm_vma_wrapper_destroy(vma->vm_private_data);
            vma_wrapper_allocated = false;
            vma->vm_private_data = vma;
-            vma->vm_ops = &uvm_vm_ops_semaphore_pool;
-            status = uvm_mem_map_cpu_user(semaphore_pool_range->mem, semaphore_pool_range->va_range.va_space, vma);
-        }
-        else if (device_p2p_range && device_p2p_range->va_range.node.start == vma->vm_start &&
-                 device_p2p_range->va_range.node.end + 1 == vma->vm_end) {
-            uvm_vma_wrapper_destroy(vma->vm_private_data);
-            vma_wrapper_allocated = false;
-            vma->vm_private_data = vma;
-            vma->vm_ops = &uvm_vm_ops_device_p2p;
-            status = uvm_va_range_device_p2p_map_cpu(va_space, vma, device_p2p_range);
+
+            switch (existing_range->type) {
+                case UVM_VA_RANGE_TYPE_SEMAPHORE_POOL:
+                    vma->vm_ops = &uvm_vm_ops_semaphore_pool;
+                    status = uvm_mem_map_cpu_user(uvm_va_range_to_semaphore_pool(existing_range)->mem, va_space, vma);
+                    break;
+
+                case UVM_VA_RANGE_TYPE_DEVICE_P2P:
+                    vma->vm_ops = &uvm_vm_ops_device_p2p;
+                    status = uvm_va_range_device_p2p_map_cpu(va_space,
+                                                             vma,
+                                                             uvm_va_range_to_device_p2p(existing_range));
+                    break;
+
+                default:
+                    UVM_ASSERT(0);
+                    break;
+            }
        }
    }

@@ -999,33 +947,40 @@ static NV_STATUS uvm_api_initialize(UVM_INITIALIZE_PARAMS *params, struct file *
    // attempt to be made. This is safe because other threads will have only had
    // a chance to observe UVM_FD_INITIALIZING and not UVM_FD_VA_SPACE in this
    // case.
-    old_fd_type = atomic_long_cmpxchg((atomic_long_t *)&filp->private_data,
-                                      UVM_FD_UNINITIALIZED,
-                                      UVM_FD_INITIALIZING);
-    old_fd_type &= UVM_FD_TYPE_MASK;
-    if (old_fd_type == UVM_FD_UNINITIALIZED) {
-        status = uvm_va_space_create(filp->f_mapping, &va_space, params->flags);
-        if (status != NV_OK) {
-            atomic_long_set_release((atomic_long_t *)&filp->private_data, UVM_FD_UNINITIALIZED);
-            return status;
-        }
+    old_fd_type = uvm_fd_type_init_cas(filp);
+    switch (old_fd_type) {
+        case UVM_FD_UNINITIALIZED:
+            status = uvm_va_space_create(filp->f_mapping, &va_space, params->flags);
+            if (status != NV_OK) {
+                uvm_fd_type_set(filp, UVM_FD_UNINITIALIZED, NULL);
+                return status;
+            }

-        atomic_long_set_release((atomic_long_t *)&filp->private_data, (long)va_space | UVM_FD_VA_SPACE);
-    }
-    else if (old_fd_type == UVM_FD_VA_SPACE) {
-        va_space = uvm_va_space_get(filp);
+            uvm_fd_type_set(filp, UVM_FD_VA_SPACE, va_space);
+            break;

-        if (params->flags != va_space->initialization_flags)
+        case UVM_FD_VA_SPACE:
+            va_space = uvm_va_space_get(filp);
+            if (params->flags != va_space->initialization_flags)
+                status = NV_ERR_INVALID_ARGUMENT;
+            else
+                status = NV_OK;
+
+            break;
+
+        case UVM_FD_MM:
+        case UVM_FD_TEST:
            status = NV_ERR_INVALID_ARGUMENT;
-        else
-            status = NV_OK;
-    }
-    else if (old_fd_type == UVM_FD_MM) {
-        status = NV_ERR_INVALID_ARGUMENT;
-    }
-    else {
-        UVM_ASSERT(old_fd_type == UVM_FD_INITIALIZING);
-        status = NV_ERR_BUSY_RETRY;
+            break;
+
+        case UVM_FD_INITIALIZING:
+            status = NV_ERR_BUSY_RETRY;
+            break;
+
+        default:
+            UVM_ASSERT(0);
+            status = NV_ERR_INVALID_STATE; // Quiet compiler warnings
+            break;
    }

    return status;
@@ -1061,6 +1016,7 @@ static long uvm_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
        UVM_ROUTE_CMD_ALLOC_INIT_CHECK(UVM_MAP_EXTERNAL_ALLOCATION,        uvm_api_map_external_allocation);
        UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_MAP_EXTERNAL_SPARSE,            uvm_api_map_external_sparse);
        UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_FREE,                           uvm_api_free);
+        UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_DISCARD,                        uvm_api_discard);
        UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_PREVENT_MIGRATION_RANGE_GROUPS, uvm_api_prevent_migration_range_groups);
        UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_ALLOW_MIGRATION_RANGE_GROUPS,   uvm_api_allow_migration_range_groups);
        UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_SET_PREFERRED_LOCATION,         uvm_api_set_preferred_location);
--- a/kernel-open/nvidia-uvm/uvm.h
+++ b/kernel-open/nvidia-uvm/uvm.h
@@ -1,5 +1,5 @@
 /*******************************************************************************
-    Copyright (c) 2013-2024 NVIDIA Corporation
+    Copyright (c) 2013-2025 NVIDIA Corporation

    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to
@@ -1430,9 +1430,9 @@ NV_STATUS UvmAllocDeviceP2P(NvProcessorUuid gpuUuid,
 // UvmMigrate
 //
 // Migrates the backing of a given virtual address range to the specified
-// destination processor. If any page in the VA range is unpopulated, it is
-// populated at the destination processor. The migrated pages in the VA range
-// are also mapped on the destination processor.
+// destination processor's nearest memory. If any page in the VA range is
+// unpopulated, it is populated at the destination processor. The migrated pages
+// in the VA range are also mapped on the destination processor.
 //
 // Both base and length must be aligned to the smallest page size supported by
 // the CPU. The VA range must lie within the largest possible virtual address
@@ -1456,17 +1456,19 @@ NV_STATUS UvmAllocDeviceP2P(NvProcessorUuid gpuUuid,
 // they will not be migrated.
 //
 // If the input virtual range corresponds to system-allocated pageable memory,
-// and UvmIsPageableMemoryAccessSupported reports that pageable memory access
-// is supported, then the driver will populate any unpopulated pages at the
+// and UvmIsPageableMemoryAccessSupported reports that pageable memory access is
+// supported, then the driver will populate any unpopulated pages at the
 // destination processor and migrate the data from any source location to the
-// destination. Pages in the VA range are migrated even if their preferred
-// location is set to a processor other than the destination processor.
-// If the accessed-by list of any of the pages in the VA range is not empty,
-// then mappings to those pages from all the appropriate processors are updated
-// to refer to the new location if establishing such a mapping is possible.
-// Otherwise, those mappings are cleared.
-// Note that in this case, software managed pageable memory does not support
-// migration of MAP_SHARED, file-backed, or PROT_NONE mappings.
+// destination. On coherent platforms, if the destination processor is a GPU and
+// the GPU is not a NUMA node, pages will be populated on the closest CPU NUMA
+// node if they are not already populated anywhere. Pages in the VA range are
+// migrated even if their preferred location is set to a processor other than
+// the destination processor. If the accessed-by list of any of the pages in the
+// VA range is not empty, then mappings to those pages from all the appropriate
+// processors are updated to refer to the new location if establishing such a
+// mapping is possible. Otherwise, those mappings are cleared. Note that in this
+// case, software managed pageable memory does not support migration of
+// MAP_SHARED, file-backed, or PROT_NONE mappings.
 //
 // If any pages in the given VA range are associated with a range group which
 // has been made non-migratable via UvmPreventMigrationRangeGroups, then those
@@ -2124,11 +2126,6 @@ NV_STATUS UvmUnmapExternal(void                  *base,
                           NvLength               length,
                           const NvProcessorUuid *gpuUuid);

-// TODO: Bug 2732305: Remove this declaration when the new external APIs have
-//       been implemented.
-NV_STATUS UvmUnmapExternalAllocation(void                  *base,
-                                     const NvProcessorUuid *gpuUuid);
-
 //------------------------------------------------------------------------------
 // UvmMapDynamicParallelismRegion
 //
@@ -2207,9 +2204,9 @@ NV_STATUS UvmMapDynamicParallelismRegion(void                  *base,
 // allocated via a call to either UvmAlloc or UvmMemMap, or be supported
 // system-allocated pageable memory. If the input virtual range corresponds to
 // system-allocated pageable memory and UvmIsPageableMemoryAccessSupported
-// reports that pageable memory access is supported, the behavior described
-// below does not take effect, and read duplication will not be enabled for
-// the input range.
+// reports that pageable memory access is supported, or if a memoryless
+// processor is present, the behavior described below does not take effect, and
+// read duplication will not be enabled for the input range.
 //
 // Both base and length must be aligned to the smallest page size supported by
 // the CPU.
@@ -2330,7 +2327,7 @@ NV_STATUS UvmDisableReadDuplication(void     *base,
 // UvmSetPreferredLocation
 //
 // Sets the preferred location for the given virtual address range to be the
-// specified processor's memory.
+// specified processor's nearest memory.
 //
 // Both base and length must be aligned to the smallest page size supported by
 // the CPU. The VA range must lie within the largest possible virtual address
@@ -2359,6 +2356,11 @@ NV_STATUS UvmDisableReadDuplication(void     *base,
 // not cause a migration if a mapping for that page from that processor can be
 // established without migrating the page.
 //
+// If the specified processor is a GPU and the GPU is not a NUMA node and the
+// input range is system-allocated pageable memory and the system supports
+// transparent access to pageable memory, preferred location will be set to the
+// closest CPU NUMA node.
+//
 // When a page that was allocated via either UvmAlloc or UvmMemMap migrates away
 // from its preferred location, the mapping on the preferred location's
 // processor is cleared so that the next access from that processor will cause a
@@ -2675,6 +2677,111 @@ NV_STATUS UvmUnsetAccessedBy(void                  *base,
                             NvLength               length,
                             const NvProcessorUuid *accessedByUuid);

+//------------------------------------------------------------------------------
+// UvmDiscard
+//
+// Inform the UVM driver that the data in the specified virtual address range
+// is no longer needed.
+//
+// Both base and length must be aligned to the smallest page size supported by
+// the CPU. The VA range must lie within the largest possible virtual address
+// supported by the specified processor.
+//
+// The virtual address range specified by (base, length) must have been
+// allocated via a call to either UvmAlloc or UvmMemMap, or be supported
+// system-allocated pageable memory.
+//
+// If the input virtual range corresponds to system-allocated pageable memory,
+// and there is at least one GPU in the system that supports transparent access
+// to pageable memory, the behavior described in the next paragraphs does not
+// take effect.
+//
+// When a virtual address range is discarded using this API, any
+// read-duplicated copies are collapsed. UvmDiscard will not cause the
+// immediate migration of any pages covered by the specified virtual address
+// range.
+//
+// A discard operation done without the flag UVM_DISCARD_FLAGS_UNMAP will be
+// faster than an operation with that flag, but clearing the discard status can
+// only be done with a migration API call as described below.
+//
+// After a page has been discarded, reads and writes to/from discarded memory
+// have the following behavior:
+//
+//   * Reads and writes to/from memory discarded without
+//     UVM_DISCARD_FLAGS_UNMAP have undefined behavior.
+//   * Reads and writes to/from memory discarded without
+//     UVM_DISCARD_FLAGS_UNMAP will not clear the discard status.
+//   * Reads from memory discarded with UVM_DISCARD_FLAGS_UNMAP, including
+//     back-to-back reads, return indeterminate data.
+//   * Writes to memory discarded with UVM_DISCARD_FLAGS_UNMAP
+//     - are guaranteed to land and remove the discard status of the virtual
+//       address,
+//     - any reads after a write will observe the written data,
+//     - will collapse any read-duplicated copies of the virtual address.
+//
+// UvmDiscard can happen concurrently with memory migrations.Therefore, the
+// caller is responsible for serializing page accesses and/or migrations and
+// discard operations.
+//
+// Calls to UvmMigrate, UvmMigrateAsync, UvmPreventMigrationRangeGroups, or
+// UvmMigrateRangeGroup, on a discarded virtual address range will cause the
+// collapsing of any discarded read-duplicated pages and will clear the discard
+// status of all discarded pages in the migrated VA range.
+//
+// If discarded memory is evicted, the data in the pages backing the evicted
+// virtual range is not copied to the eviction destination and the discard
+// status of the evicted pages is not cleared. Pages that have been discarded
+// will be selected for eviction before pages that require copies during
+// eviction.
+//
+// If UvmEnableReadDuplication/UvmDisableReadDuplication is called on a
+// discarded virtual address range, the discard status of the range is not
+// cleared.
+//
+// If discarded pages are in a processor's accessed-by list, mappings to those
+// pages are not guaranteed be created on the processor while the page is
+// discarded.
+//
+// If UvmSetPreferredLocation is called on a discarded virtual address range,
+// data from the pages backing the range will not be copied if those pages
+// require migration as a result of setting the preferred location.
+//
+// Calling this API while a non-fault-capable GPU is registered, will result in
+// the API returning an error. If a non-fault-capable GPU is registered after
+// pages have been discarded, UvmPreventMigrationRangeGroup will clear the
+// discard status of the range.
+//
+// Arguments:
+//     base: (INPUT)
+//         Base address of the virtual address range.
+//
+//     length: (INPUT)
+//         Length, in bytes, of the range.
+//
+//     flags: (INPUT)
+//         UvmDiscard operation flags.
+//            UVM_DISCARD_FLAGS_UNMAP: The discarded pages will be unmapped.
+//            This allows future writes to remove the discard status.
+//
+// Errors:
+//     NV_ERR_INVALID_ADDRESS:
+//         base and length are not properly aligned, the range does not
+//         represent a valid UVM allocation, or the range is not covered by a
+//         single UVM managed VA range.
+//
+//     NV_ERR_INVALID_ARGUMENT:
+//         the flags parameter is not valid.
+//
+//     NV_ERR_INVALID_DEVICE:
+//         At least one non-fault-capable GPU has a registered VA space.
+//
+//     NV_ERR_NO_MEMORY:
+//         Internal memory allocation failed.
+//
+//------------------------------------------------------------------------------
+NV_STATUS UvmDiscard(void *base, NvLength length, NvU64 flags);
+
 //------------------------------------------------------------------------------
 // UvmEnableSystemWideAtomics
 //
--- a/kernel-open/nvidia-uvm/uvm_ada.c
+++ b/kernel-open/nvidia-uvm/uvm_ada.c
@@ -78,8 +78,6 @@ void uvm_hal_ada_arch_init_properties(uvm_parent_gpu_t *parent_gpu)

    parent_gpu->non_replayable_faults_supported = true;

-    parent_gpu->access_counters_supported = true;
-
    parent_gpu->fault_cancel_va_supported = true;

    parent_gpu->scoped_atomics_supported = true;
@@ -96,7 +94,7 @@ void uvm_hal_ada_arch_init_properties(uvm_parent_gpu_t *parent_gpu)

    parent_gpu->plc_supported = true;

-    parent_gpu->no_ats_range_required = false;
+    parent_gpu->ats.no_ats_range_required = false;

    parent_gpu->conf_computing.per_channel_key_rotation = false;
 }
--- a/kernel-open/nvidia-uvm/uvm_ampere.c
+++ b/kernel-open/nvidia-uvm/uvm_ampere.c
@@ -82,8 +82,6 @@ void uvm_hal_ampere_arch_init_properties(uvm_parent_gpu_t *parent_gpu)

    parent_gpu->non_replayable_faults_supported = true;

-    parent_gpu->access_counters_supported = true;
-
    parent_gpu->fault_cancel_va_supported = true;

    parent_gpu->scoped_atomics_supported = true;
@@ -105,7 +103,7 @@ void uvm_hal_ampere_arch_init_properties(uvm_parent_gpu_t *parent_gpu)

    parent_gpu->plc_supported = true;

-    parent_gpu->no_ats_range_required = false;
+    parent_gpu->ats.no_ats_range_required = false;

    parent_gpu->conf_computing.per_channel_key_rotation = false;
 }
--- a/kernel-open/nvidia-uvm/uvm_api.h
+++ b/kernel-open/nvidia-uvm/uvm_api.h
@@ -1,5 +1,5 @@
 /*******************************************************************************
-    Copyright (c) 2015-2019 NVIDIA Corporation
+    Copyright (c) 2015-2025 NVIDIA Corporation

    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to
@@ -32,7 +32,7 @@
 #include "uvm_thread_context.h"
 #include "uvm_kvmalloc.h"
 #include "uvm_va_space.h"
-#include "nv_uvm_types.h"
+#include "nv_uvm_user_types.h"

 // This weird number comes from UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS. That
 // ioctl is called frequently so we don't want to allocate a copy every time.
@@ -189,7 +189,7 @@ static bool uvm_api_range_invalid(NvU64 base, NvU64 length)
 }

 // Some APIs can only enforce 4K alignment as it's the smallest GPU page size
-// even when the smallest host page is larger (e.g. 64K on ppc64le).
+// even when the smallest host page is larger.
 static bool uvm_api_range_invalid_4k(NvU64 base, NvU64 length)
 {
    return uvm_api_range_invalid_aligned(base, length, UVM_PAGE_SIZE_4K);
@@ -212,6 +212,10 @@ typedef enum
 // If the interval [base, base + length) is fully covered by VMAs which all have
 // the same uvm_api_range_type_t, that range type is returned.
 //
+// If the platform supports ATS but no GPU has yet been registered and a
+// possible ATS range is identified then the VA space state is updated such that
+// it will only be possible to register GPUs that support ATS.
+//
 // LOCKING: va_space->lock must be held in at least read mode. If mm != NULL,
 //          mm->mmap_lock must also be held in at least read mode.
 uvm_api_range_type_t uvm_api_range_type_check(uvm_va_space_t *va_space, struct mm_struct *mm, NvU64 base, NvU64 length);
@@ -228,6 +232,7 @@ NV_STATUS uvm_api_create_external_range(UVM_CREATE_EXTERNAL_RANGE_PARAMS *params
 NV_STATUS uvm_api_map_external_allocation(UVM_MAP_EXTERNAL_ALLOCATION_PARAMS *params, struct file *filp);
 NV_STATUS uvm_api_map_external_sparse(UVM_MAP_EXTERNAL_SPARSE_PARAMS *params, struct file *filp);
 NV_STATUS uvm_api_free(UVM_FREE_PARAMS *params, struct file *filp);
+NV_STATUS uvm_api_discard(UVM_DISCARD_PARAMS *params, struct file *filp);
 NV_STATUS uvm_api_prevent_migration_range_groups(UVM_PREVENT_MIGRATION_RANGE_GROUPS_PARAMS *params, struct file *filp);
 NV_STATUS uvm_api_allow_migration_range_groups(UVM_ALLOW_MIGRATION_RANGE_GROUPS_PARAMS *params, struct file *filp);
 NV_STATUS uvm_api_set_preferred_location(const UVM_SET_PREFERRED_LOCATION_PARAMS *params, struct file *filp);
--- a/kernel-open/nvidia-uvm/uvm_ats.c
+++ b/kernel-open/nvidia-uvm/uvm_ats.c
@@ -1,5 +1,5 @@
 /*******************************************************************************
-    Copyright (c) 2018-2024 NVIDIA Corporation
+    Copyright (c) 2018-2025 NVIDIA Corporation

    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to
@@ -42,26 +42,11 @@ void uvm_ats_init(const UvmPlatformInfo *platform_info)
                               uvm_va_space_mm_enabled_system();
 }

-void uvm_ats_init_va_space(uvm_va_space_t *va_space)
-{
-    uvm_init_rwsem(&va_space->ats.lock, UVM_LOCK_ORDER_LEAF);
-
-    if (UVM_ATS_IBM_SUPPORTED())
-        uvm_ats_ibm_init_va_space(va_space);
-}
-
 NV_STATUS uvm_ats_add_gpu(uvm_parent_gpu_t *parent_gpu)
 {
-    if (UVM_ATS_IBM_SUPPORTED()) {
-        // uvm_ibm_add_gpu() needs to be called even if ATS is disabled since it
-        // sets parent_gpu->npu. Not setting parent_gpu->npu will result in
-        // incorrect NVLink addresses. See dma_addr_to_gpu_addr().
-
-        return uvm_ats_ibm_add_gpu(parent_gpu);
-    }
-    else if (UVM_ATS_SVA_SUPPORTED()) {
-        if (g_uvm_global.ats.enabled)
-            return uvm_ats_sva_add_gpu(parent_gpu);
+    if (g_uvm_global.ats.enabled && uvm_parent_gpu_supports_ats(parent_gpu)) {
+        UVM_ASSERT(UVM_ATS_SVA_SUPPORTED());
+        return uvm_ats_sva_add_gpu(parent_gpu);
    }

    return NV_OK;
@@ -69,38 +54,25 @@ NV_STATUS uvm_ats_add_gpu(uvm_parent_gpu_t *parent_gpu)

 void uvm_ats_remove_gpu(uvm_parent_gpu_t *parent_gpu)
 {
-    if (UVM_ATS_IBM_SUPPORTED()) {
-        // uvm_ibm_remove_gpu() needs to be called even if ATS is disabled since
-        // uvm_ibm_add_gpu() is called even in that case and
-        // uvm_ibm_remove_gpu() needs to undo the work done by
-        // uvm_ats_add_gpu() (gpu retained_count etc.).
-
-        uvm_ats_ibm_remove_gpu(parent_gpu);
-    }
-    else if (UVM_ATS_SVA_SUPPORTED()) {
-        if (g_uvm_global.ats.enabled)
-            uvm_ats_sva_remove_gpu(parent_gpu);
+    if (g_uvm_global.ats.enabled && uvm_parent_gpu_supports_ats(parent_gpu)) {
+        UVM_ASSERT(UVM_ATS_SVA_SUPPORTED());
+        uvm_ats_sva_remove_gpu(parent_gpu);
    }
 }

 NV_STATUS uvm_ats_bind_gpu(uvm_gpu_va_space_t *gpu_va_space)
 {
-    NV_STATUS status = NV_OK;
-
    UVM_ASSERT(gpu_va_space);

    if (!gpu_va_space->ats.enabled)
-        return status;
+        return NV_OK;
+
+    UVM_ASSERT(UVM_ATS_SVA_SUPPORTED());

    uvm_assert_lockable_order(UVM_LOCK_ORDER_MMAP_LOCK);
    uvm_assert_lockable_order(UVM_LOCK_ORDER_VA_SPACE);

-    if (UVM_ATS_IBM_SUPPORTED())
-        status = uvm_ats_ibm_bind_gpu(gpu_va_space);
-    else if (UVM_ATS_SVA_SUPPORTED())
-        status = uvm_ats_sva_bind_gpu(gpu_va_space);
-
-    return status;
+    return uvm_ats_sva_bind_gpu(gpu_va_space);
 }

 void uvm_ats_unbind_gpu(uvm_gpu_va_space_t *gpu_va_space)
@@ -110,10 +82,9 @@ void uvm_ats_unbind_gpu(uvm_gpu_va_space_t *gpu_va_space)
    if (!gpu_va_space->ats.enabled)
        return;

-    if (UVM_ATS_IBM_SUPPORTED())
-        uvm_ats_ibm_unbind_gpu(gpu_va_space);
-    else if (UVM_ATS_SVA_SUPPORTED())
-        uvm_ats_sva_unbind_gpu(gpu_va_space);
+    UVM_ASSERT(UVM_ATS_SVA_SUPPORTED());
+
+    uvm_ats_sva_unbind_gpu(gpu_va_space);
 }

 NV_STATUS uvm_ats_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space)
@@ -127,6 +98,8 @@ NV_STATUS uvm_ats_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space)
    if (!gpu_va_space->ats.enabled)
        return status;

+    UVM_ASSERT(UVM_ATS_SVA_SUPPORTED());
+
    va_space = gpu_va_space->va_space;
    UVM_ASSERT(va_space);

@@ -138,10 +111,7 @@ NV_STATUS uvm_ats_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space)
    if (uvm_processor_mask_test(&va_space->ats.registered_gpu_va_spaces, gpu_id))
        return NV_ERR_INVALID_DEVICE;

-    if (UVM_ATS_IBM_SUPPORTED())
-        status = uvm_ats_ibm_register_gpu_va_space(gpu_va_space);
-    else if (UVM_ATS_SVA_SUPPORTED())
-        status = uvm_ats_sva_register_gpu_va_space(gpu_va_space);
+    status = uvm_ats_sva_register_gpu_va_space(gpu_va_space);

    if (status == NV_OK)
        uvm_processor_mask_set(&va_space->ats.registered_gpu_va_spaces, gpu_id);
@@ -159,25 +129,14 @@ void uvm_ats_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space)
    if (!gpu_va_space->ats.enabled)
        return;

+    UVM_ASSERT(UVM_ATS_SVA_SUPPORTED());
+
    va_space = gpu_va_space->va_space;
    gpu_id = gpu_va_space->gpu->id;

-    if (UVM_ATS_IBM_SUPPORTED())
-        uvm_ats_ibm_unregister_gpu_va_space(gpu_va_space);
-    else if (UVM_ATS_SVA_SUPPORTED())
-        uvm_ats_sva_unregister_gpu_va_space(gpu_va_space);
+    uvm_ats_sva_unregister_gpu_va_space(gpu_va_space);

    uvm_va_space_down_write(va_space);
    uvm_processor_mask_clear(&va_space->ats.registered_gpu_va_spaces, gpu_id);
    uvm_va_space_up_write(va_space);
 }
-
-void uvm_ats_invalidate(uvm_va_space_t *va_space, NvU64 start, NvU64 end)
-{
-    // We can only reach here from the mmu_notifier callbacks and these callbacks
-    // wouldn't have been registered if ATS wasn't enabled.
-    UVM_ASSERT(g_uvm_global.ats.enabled);
-
-    if (UVM_ATS_IBM_SUPPORTED())
-        uvm_ats_ibm_invalidate(va_space, start, end);
-}
--- a/kernel-open/nvidia-uvm/uvm_ats.h
+++ b/kernel-open/nvidia-uvm/uvm_ats.h
@@ -1,5 +1,5 @@
 /*******************************************************************************
-    Copyright (c) 2018-2024 NVIDIA Corporation
+    Copyright (c) 2018-2025 NVIDIA Corporation

    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to
@@ -26,12 +26,32 @@

 #include "uvm_linux.h"
 #include "uvm_forward_decl.h"
-#include "uvm_ats_ibm.h"
 #include "nv_uvm_types.h"
 #include "uvm_lock.h"
 #include "uvm_ats_sva.h"

-#define UVM_ATS_SUPPORTED() (UVM_ATS_IBM_SUPPORTED() || UVM_ATS_SVA_SUPPORTED())
+#define UVM_ATS_SUPPORTED() UVM_ATS_SVA_SUPPORTED()
+
+typedef enum
+{
+    // The VA space has been initialized on a system that supports ATS but it is
+    // unknown yet whether it will hold ATS capable GPUs or not.
+    UVM_ATS_VA_SPACE_ATS_UNSET = 0,
+
+    // The VA space only allows registering GPUs that support ATS. This state is
+    // entered on a system that supports ATS by:
+    //   - Registering an ATS capable GPU
+    //   - Migrating or setting a policy on pageable memory
+    // Once entered, this state is never left.
+    UVM_ATS_VA_SPACE_ATS_SUPPORTED,
+
+    // The VA space only allows registering GPUs that do not support ATS. This
+    // state is entered by:
+    //   - Initialization on platforms that do not support ATS
+    //   - Registering a non ATS capable GPU on platforms that do support ATS
+    // Once entered, this state is never left.
+    UVM_ATS_VA_SPACE_ATS_UNSUPPORTED
+} uvm_ats_va_space_state_t;

 typedef struct
 {
@@ -43,12 +63,20 @@ typedef struct
    // being called in ats_compute_residency_mask().
    uvm_rw_semaphore_t lock;

-    union
-    {
-        uvm_ibm_va_space_t ibm;
+    uvm_sva_va_space_t sva;

-        uvm_sva_va_space_t sva;
-    };
+    // Tracks if ATS is supported in this va_space. The state is set during GPU
+    // registration or some ATS related calls, and is protected as an atomic.
+    // This is because during some ATS related API calls a VA space can
+    // transition from UNSET to ATS_SUPPORTED. In these cases the va_space's
+    // semaphore is only held in a read-locked state. A race results in the
+    // duplicate writing of ATS_SUPPORTED to the state value. 
+    // This OK as the only possible transition here is
+    // UVM_ATS_VA_SPACE_ATS_UNSET -> UVM_ATS_VA_SPACE_ATS_SUPPORTED.
+    // Entering UVM_ATS_VA_SPACE_ATS_UNSUPPORTED requires registering a
+    // GPU in the VA space which must hold the lock in write mode.
+    // Enums from uvm_ats_va_space_state_t are stored in this atomic_t value.
+    atomic_t state;
 } uvm_ats_va_space_t;

 typedef struct
@@ -61,12 +89,7 @@ typedef struct

    NvU32 pasid;

-    union
-    {
-        uvm_ibm_gpu_va_space_t ibm;
-
-        uvm_sva_gpu_va_space_t sva;
-    };
+    uvm_sva_gpu_va_space_t sva;
 } uvm_ats_gpu_va_space_t;

 // Initializes driver-wide ATS state
@@ -74,11 +97,6 @@ typedef struct
 // LOCKING: None
 void uvm_ats_init(const UvmPlatformInfo *platform_info);

-// Initializes ATS specific GPU state
-//
-// LOCKING: None
-void uvm_ats_init_va_space(uvm_va_space_t *va_space);
-
 // Enables ATS feature on the GPU.
 //
 // LOCKING: g_uvm_global.global lock mutex must be held.
@@ -115,8 +133,6 @@ void uvm_ats_unbind_gpu(uvm_gpu_va_space_t *gpu_va_space);
 //
 // LOCKING: The VA space lock must be held in write mode.
 //          mm has to be retained prior to calling this function.
-//          current->mm->mmap_lock must be held in write mode iff
-//          UVM_ATS_IBM_SUPPORTED_IN_KERNEL() is 1.
 NV_STATUS uvm_ats_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space);

 // Disables ATS access for the gpu_va_space. Prior to calling this function,
@@ -124,19 +140,8 @@ NV_STATUS uvm_ats_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space);
 // accesses in this GPU VA space, and that no ATS fault handling for this
 // GPU will be attempted.
 //
-// LOCKING: This function may block on mmap_lock and will acquire the VA space
-// lock, so neither lock must be held.
+// LOCKING: This function will acquire the VA space lock, so it must not be
+// held.
 void uvm_ats_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space);

-// Synchronously invalidate ATS translations cached by GPU TLBs. The
-// invalidate applies to all GPUs with active GPU VA spaces in va_space, and
-// covers all pages touching any part of the given range. end is inclusive.
-//
-// GMMU translations in the given range are not guaranteed to be
-// invalidated.
-//
-// LOCKING: No locks are required, but this function may be called with
-//          interrupts disabled.
-void uvm_ats_invalidate(uvm_va_space_t *va_space, NvU64 start, NvU64 end);
-
 #endif // __UVM_ATS_H__
--- a/kernel-open/nvidia-uvm/uvm_ats_faults.c
+++ b/kernel-open/nvidia-uvm/uvm_ats_faults.c
@@ -22,6 +22,7 @@

 #include "uvm_api.h"
 #include "uvm_tools.h"
+#include "uvm_va_block_types.h"
 #include "uvm_va_range.h"
 #include "uvm_ats.h"
 #include "uvm_ats_faults.h"
@@ -58,37 +59,6 @@ static NV_STATUS service_ats_requests(uvm_gpu_va_space_t *gpu_va_space,
    bool write = (access_type >= UVM_FAULT_ACCESS_TYPE_WRITE);
    bool is_fault_service_type = (service_type == UVM_ATS_SERVICE_TYPE_FAULTS);
    bool is_prefetch_faults = (is_fault_service_type && (access_type == UVM_FAULT_ACCESS_TYPE_PREFETCH));
-    uvm_populate_permissions_t populate_permissions = is_fault_service_type ?
-                                            (write ? UVM_POPULATE_PERMISSIONS_WRITE : UVM_POPULATE_PERMISSIONS_ANY) :
-                                            UVM_POPULATE_PERMISSIONS_INHERIT;
-
-
-    // Request uvm_migrate_pageable() to touch the corresponding page after
-    // population.
-    // Under virtualization ATS provides two translations:
-    // 1) guest virtual -> guest physical
-    // 2) guest physical -> host physical
-    //
-    // The overall ATS translation will fault if either of those translations is
-    // invalid. The pin_user_pages() call within uvm_migrate_pageable() call
-    // below handles translation #1, but not #2. We don't know if we're running
-    // as a guest, but in case we are we can force that translation to be valid
-    // by touching the guest physical address from the CPU. If the translation
-    // is not valid then the access will cause a hypervisor fault. Note that
-    // dma_map_page() can't establish mappings used by GPU ATS SVA translations.
-    // GPU accesses to host physical addresses obtained as a result of the
-    // address translation request uses the CPU address space instead of the
-    // IOMMU address space since the translated host physical address isn't
-    // necessarily an IOMMU address. The only way to establish guest physical to
-    // host physical mapping in the CPU address space is to touch the page from
-    // the CPU.
-    //
-    // We assume that the hypervisor mappings are all VM_PFNMAP, VM_SHARED, and
-    // VM_WRITE, meaning that the mappings are all granted write access on any
-    // fault and that the kernel will never revoke them.
-    // drivers/vfio/pci/vfio_pci_nvlink2.c enforces this. Thus we can assume
-    // that a read fault is always sufficient to also enable write access on the
-    // guest translation.

    uvm_migrate_args_t uvm_migrate_args =
    {
@@ -98,8 +68,8 @@ static NV_STATUS service_ats_requests(uvm_gpu_va_space_t *gpu_va_space,
        .dst_node_id                        = ats_context->residency_node,
        .start                              = start,
        .length                             = length,
-        .populate_permissions               = populate_permissions,
-        .touch                              = is_fault_service_type,
+        .populate_permissions               = UVM_POPULATE_PERMISSIONS_INHERIT,
+        .populate_flags                     = UVM_POPULATE_PAGEABLE_FLAG_SKIP_PROT_CHECK,
        .skip_mapped                        = is_fault_service_type,
        .populate_on_cpu_alloc_failures     = is_fault_service_type,
        .populate_on_migrate_vma_failures   = is_fault_service_type,
@@ -115,6 +85,22 @@ static NV_STATUS service_ats_requests(uvm_gpu_va_space_t *gpu_va_space,
        .fail_on_unresolved_sto_errors      = !is_fault_service_type || is_prefetch_faults,
    };

+    if (is_fault_service_type) {
+        uvm_migrate_args.populate_permissions = (write ? UVM_POPULATE_PERMISSIONS_WRITE : UVM_POPULATE_PERMISSIONS_ANY);
+
+        // If we're faulting, let the GPU access special vmas
+        uvm_migrate_args.populate_flags |= UVM_POPULATE_PAGEABLE_FLAG_ALLOW_SPECIAL;
+
+        if (ats_context->client_type == UVM_FAULT_CLIENT_TYPE_GPC)
+            uvm_migrate_args.cause = UVM_MAKE_RESIDENT_CAUSE_REPLAYABLE_FAULT;
+        else
+            uvm_migrate_args.cause = UVM_MAKE_RESIDENT_CAUSE_NON_REPLAYABLE_FAULT;
+    }
+    else {
+        uvm_migrate_args.cause = UVM_MAKE_RESIDENT_CAUSE_ACCESS_COUNTER;
+        uvm_migrate_args.access_counters_buffer_index = ats_context->access_counters.buffer_index;
+    }
+
    UVM_ASSERT(uvm_ats_can_service_faults(gpu_va_space, mm));

    // We are trying to use migrate_vma API in the kernel (if it exists) to
@@ -157,67 +143,73 @@ static void ats_batch_select_residency(uvm_gpu_va_space_t *gpu_va_space,
 {
    uvm_gpu_t *gpu = gpu_va_space->gpu;
    int residency;
+    bool cdmm_enabled = gpu->mem_info.cdmm_enabled;

-    UVM_ASSERT(gpu->mem_info.numa.enabled);
-    residency = uvm_gpu_numa_node(gpu);
-
-#if defined(NV_MEMPOLICY_HAS_UNIFIED_NODES)
-    struct mempolicy *vma_policy = vma_policy(vma);
-    unsigned short mode;
-
-    ats_context->prefetch_state.has_preferred_location = false;
-
-    // It's safe to read vma_policy since the mmap_lock is held in at least read
-    // mode in this path.
-    uvm_assert_mmap_lock_locked(vma->vm_mm);
-
-    if (!vma_policy)
-        goto done;
-
-    mode = vma_policy->mode;
-
-    if ((mode == MPOL_BIND)
-#if defined(NV_MPOL_PREFERRED_MANY_PRESENT)
-         || (mode == MPOL_PREFERRED_MANY)
-#endif
-         || (mode == MPOL_PREFERRED)) {
-        int home_node = NUMA_NO_NODE;
-
-#if defined(NV_MEMPOLICY_HAS_HOME_NODE)
-        if ((mode != MPOL_PREFERRED) && (vma_policy->home_node != NUMA_NO_NODE))
-            home_node = vma_policy->home_node;
-#endif
-
-        // Prefer home_node if set. Otherwise, prefer the faulting GPU if it's
-        // in the list of preferred nodes, else prefer the closest_cpu_numa_node
-        // to the GPU if closest_cpu_numa_node is in the list of preferred
-        // nodes. Fallback to the faulting GPU if all else fails.
-        if (home_node != NUMA_NO_NODE) {
-            residency = home_node;
-        }
-        else if (!node_isset(residency, vma_policy->nodes)) {
-            int closest_cpu_numa_node = gpu->parent->closest_cpu_numa_node;
-
-            if ((closest_cpu_numa_node != NUMA_NO_NODE) && node_isset(closest_cpu_numa_node, vma_policy->nodes))
-                residency = gpu->parent->closest_cpu_numa_node;
-            else
-                residency = first_node(vma_policy->nodes);
-        }
-
-        if (!nodes_empty(vma_policy->nodes))
-            ats_context->prefetch_state.has_preferred_location = true;
+    if (gpu->parent->is_integrated_gpu || cdmm_enabled) {
+        residency = gpu->parent->closest_cpu_numa_node;
+    }
+    else {
+        UVM_ASSERT(gpu->mem_info.numa.enabled);
+        residency = uvm_gpu_numa_node(gpu);
    }

-    // Update gpu if residency is not the faulting gpu.
-    if (residency != uvm_gpu_numa_node(gpu))
-        gpu = uvm_va_space_find_gpu_with_memory_node_id(gpu_va_space->va_space, residency);
-
-done:
-#else
    ats_context->prefetch_state.has_preferred_location = false;
+
+#if defined(NV_MEMPOLICY_HAS_UNIFIED_NODES)
+    {
+        struct mempolicy *vma_policy = vma_policy(vma);
+        unsigned short mode;
+
+        // It's safe to read vma_policy since the mmap_lock is held in at least
+        // read mode in this path.
+        uvm_assert_mmap_lock_locked(vma->vm_mm);
+
+        if (vma_policy) {
+            mode = vma_policy->mode;
+
+            if ((mode == MPOL_BIND)
+#if defined(NV_MPOL_PREFERRED_MANY_PRESENT)
+                 || (mode == MPOL_PREFERRED_MANY)
+#endif
+                 || (mode == MPOL_PREFERRED)) {
+                int home_node = NUMA_NO_NODE;
+
+#if defined(NV_MEMPOLICY_HAS_HOME_NODE)
+                if ((mode != MPOL_PREFERRED) && (vma_policy->home_node != NUMA_NO_NODE))
+                    home_node = vma_policy->home_node;
 #endif

-    ats_context->residency_id = gpu ? gpu->id : UVM_ID_CPU;
+                // Prefer home_node if set. Otherwise, prefer the faulting GPU
+                // if it's in the list of preferred nodes, else prefer the
+                // closest_cpu_numa_node to the GPU if closest_cpu_numa_node is
+                // in the list of preferred nodes. Fallback to the faulting GPU
+                // if all else fails.
+                if (home_node != NUMA_NO_NODE) {
+                    residency = home_node;
+                }
+                else if (!node_isset(residency, vma_policy->nodes)) {
+                    int closest_cpu_numa_node = gpu->parent->closest_cpu_numa_node;
+
+                    if ((closest_cpu_numa_node != NUMA_NO_NODE) &&
+                        node_isset(closest_cpu_numa_node, vma_policy->nodes))
+                        residency = gpu->parent->closest_cpu_numa_node;
+                    else
+                        residency = first_node(vma_policy->nodes);
+                }
+
+                if (!nodes_empty(vma_policy->nodes))
+                    ats_context->prefetch_state.has_preferred_location = true;
+            }
+
+            // Update gpu if residency is not the faulting gpu.
+            if (residency != uvm_gpu_numa_node(gpu))
+                gpu = uvm_va_space_find_gpu_with_memory_node_id(gpu_va_space->va_space, residency);
+
+        }
+    }
+#endif
+
+    ats_context->residency_id = gpu && !gpu->parent->is_integrated_gpu && !cdmm_enabled ? gpu->id : UVM_ID_CPU;
    ats_context->residency_node = residency;
 }

@@ -533,8 +525,20 @@ static NV_STATUS uvm_ats_service_faults_region(uvm_gpu_va_space_t *gpu_va_space,
                                  access_type,
                                  UVM_ATS_SERVICE_TYPE_FAULTS,
                                  ats_context);
-    if (status != NV_OK)
+    if (status != NV_OK) {
+        // This condition can occur if we unexpectedly fault on a vma that
+        // doesn't support faulting (or at least doesn't support
+        // pin_user_pages). This may be an incorrect mapping setup from the
+        // vma's owning driver, a hardware bug, or just that the owning driver
+        // didn't expect a device fault. Either way, we don't want to consider
+        // this a global error so don't propagate it, but also don't indicate
+        // that the faults were serviced. That way the caller knows to cancel
+        // them precisely.
+        if (status == NV_ERR_INVALID_ADDRESS)
+            return NV_OK;
+
        return status;
+    }

    uvm_page_mask_region_fill(faults_serviced_mask, region);

@@ -689,12 +693,14 @@ bool uvm_ats_check_in_gmmu_region(uvm_va_space_t *va_space, NvU64 address, uvm_v
        if (next->node.start <= gmmu_region_base + UVM_GMMU_ATS_GRANULARITY - 1)
            return true;

-        prev = uvm_va_range_container(uvm_range_tree_prev(&va_space->va_range_tree, &next->node));
+        prev = uvm_va_range_gmmu_mappable_prev(next);
    }
    else {
        // No VA range exists after address, so check the last VA range in the
        // tree.
        prev = uvm_va_range_container(uvm_range_tree_last(&va_space->va_range_tree));
+        while (prev && !uvm_va_range_is_gmmu_mappable(prev))
+            prev = uvm_va_range_gmmu_mappable_prev(prev);
    }

    return prev && (prev->node.end >= gmmu_region_base);
@@ -767,6 +773,20 @@ NV_STATUS uvm_ats_service_access_counters(uvm_gpu_va_space_t *gpu_va_space,
                         &ats_context->access_counters.accessed_mask,
                         &ats_context->prefetch_state.residency_mask);

+    // Pretend that pages that are already resident at the destination GPU were
+    // migrated now. This makes sure that the access counter is cleared even if
+    // the accessed pages, were already resident on the target.
+    // TODO: Bug 5296998: [uvm][ats] Not clearing stale access counter
+    //                     notifications can lead to missed migrations
+    // The same problem of stale notification exists for migration to other
+    // locations than local vidmem. However, stale notifications to data
+    // migrated to another remote location are identical to those triggered
+    // by accessing memory that cannot or should not be migrated.
+    if (uvm_id_equal(ats_context->residency_id, gpu_va_space->gpu->id)) {
+        uvm_page_mask_copy(&ats_context->access_counters.migrated_mask,
+                           &ats_context->prefetch_state.residency_mask);
+    }
+
    for_each_va_block_subregion_in_mask(subregion, &ats_context->access_counters.accessed_mask, region) {
        NV_STATUS status;
        NvU64 start = base + (subregion.first * PAGE_SIZE);
@@ -779,7 +799,7 @@ NV_STATUS uvm_ats_service_access_counters(uvm_gpu_va_space_t *gpu_va_space,

        status = service_ats_requests(gpu_va_space, vma, start, length, access_type, service_type, ats_context);

-        // clear access counters if pages were migrated or migration needs to
+        // Clear access counters if pages were migrated or migration needs to
        // be retried
        if (status == NV_OK || status == NV_ERR_BUSY_RETRY)
            uvm_page_mask_region_fill(migrated_mask, subregion);
--- a/kernel-open/nvidia-uvm/uvm_ats_ibm.c
+++ b/kernel-open/nvidia-uvm/uvm_ats_ibm.c
@@ -1,715 +0,0 @@
-/*******************************************************************************
-    Copyright (c) 2018-2019 NVIDIA Corporation
-
-    Permission is hereby granted, free of charge, to any person obtaining a copy
-    of this software and associated documentation files (the "Software"), to
-    deal in the Software without restriction, including without limitation the
-    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-    sell copies of the Software, and to permit persons to whom the Software is
-    furnished to do so, subject to the following conditions:
-
-        The above copyright notice and this permission notice shall be
-        included in all copies or substantial portions of the Software.
-
-    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-    DEALINGS IN THE SOFTWARE.
-
-*******************************************************************************/
-
-#include "uvm_api.h"
-#include "uvm_lock.h"
-#include "uvm_kvmalloc.h"
-#include "uvm_global.h"
-#include "uvm_va_space.h"
-#include "uvm_va_space_mm.h"
-#include "uvm_ats_ibm.h"
-#include "uvm_common.h"
-
-#include <linux/pci.h>
-
-#if UVM_IBM_NPU_SUPPORTED()
-
-#include <linux/of.h>
-#include <linux/sizes.h>
-#include <asm/pci-bridge.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/mmu_context.h>
-
-#define NPU_ATSD_REG_MAP_SIZE 32
-
-// There are three 8-byte registers in each ATSD mapping:
-#define NPU_ATSD_REG_LAUNCH 0
-#define NPU_ATSD_REG_AVA    1
-#define NPU_ATSD_REG_STAT   2
-
-// Fields within the NPU_ATSD_REG_LAUNCH register:
-
-// "PRS" (process-scoped) bit. 1 means to limit invalidates to the specified
-// PASID.
-#define NPU_ATSD_REG_LAUNCH_PASID_ENABLE    13
-
-// "PID" field. This specifies the PASID target of the invalidate.
-#define NPU_ATSD_REG_LAUNCH_PASID_VAL       38
-
-// "IS" bit. 0 means the specified virtual address range will be invalidated. 1
-// means all entries will be invalidated.
-#define NPU_ATSD_REG_LAUNCH_INVAL_ALL       12
-
-// "AP" field. This encodes the size of a range-based invalidate.
-#define NPU_ATSD_REG_LAUNCH_INVAL_SIZE      17
-
-// "No flush" bit. 0 will trigger a flush (membar) from the GPU following the
-// invalidate, 1 will not.
-#define NPU_ATSD_REG_LAUNCH_FLUSH_DISABLE   39
-
-// Helper to iterate over the active NPUs in the given VA space (all NPUs with
-// GPUs that have GPU VA spaces registered in this VA space).
-#define for_each_npu_index_in_va_space(npu_index, va_space)                                                 \
-    for (({uvm_assert_rwlock_locked(&(va_space)->ats.ibm.rwlock);                                           \
-           (npu_index) = find_first_bit((va_space)->ats.ibm.npu_active_mask, NV_MAX_NPUS);});               \
-           (npu_index) < NV_MAX_NPUS;                                                                       \
-           (npu_index) = find_next_bit((va_space)->ats.ibm.npu_active_mask, NV_MAX_NPUS, (npu_index) + 1))
-
-// An invalidate requires operating on one set of registers in each NPU. This
-// struct tracks which register set (id) is in use per NPU for a given
-// operation.
-typedef struct
-{
-    NvU8 ids[NV_MAX_NPUS];
-} uvm_atsd_regs_t;
-
-// Get the index of the input npu pointer within UVM's global npus array
-static size_t uvm_ibm_npu_index(uvm_ibm_npu_t *npu)
-{
-    size_t npu_index = npu - &g_uvm_global.npus[0];
-    UVM_ASSERT(npu_index < ARRAY_SIZE(g_uvm_global.npus));
-    return npu_index;
-}
-
-// Find an existing NPU matching pci_domain, or return an empty NPU slot if none
-// is found. Returns NULL if no slots are available.
-static uvm_ibm_npu_t *uvm_ibm_npu_find(int pci_domain)
-{
-    size_t i;
-    uvm_ibm_npu_t *npu, *first_free = NULL;
-
-    uvm_assert_mutex_locked(&g_uvm_global.global_lock);
-
-    for (i = 0; i < ARRAY_SIZE(g_uvm_global.npus); i++) {
-        npu = &g_uvm_global.npus[i];
-        if (npu->num_retained_gpus == 0) {
-            if (!first_free)
-                first_free = npu;
-        }
-        else if (npu->pci_domain == pci_domain) {
-            return npu;
-        }
-    }
-
-    return first_free;
-}
-
-static void uvm_ibm_npu_destroy(uvm_ibm_npu_t *npu)
-{
-    size_t i;
-
-    uvm_assert_mutex_locked(&g_uvm_global.global_lock);
-    UVM_ASSERT(npu->num_retained_gpus == 0);
-    UVM_ASSERT(bitmap_empty(npu->atsd_regs.locks, UVM_MAX_ATSD_REGS));
-
-    for (i = 0; i < npu->atsd_regs.count; i++) {
-        UVM_ASSERT(npu->atsd_regs.io_addrs[i]);
-        iounmap(npu->atsd_regs.io_addrs[i]);
-    }
-
-    memset(npu, 0, sizeof(*npu));
-}
-
-static NV_STATUS uvm_ibm_npu_init(uvm_ibm_npu_t *npu, struct pci_dev *npu_dev)
-{
-    struct pci_controller *hose;
-    size_t i, reg_count, reg_size = sizeof(npu->atsd_regs.io_addrs[0]);
-    int ret;
-
-    uvm_assert_mutex_locked(&g_uvm_global.global_lock);
-    UVM_ASSERT(npu->num_retained_gpus == 0);
-    UVM_ASSERT(bitmap_empty(npu->atsd_regs.locks, UVM_MAX_ATSD_REGS));
-
-    npu->pci_domain = pci_domain_nr(npu_dev->bus);
-
-    if (!UVM_ATS_IBM_SUPPORTED_IN_DRIVER())
-        return NV_OK;
-
-    hose = pci_bus_to_host(npu_dev->bus);
-
-    ret = of_property_count_elems_of_size(hose->dn, "ibm,mmio-atsd", reg_size);
-    if (ret < 0) {
-        UVM_ERR_PRINT("Failed to query NPU %d ATSD register count: %d\n", npu->pci_domain, ret);
-        return errno_to_nv_status(ret);
-    }
-
-    // For ATS to be enabled globally, we must have NPU ATSD registers
-    reg_count = ret;
-    if (reg_count == 0 || reg_count > UVM_MAX_ATSD_REGS) {
-        UVM_ERR_PRINT("NPU %d has invalid ATSD register count: %zu\n", npu->pci_domain, reg_count);
-        return NV_ERR_INVALID_STATE;
-    }
-
-    // Map the ATSD registers
-    for (i = 0; i < reg_count; i++) {
-        u64 phys_addr;
-        __be64 __iomem *io_addr;
-        ret = of_property_read_u64_index(hose->dn, "ibm,mmio-atsd", i, &phys_addr);
-        UVM_ASSERT(ret == 0);
-
-        io_addr = ioremap(phys_addr, NPU_ATSD_REG_MAP_SIZE);
-        if (!io_addr) {
-            uvm_ibm_npu_destroy(npu);
-            return NV_ERR_NO_MEMORY;
-        }
-
-        npu->atsd_regs.io_addrs[npu->atsd_regs.count++] = io_addr;
-    }
-
-    return NV_OK;
-}
-
-NV_STATUS uvm_ats_ibm_add_gpu(uvm_parent_gpu_t *parent_gpu)
-{
-    struct pci_dev *npu_dev = pnv_pci_get_npu_dev(parent_gpu->pci_dev, 0);
-    uvm_ibm_npu_t *npu;
-    NV_STATUS status;
-
-    uvm_assert_mutex_locked(&g_uvm_global.global_lock);
-
-    if (!npu_dev)
-        return NV_OK;
-
-    npu = uvm_ibm_npu_find(pci_domain_nr(npu_dev->bus));
-    if (!npu) {
-        // If this happens then we can't support the system configuation until
-        // NV_MAX_NPUS is updated. Return the same error as when the number of
-        // GPUs exceeds UVM_MAX_GPUS.
-        UVM_ERR_PRINT("No more NPU slots available, update NV_MAX_NPUS\n");
-        return NV_ERR_INSUFFICIENT_RESOURCES;
-    }
-
-    if (npu->num_retained_gpus == 0) {
-        status = uvm_ibm_npu_init(npu, npu_dev);
-        if (status != NV_OK)
-            return status;
-    }
-
-    // This npu field could be read concurrently by a thread in the ATSD
-    // invalidate path. We don't need to provide ordering with those threads
-    // because those invalidates won't apply to the GPU being added until a GPU
-    // VA space on this GPU is registered.
-    npu->atsd_regs.num_membars = max(npu->atsd_regs.num_membars, parent_gpu->num_hshub_tlb_invalidate_membars);
-
-    parent_gpu->npu = npu;
-    ++npu->num_retained_gpus;
-    return NV_OK;
-}
-
-void uvm_ats_ibm_remove_gpu(uvm_parent_gpu_t *parent_gpu)
-{
-    uvm_ibm_npu_t *npu = parent_gpu->npu;
-    uvm_parent_gpu_t *other_parent_gpu;
-    NvU32 num_membars_new = 0;
-
-    uvm_assert_mutex_locked(&g_uvm_global.global_lock);
-
-    if (!npu)
-        return;
-
-    UVM_ASSERT(npu->num_retained_gpus > 0);
-    if (--npu->num_retained_gpus == 0) {
-        uvm_ibm_npu_destroy(npu);
-    }
-    else {
-        // Re-calculate the membar count
-        for_each_parent_gpu(other_parent_gpu) {
-            // The current GPU being removed should've already been removed from
-            // the global list.
-            UVM_ASSERT(other_parent_gpu != parent_gpu);
-            if (other_parent_gpu->npu == npu)
-                num_membars_new = max(num_membars_new, other_parent_gpu->num_hshub_tlb_invalidate_membars);
-        }
-
-        UVM_ASSERT(num_membars_new > 0);
-        npu->atsd_regs.num_membars = num_membars_new;
-    }
-}
-
-#if UVM_ATS_IBM_SUPPORTED()
-
-void uvm_ats_ibm_init_va_space(uvm_va_space_t *va_space)
-{
-    uvm_ibm_va_space_t *ibm_va_space;
-
-    UVM_ASSERT(va_space);
-    ibm_va_space = &va_space->ats.ibm;
-
-    uvm_rwlock_irqsave_init(&ibm_va_space->rwlock, UVM_LOCK_ORDER_LEAF);
-}
-
-#if UVM_ATS_IBM_SUPPORTED_IN_KERNEL()
-static void npu_release_dummy(struct npu_context *npu_context, void *va_mm)
-{
-    // See the comment on the call to pnv_npu2_init_context()
-}
-
-static NV_STATUS uvm_ats_ibm_register_gpu_va_space_kernel(uvm_gpu_va_space_t *gpu_va_space)
-{
-    uvm_va_space_t *va_space = gpu_va_space->va_space;
-    uvm_ibm_gpu_va_space_t *ibm_gpu_va_space = &gpu_va_space->ats.ibm;
-    struct npu_context *npu_context;
-
-    // pnv_npu2_init_context() registers current->mm with
-    // mmu_notifier_register(). We need that to match the mm we passed to our
-    // own mmu_notifier_register() for this VA space.
-    if (current->mm != va_space->va_space_mm.mm)
-        return NV_ERR_NOT_SUPPORTED;
-
-    uvm_assert_mmap_lock_locked_write(current->mm);
-    uvm_assert_rwsem_locked_write(&va_space->lock);
-
-    // pnv_npu2_init_context() doesn't handle being called multiple times for
-    // the same GPU under the same mm, which could happen if multiple VA spaces
-    // are created in this process. To handle that we pass the VA space pointer
-    // as the callback parameter: the callback values are shared by all devices
-    // under this mm, so pnv_npu2_init_context() enforces that the values match
-    // the ones already registered to the mm.
-    //
-    // Otherwise we don't use the callback, since we have our own callback
-    // registered under the va_space_mm that will be called at the same point
-    // (mmu_notifier release).
-    npu_context = pnv_npu2_init_context(gpu_va_space->gpu->parent->pci_dev,
-                                        (MSR_DR | MSR_PR | MSR_HV),
-                                        npu_release_dummy,
-                                        va_space);
-    if (IS_ERR(npu_context)) {
-        int err = PTR_ERR(npu_context);
-
-        // We'll get -EINVAL if the callback value (va_space) differs from the
-        // one already registered to the npu_context associated with this mm.
-        // That can only happen when multiple VA spaces attempt registration
-        // within the same process, which is disallowed and should return
-        // NV_ERR_NOT_SUPPORTED.
-        if (err == -EINVAL)
-            return NV_ERR_NOT_SUPPORTED;
-        return errno_to_nv_status(err);
-    }
-
-    ibm_gpu_va_space->npu_context = npu_context;
-
-    return NV_OK;
-}
-
-static void uvm_ats_ibm_unregister_gpu_va_space_kernel(uvm_gpu_va_space_t *gpu_va_space)
-{
-    uvm_gpu_va_space_state_t state;
-    uvm_va_space_t *va_space = gpu_va_space->va_space;
-    uvm_ibm_va_space_t *ibm_va_space;
-    uvm_ibm_gpu_va_space_t *ibm_gpu_va_space = &gpu_va_space->ats.ibm;
-
-    if (!ibm_gpu_va_space->npu_context)
-        return;
-
-    // va_space is guaranteed to not be NULL if ibm_gpu_va_space->npu_context is
-    // not NULL.
-    UVM_ASSERT(va_space);
-
-    state = uvm_gpu_va_space_state(gpu_va_space);
-    UVM_ASSERT(state == UVM_GPU_VA_SPACE_STATE_INIT || state == UVM_GPU_VA_SPACE_STATE_DEAD);
-
-    ibm_va_space = &va_space->ats.ibm;
-
-    // pnv_npu2_destroy_context() may in turn call mmu_notifier_unregister().
-    // If uvm_va_space_mm_shutdown() is concurrently executing in another
-    // thread, mmu_notifier_unregister() will wait for
-    // uvm_va_space_mm_shutdown() to finish. uvm_va_space_mm_shutdown() takes
-    // mmap_lock and the VA space lock, so we can't be holding those locks on
-    // this path.
-    uvm_assert_unlocked_order(UVM_LOCK_ORDER_MMAP_LOCK);
-    uvm_assert_unlocked_order(UVM_LOCK_ORDER_VA_SPACE);
-
-    pnv_npu2_destroy_context(ibm_gpu_va_space->npu_context, gpu_va_space->gpu->parent->pci_dev);
-    ibm_gpu_va_space->npu_context = NULL;
-}
-
-#else
-
-static void uvm_ats_ibm_register_gpu_va_space_driver(uvm_gpu_va_space_t *gpu_va_space)
-{
-    uvm_va_space_t *va_space = gpu_va_space->va_space;
-    uvm_ibm_gpu_va_space_t *ibm_gpu_va_space = &gpu_va_space->ats.ibm;
-    uvm_gpu_t *gpu = gpu_va_space->gpu;
-    size_t npu_index = uvm_ibm_npu_index(gpu->parent->npu);
-    uvm_ibm_va_space_t *ibm_va_space;
-
-    UVM_ASSERT(va_space);
-    ibm_va_space = &va_space->ats.ibm;
-
-    uvm_assert_rwsem_locked_write(&va_space->lock);
-
-    uvm_write_lock_irqsave(&ibm_va_space->rwlock);
-
-    // If this is the first GPU VA space to use this NPU in the VA space, mark
-    // the NPU as active so invalidates are issued to it.
-    if (ibm_va_space->npu_ref_counts[npu_index] == 0) {
-        // If this is the first active NPU in the entire VA space, we have to
-        // tell the kernel to send TLB invalidations to the IOMMU. See kernel
-        // commit 03b8abedf4f4965e7e9e0d4f92877c42c07ce19f for background.
-        //
-        // This is safe to do without holding mm_users high or mmap_lock.
-        if (bitmap_empty(ibm_va_space->npu_active_mask, NV_MAX_NPUS))
-            mm_context_add_copro(va_space->va_space_mm.mm);
-
-        UVM_ASSERT(!test_bit(npu_index, ibm_va_space->npu_active_mask));
-        __set_bit(npu_index, ibm_va_space->npu_active_mask);
-    }
-    else {
-        UVM_ASSERT(test_bit(npu_index, ibm_va_space->npu_active_mask));
-    }
-
-    ++ibm_va_space->npu_ref_counts[npu_index];
-
-    // As soon as this lock is dropped, invalidates on this VA space's mm may
-    // begin issuing ATSDs to this NPU.
-    uvm_write_unlock_irqrestore(&ibm_va_space->rwlock);
-
-    ibm_gpu_va_space->did_ibm_driver_init = true;
-}
-
-static void uvm_ats_ibm_unregister_gpu_va_space_driver(uvm_gpu_va_space_t *gpu_va_space)
-{
-    uvm_va_space_t *va_space = gpu_va_space->va_space;
-    uvm_gpu_t *gpu = gpu_va_space->gpu;
-    size_t npu_index = uvm_ibm_npu_index(gpu->parent->npu);
-    bool do_remove = false;
-    uvm_ibm_va_space_t *ibm_va_space;
-    uvm_ibm_gpu_va_space_t *ibm_gpu_va_space = &gpu_va_space->ats.ibm;
-
-    if (!ibm_gpu_va_space->did_ibm_driver_init)
-        return;
-
-    UVM_ASSERT(va_space);
-    ibm_va_space = &va_space->ats.ibm;
-
-    // Note that we aren't holding the VA space lock here, so another thread
-    // could be in uvm_ats_ibm_register_gpu_va_space() for this same GPU right
-    // now. The write lock and ref counts below will handle that case.
-
-    // Once we return from this function with a bit cleared in the
-    // npu_active_mask, we have to guarantee that this VA space no longer
-    // accesses that NPU's ATSD registers. This is needed in case GPU unregister
-    // needs to unmap those registers. We use the reader/writer lock to
-    // guarantee this, which means that invalidations must not access the ATSD
-    // registers outside of the lock.
-    //
-    // Future work: if we could synchronize_srcu() on the mmu_notifier SRCU we
-    // might do that here instead to flush out all invalidates. That would allow
-    // us to avoid taking a read lock in the invalidate path, though we'd have
-    // to be careful when clearing the mask bit relative to the synchronize, and
-    // we'd have to be careful in cases where this thread doesn't hold a
-    // reference to mm_users.
-    uvm_write_lock_irqsave(&ibm_va_space->rwlock);
-
-    UVM_ASSERT(ibm_va_space->npu_ref_counts[npu_index] > 0);
-    UVM_ASSERT(test_bit(npu_index, ibm_va_space->npu_active_mask));
-
-    --ibm_va_space->npu_ref_counts[npu_index];
-    if (ibm_va_space->npu_ref_counts[npu_index] == 0) {
-        __clear_bit(npu_index, ibm_va_space->npu_active_mask);
-        if (bitmap_empty(ibm_va_space->npu_active_mask, NV_MAX_NPUS))
-            do_remove = true;
-    }
-
-    uvm_write_unlock_irqrestore(&ibm_va_space->rwlock);
-
-    if (do_remove) {
-        // mm_context_remove_copro() must be called outside of the spinlock
-        // because it may issue invalidates across CPUs in this mm. The
-        // coprocessor count is atomically refcounted by that function, so it's
-        // safe to call here even if another thread jumps in with a register and
-        // calls mm_context_add_copro() between this thread's unlock and this
-        // call.
-        UVM_ASSERT(va_space->va_space_mm.mm);
-        mm_context_remove_copro(va_space->va_space_mm.mm);
-    }
-}
-
-#endif // UVM_ATS_IBM_SUPPORTED_IN_KERNEL()
-
-static mm_context_id_t va_space_pasid(uvm_va_space_t *va_space)
-{
-    struct mm_struct *mm = va_space->va_space_mm.mm;
-    UVM_ASSERT(mm);
-    return mm->context.id;
-}
-
-NV_STATUS uvm_ats_ibm_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space)
-{
-    uvm_va_space_t *va_space = gpu_va_space->va_space;
-    NV_STATUS status = NV_OK;
-
-    UVM_ASSERT(gpu_va_space->ats.enabled);
-    UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_INIT);
-    UVM_ASSERT(va_space->va_space_mm.mm);
-    uvm_assert_rwsem_locked_write(&va_space->lock);
-
-#if UVM_ATS_IBM_SUPPORTED_IN_KERNEL()
-    status = uvm_ats_ibm_register_gpu_va_space_kernel(gpu_va_space);
-#else
-    uvm_ats_ibm_register_gpu_va_space_driver(gpu_va_space);
-#endif
-
-    gpu_va_space->ats.pasid = (NvU32) va_space_pasid(gpu_va_space->va_space);
-
-    return status;
-}
-
-void uvm_ats_ibm_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space)
-{
-#if UVM_ATS_IBM_SUPPORTED_IN_KERNEL()
-    uvm_ats_ibm_unregister_gpu_va_space_kernel(gpu_va_space);
-#else
-    uvm_ats_ibm_unregister_gpu_va_space_driver(gpu_va_space);
-#endif
-
-    gpu_va_space->ats.pasid = -1U;
-}
-
-#if UVM_ATS_IBM_SUPPORTED_IN_DRIVER()
-
-// Find any available ATSD register set in this NPU and return that index. This
-// will busy wait until a register set is free.
-static NvU8 atsd_reg_acquire(uvm_ibm_npu_t *npu)
-{
-    uvm_spin_loop_t spin;
-    size_t i;
-    bool first = true;
-
-    while (1) {
-        // Using for_each_clear_bit is racy, since the bits could change at any
-        // point. That's ok since we'll either just retry or use a real atomic
-        // to lock the bit. Checking for clear bits first avoids spamming
-        // atomics in the contended case.
-        for_each_clear_bit(i, npu->atsd_regs.locks, npu->atsd_regs.count) {
-            if (!test_and_set_bit_lock(i, npu->atsd_regs.locks))
-                return (NvU8)i;
-        }
-
-        // Back off and try again, avoiding the overhead of initializing the
-        // tracking timers unless we need them.
-        if (first) {
-            uvm_spin_loop_init(&spin);
-            first = false;
-        }
-        else {
-            UVM_SPIN_LOOP(&spin);
-        }
-    }
-}
-
-static void atsd_reg_release(uvm_ibm_npu_t *npu, NvU8 reg)
-{
-    UVM_ASSERT(reg < npu->atsd_regs.count);
-    UVM_ASSERT(test_bit(reg, npu->atsd_regs.locks));
-    clear_bit_unlock(reg, npu->atsd_regs.locks);
-}
-
-static __be64 atsd_reg_read(uvm_ibm_npu_t *npu, NvU8 reg, size_t offset)
-{
-    __be64 __iomem *io_addr = npu->atsd_regs.io_addrs[reg] + offset;
-    UVM_ASSERT(reg < npu->atsd_regs.count);
-    return __raw_readq(io_addr);
-}
-
-static void atsd_reg_write(uvm_ibm_npu_t *npu, NvU8 reg, size_t offset, NvU64 val)
-{
-    __be64 __iomem *io_addr = npu->atsd_regs.io_addrs[reg] + offset;
-    UVM_ASSERT(reg < npu->atsd_regs.count);
-    __raw_writeq_be(val, io_addr);
-}
-
-// Acquire a set of registers in each NPU which is active in va_space
-static void atsd_regs_acquire(uvm_va_space_t *va_space, uvm_atsd_regs_t *regs)
-{
-    size_t i;
-    for_each_npu_index_in_va_space(i, va_space)
-        regs->ids[i] = atsd_reg_acquire(&g_uvm_global.npus[i]);
-}
-
-static void atsd_regs_release(uvm_va_space_t *va_space, uvm_atsd_regs_t *regs)
-{
-    size_t i;
-    for_each_npu_index_in_va_space(i, va_space)
-        atsd_reg_release(&g_uvm_global.npus[i], regs->ids[i]);
-}
-
-// Write the provided value to each NPU active in va_space at the provided
-// register offset.
-static void atsd_regs_write(uvm_va_space_t *va_space, uvm_atsd_regs_t *regs, size_t offset, NvU64 val)
-{
-    size_t i;
-    for_each_npu_index_in_va_space(i, va_space)
-        atsd_reg_write(&g_uvm_global.npus[i], regs->ids[i], offset, val);
-}
-
-// Wait for all prior operations issued to active NPUs in va_space on the given
-// registers to finish.
-static void atsd_regs_wait(uvm_va_space_t *va_space, uvm_atsd_regs_t *regs)
-{
-    uvm_spin_loop_t spin;
-    size_t i;
-    for_each_npu_index_in_va_space(i, va_space) {
-        UVM_SPIN_WHILE(atsd_reg_read(&g_uvm_global.npus[i], regs->ids[i], NPU_ATSD_REG_STAT), &spin)
-            ;
-    }
-}
-
-// Encode an invalidate targeting the given pasid and the given size for the
-// NPU_ATSD_REG_LAUNCH register. The target address is encoded separately.
-//
-// psize must be one of the MMU_PAGE_* values defined in powerpc's asm/mmu.h. A
-// psize of MMU_PAGE_COUNT means to invalidate the entire address space.
-static NvU64 atsd_get_launch_val(mm_context_id_t pasid, int psize)
-{
-    NvU64 val = 0;
-
-    val |= PPC_BIT(NPU_ATSD_REG_LAUNCH_PASID_ENABLE);
-    val |= pasid << PPC_BITLSHIFT(NPU_ATSD_REG_LAUNCH_PASID_VAL);
-
-    if (psize == MMU_PAGE_COUNT) {
-        val |= PPC_BIT(NPU_ATSD_REG_LAUNCH_INVAL_ALL);
-    }
-    else {
-        // The NPU registers do not support arbitrary sizes
-        UVM_ASSERT(psize == MMU_PAGE_64K || psize == MMU_PAGE_2M  || psize == MMU_PAGE_1G);
-        val |= (NvU64)mmu_get_ap(psize) << PPC_BITLSHIFT(NPU_ATSD_REG_LAUNCH_INVAL_SIZE);
-    }
-
-    return val;
-}
-
-// Return the encoded size to use for an ATSD targeting the given range, in one
-// of the MMU_PAGE_* values defined in powerpc's asm/mmu.h. A return value of
-// MMU_PAGE_COUNT means the entire address space must be invalidated.
-//
-// start is an in/out parameter. On return start will be set to the aligned
-// starting address to use for the ATSD. end is inclusive.
-static int atsd_calc_size(NvU64 *start, NvU64 end)
-{
-    // ATSDs have high latency, so we prefer to over-invalidate rather than
-    // issue multiple precise invalidates. Supported sizes are only 64K, 2M, and
-    // 1G.
-
-    *start = UVM_ALIGN_DOWN(*start, SZ_64K);
-    end = UVM_ALIGN_DOWN(end, SZ_64K);
-    if (*start == end)
-        return MMU_PAGE_64K;
-
-    *start = UVM_ALIGN_DOWN(*start, SZ_2M);
-    end = UVM_ALIGN_DOWN(end, SZ_2M);
-    if (*start == end)
-        return MMU_PAGE_2M;
-
-    *start = UVM_ALIGN_DOWN(*start, SZ_1G);
-    end = UVM_ALIGN_DOWN(end, SZ_1G);
-    if (*start == end)
-        return MMU_PAGE_1G;
-
-    return MMU_PAGE_COUNT;
-}
-
-// Issue an ATSD to all NPUs and wait for completion
-static void atsd_launch_wait(uvm_va_space_t *va_space, uvm_atsd_regs_t *regs, NvU64 val)
-{
-    atsd_regs_write(va_space, regs, NPU_ATSD_REG_LAUNCH, val);
-    atsd_regs_wait(va_space, regs);
-}
-
-// Issue and wait for the required membars following an invalidate
-static void atsd_issue_membars(uvm_va_space_t *va_space, uvm_atsd_regs_t *regs)
-{
-    size_t i;
-    NvU32 num_membars = 0;
-
-    // These membars are issued using ATSDs which target a reserved PASID of 0.
-    // That PASID is valid on the GPU in order for the membar to be valid, but
-    // 0 will never be used by the kernel for an actual address space so the
-    // ATSD won't actually invalidate any entries.
-    NvU64 val = atsd_get_launch_val(0, MMU_PAGE_COUNT);
-
-    for_each_npu_index_in_va_space(i, va_space) {
-        uvm_ibm_npu_t *npu = &g_uvm_global.npus[i];
-        num_membars = max(num_membars, npu->atsd_regs.num_membars);
-    }
-
-    for (i = 0; i < num_membars; i++)
-        atsd_launch_wait(va_space, regs, val);
-}
-
-static void uvm_ats_ibm_invalidate_all(uvm_va_space_t *va_space, uvm_atsd_regs_t *regs)
-{
-    NvU64 val = atsd_get_launch_val(va_space_pasid(va_space), MMU_PAGE_COUNT);
-    atsd_launch_wait(va_space, regs, val);
-    atsd_issue_membars(va_space, regs);
-}
-
-static void uvm_ats_ibm_invalidate_range(uvm_va_space_t *va_space, uvm_atsd_regs_t *regs, NvU64 start, int psize)
-{
-    NvU64 val = atsd_get_launch_val(va_space_pasid(va_space), psize);
-
-    // Barriers are expensive, so write all address registers first then do a
-    // single barrier for all of them.
-    atsd_regs_write(va_space, regs, NPU_ATSD_REG_AVA, start);
-    eieio();
-    atsd_launch_wait(va_space, regs, val);
-    atsd_issue_membars(va_space, regs);
-}
-
-#endif // UVM_ATS_IBM_SUPPORTED_IN_DRIVER()
-
-void uvm_ats_ibm_invalidate(uvm_va_space_t *va_space, NvU64 start, NvU64 end)
-{
-#if UVM_ATS_IBM_SUPPORTED_IN_DRIVER()
-    unsigned long irq_flags;
-    uvm_atsd_regs_t regs;
-    NvU64 atsd_start = start;
-    int psize = atsd_calc_size(&atsd_start, end);
-    uvm_ibm_va_space_t *ibm_va_space = &va_space->ats.ibm;
-
-    BUILD_BUG_ON(order_base_2(UVM_MAX_ATSD_REGS) > 8*sizeof(regs.ids[0]));
-
-    // We must hold this lock in at least read mode when accessing NPU
-    // registers. See the comment in uvm_ats_ibm_unregister_gpu_va_space_driver.
-    uvm_read_lock_irqsave(&ibm_va_space->rwlock, irq_flags);
-
-    if (!bitmap_empty(ibm_va_space->npu_active_mask, NV_MAX_NPUS)) {
-        atsd_regs_acquire(va_space, &regs);
-
-        if (psize == MMU_PAGE_COUNT)
-            uvm_ats_ibm_invalidate_all(va_space, &regs);
-        else
-            uvm_ats_ibm_invalidate_range(va_space, &regs, atsd_start, psize);
-
-        atsd_regs_release(va_space, &regs);
-    }
-
-    uvm_read_unlock_irqrestore(&ibm_va_space->rwlock, irq_flags);
-#else
-    UVM_ASSERT_MSG(0, "This function should not be called on this kernel version\n");
-#endif // UVM_ATS_IBM_SUPPORTED_IN_DRIVER()
-}
-
-#endif // UVM_ATS_IBM_SUPPORTED
-#endif // UVM_IBM_NPU_SUPPORTED
--- a/kernel-open/nvidia-uvm/uvm_ats_ibm.h
+++ b/kernel-open/nvidia-uvm/uvm_ats_ibm.h
@@ -1,266 +0,0 @@
-/*******************************************************************************
-    Copyright (c) 2018-2019 NVIDIA Corporation
-
-    Permission is hereby granted, free of charge, to any person obtaining a copy
-    of this software and associated documentation files (the "Software"), to
-    deal in the Software without restriction, including without limitation the
-    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-    sell copies of the Software, and to permit persons to whom the Software is
-    furnished to do so, subject to the following conditions:
-
-        The above copyright notice and this permission notice shall be
-        included in all copies or substantial portions of the Software.
-
-    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-    DEALINGS IN THE SOFTWARE.
-
-*******************************************************************************/
-
-#ifndef __UVM_ATS_IBM_H__
-#define __UVM_ATS_IBM_H__
-
-#include "uvm_linux.h"
-#include "uvm_forward_decl.h"
-#include "uvm_hal_types.h"
-
-#if defined(NVCPU_PPC64LE) && defined(NV_PNV_PCI_GET_NPU_DEV_PRESENT)
-    #include <asm/mmu.h>
-    #if defined(NV_MAX_NPUS)
-        #define UVM_IBM_NPU_SUPPORTED() 1
-    #else
-        #define UVM_IBM_NPU_SUPPORTED() 0
-    #endif
-#else
-    #define UVM_IBM_NPU_SUPPORTED() 0
-#endif
-
-#if defined(NV_ASM_OPAL_API_H_PRESENT)
-    // For OPAL_NPU_INIT_CONTEXT
-    #include <asm/opal-api.h>
-#endif
-
-// Timeline of kernel changes:
-//
-// 0) Before 1ab66d1fbadad86b1f4a9c7857e193af0ee0022c
-//      - No NPU-ATS code existed, nor did the OPAL_NPU_INIT_CONTEXT firmware
-//        call.
-//      - NV_PNV_NPU2_INIT_CONTEXT_PRESENT                  Not defined
-//      - NV_PNV_NPU2_INIT_CONTEXT_CALLBACK_RETURNS_VOID    Not defined
-//      - OPAL_NPU_INIT_CONTEXT                             Not defined
-//      - ATS support type                                  None
-//
-// 1) NPU ATS code added: 1ab66d1fbadad86b1f4a9c7857e193af0ee0022c, v4.12
-//    (2017-04-03)
-//      - This commit added initial support for NPU ATS, including the necessary
-//        OPAL firmware calls. This support was developmental and required
-//        several bug fixes before it could be used in production.
-//      - NV_PNV_NPU2_INIT_CONTEXT_PRESENT                  Defined
-//      - NV_PNV_NPU2_INIT_CONTEXT_CALLBACK_RETURNS_VOID    Not defined
-//      - OPAL_NPU_INIT_CONTEXT                             Defined
-//      - ATS support type                                  None
-//
-// 2) NPU ATS code fixed: a1409adac748f0db655e096521bbe6904aadeb98, v4.17
-//    (2018-04-11)
-//      - This commit changed the function signature for pnv_npu2_init_context's
-//        callback parameter. Since all required bug fixes went in prior to this
-//        change, we can use the callback signature as a flag to indicate
-//        whether the PPC arch layer in the kernel supports ATS in production.
-//      - NV_PNV_NPU2_INIT_CONTEXT_PRESENT                  Defined
-//      - NV_PNV_NPU2_INIT_CONTEXT_CALLBACK_RETURNS_VOID    Defined
-//      - OPAL_NPU_INIT_CONTEXT                             Defined
-//      - ATS support type                                  Kernel
-//
-// 3) NPU ATS code removed: 7eb3cf761927b2687164e182efa675e6c09cfe44, v5.3
-//    (2019-06-25)
-//      - This commit removed NPU-ATS support from the PPC arch layer, so the
-//        driver needs to handle things instead. pnv_npu2_init_context is no
-//        longer present, so we use OPAL_NPU_INIT_CONTEXT to differentiate
-//        between this state and scenario #0.
-//      - NV_PNV_NPU2_INIT_CONTEXT_PRESENT                  Not defined
-//      - NV_PNV_NPU2_INIT_CONTEXT_CALLBACK_RETURNS_VOID    Not defined
-//      - OPAL_NPU_INIT_CONTEXT                             Defined
-//      - ATS support type                                  Driver
-//
-#if defined(NV_PNV_NPU2_INIT_CONTEXT_CALLBACK_RETURNS_VOID)
-    #define UVM_ATS_IBM_SUPPORTED_IN_KERNEL()   1
-    #define UVM_ATS_IBM_SUPPORTED_IN_DRIVER()   0
-#elif !defined(NV_PNV_NPU2_INIT_CONTEXT_PRESENT) && defined(OPAL_NPU_INIT_CONTEXT) && UVM_CAN_USE_MMU_NOTIFIERS()
-    #define UVM_ATS_IBM_SUPPORTED_IN_KERNEL()   0
-    #define UVM_ATS_IBM_SUPPORTED_IN_DRIVER()   1
-#else
-    #define UVM_ATS_IBM_SUPPORTED_IN_KERNEL()   0
-    #define UVM_ATS_IBM_SUPPORTED_IN_DRIVER()   0
-#endif
-
-#define UVM_ATS_IBM_SUPPORTED() (UVM_ATS_IBM_SUPPORTED_IN_KERNEL() || UVM_ATS_IBM_SUPPORTED_IN_DRIVER())
-
-// Maximum number of parallel ATSD register sets per NPU
-#define UVM_MAX_ATSD_REGS 16
-
-typedef struct
-{
-#if UVM_IBM_NPU_SUPPORTED()
-    // These are the active NPUs in this VA space, that is, all NPUs with
-    // GPUs that have GPU VA spaces registered in this VA space.
-    //
-    // If a bit is clear in npu_active_mask then the corresponding entry of
-    // npu_ref_counts is 0. If a bit is set then the corresponding entry of
-    // npu_ref_counts is greater than 0.
-    NvU32 npu_ref_counts[NV_MAX_NPUS];
-    DECLARE_BITMAP(npu_active_mask, NV_MAX_NPUS);
-#endif
-
-    // Lock protecting npu_ref_counts and npu_active_mask. Invalidations
-    // take this lock for read. GPU VA space register and unregister take
-    // this lock for write. Since all invalidations take the lock for read
-    // for the duration of the invalidate, taking the lock for write also
-    // flushes all invalidates.
-    //
-    // This is a spinlock because the invalidation code paths may be called
-    // with interrupts disabled, so those paths can't take the VA space
-    // lock. We could use a normal exclusive spinlock instead, but a reader/
-    // writer lock is preferred to allow concurrent invalidates in the same
-    // VA space.
-    uvm_rwlock_irqsave_t rwlock;
-} uvm_ibm_va_space_t;
-
-typedef struct
-{
-#if UVM_ATS_IBM_SUPPORTED_IN_KERNEL()
-    struct npu_context *npu_context;
-#endif
-
-    // Used on the teardown path to know what to clean up. npu_context acts
-    // as the equivalent flag for kernel-provided support.
-    bool did_ibm_driver_init;
-} uvm_ibm_gpu_va_space_t;
-
-struct uvm_ibm_npu_struct
-{
-    // Number of retained GPUs under this NPU. The other fields in this struct
-    // are only valid if this is non-zero.
-    unsigned int num_retained_gpus;
-
-    // PCI domain containing this NPU. This acts as a unique system-wide ID for
-    // this UVM NPU.
-    int pci_domain;
-
-    // The ATS-related fields are only valid when ATS support is enabled and
-    // UVM_ATS_IBM_SUPPORTED_IN_DRIVER() is 1.
-    struct
-    {
-        // Mapped addresses of the ATSD trigger registers. There may be more
-        // than one set of identical registers per NPU to enable concurrent
-        // invalidates.
-        //
-        // These will not be accessed unless there is a GPU VA space registered
-        // on a GPU under this NPU. They are protected by bit locks in the locks
-        // field.
-        __be64 __iomem *io_addrs[UVM_MAX_ATSD_REGS];
-
-        // Actual number of registers in the io_addrs array
-        size_t count;
-
-        // Bitmask for allocation and locking of the registers. Bit index n
-        // corresponds to io_addrs[n]. A set bit means that index is in use
-        // (locked).
-        DECLARE_BITMAP(locks, UVM_MAX_ATSD_REGS);
-
-        // Max value of any uvm_parent_gpu_t::num_hshub_tlb_invalidate_membars
-        // for all retained GPUs under this NPU.
-        NvU32 num_membars;
-    } atsd_regs;
-};
-
-#if UVM_IBM_NPU_SUPPORTED()
-    NV_STATUS uvm_ats_ibm_add_gpu(uvm_parent_gpu_t *parent_gpu);
-    void uvm_ats_ibm_remove_gpu(uvm_parent_gpu_t *parent_gpu);
-#else
-    static NV_STATUS uvm_ats_ibm_add_gpu(uvm_parent_gpu_t *parent_gpu)
-    {
-        return NV_OK;
-    }
-
-    static void uvm_ats_ibm_remove_gpu(uvm_parent_gpu_t *parent_gpu)
-    {
-
-    }
-#endif // UVM_IBM_NPU_SUPPORTED
-
-#if UVM_ATS_IBM_SUPPORTED()
-    // Initializes IBM specific GPU state.
-    //
-    // LOCKING: None
-    void uvm_ats_ibm_init_va_space(uvm_va_space_t *va_space);
-
-    // Enables ATS access for the gpu_va_space on the mm_struct associated with
-    // the VA space (va_space_mm).
-    //
-    // If UVM_ATS_IBM_SUPPORTED_IN_KERNEL() is 1, NV_ERR_NOT_SUPPORTED is
-    // returned if current->mm does not match va_space_mm.mm or if a GPU VA
-    // space within another VA space has already called this function on the
-    // same mm.
-    //
-    // If UVM_ATS_IBM_SUPPORTED_IN_DRIVER() is 1 there are no such restrictions.
-    //
-    // LOCKING: The VA space lock must be held in write mode.
-    //          current->mm->mmap_lock must be held in write mode iff
-    //          UVM_ATS_IBM_SUPPORTED_IN_KERNEL() is 1.
-    NV_STATUS uvm_ats_ibm_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space);
-
-    // Disables ATS access for the gpu_va_space. Prior to calling this function,
-    // the caller must guarantee that the GPU will no longer make any ATS
-    // accesses in this GPU VA space, and that no ATS fault handling for this
-    // GPU will be attempted.
-    //
-    // LOCKING: This function may block on mmap_lock and the VA space lock, so
-    //          neither must be held.
-    void uvm_ats_ibm_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space);
-
-    // Synchronously invalidate ATS translations cached by GPU TLBs. The
-    // invalidate applies to all GPUs with active GPU VA spaces in va_space, and
-    // covers all pages touching any part of the given range. end is inclusive.
-    //
-    // GMMU translations in the given range are not guaranteed to be
-    // invalidated.
-    //
-    // LOCKING: No locks are required, but this function may be called with
-    //          interrupts disabled.
-    void uvm_ats_ibm_invalidate(uvm_va_space_t *va_space, NvU64 start, NvU64 end);
-#else
-    static void uvm_ats_ibm_init_va_space(uvm_va_space_t *va_space)
-    {
-
-    }
-    static NV_STATUS uvm_ats_ibm_register_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space)
-    {
-        return NV_OK;
-    }
-
-    static void uvm_ats_ibm_unregister_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space)
-    {
-
-    }
-
-    static void uvm_ats_ibm_invalidate(uvm_va_space_t *va_space, NvU64 start, NvU64 end)
-    {
-
-    }
-#endif // UVM_ATS_IBM_SUPPORTED
-
-static NV_STATUS uvm_ats_ibm_bind_gpu(uvm_gpu_va_space_t *gpu_va_space)
-{
-    return NV_OK;
-}
-
-static void uvm_ats_ibm_unbind_gpu(uvm_gpu_va_space_t *gpu_va_space)
-{
-
-}
-
-#endif // __UVM_ATS_IBM_H__
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Maneet Singh	87c0b12473	580.82.09	2025-09-09 16:15:34 -07:00
Maneet Singh	6387af3092	580.82.07	2025-09-02 10:35:52 -07:00
Maneet Singh	288f16e614	580.76.05	2025-08-12 12:13:43 -07:00
Maneet Singh	307159f262	580.65.06	2025-08-04 11:15:02 -07:00
Bernhard Stoeckner	d890313300	575.64.05	2025-07-22 21:09:46 +02:00
Bernhard Stoeckner	1893c6c8fd	575.64.03	2025-07-01 19:29:04 +02:00
Maneet Singh	fade1f7b20	575.64	2025-06-16 19:28:19 -07:00
Maneet Singh	30e15d79de	575.57.08	2025-05-29 10:58:21 -07:00
Andy Ritger	e00332b05f	575.51.03	2025-05-01 22:14:31 -07:00
Bernhard Stoeckner	4159579888	575.51.02	2025-04-17 19:35:59 +02:00