mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-05-11 17:00:18 +00:00
refactor
This commit is contained in:
@@ -18,6 +18,8 @@ template <index_t GridSize,
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class InGlobalDesc,
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class WeiGlobalDesc,
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class OutGlobalDesc,
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class ConvStrides,
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class ConvDilations,
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index_t BPerBlock,
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index_t KPerBlock,
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index_t EPerBlock,
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@@ -64,10 +66,7 @@ struct GridwiseConvolutionImplicitGemm_v4r1_nchw_kcyx_nkhw
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constexpr auto I1 = Number<1>{};
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constexpr auto I2 = Number<2>{};
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constexpr auto I3 = Number<3>{};
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constexpr auto I4 = Number<4>{};
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constexpr auto I5 = Number<5>{};
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constexpr auto I6 = Number<6>{};
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constexpr auto I7 = Number<7>{};
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constexpr auto True = integral_constant<bool, true>{};
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@@ -75,10 +74,8 @@ struct GridwiseConvolutionImplicitGemm_v4r1_nchw_kcyx_nkhw
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constexpr auto wei_k_c_y_x_global_desc = WeiGlobalDesc{};
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constexpr auto out_n_k_h_w_global_desc = OutGlobalDesc{};
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constexpr index_t N = in_n_c_h_w_global_desc.GetLength(I0);
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constexpr index_t C = in_n_c_h_w_global_desc.GetLength(I1);
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constexpr index_t Hi = in_n_c_h_w_global_desc.GetLength(I2);
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constexpr index_t Wi = in_n_c_h_w_global_desc.GetLength(I3);
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constexpr index_t N = in_n_c_h_w_global_desc.GetLength(I0);
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constexpr index_t C = in_n_c_h_w_global_desc.GetLength(I1);
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constexpr index_t K = out_n_k_h_w_global_desc.GetLength(I1);
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constexpr index_t Ho = out_n_k_h_w_global_desc.GetLength(I2);
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@@ -87,6 +84,12 @@ struct GridwiseConvolutionImplicitGemm_v4r1_nchw_kcyx_nkhw
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constexpr index_t Y = wei_k_c_y_x_global_desc.GetLength(I2);
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constexpr index_t X = wei_k_c_y_x_global_desc.GetLength(I3);
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constexpr index_t ConvStrideH = ConvStrides{}[0];
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constexpr index_t ConvStrideW = ConvStrides{}[1];
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constexpr index_t ConvDilationH = ConvDilations{}[0];
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constexpr index_t ConvDilationW = ConvDilations{}[1];
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static_assert(N % (N1 * N2) == 0, "wrong! cannot divice N evenly among thread");
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constexpr index_t N0 = N / (N1 * N2);
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@@ -95,6 +98,14 @@ struct GridwiseConvolutionImplicitGemm_v4r1_nchw_kcyx_nkhw
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constexpr index_t E = C * Y * X;
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// sanity-check for vectorized memory load
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static_assert(ConvStrideW == 1 || InBlockCopySrcDataPerRead_B == 1,
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"wrong! global vector load of input tensor is wrong");
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static_assert((X == 1 || ConvDilationW % InBlockCopySrcDataPerRead_B == 0),
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"wrong! aligment requirement for vectorized global load of input tensor will "
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"be violated");
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// divide block work by [K, B]
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static_assert(K % KPerBlock == 0 && B % BPerBlock == 0 && E % EPerBlock == 0,
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"wrong! cannot divide work evenly among block");
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@@ -113,15 +124,17 @@ struct GridwiseConvolutionImplicitGemm_v4r1_nchw_kcyx_nkhw
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// input tensor
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// tensor descriptor in device memory [N0, N1, N2, Ho, Wo]
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constexpr auto in_n0_n1_n2_h_w_global_desc = in_n_c_h_w_global_desc.Slice(I2, Number<Ho>{})
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.Slice(I3, Number<Wo>{})
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.Fold(I0, Number<N1>{}, Number<N2>{})
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.Extract(Sequence<0, 1, 2, 4, 5>{});
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constexpr auto in_n0_n1_n2_h_w_global_desc =
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in_n_c_h_w_global_desc.StridedSlice(I2, Number<Ho>{}, Number<ConvStrideH>{})
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.StridedSlice(I3, Number<Wo>{}, Number<ConvStrideW>{})
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.Fold(I0, Number<N1>{}, Number<N2>{})
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.Extract(Sequence<0, 1, 2, 4, 5>{});
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// batch descritpor for device memory
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constexpr auto in_c_y_x_global_desc = in_n_c_h_w_global_desc.Slice(I2, Number<Y>{})
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.Slice(I3, Number<X>{})
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.Extract(Sequence<1, 2, 3>{});
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constexpr auto in_c_y_x_global_desc =
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in_n_c_h_w_global_desc.StridedSlice(I2, Number<Y>{}, Number<ConvDilationH>{})
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.StridedSlice(I3, Number<X>{}, Number<ConvDilationW>{})
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.Extract(Sequence<1, 2, 3>{});
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// merged tensor descriptor in device memory [E, N1, B, N2], src of blockwise copy
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constexpr auto in_e_n1_b_n2_global_merged_desc = make_ConstantMergedTensorDescriptor(
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@@ -131,17 +144,6 @@ struct GridwiseConvolutionImplicitGemm_v4r1_nchw_kcyx_nkhw
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Sequence<3, 6, 7>{},
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Sequence<5>{});
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#if 0
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if(get_block_1d_id() == 0 && get_thread_local_1d_id() == 0)
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{
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print_ConstantTensorDescriptor(in_n0_n1_n2_h_w_global_desc,
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"in_n0_n1_n2_h_w_global_desc: ");
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print_ConstantTensorDescriptor(in_c_y_x_global_desc, "in_c_y_x_global_desc: ");
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print_ConstantMergedTensorDescriptor(in_e_n1_b_n2_global_merged_desc,
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"in_e_n1_b_n2_global_merged_desc: ");
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}
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#endif
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// memory layout descriptor in LDS [E, N1, B, N2], dst of blockwise copy
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// be careful of LDS alignment
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constexpr auto in_e_n1_b_n2_block_desc = make_ConstantTensorDescriptor_aligned(
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@@ -206,13 +208,12 @@ struct GridwiseConvolutionImplicitGemm_v4r1_nchw_kcyx_nkhw
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// b_mtx[EPerBlocl, N1 * BPerBlock * N2] is in LDS
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// c_mtx[KPerBlock, N1 * BPerBlock * N2] is distributed among threads, and saved in
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// register
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constexpr auto a_e_k_block_mtx_desc = make_ConstantMatrixDescriptor(
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Number<EPerBlock>{}, Number<KPerBlock>{}, Number<wei_e_k_block_desc.GetStride(I0)>{});
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constexpr auto a_e_k_block_mtx_desc =
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make_ConstantMatrixDescriptor_from_ConstantTensorDescriptor(wei_e_k_block_desc);
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constexpr auto b_e_n1bn2_block_mtx_desc =
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make_ConstantMatrixDescriptor(Number<EPerBlock>{},
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Number<N1 * BPerBlock * N2>{},
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Number<in_e_n1_b_n2_block_desc.GetStride(I0)>{});
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make_ConstantMatrixDescriptor_from_ConstantTensorDescriptor(
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in_e_n1_b_n2_block_desc.Unfold(I1, I3));
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// sanity check
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static_assert(KPerBlock % (GemmMPerThreadSubC * GemmMLevel0Cluster * GemmMLevel1Cluster) ==
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@@ -242,15 +243,6 @@ struct GridwiseConvolutionImplicitGemm_v4r1_nchw_kcyx_nkhw
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GemmDataPerReadA,
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GemmDataPerReadB>{};
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// choose GEMM implementation here
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const auto run_blockwise_gemm = [&](auto... Xs) {
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#if 1
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return blockwise_gemm.Run(Xs...);
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#else
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return blockwise_gemm.Run_amd_asm(Xs...);
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#endif
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};
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// LDS allocation for input and weight: be careful of alignment
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constexpr index_t max_align = math::lcm(InBlockCopyDstDataPerWrite_N2,
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WeiBlockCopyDstDataPerWrite_K,
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@@ -281,7 +273,7 @@ struct GridwiseConvolutionImplicitGemm_v4r1_nchw_kcyx_nkhw
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__syncthreads();
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run_blockwise_gemm(p_wei_block, p_in_block, p_out_thread);
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blockwise_gemm.Run(p_wei_block, p_in_block, p_out_thread);
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__syncthreads();
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@@ -293,7 +285,6 @@ struct GridwiseConvolutionImplicitGemm_v4r1_nchw_kcyx_nkhw
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{
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constexpr index_t K2 = GemmMPerThreadSubC;
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constexpr index_t K1 = GemmMLevel0Cluster * GemmMLevel1Cluster;
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constexpr index_t K0 = K / (K1 * K2);
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// define tensor descriptor for threadwise copy
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// output memory layout descriptor in register
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@@ -59,7 +59,7 @@ void device_convolution_implicit_gemm_v4r1_nchw_kcyx_nkhw(InDesc,
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constexpr index_t B = (N * Ho * Wo) / (N1 * N2);
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#if 0
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#if 1
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// each thread hold 64 data
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constexpr index_t BlockSize = 256;
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@@ -94,7 +94,7 @@ void device_convolution_implicit_gemm_v4r1_nchw_kcyx_nkhw(InDesc,
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constexpr index_t WeiBlockCopySrcDataPerRead_E = 4;
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constexpr index_t WeiBlockCopyDstDataPerWrite_K = 1;
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#elif 1
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#elif 0
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// each thread hold 32 data
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constexpr index_t BlockSize = 256;
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