mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-07-17 17:19:12 +00:00
Added bwd_data cwave tile transfer support
This commit is contained in:
apoorva
@@ -35,8 +35,8 @@ namespace device {
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namespace {
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template <typename GridwiseGemm,
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typename AGridDesc_AK0_M_AK1,
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typename BGridDesc_BK0_N_BK1,
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typename AGridDesc_M_K,
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typename BGridDesc_N_K,
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typename DsGridDescriptor_MBlock_MPerBlock_NBlock_NPerBlock,
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typename EGridDesc_MBlock_MPerBlock_NBlock_NPerBlock,
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index_t MaxGroupedGemmGroupsNum,
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@@ -66,14 +66,24 @@ __launch_bounds__(CK_MAX_THREAD_PER_BLOCK, MinimumOccupancy)
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if constexpr(EGlobalMemoryDataOperation != InMemoryDataOperationEnum::AtomicAdd)
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{
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#endif
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__shared__ char p_shared[GridwiseGemm::template GetSharedMemoryNumberOfByte<
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typename GridwiseGemm::EpilogueCShuffle>()];
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auto epilogue_args = typename GridwiseGemm::EpilogueCShuffle{};
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using EpilogueType =
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typename std::conditional<GridwiseGemm::IsBWaveTransferApplicable &&
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GridwiseGemm::UseDirectStore,
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typename GridwiseGemm::EpilogueDirectStore,
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typename GridwiseGemm::EpilogueCShuffle>::type;
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constexpr index_t LDS_size =
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GridwiseGemm::template GetSharedMemoryNumberOfByte<EpilogueType>();
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__shared__ char p_shared[LDS_size];
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auto epilogue_args = EpilogueType{};
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const index_t block_args_id = __builtin_amdgcn_readfirstlane(blockIdx.x);
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index_t left = 0;
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index_t right = gemms_count;
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index_t group_id = index_t((left + right) / 2);
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while((!(block_args_id >= gemm_kernel_args[group_id].BlockStart_ &&
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block_args_id < gemm_kernel_args[group_id].BlockEnd_)) &&
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left <= right)
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@@ -90,13 +100,13 @@ __launch_bounds__(CK_MAX_THREAD_PER_BLOCK, MinimumOccupancy)
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}
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const auto num_k_per_block =
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gemm_kernel_args[group_id].a_grid_desc_ak0_m_ak1_.GetLength(Number<0>{}) / KBatch;
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gemm_kernel_args[group_id].a_grid_desc_m_k_.GetLength(Number<0>{}) / KBatch;
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if constexpr(HasMainKBlockLoopInAllGemm || NoMainKBlockLoopInAllGemm)
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{
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GridwiseGemm::template Run<AGridDesc_AK0_M_AK1,
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BGridDesc_BK0_N_BK1,
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GridwiseGemm::template Run<decltype(gemm_kernel_args[group_id].a_grid_desc_m_k_),
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decltype(gemm_kernel_args[group_id].b_grid_desc_n_k_),
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DsGridDescriptor_MBlock_MPerBlock_NBlock_NPerBlock,
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EGridDesc_MBlock_MPerBlock_NBlock_NPerBlock,
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decltype(gemm_kernel_args[group_id].block_2_ctile_map_),
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@@ -107,8 +117,8 @@ __launch_bounds__(CK_MAX_THREAD_PER_BLOCK, MinimumOccupancy)
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CTranspose,
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TailNum>(
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p_shared,
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gemm_kernel_args[group_id].a_grid_desc_ak0_m_ak1_,
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gemm_kernel_args[group_id].b_grid_desc_bk0_n_bk1_,
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gemm_kernel_args[group_id].a_grid_desc_m_k_,
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gemm_kernel_args[group_id].b_grid_desc_n_k_,
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gemm_kernel_args[group_id].ds_grid_desc_mblock_mperblock_nblock_nperblock_,
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gemm_kernel_args[group_id].e_grid_desc_mblock_mperblock_nblock_nperblock_,
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gemm_kernel_args[group_id].block_2_ctile_map_,
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@@ -122,8 +132,8 @@ __launch_bounds__(CK_MAX_THREAD_PER_BLOCK, MinimumOccupancy)
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{
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if(gemm_kernel_args[group_id].HasMainKBlockLoop_)
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{
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GridwiseGemm::template Run<AGridDesc_AK0_M_AK1,
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BGridDesc_BK0_N_BK1,
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GridwiseGemm::template Run<decltype(gemm_kernel_args[group_id].a_grid_desc_m_k_),
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decltype(gemm_kernel_args[group_id].b_grid_desc_n_k_),
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DsGridDescriptor_MBlock_MPerBlock_NBlock_NPerBlock,
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EGridDesc_MBlock_MPerBlock_NBlock_NPerBlock,
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decltype(gemm_kernel_args[group_id].block_2_ctile_map_),
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@@ -134,8 +144,8 @@ __launch_bounds__(CK_MAX_THREAD_PER_BLOCK, MinimumOccupancy)
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CTranspose,
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TailNum>(
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p_shared,
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gemm_kernel_args[group_id].a_grid_desc_ak0_m_ak1_,
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gemm_kernel_args[group_id].b_grid_desc_bk0_n_bk1_,
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gemm_kernel_args[group_id].a_grid_desc_m_k_,
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gemm_kernel_args[group_id].b_grid_desc_n_k_,
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gemm_kernel_args[group_id].ds_grid_desc_mblock_mperblock_nblock_nperblock_,
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gemm_kernel_args[group_id].e_grid_desc_mblock_mperblock_nblock_nperblock_,
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gemm_kernel_args[group_id].block_2_ctile_map_,
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@@ -147,8 +157,8 @@ __launch_bounds__(CK_MAX_THREAD_PER_BLOCK, MinimumOccupancy)
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}
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else
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{
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GridwiseGemm::template Run<AGridDesc_AK0_M_AK1,
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BGridDesc_BK0_N_BK1,
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GridwiseGemm::template Run<decltype(gemm_kernel_args[group_id].a_grid_desc_m_k_),
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decltype(gemm_kernel_args[group_id].b_grid_desc_n_k_),
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DsGridDescriptor_MBlock_MPerBlock_NBlock_NPerBlock,
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EGridDesc_MBlock_MPerBlock_NBlock_NPerBlock,
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decltype(gemm_kernel_args[group_id].block_2_ctile_map_),
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@@ -159,8 +169,8 @@ __launch_bounds__(CK_MAX_THREAD_PER_BLOCK, MinimumOccupancy)
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CTranspose,
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TailNum>(
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p_shared,
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gemm_kernel_args[group_id].a_grid_desc_ak0_m_ak1_,
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gemm_kernel_args[group_id].b_grid_desc_bk0_n_bk1_,
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gemm_kernel_args[group_id].a_grid_desc_m_k_,
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gemm_kernel_args[group_id].b_grid_desc_n_k_,
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gemm_kernel_args[group_id].ds_grid_desc_mblock_mperblock_nblock_nperblock_,
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gemm_kernel_args[group_id].e_grid_desc_mblock_mperblock_nblock_nperblock_,
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gemm_kernel_args[group_id].block_2_ctile_map_,
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@@ -242,6 +252,7 @@ template <index_t NDimSpatial,
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typename CShuffleBlockTransferScalarPerVector,
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BlockGemmPipelineScheduler BlkGemmPipeSched = BlockGemmPipelineScheduler::Intrawave,
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BlockGemmPipelineVersion BlkGemmPipelineVer = BlockGemmPipelineVersion::v1,
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bool UseThreadTileTransfer = true,
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typename AComputeType = ADataType,
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typename BComputeType = AComputeType,
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index_t MaxTransposeTransferInScalarPerVector = 1,
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@@ -266,6 +277,14 @@ struct DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3
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static_assert(NDimSpatial == 2 || NDimSpatial == 3,
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"wrong! only implemented for 2D and 3D now");
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#ifdef USE_WAVE_TRANSFER
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static_assert(UseThreadTileTransfer == false &&
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(ConvBackwardDataSpecialization ==
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ConvolutionBackwardDataSpecialization::Filter1x1Stride1Pad0),
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"Only Filter1x1Stride1Pad0is supported for wavetile transfer");
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#endif
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// MaxGroupedGemmGroupsNum is used to specify number of gemm args in compile time. With this
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// implementation we can avoid copy data to workspace before kernel launch since number of
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// groups is runtime parameter. If number of groups is larger than MaxGroupedGemmGroupsNum then
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@@ -355,9 +374,9 @@ struct DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3
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static auto
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GetDummyABDsEGridDescriptor(const ConvToGemmBwdDataTransform& conv_to_gemm_transform)
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{
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const auto a_grid_desc_ak0_m_ak1 = conv_to_gemm_transform.MakeADescriptor_AK0_M_AK1();
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const auto a_grid_desc_m_k = conv_to_gemm_transform.MakeADescriptor_AK0_M_AK1();
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const auto b_grid_desc_bk0_n_bk1 = conv_to_gemm_transform.MakeBDescriptor_BK0_N_BK1();
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const auto b_grid_desc_n_k = conv_to_gemm_transform.MakeBDescriptor_BK0_N_BK1();
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const auto ds_grid_desc_m_n = generate_tuple(
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[&](auto i) {
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@@ -390,13 +409,11 @@ struct DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3
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if constexpr(CTranspose)
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{
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return make_tuple(
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b_grid_desc_bk0_n_bk1, a_grid_desc_ak0_m_ak1, ds_grid_desc_m_n, e_grid_desc_m_n);
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return make_tuple(b_grid_desc_n_k, a_grid_desc_m_k, ds_grid_desc_m_n, e_grid_desc_m_n);
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}
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else
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{
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return make_tuple(
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a_grid_desc_ak0_m_ak1, b_grid_desc_bk0_n_bk1, ds_grid_desc_m_n, e_grid_desc_m_n);
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return make_tuple(a_grid_desc_m_k, b_grid_desc_n_k, ds_grid_desc_m_n, e_grid_desc_m_n);
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}
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}
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@@ -450,10 +467,10 @@ struct DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3
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BlkGemmPipelineVer,
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AComputeType,
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BComputeType,
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false, // PermuteA
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false, // PermuteB
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false, // IsBPreShuffled
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true>; // ForceThreadTileTransfer
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false,
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false,
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false,
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UseThreadTileTransfer>;
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#define GridwiseGemmCTransposeTemplateParameters \
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ALayout, BLayout, DsLayout, ELayout, Tuple<ADataType>, Tuple<BDataType>, AccDataType, \
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@@ -494,13 +511,13 @@ struct DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3
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constexpr static ConvToGemmBwdDataTransform dummy_conv_to_gemm_transform;
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using ABDsEGridDesc = decltype(GetDummyABDsEGridDescriptor(dummy_conv_to_gemm_transform));
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using AGridDesc_AK0_M_AK1 = remove_cvref_t<tuple_element_t<0, ABDsEGridDesc>>;
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using BGridDesc_BK0_N_BK1 = remove_cvref_t<tuple_element_t<1, ABDsEGridDesc>>;
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using DsGridDesc_M_N = remove_cvref_t<tuple_element_t<2, ABDsEGridDesc>>;
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using EGridDesc_M_N = remove_cvref_t<tuple_element_t<3, ABDsEGridDesc>>;
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using AGridDesc_M_K_ = remove_cvref_t<tuple_element_t<0, ABDsEGridDesc>>;
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using BGridDesc_N_K_ = remove_cvref_t<tuple_element_t<1, ABDsEGridDesc>>;
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using DsGridDesc_M_N = remove_cvref_t<tuple_element_t<2, ABDsEGridDesc>>;
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using EGridDesc_M_N = remove_cvref_t<tuple_element_t<3, ABDsEGridDesc>>;
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using AGridDesc_M_K = decltype(transform_k0_m_k1_to_m_k(AGridDesc_AK0_M_AK1{}));
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using BGridDesc_N_K = decltype(transform_k0_m_k1_to_m_k(BGridDesc_BK0_N_BK1{}));
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using AGridDesc_M_K = decltype(transform_k0_m_k1_to_m_k(AGridDesc_M_K_{}));
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using BGridDesc_N_K = decltype(transform_k0_m_k1_to_m_k(BGridDesc_N_K_{}));
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// Note: here we can call gridwise functions with dummy arguments,
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// just to create the alias
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@@ -517,8 +534,8 @@ struct DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3
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struct GemmArgs
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{
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GemmArgs() = default;
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GemmArgs(AGridDesc_AK0_M_AK1 a_grid_desc_ak0_m_ak1,
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BGridDesc_BK0_N_BK1 b_grid_desc_bk0_n_bk1,
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GemmArgs(AGridDesc_M_K_ a_grid_desc_m_k,
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BGridDesc_N_K_ b_grid_desc_n_k,
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DsGridDesc_MBlock_MPerBlock_NBlock_NPerBlock
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ds_grid_desc_mblock_mperblock_nblock_nperblock,
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EGridDesc_MBlock_MPerBlock_NBlock_NPerBlock
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@@ -527,8 +544,8 @@ struct DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3
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index_t BlockStart,
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index_t BlockEnd,
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bool HasMainKBlockLoop)
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: a_grid_desc_ak0_m_ak1_(a_grid_desc_ak0_m_ak1),
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b_grid_desc_bk0_n_bk1_(b_grid_desc_bk0_n_bk1),
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: a_grid_desc_m_k_(a_grid_desc_m_k),
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b_grid_desc_n_k_(b_grid_desc_n_k),
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ds_grid_desc_mblock_mperblock_nblock_nperblock_(
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ds_grid_desc_mblock_mperblock_nblock_nperblock),
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@@ -543,8 +560,8 @@ struct DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3
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{
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}
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// tensor descriptors for block/thread-wise copy
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AGridDesc_AK0_M_AK1 a_grid_desc_ak0_m_ak1_;
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BGridDesc_BK0_N_BK1 b_grid_desc_bk0_n_bk1_;
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AGridDesc_M_K_ a_grid_desc_m_k_;
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BGridDesc_N_K_ b_grid_desc_n_k_;
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DsGridDesc_MBlock_MPerBlock_NBlock_NPerBlock
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ds_grid_desc_mblock_mperblock_nblock_nperblock_;
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EGridDesc_MBlock_MPerBlock_NBlock_NPerBlock e_grid_desc_mblock_mperblock_nblock_nperblock_;
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@@ -1055,10 +1072,10 @@ struct DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3
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{
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for(std::size_t i = 0; i < a_grid_desc_m_k_container_.size(); i++)
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{
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std::cout << "a_grid_desc_m_ak_container_" << a_grid_desc_m_k_container_[i]
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std::cout << "a_grid_desc_m_k_container_" << a_grid_desc_m_k_container_[i]
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<< std::endl;
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std::cout << "b_grid_desc_n_bk_container_" << b_grid_desc_n_k_container_[i]
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std::cout << "b_grid_desc_n_k_container_" << b_grid_desc_n_k_container_[i]
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<< std::endl;
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static_for<0, NumDTensor, 1>{}([&](auto j) {
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@@ -1086,8 +1103,8 @@ struct DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3
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std::vector<EGridDesc_M_N> e_grid_desc_m_n_container_;
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// tensor descriptor for block-wise copy
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std::vector<AGridDesc_AK0_M_AK1> a_grid_desc_ak0_m_ak1_container_;
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std::vector<BGridDesc_BK0_N_BK1> b_grid_desc_bk0_n_bk1_container_;
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// std::vector<AGridDesc_M_K> a_grid_desc_m_k_container_;
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// std::vector<BGridDesc_N_K> b_grid_desc_n_k_container_;
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std::vector<DsGridDesc_MBlock_MPerBlock_NBlock_NPerBlock>
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ds_grid_desc_mblock_mperblock_nblock_nperblock_container_;
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std::vector<EGridDesc_MBlock_MPerBlock_NBlock_NPerBlock>
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@@ -1233,8 +1250,8 @@ struct DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3
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constexpr bool no_main_loop = no_main_k_block_loop.value;
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const auto kernel = kernel_grouped_conv_bwd_data_wmma_cshuffle_v3<
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GridwiseGemmCTranspose,
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DeviceOp::AGridDesc_AK0_M_AK1,
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DeviceOp::BGridDesc_BK0_N_BK1,
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DeviceOp::AGridDesc_M_K,
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DeviceOp::BGridDesc_N_K,
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DeviceOp::DsGridDesc_MBlock_MPerBlock_NBlock_NPerBlock,
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DeviceOp::EGridDesc_MBlock_MPerBlock_NBlock_NPerBlock,
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MaxGroupedGemmGroupsNum,
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@@ -1785,12 +1802,12 @@ struct DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3
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p_ds_grid_dummy[i] = nullptr;
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StrideDs_dummy[i] = I0;
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});
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for(std::size_t i = 0; i < arg.a_grid_desc_ak0_m_ak1_container_.size(); i++)
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for(std::size_t i = 0; i < arg.a_grid_desc_m_k_container_.size(); i++)
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{
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const index_t GemmM = arg.a_grid_desc_ak0_m_ak1_container_[i].GetLength(I1);
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const index_t GemmN = arg.b_grid_desc_bk0_n_bk1_container_[i].GetLength(I1);
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const index_t GemmK = arg.a_grid_desc_ak0_m_ak1_container_[i].GetLength(I0) *
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arg.a_grid_desc_ak0_m_ak1_container_[i].GetLength(I2);
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const index_t GemmM = arg.a_grid_desc_m_k_container_[i].GetLength(I0);
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const index_t GemmN = arg.b_grid_desc_n_k_container_[i].GetLength(I0);
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const index_t GemmK = arg.a_grid_desc_m_k_container_[i].GetLength(I1);
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// Create gemm arguments with dummy values to check for validity
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typename GridwiseGemmCTranspose::Argument gemm_arg{
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std::array<const void*, 1>{nullptr}, // p_as_grid
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@@ -0,0 +1,83 @@
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// Copyright (c) Advanced Micro Devices, Inc., or its affiliates.
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// SPDX-License-Identifier: MIT
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#pragma once
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#include "ck/ck.hpp"
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#include "ck/tensor_operation/gpu/device/tensor_layout.hpp"
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#include "ck/tensor_operation/gpu/device/impl/device_grouped_conv_bwd_data_multiple_d_wmma_cshuffle_v3.hpp"
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#include "ck/tensor_operation/gpu/element/element_wise_operation.hpp"
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#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
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namespace ck {
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namespace tensor_operation {
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namespace device {
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namespace instance {
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#define USE_WAVE_TRANSFER
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using BF16 = ck::bhalf_t;
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using F16 = ck::half_t;
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using F32 = float;
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using BF8 = ck::bf8_t;
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using F8 = ck::f8_t;
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using Empty_Tuple = ck::Tuple<>;
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template <ck::index_t... Is>
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using S = ck::Sequence<Is...>;
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using namespace ck::tensor_layout::convolution;
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using PassThrough = ck::tensor_operation::element_wise::PassThrough;
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static constexpr auto ConvBwdDataDefault = ConvolutionBackwardDataSpecialization::Default;
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static constexpr auto ConvBwdDataFilter1x1Stride1Pad0 =
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ConvolutionBackwardDataSpecialization::Filter1x1Stride1Pad0;
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template <index_t NDimSpatial,
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typename ALayout,
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typename BLayout,
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typename DsLayout,
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typename ELayout,
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ConvolutionBackwardDataSpecialization ConvSpec>
|
||||
using device_grouped_conv_bwd_data_wmma_cshufflev3_bf16_wave_transfer_instances = std::tuple<
|
||||
// clang-format off
|
||||
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MWmma| NWmma| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer| Pipeline scheduler | Pipeline version |
|
||||
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Size| Block| Block| Block| | | WMMA| WMMA| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MWmmaPerWave| NWmmaPerWave| _MBlock_MWaveMPerWmma| ScalarPerVector| | |
|
||||
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerWmma| _NWaveNPerWmma| | |
|
||||
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
|
||||
// generic instance
|
||||
DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3<NDimSpatial, ALayout, BLayout, DsLayout, ELayout, BF16, BF16, F32, BF16, Empty_Tuple, BF16, PassThrough, PassThrough, PassThrough, ConvSpec, true, true, 64, 64, 64, 32, 8, 8, 16, 16, 4, 2, S<4, 16, 1>, S<1, 0, 2>, S<1, 0, 2>, 2, 1, 8, 1, S<4, 8, 1>, S<0, 2, 1>, S<0, 2, 1>, 1, 1, 8, 1, 1, 1, S<1, 16, 1, 4>, S<1,1,1>,BlockGemmPipelineScheduler::Intrawave, BlockGemmPipelineVersion::v1, false>,
|
||||
|
||||
DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3<NDimSpatial, ALayout, BLayout, DsLayout, ELayout, BF16, BF16, F32, BF16, Empty_Tuple, BF16, PassThrough, PassThrough, PassThrough, ConvSpec, true, true, 128, 128, 128, 32, 8, 8, 16, 16, 8, 2, S<4, 32, 1>, S<1, 0, 2>, S<1, 0, 2>, 2, 8, 8, 1, S<4, 32, 1>, S<0, 2, 1>, S<0, 2, 1>, 1, 4, 8, 1, 1, 1, S<1, 16, 1, 8>, S<8,8,8>,BlockGemmPipelineScheduler::Intrawave, BlockGemmPipelineVersion::v1, false>,
|
||||
DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3<NDimSpatial, ALayout, BLayout, DsLayout, ELayout, BF16, BF16, F32, BF16, Empty_Tuple, BF16, PassThrough, PassThrough, PassThrough, ConvSpec, true, true, 64, 64, 32, 32, 8, 8, 16, 16, 4, 1, S<4, 16, 1>, S<1, 0, 2>, S<1, 0, 2>, 2, 8, 8, 1, S<4, 16, 1>, S<0, 2, 1>, S<0, 2, 1>, 1, 1, 8, 1, 1, 1, S<1, 16, 1, 4>, S<8,8,8>,BlockGemmPipelineScheduler::Intrawave, BlockGemmPipelineVersion::v1, false>
|
||||
// clang-format on
|
||||
>;
|
||||
|
||||
template <index_t NDimSpatial,
|
||||
typename ALayout,
|
||||
typename BLayout,
|
||||
typename DsLayout,
|
||||
typename ELayout,
|
||||
ConvolutionBackwardDataSpecialization ConvSpec>
|
||||
using device_grouped_conv_bwd_data_wmma_cshufflev3_f16_wave_transfer_instances = std::tuple<
|
||||
// clang-format off
|
||||
//########################################| NumDim| A| B| Ds| E| AData| BData| AccData| CShuffle| Ds| EData| A| B| CDE| ConvForward| GEMM| Block| MPer| NPer| KPer| AK1| BK1| MPer| NPer| MWmma| NWmma| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockTransfer| ABlockLds| BBlockTransfer| BBlockTransfer| BBlockTransfer| BlockTransfer| BBlockTransfer| BBlockTransfer| BBlockLds| CShuffle| CShuffle| CBlockTransferClusterLengths| CBlockTransfer| Pipeline scheduler | Pipeline version |
|
||||
//########################################| Spatial| Layout| Layout| Layout| Layout| Type| Type| Type| DataType| DataType| Type| Elementwise| Elementwise| Elementwise| Specialization| Specialization| Size| Block| Block| Block| | | WMMA| WMMA| Per| Per| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraM| ThreadCluster| ThreadCluster| SrcAccessOrder| SrcVectorDim| SrcScalar| DstScalar| AddExtraN| MWmmaPerWave| NWmmaPerWave| _MBlock_MWaveMPerWmma| ScalarPerVector| | |
|
||||
//########################################| | | | | | | | | | | | Operation| Operation| Operation| | | | | | | | | | | Wave| Wave| Lengths_K0_M_K1| ArrangeOrder| | | PerVector| PerVector_K1| | Lengths_K0_N_K1| ArrangeOrder| | | PerVector| PerVector_K1| | PerShuffle| PerShuffle| _NBlock_NWaveNPerWmma| _NWaveNPerWmma| | |
|
||||
//########################################| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
|
||||
|
||||
// generic instance
|
||||
DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3<NDimSpatial, ALayout, BLayout, DsLayout, ELayout, F16, F16, F32, F16, Empty_Tuple, F16, PassThrough, PassThrough, PassThrough, ConvSpec, true, true, 64, 64, 64, 32, 8, 8, 16, 16, 4, 2, S<4, 16, 1>, S<1, 0, 2>, S<1, 0, 2>, 2, 1, 8, 1, S<4, 8, 1>, S<0, 2, 1>, S<0, 2, 1>, 1, 1, 8, 1, 1, 1, S<1, 16, 1, 4>, S<1,1,1>,BlockGemmPipelineScheduler::Intrawave, BlockGemmPipelineVersion::v1, false>,
|
||||
|
||||
DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3<NDimSpatial, ALayout, BLayout, DsLayout, ELayout, F16, F16, F32, F16, Empty_Tuple, F16, PassThrough, PassThrough, PassThrough, ConvSpec, true, true, 64, 64, 32, 64, 8, 8, 16, 16, 4, 1, S<8, 8, 1>, S<1, 0, 2>, S<1, 0, 2>, 2, 8, 8, 1, S<8, 8, 1>, S<0, 2, 1>, S<0, 2, 1>, 1, 4, 8, 1, 1, 1, S<1, 16, 1, 4>, S<8,8,8>,BlockGemmPipelineScheduler::Intrawave, BlockGemmPipelineVersion::v1, false>,
|
||||
DeviceGroupedConvBwdDataMultipleD_Wmma_CShuffleV3<NDimSpatial, ALayout, BLayout, DsLayout, ELayout, F16, F16, F32, F16, Empty_Tuple, F16, PassThrough, PassThrough, PassThrough, ConvSpec, true, true, 64, 64, 64, 32, 8, 8, 16, 16, 4, 2, S<4, 16, 1>, S<1, 0, 2>, S<1, 0, 2>, 2, 4, 8, 1, S<4, 16, 1>, S<0, 2, 1>, S<0, 2, 1>, 1, 4, 8, 1, 1, 1, S<1, 16, 1, 4>, S<8,8,8>,BlockGemmPipelineScheduler::Intrawave, BlockGemmPipelineVersion::v1, false>
|
||||
|
||||
// clang-format on
|
||||
>;
|
||||
|
||||
} // namespace instance
|
||||
} // namespace device
|
||||
} // namespace tensor_operation
|
||||
} // namespace ck
|
||||
@@ -450,6 +450,8 @@ struct DeviceOperationInstanceFactory<
|
||||
op_ptrs);
|
||||
add_device_grouped_conv2d_bwd_data_wmma_nhwgk_gkyxc_nhwgc_f16_1x1s1p0_instances(
|
||||
op_ptrs);
|
||||
add_device_grouped_conv2d_bwd_data_wmma_v3_wave_transfer_nhwgk_gkyxc_nhwgc_f16_instances(
|
||||
op_ptrs);
|
||||
}
|
||||
#endif
|
||||
#ifdef CK_ENABLE_BF16
|
||||
@@ -461,6 +463,9 @@ struct DeviceOperationInstanceFactory<
|
||||
op_ptrs);
|
||||
add_device_grouped_conv2d_bwd_data_wmma_v3_nhwgk_gkyxc_nhwgc_bf16_16_16_instances(
|
||||
op_ptrs);
|
||||
|
||||
add_device_grouped_conv2d_bwd_data_wmma_v3_wave_transfer_nhwgk_gkyxc_nhwgc_bf16_instances(
|
||||
op_ptrs);
|
||||
}
|
||||
#endif
|
||||
#ifdef CK_ENABLE_INT8
|
||||
@@ -520,6 +525,8 @@ struct DeviceOperationInstanceFactory<
|
||||
op_ptrs);
|
||||
add_device_grouped_conv3d_bwd_data_wmma_v3_ndhwgk_gkzyxc_ndhwgc_f16_16_16_instances(
|
||||
op_ptrs);
|
||||
add_device_grouped_conv3d_bwd_data_wmma_v3_wave_transfer_ndhwgk_gkzyxc_ndhwgc_f16_instances(
|
||||
op_ptrs);
|
||||
}
|
||||
#endif
|
||||
#ifdef CK_ENABLE_BF16
|
||||
@@ -531,6 +538,8 @@ struct DeviceOperationInstanceFactory<
|
||||
op_ptrs);
|
||||
add_device_grouped_conv3d_bwd_data_wmma_v3_ndhwgk_gkzyxc_ndhwgc_bf16_16_16_instances(
|
||||
op_ptrs);
|
||||
add_device_grouped_conv3d_bwd_data_wmma_v3_wave_transfer_ndhwgk_gkzyxc_ndhwgc_bf16_instances(
|
||||
op_ptrs);
|
||||
}
|
||||
#endif
|
||||
#ifdef CK_ENABLE_INT8
|
||||
|
||||
@@ -80,6 +80,20 @@ void add_device_grouped_conv2d_bwd_data_wmma_nhwgk_gkyxc_nhwgc_f16_instances(
|
||||
PassThrough,
|
||||
PassThrough>>>& instances);
|
||||
|
||||
void add_device_grouped_conv2d_bwd_data_wmma_v3_wave_transfer_nhwgk_gkyxc_nhwgc_f16_instances(
|
||||
std::vector<std::unique_ptr<DeviceGroupedConvBwdDataMultipleD<2,
|
||||
NHWGK,
|
||||
GKYXC,
|
||||
Empty_Tuple,
|
||||
NHWGC,
|
||||
F16,
|
||||
F16,
|
||||
Empty_Tuple,
|
||||
F16,
|
||||
PassThrough,
|
||||
PassThrough,
|
||||
PassThrough>>>& instances);
|
||||
|
||||
void add_device_grouped_conv2d_bwd_data_wmma_nhwgk_gkyxc_nhwgc_f16_1x1s1p0_instances(
|
||||
std::vector<std::unique_ptr<DeviceGroupedConvBwdDataMultipleD<2,
|
||||
NHWGK,
|
||||
@@ -294,6 +308,20 @@ void add_device_grouped_conv2d_bwd_data_wmma_v3_nhwgk_gkyxc_nhwgc_bf16_16_16_ins
|
||||
PassThrough,
|
||||
PassThrough>>>& instances);
|
||||
|
||||
void add_device_grouped_conv2d_bwd_data_wmma_v3_wave_transfer_nhwgk_gkyxc_nhwgc_bf16_instances(
|
||||
std::vector<std::unique_ptr<DeviceGroupedConvBwdDataMultipleD<2,
|
||||
NHWGK,
|
||||
GKYXC,
|
||||
Empty_Tuple,
|
||||
NHWGC,
|
||||
BF16,
|
||||
BF16,
|
||||
Empty_Tuple,
|
||||
BF16,
|
||||
PassThrough,
|
||||
PassThrough,
|
||||
PassThrough>>>& instances);
|
||||
|
||||
#endif
|
||||
|
||||
// conv3dbwdData
|
||||
@@ -326,6 +354,20 @@ void add_device_grouped_conv3d_bwd_data_wmma_v3_ndhwgk_gkzyxc_ndhwgc_bf16_16_16_
|
||||
PassThrough,
|
||||
PassThrough,
|
||||
PassThrough>>>& instances);
|
||||
|
||||
void add_device_grouped_conv3d_bwd_data_wmma_v3_wave_transfer_ndhwgk_gkzyxc_ndhwgc_bf16_instances(
|
||||
std::vector<std::unique_ptr<DeviceGroupedConvBwdDataMultipleD<3,
|
||||
NDHWGK,
|
||||
GKZYXC,
|
||||
Empty_Tuple,
|
||||
NDHWGC,
|
||||
BF16,
|
||||
BF16,
|
||||
Empty_Tuple,
|
||||
BF16,
|
||||
PassThrough,
|
||||
PassThrough,
|
||||
PassThrough>>>& instances);
|
||||
#endif
|
||||
#ifdef CK_ENABLE_FP16
|
||||
void add_device_grouped_conv3d_bwd_data_wmma_v3_ndhwgk_gkzyxc_ndhwgc_f16_instances(
|
||||
@@ -355,6 +397,20 @@ void add_device_grouped_conv3d_bwd_data_wmma_v3_ndhwgk_gkzyxc_ndhwgc_f16_16_16_i
|
||||
PassThrough,
|
||||
PassThrough,
|
||||
PassThrough>>>& instances);
|
||||
|
||||
void add_device_grouped_conv3d_bwd_data_wmma_v3_wave_transfer_ndhwgk_gkzyxc_ndhwgc_f16_instances(
|
||||
std::vector<std::unique_ptr<DeviceGroupedConvBwdDataMultipleD<3,
|
||||
NDHWGK,
|
||||
GKZYXC,
|
||||
Empty_Tuple,
|
||||
NDHWGC,
|
||||
F16,
|
||||
F16,
|
||||
Empty_Tuple,
|
||||
F16,
|
||||
PassThrough,
|
||||
PassThrough,
|
||||
PassThrough>>>& instances);
|
||||
#endif
|
||||
|
||||
} // namespace instance
|
||||
|
||||
@@ -49,5 +49,8 @@ add_instance_library(
|
||||
wmma/device_grouped_conv2d_bwd_data_wmma_v3_nhwgc_gkyxc_nhwgk_bf16_instance.cpp
|
||||
wmma/device_grouped_conv2d_bwd_data_wmma_v3_nhwgc_gkyxc_nhwgk_bf16_16_16_instance.cpp
|
||||
|
||||
|
||||
|
||||
|
||||
wmma/device_grouped_conv2d_bwd_data_wmma_v3_wave_transfer_nhwgc_gkyxc_nhwgk_bf16_instance.cpp
|
||||
wmma/device_grouped_conv2d_bwd_data_wmma_v3_wave_transfer_nhwgc_gkyxc_nhwgk_f16_instance.cpp
|
||||
)
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
// Copyright (c) Advanced Micro Devices, Inc., or its affiliates.
|
||||
// SPDX-License-Identifier: MIT
|
||||
|
||||
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
|
||||
#include "ck/library/tensor_operation_instance/gpu/grouped_conv_bwd_data/device_grouped_conv_bwd_data_wmma_v3_wave_tranfer_instances.hpp"
|
||||
|
||||
namespace ck {
|
||||
namespace tensor_operation {
|
||||
namespace device {
|
||||
namespace instance {
|
||||
|
||||
void add_device_grouped_conv2d_bwd_data_wmma_v3_wave_transfer_nhwgk_gkyxc_nhwgc_bf16_instances(
|
||||
std::vector<std::unique_ptr<DeviceGroupedConvBwdDataMultipleD<2,
|
||||
NHWGK,
|
||||
GKYXC,
|
||||
Empty_Tuple,
|
||||
NHWGC,
|
||||
BF16,
|
||||
BF16,
|
||||
Empty_Tuple,
|
||||
BF16,
|
||||
PassThrough,
|
||||
PassThrough,
|
||||
PassThrough>>>& instances)
|
||||
{
|
||||
|
||||
// 2. Filter1x1Stride1Pad0
|
||||
add_device_operation_instances(
|
||||
instances,
|
||||
device_grouped_conv_bwd_data_wmma_cshufflev3_bf16_wave_transfer_instances<
|
||||
2,
|
||||
NHWGK,
|
||||
GKYXC,
|
||||
Empty_Tuple,
|
||||
NHWGC,
|
||||
ConvBwdDataFilter1x1Stride1Pad0>{});
|
||||
}
|
||||
|
||||
} // namespace instance
|
||||
} // namespace device
|
||||
} // namespace tensor_operation
|
||||
} // namespace ck
|
||||
@@ -0,0 +1,42 @@
|
||||
// Copyright (c) Advanced Micro Devices, Inc., or its affiliates.
|
||||
// SPDX-License-Identifier: MIT
|
||||
|
||||
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
|
||||
#include "ck/library/tensor_operation_instance/gpu/grouped_conv_bwd_data/device_grouped_conv_bwd_data_wmma_v3_wave_tranfer_instances.hpp"
|
||||
|
||||
namespace ck {
|
||||
namespace tensor_operation {
|
||||
namespace device {
|
||||
namespace instance {
|
||||
|
||||
void add_device_grouped_conv2d_bwd_data_wmma_v3_wave_transfer_nhwgk_gkyxc_nhwgc_f16_instances(
|
||||
std::vector<std::unique_ptr<DeviceGroupedConvBwdDataMultipleD<2,
|
||||
NHWGK,
|
||||
GKYXC,
|
||||
Empty_Tuple,
|
||||
NHWGC,
|
||||
F16,
|
||||
F16,
|
||||
Empty_Tuple,
|
||||
F16,
|
||||
PassThrough,
|
||||
PassThrough,
|
||||
PassThrough>>>& instances)
|
||||
{
|
||||
|
||||
// 2. Filter1x1Stride1Pad0
|
||||
add_device_operation_instances(
|
||||
instances,
|
||||
device_grouped_conv_bwd_data_wmma_cshufflev3_f16_wave_transfer_instances<
|
||||
2,
|
||||
NHWGK,
|
||||
GKYXC,
|
||||
Empty_Tuple,
|
||||
NHWGC,
|
||||
ConvBwdDataFilter1x1Stride1Pad0>{});
|
||||
}
|
||||
|
||||
} // namespace instance
|
||||
} // namespace device
|
||||
} // namespace tensor_operation
|
||||
} // namespace ck
|
||||
@@ -45,6 +45,10 @@ set(GROUPED_CONV3D_BWD_DATA
|
||||
|
||||
wmma/device_grouped_conv3d_bwd_data_wmma_v3_ndhwgc_gkzyxc_ndhwgk_f16_16_16_instance.cpp
|
||||
wmma/device_grouped_conv3d_bwd_data_wmma_v3_ndhwgc_gkzyxc_ndhwgk_f16_instance.cpp
|
||||
|
||||
|
||||
wmma/device_grouped_conv3d_bwd_data_wmma_v3_wave_transfer_ndhwgc_gkzyxc_ndhwgk_bf16_instance.cpp
|
||||
wmma/device_grouped_conv3d_bwd_data_wmma_v3_wave_transfer_ndhwgc_gkzyxc_ndhwgk_f16_instance.cpp
|
||||
)
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
// Copyright (c) Advanced Micro Devices, Inc., or its affiliates.
|
||||
// SPDX-License-Identifier: MIT
|
||||
|
||||
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
|
||||
#include "ck/library/tensor_operation_instance/gpu/grouped_conv_bwd_data/device_grouped_conv_bwd_data_wmma_v3_wave_tranfer_instances.hpp"
|
||||
|
||||
namespace ck {
|
||||
namespace tensor_operation {
|
||||
namespace device {
|
||||
namespace instance {
|
||||
|
||||
void add_device_grouped_conv3d_bwd_data_wmma_v3_wave_transfer_ndhwgk_gkzyxc_ndhwgc_bf16_instances(
|
||||
std::vector<std::unique_ptr<DeviceGroupedConvBwdDataMultipleD<3,
|
||||
NDHWGK,
|
||||
GKZYXC,
|
||||
Empty_Tuple,
|
||||
NDHWGC,
|
||||
BF16,
|
||||
BF16,
|
||||
Empty_Tuple,
|
||||
BF16,
|
||||
PassThrough,
|
||||
PassThrough,
|
||||
PassThrough>>>& instances)
|
||||
{
|
||||
|
||||
// 2. Filter1x1Stride1Pad0
|
||||
add_device_operation_instances(
|
||||
instances,
|
||||
device_grouped_conv_bwd_data_wmma_cshufflev3_bf16_wave_transfer_instances<
|
||||
3,
|
||||
NDHWGK,
|
||||
GKZYXC,
|
||||
Empty_Tuple,
|
||||
NDHWGC,
|
||||
ConvBwdDataFilter1x1Stride1Pad0>{});
|
||||
}
|
||||
|
||||
} // namespace instance
|
||||
} // namespace device
|
||||
} // namespace tensor_operation
|
||||
} // namespace ck
|
||||
@@ -0,0 +1,42 @@
|
||||
// Copyright (c) Advanced Micro Devices, Inc., or its affiliates.
|
||||
// SPDX-License-Identifier: MIT
|
||||
|
||||
#include "ck/library/tensor_operation_instance/add_device_operation_instance.hpp"
|
||||
#include "ck/library/tensor_operation_instance/gpu/grouped_conv_bwd_data/device_grouped_conv_bwd_data_wmma_v3_wave_tranfer_instances.hpp"
|
||||
|
||||
namespace ck {
|
||||
namespace tensor_operation {
|
||||
namespace device {
|
||||
namespace instance {
|
||||
|
||||
void add_device_grouped_conv3d_bwd_data_wmma_v3_wave_transfer_ndhwgk_gkzyxc_ndhwgc_f16_instances(
|
||||
std::vector<std::unique_ptr<DeviceGroupedConvBwdDataMultipleD<3,
|
||||
NDHWGK,
|
||||
GKZYXC,
|
||||
Empty_Tuple,
|
||||
NDHWGC,
|
||||
F16,
|
||||
F16,
|
||||
Empty_Tuple,
|
||||
F16,
|
||||
PassThrough,
|
||||
PassThrough,
|
||||
PassThrough>>>& instances)
|
||||
{
|
||||
|
||||
// 2. Filter1x1Stride1Pad0
|
||||
add_device_operation_instances(
|
||||
instances,
|
||||
device_grouped_conv_bwd_data_wmma_cshufflev3_f16_wave_transfer_instances<
|
||||
3,
|
||||
NDHWGK,
|
||||
GKZYXC,
|
||||
Empty_Tuple,
|
||||
NDHWGC,
|
||||
ConvBwdDataFilter1x1Stride1Pad0>{});
|
||||
}
|
||||
|
||||
} // namespace instance
|
||||
} // namespace device
|
||||
} // namespace tensor_operation
|
||||
} // namespace ck
|
||||
Reference in New Issue
Block a user