mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-05-11 08:50:17 +00:00
debugged: CUDA should use its own float4 definition
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@@ -193,6 +193,7 @@ void device_implicit_gemm_convolution_2_chwn_cyxk_khwn(InDesc,
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constexpr index_t BlockSize = 256;
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#elif 0
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// 1x1, 14x14, Vega 20, disable lds_double_buffer, enable register double buffer
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// 1x1, 14x14, Pascal, enable lds_double_buffer, disable register double buffer
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constexpr index_t BPerBlock = 64;
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constexpr index_t KPerBlock = 128;
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constexpr index_t CPerBlock = 8;
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@@ -266,7 +267,7 @@ void device_implicit_gemm_convolution_2_chwn_cyxk_khwn(InDesc,
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for(index_t i = 0; i < nrepeat; ++i)
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{
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constexpr auto gridwise_conv =
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#if 1
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#if 0
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GridwiseConvolutionImplicitGemm_v2_chwn_cyxk_khwn
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#else
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GridwiseConvolutionImplicitGemm_v2_chwn_cyxk_khwn_lds_double_buffer
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@@ -580,7 +580,7 @@ int main(int argc, char* argv[])
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constexpr index_t HPad = 0;
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constexpr index_t WPad = 0;
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#elif 0
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#elif 1
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// 1x1 filter, 14x14 image, C = 2048
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constexpr index_t N = 128;
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constexpr index_t C = 2048;
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@@ -15,9 +15,13 @@ struct vector_type<float, 1>
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template <>
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struct vector_type<float, 2>
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{
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#if 1
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#if DEVICE_BACKEND_HIP
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// For some reason, HIP compiler need this definition to generate optimal load and store instruction
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typedef float MemoryType __attribute__((ext_vector_type(2)));
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#else
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#elif DEVICE_BACKEND_CUDA
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// For some reason, CUDA need this definition to, otherwise
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// compiler won't generate optimal load and store instruction, and
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// kernel would produce wrong result, indicating the compiler fail to generate correct instruction,
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using MemoryType = float2;
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#endif
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@@ -38,9 +42,13 @@ struct vector_type<float, 2>
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template <>
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struct vector_type<float, 4>
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{
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#if 1
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#if DEVICE_BACKEND_HIP
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// For some reason, HIP compiler need this definition to generate optimal load and store instruction
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typedef float MemoryType __attribute__((ext_vector_type(4)));
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#else
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#elif DEVICE_BACKEND_CUDA
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// For some reason, CUDA need this definition to, otherwise
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// compiler won't generate optimal load and store instruction, and
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// kernel would produce wrong result, indicating the compiler fail to generate correct instruction,
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using MemoryType = float4;
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#endif
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};
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@@ -204,8 +204,18 @@ struct GridwiseConvolutionImplicitGemm_v2_chwn_cyxk_khwn_lds_double_buffer
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// preload data into LDS
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{
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#if 1
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blockwise_in_copy.Run(p_in_global_block_offset, p_in_block_double);
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blockwise_wei_copy.Run(p_wei_global_block_offset, p_wei_block_double);
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Float p_in_register_clipboard[blockwise_in_copy.GetRegisterClipboardSize()];
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Float p_wei_register_clipboard[blockwise_wei_copy.GetRegisterClipboardSize()];
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blockwise_in_copy.RunLoadRegisterClipboard(p_in_global_block_offset,
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p_in_register_clipboard);
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blockwise_wei_copy.RunLoadRegisterClipboard(p_wei_global_block_offset,
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p_wei_register_clipboard);
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blockwise_in_copy.RunStoreRegisterClipboard(p_in_register_clipboard,
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p_in_block_double);
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blockwise_wei_copy.RunStoreRegisterClipboard(p_wei_register_clipboard,
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p_wei_block_double);
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#elif 0
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Float p_in_register_clipboard[blockwise_in_copy.GetRegisterClipboardSize()];
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Float p_wei_register_clipboard[blockwise_wei_copy.GetRegisterClipboardSize()];
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@@ -363,9 +373,9 @@ struct GridwiseConvolutionImplicitGemm_v2_chwn_cyxk_khwn_lds_double_buffer
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#elif 1
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blockwise_gemm.Run_asm
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#endif
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(p_wei_block_double + in_block_space +
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(p_wei_block_double + wei_block_space +
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wei_cyxk_block_desc.Get1dIndex(0, y, x, 0),
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p_in_block_double + wei_block_space + y * Wi + x,
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p_in_block_double + in_block_space + y * Wi + x,
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p_out_thread);
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}
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}
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