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https://github.com/ROCm/composable_kernel.git
synced 2026-05-14 02:02:46 +00:00
[CK_BUILDER] Fix cosmetic problem with conv_description (#3333)
The ConvDescription::detailed command wasn't using TreeFormatter::writeLast correctly, which led to extra lines being drawn in the tree view. It's a simple fix, just a cosmetic improvment out reflection output (ASCII art).
[ROCm/composable_kernel commit: d17994f3df]
This commit is contained in:
@@ -98,7 +98,7 @@ struct ConvDescription
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f.writeLine(2, "Weights elementwise operation: ", signature.weight_element_op);
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f.writeLast(2, "Output elementwise operation: ", signature.output_element_op);
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f.writeLine(1, "Algorithm");
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f.writeLast(1, "Algorithm");
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// Compute Block section
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f.writeLine(2, "Thread block size: ", algorithm.thread_block_size);
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f.writeLine(2,
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@@ -123,7 +123,7 @@ struct ConvDescription
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algorithm.warp_gemm.n_iter);
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// Memory Access section
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f.writeLine(2, "Memory access:");
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f.writeLast(2, "Memory access:");
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f.writeLine(3, "A Tile transfer: ");
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f.writeLine(4,
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@@ -219,8 +219,6 @@ struct ConvDescription
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f.writeLast(4,
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"Vector access (GMEM write) instruction size: ",
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algorithm.c_tile_transfer.scalar_per_vector);
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f.writeLast(2);
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f.writeLast(1);
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return f.getString();
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}
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@@ -127,41 +127,39 @@ TEST(ConvDescriptionTest, DefaultInstanceHasDetailedDescription)
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"│ ├─ Input elementwise operation: PASS_THROUGH\n"
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"│ ├─ Weights elementwise operation: PASS_THROUGH\n"
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"│ └─ Output elementwise operation: PASS_THROUGH\n"
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"├─ Algorithm\n"
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"│ ├─ Thread block size: 256\n"
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"│ ├─ Data tile size: 256×256×32\n"
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"│ ├─ Gemm padding: DEFAULT\n"
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"│ ├─ Convolution specialization: DEFAULT\n"
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"│ ├─ Pipeline version: V4\n"
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"│ ├─ Pipeline scheduler: INTRAWAVE\n"
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"│ ├─ Warp Gemm parameters: \n"
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"│ │ ├─ subtile size: 16×16\n"
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"│ │ └─ Number of warp gemm iterations: 4×4\n"
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"│ ├─ Memory access:\n"
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"│ │ ├─ A Tile transfer: \n"
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"│ │ │ ├─ Tile dimensions: 4×256×8×\n"
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"│ │ │ ├─ The innermost K subdimension size: 8\n"
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"│ │ │ ├─ Spatial thread distribution over the data tile: 0×1×2\n"
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"│ │ │ ├─ The order of accessing data tile axes: 0×1×2\n"
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"│ │ │ ├─ Vectorized memory access axis index (with contiguous memory): 2\n"
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"│ │ │ ├─ Vector access (GMEM read) instruction size: 8\n"
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"│ │ │ ├─ Vector access (LDS write) instruction size: 8\n"
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"│ │ │ └─ LDS data layout padding (to prevent bank conflicts): 8\n"
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"│ │ ├─ B Tile transfer: \n"
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"│ │ │ ├─ Tile dimensions: 4×256×8×\n"
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"│ │ │ ├─ The innermost K subdimension size: 8\n"
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"│ │ │ ├─ Spatial thread distribution over the data tile: 0×1×2\n"
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"│ │ │ ├─ The order of accessing data tile axes: 0×1×2\n"
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"│ │ │ ├─ Vectorized memory access axis index (with contiguous memory): 2\n"
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"│ │ │ ├─ Vector access (GMEM read) instruction size: 8\n"
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"│ │ │ ├─ Vector access (LDS write) instruction size: 8\n"
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"│ │ │ └─ LDS data layout padding (to prevent bank conflicts): 8\n"
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"│ │ └─ C Tile transfer: \n"
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"│ │ ├─ Data shuffle (number of gemm instructions per iteration): 1×1\n"
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"│ │ ├─ Spatial thread distribution used to store data: 1×32×1×8\n"
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"│ │ └─ Vector access (GMEM write) instruction size: 8\n"
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"│ └─ \n"
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"└─ "));
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"└─ Algorithm\n"
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" ├─ Thread block size: 256\n"
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" ├─ Data tile size: 256×256×32\n"
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" ├─ Gemm padding: DEFAULT\n"
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" ├─ Convolution specialization: DEFAULT\n"
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" ├─ Pipeline version: V4\n"
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" ├─ Pipeline scheduler: INTRAWAVE\n"
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" ├─ Warp Gemm parameters: \n"
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" │ ├─ subtile size: 16×16\n"
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" │ └─ Number of warp gemm iterations: 4×4\n"
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" └─ Memory access:\n"
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" ├─ A Tile transfer: \n"
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" │ ├─ Tile dimensions: 4×256×8×\n"
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" │ ├─ The innermost K subdimension size: 8\n"
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" │ ├─ Spatial thread distribution over the data tile: 0×1×2\n"
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" │ ├─ The order of accessing data tile axes: 0×1×2\n"
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" │ ├─ Vectorized memory access axis index (with contiguous memory): 2\n"
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" │ ├─ Vector access (GMEM read) instruction size: 8\n"
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" │ ├─ Vector access (LDS write) instruction size: 8\n"
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" │ └─ LDS data layout padding (to prevent bank conflicts): 8\n"
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" ├─ B Tile transfer: \n"
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" │ ├─ Tile dimensions: 4×256×8×\n"
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" │ ├─ The innermost K subdimension size: 8\n"
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" │ ├─ Spatial thread distribution over the data tile: 0×1×2\n"
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" │ ├─ The order of accessing data tile axes: 0×1×2\n"
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" │ ├─ Vectorized memory access axis index (with contiguous memory): 2\n"
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" │ ├─ Vector access (GMEM read) instruction size: 8\n"
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" │ ├─ Vector access (LDS write) instruction size: 8\n"
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" │ └─ LDS data layout padding (to prevent bank conflicts): 8\n"
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" └─ C Tile transfer: \n"
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" ├─ Data shuffle (number of gemm instructions per iteration): 1×1\n"
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" ├─ Spatial thread distribution used to store data: 1×32×1×8\n"
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" └─ Vector access (GMEM write) instruction size: 8"));
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}
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// NOTE: BackwardDataInstanceHasDetailedDescription test is disabled because ConvFactory
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