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Simplify condition for setting tile values

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Linjun-AMD
2026-02-02 15:48:26 +08:00
committed by GitHub
parent 7f0d5cdcc9
commit c4d95db73d
1 changed files with 1 additions and 1 deletions
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2
include/ck_tile/ops/fmha/pipeline/block_fmha_fwd_pagedkv_pipeline_qr_ks_vs.hpp
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@@ -240,7 +240,7 @@ struct BlockFmhaFwdPagedKVPipelineQRKSVS
}();
clear_tile(o_acc);
if((__builtin_isinf_sign(sink_v) >= 0) && i_split == 0)
if(__builtin_isinf_sign(sink_v) >= 0)
{
set_tile(m, init_m_val);
set_tile(l, SMPLComputeDataType{1.0f});