mirror of
https://github.com/ROCm/composable_kernel.git
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Add Grouped Conv Backward Weight on Navi21 for ResNet50. (#505)
* Add DeviceOp and examples
* Format DeviceOp template arguments
* Remove bf16 example
* Format
* Format
* Update MakeABCGridDescriptor_A_K0_M_K1_B_K0_N_K1_C_M_N
* Refactor argument preparation
* Update conv_bwd_weight_dl to grouped_conv_bwd_weight_dl
* Rename device op file
* Update include directive in the example file
* Update descriptor preparation for grouped op
* Update the argument
* Update batch handling
* Add gridwise gemm supporting batched input
* Update blockwise indexing, working version
* Update copyright year
* Update check if argument is supported
* Refactor and make consistent with xdl examples
* Update check if argument is supported
* Add changelog entry
* Added comments on Dl op split_k>1 support
---------
Co-authored-by: Rosty Geyyer <rosty.geyyer@amd.com>
Co-authored-by: zjing14 <zhangjing14@gmail.com>
[ROCm/composable_kernel commit: 246ceee49e]
This commit is contained in:
Rostyslav Geyyer
@@ -18,6 +18,7 @@ Full documentation for Composable Kernel is not yet available.
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- Added multi-D GEMM client APIs (#534).
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- Added multi-embeddings support (#542).
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- Added Navi3x blockwise GEMM and real GEMM support (#541).
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- Added Navi grouped ConvBwdWeight support (#505).
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### Changed
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- Changed ...
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@@ -6,3 +6,9 @@ add_example_executable(example_grouped_conv_bwd_weight_xdl_bf16 grouped_conv_bwd
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add_dependencies(example_grouped_conv_bwd_weight example_grouped_conv_bwd_weight_xdl_fp16
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example_grouped_conv_bwd_weight_xdl_bf16)
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add_custom_target(example_grouped_conv_bwd_weight_dl)
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add_example_executable(example_grouped_conv_bwd_weight_dl_fp16 grouped_conv_bwd_weight_dl_fp16.cpp)
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add_dependencies(example_grouped_conv_bwd_weight_dl example_grouped_conv_bwd_weight_dl_fp16)
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@@ -9,7 +9,6 @@
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#include "ck/ck.hpp"
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#include "ck/tensor_operation/gpu/device/convolution_backward_weight_specialization.hpp"
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#include "ck/tensor_operation/gpu/device/impl/device_grouped_conv_bwd_weight_gnwc_gkxc_gnwk_xdl_cshuffle.hpp"
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#include "ck/tensor_operation/gpu/device/tensor_layout.hpp"
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#include "ck/tensor_operation/gpu/element/element_wise_operation.hpp"
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@@ -0,0 +1,59 @@
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
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#include "common.hpp"
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#include "ck/tensor_operation/gpu/device/impl/device_grouped_conv_bwd_weight_gnwc_gkxc_gnwk_dl.hpp"
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using InDataType = F16;
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using WeiDataType = F16;
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using OutDataType = F16;
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using AccDataType = F32;
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using InElementOp = PassThrough;
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using WeiElementOp = PassThrough;
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using OutElementOp = PassThrough;
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template <ck::index_t NDimSpatial>
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using DeviceConvBwdWeightInstance =
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ck::tensor_operation::device::DeviceGroupedConvBwdWeightGnwcGkxcGnwk_Dl<
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NDimSpatial, // NDimSpatial
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InDataType, // InDataType
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WeiDataType, // WeiDataType
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OutDataType, // OutDataType
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AccDataType, // AccDataType
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InElementOp, // InElementwiseOperation
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WeiElementOp, // WeiElementwiseOperation
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OutElementOp, // OutElementwiseOperation
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ConvBwdWeightDefault, // ConvBackwardWeightSpecialization
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256, // BlockSize
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128, // MPerBlock
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128, // NPerBlock
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16, // K0PerBlock
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2, // K1
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4, // M1PerThread
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4, // N1PerThread
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1, // KPerThread
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S<8, 2>, // M1N1ThreadClusterM1Xs
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S<8, 2>, // M1N1ThreadClusterN1Xs
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S<1, 8, 1, 1, 2>, // ABlockTransferThreadSliceLengths_K0_M0_M1_K1
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S<1, 2, 1, 128, 1>, // ABlockTransferThreadClusterLengths_K0_M0_M1_K1
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S<0, 2, 3, 1, 4>, // ABlockTransferThreadClusterArrangeOrder
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S<0, 2, 3, 1, 4>, // ABlockTransferSrcAccessOrder
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S<1, 1, 1, 1, 1>, // ABlockTransferSrcVectorTensorLengths_K0_M0_M1_K1
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S<0, 2, 3, 1, 4>, // ABlockTransferSrcVectorTensorContiguousDimOrder
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S<1, 1, 1, 1, 1>, // ABlockTransferDstVectorTensorLengths_K0_M0_M1_K1
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S<1, 1, 1, 8, 2>, // BBlockTransferThreadSliceLengths_K0_N0_N1_K1
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S<1, 16, 1, 16, 1>, // BBlockTransferThreadClusterLengths_K0_N0_N1_K1
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S<0, 1, 4, 2, 3>, // BBlockTransferThreadClusterArrangeOrder
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S<0, 1, 4, 2, 3>, // BBlockTransferSrcAccessOrder
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S<1, 1, 1, 8, 1>, // BBlockTransferSrcVectorTensorLengths_K0_N0_N1_K1
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S<0, 1, 4, 2, 3>, // BBlockTransferSrcVectorTensorContiguousDimOrder
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S<1, 1, 1, 1, 2>, // BBlockTransferDstVectorTensorLengths_K0_N0_N1_K1
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S<0, 1, 2, 3, 4, 5>, // CThreadTransferSrcDstAccessOrder
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5, // CThreadTransferSrcDstVectorDim
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4>; // CThreadTransferDstScalarPerVector
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#include "run_grouped_conv_bwd_weight_example.inc"
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int main(int argc, char* argv[]) { return !run_grouped_conv_bwd_weight_example(argc, argv); }
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@@ -3,6 +3,8 @@
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#include "common.hpp"
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#include "ck/tensor_operation/gpu/device/impl/device_grouped_conv_bwd_weight_gnwc_gkxc_gnwk_xdl_cshuffle.hpp"
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using InDataType = BF16;
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// bf16 kernel use fp32 atomic add to accumulate Weight tensor into global memory
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using WeiDataType = F32;
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@@ -13,6 +15,46 @@ using InElementOp = PassThrough;
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using WeiElementOp = PassThrough;
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using OutElementOp = PassThrough;
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template <ck::index_t NDimSpatial>
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using DeviceConvBwdWeightInstance =
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ck::tensor_operation::device::DeviceGroupedConvBwdWeightGnwcGkxcGnwk_Xdl_CShuffle<
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NDimSpatial, // NDimSpatial
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InDataType, // InDataType
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WeiDataType, // WeiDataType
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OutDataType, // OutDataType
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AccDataType, // AccDataType
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InElementOp, // InElementwiseOperation
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WeiElementOp, // WeiElementwiseOperation
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OutElementOp, // OutElementwiseOperation
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ConvBwdWeightDefault, // ConvolutionBackwardWeightSpecialization
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256, // BlockSize
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128, // MPerBlock
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128, // NPerBlock
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4, // K0PerBlock
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8, // K1
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32, // MPerXdl
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32, // NPerXdl
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2, // MXdlPerWave
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2, // NXdlPerWave
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S<1, 4, 16, 4>, // ABlockTransferThreadClusterLengths_K0_M_K1
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S<0, 3, 1, 2>, // ABlockTransferThreadClusterArrangeOrder
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S<0, 2, 1, 3>, // ABlockTransferSrcAccessOrder
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2, // ABlockTransferSrcVectorDim
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8, // ABlockTransferSrcScalarPerVector
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2, // ABlockTransferDstScalarPerVector_K1
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true, // ABlockLdsAddExtraM
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S<1, 4, 16, 4>, // BBlockTransferThreadClusterLengths_K0_N_K1
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S<0, 3, 1, 2>, // BBlockTransferThreadClusterArrangeOrder
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S<0, 2, 1, 3>, // BBlockTransferSrcAccessOrder
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2, // BBlockTransferSrcVectorDim
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8, // BBlockTransferSrcScalarPerVector
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2, // BBlockTransferDstScalarPerVector_K1
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true, // BBlockLdsAddExtraN
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1, // CShuffleMXdlPerWavePerShuffle
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1, // CShuffleNXdlPerWavePerShuffle
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S<1, 32, 1, 4>, // CBlockTransferClusterLengths_MBlock_MPerBlock_NBlock_NPerBlock
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128 / (sizeof(WeiDataType) * CHAR_BIT)>; // CBlockTransferScalarPerVector_NWaveNPerXdl
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#include "run_grouped_conv_bwd_weight_example.inc"
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int main(int argc, char* argv[]) { return !run_grouped_conv_bwd_weight_example(argc, argv); }
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@@ -3,6 +3,8 @@
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#include "common.hpp"
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#include "ck/tensor_operation/gpu/device/impl/device_grouped_conv_bwd_weight_gnwc_gkxc_gnwk_xdl_cshuffle.hpp"
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using InDataType = F16;
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using WeiDataType = F16;
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using OutDataType = F16;
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@@ -12,6 +14,46 @@ using InElementOp = PassThrough;
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using WeiElementOp = PassThrough;
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using OutElementOp = PassThrough;
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template <ck::index_t NDimSpatial>
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using DeviceConvBwdWeightInstance =
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ck::tensor_operation::device::DeviceGroupedConvBwdWeightGnwcGkxcGnwk_Xdl_CShuffle<
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NDimSpatial, // NDimSpatial
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InDataType, // InDataType
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WeiDataType, // WeiDataType
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OutDataType, // OutDataType
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AccDataType, // AccDataType
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InElementOp, // InElementwiseOperation
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WeiElementOp, // WeiElementwiseOperation
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OutElementOp, // OutElementwiseOperation
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ConvBwdWeightDefault, // ConvolutionBackwardWeightSpecialization
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256, // BlockSize
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128, // MPerBlock
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128, // NPerBlock
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4, // K0PerBlock
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8, // K1
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32, // MPerXdl
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32, // NPerXdl
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2, // MXdlPerWave
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2, // NXdlPerWave
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S<1, 4, 16, 4>, // ABlockTransferThreadClusterLengths_K0_M_K1
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S<0, 3, 1, 2>, // ABlockTransferThreadClusterArrangeOrder
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S<0, 2, 1, 3>, // ABlockTransferSrcAccessOrder
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2, // ABlockTransferSrcVectorDim
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8, // ABlockTransferSrcScalarPerVector
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2, // ABlockTransferDstScalarPerVector_K1
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true, // ABlockLdsAddExtraM
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S<1, 4, 16, 4>, // BBlockTransferThreadClusterLengths_K0_N_K1
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S<0, 3, 1, 2>, // BBlockTransferThreadClusterArrangeOrder
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S<0, 2, 1, 3>, // BBlockTransferSrcAccessOrder
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2, // BBlockTransferSrcVectorDim
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8, // BBlockTransferSrcScalarPerVector
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2, // BBlockTransferDstScalarPerVector_K1
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true, // BBlockLdsAddExtraN
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1, // CShuffleMXdlPerWavePerShuffle
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1, // CShuffleNXdlPerWavePerShuffle
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S<1, 32, 1, 4>, // CBlockTransferClusterLengths_MBlock_MPerBlock_NBlock_NPerBlock
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128 / (sizeof(WeiDataType) * CHAR_BIT)>; // CBlockTransferScalarPerVector_NWaveNPerXdl
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#include "run_grouped_conv_bwd_weight_example.inc"
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int main(int argc, char* argv[]) { return !run_grouped_conv_bwd_weight_example(argc, argv); }
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@@ -1,46 +1,6 @@
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2018-2022, Advanced Micro Devices, Inc. All rights reserved.
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template <ck::index_t NDimSpatial>
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using DeviceConvBwdWeightInstance =
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ck::tensor_operation::device::DeviceGroupedConvBwdWeightGnwcGkxcGnwk_Xdl_CShuffle<
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NDimSpatial, // NDimSpatial
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InDataType, // InDataType
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WeiDataType, // WeiDataType
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OutDataType, // OutDataType
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AccDataType, // AccDataType
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InElementOp, // InElementwiseOperation
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WeiElementOp, // WeiElementwiseOperation
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OutElementOp, // OutElementwiseOperation
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ConvBwdWeightDefault, // ConvolutionBackwardWeightSpecialization
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256, // BlockSize
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128, // MPerBlock
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128, // NPerBlock
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4, // K0PerBlock
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8, // K1
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32, // MPerXdl
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32, // NPerXdl
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2, // MXdlPerWave
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2, // NXdlPerWave
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S<1, 4, 16, 4>, // ABlockTransferThreadClusterLengths_K0_M_K1
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S<0, 3, 1, 2>, // ABlockTransferThreadClusterArrangeOrder
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S<0, 2, 1, 3>, // ABlockTransferSrcAccessOrder
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2, // ABlockTransferSrcVectorDim
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8, // ABlockTransferSrcScalarPerVector
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2, // ABlockTransferDstScalarPerVector_K1
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true, // ABlockLdsAddExtraM
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S<1, 4, 16, 4>, // BBlockTransferThreadClusterLengths_K0_N_K1
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S<0, 3, 1, 2>, // BBlockTransferThreadClusterArrangeOrder
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S<0, 2, 1, 3>, // BBlockTransferSrcAccessOrder
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2, // BBlockTransferSrcVectorDim
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8, // BBlockTransferSrcScalarPerVector
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2, // BBlockTransferDstScalarPerVector_K1
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true, // BBlockLdsAddExtraN
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1, // CShuffleMXdlPerWavePerShuffle
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1, // CShuffleNXdlPerWavePerShuffle
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S<1, 32, 1, 4>, // CBlockTransferClusterLengths_MBlock_MPerBlock_NBlock_NPerBlock
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128 / (sizeof(WeiDataType) * CHAR_BIT)>; // CBlockTransferScalarPerVector_NWaveNPerXdl
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template <ck::index_t NDimSpatial>
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using HostConvBwdWeightInstance = ck::tensor_operation::host::ReferenceConvBwdWeight<NDimSpatial,
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InDataType,
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@@ -54,8 +14,19 @@ template <ck::index_t NDimSpatial>
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bool run_grouped_conv_bwd_weight(const ExecutionConfig& config,
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const ck::utils::conv::ConvParam& conv_param)
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{
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constexpr ck::index_t split_k = 2;
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ck::index_t split_k;
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// Set split_k = 2 for xdl op, split_k = 1 for dl
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// Dl op doesn't support split_k > 1
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// TODO: Add Dl op split_k > 1 support
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if(!(ck::get_device_name() == "gfx906" || ck::get_device_name() == "gfx1030"))
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{
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split_k = 2;
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}
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else
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{
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split_k = 1;
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}
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const auto in_g_n_c_wis_desc =
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ck::utils::conv::make_input_host_tensor_descriptor_g_n_c_wis_packed<
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InputLayout<NDimSpatial>>(conv_param);
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@@ -144,7 +115,7 @@ bool run_grouped_conv_bwd_weight(const ExecutionConfig& config,
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std::cerr << "wrong! device_conv with the specified compilation parameters does "
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"not support this Conv problem"
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<< std::endl;
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return false;
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return true;
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}
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float avg_time = invoker.Run(argument, StreamConfig{nullptr, config.time_kernel});
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File diff suppressed because it is too large
Load Diff
@@ -1,5 +1,5 @@
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2018-2022, Advanced Micro Devices, Inc. All rights reserved.
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// Copyright (c) 2018-2023, Advanced Micro Devices, Inc. All rights reserved.
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#pragma once
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@@ -574,4 +574,546 @@ struct GridwiseGemmDl_km_kn_mn_v1r3
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}
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};
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template <index_t BlockSize,
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typename FloatAB,
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typename FloatAcc,
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typename FloatC,
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InMemoryDataOperationEnum CGlobalMemoryDataOperation,
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typename AGridDesc_B_K0_M_K1,
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typename BGridDesc_B_K0_N_K1,
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typename CGridDesc_M_N,
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index_t MPerBlock,
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index_t NPerBlock,
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index_t K0PerBlock,
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index_t K1Value,
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index_t M1PerThreadM111,
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index_t N1PerThreadN111,
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index_t KPerThread,
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typename M11N11ThreadClusterM110Xs,
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typename M11N11ThreadClusterN110Xs,
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typename ABlockTransferThreadSliceLengths_K0_M0_M1_K1,
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typename ABlockTransferThreadClusterLengths_K0_M0_M1_K1,
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typename ABlockTransferThreadClusterArrangeOrder,
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typename ABlockTransferSrcAccessOrder,
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typename ABlockTransferSrcVectorTensorLengths_K0_M0_M1_K1,
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typename ABlockTransferSrcVectorTensorContiguousDimOrder,
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typename ABlockTransferDstVectorTensorLengths_K0_M0_M1_K1,
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typename BBlockTransferThreadSliceLengths_K0_N0_N1_K1,
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typename BBlockTransferThreadClusterLengths_K0_N0_N1_K1,
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typename BBlockTransferThreadClusterArrangeOrder,
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typename BBlockTransferSrcAccessOrder,
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typename BBlockTransferSrcVectorTensorLengths_K0_N0_N1_K1,
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typename BBlockTransferSrcVectorTensorContiguousDimOrder,
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typename BBlockTransferDstVectorTensorLengths_K0_N0_N1_K1,
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typename CThreadTransferSrcDstAccessOrder,
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index_t CThreadTransferSrcDstVectorDim,
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index_t CThreadTransferDstScalarPerVector>
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struct GridwiseGemmDl_bkm_bkn_mn_v1r3
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{
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static constexpr auto I0 = Number<0>{};
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static constexpr auto I1 = Number<1>{};
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static constexpr auto I2 = Number<2>{};
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static constexpr auto I3 = Number<3>{};
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// K1 should be Number<...>
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static constexpr auto K1 = Number<K1Value>{};
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__host__ __device__ static constexpr index_t GetSharedMemoryNumberOfByte()
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{
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// TODO: change this. I think it needs multi-dimensional alignment
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constexpr auto max_lds_align = K1;
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// TODO: check alignment
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// A matrix in LDS memory, dst of blockwise copy
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constexpr auto a_block_desc_b_k0_m_k1 = make_naive_tensor_descriptor_aligned(
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make_tuple(Number<1>{}, Number<K0PerBlock>{}, Number<MPerBlock>{}, K1), max_lds_align);
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// TODO: check alignment
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// B matrix in LDS memory, dst of blockwise copy
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constexpr auto b_block_desc_b_k0_n_k1 = make_naive_tensor_descriptor_aligned(
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make_tuple(Number<1>{}, Number<K0PerBlock>{}, Number<NPerBlock>{}, K1), max_lds_align);
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// TODO: check alignment
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// LDS allocation for A and B: be careful of alignment
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constexpr auto a_block_aligned_space_size = math::integer_least_multiple(
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a_block_desc_b_k0_m_k1.GetElementSpaceSize(), max_lds_align);
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constexpr auto b_block_aligned_space_size = math::integer_least_multiple(
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b_block_desc_b_k0_n_k1.GetElementSpaceSize(), max_lds_align);
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return 2 * (a_block_aligned_space_size + b_block_aligned_space_size) * sizeof(FloatAB);
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}
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__host__ __device__ static constexpr bool
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CheckValidity(const AGridDesc_B_K0_M_K1& a_grid_desc_b_k0_m_k1,
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const BGridDesc_B_K0_N_K1& b_grid_desc_b_k0_n_k1,
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const CGridDesc_M_N& c_grid_desc_m_n)
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{
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const auto M = a_grid_desc_b_k0_m_k1.GetLength(I2);
|
||||
const auto N = b_grid_desc_b_k0_n_k1.GetLength(I2);
|
||||
const auto K0 = a_grid_desc_b_k0_m_k1.GetLength(I1);
|
||||
const auto KBatch = a_grid_desc_b_k0_m_k1.GetLength(I0);
|
||||
|
||||
// TODO: also check validity of all components (blockwise-copy, threadwise-copy, etc)
|
||||
|
||||
return (M == c_grid_desc_m_n.GetLength(I0) && N == c_grid_desc_m_n.GetLength(I1) &&
|
||||
K0 == b_grid_desc_b_k0_n_k1.GetLength(I1) &&
|
||||
K1 == a_grid_desc_b_k0_m_k1.GetLength(I3) &&
|
||||
K1 == b_grid_desc_b_k0_n_k1.GetLength(I3)) &&
|
||||
KBatch == b_grid_desc_b_k0_n_k1.GetLength(I0) &&
|
||||
(M % MPerBlock == 0 && N % NPerBlock == 0 && K0 % K0PerBlock == 0);
|
||||
}
|
||||
|
||||
__host__ __device__ static constexpr index_t CalculateGridSize(index_t M, index_t N)
|
||||
{
|
||||
const index_t grid_size = (M / MPerBlock) * (N / NPerBlock);
|
||||
|
||||
return grid_size;
|
||||
}
|
||||
|
||||
__host__ __device__ static constexpr bool CalculateHasMainKBlockLoop(index_t K0)
|
||||
{
|
||||
const bool has_main_k_block_loop = (K0 + K0PerBlock) / (2 * K0PerBlock) > 1;
|
||||
|
||||
return has_main_k_block_loop;
|
||||
}
|
||||
|
||||
__host__ __device__ static constexpr bool CalculateHasDoubleTailKBlockLoop(index_t K0)
|
||||
{
|
||||
const bool has_double_tail_k_block_loop = (K0 / K0PerBlock) % 2 == 0;
|
||||
|
||||
return has_double_tail_k_block_loop;
|
||||
}
|
||||
|
||||
__host__ __device__ static constexpr auto
|
||||
MakeAGridDescriptor_B_K0_M0_M1_K1(const AGridDesc_B_K0_M_K1& a_grid_desc_b_k0_m_k1)
|
||||
{
|
||||
const auto KBatch = a_grid_desc_b_k0_m_k1.GetLength(I0);
|
||||
const auto K0 = a_grid_desc_b_k0_m_k1.GetLength(I1);
|
||||
const auto M = a_grid_desc_b_k0_m_k1.GetLength(I2);
|
||||
|
||||
const auto M1 = Number<MPerBlock>{};
|
||||
const auto M0 = M / M1;
|
||||
|
||||
const auto a_grid_desc_b_k0_m0_m1_k1 = transform_tensor_descriptor(
|
||||
a_grid_desc_b_k0_m_k1,
|
||||
make_tuple(make_pass_through_transform(KBatch),
|
||||
make_pass_through_transform(K0),
|
||||
make_unmerge_transform(make_tuple(M0, M1)),
|
||||
make_pass_through_transform(K1)),
|
||||
make_tuple(Sequence<0>{}, Sequence<1>{}, Sequence<2>{}, Sequence<3>{}),
|
||||
make_tuple(Sequence<0>{}, Sequence<1>{}, Sequence<2, 3>{}, Sequence<4>{}));
|
||||
|
||||
return a_grid_desc_b_k0_m0_m1_k1;
|
||||
}
|
||||
|
||||
__host__ __device__ static constexpr auto
|
||||
MakeBGridDescriptor_B_K0_N0_N1_K1(const BGridDesc_B_K0_N_K1& b_grid_desc_b_k0_n_k1)
|
||||
{
|
||||
const auto KBatch = b_grid_desc_b_k0_n_k1.GetLength(I0);
|
||||
const auto K0 = b_grid_desc_b_k0_n_k1.GetLength(I1);
|
||||
const auto N = b_grid_desc_b_k0_n_k1.GetLength(I2);
|
||||
|
||||
const auto N1 = Number<NPerBlock>{};
|
||||
const auto N0 = N / N1;
|
||||
|
||||
const auto b_grid_desc_b_k0_n0_n1_k1 = transform_tensor_descriptor(
|
||||
b_grid_desc_b_k0_n_k1,
|
||||
make_tuple(make_pass_through_transform(KBatch),
|
||||
make_pass_through_transform(K0),
|
||||
make_unmerge_transform(make_tuple(N0, N1)),
|
||||
make_pass_through_transform(K1)),
|
||||
make_tuple(Sequence<0>{}, Sequence<1>{}, Sequence<2>{}, Sequence<3>{}),
|
||||
make_tuple(Sequence<0>{}, Sequence<1>{}, Sequence<2, 3>{}, Sequence<4>{}));
|
||||
|
||||
return b_grid_desc_b_k0_n0_n1_k1;
|
||||
}
|
||||
|
||||
__host__ __device__ static constexpr auto
|
||||
MakeCGridDescriptor_M0_M10_M11_N0_N10_N11(const CGridDesc_M_N& c_grid_desc_m_n)
|
||||
{
|
||||
const auto M = c_grid_desc_m_n.GetLength(I0);
|
||||
const auto N = c_grid_desc_m_n.GetLength(I1);
|
||||
|
||||
constexpr auto M1 = Number<MPerBlock>{};
|
||||
constexpr auto N1 = Number<NPerBlock>{};
|
||||
|
||||
const auto M0 = M / M1;
|
||||
const auto N0 = N / N1;
|
||||
|
||||
constexpr auto M11 =
|
||||
Number<container_reduce(M11N11ThreadClusterM110Xs{}, math::multiplies{}, I1) *
|
||||
M1PerThreadM111>{};
|
||||
constexpr auto N11 =
|
||||
Number<container_reduce(M11N11ThreadClusterN110Xs{}, math::multiplies{}, I1) *
|
||||
N1PerThreadN111>{};
|
||||
|
||||
constexpr auto M10 = M1 / M11;
|
||||
constexpr auto N10 = N1 / N11;
|
||||
|
||||
const auto c_grid_desc_m0_m10_m11_n0_n10_n11 = transform_tensor_descriptor(
|
||||
c_grid_desc_m_n,
|
||||
make_tuple(make_unmerge_transform(make_tuple(M0, M10, M11)),
|
||||
make_unmerge_transform(make_tuple(N0, N10, N11))),
|
||||
make_tuple(Sequence<0>{}, Sequence<1>{}),
|
||||
make_tuple(Sequence<0, 1, 2>{}, Sequence<3, 4, 5>{}));
|
||||
|
||||
return c_grid_desc_m0_m10_m11_n0_n10_n11;
|
||||
}
|
||||
|
||||
// return block_id to C matrix tile idx (m0, n0) mapping
|
||||
__host__ __device__ static constexpr auto MakeCBlockClusterAdaptor(
|
||||
const CGridDesc_M_N& c_m_n_grid_desc, index_t M01, index_t N01, index_t KBatch)
|
||||
{
|
||||
return BlockToCTileMap_KSplit_M00_N00_M01_N01<MPerBlock, NPerBlock, CGridDesc_M_N>(
|
||||
c_m_n_grid_desc, M01, N01, KBatch);
|
||||
}
|
||||
|
||||
using AGridDesc_B_K0_M0_M1_K1 =
|
||||
decltype(MakeAGridDescriptor_B_K0_M0_M1_K1(AGridDesc_B_K0_M_K1{}));
|
||||
using BGridDesc_B_K0_N0_N1_K1 =
|
||||
decltype(MakeBGridDescriptor_B_K0_N0_N1_K1(BGridDesc_B_K0_N_K1{}));
|
||||
using CGridDesc_M0_M10_M11_N0_N10_N11 =
|
||||
decltype(MakeCGridDescriptor_M0_M10_M11_N0_N10_N11(CGridDesc_M_N{}));
|
||||
using CBlockClusterAdaptor = decltype(MakeCBlockClusterAdaptor(CGridDesc_M_N{}, 1, 1, 1));
|
||||
|
||||
template <bool HasMainKBlockLoop, bool HasDoubleTailKBlockLoop>
|
||||
__device__ static void
|
||||
Run(const FloatAB* __restrict__ p_a_grid,
|
||||
const FloatAB* __restrict__ p_b_grid,
|
||||
FloatC* __restrict__ p_c_grid,
|
||||
FloatAB* __restrict__ p_shared_block,
|
||||
const AGridDesc_B_K0_M0_M1_K1& a_grid_desc_b_k0_m0_m1_k1,
|
||||
const BGridDesc_B_K0_N0_N1_K1& b_grid_desc_b_k0_n0_n1_k1,
|
||||
const CGridDesc_M0_M10_M11_N0_N10_N11& c_grid_desc_m0_m10_m11_n0_n10_n11,
|
||||
const CBlockClusterAdaptor& c_block_cluster_adaptor,
|
||||
integral_constant<bool, HasMainKBlockLoop>,
|
||||
integral_constant<bool, HasDoubleTailKBlockLoop>)
|
||||
{
|
||||
const auto a_global_buf = make_dynamic_buffer<AddressSpaceEnum::Global>(
|
||||
p_a_grid, a_grid_desc_b_k0_m0_m1_k1.GetElementSpaceSize());
|
||||
const auto b_global_buf = make_dynamic_buffer<AddressSpaceEnum::Global>(
|
||||
p_b_grid, b_grid_desc_b_k0_n0_n1_k1.GetElementSpaceSize());
|
||||
auto c_grid_buf = make_dynamic_buffer<AddressSpaceEnum::Global>(
|
||||
p_c_grid, c_grid_desc_m0_m10_m11_n0_n10_n11.GetElementSpaceSize());
|
||||
|
||||
// divide block work by [M, N]
|
||||
const auto block_work_idx =
|
||||
c_block_cluster_adaptor.CalculateBottomIndex(make_multi_index(get_block_1d_id()));
|
||||
|
||||
const index_t k_batch_id = block_work_idx[I0];
|
||||
|
||||
if(!c_block_cluster_adaptor.ValidCTileIndex(
|
||||
make_tuple(block_work_idx[I1], block_work_idx[I2]),
|
||||
make_tuple(c_grid_desc_m0_m10_m11_n0_n10_n11.GetLength(I0),
|
||||
c_grid_desc_m0_m10_m11_n0_n10_n11.GetLength(I3))))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
// HACK: this force m/n_block_data_idx_on_grid into SGPR
|
||||
const index_t m_block_data_idx_on_grid = __builtin_amdgcn_readfirstlane(block_work_idx[I1]);
|
||||
|
||||
const index_t n_block_data_idx_on_grid = __builtin_amdgcn_readfirstlane(block_work_idx[I2]);
|
||||
|
||||
// TODO: change this. I think it needs multi-dimensional alignment
|
||||
constexpr auto max_lds_align = K1;
|
||||
|
||||
// TODO: check alignment
|
||||
// A matrix in LDS memory, dst of blockwise copy
|
||||
// be careful of LDS alignment
|
||||
constexpr auto a_block_desc_b_k0_m0_m1_k1 = make_naive_tensor_descriptor_aligned(
|
||||
make_tuple(I1, Number<K0PerBlock>{}, I1, Number<MPerBlock>{}, K1), max_lds_align);
|
||||
|
||||
// TODO: check alignment
|
||||
// B matrix in LDS memory, dst of blockwise copy
|
||||
// be careful of LDS alignment
|
||||
constexpr auto b_block_desc_b_k0_n0_n1_k1 = make_naive_tensor_descriptor_aligned(
|
||||
make_tuple(I1, Number<K0PerBlock>{}, I1, Number<NPerBlock>{}, K1), max_lds_align);
|
||||
|
||||
// TODO: check alignment
|
||||
// A matrix in LDS memory, dst of blockwise copy
|
||||
// be careful of LDS alignment
|
||||
constexpr auto a_block_desc_k0_m0_m1_k1 = make_naive_tensor_descriptor_aligned(
|
||||
make_tuple(Number<K0PerBlock>{}, I1, Number<MPerBlock>{}, K1), max_lds_align);
|
||||
|
||||
// TODO: check alignment
|
||||
// B matrix in LDS memory, dst of blockwise copy
|
||||
// be careful of LDS alignment
|
||||
constexpr auto b_block_desc_k0_n0_n1_k1 = make_naive_tensor_descriptor_aligned(
|
||||
make_tuple(Number<K0PerBlock>{}, I1, Number<NPerBlock>{}, K1), max_lds_align);
|
||||
|
||||
// TODO: check alignment
|
||||
// A matrix in LDS memory, for blockwise GEMM
|
||||
constexpr auto a_k0_m_k1_block_desc = make_naive_tensor_descriptor_aligned(
|
||||
make_tuple(Number<K0PerBlock>{}, Number<MPerBlock>{}, K1), max_lds_align);
|
||||
|
||||
// TODO: check alignment
|
||||
// B matrix in LDS memory, for blockwise GEMM
|
||||
constexpr auto b_k0_n_k1_block_desc = make_naive_tensor_descriptor_aligned(
|
||||
make_tuple(Number<K0PerBlock>{}, Number<NPerBlock>{}, K1), max_lds_align);
|
||||
|
||||
static_assert(a_block_desc_k0_m0_m1_k1.GetElementSpaceSize() ==
|
||||
a_k0_m_k1_block_desc.GetElementSpaceSize() &&
|
||||
b_block_desc_k0_n0_n1_k1.GetElementSpaceSize() ==
|
||||
b_k0_n_k1_block_desc.GetElementSpaceSize() &&
|
||||
"wrong!");
|
||||
|
||||
// A matrix blockwise copy
|
||||
auto a_blockwise_copy = BlockwiseTensorSliceTransfer_v5r1<
|
||||
BlockSize,
|
||||
InMemoryDataOperationEnum::Set,
|
||||
Sequence<1, K0PerBlock, 1, MPerBlock, K1.value>,
|
||||
ABlockTransferThreadSliceLengths_K0_M0_M1_K1,
|
||||
ABlockTransferThreadClusterLengths_K0_M0_M1_K1,
|
||||
ABlockTransferThreadClusterArrangeOrder,
|
||||
FloatAB,
|
||||
FloatAB,
|
||||
remove_reference_t<decltype(a_grid_desc_b_k0_m0_m1_k1)>,
|
||||
decltype(a_block_desc_b_k0_m0_m1_k1),
|
||||
ABlockTransferSrcAccessOrder,
|
||||
Sequence<0, 1, 2, 3, 4>,
|
||||
ABlockTransferSrcVectorTensorLengths_K0_M0_M1_K1, // SrcVectorTensorLengths
|
||||
ABlockTransferDstVectorTensorLengths_K0_M0_M1_K1, // DstVectorTensorLengths
|
||||
ABlockTransferSrcVectorTensorContiguousDimOrder, // SrcVectorTensorContiguousDimOrder
|
||||
Sequence<0, 1, 2, 3, 4>, // DstVectorTensorContiguousDimOrder
|
||||
false,
|
||||
true>(a_grid_desc_b_k0_m0_m1_k1,
|
||||
make_multi_index(k_batch_id, 0, m_block_data_idx_on_grid, 0, 0),
|
||||
a_block_desc_b_k0_m0_m1_k1,
|
||||
make_multi_index(0, 0, 0, 0, 0));
|
||||
|
||||
// B matrix blockwise copy
|
||||
auto b_blockwise_copy = BlockwiseTensorSliceTransfer_v5r1<
|
||||
BlockSize,
|
||||
InMemoryDataOperationEnum::Set,
|
||||
Sequence<1, K0PerBlock, 1, NPerBlock, K1.value>,
|
||||
BBlockTransferThreadSliceLengths_K0_N0_N1_K1,
|
||||
BBlockTransferThreadClusterLengths_K0_N0_N1_K1,
|
||||
BBlockTransferThreadClusterArrangeOrder,
|
||||
FloatAB,
|
||||
FloatAB,
|
||||
remove_reference_t<decltype(b_grid_desc_b_k0_n0_n1_k1)>,
|
||||
decltype(b_block_desc_b_k0_n0_n1_k1),
|
||||
BBlockTransferSrcAccessOrder,
|
||||
Sequence<0, 1, 2, 3, 4>,
|
||||
BBlockTransferSrcVectorTensorLengths_K0_N0_N1_K1, // SrcVectorTensorLengths
|
||||
BBlockTransferDstVectorTensorLengths_K0_N0_N1_K1, // DstVectorTensorLengths
|
||||
BBlockTransferSrcVectorTensorContiguousDimOrder, // SrcVectorTensorContiguousDimOrder
|
||||
Sequence<0, 1, 2, 3, 4>, // DstVectorTensorContiguousDimOrder
|
||||
false,
|
||||
true>(b_grid_desc_b_k0_n0_n1_k1,
|
||||
make_multi_index(k_batch_id, 0, n_block_data_idx_on_grid, 0, 0),
|
||||
b_block_desc_b_k0_n0_n1_k1,
|
||||
make_multi_index(0, 0, 0, 0, 0));
|
||||
|
||||
// GEMM definition
|
||||
// c_mtx += transpose(a_mtx) * b_mtx
|
||||
// a_mtx[K0PerBlock, MPerBlock] is in LDS
|
||||
// b_mtx[KPerBlocl, NPerBlock] is in LDS
|
||||
// c_mtx[MPerBlock, NPerBlock] is distributed among threads, and saved in
|
||||
// register
|
||||
const auto blockwise_gemm =
|
||||
BlockwiseGemmDl_A_BK0_BM_BK1_B_BK0_BN_BK1_C_BM0_BM1_BN0_BN1_pipeline_BM0_2_BN0_2<
|
||||
BlockSize,
|
||||
FloatAB,
|
||||
FloatAB,
|
||||
FloatAcc,
|
||||
decltype(a_k0_m_k1_block_desc),
|
||||
decltype(b_k0_n_k1_block_desc),
|
||||
M1PerThreadM111,
|
||||
N1PerThreadN111,
|
||||
KPerThread,
|
||||
M11N11ThreadClusterM110Xs,
|
||||
M11N11ThreadClusterN110Xs,
|
||||
M1PerThreadM111,
|
||||
N1PerThreadN111>{};
|
||||
|
||||
constexpr auto c_m10_m11_n10_n11_thread_tensor_lengths =
|
||||
decltype(blockwise_gemm)::GetCThreadTensorLengths_BM0_BM1_BN0_BN1();
|
||||
|
||||
constexpr auto c_thread_desc_m10_m11_n10_n11 = make_naive_tensor_descriptor_packed(
|
||||
sequence_to_tuple_of_number(c_m10_m11_n10_n11_thread_tensor_lengths));
|
||||
|
||||
// LDS allocation for A and B: be careful of alignment
|
||||
constexpr auto a_block_aligned_space_size = math::integer_least_multiple(
|
||||
a_block_desc_k0_m0_m1_k1.GetElementSpaceSize(), max_lds_align);
|
||||
|
||||
constexpr auto b_block_aligned_space_size = math::integer_least_multiple(
|
||||
b_block_desc_k0_n0_n1_k1.GetElementSpaceSize(), max_lds_align);
|
||||
|
||||
FloatAB* p_a_block_double = p_shared_block;
|
||||
FloatAB* p_b_block_double = p_shared_block + 2 * a_block_aligned_space_size;
|
||||
|
||||
// register allocation for output
|
||||
auto c_thread_buf = make_static_buffer<AddressSpaceEnum::Vgpr, FloatAcc>(
|
||||
c_thread_desc_m10_m11_n10_n11.GetElementSpaceSize());
|
||||
|
||||
// Initialize C
|
||||
c_thread_buf.Clear();
|
||||
|
||||
constexpr auto a_block_slice_copy_step = make_multi_index(0, K0PerBlock, 0, 0, 0);
|
||||
constexpr auto b_block_slice_copy_step = make_multi_index(0, K0PerBlock, 0, 0, 0);
|
||||
|
||||
auto a_block_even_buf = make_dynamic_buffer<AddressSpaceEnum::Lds>(
|
||||
p_a_block_double, a_block_desc_k0_m0_m1_k1.GetElementSpaceSize());
|
||||
auto b_block_even_buf = make_dynamic_buffer<AddressSpaceEnum::Lds>(
|
||||
p_b_block_double, b_block_desc_k0_n0_n1_k1.GetElementSpaceSize());
|
||||
|
||||
auto a_block_odd_buf = make_dynamic_buffer<AddressSpaceEnum::Lds>(
|
||||
p_a_block_double + a_block_aligned_space_size,
|
||||
a_block_desc_k0_m0_m1_k1.GetElementSpaceSize());
|
||||
auto b_block_odd_buf = make_dynamic_buffer<AddressSpaceEnum::Lds>(
|
||||
p_b_block_double + b_block_aligned_space_size,
|
||||
b_block_desc_k0_n0_n1_k1.GetElementSpaceSize());
|
||||
|
||||
// LDS double buffer: preload data into LDS
|
||||
{
|
||||
a_blockwise_copy.RunRead(a_grid_desc_b_k0_m0_m1_k1, a_global_buf);
|
||||
b_blockwise_copy.RunRead(b_grid_desc_b_k0_n0_n1_k1, b_global_buf);
|
||||
|
||||
a_blockwise_copy.RunWrite(a_block_desc_b_k0_m0_m1_k1, a_block_even_buf);
|
||||
b_blockwise_copy.RunWrite(b_block_desc_b_k0_n0_n1_k1, b_block_even_buf);
|
||||
}
|
||||
|
||||
if constexpr(HasMainKBlockLoop)
|
||||
{
|
||||
const auto K0 = a_grid_desc_b_k0_m0_m1_k1.GetLength(I1);
|
||||
|
||||
index_t k_block_data_begin = 0;
|
||||
|
||||
// LDS double buffer: main body
|
||||
// use Do-While loop instead of For loop to simplify control flow
|
||||
do
|
||||
{
|
||||
// even iteration
|
||||
a_blockwise_copy.MoveSrcSliceWindow(a_grid_desc_b_k0_m0_m1_k1,
|
||||
a_block_slice_copy_step);
|
||||
b_blockwise_copy.MoveSrcSliceWindow(b_grid_desc_b_k0_n0_n1_k1,
|
||||
b_block_slice_copy_step);
|
||||
|
||||
// LDS doubel buffer: load next data from device mem
|
||||
a_blockwise_copy.RunRead(a_grid_desc_b_k0_m0_m1_k1, a_global_buf);
|
||||
b_blockwise_copy.RunRead(b_grid_desc_b_k0_n0_n1_k1, b_global_buf);
|
||||
|
||||
block_sync_lds();
|
||||
|
||||
// LDS double buffer: GEMM on current data
|
||||
blockwise_gemm.Run(c_thread_desc_m10_m11_n10_n11,
|
||||
a_block_even_buf,
|
||||
b_block_even_buf,
|
||||
c_thread_buf);
|
||||
|
||||
// LDS double buffer: store next data to LDS
|
||||
a_blockwise_copy.RunWrite(a_block_desc_b_k0_m0_m1_k1, a_block_odd_buf);
|
||||
b_blockwise_copy.RunWrite(b_block_desc_b_k0_n0_n1_k1, b_block_odd_buf);
|
||||
|
||||
// odd iteration
|
||||
a_blockwise_copy.MoveSrcSliceWindow(a_grid_desc_b_k0_m0_m1_k1,
|
||||
a_block_slice_copy_step);
|
||||
b_blockwise_copy.MoveSrcSliceWindow(b_grid_desc_b_k0_n0_n1_k1,
|
||||
b_block_slice_copy_step);
|
||||
|
||||
// LDS doubel buffer: load next data from device mem
|
||||
a_blockwise_copy.RunRead(a_grid_desc_b_k0_m0_m1_k1, a_global_buf);
|
||||
b_blockwise_copy.RunRead(b_grid_desc_b_k0_n0_n1_k1, b_global_buf);
|
||||
|
||||
block_sync_lds();
|
||||
|
||||
// LDS double buffer: GEMM on current data
|
||||
blockwise_gemm.Run(
|
||||
c_thread_desc_m10_m11_n10_n11, a_block_odd_buf, b_block_odd_buf, c_thread_buf);
|
||||
|
||||
// LDS double buffer: store next data to LDS
|
||||
a_blockwise_copy.RunWrite(a_block_desc_b_k0_m0_m1_k1, a_block_even_buf);
|
||||
b_blockwise_copy.RunWrite(b_block_desc_b_k0_n0_n1_k1, b_block_even_buf);
|
||||
|
||||
k_block_data_begin += 2 * K0PerBlock;
|
||||
} while(k_block_data_begin < K0 - 2 * K0PerBlock);
|
||||
}
|
||||
|
||||
// LDS double buffer: tail
|
||||
if constexpr(HasDoubleTailKBlockLoop) // if has 2 iteration left
|
||||
{
|
||||
a_blockwise_copy.MoveSrcSliceWindow(a_grid_desc_b_k0_m0_m1_k1, a_block_slice_copy_step);
|
||||
b_blockwise_copy.MoveSrcSliceWindow(b_grid_desc_b_k0_n0_n1_k1, b_block_slice_copy_step);
|
||||
|
||||
block_sync_lds();
|
||||
|
||||
// LDS double buffer: load last data from device mem
|
||||
a_blockwise_copy.RunRead(a_grid_desc_b_k0_m0_m1_k1, a_global_buf);
|
||||
b_blockwise_copy.RunRead(b_grid_desc_b_k0_n0_n1_k1, b_global_buf);
|
||||
|
||||
// LDS double buffer: GEMM on 2nd-last data
|
||||
blockwise_gemm.Run(
|
||||
c_thread_desc_m10_m11_n10_n11, a_block_even_buf, b_block_even_buf, c_thread_buf);
|
||||
|
||||
// LDS double buffer: store last data to LDS
|
||||
a_blockwise_copy.RunWrite(a_block_desc_b_k0_m0_m1_k1, a_block_odd_buf);
|
||||
b_blockwise_copy.RunWrite(b_block_desc_b_k0_n0_n1_k1, b_block_odd_buf);
|
||||
|
||||
block_sync_lds();
|
||||
|
||||
// LDS double buffer: GEMM on last data
|
||||
blockwise_gemm.Run(
|
||||
c_thread_desc_m10_m11_n10_n11, a_block_odd_buf, b_block_odd_buf, c_thread_buf);
|
||||
}
|
||||
else // if has 1 iteration left
|
||||
{
|
||||
__syncthreads();
|
||||
|
||||
// LDS double buffer: GEMM on last data
|
||||
blockwise_gemm.Run(
|
||||
c_thread_desc_m10_m11_n10_n11, a_block_even_buf, b_block_even_buf, c_thread_buf);
|
||||
}
|
||||
|
||||
// output: register to global memory
|
||||
{
|
||||
constexpr auto c_thread_desc_m0_m10_m11_n0_n10_n11 =
|
||||
make_naive_tensor_descriptor_packed(
|
||||
make_tuple(I1,
|
||||
Number<c_m10_m11_n10_n11_thread_tensor_lengths[I0]>{},
|
||||
Number<c_m10_m11_n10_n11_thread_tensor_lengths[I1]>{},
|
||||
I1,
|
||||
Number<c_m10_m11_n10_n11_thread_tensor_lengths[I2]>{},
|
||||
Number<c_m10_m11_n10_n11_thread_tensor_lengths[I3]>{}));
|
||||
|
||||
const auto c_m10_m11_n10_n11_thread_origin_idx_on_block =
|
||||
blockwise_gemm.CalculateCThreadOriginOnBlock_BM0_BM1_BN0_BN1(
|
||||
get_thread_local_1d_id());
|
||||
|
||||
ThreadwiseTensorSliceTransfer_v1r3<
|
||||
FloatAcc,
|
||||
FloatC,
|
||||
decltype(c_thread_desc_m0_m10_m11_n0_n10_n11),
|
||||
decltype(c_grid_desc_m0_m10_m11_n0_n10_n11),
|
||||
ck::tensor_operation::element_wise::PassThrough,
|
||||
Sequence<1,
|
||||
c_m10_m11_n10_n11_thread_tensor_lengths[I0],
|
||||
c_m10_m11_n10_n11_thread_tensor_lengths[I1],
|
||||
1,
|
||||
c_m10_m11_n10_n11_thread_tensor_lengths[I2],
|
||||
c_m10_m11_n10_n11_thread_tensor_lengths[I3]>,
|
||||
CThreadTransferSrcDstAccessOrder,
|
||||
CThreadTransferSrcDstVectorDim,
|
||||
CThreadTransferDstScalarPerVector,
|
||||
CGlobalMemoryDataOperation,
|
||||
1,
|
||||
true>{c_grid_desc_m0_m10_m11_n0_n10_n11,
|
||||
make_multi_index(m_block_data_idx_on_grid,
|
||||
c_m10_m11_n10_n11_thread_origin_idx_on_block[I0],
|
||||
c_m10_m11_n10_n11_thread_origin_idx_on_block[I1],
|
||||
n_block_data_idx_on_grid,
|
||||
c_m10_m11_n10_n11_thread_origin_idx_on_block[I2],
|
||||
c_m10_m11_n10_n11_thread_origin_idx_on_block[I3]),
|
||||
ck::tensor_operation::element_wise::PassThrough{}}
|
||||
.Run(c_thread_desc_m0_m10_m11_n0_n10_n11,
|
||||
make_tuple(I0, I0, I0, I0, I0, I0),
|
||||
c_thread_buf,
|
||||
c_grid_desc_m0_m10_m11_n0_n10_n11,
|
||||
c_grid_buf);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace ck
|
||||
|
||||
Reference in New Issue
Block a user