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Author	SHA1	Message	Date
Chao Liu	f00c138145	adding logic to judge linear dimension	2019-09-20 20:43:13 -05:00
Chao Liu	bf7e7d62a8	refactor	2019-09-19 23:44:23 -05:00
Chao Liu	b6e1c52a80	use buffer_load buffer_store intrinsic	2019-09-19 15:39:07 -05:00
Chao Liu	8afbb10d18	reduce some register usage in index	2019-09-18 16:42:45 -05:00
Chao Liu	94bb1b4835	refactor	2019-09-18 16:08:24 -05:00
Chao Liu	86cc678f18	add global_load and buffer_load inline asm	2019-09-18 15:41:55 -05:00
Chao Liu	5b7a18c506	experimenting global and buffer load/store	2019-09-18 02:05:42 -05:00
Chao Liu	c7a6545ec4	experimenting global and buffer load/store	2019-09-18 01:37:28 -05:00
Chao Liu	9f46cdf5fa	experimenting global and buffer load/store	2019-09-18 00:15:57 -05:00
Chao Liu	f58bf38445	enable hip compiler flag: -amdgpu-enable-global-sgpr-addr	2019-09-17 17:34:39 -05:00
Chao Liu	126cae0c9b	bug fix	2019-09-17 15:02:12 -05:00
Chao Liu	e1a67b693e	refactor	2019-09-17 11:19:15 -05:00
Chao Liu	f7be86b9e4	refactor	2019-09-16 22:47:55 -05:00
Chao Liu	d707993933	bug fix	2019-09-15 20:57:07 -05:00
Chao Liu	69fea593ec	amd build	2019-09-15 17:55:46 -05:00
Chao Liu	940949d9d5	add lds doble buffer to nchw padded v4r1 and v4r4	2019-09-15 16:59:54 -05:00
Chao Liu	bf97542846	add lds doble buffer to nchw padded v4r1 and v4r4	2019-09-15 16:58:16 -05:00
Chao Liu	2c93b3057d	initial implementation for nchw v4r4 padding	2019-09-15 16:31:54 -05:00
Chao Liu	53094f7fae	clean up	2019-09-15 12:13:58 -05:00
Chao Liu	d4878d99f9	initial padding support for nchw	2019-09-13 23:30:48 -05:00
Chao Liu	bd7a230006	clean up	2019-09-12 14:55:46 -05:00
Chao Liu	1f70524471	padding for chwn is functional	2019-09-12 01:12:08 -05:00
Chao Liu	724e984bff	enabling padding for chwn format	2019-09-11 01:13:13 -05:00
Chao Liu	ca42e9101d	adding merge transform	2019-09-10 01:53:49 -05:00
Chao Liu	7a7fe16086	more utility code	2019-09-09 00:29:33 -05:00
Chao Liu	625838def0	added tuple	2019-09-06 18:07:56 -05:00
Chao Liu	12da8154c8	adding dimension transformation	2019-09-05 00:20:05 -05:00
Chao Liu	0c05f4279f	adding dimension tranformation	2019-09-05 00:19:06 -05:00
Chao Liu	bd44e6390d	adding dimension transformation	2019-09-02 00:21:00 -05:00
Chao Liu	cb6475c77d	clean	2019-08-23 09:59:23 -05:00
Chao Liu	6ff3fe5d05	Merge remote-tracking branch 'origin/master' into add_tensor_view	2019-08-21 14:46:16 -05:00
Chao Liu	0c83df668f	add script for doing Jack's ISA injection hack	2019-08-21 14:29:13 -05:00
Chao Liu	238d58c2f5	adding tensor_view	2019-08-20 17:29:54 -05:00
Chao Liu	08bf57b01c	bug fix: BlockwiseGenericTensorSliceCopy_v2::MoveDstSlicingWindow	2019-08-15 15:12:13 -05:00
Chao Liu	86ceded98b	Merge remote-tracking branch 'origin/master' into add_padding	2019-08-15 13:48:45 -05:00
Chao Liu	0979fb4af9	clean up	2019-08-15 13:21:51 -05:00
Chao Liu	4fb81e008c	adding padding to implicit gemm v1r3	2019-08-14 10:55:34 -05:00
Chao Liu	740149fcf1	clean up	2019-08-13 17:26:00 -05:00
Chao Liu	40836ab926	add back some code	2019-08-13 12:21:38 -05:00
Chao Liu	8bdaba51f8	clean up	2019-08-13 00:37:23 -05:00
Chao Liu	fab2f10a55	clean up	2019-08-12 15:48:35 -05:00
Chao Liu	1c4ef23cff	cleaning up	2019-08-09 22:48:28 -05:00
Chao Liu	4908fe3fdc	tweak on amd	2019-08-08 12:14:06 -05:00
Chao Liu	a9b2b1dcd7	added ThreadwiseGenericTensorSliceCopy_v2r1	2019-08-08 02:42:52 -05:00
Chao Liu	701b7341f0	clean up	2019-08-07 19:25:54 -05:00
Chao Liu	bc9ea646f8	use ford/for instead of static_ford/static_for in threadwise copy, somehow register spill is greatly reduced on AMD	2019-08-07 19:09:13 -05:00
Chao Liu	5636576f9b	bug fix in ford, forgot to reorder lengths	2019-08-07 18:27:10 -05:00
Chao Liu	9d99a58072	adding ThreadwiseGenericTensorSliceCopy_v1r2	2019-08-07 16:51:14 -05:00
Chao Liu	1b3c2e4035	reworked ThreadwiseGenericTensorSliceCopy_v1	2019-08-07 00:52:13 -05:00
Chao Liu	41cdde99e5	add looping Orders into ford and static_ford	2019-08-06 20:23:11 -05:00