Ville Pietilä
f3e4c0721f
Improved config.
2026-02-16 10:48:32 -06:00
Ville Pietilä
fb782ba133
Remove additional barriers from double buffer implementation.
2026-02-16 09:53:43 -06:00
Ville Pietilä
5494425e7b
Double buffering baseline.
2026-02-16 07:44:45 -06:00
Ville Pietilä
b4112526ce
WIP: Triple buffer pipeline.
2026-02-11 10:32:35 -05:00
Ville Pietilä
998ddc5d12
Add scheduling barriers and remove debug sync statements.
2026-02-11 08:31:56 -05:00
Ville Pietilä
5bacca7b8a
Working double buffer implementation for V1 gridwise GEMM pipeline,
2026-02-11 06:35:49 -05:00
Ville Pietilä
afdd6a84a7
WIP: Double buffer implementation.
2026-02-10 10:03:41 -05:00
Ville Pietilä
59cbe19c83
More documentation.
2026-02-10 07:34:27 -05:00
Ville Pietilä
c9504f2c27
Update profiling doc.
2026-02-10 04:45:54 -05:00
Ville Pietilä
d32bdb1412
Merge branch 'vpietila/retina-net-fwd-convs' into vpietila/retina-net-training-perf
2026-02-09 06:54:16 -05:00
Ville Pietilä
b722492a30
Add BF16 example.
2026-02-09 06:36:20 -05:00
Ville Pietilä
60d1ec34a9
Improve benchmarking scripts.
2026-02-09 04:34:27 -05:00
Ville Pietilä
53201d2081
Disable some cases.
2026-02-04 10:47:12 -05:00
Ville Pietilä
7660fa0a2e
Fix gitignore.
2026-02-04 10:07:26 -05:00
Ville Pietilä
e2225e2baa
Git ignore rocprofv3 files.
2026-02-04 10:05:14 -05:00
Ville Pietilä
c97795b139
Remove .dat file.
2026-02-04 10:04:55 -05:00
Ville Pietilä
1c842f39a4
Git ignore profiler output.
2026-02-04 10:02:57 -05:00
Ville Pietilä
1c1ac4ef10
Small fixes to runner script.
2026-02-04 09:55:05 -05:00
Ville Pietilä
73b459c5a4
Runner script for benchmarking.
2026-02-04 09:38:16 -05:00
Ville Pietilä
3e6415a8ea
True baseline benchmarking results.
2026-02-04 07:56:15 -05:00
Ville Pietilä
20cf6df685
Best instances for benchmark shapes.
2026-02-04 07:27:34 -05:00
Ville Pietilä
2cfc4209bb
Profile optionally only a given instance.
2026-02-04 06:31:36 -05:00
Ville Pietilä
f6f381dbd4
Benchmarking shapes and baseline results.
2026-02-04 06:07:19 -05:00
Ville Pietilä
403f36ed26
Disable building all but fwd convs for CK profiler.
2026-02-04 06:07:06 -05:00
Ville Pietilä
d132df2bf5
Finalize conv specialization for filter 3x3, pad 1, stride 1, dilation 1 case.
2026-02-03 04:10:09 -05:00
Ville Pietilä
a814ba15fd
Add profiling documentation.
2026-02-02 11:15:46 -05:00
Ville Pietilä
bd81d645e2
Add one more specialization.
2026-02-02 03:03:13 -05:00
Bartłomiej Kocot
fbb073f276
Update device_grouped_conv_bwd_data_multiple_d_xdl_cshuffle_v3.hpp
2026-01-31 20:46:58 +01:00
Jakub Piasecki
2086516deb
fixed building errors
2026-01-30 19:22:34 +00:00
Jakub Piasecki
ae2d2d9f2c
fixed conflicts
2026-01-30 18:47:19 +00:00
Bartlomiej Kocot
a7b57187cf
Grouped Convolution Backward Data Direct Load
...
Co-authored-by: Jakub Piasecki <jakpia21@gmail.com >
2026-01-30 18:45:23 +00:00
Graner, Johannes
c815e734c7
Add good instance
2026-01-30 10:50:06 -05:00
Ville Pietilä
4b7ec1bacb
Filter 3x3, pad1, stride1, dilation 1 - specialization.
2026-01-30 10:26:48 -05:00
Ville Pietilä
7ffa682bd3
Add missing applicability check to v3 fwd convs.
2026-01-30 05:05:38 -05:00
Ville Pietilä
966706bb21
Add new grouped conv instance to the gfx950 branch.
2026-01-30 04:13:36 -05:00
Ville Pietilä
fc7964462e
Conv specializations.
2026-01-29 11:50:50 -05:00
Graner, Johannes
5301efc8e4
Add NumGroupsToMerge to BwdWeight type string
2026-01-29 09:30:02 -05:00
Ville Pietilä
0fba67a7e7
Add fwd conv group merging to the v3 conv instances.
2026-01-29 08:16:11 -05:00
Ville Pietilä
d7c4775455
Improve logging.
2026-01-29 05:50:09 -05:00
Ville Pietilä
44960922a2
Merge remote-tracking branch 'origin/jograner/bwd-weight-splitk-autodeduce' into features/grouped-conv-perf-uplift
2026-01-28 10:57:40 -05:00
Ville Pietilä
c92b954537
Add new fwd conv fp16/bf16 instances optimized for unit group size.
2026-01-28 10:50:46 -05:00
Graner, Johannes
029efffeb5
Update test with new applicability
2026-01-28 09:19:41 -05:00
Graner, Johannes
0eee2d3392
Fix threshold calculation
2026-01-28 09:18:03 -05:00
Ville Pietilä
349fb5206e
Merge remote-tracking branch 'origin/develop' into vpietila/retina-net-training-perf
2026-01-28 02:38:04 -05:00
Graner, Johannes
55d8e9b4f0
Add missing logic to wmma multiple d kernel
2026-01-28 02:12:18 -05:00
damien-lejeune
91e32f305f
[CK Tile] multi reduce improvements ( #3607 )
...
* WIP: refactoring
* Swap operation/data nested loops order
* Improve memory coalescing
* Add comments
* Enforce same identity element for the reduce operations
* Re-add compile time constant
* Comment + re-add __builtin_amdgcn_readfirstlane(0) to the loop init
---------
Co-authored-by: Damien Lejeune <damien.lejeune@amd.com >
2026-01-27 12:56:09 -08:00
linqunAMD
23cefda140
[ck] add gridwise base class for in all xdl kernel ( #186 ) ( #3544 )
...
1. Add base class GridwiseGemm_xdl_cshuffle_base for all gridwise_gemm_xdl classes.
- to select correct LDS layout and epilogue behavior , three additional parameters is added.
- ForceNaiveLdsLayout: disable XOR based LDS layout when it is true
- DirectLoad: pipeline only use directload, we need force naive layout and ignore any padding on gfx9
- IsMxGemm: epilogue has two addtional dimensions
2. Move all LDS descriptor layout related fucntion to base class, including
- GetABlockDescriptor_AK0PerBlock_MPerBlock_AK1
- GetBBlockDescriptor_BK0PerBlock_NPerBlock_BK1
- GetCShuffleBlockDescriptor_MBlock_MPerBlock_NBlock_NPerBlock
3. Move several LDS related helper funtions to base class, including
- GetSharedMemoryNumberOfByte
- GetABlockDescriptor_AKB_AK0PerBlock_MPerBlock_AK1
- GetBBlockDescriptor_BKB_BK0PerBlock_NPerBlock_BK1
- GetCBlockDescriptor_MBlock_NXdlPerWave_MWaveMPerXdl_NBlock_NXdlPerWave_NWaveNPerXdl
4. Move all c epilogue related code to base class, and 4 kind of implementation are provided
- RunEpilogueNoShuffle
- RunEpilogue
- RunMultiDEpilogue
- RunMoeEpilogue
2026-01-27 12:49:47 -08:00
Michał Kulikowski
b737f1dee5
[CK]Refactoring threadwise_tensor_slice_transfer_v3r1.hpp ( #3263 )
...
Signed-off-by: Michal Kulikowski <Michal.Kulikowski@amd.com >
Co-authored-by: Illia Silin <98187287+illsilin@users.noreply.github.com >
2026-01-27 10:48:16 -08:00
Illia Silin
b26cb596b0
fix some syntax errors ( #3658 )
2026-01-27 09:59:39 -08:00
Ville Pietilä
42fde4860a
Custom global mem write.
2026-01-27 11:24:29 -05:00
