Chao Liu
f4acec502e
Restructure gridwise and blockwise GEMM, add tensor contraction and FWD-v4r5 ( #36 )
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* experimenting magic number division
* overhauling fwd-v4r4 to clearly reflect transformation graph
* added fwd-v4r5
* bug fix for make_dynamic_naive_tensor_descriptor_aligned_v2
* bug fix and added sanity-check in transform_dynamic_tensor_descriptor
* added conv_driver_v2
[ROCm/composable_kernel commit: 30072aec37
2021-06-09 23:53:08 -05:00
Chao Liu
040023fdcd
reorganize some files ( #33 )
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[ROCm/composable_kernel commit: 71d6b19d18
2021-05-12 14:15:38 -05:00
Chao Liu
da8f48c6d6
Use DynamicBuffer instead of raw pointer ( #32 )
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* Use DynamicBuffer to hold raw pointer (to global and LDS memory)
* add workaround for compiler issue (inefficient ISA) of ds_write for int8x4, int8x8, int8x16
[ROCm/composable_kernel commit: 78b987fbd6
2021-05-12 13:10:42 -05:00
Chao Liu
ce4662dbda
No raw index calculation ( #31 )
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* Replace most raw index calculation to coordinate transformation
* Overhaul blockwise and threadwise GEMM
* Overhaul driver for gridwies GEMM kernel
Co-authored-by: Jing Zhang <jizhan@amd.com >
[ROCm/composable_kernel commit: 01055d95d9
2021-05-11 00:09:25 -05:00
Chao Liu
8a0d2f6753
Use Tuple and vector_type instead of Array for holding tensor data ( #30 )
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* replacing array with tuple and vector for tensor data
[ROCm/composable_kernel commit: d075adf126
2021-04-28 13:10:33 -05:00
Chao Liu
504850a3ee
Overhaul vector_type and use real vector for int8x4_t instead of aliasing from int32_t ( #29 )
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* overhaul vector_type, make int8x4_t real vector instead of aliasing from int32_t
[ROCm/composable_kernel commit: e4790c250c
2021-04-12 23:48:43 -05:00
Chao Liu
e8dee31b22
Initial implementation of magic number division and "Merge" transformation that use it ( #28 )
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* initial implementation for magic number division and DynamicMerge_v2_magic_division that uses it
* turn off DynamicMerge_v2_magic_division that use magic number division by default
[ROCm/composable_kernel commit: 3bf52e60c5
2021-04-12 21:32:55 -05:00
zjing14
2b37c278c8
Hybrid direct + implicit GEMM forward convolution NCHWc v5r1 ( #25 )
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* Hybrid direct + implicit GEMM forward convolution NCHWc v5r1. Input tensor bypass LDS. Support fp32/fp16/int8
[ROCm/composable_kernel commit: 792a20fa5b
2021-04-07 16:47:29 -05:00
Chao Liu
53b5a937a9
Fix performance issue when passing tensor descriptor from host to kernel by void pointers ( #27 )
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* use address_space(4) in kernel signature to fix performance issue when passing tensor descriptor from host to kernel by (void) pointers
* remove passing by pointer* option (only use pass by value or void*)
[ROCm/composable_kernel commit: d2217f3040
2021-04-06 17:49:57 -05:00
zjing14
e3c16f20e0
bug fix for buffer resource setting ( #26 )
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[ROCm/composable_kernel commit: 6a5ea49309
2021-04-06 16:59:52 -05:00
Chao Liu
b4dbf677ce
Dynamic tensor descriptor ( #24 )
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* support dynamic tensor descriptor
* use buffer load OOB feature for padding case
* add navi support
* add int8x4 inference kernel
Co-authored-by: Chao Liu <chao@ixt-rack-81.local.lan >
Co-authored-by: Jing Zhang <jizhan@amd.com >
[ROCm/composable_kernel commit: fcbb978828
2021-03-25 13:51:11 -05:00
Chao Liu
00d2add663
Bwd Data NHWC ( #22 )
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* fix buffer_store bug
* remove obsolete kernels
* add bwd-data-v5r1-nhwc
[ROCm/composable_kernel commit: bbcb67d0aa
2020-08-06 12:22:11 -05:00
Chao Liu
74112e767f
Improve buffer address for out of bound check ( #21 )
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* Use buffer load built-in OOB check. buffer size is limited to 2GB.
* buffer APIs use combined wave and thread offset
* use uint32_t for addr shift in buffer addressing
[ROCm/composable_kernel commit: ac62d13ecd
2020-07-29 18:04:09 -05:00
Chao Liu
0eb214d1cd
Code clean up ( #20 )
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* tuning para,
* testing on v100
* add fp16
* remove deprecated tensor descriptor
* sync with miopen
* update build script
Co-authored-by: Jing Zhang <jizhan@amd.com >
[ROCm/composable_kernel commit: 5c7cec1115
2020-06-23 20:31:27 -05:00
Chao Liu
3f1a4f1c56
MIOpen integration ( #15 )
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* renaming
[ROCm/composable_kernel commit: 7d09790a0a
2020-02-18 10:42:18 -06:00
Chao Liu
ef393a2bb2
MIopen integration ( #13 )
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* update for miopen integration: cosmetic refactor
[ROCm/composable_kernel commit: 1a66e35b6f
2020-02-17 09:53:20 -06:00
Chao Liu
81e3c745dc
Update for recent MIOpen integration ( #11 )
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* update for MIOpen integration
[ROCm/composable_kernel commit: 3406a1148a
2020-01-27 15:29:33 -06:00
Chao Liu
8b51bc4b1d
Added bwd data v3r1 v4r1, tweaking v1 ( #10 )
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* Added bwd data v3r1: breaking down compute into a series of load balanced GEMM, and launch in a single kernel
* Added bwd data v4r1: like v3r1, but launch GEMMs in multiple kernels
* Tweaked v1r1 and v1r2 (atomic) on AMD GPU
[ROCm/composable_kernel commit: c5da0377fb
2020-01-20 10:20:03 -06:00
Chao Liu
670a6134d6
update implicit GEMM forward v4r4 to use gridwise gemm ( #9 )
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* updated fwd v4r4 to use gridwise gemm
* updated gridwise gemm api calls in bwd-data v1r1 and v2r1
[ROCm/composable_kernel commit: e2b4c5b469
2019-12-05 12:36:36 -06:00
Chao Liu
095808df3a
fixed faulty padding API calls ( #8 )
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[ROCm/composable_kernel commit: 19a93dac05
2019-12-03 01:46:44 -06:00
Chao Liu
3799741fee
backward data ( #7 )
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* enabled atomic add in tensor copy
* added gridwise GEMM
* added backward data conv using GEMM + atomic
* added backward data conv using GEMM, no atomic
[ROCm/composable_kernel commit: 8f5f64960e
2019-12-03 01:16:12 -06:00
Chao Liu
2cfc943628
remove dead file ( #6 )
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[ROCm/composable_kernel commit: 31ded4ac4b
2019-11-04 17:13:38 -06:00
Chao Liu
d6dccf43fe
MIOpen integration: recent bug fixes from MIOpen ( #5 )
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[ROCm/composable_kernel commit: 562e1e2767
2019-11-04 16:51:12 -06:00
Chao Liu
08f130fed1
Refactor for MIOpen integration ( #4 )
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Refactor, so can bring multi-index transformation and padding support into MIOpen
[ROCm/composable_kernel commit: 52c3fe05be
2019-10-11 11:37:31 -05:00
Chao Liu
0c41efb629
enable type conversion in blockwise copy v2 and threadwise copy v2r1
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[ROCm/composable_kernel commit: cf21818455
2019-09-30 15:11:05 -05:00
Chao Liu
3bc034ec9e
tweaking
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[ROCm/composable_kernel commit: 012d3a071b
2019-09-27 16:38:11 -05:00
Chao Liu
28d6a9834a
tweaking
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[ROCm/composable_kernel commit: 14315b72f3
2019-09-27 15:24:27 -05:00
Chao Liu
8df18296f5
debugging
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[ROCm/composable_kernel commit: ebe38f3d48
2019-09-27 11:31:01 -05:00
Chao Liu
a87fa81015
remove dead code
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[ROCm/composable_kernel commit: 9b280cc50d
2019-09-27 02:00:59 -05:00
Chao Liu
38b3aeafb6
nvidia build
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[ROCm/composable_kernel commit: 98a2cfcc84
2019-09-27 00:15:05 -05:00
Chao Liu
1109bb05d0
clean up
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[ROCm/composable_kernel commit: 00089cd6e5
2019-09-26 21:39:28 -05:00
Chao Liu
c5e4a623f9
clean up
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[ROCm/composable_kernel commit: b12bbceebc
2019-09-26 14:59:19 -05:00
Chao Liu
bd8f263b70
removing dependency on old tensor descriptor
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[ROCm/composable_kernel commit: 51a9fa1dbd
2019-09-26 11:49:05 -05:00
Chao Liu
eb0a575ad1
added type conversion in threadwise and blockwise copy
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[ROCm/composable_kernel commit: 0f52c4c0e4
2019-09-26 00:00:25 -05:00
Chao Liu
4b54b1f190
added type conversion in threadwise and blockwise copy
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[ROCm/composable_kernel commit: b3d4595f5a
2019-09-25 23:38:26 -05:00
Chao Liu
2c7fc0bc28
removing old implementation of tensor descriptor
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[ROCm/composable_kernel commit: 3cb2a7d09f
2019-09-25 22:43:34 -05:00
Chao Liu
313eb881cd
removing old implementation of tensor descriptor
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[ROCm/composable_kernel commit: 39d92e7dfd
2019-09-25 22:24:06 -05:00
Chao Liu
66f7a03ee4
clean up
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[ROCm/composable_kernel commit: 012b525377
2019-09-25 03:28:53 -05:00
Chao Liu
9695b9f548
added GetLinearDimensionMask
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[ROCm/composable_kernel commit: e1ae8f18f7
2019-09-25 02:52:41 -05:00
Chao Liu
1019fcf64d
adding GetLinearDimensionMask()
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[ROCm/composable_kernel commit: 4f4aba4872
2019-09-24 23:59:47 -05:00
Chao Liu
ca661e1f52
refactor
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[ROCm/composable_kernel commit: 545d930568
2019-09-24 18:06:05 -05:00
Chao Liu
9338f82689
nvidia build
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[ROCm/composable_kernel commit: 37f4e2b6d8
2019-09-22 03:23:19 -05:00
Chao Liu
b60cecbbc8
done: explicitly separate offset component into compile-time, block-invariant and per-thread components. Experimenting
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[ROCm/composable_kernel commit: 6c2c50b020
2019-09-22 03:17:41 -05:00
Chao Liu
c3a1be3865
WIP: explicitly separate offset component into compile-time, block-invariant and per-thread components
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[ROCm/composable_kernel commit: 51884fc214
2019-09-21 22:53:03 -05:00
Chao Liu
f961bfabf7
refactor
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[ROCm/composable_kernel commit: 740da00aa2
2019-09-20 21:45:20 -05:00
Chao Liu
18b23028f0
nvidia build
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[ROCm/composable_kernel commit: 184c6e7d37
2019-09-20 21:45:03 -05:00
Chao Liu
3bd3443225
adding logic to judge linear dimension
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[ROCm/composable_kernel commit: f00c138145
2019-09-20 20:43:13 -05:00
Chao Liu
b9722daae4
refactor
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[ROCm/composable_kernel commit: bf7e7d62a8
2019-09-19 23:44:23 -05:00
Chao Liu
056e48a3ac
use buffer_load buffer_store intrinsic
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[ROCm/composable_kernel commit: b6e1c52a80
2019-09-19 15:39:07 -05:00
Chao Liu
c1f7320764
reduce some register usage in index
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[ROCm/composable_kernel commit: 8afbb10d18
2019-09-18 16:42:45 -05:00
