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[CK_TILE] Integrate CK Tile Dispatcher code generation into CK Tile Profiler (#7284) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ## Motivation CK Tile is going to be delivered to hipDNN via CK Dispatcher. Currently the CK Tile Profiler using CK Builder for generating the profiled instances from the configuration files that identify the instances that old CK exposes. We need to replace this instance generation with the CK Tile Dispatcher codegen. ## Technical Details The old CK Profiler config files are converted to JSON files that the CK Tile Dispatcher can digest. The conversion script for configurations is stored to source control in case we need to update the JSON configurations later. The dispatcher generates instance libraries per conv direction (fwd, bwd data, and bwd weight) that are linked to the CK Profiler executable. I also implemented codegne for the stream-K and depthwise conv instances. The proposed solution replaces the CK Builder codegen with the CK Tile Dispatcher codegen. There are two new methods that are exposed via the dispatcher backend - `is_supported` - required to enabled the profiler workflow where we check the applicability of the kernel instance before running it. - `get_instance_string` - this mainly for verification. This provide the CK Builder instance string for verifying that the old CK Builder based profiler and the new CK Tile Dispatcher based profiler have the same instances. The rules that limit the generated instances are now collected to a single location under the dispacther. The CK Builder codegen uses these, which ensures that the two codegen pipelines are in sync. The next step (different PR) is to remove the CK Builder codegen pipeline altogether. ## Test Plan Verified that the old CK Builder based profiler and the new CK Tile Dispatcher based profiler have the same instances, that is, the Dispatcher based codgen can generate the same instances as the old CK Builder. ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.
274 lines
9.4 KiB
JSON
274 lines
9.4 KiB
JSON
{
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"_comment": "Single source of truth for GPU architecture specifications. Edit this file to add new GPU support.",
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"_version": "1.2.0",
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"_instructions": "See ADDING_NEW_GPU.md for instructions on adding new GPU support.",
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"_supported_arch_note": "CK Tile supports: GFX9 (gfx908, gfx90a, gfx942, gfx950), GFX10.3 (gfx103x), GFX11 (gfx110x, gfx115x), GFX12 (gfx120x)",
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"architectures": {
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"gfx908": {
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"family": "cdna1",
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"target_family": "gfx9",
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"architecture": "cdna",
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"description": "AMD Instinct MI100",
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"warp_size": 64,
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"lds_capacity_kb": 64,
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"warp_configs": [
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[1, 4, 1],
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[2, 2, 1],
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[4, 1, 1]
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],
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"warp_tile_combos": {
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"fp32_fp32_fp32": [[16, 16, 4], [16, 16, 16]],
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32]],
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"int8_int8_int32": [[32, 32, 16], [16, 16, 32]]
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}
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},
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"gfx90a": {
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"family": "cdna2",
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"target_family": "gfx9",
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"architecture": "cdna",
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"description": "AMD Instinct MI200 series",
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"warp_size": 64,
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"lds_capacity_kb": 64,
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"warp_configs": [
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[1, 4, 1],
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[2, 2, 1],
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[4, 1, 1]
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],
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"warp_tile_combos": {
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"fp32_fp32_fp32": [[16, 16, 4], [16, 16, 16]],
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [4, 64, 16], [64, 4, 16]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [4, 64, 16], [64, 4, 16]],
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"fp8_fp8_fp32": [[32, 32, 16], [32, 32, 32]],
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"bf8_bf8_fp32": [[32, 32, 16], [32, 32, 32]],
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"int8_int8_int32": [[32, 32, 16], [16, 16, 32]]
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}
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},
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"gfx942": {
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"family": "cdna3",
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"target_family": "gfx9",
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"architecture": "cdna",
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"description": "AMD Instinct MI300 series",
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"warp_size": 64,
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"lds_capacity_kb": 64,
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"warp_configs": [
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[1, 4, 1],
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[2, 2, 1],
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[4, 1, 1]
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],
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"warp_tile_combos": {
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"fp32_fp32_fp32": [[16, 16, 4], [16, 16, 16]],
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [4, 64, 16], [64, 4, 16]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [4, 64, 16], [64, 4, 16]],
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"fp8_fp8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 64]],
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"fp8_bf8_fp32": [[32, 32, 16], [16, 16, 32], [32, 32, 32]],
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"bf8_fp8_fp32": [[32, 32, 16]],
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"bf8_bf8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 64]],
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"int8_int8_int32": [[32, 32, 16], [16, 16, 32]]
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}
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},
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"gfx950": {
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"family": "cdna4",
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"target_family": "gfx9",
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"architecture": "cdna",
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"description": "AMD Instinct MI350 series",
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"warp_size": 64,
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"lds_capacity_kb": 160,
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"warp_configs": [
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[1, 4, 1],
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[2, 2, 1],
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[4, 1, 1],
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[8, 2, 1],
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[4, 4, 1]
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],
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"warp_tile_combos": {
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"fp32_fp32_fp32": [[16, 16, 4], [16, 16, 16]],
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [4, 64, 16], [64, 4, 16]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [4, 64, 16], [64, 4, 16]],
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"fp8_fp8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 64], [16, 16, 128], [32, 32, 64]],
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"fp8_bf8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 128], [32, 32, 64]],
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"bf8_fp8_fp32": [[32, 32, 16], [16, 16, 128], [32, 32, 64]],
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"bf8_bf8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 64], [16, 16, 128], [32, 32, 64]],
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"int8_int8_int32": [[32, 32, 16], [16, 16, 32]],
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"pk_fp4_pk_fp4_fp32": [[16, 16, 128]]
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}
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},
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"gfx1100": {
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"family": "rdna3",
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"target_family": "gfx11",
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"architecture": "rdna",
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"description": "AMD Radeon RX 7900 series (RDNA3)",
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"warp_size": 32,
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"lds_capacity_kb": 64,
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"warp_configs": [
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[2, 4, 1],
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[1, 8, 1],
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[8, 1, 1],
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[4, 2, 1]
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],
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"warp_tile_combos": {
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"fp16_fp16_fp32": [[16, 16, 16]],
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"bf16_bf16_fp32": [[16, 16, 16]],
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"int8_int8_int32": [[16, 16, 16]]
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}
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},
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"gfx1200": {
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"family": "rdna4",
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"target_family": "gfx12",
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"architecture": "rdna",
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"description": "AMD Radeon RX 9000 series (RDNA4)",
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"warp_size": 32,
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"lds_capacity_kb": 64,
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"warp_configs": [
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[2, 4, 1],
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[1, 8, 1],
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[8, 1, 1],
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[4, 2, 1]
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],
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"warp_tile_combos": {
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"fp16_fp16_fp32": [[16, 16, 16]],
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"bf16_bf16_fp32": [[16, 16, 16]],
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"fp8_fp8_fp32": [[16, 16, 16]],
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"bf8_bf8_fp32": [[16, 16, 16]],
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"fp8_bf8_fp32": [[16, 16, 16]],
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"bf8_fp8_fp32": [[16, 16, 16]],
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"int8_int8_int32": [[16, 16, 16]]
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}
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},
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"gfx1201": {
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"family": "rdna4",
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"target_family": "gfx12",
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"architecture": "rdna",
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"description": "AMD Radeon RX 9000 series (RDNA4)",
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"warp_size": 32,
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"lds_capacity_kb": 64,
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"warp_configs": [
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[2, 4, 1],
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[1, 8, 1],
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[8, 1, 1],
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[4, 2, 1]
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],
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"warp_tile_combos": {
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"fp16_fp16_fp32": [[16, 16, 16]],
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"bf16_bf16_fp32": [[16, 16, 16]],
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"fp8_fp8_fp32": [[16, 16, 16]],
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"bf8_bf8_fp32": [[16, 16, 16]],
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"fp8_bf8_fp32": [[16, 16, 16]],
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"bf8_fp8_fp32": [[16, 16, 16]],
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"int8_int8_int32": [[16, 16, 16]]
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}
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}
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},
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"element_sizes": {
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"fp16": 2,
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"bf16": 2,
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"fp32": 4,
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"fp64": 8,
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"fp8": 1,
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"bf8": 1,
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"int8": 1,
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"int4": 0.5,
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"pk_fp4": 0.5,
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"int32": 4
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},
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"datatype_cpp_map": {
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"_comment": "Maps dtype string to CK Tile C++ type for code generation",
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"fp16": "ck_tile::half_t",
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"bf16": "ck_tile::bf16_t",
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"fp32": "float",
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"fp64": "double",
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"fp8": "ck_tile::fp8_t",
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"bf8": "ck_tile::bf8_t",
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"int8": "ck_tile::int8_t",
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"int4": "ck_tile::pk_int4_t",
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"pk_fp4": "ck_tile::pk_fp4_t",
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"int32": "ck_tile::int32_t"
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},
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"dtype_combinations": {
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"_comment": "All valid (A, B) -> Acc combinations for GEMM from warp_gemm_dispatcher.hpp",
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"fp32_fp32": {"acc": "fp32", "notes": "Full precision"},
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"fp16_fp16": {"acc": "fp32", "notes": "Standard half precision"},
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"bf16_bf16": {"acc": "fp32", "notes": "Brain float 16"},
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"fp8_fp8": {"acc": "fp32", "notes": "FP8 E4M3"},
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"fp8_bf8": {"acc": "fp32", "notes": "Mixed FP8/BF8"},
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"bf8_fp8": {"acc": "fp32", "notes": "Mixed BF8/FP8"},
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"bf8_bf8": {"acc": "fp32", "notes": "BF8 E5M2"},
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"int8_int8": {"acc": "int32", "notes": "Integer GEMM"},
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"pk_fp4_pk_fp4": {"acc": "fp32", "notes": "Packed 4-bit float"}
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},
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"layout_cpp_map": {
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"_comment": "Maps layout character to CK Tile C++ type",
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"r": "ck_tile::tensor_layout::gemm::RowMajor",
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"c": "ck_tile::tensor_layout::gemm::ColumnMajor"
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},
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"pipeline_lds_limits": {
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"_comment": "LDS capacity limits in bytes for different pipeline types",
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"mem": 65536,
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"compv1": 65536,
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"compv2": 65536,
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"compv3": 65536,
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"compv4": 32768,
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"compv5": 65536,
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"compv6": 32768,
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"preshufflev1": 32768,
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"preshufflev2": 32768,
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"default": 65536
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},
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"unsupported_trait_combos": {
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"_comment": "Only 'mem' pipeline supports interwave scheduler. All compute pipelines only support intrawave.",
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"combinations": [
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["compv3", "cshuffle", "interwave"],
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["compv3", "default", "interwave"],
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["compv4", "cshuffle", "interwave"],
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["compv4", "default", "interwave"],
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["compv5", "cshuffle", "interwave"],
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["compv5", "default", "interwave"],
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["compv6", "cshuffle", "interwave"],
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["compv6", "default", "interwave"],
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["comp_async", "cshuffle", "interwave"],
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["comp_async", "default", "interwave"]
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]
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},
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"preshuffle_warp_tile_combos": {
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"_comment": "Preshuffle-specific warp tile combinations (subset of standard GEMM, no [4, 64, 16])",
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"gfx90a": {
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [64, 4, 16]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [64, 4, 16]],
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"fp8_fp8_fp32": [[32, 32, 16], [32, 32, 32]],
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"bf8_bf8_fp32": [[32, 32, 16], [32, 32, 32]]
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},
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"gfx942": {
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [64, 4, 16]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [64, 4, 16]],
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"fp8_fp8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 64]],
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"bf8_bf8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 64], [16, 16, 32]],
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"int8_int8_int32": [[16, 16, 32], [32, 32, 16]]
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},
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"gfx950": {
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [64, 4, 16], [32, 32, 32], [16, 16, 64]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [64, 4, 16], [32, 32, 32], [16, 16, 64]],
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"fp8_fp8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 64], [16, 16, 128], [32, 32, 64]],
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"bf8_bf8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 64], [16, 16, 32], [16, 16, 128], [32, 32, 64]]
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}
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},
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"preshuffle_pipelines": {
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"_comment": "Pipelines supported for preshuffle GEMM variant",
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"supported": ["preshufflev2"]
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}
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}
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