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* Adding CK Tile documentation * Updates based on feedback * Fix tile window API description * Fix remaining images * add documentation about flush_cache and rotating_buffer functionality in ck_tile * Supplement the documentation * light edit of the ck tile conceptual doc * Fixes for ruff check. * Fixes for ruff check 2. * Fixes for ruff check 3. --------- Co-authored-by: Vidyasagar <vanantha@amd.com> Co-authored-by: AviralGoelAMD <aviral.goel@amd.com> Co-authored-by: ThomasNing <thomas.ning@amd.com> Co-authored-by: Vidyasagar Ananthan <vidyasagar.ananthan@amd.com>
128 lines
3.4 KiB
ReStructuredText
128 lines
3.4 KiB
ReStructuredText
.. meta::
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:description: CK Tile Hardware-Specific Documentation
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:keywords: CDNA, GPU architecture, LDS, GEMM, CK, Composable Kernel
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.. _ck_tile_hardware:
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********************************************************************
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CK Tile Hardware Documentation
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********************************************************************
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This section provides in-depth coverage of hardware-specific concepts and optimizations for CK Tile on AMD GPUs.
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Overview
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========
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Understanding the underlying hardware architecture is crucial for achieving optimal performance with CK Tile. This documentation covers:
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- AMD CDNA architecture fundamentals
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- Memory hierarchy and optimization techniques
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- Practical examples of high-performance kernels
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Documentation Structure
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=======================
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.. toctree::
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:maxdepth: 2
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:caption: Hardware Topics
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gpu_basics
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lds_bank_conflicts
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gemm_optimization
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GPU Architecture Basics
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-----------------------
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:ref:`ck_tile_gpu_basics` provides an introduction to AMD CDNA architecture.
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LDS and Bank Conflicts
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----------------------
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:ref:`ck_tile_lds_bank_conflicts` explains Local Data Share (LDS) optimization.
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GEMM Optimization Case Study
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----------------------------
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:ref:`ck_tile_gemm_optimization` demonstrates a complete optimization journey.
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Key Hardware Considerations
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===========================
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Memory Hierarchy
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----------------
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1. **Global Memory**: High latency, high bandwidth
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- Optimize with coalesced access patterns
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- Use tile windows for automatic optimization
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2. **L2/Infinity Cache**: Intermediate storage
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- Benefits from spatial and temporal locality
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- CK Tile's tiling naturally improves cache hit rates
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3. **LDS**: Low latency, shared within CU
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- 64KB per CU, organized in 32 banks
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- CK Tile handles bank conflict avoidance
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4. **Registers**: Lowest latency, per-thread storage
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- 512 VGPRs available per wavefront
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- CK Tile's compile-time optimization minimizes usage
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Compute Resources
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-----------------
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1. **Wavefront Execution**: 64 threads in lockstep
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- CK Tile ensures coalesced memory access
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- Automatic warp-level synchronization
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2. **Matrix Units**: Specialized MFMA instructions
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- 16x16x16 operations in 16 cycles
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- CK Tile can leverage these automatically
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3. **Occupancy**: Balancing threads vs resources
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- Register pressure affects occupancy
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- CK Tile helps through efficient register use
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Performance Guidelines
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======================
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To achieve optimal performance with CK Tile:
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1. **Choose appropriate tile sizes**:
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- Match hardware capabilities (e.g., 256x256 for GEMM)
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- Consider LDS capacity and register pressure
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2. **Align problem dimensions**:
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- Match CU count when possible (304 for MI300)
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- Use padding for non-aligned sizes
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3. **Enable pipelining**:
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- Use double buffering for latency hiding
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- CK Tile supports async operations
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4. **Profile and verify**:
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- Use rocprof to check for bottlenecks
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- Verify bank conflict avoidance
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- Monitor occupancy and register usage
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Next Steps
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==========
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- Review :ref:`ck_tile_gpu_basics` for architecture fundamentals
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- Study :ref:`ck_tile_lds_bank_conflicts` for shared memory optimization
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- Explore :ref:`ck_tile_gemm_optimization` for a complete optimization example
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For practical implementation, refer back to the main :ref:`ck_tile_conceptual` documentation to see how these hardware concepts integrate with CK Tile's abstractions.
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